1unit ATmega8A; 2 3{$goto on} 4 5interface 6 7var 8 // ANALOG_COMPARATOR 9 SFIOR : byte absolute $00+$50; // Special Function IO Register 10 ACSR : byte absolute $00+$28; // Analog Comparator Control And Status Register 11 // SPI 12 SPDR : byte absolute $00+$2F; // SPI Data Register 13 SPSR : byte absolute $00+$2E; // SPI Status Register 14 SPCR : byte absolute $00+$2D; // SPI Control Register 15 // EXTERNAL_INTERRUPT 16 GICR : byte absolute $00+$5B; // General Interrupt Control Register 17 GIFR : byte absolute $00+$5A; // General Interrupt Flag Register 18 MCUCR : byte absolute $00+$55; // MCU Control Register 19 // TIMER_COUNTER_0 20 TIMSK : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register 21 TIFR : byte absolute $00+$58; // Timer/Counter Interrupt Flag register 22 TCCR0 : byte absolute $00+$53; // Timer/Counter0 Control Register 23 TCNT0 : byte absolute $00+$52; // Timer Counter 0 24 // TIMER_COUNTER_1 25 TCCR1A : byte absolute $00+$4F; // Timer/Counter1 Control Register A 26 TCCR1B : byte absolute $00+$4E; // Timer/Counter1 Control Register B 27 TCNT1 : word absolute $00+$4C; // Timer/Counter1 Bytes 28 TCNT1L : byte absolute $00+$4C; // Timer/Counter1 Bytes 29 TCNT1H : byte absolute $00+$4C+1; // Timer/Counter1 Bytes 30 OCR1A : word absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes 31 OCR1AL : byte absolute $00+$4A; // Timer/Counter1 Output Compare Register Bytes 32 OCR1AH : byte absolute $00+$4A+1; // Timer/Counter1 Output Compare Register Bytes 33 OCR1B : word absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes 34 OCR1BL : byte absolute $00+$48; // Timer/Counter1 Output Compare Register Bytes 35 OCR1BH : byte absolute $00+$48+1; // Timer/Counter1 Output Compare Register Bytes 36 ICR1 : word absolute $00+$46; // Timer/Counter1 Input Capture Register Bytes 37 ICR1L : byte absolute $00+$46; // Timer/Counter1 Input Capture Register Bytes 38 ICR1H : byte absolute $00+$46+1; // Timer/Counter1 Input Capture Register Bytes 39 // TIMER_COUNTER_2 40 TCCR2 : byte absolute $00+$45; // Timer/Counter2 Control Register 41 TCNT2 : byte absolute $00+$44; // Timer/Counter2 42 OCR2 : byte absolute $00+$43; // Timer/Counter2 Output Compare Register 43 ASSR : byte absolute $00+$42; // Asynchronous Status Register 44 // USART 45 UDR : byte absolute $00+$2C; // USART I/O Data Register 46 UCSRA : byte absolute $00+$2B; // USART Control and Status Register A 47 UCSRB : byte absolute $00+$2A; // USART Control and Status Register B 48 UCSRC : byte absolute $00+$40; // USART Control and Status Register C 49 UBRRH : byte absolute $00+$40; // USART Baud Rate Register Hight Byte 50 UBRRL : byte absolute $00+$29; // USART Baud Rate Register Low Byte 51 // TWI 52 TWBR : byte absolute $00+$20; // TWI Bit Rate register 53 TWCR : byte absolute $00+$56; // TWI Control Register 54 TWSR : byte absolute $00+$21; // TWI Status Register 55 TWDR : byte absolute $00+$23; // TWI Data register 56 TWAR : byte absolute $00+$22; // TWI (Slave) Address register 57 // WATCHDOG 58 WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register 59 // PORTB 60 PORTB : byte absolute $00+$38; // Port B Data Register 61 DDRB : byte absolute $00+$37; // Port B Data Direction Register 62 PINB : byte absolute $00+$36; // Port B Input Pins 63 // PORTC 64 PORTC : byte absolute $00+$35; // Port C Data Register 65 DDRC : byte absolute $00+$34; // Port C Data Direction Register 66 PINC : byte absolute $00+$33; // Port C Input Pins 67 // PORTD 68 PORTD : byte absolute $00+$32; // Port D Data Register 69 DDRD : byte absolute $00+$31; // Port D Data Direction Register 70 PIND : byte absolute $00+$30; // Port D Input Pins 71 // EEPROM 72 EEAR : word absolute $00+$3E; // EEPROM Address Register Bytes 73 EEARL : byte absolute $00+$3E; // EEPROM Address Register Bytes 74 EEARH : byte absolute $00+$3E+1; // EEPROM Address Register Bytes 75 EEDR : byte absolute $00+$3D; // EEPROM Data Register 76 EECR : byte absolute $00+$3C; // EEPROM Control Register 77 // CPU 78 SREG : byte absolute $00+$5F; // Status Register 79 SP : word absolute $00+$5D; // Stack Pointer 80 SPL : byte absolute $00+$5D; // Stack Pointer 81 SPH : byte absolute $00+$5D+1; // Stack Pointer 82 MCUCSR : byte absolute $00+$54; // MCU Control And Status Register 83 OSCCAL : byte absolute $00+$51; // Oscillator Calibration Value 84 SPMCR : byte absolute $00+$57; // Store Program Memory Control Register 85 // AD_CONVERTER 86 ADMUX : byte absolute $00+$27; // The ADC multiplexer Selection Register 87 ADCSRA : byte absolute $00+$26; // The ADC Control and Status register 88 ADC : word absolute $00+$24; // ADC Data Register Bytes 89 ADCL : byte absolute $00+$24; // ADC Data Register Bytes 90 ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes 91 92const 93 // SFIOR 94 ACME = 3; // Analog Comparator Multiplexer Enable 95 // ACSR 96 ACD = 7; // Analog Comparator Disable 97 ACBG = 6; // Analog Comparator Bandgap Select 98 ACO = 5; // Analog Compare Output 99 ACI = 4; // Analog Comparator Interrupt Flag 100 ACIE = 3; // Analog Comparator Interrupt Enable 101 ACIC = 2; // Analog Comparator Input Capture Enable 102 ACIS = 0; // Analog Comparator Interrupt Mode Select bits 103 // SPSR 104 SPIF = 7; // SPI Interrupt Flag 105 WCOL = 6; // Write Collision Flag 106 SPI2X = 0; // Double SPI Speed Bit 107 // SPCR 108 SPIE = 7; // SPI Interrupt Enable 109 SPE = 6; // SPI Enable 110 DORD = 5; // Data Order 111 MSTR = 4; // Master/Slave Select 112 CPOL = 3; // Clock polarity 113 CPHA = 2; // Clock Phase 114 SPR = 0; // SPI Clock Rate Selects 115 // GICR 116 INT = 6; // External Interrupt Request 1 Enable 117 IVSEL = 1; // Interrupt Vector Select 118 IVCE = 0; // Interrupt Vector Change Enable 119 // GIFR 120 INTF = 6; // External Interrupt Flags 121 // MCUCR 122 ISC1 = 2; // Interrupt Sense Control 1 Bits 123 ISC0 = 0; // Interrupt Sense Control 0 Bits 124 // TIMSK 125 TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable 126 // TIFR 127 TOV0 = 0; // Timer/Counter0 Overflow Flag 128 // TCCR0 129 CS02 = 2; // Clock Select0 bit 2 130 CS01 = 1; // Clock Select0 bit 1 131 CS00 = 0; // Clock Select0 bit 0 132 // TIMSK 133 TICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable 134 OCIE1A = 4; // Timer/Counter1 Output CompareA Match Interrupt Enable 135 OCIE1B = 3; // Timer/Counter1 Output CompareB Match Interrupt Enable 136 TOIE1 = 2; // Timer/Counter1 Overflow Interrupt Enable 137 // TIFR 138 ICF1 = 5; // Input Capture Flag 1 139 OCF1A = 4; // Output Compare Flag 1A 140 OCF1B = 3; // Output Compare Flag 1B 141 TOV1 = 2; // Timer/Counter1 Overflow Flag 142 // TCCR1A 143 COM1A = 6; // Compare Output Mode 1A, bits 144 COM1B = 4; // Compare Output Mode 1B, bits 145 FOC1A = 3; // Force Output Compare 1A 146 FOC1B = 2; // Force Output Compare 1B 147 WGM1 = 0; // Waveform Generation Mode 148 // TCCR1B 149 ICNC1 = 7; // Input Capture 1 Noise Canceler 150 ICES1 = 6; // Input Capture 1 Edge Select 151 CS1 = 0; // Prescaler source of Timer/Counter 1 152 // TIMSK 153 OCIE2 = 7; // Timer/Counter2 Output Compare Match Interrupt Enable 154 TOIE2 = 6; // Timer/Counter2 Overflow Interrupt Enable 155 // TIFR 156 OCF2 = 7; // Output Compare Flag 2 157 TOV2 = 6; // Timer/Counter2 Overflow Flag 158 // TCCR2 159 FOC2 = 7; // Force Output Compare 160 WGM20 = 6; // Waveform Genration Mode 161 COM2 = 4; // Compare Output Mode bits 162 WGM21 = 3; // Waveform Generation Mode 163 CS2 = 0; // Clock Select bits 164 // ASSR 165 AS2 = 3; // Asynchronous Timer/counter2 166 TCN2UB = 2; // Timer/Counter2 Update Busy 167 OCR2UB = 1; // Output Compare Register2 Update Busy 168 TCR2UB = 0; // Timer/counter Control Register2 Update Busy 169 // SFIOR 170 PSR2 = 1; // Prescaler Reset Timer/Counter2 171 // UCSRA 172 RXC = 7; // USART Receive Complete 173 TXC = 6; // USART Transmitt Complete 174 UDRE = 5; // USART Data Register Empty 175 FE = 4; // Framing Error 176 DOR = 3; // Data overRun 177 UPE = 2; // Parity Error 178 U2X = 1; // Double the USART transmission speed 179 MPCM = 0; // Multi-processor Communication Mode 180 // UCSRB 181 RXCIE = 7; // RX Complete Interrupt Enable 182 TXCIE = 6; // TX Complete Interrupt Enable 183 UDRIE = 5; // USART Data register Empty Interrupt Enable 184 RXEN = 4; // Receiver Enable 185 TXEN = 3; // Transmitter Enable 186 UCSZ2 = 2; // Character Size 187 RXB8 = 1; // Receive Data Bit 8 188 TXB8 = 0; // Transmit Data Bit 8 189 // UCSRC 190 URSEL = 7; // Register Select 191 UMSEL = 6; // USART Mode Select 192 UPM = 4; // Parity Mode Bits 193 USBS = 3; // Stop Bit Select 194 UCSZ = 1; // Character Size 195 UCPOL = 0; // Clock Polarity 196 // TWCR 197 TWINT = 7; // TWI Interrupt Flag 198 TWEA = 6; // TWI Enable Acknowledge Bit 199 TWSTA = 5; // TWI Start Condition Bit 200 TWSTO = 4; // TWI Stop Condition Bit 201 TWWC = 3; // TWI Write Collition Flag 202 TWEN = 2; // TWI Enable Bit 203 TWIE = 0; // TWI Interrupt Enable 204 // TWSR 205 TWS = 3; // TWI Status 206 TWPS = 0; // TWI Prescaler 207 // TWAR 208 TWA = 1; // TWI (Slave) Address register Bits 209 TWGCE = 0; // TWI General Call Recognition Enable Bit 210 // WDTCR 211 WDCE = 4; // Watchdog Change Enable 212 WDE = 3; // Watch Dog Enable 213 WDP = 0; // Watch Dog Timer Prescaler bits 214 // EECR 215 EERIE = 3; // EEPROM Ready Interrupt Enable 216 EEMWE = 2; // EEPROM Master Write Enable 217 EEWE = 1; // EEPROM Write Enable 218 EERE = 0; // EEPROM Read Enable 219 // SREG 220 I = 7; // Global Interrupt Enable 221 T = 6; // Bit Copy Storage 222 H = 5; // Half Carry Flag 223 S = 4; // Sign Bit 224 V = 3; // Two's Complement Overflow Flag 225 N = 2; // Negative Flag 226 Z = 1; // Zero Flag 227 C = 0; // Carry Flag 228 // MCUCR 229 SE = 7; // Sleep Enable 230 SM = 4; // Sleep Mode Select 231 // MCUCSR 232 WDRF = 3; // Watchdog Reset Flag 233 BORF = 2; // Brown-out Reset Flag 234 EXTRF = 1; // External Reset Flag 235 PORF = 0; // Power-on reset flag 236 // SPMCR 237 SPMIE = 7; // SPM Interrupt Enable 238 RWWSB = 6; // Read-While-Write Section Busy 239 RWWSRE = 4; // Read-While-Write Section Read Enable 240 BLBSET = 3; // Boot Lock Bit Set 241 PGWRT = 2; // Page Write 242 PGERS = 1; // Page Erase 243 SPMEN = 0; // Store Program Memory Enable 244 // SFIOR 245 ADHSM = 4; // ADC High Speed Mode 246 PUD = 2; // Pull-up Disable 247 PSR10 = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0 248 // ADMUX 249 REFS = 6; // Reference Selection Bits 250 ADLAR = 5; // Left Adjust Result 251 MUX = 0; // Analog Channel and Gain Selection Bits 252 // ADCSRA 253 ADEN = 7; // ADC Enable 254 ADSC = 6; // ADC Start Conversion 255 ADFR = 5; // ADC Free Running Select 256 ADIF = 4; // ADC Interrupt Flag 257 ADIE = 3; // ADC Interrupt Enable 258 ADPS = 0; // ADC Prescaler Select Bits 259 260implementation 261 262{$define RELBRANCHES} 263 264{$i avrcommon.inc} 265 266procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0 267procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 2 External Interrupt Request 1 268procedure TIMER2_COMP_ISR; external name 'TIMER2_COMP_ISR'; // Interrupt 3 Timer/Counter2 Compare Match 269procedure TIMER2_OVF_ISR; external name 'TIMER2_OVF_ISR'; // Interrupt 4 Timer/Counter2 Overflow 270procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 5 Timer/Counter1 Capture Event 271procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 6 Timer/Counter1 Compare Match A 272procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 7 Timer/Counter1 Compare Match B 273procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 8 Timer/Counter1 Overflow 274procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 9 Timer/Counter0 Overflow 275procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 10 Serial Transfer Complete 276procedure USART__RXC_ISR; external name 'USART__RXC_ISR'; // Interrupt 11 USART, Rx Complete 277procedure USART__UDRE_ISR; external name 'USART__UDRE_ISR'; // Interrupt 12 USART Data Register Empty 278procedure USART__TXC_ISR; external name 'USART__TXC_ISR'; // Interrupt 13 USART, Tx Complete 279procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 14 ADC Conversion Complete 280procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 15 EEPROM Ready 281procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 16 Analog Comparator 282procedure TWI_ISR; external name 'TWI_ISR'; // Interrupt 17 2-wire Serial Interface 283procedure SPM_RDY_ISR; external name 'SPM_RDY_ISR'; // Interrupt 18 Store Program Memory Ready 284 285procedure _FPC_start; assembler; nostackframe; 286label 287 _start; 288 asm 289 .init 290 .globl _start 291 292 rjmp _start 293 rjmp INT0_ISR 294 rjmp INT1_ISR 295 rjmp TIMER2_COMP_ISR 296 rjmp TIMER2_OVF_ISR 297 rjmp TIMER1_CAPT_ISR 298 rjmp TIMER1_COMPA_ISR 299 rjmp TIMER1_COMPB_ISR 300 rjmp TIMER1_OVF_ISR 301 rjmp TIMER0_OVF_ISR 302 rjmp SPI__STC_ISR 303 rjmp USART__RXC_ISR 304 rjmp USART__UDRE_ISR 305 rjmp USART__TXC_ISR 306 rjmp ADC_ISR 307 rjmp EE_RDY_ISR 308 rjmp ANA_COMP_ISR 309 rjmp TWI_ISR 310 rjmp SPM_RDY_ISR 311 312 {$i start.inc} 313 314 .weak INT0_ISR 315 .weak INT1_ISR 316 .weak TIMER2_COMP_ISR 317 .weak TIMER2_OVF_ISR 318 .weak TIMER1_CAPT_ISR 319 .weak TIMER1_COMPA_ISR 320 .weak TIMER1_COMPB_ISR 321 .weak TIMER1_OVF_ISR 322 .weak TIMER0_OVF_ISR 323 .weak SPI__STC_ISR 324 .weak USART__RXC_ISR 325 .weak USART__UDRE_ISR 326 .weak USART__TXC_ISR 327 .weak ADC_ISR 328 .weak EE_RDY_ISR 329 .weak ANA_COMP_ISR 330 .weak TWI_ISR 331 .weak SPM_RDY_ISR 332 333 .set INT0_ISR, Default_IRQ_handler 334 .set INT1_ISR, Default_IRQ_handler 335 .set TIMER2_COMP_ISR, Default_IRQ_handler 336 .set TIMER2_OVF_ISR, Default_IRQ_handler 337 .set TIMER1_CAPT_ISR, Default_IRQ_handler 338 .set TIMER1_COMPA_ISR, Default_IRQ_handler 339 .set TIMER1_COMPB_ISR, Default_IRQ_handler 340 .set TIMER1_OVF_ISR, Default_IRQ_handler 341 .set TIMER0_OVF_ISR, Default_IRQ_handler 342 .set SPI__STC_ISR, Default_IRQ_handler 343 .set USART__RXC_ISR, Default_IRQ_handler 344 .set USART__UDRE_ISR, Default_IRQ_handler 345 .set USART__TXC_ISR, Default_IRQ_handler 346 .set ADC_ISR, Default_IRQ_handler 347 .set EE_RDY_ISR, Default_IRQ_handler 348 .set ANA_COMP_ISR, Default_IRQ_handler 349 .set TWI_ISR, Default_IRQ_handler 350 .set SPM_RDY_ISR, Default_IRQ_handler 351 end; 352 353end. 354