1unit mk64f12; 2interface 3{$PACKRECORDS 2} 4{$GOTO ON} 5{$MODESWITCH ADVANCEDRECORDS} 6// ** ################################################################### 7// ** Processors: MK64FN1M0VDC12 8// ** MK64FN1M0VLL12 9// ** MK64FN1M0VLQ12 10// ** MK64FN1M0VMD12 11// ** 12// ** Compilers: Keil ARM C/C++ Compiler 13// ** Freescale C/C++ for Embedded ARM 14// ** GNU C Compiler 15// ** GNU C Compiler - CodeSourcery Sourcery G++ 16// ** IAR ANSI C/C++ Compiler for ARM 17// ** 18// ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 19// ** Version: rev. 2.8, 2015-02-19 20// ** Build: b150225 21// ** 22// ** Abstract: 23// ** CMSIS Peripheral Access Layer for MK64F12 24// ** 25// ** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. 26// ** All rights reserved. 27// ** 28// ** Redistribution and use in source and binary forms, with or without modification, 29// ** are permitted provided that the following conditions are met: 30// ** 31// ** o Redistributions of source code must retain the above copyright notice, this list 32// ** of conditions and the following disclaimer. 33// ** 34// ** o Redistributions in binary form must reproduce the above copyright notice, this 35// ** list of conditions and the following disclaimer in the documentation and/or 36// ** other materials provided with the distribution. 37// ** 38// ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its 39// ** contributors may be used to endorse or promote products derived from this 40// ** software without specific prior written permission. 41// ** 42// ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 43// ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 44// ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 45// ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR 46// ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 47// ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 48// ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 49// ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 50// ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 51// ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 52// ** 53// ** http: www.freescale.com 54// ** mail: support@freescale.com 55// ** 56// ** Revisions: 57// ** - rev. 1.0 (2013-08-12) 58// ** Initial version. 59// ** - rev. 2.0 (2013-10-29) 60// ** Register accessor macros added to the memory map. 61// ** Symbols for Processor Expert memory map compatibility added to the memory map. 62// ** Startup file for gcc has been updated according to CMSIS 3.2. 63// ** System initialization updated. 64// ** MCG - registers updated. 65// ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 66// ** - rev. 2.1 (2013-10-30) 67// ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 68// ** - rev. 2.2 (2013-12-09) 69// ** DMA - EARS register removed. 70// ** AIPS0, AIPS1 - MPRA register updated. 71// ** - rev. 2.3 (2014-01-24) 72// ** Update according to reference manual rev. 2 73// ** ENET, MCG, MCM, SIM, USB - registers updated 74// ** - rev. 2.4 (2014-02-10) 75// ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 76// ** Update of SystemInit() and SystemCoreClockUpdate() functions. 77// ** - rev. 2.5 (2014-02-10) 78// ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 79// ** Update of SystemInit() and SystemCoreClockUpdate() functions. 80// ** Module access macro module_BASES replaced by module_BASE_PTRS. 81// ** - rev. 2.6 (2014-08-28) 82// ** Update of system files - default clock configuration changed. 83// ** Update of startup files - possibility to override DefaultISR added. 84// ** - rev. 2.7 (2014-10-14) 85// ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. 86// ** - rev. 2.8 (2015-02-19) 87// ** Renamed interrupt vector LLW to LLWU. 88// ** 89// ** ################################################################### 90// ! 91// * @file MK64F12.h 92// * @version 2.8 93// * @date 2015-02-19 94// CMSIS Peripheral Access Layer for MK64F12 95// * 96// * CMSIS Peripheral Access Layer for MK64F12 97// ---------------------------------------------------------------------------- 98// -- MCU activation 99// ---------------------------------------------------------------------------- 100// Prevention from multiple including the same memory map 101// Check if another memory map has not been also included 102// * Memory map major version (memory maps with equal major version number are 103// * compatible) 104// * Memory map minor version 105// Macro to calculate address of an aliased word in the peripheral 106// * bitband area for a peripheral register and bit (bit band region 0x40000000 to 107// * 0x400FFFFF). 108// * @param Reg Register to access. 109// * @param Bit Bit number to access. 110// * @return Address of the aliased word in the peripheral bitband area. 111// Macro to access a single bit of a peripheral register (bit band region 112// * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 113// * be used for peripherals with 32bit access allowed. 114// * @param Reg Register to access. 115// * @param Bit Bit number to access. 116// * @return Value of the targeted bit in the bit band region. 117// Macro to access a single bit of a peripheral register (bit band region 118// * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 119// * be used for peripherals with 16bit access allowed. 120// * @param Reg Register to access. 121// * @param Bit Bit number to access. 122// * @return Value of the targeted bit in the bit band region. 123// Macro to access a single bit of a peripheral register (bit band region 124// * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can 125// * be used for peripherals with 8bit access allowed. 126// * @param Reg Register to access. 127// * @param Bit Bit number to access. 128// * @return Value of the targeted bit in the bit band region. 129// ---------------------------------------------------------------------------- 130// -- Interrupt vector numbers 131// ---------------------------------------------------------------------------- 132// ! 133// * Interrupt Number Definitions 134 135type 136 TIRQn_Enum = ( 137 NonMaskableInt_IRQn = -14, // *< Non Maskable Interrupt 138 HardFault_IRQn = -13, // *< Cortex-M4 SV Hard Fault Interrupt 139 MemoryManagement_IRQn = -12, // *< Cortex-M4 Memory Management Interrupt 140 BusFault_IRQn = -11, // *< Cortex-M4 Bus Fault Interrupt 141 UsageFault_IRQn = -10, // *< Cortex-M4 Usage Fault Interrupt 142 SVCall_IRQn = -5, // *< Cortex-M4 SV Call Interrupt 143 DebugMonitor_IRQn = -4, // *< Cortex-M4 Debug Monitor Interrupt 144 PendSV_IRQn = -2, // *< Cortex-M4 Pend SV Interrupt 145 SysTick_IRQn = -1, // *< Cortex-M4 System Tick Interrupt 146 DMA0_IRQn = 0, // *< DMA Channel 0 Transfer Complete 147 DMA1_IRQn = 1, // *< DMA Channel 1 Transfer Complete 148 DMA2_IRQn = 2, // *< DMA Channel 2 Transfer Complete 149 DMA3_IRQn = 3, // *< DMA Channel 3 Transfer Complete 150 DMA4_IRQn = 4, // *< DMA Channel 4 Transfer Complete 151 DMA5_IRQn = 5, // *< DMA Channel 5 Transfer Complete 152 DMA6_IRQn = 6, // *< DMA Channel 6 Transfer Complete 153 DMA7_IRQn = 7, // *< DMA Channel 7 Transfer Complete 154 DMA8_IRQn = 8, // *< DMA Channel 8 Transfer Complete 155 DMA9_IRQn = 9, // *< DMA Channel 9 Transfer Complete 156 DMA10_IRQn = 10, // *< DMA Channel 10 Transfer Complete 157 DMA11_IRQn = 11, // *< DMA Channel 11 Transfer Complete 158 DMA12_IRQn = 12, // *< DMA Channel 12 Transfer Complete 159 DMA13_IRQn = 13, // *< DMA Channel 13 Transfer Complete 160 DMA14_IRQn = 14, // *< DMA Channel 14 Transfer Complete 161 DMA15_IRQn = 15, // *< DMA Channel 15 Transfer Complete 162 DMA_Error_IRQn = 16, // *< DMA Error Interrupt 163 MCM_IRQn = 17, // *< Normal Interrupt 164 FTFE_IRQn = 18, // *< FTFE Command complete interrupt 165 Read_Collision_IRQn = 19, // *< Read Collision Interrupt 166 LVD_LVW_IRQn = 20, // *< Low Voltage Detect, Low Voltage Warning 167 LLWU_IRQn = 21, // *< Low Leakage Wakeup Unit 168 WDOG_EWM_IRQn = 22, // *< WDOG Interrupt 169 RNG_IRQn = 23, // *< RNG Interrupt 170 I2C0_IRQn = 24, // *< I2C0 interrupt 171 I2C1_IRQn = 25, // *< I2C1 interrupt 172 SPI0_IRQn = 26, // *< SPI0 Interrupt 173 SPI1_IRQn = 27, // *< SPI1 Interrupt 174 I2S0_Tx_IRQn = 28, // *< I2S0 transmit interrupt 175 I2S0_Rx_IRQn = 29, // *< I2S0 receive interrupt 176 UART0_LON_IRQn = 30, // *< UART0 LON interrupt 177 UART0_RX_TX_IRQn = 31, // *< UART0 Receive/Transmit interrupt 178 UART0_ERR_IRQn = 32, // *< UART0 Error interrupt 179 UART1_RX_TX_IRQn = 33, // *< UART1 Receive/Transmit interrupt 180 UART1_ERR_IRQn = 34, // *< UART1 Error interrupt 181 UART2_RX_TX_IRQn = 35, // *< UART2 Receive/Transmit interrupt 182 UART2_ERR_IRQn = 36, // *< UART2 Error interrupt 183 UART3_RX_TX_IRQn = 37, // *< UART3 Receive/Transmit interrupt 184 UART3_ERR_IRQn = 38, // *< UART3 Error interrupt 185 ADC0_IRQn = 39, // *< ADC0 interrupt 186 CMP0_IRQn = 40, // *< CMP0 interrupt 187 CMP1_IRQn = 41, // *< CMP1 interrupt 188 FTM0_IRQn = 42, // *< FTM0 fault, overflow and channels interrupt 189 FTM1_IRQn = 43, // *< FTM1 fault, overflow and channels interrupt 190 FTM2_IRQn = 44, // *< FTM2 fault, overflow and channels interrupt 191 CMT_IRQn = 45, // *< CMT interrupt 192 RTC_IRQn = 46, // *< RTC interrupt 193 RTC_Seconds_IRQn = 47, // *< RTC seconds interrupt 194 PIT0_IRQn = 48, // *< PIT timer channel 0 interrupt 195 PIT1_IRQn = 49, // *< PIT timer channel 1 interrupt 196 PIT2_IRQn = 50, // *< PIT timer channel 2 interrupt 197 PIT3_IRQn = 51, // *< PIT timer channel 3 interrupt 198 PDB0_IRQn = 52, // *< PDB0 Interrupt 199 USB0_IRQn = 53, // *< USB0 interrupt 200 USBDCD_IRQn = 54, // *< USBDCD Interrupt 201 RESERVED71_IRQn = 55, // *< Reserved interrupt 71 202 DAC0_IRQn = 56, // *< DAC0 interrupt 203 MCG_IRQn = 57, // *< MCG Interrupt 204 LPTMR0_IRQn = 58, // *< LPTimer interrupt 205 PORTA_IRQn = 59, // *< Port A interrupt 206 PORTB_IRQn = 60, // *< Port B interrupt 207 PORTC_IRQn = 61, // *< Port C interrupt 208 PORTD_IRQn = 62, // *< Port D interrupt 209 PORTE_IRQn = 63, // *< Port E interrupt 210 SWI_IRQn = 64, // *< Software interrupt 211 SPI2_IRQn = 65, // *< SPI2 Interrupt 212 UART4_RX_TX_IRQn = 66, // *< UART4 Receive/Transmit interrupt 213 UART4_ERR_IRQn = 67, // *< UART4 Error interrupt 214 UART5_RX_TX_IRQn = 68, // *< UART5 Receive/Transmit interrupt 215 UART5_ERR_IRQn = 69, // *< UART5 Error interrupt 216 CMP2_IRQn = 70, // *< CMP2 interrupt 217 FTM3_IRQn = 71, // *< FTM3 fault, overflow and channels interrupt 218 DAC1_IRQn = 72, // *< DAC1 interrupt 219 ADC1_IRQn = 73, // *< ADC1 interrupt 220 I2C2_IRQn = 74, // *< I2C2 interrupt 221 CAN0_ORed_Message_buffer_IRQn = 75, // *< CAN0 OR'd message buffers interrupt 222 CAN0_Bus_Off_IRQn = 76, // *< CAN0 bus off interrupt 223 CAN0_Error_IRQn = 77, // *< CAN0 error interrupt 224 CAN0_Tx_Warning_IRQn = 78, // *< CAN0 Tx warning interrupt 225 CAN0_Rx_Warning_IRQn = 79, // *< CAN0 Rx warning interrupt 226 CAN0_Wake_Up_IRQn = 80, // *< CAN0 wake up interrupt 227 SDHC_IRQn = 81, // *< SDHC interrupt 228 ENET_1588_Timer_IRQn = 82, // *< Ethernet MAC IEEE 1588 Timer Interrupt 229 ENET_Transmit_IRQn = 83, // *< Ethernet MAC Transmit Interrupt 230 ENET_Receive_IRQn = 84, // *< Ethernet MAC Receive Interrupt 231 ENET_Error_IRQn = 85 // *< Ethernet MAC Error and miscelaneous Interrupt 232 ); 233 234 TADC_Registers = record 235 SC1 : array[0..1] of longword; // *< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 236 CFG1 : longword; // *< ADC Configuration Register 1, offset: 0x8 237 CFG2 : longword; // *< ADC Configuration Register 2, offset: 0xC 238 R : array[0..1] of longword; // *< ADC Data Result Register, array offset: 0x10, array step: 0x4 239 CV1 : longword; // *< Compare Value Registers, offset: 0x18 240 CV2 : longword; // *< Compare Value Registers, offset: 0x1C 241 SC2 : longword; // *< Status and Control Register 2, offset: 0x20 242 SC3 : longword; // *< Status and Control Register 3, offset: 0x24 243 OFS : longword; // *< ADC Offset Correction Register, offset: 0x28 244 PG : longword; // *< ADC Plus-Side Gain Register, offset: 0x2C 245 MG : longword; // *< ADC Minus-Side Gain Register, offset: 0x30 246 CLPD : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x34 247 CLPS : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x38 248 CLP4 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x3C 249 CLP3 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x40 250 CLP2 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x44 251 CLP1 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x48 252 CLP0 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x4C 253 RESERVED_0 : array[0..3] of byte; 254 CLMD : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x54 255 CLMS : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x58 256 CLM4 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x5C 257 CLM3 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x60 258 CLM2 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x64 259 CLM1 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x68 260 CLM0 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x6C 261 end; 262 263const 264 ADC0_BASE = $4003B000; 265 266var 267 ADC0 : TADC_Registers absolute ADC0_BASE; 268 269const 270 ADC1_BASE = $400BB000; 271 272var 273 ADC1 : TADC_Registers absolute ADC1_BASE; 274 275type 276 TAIPS_Registers = record 277 MPRA : longword; // *< Master Privilege Register A, offset: 0x0 278 RESERVED_0 : array[0..27] of byte; 279 PACRA : longword; // *< Peripheral Access Control Register, offset: 0x20 280 PACRB : longword; // *< Peripheral Access Control Register, offset: 0x24 281 PACRC : longword; // *< Peripheral Access Control Register, offset: 0x28 282 PACRD : longword; // *< Peripheral Access Control Register, offset: 0x2C 283 RESERVED_1 : array[0..15] of byte; 284 PACRE : longword; // *< Peripheral Access Control Register, offset: 0x40 285 PACRF : longword; // *< Peripheral Access Control Register, offset: 0x44 286 PACRG : longword; // *< Peripheral Access Control Register, offset: 0x48 287 PACRH : longword; // *< Peripheral Access Control Register, offset: 0x4C 288 PACRI : longword; // *< Peripheral Access Control Register, offset: 0x50 289 PACRJ : longword; // *< Peripheral Access Control Register, offset: 0x54 290 PACRK : longword; // *< Peripheral Access Control Register, offset: 0x58 291 PACRL : longword; // *< Peripheral Access Control Register, offset: 0x5C 292 PACRM : longword; // *< Peripheral Access Control Register, offset: 0x60 293 PACRN : longword; // *< Peripheral Access Control Register, offset: 0x64 294 PACRO : longword; // *< Peripheral Access Control Register, offset: 0x68 295 PACRP : longword; // *< Peripheral Access Control Register, offset: 0x6C 296 RESERVED_2 : array[0..15] of byte; 297 PACRU : longword; // *< Peripheral Access Control Register, offset: 0x80 298 end; 299 300const 301 AIPS0_BASE = $40000000; 302 303var 304 AIPS0 : TAIPS_Registers absolute AIPS0_BASE; 305 306const 307 AIPS1_BASE = $40080000; 308 309var 310 AIPS1 : TAIPS_Registers absolute AIPS1_BASE; 311 312type 313 TAXBS_SLAVE = record 314 PRS : longword; // *< Priority Registers Slave, array offset: 0x0, array step: 0x100 315 RESERVED_0 : array[0..11] of byte; 316 CRS : longword; // *< Control Register, array offset: 0x10, array step: 0x100 317 RESERVED_1 : array[0..235] of byte; 318 end; 319 320 TAXBS_Registers = record 321 SLAVE : array[0..4] of TAXBS_SLAVE; 322 RESERVED_0 : array[0..767] of byte; 323 MGPCR0 : longword; // *< Master General Purpose Control Register, offset: 0x800 324 RESERVED_1 : array[0..251] of byte; 325 MGPCR1 : longword; // *< Master General Purpose Control Register, offset: 0x900 326 RESERVED_2 : array[0..251] of byte; 327 MGPCR2 : longword; // *< Master General Purpose Control Register, offset: 0xA00 328 RESERVED_3 : array[0..251] of byte; 329 MGPCR3 : longword; // *< Master General Purpose Control Register, offset: 0xB00 330 RESERVED_4 : array[0..251] of byte; 331 MGPCR4 : longword; // *< Master General Purpose Control Register, offset: 0xC00 332 RESERVED_5 : array[0..251] of byte; 333 MGPCR5 : longword; // *< Master General Purpose Control Register, offset: 0xD00 334 end; 335 336const 337 AXBS_BASE = $40004000; 338 339var 340 AXBS : TAXBS_Registers absolute AXBS_BASE; 341 342type 343 TCAN_MB = record 344 CS : longword; // *< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 345 ID : longword; // *< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 346 WORD0 : longword; // *< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 347 WORD1 : longword; // *< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 348 end; 349 350 TCAN_Registers = record 351 MCR : longword; // *< Module Configuration Register, offset: 0x0 352 CTRL1 : longword; // *< Control 1 register, offset: 0x4 353 TIMER : longword; // *< Free Running Timer, offset: 0x8 354 RESERVED_0 : array[0..3] of byte; 355 RXMGMASK : longword; // *< Rx Mailboxes Global Mask Register, offset: 0x10 356 RX14MASK : longword; // *< Rx 14 Mask register, offset: 0x14 357 RX15MASK : longword; // *< Rx 15 Mask register, offset: 0x18 358 ECR : longword; // *< Error Counter, offset: 0x1C 359 ESR1 : longword; // *< Error and Status 1 register, offset: 0x20 360 RESERVED_1 : array[0..3] of byte; 361 IMASK1 : longword; // *< Interrupt Masks 1 register, offset: 0x28 362 RESERVED_2 : array[0..3] of byte; 363 IFLAG1 : longword; // *< Interrupt Flags 1 register, offset: 0x30 364 CTRL2 : longword; // *< Control 2 register, offset: 0x34 365 ESR2 : longword; // *< Error and Status 2 register, offset: 0x38 366 RESERVED_3 : array[0..7] of byte; 367 CRCR : longword; // *< CRC Register, offset: 0x44 368 RXFGMASK : longword; // *< Rx FIFO Global Mask register, offset: 0x48 369 RXFIR : longword; // *< Rx FIFO Information Register, offset: 0x4C 370 RESERVED_4 : array[0..47] of byte; 371 MB : array[0..15] of TCAN_MB; 372 RESERVED_5 : array[0..1791] of byte; 373 RXIMR : array[0..15] of longword; // *< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 374 end; 375 376const 377 CAN0_BASE = $40024000; 378 379var 380 CAN0 : TCAN_Registers absolute CAN0_BASE; 381 382type 383 TCAU_Registers = record 384 DIRECT : array[0..15] of longword; // *< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 385 RESERVED_0 : array[0..2047] of byte; 386 LDR_CASR : longword; // *< Status register - Load Register command, offset: 0x840 387 LDR_CAA : longword; // *< Accumulator register - Load Register command, offset: 0x844 388 LDR_CA : array[0..8] of longword; // *< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 389 RESERVED_1 : array[0..19] of byte; 390 STR_CASR : longword; // *< Status register - Store Register command, offset: 0x880 391 STR_CAA : longword; // *< Accumulator register - Store Register command, offset: 0x884 392 STR_CA : array[0..8] of longword; // *< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 393 RESERVED_2 : array[0..19] of byte; 394 ADR_CASR : longword; // *< Status register - Add Register command, offset: 0x8C0 395 ADR_CAA : longword; // *< Accumulator register - Add to register command, offset: 0x8C4 396 ADR_CA : array[0..8] of longword; // *< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 397 RESERVED_3 : array[0..19] of byte; 398 RADR_CASR : longword; // *< Status register - Reverse and Add to Register command, offset: 0x900 399 RADR_CAA : longword; // *< Accumulator register - Reverse and Add to Register command, offset: 0x904 400 RADR_CA : array[0..8] of longword; // *< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 401 RESERVED_4 : array[0..83] of byte; 402 XOR_CASR : longword; // *< Status register - Exclusive Or command, offset: 0x980 403 XOR_CAA : longword; // *< Accumulator register - Exclusive Or command, offset: 0x984 404 XOR_CA : array[0..8] of longword; // *< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 405 RESERVED_5 : array[0..19] of byte; 406 ROTL_CASR : longword; // *< Status register - Rotate Left command, offset: 0x9C0 407 ROTL_CAA : longword; // *< Accumulator register - Rotate Left command, offset: 0x9C4 408 ROTL_CA : array[0..8] of longword; // *< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 409 RESERVED_6 : array[0..275] of byte; 410 AESC_CASR : longword; // *< Status register - AES Column Operation command, offset: 0xB00 411 AESC_CAA : longword; // *< Accumulator register - AES Column Operation command, offset: 0xB04 412 AESC_CA : array[0..8] of longword; // *< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 413 RESERVED_7 : array[0..19] of byte; 414 AESIC_CASR : longword; // *< Status register - AES Inverse Column Operation command, offset: 0xB40 415 AESIC_CAA : longword; // *< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 416 AESIC_CA : array[0..8] of longword; // *< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 417 end; 418 419const 420 CAU_BASE = $E0081000; 421 422var 423 CAU : TCAU_Registers absolute CAU_BASE; 424 425type 426 TCMP_Registers = record 427 CR0 : byte; // *< CMP Control Register 0, offset: 0x0 428 CR1 : byte; // *< CMP Control Register 1, offset: 0x1 429 FPR : byte; // *< CMP Filter Period Register, offset: 0x2 430 SCR : byte; // *< CMP Status and Control Register, offset: 0x3 431 DACCR : byte; // *< DAC Control Register, offset: 0x4 432 MUXCR : byte; // *< MUX Control Register, offset: 0x5 433 end; 434 435const 436 CMP0_BASE = $40073000; 437 438var 439 CMP0 : TCMP_Registers absolute CMP0_BASE; 440 441const 442 CMP1_BASE = $40073008; 443 444var 445 CMP1 : TCMP_Registers absolute CMP1_BASE; 446 447const 448 CMP2_BASE = $40073010; 449 450var 451 CMP2 : TCMP_Registers absolute CMP2_BASE; 452 453type 454 TCMT_Registers = record 455 CGH1 : byte; // *< CMT Carrier Generator High Data Register 1, offset: 0x0 456 CGL1 : byte; // *< CMT Carrier Generator Low Data Register 1, offset: 0x1 457 CGH2 : byte; // *< CMT Carrier Generator High Data Register 2, offset: 0x2 458 CGL2 : byte; // *< CMT Carrier Generator Low Data Register 2, offset: 0x3 459 OC : byte; // *< CMT Output Control Register, offset: 0x4 460 MSC : byte; // *< CMT Modulator Status and Control Register, offset: 0x5 461 CMD1 : byte; // *< CMT Modulator Data Register Mark High, offset: 0x6 462 CMD2 : byte; // *< CMT Modulator Data Register Mark Low, offset: 0x7 463 CMD3 : byte; // *< CMT Modulator Data Register Space High, offset: 0x8 464 CMD4 : byte; // *< CMT Modulator Data Register Space Low, offset: 0x9 465 PPS : byte; // *< CMT Primary Prescaler Register, offset: 0xA 466 DMA : byte; // *< CMT Direct Memory Access Register, offset: 0xB 467 end; 468 469const 470 CMT_BASE = $40062000; 471 472var 473 CMT : TCMT_Registers absolute CMT_BASE; 474 475type 476 TCRC_Registers = record 477 DATA : longword; // *< CRC Data register, offset: 0x0 478 GPOLY : longword; // *< CRC Polynomial register, offset: 0x4 479 CTRL : longword; // *< CRC Control register, offset: 0x8 480 end; 481 482const 483 CRC_BASE = $40032000; 484 485var 486 CRC0 : TCRC_Registers absolute CRC_BASE; 487 488type 489 TDAC_DAT = record 490 DATL : byte; // *< DAC Data Low Register, array offset: 0x0, array step: 0x2 491 DATH : byte; // *< DAC Data High Register, array offset: 0x1, array step: 0x2 492 end; 493 494 TDAC_Registers = record 495 DAT : array[0..15] of TDAC_DAT; 496 SR : byte; // *< DAC Status Register, offset: 0x20 497 C0 : byte; // *< DAC Control Register, offset: 0x21 498 C1 : byte; // *< DAC Control Register 1, offset: 0x22 499 C2 : byte; // *< DAC Control Register 2, offset: 0x23 500 end; 501 502const 503 DAC0_BASE = $400CC000; 504 505var 506 DAC0 : TDAC_Registers absolute DAC0_BASE; 507 508const 509 DAC1_BASE = $400CD000; 510 511var 512 DAC1 : TDAC_Registers absolute DAC1_BASE; 513 514type 515 TDMA_TCD = record 516 SADDR : longword; // *< TCD Source Address, array offset: 0x1000, array step: 0x20 517 SOFF : word; // *< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 518 ATTR : word; // *< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 519 NBYTES_MLNO : longword; // *< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 520 SLAST : longword; // *< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 521 DADDR : longword; // *< TCD Destination Address, array offset: 0x1010, array step: 0x20 522 DOFF : word; // *< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 523 CITER_ELINKNO : word; // *< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 524 DLAST_SGA : longword; // *< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 525 CSR : word; // *< TCD Control and Status, array offset: 0x101C, array step: 0x20 526 BITER_ELINKNO : word; // *< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 527 end; 528 529 TDMA_Registers = record 530 CR : longword; // *< Control Register, offset: 0x0 531 ES : longword; // *< Error Status Register, offset: 0x4 532 RESERVED_0 : array[0..3] of byte; 533 ERQ : longword; // *< Enable Request Register, offset: 0xC 534 RESERVED_1 : array[0..3] of byte; 535 EEI : longword; // *< Enable Error Interrupt Register, offset: 0x14 536 CEEI : byte; // *< Clear Enable Error Interrupt Register, offset: 0x18 537 SEEI : byte; // *< Set Enable Error Interrupt Register, offset: 0x19 538 CERQ : byte; // *< Clear Enable Request Register, offset: 0x1A 539 SERQ : byte; // *< Set Enable Request Register, offset: 0x1B 540 CDNE : byte; // *< Clear DONE Status Bit Register, offset: 0x1C 541 SSRT : byte; // *< Set START Bit Register, offset: 0x1D 542 CERR : byte; // *< Clear Error Register, offset: 0x1E 543 CINT : byte; // *< Clear Interrupt Request Register, offset: 0x1F 544 RESERVED_2 : array[0..3] of byte; 545 INT : longword; // *< Interrupt Request Register, offset: 0x24 546 RESERVED_3 : array[0..3] of byte; 547 ERR : longword; // *< Error Register, offset: 0x2C 548 RESERVED_4 : array[0..3] of byte; 549 HRS : longword; // *< Hardware Request Status Register, offset: 0x34 550 RESERVED_5 : array[0..199] of byte; 551 DCHPRI3 : byte; // *< Channel n Priority Register, offset: 0x100 552 DCHPRI2 : byte; // *< Channel n Priority Register, offset: 0x101 553 DCHPRI1 : byte; // *< Channel n Priority Register, offset: 0x102 554 DCHPRI0 : byte; // *< Channel n Priority Register, offset: 0x103 555 DCHPRI7 : byte; // *< Channel n Priority Register, offset: 0x104 556 DCHPRI6 : byte; // *< Channel n Priority Register, offset: 0x105 557 DCHPRI5 : byte; // *< Channel n Priority Register, offset: 0x106 558 DCHPRI4 : byte; // *< Channel n Priority Register, offset: 0x107 559 DCHPRI11 : byte; // *< Channel n Priority Register, offset: 0x108 560 DCHPRI10 : byte; // *< Channel n Priority Register, offset: 0x109 561 DCHPRI9 : byte; // *< Channel n Priority Register, offset: 0x10A 562 DCHPRI8 : byte; // *< Channel n Priority Register, offset: 0x10B 563 DCHPRI15 : byte; // *< Channel n Priority Register, offset: 0x10C 564 DCHPRI14 : byte; // *< Channel n Priority Register, offset: 0x10D 565 DCHPRI13 : byte; // *< Channel n Priority Register, offset: 0x10E 566 DCHPRI12 : byte; // *< Channel n Priority Register, offset: 0x10F 567 RESERVED_6 : array[0..3823] of byte; 568 TCD : array[0..15] of TDMA_TCD; 569 end; 570 571const 572 DMA_BASE = $40008000; 573 574var 575 DMA0 : TDMA_Registers absolute DMA_BASE; 576 577type 578 TDMAMUX_Registers = record 579 CHCFG : array[0..15] of byte; // *< Channel Configuration register, array offset: 0x0, array step: 0x1 580 end; 581 582const 583 DMAMUX_BASE = $40021000; 584 585var 586 DMAMUX : TDMAMUX_Registers absolute DMAMUX_BASE; 587 588type 589 TENET_CHANNEL= record 590 TCSR : longword; // *< Timer Control Status Register, array offset: 0x608, array step: 0x8 591 TCCR : longword; // *< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 592 end; 593 594 TENET_Registers = record 595 RESERVED_0 : array[0..3] of byte; 596 EIR : longword; // *< Interrupt Event Register, offset: 0x4 597 EIMR : longword; // *< Interrupt Mask Register, offset: 0x8 598 RESERVED_1 : array[0..3] of byte; 599 RDAR : longword; // *< Receive Descriptor Active Register, offset: 0x10 600 TDAR : longword; // *< Transmit Descriptor Active Register, offset: 0x14 601 RESERVED_2 : array[0..11] of byte; 602 ECR : longword; // *< Ethernet Control Register, offset: 0x24 603 RESERVED_3 : array[0..23] of byte; 604 MMFR : longword; // *< MII Management Frame Register, offset: 0x40 605 MSCR : longword; // *< MII Speed Control Register, offset: 0x44 606 RESERVED_4 : array[0..27] of byte; 607 MIBC : longword; // *< MIB Control Register, offset: 0x64 608 RESERVED_5 : array[0..27] of byte; 609 RCR : longword; // *< Receive Control Register, offset: 0x84 610 RESERVED_6 : array[0..59] of byte; 611 TCR : longword; // *< Transmit Control Register, offset: 0xC4 612 RESERVED_7 : array[0..27] of byte; 613 PALR : longword; // *< Physical Address Lower Register, offset: 0xE4 614 PAUR : longword; // *< Physical Address Upper Register, offset: 0xE8 615 OPD : longword; // *< Opcode/Pause Duration Register, offset: 0xEC 616 RESERVED_8 : array[0..39] of byte; 617 IAUR : longword; // *< Descriptor Individual Upper Address Register, offset: 0x118 618 IALR : longword; // *< Descriptor Individual Lower Address Register, offset: 0x11C 619 GAUR : longword; // *< Descriptor Group Upper Address Register, offset: 0x120 620 GALR : longword; // *< Descriptor Group Lower Address Register, offset: 0x124 621 RESERVED_9 : array[0..27] of byte; 622 TFWR : longword; // *< Transmit FIFO Watermark Register, offset: 0x144 623 RESERVED_10 : array[0..55] of byte; 624 RDSR : longword; // *< Receive Descriptor Ring Start Register, offset: 0x180 625 TDSR : longword; // *< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 626 MRBR : longword; // *< Maximum Receive Buffer Size Register, offset: 0x188 627 RESERVED_11 : array[0..3] of byte; 628 RSFL : longword; // *< Receive FIFO Section Full Threshold, offset: 0x190 629 RSEM : longword; // *< Receive FIFO Section Empty Threshold, offset: 0x194 630 RAEM : longword; // *< Receive FIFO Almost Empty Threshold, offset: 0x198 631 RAFL : longword; // *< Receive FIFO Almost Full Threshold, offset: 0x19C 632 TSEM : longword; // *< Transmit FIFO Section Empty Threshold, offset: 0x1A0 633 TAEM : longword; // *< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 634 TAFL : longword; // *< Transmit FIFO Almost Full Threshold, offset: 0x1A8 635 TIPG : longword; // *< Transmit Inter-Packet Gap, offset: 0x1AC 636 FTRL : longword; // *< Frame Truncation Length, offset: 0x1B0 637 RESERVED_12 : array[0..11] of byte; 638 TACC : longword; // *< Transmit Accelerator Function Configuration, offset: 0x1C0 639 RACC : longword; // *< Receive Accelerator Function Configuration, offset: 0x1C4 640 RESERVED_13 : array[0..59] of byte; 641 RMON_T_PACKETS : longword; // *< Tx Packet Count Statistic Register, offset: 0x204 642 RMON_T_BC_PKT : longword; // *< Tx Broadcast Packets Statistic Register, offset: 0x208 643 RMON_T_MC_PKT : longword; // *< Tx Multicast Packets Statistic Register, offset: 0x20C 644 RMON_T_CRC_ALIGN : longword; // *< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 645 RMON_T_UNDERSIZE : longword; // *< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 646 RMON_T_OVERSIZE : longword; // *< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 647 RMON_T_FRAG : longword; // *< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C 648 RMON_T_JAB : longword; // *< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 649 RMON_T_COL : longword; // *< Tx Collision Count Statistic Register, offset: 0x224 650 RMON_T_P64 : longword; // *< Tx 64-Byte Packets Statistic Register, offset: 0x228 651 RMON_T_P65TO127 : longword; // *< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C 652 RMON_T_P128TO255 : longword; // *< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 653 RMON_T_P256TO511 : longword; // *< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 654 RMON_T_P512TO1023 : longword; // *< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 655 RMON_T_P1024TO2047 : longword; // *< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C 656 RMON_T_P_GTE2048 : longword; // *< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 657 RMON_T_OCTETS : longword; // *< Tx Octets Statistic Register, offset: 0x244 658 RESERVED_14 : array[0..3] of byte; 659 IEEE_T_FRAME_OK : longword; // *< Frames Transmitted OK Statistic Register, offset: 0x24C 660 IEEE_T_1COL : longword; // *< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 661 IEEE_T_MCOL : longword; // *< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 662 IEEE_T_DEF : longword; // *< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 663 IEEE_T_LCOL : longword; // *< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C 664 IEEE_T_EXCOL : longword; // *< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 665 IEEE_T_MACERR : longword; // *< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 666 IEEE_T_CSERR : longword; // *< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 667 RESERVED_15 : array[0..3] of byte; 668 IEEE_T_FDXFC : longword; // *< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 669 IEEE_T_OCTETS_OK : longword; // *< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 670 RESERVED_16 : array[0..11] of byte; 671 RMON_R_PACKETS : longword; // *< Rx Packet Count Statistic Register, offset: 0x284 672 RMON_R_BC_PKT : longword; // *< Rx Broadcast Packets Statistic Register, offset: 0x288 673 RMON_R_MC_PKT : longword; // *< Rx Multicast Packets Statistic Register, offset: 0x28C 674 RMON_R_CRC_ALIGN : longword; // *< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 675 RMON_R_UNDERSIZE : longword; // *< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 676 RMON_R_OVERSIZE : longword; // *< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 677 RMON_R_FRAG : longword; // *< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C 678 RMON_R_JAB : longword; // *< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 679 RESERVED_17 : array[0..3] of byte; 680 RMON_R_P64 : longword; // *< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 681 RMON_R_P65TO127 : longword; // *< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC 682 RMON_R_P128TO255 : longword; // *< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 683 RMON_R_P256TO511 : longword; // *< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 684 RMON_R_P512TO1023 : longword; // *< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 685 RMON_R_P1024TO2047 : longword; // *< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC 686 RMON_R_P_GTE2048 : longword; // *< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 687 RMON_R_OCTETS : longword; // *< Rx Octets Statistic Register, offset: 0x2C4 688 IEEE_R_DROP : longword; // *< Frames not Counted Correctly Statistic Register, offset: 0x2C8 689 IEEE_R_FRAME_OK : longword; // *< Frames Received OK Statistic Register, offset: 0x2CC 690 IEEE_R_CRC : longword; // *< Frames Received with CRC Error Statistic Register, offset: 0x2D0 691 IEEE_R_ALIGN : longword; // *< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 692 IEEE_R_MACERR : longword; // *< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 693 IEEE_R_FDXFC : longword; // *< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC 694 IEEE_R_OCTETS_OK : longword; // *< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 695 RESERVED_18 : array[0..283] of byte; 696 ATCR : longword; // *< Adjustable Timer Control Register, offset: 0x400 697 ATVR : longword; // *< Timer Value Register, offset: 0x404 698 ATOFF : longword; // *< Timer Offset Register, offset: 0x408 699 ATPER : longword; // *< Timer Period Register, offset: 0x40C 700 ATCOR : longword; // *< Timer Correction Register, offset: 0x410 701 ATINC : longword; // *< Time-Stamping Clock Period Register, offset: 0x414 702 ATSTMP : longword; // *< Timestamp of Last Transmitted Frame, offset: 0x418 703 RESERVED_19 : array[0..487] of byte; 704 TGSR : longword; // *< Timer Global Status Register, offset: 0x604 705 CHANNEL : array[0..3] of TENET_CHANNEL; 706 end; 707 708const 709 ENET_BASE = $400C0000; 710 711var 712 ENET : TENET_Registers absolute ENET_BASE; 713 714type 715 TEWM_Registers = record 716 CTRL : byte; // *< Control Register, offset: 0x0 717 SERV : byte; // *< Service Register, offset: 0x1 718 CMPL : byte; // *< Compare Low Register, offset: 0x2 719 CMPH : byte; // *< Compare High Register, offset: 0x3 720 end; 721 722const 723 EWM_BASE = $40061000; 724 725var 726 EWM : TEWM_Registers absolute EWM_BASE; 727 728type 729 TFB_CS = record 730 CSAR : longword; // *< Chip Select Address Register, array offset: 0x0, array step: 0xC 731 CSMR : longword; // *< Chip Select Mask Register, array offset: 0x4, array step: 0xC 732 CSCR : longword; // *< Chip Select Control Register, array offset: 0x8, array step: 0xC 733 end; 734 735 TFB_Registers = record 736 CS : array[0..5] of TFB_CS; 737 RESERVED_0 : array[0..23] of byte; 738 CSPMCR : longword; // *< Chip Select port Multiplexing Control Register, offset: 0x60 739 end; 740 741const 742 FB_BASE = $4000C000; 743 744var 745 FB : TFB_Registers absolute FB_BASE; 746 747type 748 TFMC_SET = record 749 DATA_U : longword; // *< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 750 DATA_L : longword; // *< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 751 end; 752 753 TFMC_Registers = record 754 PFAPR : longword; // *< Flash Access Protection Register, offset: 0x0 755 PFB0CR : longword; // *< Flash Bank 0 Control Register, offset: 0x4 756 PFB1CR : longword; // *< Flash Bank 1 Control Register, offset: 0x8 757 RESERVED_0 : array[0..243] of byte; 758 TAGVDW0S : array[0..3] of longword; // *< Cache Tag Storage, array offset: 0x100, array step: 0x4 759 TAGVDW1S : array[0..3] of longword; // *< Cache Tag Storage, array offset: 0x110, array step: 0x4 760 TAGVDW2S : array[0..3] of longword; // *< Cache Tag Storage, array offset: 0x120, array step: 0x4 761 TAGVDW3S : array[0..3] of longword; // *< Cache Tag Storage, array offset: 0x130, array step: 0x4 762 RESERVED_1 : array[0..191] of byte; 763 &SET : array[0..3] of TFMC_SET; 764 end; 765 766const 767 FMC_BASE = $4001F000; 768 769var 770 FMC : TFMC_Registers absolute FMC_BASE; 771 772type 773 TFTFE_Registers = record 774 FSTAT : byte; // *< Flash Status Register, offset: 0x0 775 FCNFG : byte; // *< Flash Configuration Register, offset: 0x1 776 FSEC : byte; // *< Flash Security Register, offset: 0x2 777 FOPT : byte; // *< Flash Option Register, offset: 0x3 778 FCCOB3 : byte; // *< Flash Common Command Object Registers, offset: 0x4 779 FCCOB2 : byte; // *< Flash Common Command Object Registers, offset: 0x5 780 FCCOB1 : byte; // *< Flash Common Command Object Registers, offset: 0x6 781 FCCOB0 : byte; // *< Flash Common Command Object Registers, offset: 0x7 782 FCCOB7 : byte; // *< Flash Common Command Object Registers, offset: 0x8 783 FCCOB6 : byte; // *< Flash Common Command Object Registers, offset: 0x9 784 FCCOB5 : byte; // *< Flash Common Command Object Registers, offset: 0xA 785 FCCOB4 : byte; // *< Flash Common Command Object Registers, offset: 0xB 786 FCCOBB : byte; // *< Flash Common Command Object Registers, offset: 0xC 787 FCCOBA : byte; // *< Flash Common Command Object Registers, offset: 0xD 788 FCCOB9 : byte; // *< Flash Common Command Object Registers, offset: 0xE 789 FCCOB8 : byte; // *< Flash Common Command Object Registers, offset: 0xF 790 FPROT3 : byte; // *< Program Flash Protection Registers, offset: 0x10 791 FPROT2 : byte; // *< Program Flash Protection Registers, offset: 0x11 792 FPROT1 : byte; // *< Program Flash Protection Registers, offset: 0x12 793 FPROT0 : byte; // *< Program Flash Protection Registers, offset: 0x13 794 RESERVED_0 : array[0..1] of byte; 795 FEPROT : byte; // *< EEPROM Protection Register, offset: 0x16 796 FDPROT : byte; // *< Data Flash Protection Register, offset: 0x17 797 end; 798 799const 800 FTFE_BASE = $40020000; 801 802var 803 FTFE : TFTFE_Registers absolute FTFE_BASE; 804 805type 806 TFTM_CONTROLS= record 807 CnSC : longword; // *< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 808 CnV : longword; // *< Channel (n) Value, array offset: 0x10, array step: 0x8 809 end; 810 811 TFTM_Registers = record 812 SC : longword; // *< Status And Control, offset: 0x0 813 CNT : longword; // *< Counter, offset: 0x4 814 &MOD : longword; // *< Modulo, offset: 0x8 815 CONTROLS : array[0..7] of TFTM_CONTROLS; 816 CNTIN : longword; // *< Counter Initial Value, offset: 0x4C 817 STATUS : longword; // *< Capture And Compare Status, offset: 0x50 818 MODE : longword; // *< Features Mode Selection, offset: 0x54 819 SYNC : longword; // *< Synchronization, offset: 0x58 820 OUTINIT : longword; // *< Initial State For Channels Output, offset: 0x5C 821 OUTMASK : longword; // *< Output Mask, offset: 0x60 822 COMBINE : longword; // *< Function For Linked Channels, offset: 0x64 823 DEADTIME : longword; // *< Deadtime Insertion Control, offset: 0x68 824 EXTTRIG : longword; // *< FTM External Trigger, offset: 0x6C 825 POL : longword; // *< Channels Polarity, offset: 0x70 826 FMS : longword; // *< Fault Mode Status, offset: 0x74 827 FILTER : longword; // *< Input Capture Filter Control, offset: 0x78 828 FLTCTRL : longword; // *< Fault Control, offset: 0x7C 829 QDCTRL : longword; // *< Quadrature Decoder Control And Status, offset: 0x80 830 CONF : longword; // *< Configuration, offset: 0x84 831 FLTPOL : longword; // *< FTM Fault Input Polarity, offset: 0x88 832 SYNCONF : longword; // *< Synchronization Configuration, offset: 0x8C 833 INVCTRL : longword; // *< FTM Inverting Control, offset: 0x90 834 SWOCTRL : longword; // *< FTM Software Output Control, offset: 0x94 835 PWMLOAD : longword; // *< FTM PWM Load, offset: 0x98 836 end; 837 838const 839 FTM0_BASE = $40038000; 840 841var 842 FTM0 : TFTM_Registers absolute FTM0_BASE; 843 844const 845 FTM1_BASE = $40039000; 846 847var 848 FTM1 : TFTM_Registers absolute FTM1_BASE; 849 850const 851 FTM2_BASE = $4003A000; 852 853var 854 FTM2 : TFTM_Registers absolute FTM2_BASE; 855 856const 857 FTM3_BASE = $400B9000; 858 859var 860 FTM3 : TFTM_Registers absolute FTM3_BASE; 861 862type 863 TGPIO_Registers = record 864 PDOR : longword; // *< Port Data Output Register, offset: 0x0 865 PSOR : longword; // *< Port Set Output Register, offset: 0x4 866 PCOR : longword; // *< Port Clear Output Register, offset: 0x8 867 PTOR : longword; // *< Port Toggle Output Register, offset: 0xC 868 PDIR : longword; // *< Port Data Input Register, offset: 0x10 869 PDDR : longword; // *< Port Data Direction Register, offset: 0x14 870 end; 871 872const 873 PTA_BASE = $400FF000; 874 875var 876 PTA : TGPIO_Registers absolute PTA_BASE; 877 878const 879 PTB_BASE = $400FF040; 880 881var 882 PTB : TGPIO_Registers absolute PTB_BASE; 883 884const 885 PTC_BASE = $400FF080; 886 887var 888 PTC : TGPIO_Registers absolute PTC_BASE; 889 890const 891 PTD_BASE = $400FF0C0; 892 893var 894 PTD : TGPIO_Registers absolute PTD_BASE; 895 896const 897 PTE_BASE = $400FF100; 898 899var 900 PTE : TGPIO_Registers absolute PTE_BASE; 901 902type 903 TI2C_Registers = record 904 A1 : byte; // *< I2C Address Register 1, offset: 0x0 905 F : byte; // *< I2C Frequency Divider register, offset: 0x1 906 C1 : byte; // *< I2C Control Register 1, offset: 0x2 907 S : byte; // *< I2C Status register, offset: 0x3 908 D : byte; // *< I2C Data I/O register, offset: 0x4 909 C2 : byte; // *< I2C Control Register 2, offset: 0x5 910 FLT : byte; // *< I2C Programmable Input Glitch Filter register, offset: 0x6 911 RA : byte; // *< I2C Range Address register, offset: 0x7 912 SMB : byte; // *< I2C SMBus Control and Status register, offset: 0x8 913 A2 : byte; // *< I2C Address Register 2, offset: 0x9 914 SLTH : byte; // *< I2C SCL Low Timeout Register High, offset: 0xA 915 SLTL : byte; // *< I2C SCL Low Timeout Register Low, offset: 0xB 916 end; 917 918const 919 I2C0_BASE = $40066000; 920 921var 922 I2C0 : TI2C_Registers absolute I2C0_BASE; 923 924const 925 I2C1_BASE = $40067000; 926 927var 928 I2C1 : TI2C_Registers absolute I2C1_BASE; 929 930const 931 I2C2_BASE = $400E6000; 932 933var 934 I2C2 : TI2C_Registers absolute I2C2_BASE; 935 936type 937 TI2S_Registers = record 938 TCSR : longword; // *< SAI Transmit Control Register, offset: 0x0 939 TCR1 : longword; // *< SAI Transmit Configuration 1 Register, offset: 0x4 940 TCR2 : longword; // *< SAI Transmit Configuration 2 Register, offset: 0x8 941 TCR3 : longword; // *< SAI Transmit Configuration 3 Register, offset: 0xC 942 TCR4 : longword; // *< SAI Transmit Configuration 4 Register, offset: 0x10 943 TCR5 : longword; // *< SAI Transmit Configuration 5 Register, offset: 0x14 944 RESERVED_0 : array[0..7] of byte; 945 TDR : array[0..1] of longword; // *< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 946 RESERVED_1 : array[0..23] of byte; 947 TFR : array[0..1] of longword; // *< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 948 RESERVED_2 : array[0..23] of byte; 949 TMR : longword; // *< SAI Transmit Mask Register, offset: 0x60 950 RESERVED_3 : array[0..27] of byte; 951 RCSR : longword; // *< SAI Receive Control Register, offset: 0x80 952 RCR1 : longword; // *< SAI Receive Configuration 1 Register, offset: 0x84 953 RCR2 : longword; // *< SAI Receive Configuration 2 Register, offset: 0x88 954 RCR3 : longword; // *< SAI Receive Configuration 3 Register, offset: 0x8C 955 RCR4 : longword; // *< SAI Receive Configuration 4 Register, offset: 0x90 956 RCR5 : longword; // *< SAI Receive Configuration 5 Register, offset: 0x94 957 RESERVED_4 : array[0..7] of byte; 958 RDR : array[0..1] of longword; // *< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 959 RESERVED_5 : array[0..23] of byte; 960 RFR : array[0..1] of longword; // *< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 961 RESERVED_6 : array[0..23] of byte; 962 RMR : longword; // *< SAI Receive Mask Register, offset: 0xE0 963 RESERVED_7 : array[0..27] of byte; 964 MCR : longword; // *< SAI MCLK Control Register, offset: 0x100 965 MDR : longword; // *< SAI MCLK Divide Register, offset: 0x104 966 end; 967 968const 969 I2S0_BASE = $4002F000; 970 971var 972 I2S0 : TI2S_Registers absolute I2S0_BASE; 973 974type 975 TLLWU_Registers = record 976 PE1 : byte; // *< LLWU Pin Enable 1 register, offset: 0x0 977 PE2 : byte; // *< LLWU Pin Enable 2 register, offset: 0x1 978 PE3 : byte; // *< LLWU Pin Enable 3 register, offset: 0x2 979 PE4 : byte; // *< LLWU Pin Enable 4 register, offset: 0x3 980 ME : byte; // *< LLWU Module Enable register, offset: 0x4 981 F1 : byte; // *< LLWU Flag 1 register, offset: 0x5 982 F2 : byte; // *< LLWU Flag 2 register, offset: 0x6 983 F3 : byte; // *< LLWU Flag 3 register, offset: 0x7 984 FILT1 : byte; // *< LLWU Pin Filter 1 register, offset: 0x8 985 FILT2 : byte; // *< LLWU Pin Filter 2 register, offset: 0x9 986 RST : byte; // *< LLWU Reset Enable register, offset: 0xA 987 end; 988 989const 990 LLWU_BASE = $4007C000; 991 992var 993 LLWU : TLLWU_Registers absolute LLWU_BASE; 994 995type 996 TLPTMR_Registers = record 997 CSR : longword; // *< Low Power Timer Control Status Register, offset: 0x0 998 PSR : longword; // *< Low Power Timer Prescale Register, offset: 0x4 999 CMR : longword; // *< Low Power Timer Compare Register, offset: 0x8 1000 CNR : longword; // *< Low Power Timer Counter Register, offset: 0xC 1001 end; 1002 1003const 1004 LPTMR0_BASE = $40040000; 1005 1006var 1007 LPTMR0 : TLPTMR_Registers absolute LPTMR0_BASE; 1008 1009type 1010 TMCG_Registers = record 1011 C1 : byte; // *< MCG Control 1 Register, offset: 0x0 1012 C2 : byte; // *< MCG Control 2 Register, offset: 0x1 1013 C3 : byte; // *< MCG Control 3 Register, offset: 0x2 1014 C4 : byte; // *< MCG Control 4 Register, offset: 0x3 1015 C5 : byte; // *< MCG Control 5 Register, offset: 0x4 1016 C6 : byte; // *< MCG Control 6 Register, offset: 0x5 1017 S : byte; // *< MCG Status Register, offset: 0x6 1018 RESERVED_0 : array[0..0] of byte; 1019 SC : byte; // *< MCG Status and Control Register, offset: 0x8 1020 RESERVED_1 : array[0..0] of byte; 1021 ATCVH : byte; // *< MCG Auto Trim Compare Value High Register, offset: 0xA 1022 ATCVL : byte; // *< MCG Auto Trim Compare Value Low Register, offset: 0xB 1023 C7 : byte; // *< MCG Control 7 Register, offset: 0xC 1024 C8 : byte; // *< MCG Control 8 Register, offset: 0xD 1025 end; 1026 1027const 1028 MCG_BASE = $40064000; 1029 1030var 1031 MCG : TMCG_Registers absolute MCG_BASE; 1032 1033type 1034 TMCM_Registers = record 1035 RESERVED_0 : array[0..7] of byte; 1036 PLASC : word; // *< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 1037 PLAMC : word; // *< Crossbar Switch (AXBS) Master Configuration, offset: 0xA 1038 CR : longword; // *< Control Register, offset: 0xC 1039 ISCR : longword; // *< Interrupt Status Register, offset: 0x10 1040 ETBCC : longword; // *< ETB Counter Control register, offset: 0x14 1041 ETBRL : longword; // *< ETB Reload register, offset: 0x18 1042 ETBCNT : longword; // *< ETB Counter Value register, offset: 0x1C 1043 RESERVED_1 : array[0..15] of byte; 1044 PID : longword; // *< Process ID register, offset: 0x30 1045 end; 1046 1047const 1048 MCM_BASE = $E0080000; 1049 1050var 1051 MCM : TMCM_Registers absolute MCM_BASE; 1052 1053type 1054 TMPU_SP = record 1055 EAR : longword; // *< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 1056 EDR : longword; // *< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 1057 end; 1058 1059 TMPU_Registers = record 1060 CESR : longword; // *< Control/Error Status Register, offset: 0x0 1061 RESERVED_0 : array[0..11] of byte; 1062 SP : array[0..4] of TMPU_SP; 1063 RESERVED_1 : array[0..967] of byte; 1064 WORD : array[0..11] of longword; // *< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 1065 RESERVED_2 : array[0..831] of byte; 1066 RGDAAC : array[0..11] of longword; // *< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 1067 end; 1068 1069const 1070 MPU_BASE = $4000D000; 1071 1072var 1073 MPU : TMPU_Registers absolute MPU_BASE; 1074 1075type 1076 TNV_Registers = record 1077 BACKKEY3 : byte; // *< Backdoor Comparison Key 3., offset: 0x0 1078 BACKKEY2 : byte; // *< Backdoor Comparison Key 2., offset: 0x1 1079 BACKKEY1 : byte; // *< Backdoor Comparison Key 1., offset: 0x2 1080 BACKKEY0 : byte; // *< Backdoor Comparison Key 0., offset: 0x3 1081 BACKKEY7 : byte; // *< Backdoor Comparison Key 7., offset: 0x4 1082 BACKKEY6 : byte; // *< Backdoor Comparison Key 6., offset: 0x5 1083 BACKKEY5 : byte; // *< Backdoor Comparison Key 5., offset: 0x6 1084 BACKKEY4 : byte; // *< Backdoor Comparison Key 4., offset: 0x7 1085 FPROT3 : byte; // *< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 1086 FPROT2 : byte; // *< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 1087 FPROT1 : byte; // *< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA 1088 FPROT0 : byte; // *< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB 1089 FSEC : byte; // *< Non-volatile Flash Security Register, offset: 0xC 1090 FOPT : byte; // *< Non-volatile Flash Option Register, offset: 0xD 1091 FEPROT : byte; // *< Non-volatile EERAM Protection Register, offset: 0xE 1092 FDPROT : byte; // *< Non-volatile D-Flash Protection Register, offset: 0xF 1093 end; 1094 1095const 1096 FTFE_FlashConfig_BASE = $400; 1097 1098var 1099 FTFE_FlashConfig : TNV_Registers absolute FTFE_FlashConfig_BASE; 1100 1101type 1102 TOSC_Registers = record 1103 CR : byte; // *< OSC Control Register, offset: 0x0 1104 end; 1105 1106const 1107 OSC_BASE = $40065000; 1108 1109var 1110 OSC : TOSC_Registers absolute OSC_BASE; 1111 1112type 1113 TPDB_CH = record 1114 C1 : longword; // *< Channel n Control register 1, array offset: 0x10, array step: 0x28 1115 S : longword; // *< Channel n Status register, array offset: 0x14, array step: 0x28 1116 DLY : array[0..1] of longword; // *< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 1117 RESERVED_0 : array[0..23] of byte; 1118 end; 1119 TPDB_DAC = record 1120 INTC : longword; // *< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 1121 INT : longword; // *< DAC Interval n register, array offset: 0x154, array step: 0x8 1122 end; 1123 1124 TPDB_Registers = record 1125 SC : longword; // *< Status and Control register, offset: 0x0 1126 &MOD : longword; // *< Modulus register, offset: 0x4 1127 CNT : longword; // *< Counter register, offset: 0x8 1128 IDLY : longword; // *< Interrupt Delay register, offset: 0xC 1129 CH : array[0..1] of TPDB_CH; 1130 RESERVED_0 : array[0..239] of byte; 1131 DAC : array[0..1] of TPDB_DAC; 1132 RESERVED_1 : array[0..47] of byte; 1133 POEN : longword; // *< Pulse-Out n Enable register, offset: 0x190 1134 PODLY : array[0..2] of longword; // *< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 1135 end; 1136 1137const 1138 PDB0_BASE = $40036000; 1139 1140var 1141 PDB0 : TPDB_Registers absolute PDB0_BASE; 1142 1143type 1144 TPIT_CHANNEL = record 1145 LDVAL : longword; // *< Timer Load Value Register, array offset: 0x100, array step: 0x10 1146 CVAL : longword; // *< Current Timer Value Register, array offset: 0x104, array step: 0x10 1147 TCTRL : longword; // *< Timer Control Register, array offset: 0x108, array step: 0x10 1148 TFLG : longword; // *< Timer Flag Register, array offset: 0x10C, array step: 0x10 1149 end; 1150 1151 TPIT_Registers = record 1152 MCR : longword; // *< PIT Module Control Register, offset: 0x0 1153 RESERVED_0 : array[0..251] of byte; 1154 CHANNEL : array[0..3] of TPIT_CHANNEL; 1155 end; 1156 1157const 1158 PIT_BASE = $40037000; 1159 1160var 1161 PIT : TPIT_Registers absolute PIT_BASE; 1162 1163type 1164 TPMC_Registers = record 1165 LVDSC1 : byte; // *< Low Voltage Detect Status And Control 1 register, offset: 0x0 1166 LVDSC2 : byte; // *< Low Voltage Detect Status And Control 2 register, offset: 0x1 1167 REGSC : byte; // *< Regulator Status And Control register, offset: 0x2 1168 end; 1169 1170const 1171 PMC_BASE = $4007D000; 1172 1173var 1174 PMC : TPMC_Registers absolute PMC_BASE; 1175 1176type 1177 TPORT_Registers = record 1178 PCR : array[0..31] of longword; // *< Pin Control Register n, array offset: 0x0, array step: 0x4 1179 GPCLR : longword; // *< Global Pin Control Low Register, offset: 0x80 1180 GPCHR : longword; // *< Global Pin Control High Register, offset: 0x84 1181 RESERVED_0 : array[0..23] of byte; 1182 ISFR : longword; // *< Interrupt Status Flag Register, offset: 0xA0 1183 RESERVED_1 : array[0..27] of byte; 1184 DFER : longword; // *< Digital Filter Enable Register, offset: 0xC0 1185 DFCR : longword; // *< Digital Filter Clock Register, offset: 0xC4 1186 DFWR : longword; // *< Digital Filter Width Register, offset: 0xC8 1187 end; 1188 1189const 1190 PORTA_BASE = $40049000; 1191 1192var 1193 PORTA : TPORT_Registers absolute PORTA_BASE; 1194 1195const 1196 PORTB_BASE = $4004A000; 1197 1198var 1199 PORTB : TPORT_Registers absolute PORTB_BASE; 1200 1201const 1202 PORTC_BASE = $4004B000; 1203 1204var 1205 PORTC : TPORT_Registers absolute PORTC_BASE; 1206 1207const 1208 PORTD_BASE = $4004C000; 1209 1210var 1211 PORTD : TPORT_Registers absolute PORTD_BASE; 1212 1213const 1214 PORTE_BASE = $4004D000; 1215 1216var 1217 PORTE : TPORT_Registers absolute PORTE_BASE; 1218 1219type 1220 TRCM_Registers = record 1221 SRS0 : byte; // *< System Reset Status Register 0, offset: 0x0 1222 SRS1 : byte; // *< System Reset Status Register 1, offset: 0x1 1223 RESERVED_0 : array[0..1] of byte; 1224 RPFC : byte; // *< Reset Pin Filter Control register, offset: 0x4 1225 RPFW : byte; // *< Reset Pin Filter Width register, offset: 0x5 1226 RESERVED_1 : array[0..0] of byte; 1227 MR : byte; // *< Mode Register, offset: 0x7 1228 end; 1229 1230const 1231 RCM_BASE = $4007F000; 1232 1233var 1234 RCM : TRCM_Registers absolute RCM_BASE; 1235 1236type 1237 TRFSYS_Registers = record 1238 REG : array[0..7] of longword; // *< Register file register, array offset: 0x0, array step: 0x4 1239 end; 1240 1241const 1242 RFSYS_BASE = $40041000; 1243 1244var 1245 RFSYS : TRFSYS_Registers absolute RFSYS_BASE; 1246 1247type 1248 TRFVBAT_Registers = record 1249 REG : array[0..7] of longword; // *< VBAT register file register, array offset: 0x0, array step: 0x4 1250 end; 1251 1252const 1253 RFVBAT_BASE = $4003E000; 1254 1255var 1256 RFVBAT : TRFVBAT_Registers absolute RFVBAT_BASE; 1257 1258type 1259 TRNG_Registers = record 1260 CR : longword; // *< RNGA Control Register, offset: 0x0 1261 SR : longword; // *< RNGA Status Register, offset: 0x4 1262 ER : longword; // *< RNGA Entropy Register, offset: 0x8 1263 &OR : longword; // *< RNGA Output Register, offset: 0xC 1264 end; 1265 1266const 1267 RNG_BASE = $40029000; 1268 1269var 1270 RNG : TRNG_Registers absolute RNG_BASE; 1271 1272type 1273 TRTC_Registers = record 1274 TSR : longword; // *< RTC Time Seconds Register, offset: 0x0 1275 TPR : longword; // *< RTC Time Prescaler Register, offset: 0x4 1276 TAR : longword; // *< RTC Time Alarm Register, offset: 0x8 1277 TCR : longword; // *< RTC Time Compensation Register, offset: 0xC 1278 CR : longword; // *< RTC Control Register, offset: 0x10 1279 SR : longword; // *< RTC Status Register, offset: 0x14 1280 LR : longword; // *< RTC Lock Register, offset: 0x18 1281 IER : longword; // *< RTC Interrupt Enable Register, offset: 0x1C 1282 RESERVED_0 : array[0..2015] of byte; 1283 WAR : longword; // *< RTC Write Access Register, offset: 0x800 1284 RAR : longword; // *< RTC Read Access Register, offset: 0x804 1285 end; 1286 1287const 1288 RTC_BASE = $4003D000; 1289 1290var 1291 RTC : TRTC_Registers absolute RTC_BASE; 1292 1293type 1294 TSDHC_Registers = record 1295 DSADDR : longword; // *< DMA System Address register, offset: 0x0 1296 BLKATTR : longword; // *< Block Attributes register, offset: 0x4 1297 CMDARG : longword; // *< Command Argument register, offset: 0x8 1298 XFERTYP : longword; // *< Transfer Type register, offset: 0xC 1299 CMDRSP : array[0..3] of longword; // *< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 1300 DATPORT : longword; // *< Buffer Data Port register, offset: 0x20 1301 PRSSTAT : longword; // *< Present State register, offset: 0x24 1302 PROCTL : longword; // *< Protocol Control register, offset: 0x28 1303 SYSCTL : longword; // *< System Control register, offset: 0x2C 1304 IRQSTAT : longword; // *< Interrupt Status register, offset: 0x30 1305 IRQSTATEN : longword; // *< Interrupt Status Enable register, offset: 0x34 1306 IRQSIGEN : longword; // *< Interrupt Signal Enable register, offset: 0x38 1307 AC12ERR : longword; // *< Auto CMD12 Error Status Register, offset: 0x3C 1308 HTCAPBLT : longword; // *< Host Controller Capabilities, offset: 0x40 1309 WML : longword; // *< Watermark Level Register, offset: 0x44 1310 RESERVED_0 : array[0..7] of byte; 1311 FEVT : longword; // *< Force Event register, offset: 0x50 1312 ADMAES : longword; // *< ADMA Error Status register, offset: 0x54 1313 ADSADDR : longword; // *< ADMA System Addressregister, offset: 0x58 1314 RESERVED_1 : array[0..99] of byte; 1315 VENDOR : longword; // *< Vendor Specific register, offset: 0xC0 1316 MMCBOOT : longword; // *< MMC Boot register, offset: 0xC4 1317 RESERVED_2 : array[0..51] of byte; 1318 HOSTVER : longword; // *< Host Controller Version, offset: 0xFC 1319 end; 1320 1321const 1322 SDHC_BASE = $400B1000; 1323 1324var 1325 SDHC : TSDHC_Registers absolute SDHC_BASE; 1326 1327type 1328 TSIM_Registers = record 1329 SOPT1 : longword; // *< System Options Register 1, offset: 0x0 1330 SOPT1CFG : longword; // *< SOPT1 Configuration Register, offset: 0x4 1331 RESERVED_0 : array[0..4091] of byte; 1332 SOPT2 : longword; // *< System Options Register 2, offset: 0x1004 1333 RESERVED_1 : array[0..3] of byte; 1334 SOPT4 : longword; // *< System Options Register 4, offset: 0x100C 1335 SOPT5 : longword; // *< System Options Register 5, offset: 0x1010 1336 RESERVED_2 : array[0..3] of byte; 1337 SOPT7 : longword; // *< System Options Register 7, offset: 0x1018 1338 RESERVED_3 : array[0..7] of byte; 1339 SDID : longword; // *< System Device Identification Register, offset: 0x1024 1340 SCGC1 : longword; // *< System Clock Gating Control Register 1, offset: 0x1028 1341 SCGC2 : longword; // *< System Clock Gating Control Register 2, offset: 0x102C 1342 SCGC3 : longword; // *< System Clock Gating Control Register 3, offset: 0x1030 1343 SCGC4 : longword; // *< System Clock Gating Control Register 4, offset: 0x1034 1344 SCGC5 : longword; // *< System Clock Gating Control Register 5, offset: 0x1038 1345 SCGC6 : longword; // *< System Clock Gating Control Register 6, offset: 0x103C 1346 SCGC7 : longword; // *< System Clock Gating Control Register 7, offset: 0x1040 1347 CLKDIV1 : longword; // *< System Clock Divider Register 1, offset: 0x1044 1348 CLKDIV2 : longword; // *< System Clock Divider Register 2, offset: 0x1048 1349 FCFG1 : longword; // *< Flash Configuration Register 1, offset: 0x104C 1350 FCFG2 : longword; // *< Flash Configuration Register 2, offset: 0x1050 1351 UIDH : longword; // *< Unique Identification Register High, offset: 0x1054 1352 UIDMH : longword; // *< Unique Identification Register Mid-High, offset: 0x1058 1353 UIDML : longword; // *< Unique Identification Register Mid Low, offset: 0x105C 1354 UIDL : longword; // *< Unique Identification Register Low, offset: 0x1060 1355 end; 1356 1357const 1358 SIM_BASE = $40047000; 1359 1360var 1361 SIM : TSIM_Registers absolute SIM_BASE; 1362 1363type 1364 TSMC_Registers = record 1365 PMPROT : byte; // *< Power Mode Protection register, offset: 0x0 1366 PMCTRL : byte; // *< Power Mode Control register, offset: 0x1 1367 VLLSCTRL : byte; // *< VLLS Control register, offset: 0x2 1368 PMSTAT : byte; // *< Power Mode Status register, offset: 0x3 1369 end; 1370 1371const 1372 SMC_BASE = $4007E000; 1373 1374var 1375 SMC : TSMC_Registers absolute SMC_BASE; 1376 1377type 1378 TSPI_Registers = record 1379 MCR : longword; // *< Module Configuration Register, offset: 0x0 1380 RESERVED_0 : array[0..3] of byte; 1381 TCR : longword; // *< Transfer Count Register, offset: 0x8 1382 CTAR : array[0..1] of longword; // *< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 1383 RESERVED_1 : array[0..23] of byte; 1384 SR : longword; // *< Status Register, offset: 0x2C 1385 RSER : longword; // *< DMA/Interrupt Request Select and Enable Register, offset: 0x30 1386 PUSHR : longword; // *< PUSH TX FIFO Register In Master Mode, offset: 0x34 1387 POPR : longword; // *< POP RX FIFO Register, offset: 0x38 1388 TXFR0 : longword; // *< Transmit FIFO Registers, offset: 0x3C 1389 TXFR1 : longword; // *< Transmit FIFO Registers, offset: 0x40 1390 TXFR2 : longword; // *< Transmit FIFO Registers, offset: 0x44 1391 TXFR3 : longword; // *< Transmit FIFO Registers, offset: 0x48 1392 RESERVED_2 : array[0..47] of byte; 1393 RXFR0 : longword; // *< Receive FIFO Registers, offset: 0x7C 1394 RXFR1 : longword; // *< Receive FIFO Registers, offset: 0x80 1395 RXFR2 : longword; // *< Receive FIFO Registers, offset: 0x84 1396 RXFR3 : longword; // *< Receive FIFO Registers, offset: 0x88 1397 end; 1398 1399const 1400 SPI0_BASE = $4002C000; 1401 1402var 1403 SPI0 : TSPI_Registers absolute SPI0_BASE; 1404 1405const 1406 SPI1_BASE = $4002D000; 1407 1408var 1409 SPI1 : TSPI_Registers absolute SPI1_BASE; 1410 1411const 1412 SPI2_BASE = $400AC000; 1413 1414var 1415 SPI2 : TSPI_Registers absolute SPI2_BASE; 1416 1417type 1418 TUART_Registers = record 1419 BDH : byte; // *< UART Baud Rate Registers: High, offset: 0x0 1420 BDL : byte; // *< UART Baud Rate Registers: Low, offset: 0x1 1421 C1 : byte; // *< UART Control Register 1, offset: 0x2 1422 C2 : byte; // *< UART Control Register 2, offset: 0x3 1423 S1 : byte; // *< UART Status Register 1, offset: 0x4 1424 S2 : byte; // *< UART Status Register 2, offset: 0x5 1425 C3 : byte; // *< UART Control Register 3, offset: 0x6 1426 D : byte; // *< UART Data Register, offset: 0x7 1427 MA1 : byte; // *< UART Match Address Registers 1, offset: 0x8 1428 MA2 : byte; // *< UART Match Address Registers 2, offset: 0x9 1429 C4 : byte; // *< UART Control Register 4, offset: 0xA 1430 C5 : byte; // *< UART Control Register 5, offset: 0xB 1431 ED : byte; // *< UART Extended Data Register, offset: 0xC 1432 MODEM : byte; // *< UART Modem Register, offset: 0xD 1433 IR : byte; // *< UART Infrared Register, offset: 0xE 1434 RESERVED_0 : array[0..0] of byte; 1435 PFIFO : byte; // *< UART FIFO Parameters, offset: 0x10 1436 CFIFO : byte; // *< UART FIFO Control Register, offset: 0x11 1437 SFIFO : byte; // *< UART FIFO Status Register, offset: 0x12 1438 TWFIFO : byte; // *< UART FIFO Transmit Watermark, offset: 0x13 1439 TCFIFO : byte; // *< UART FIFO Transmit Count, offset: 0x14 1440 RWFIFO : byte; // *< UART FIFO Receive Watermark, offset: 0x15 1441 RCFIFO : byte; // *< UART FIFO Receive Count, offset: 0x16 1442 RESERVED_1 : array[0..0] of byte; 1443 C7816 : byte; // *< UART 7816 Control Register, offset: 0x18 1444 IE7816 : byte; // *< UART 7816 Interrupt Enable Register, offset: 0x19 1445 IS7816 : byte; // *< UART 7816 Interrupt Status Register, offset: 0x1A 1446 WP7816T0 : byte; // *< UART 7816 Wait Parameter Register, offset: 0x1B 1447 WN7816 : byte; // *< UART 7816 Wait N Register, offset: 0x1C 1448 WF7816 : byte; // *< UART 7816 Wait FD Register, offset: 0x1D 1449 ET7816 : byte; // *< UART 7816 Error Threshold Register, offset: 0x1E 1450 TL7816 : byte; // *< UART 7816 Transmit Length Register, offset: 0x1F 1451 end; 1452 1453const 1454 UART0_BASE = $4006A000; 1455 1456var 1457 UART0 : TUART_Registers absolute UART0_BASE; 1458 1459const 1460 UART1_BASE = $4006B000; 1461 1462var 1463 UART1 : TUART_Registers absolute UART1_BASE; 1464 1465const 1466 UART2_BASE = $4006C000; 1467 1468var 1469 UART2 : TUART_Registers absolute UART2_BASE; 1470 1471const 1472 UART3_BASE = $4006D000; 1473 1474var 1475 UART3 : TUART_Registers absolute UART3_BASE; 1476 1477const 1478 UART4_BASE = $400EA000; 1479 1480var 1481 UART4 : TUART_Registers absolute UART4_BASE; 1482 1483const 1484 UART5_BASE = $400EB000; 1485 1486var 1487 UART5 : TUART_Registers absolute UART5_BASE; 1488 1489type 1490 TUSB_ENDPOINT= record 1491 ENDPT : byte; // *< Endpoint Control register, array offset: 0xC0, array step: 0x4 1492 RESERVED_0 : array[0..2] of byte; 1493 end; 1494 1495 TUSB_Registers = record 1496 PERID : byte; // *< Peripheral ID register, offset: 0x0 1497 RESERVED_0 : array[0..2] of byte; 1498 IDCOMP : byte; // *< Peripheral ID Complement register, offset: 0x4 1499 RESERVED_1 : array[0..2] of byte; 1500 REV : byte; // *< Peripheral Revision register, offset: 0x8 1501 RESERVED_2 : array[0..2] of byte; 1502 ADDINFO : byte; // *< Peripheral Additional Info register, offset: 0xC 1503 RESERVED_3 : array[0..2] of byte; 1504 OTGISTAT : byte; // *< OTG Interrupt Status register, offset: 0x10 1505 RESERVED_4 : array[0..2] of byte; 1506 OTGICR : byte; // *< OTG Interrupt Control register, offset: 0x14 1507 RESERVED_5 : array[0..2] of byte; 1508 OTGSTAT : byte; // *< OTG Status register, offset: 0x18 1509 RESERVED_6 : array[0..2] of byte; 1510 OTGCTL : byte; // *< OTG Control register, offset: 0x1C 1511 RESERVED_7 : array[0..98] of byte; 1512 ISTAT : byte; // *< Interrupt Status register, offset: 0x80 1513 RESERVED_8 : array[0..2] of byte; 1514 INTEN : byte; // *< Interrupt Enable register, offset: 0x84 1515 RESERVED_9 : array[0..2] of byte; 1516 ERRSTAT : byte; // *< Error Interrupt Status register, offset: 0x88 1517 RESERVED_10 : array[0..2] of byte; 1518 ERREN : byte; // *< Error Interrupt Enable register, offset: 0x8C 1519 RESERVED_11 : array[0..2] of byte; 1520 STAT : byte; // *< Status register, offset: 0x90 1521 RESERVED_12 : array[0..2] of byte; 1522 CTL : byte; // *< Control register, offset: 0x94 1523 RESERVED_13 : array[0..2] of byte; 1524 ADDR : byte; // *< Address register, offset: 0x98 1525 RESERVED_14 : array[0..2] of byte; 1526 BDTPAGE1 : byte; // *< BDT Page register 1, offset: 0x9C 1527 RESERVED_15 : array[0..2] of byte; 1528 FRMNUML : byte; // *< Frame Number register Low, offset: 0xA0 1529 RESERVED_16 : array[0..2] of byte; 1530 FRMNUMH : byte; // *< Frame Number register High, offset: 0xA4 1531 RESERVED_17 : array[0..2] of byte; 1532 TOKEN : byte; // *< Token register, offset: 0xA8 1533 RESERVED_18 : array[0..2] of byte; 1534 SOFTHLD : byte; // *< SOF Threshold register, offset: 0xAC 1535 RESERVED_19 : array[0..2] of byte; 1536 BDTPAGE2 : byte; // *< BDT Page Register 2, offset: 0xB0 1537 RESERVED_20 : array[0..2] of byte; 1538 BDTPAGE3 : byte; // *< BDT Page Register 3, offset: 0xB4 1539 RESERVED_21 : array[0..10] of byte; 1540 ENDPOINT : array[0..15] of TUSB_ENDPOINT; 1541 USBCTRL : byte; // *< USB Control register, offset: 0x100 1542 RESERVED_22 : array[0..2] of byte; 1543 OBSERVE : byte; // *< USB OTG Observe register, offset: 0x104 1544 RESERVED_23 : array[0..2] of byte; 1545 CONTROL : byte; // *< USB OTG Control register, offset: 0x108 1546 RESERVED_24 : array[0..2] of byte; 1547 USBTRC0 : byte; // *< USB Transceiver Control register 0, offset: 0x10C 1548 RESERVED_25 : array[0..6] of byte; 1549 USBFRMADJUST : byte; // *< Frame Adjust Register, offset: 0x114 1550 RESERVED_26 : array[0..42] of byte; 1551 CLK_RECOVER_CTRL : byte; // *< USB Clock recovery control, offset: 0x140 1552 RESERVED_27 : array[0..2] of byte; 1553 CLK_RECOVER_IRC_EN : byte; // *< IRC48M oscillator enable register, offset: 0x144 1554 RESERVED_28 : array[0..22] of byte; 1555 CLK_RECOVER_INT_STATUS : byte; // *< Clock recovery separated interrupt status, offset: 0x15C 1556 end; 1557 1558const 1559 USB0_BASE = $40072000; 1560 1561var 1562 USB0 : TUSB_Registers absolute USB0_BASE; 1563 1564type 1565 TUSBDCD_Registers = record 1566 CONTROL : longword; // *< Control register, offset: 0x0 1567 CLOCK : longword; // *< Clock register, offset: 0x4 1568 STATUS : longword; // *< Status register, offset: 0x8 1569 RESERVED_0 : array[0..3] of byte; 1570 TIMER0 : longword; // *< TIMER0 register, offset: 0x10 1571 TIMER1 : longword; // *< TIMER1 register, offset: 0x14 1572 TIMER2_BC11: longword; // *< TIMER2_BC11 register, offset: 0x18 1573 end; 1574 1575const 1576 USBDCD_BASE = $40035000; 1577 1578var 1579 USBDCD : TUSBDCD_Registers absolute USBDCD_BASE; 1580 1581type 1582 TVREF_Registers = record 1583 TRM : byte; // *< VREF Trim Register, offset: 0x0 1584 SC : byte; // *< VREF Status and Control Register, offset: 0x1 1585 end; 1586 1587const 1588 VREF_BASE = $40074000; 1589 1590var 1591 VREF : TVREF_Registers absolute VREF_BASE; 1592 1593type 1594 TWDOG_Registers = record 1595 STCTRLH : word; // *< Watchdog Status and Control Register High, offset: 0x0 1596 STCTRLL : word; // *< Watchdog Status and Control Register Low, offset: 0x2 1597 TOVALH : word; // *< Watchdog Time-out Value Register High, offset: 0x4 1598 TOVALL : word; // *< Watchdog Time-out Value Register Low, offset: 0x6 1599 WINH : word; // *< Watchdog Window Register High, offset: 0x8 1600 WINL : word; // *< Watchdog Window Register Low, offset: 0xA 1601 REFRESH : word; // *< Watchdog Refresh register, offset: 0xC 1602 UNLOCK : word; // *< Watchdog Unlock register, offset: 0xE 1603 TMROUTH : word; // *< Watchdog Timer Output Register High, offset: 0x10 1604 TMROUTL : word; // *< Watchdog Timer Output Register Low, offset: 0x12 1605 RSTCNT : word; // *< Watchdog Reset Count register, offset: 0x14 1606 PRESC : word; // *< Watchdog Prescaler register, offset: 0x16 1607 end; 1608 1609const 1610 WDOG_BASE = $40052000; 1611 1612var 1613 WDOG : TWDOG_Registers absolute WDOG_BASE; 1614 1615implementation 1616 1617procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt'; 1618procedure HardFault_interrupt; external name 'HardFault_interrupt'; 1619procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt'; 1620procedure BusFault_interrupt; external name 'BusFault_interrupt'; 1621procedure UsageFault_interrupt; external name 'UsageFault_interrupt'; 1622procedure SVCall_interrupt; external name 'SVCall_interrupt'; 1623procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt'; 1624procedure PendSV_interrupt; external name 'PendSV_interrupt'; 1625procedure SysTick_interrupt; external name 'SysTick_interrupt'; 1626procedure DMA0_interrupt; external name 'DMA0_interrupt'; 1627procedure DMA1_interrupt; external name 'DMA1_interrupt'; 1628procedure DMA2_interrupt; external name 'DMA2_interrupt'; 1629procedure DMA3_interrupt; external name 'DMA3_interrupt'; 1630procedure DMA4_interrupt; external name 'DMA4_interrupt'; 1631procedure DMA5_interrupt; external name 'DMA5_interrupt'; 1632procedure DMA6_interrupt; external name 'DMA6_interrupt'; 1633procedure DMA7_interrupt; external name 'DMA7_interrupt'; 1634procedure DMA8_interrupt; external name 'DMA8_interrupt'; 1635procedure DMA9_interrupt; external name 'DMA9_interrupt'; 1636procedure DMA10_interrupt; external name 'DMA10_interrupt'; 1637procedure DMA11_interrupt; external name 'DMA11_interrupt'; 1638procedure DMA12_interrupt; external name 'DMA12_interrupt'; 1639procedure DMA13_interrupt; external name 'DMA13_interrupt'; 1640procedure DMA14_interrupt; external name 'DMA14_interrupt'; 1641procedure DMA15_interrupt; external name 'DMA15_interrupt'; 1642procedure DMA_Error_interrupt; external name 'DMA_Error_interrupt'; 1643procedure MCM_interrupt; external name 'MCM_interrupt'; 1644procedure FTFE_interrupt; external name 'FTFE_interrupt'; 1645procedure Read_Collision_interrupt; external name 'Read_Collision_interrupt'; 1646procedure LVD_LVW_interrupt; external name 'LVD_LVW_interrupt'; 1647procedure LLWU_interrupt; external name 'LLWU_interrupt'; 1648procedure WDOG_EWM_interrupt; external name 'WDOG_EWM_interrupt'; 1649procedure RNG_interrupt; external name 'RNG_interrupt'; 1650procedure I2C0_interrupt; external name 'I2C0_interrupt'; 1651procedure I2C1_interrupt; external name 'I2C1_interrupt'; 1652procedure SPI0_interrupt; external name 'SPI0_interrupt'; 1653procedure SPI1_interrupt; external name 'SPI1_interrupt'; 1654procedure I2S0_Tx_interrupt; external name 'I2S0_Tx_interrupt'; 1655procedure I2S0_Rx_interrupt; external name 'I2S0_Rx_interrupt'; 1656procedure UART0_LON_interrupt; external name 'UART0_LON_interrupt'; 1657procedure UART0_RX_TX_interrupt; external name 'UART0_RX_TX_interrupt'; 1658procedure UART0_ERR_interrupt; external name 'UART0_ERR_interrupt'; 1659procedure UART1_RX_TX_interrupt; external name 'UART1_RX_TX_interrupt'; 1660procedure UART1_ERR_interrupt; external name 'UART1_ERR_interrupt'; 1661procedure UART2_RX_TX_interrupt; external name 'UART2_RX_TX_interrupt'; 1662procedure UART2_ERR_interrupt; external name 'UART2_ERR_interrupt'; 1663procedure UART3_RX_TX_interrupt; external name 'UART3_RX_TX_interrupt'; 1664procedure UART3_ERR_interrupt; external name 'UART3_ERR_interrupt'; 1665procedure ADC0_interrupt; external name 'ADC0_interrupt'; 1666procedure CMP0_interrupt; external name 'CMP0_interrupt'; 1667procedure CMP1_interrupt; external name 'CMP1_interrupt'; 1668procedure FTM0_interrupt; external name 'FTM0_interrupt'; 1669procedure FTM1_interrupt; external name 'FTM1_interrupt'; 1670procedure FTM2_interrupt; external name 'FTM2_interrupt'; 1671procedure CMT_interrupt; external name 'CMT_interrupt'; 1672procedure RTC_interrupt; external name 'RTC_interrupt'; 1673procedure RTC_Seconds_interrupt; external name 'RTC_Seconds_interrupt'; 1674procedure PIT0_interrupt; external name 'PIT0_interrupt'; 1675procedure PIT1_interrupt; external name 'PIT1_interrupt'; 1676procedure PIT2_interrupt; external name 'PIT2_interrupt'; 1677procedure PIT3_interrupt; external name 'PIT3_interrupt'; 1678procedure PDB0_interrupt; external name 'PDB0_interrupt'; 1679procedure USB0_interrupt; external name 'USB0_interrupt'; 1680procedure USBDCD_interrupt; external name 'USBDCD_interrupt'; 1681procedure RESERVED71_interrupt; external name 'RESERVED71_interrupt'; 1682procedure DAC0_interrupt; external name 'DAC0_interrupt'; 1683procedure MCG_interrupt; external name 'MCG_interrupt'; 1684procedure LPTMR0_interrupt; external name 'LPTMR0_interrupt'; 1685procedure PORTA_interrupt; external name 'PORTA_interrupt'; 1686procedure PORTB_interrupt; external name 'PORTB_interrupt'; 1687procedure PORTC_interrupt; external name 'PORTC_interrupt'; 1688procedure PORTD_interrupt; external name 'PORTD_interrupt'; 1689procedure PORTE_interrupt; external name 'PORTE_interrupt'; 1690procedure SWI_interrupt; external name 'SWI_interrupt'; 1691procedure SPI2_interrupt; external name 'SPI2_interrupt'; 1692procedure UART4_RX_TX_interrupt; external name 'UART4_RX_TX_interrupt'; 1693procedure UART4_ERR_interrupt; external name 'UART4_ERR_interrupt'; 1694procedure UART5_RX_TX_interrupt; external name 'UART5_RX_TX_interrupt'; 1695procedure UART5_ERR_interrupt; external name 'UART5_ERR_interrupt'; 1696procedure CMP2_interrupt; external name 'CMP2_interrupt'; 1697procedure FTM3_interrupt; external name 'FTM3_interrupt'; 1698procedure DAC1_interrupt; external name 'DAC1_interrupt'; 1699procedure ADC1_interrupt; external name 'ADC1_interrupt'; 1700procedure I2C2_interrupt; external name 'I2C2_interrupt'; 1701procedure CAN0_ORed_Message_buffer_interrupt; external name 'CAN0_ORed_Message_buffer_interrupt'; 1702procedure CAN0_Bus_Off_interrupt; external name 'CAN0_Bus_Off_interrupt'; 1703procedure CAN0_Error_interrupt; external name 'CAN0_Error_interrupt'; 1704procedure CAN0_Tx_Warning_interrupt; external name 'CAN0_Tx_Warning_interrupt'; 1705procedure CAN0_Rx_Warning_interrupt; external name 'CAN0_Rx_Warning_interrupt'; 1706procedure CAN0_Wake_Up_interrupt; external name 'CAN0_Wake_Up_interrupt'; 1707procedure SDHC_interrupt; external name 'SDHC_interrupt'; 1708procedure ENET_1588_Timer_interrupt; external name 'ENET_1588_Timer_interrupt'; 1709procedure ENET_Transmit_interrupt; external name 'ENET_Transmit_interrupt'; 1710procedure ENET_Receive_interrupt; external name 'ENET_Receive_interrupt'; 1711procedure ENET_Error_interrupt; external name 'ENET_Error_interrupt'; 1712 1713{$i cortexm4f_start.inc} 1714 1715procedure FlashConfiguration; assembler; nostackframe; 1716label flash_conf; 1717asm 1718 .section ".flash_config.flash_conf" 1719flash_conf: 1720 .byte 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF 1721 1722 .text 1723end; 1724 1725procedure LowLevelStartup; assembler; nostackframe; [public, alias: '_LOWLEVELSTART']; 1726asm 1727 // Unlock watchdog 1728 ldr r0, .LWDOG_BASE 1729 movw r1, #50464 1730 strh r1, [r0, #0xE] 1731 movw r1, #55592 1732 strh r1, [r0, #0xE] 1733 nop 1734 nop 1735 // Disable watchdog for now 1736 movs r1, #0 1737 strh r1, [r0, #0] 1738 1739 b Startup 1740 1741.LWDOG_BASE: 1742 .long 0x40052000 1743end; 1744 1745procedure Vectors; assembler; nostackframe; 1746label interrupt_vectors; 1747asm 1748 .section ".init.interrupt_vectors" 1749 interrupt_vectors: 1750 .long _stack_top 1751 .long LowLevelStartup // int -15 1752 .long NonMaskableInt_interrupt // int -14 1753 .long HardFault_interrupt // int -13 1754 .long MemoryManagement_interrupt // int -12 1755 .long BusFault_interrupt // int -11 1756 .long UsageFault_interrupt // int -10 1757 .long 0 // int -9 1758 .long 0 // int -8 1759 .long 0 // int -7 1760 .long 0 // int -6 1761 .long SVCall_interrupt // int -5 1762 .long DebugMonitor_interrupt // int -4 1763 .long 0 // int -3 1764 .long PendSV_interrupt // int -2 1765 .long SysTick_interrupt // int -1 1766 .long DMA0_interrupt // int 0 1767 .long DMA1_interrupt // int 1 1768 .long DMA2_interrupt // int 2 1769 .long DMA3_interrupt // int 3 1770 .long DMA4_interrupt // int 4 1771 .long DMA5_interrupt // int 5 1772 .long DMA6_interrupt // int 6 1773 .long DMA7_interrupt // int 7 1774 .long DMA8_interrupt // int 8 1775 .long DMA9_interrupt // int 9 1776 .long DMA10_interrupt // int 10 1777 .long DMA11_interrupt // int 11 1778 .long DMA12_interrupt // int 12 1779 .long DMA13_interrupt // int 13 1780 .long DMA14_interrupt // int 14 1781 .long DMA15_interrupt // int 15 1782 .long DMA_Error_interrupt // int 16 1783 .long MCM_interrupt // int 17 1784 .long FTFE_interrupt // int 18 1785 .long Read_Collision_interrupt // int 19 1786 .long LVD_LVW_interrupt // int 20 1787 .long LLWU_interrupt // int 21 1788 .long WDOG_EWM_interrupt // int 22 1789 .long RNG_interrupt // int 23 1790 .long I2C0_interrupt // int 24 1791 .long I2C1_interrupt // int 25 1792 .long SPI0_interrupt // int 26 1793 .long SPI1_interrupt // int 27 1794 .long I2S0_Tx_interrupt // int 28 1795 .long I2S0_Rx_interrupt // int 29 1796 .long UART0_LON_interrupt // int 30 1797 .long UART0_RX_TX_interrupt // int 31 1798 .long UART0_ERR_interrupt // int 32 1799 .long UART1_RX_TX_interrupt // int 33 1800 .long UART1_ERR_interrupt // int 34 1801 .long UART2_RX_TX_interrupt // int 35 1802 .long UART2_ERR_interrupt // int 36 1803 .long UART3_RX_TX_interrupt // int 37 1804 .long UART3_ERR_interrupt // int 38 1805 .long ADC0_interrupt // int 39 1806 .long CMP0_interrupt // int 40 1807 .long CMP1_interrupt // int 41 1808 .long FTM0_interrupt // int 42 1809 .long FTM1_interrupt // int 43 1810 .long FTM2_interrupt // int 44 1811 .long CMT_interrupt // int 45 1812 .long RTC_interrupt // int 46 1813 .long RTC_Seconds_interrupt // int 47 1814 .long PIT0_interrupt // int 48 1815 .long PIT1_interrupt // int 49 1816 .long PIT2_interrupt // int 50 1817 .long PIT3_interrupt // int 51 1818 .long PDB0_interrupt // int 52 1819 .long USB0_interrupt // int 53 1820 .long USBDCD_interrupt // int 54 1821 .long RESERVED71_interrupt // int 55 1822 .long DAC0_interrupt // int 56 1823 .long MCG_interrupt // int 57 1824 .long LPTMR0_interrupt // int 58 1825 .long PORTA_interrupt // int 59 1826 .long PORTB_interrupt // int 60 1827 .long PORTC_interrupt // int 61 1828 .long PORTD_interrupt // int 62 1829 .long PORTE_interrupt // int 63 1830 .long SWI_interrupt // int 64 1831 .long SPI2_interrupt // int 65 1832 .long UART4_RX_TX_interrupt // int 66 1833 .long UART4_ERR_interrupt // int 67 1834 .long UART5_RX_TX_interrupt // int 68 1835 .long UART5_ERR_interrupt // int 69 1836 .long CMP2_interrupt // int 70 1837 .long FTM3_interrupt // int 71 1838 .long DAC1_interrupt // int 72 1839 .long ADC1_interrupt // int 73 1840 .long I2C2_interrupt // int 74 1841 .long CAN0_ORed_Message_buffer_interrupt // int 75 1842 .long CAN0_Bus_Off_interrupt // int 76 1843 .long CAN0_Error_interrupt // int 77 1844 .long CAN0_Tx_Warning_interrupt // int 78 1845 .long CAN0_Rx_Warning_interrupt // int 79 1846 .long CAN0_Wake_Up_interrupt // int 80 1847 .long SDHC_interrupt // int 81 1848 .long ENET_1588_Timer_interrupt // int 82 1849 .long ENET_Transmit_interrupt // int 83 1850 .long ENET_Receive_interrupt // int 84 1851 .long ENET_Error_interrupt // int 85 1852 1853 .weak NonMaskableInt_interrupt 1854 .weak HardFault_interrupt 1855 .weak MemoryManagement_interrupt 1856 .weak BusFault_interrupt 1857 .weak UsageFault_interrupt 1858 .weak SVCall_interrupt 1859 .weak DebugMonitor_interrupt 1860 .weak PendSV_interrupt 1861 .weak SysTick_interrupt 1862 .weak DMA0_interrupt 1863 .weak DMA1_interrupt 1864 .weak DMA2_interrupt 1865 .weak DMA3_interrupt 1866 .weak DMA4_interrupt 1867 .weak DMA5_interrupt 1868 .weak DMA6_interrupt 1869 .weak DMA7_interrupt 1870 .weak DMA8_interrupt 1871 .weak DMA9_interrupt 1872 .weak DMA10_interrupt 1873 .weak DMA11_interrupt 1874 .weak DMA12_interrupt 1875 .weak DMA13_interrupt 1876 .weak DMA14_interrupt 1877 .weak DMA15_interrupt 1878 .weak DMA_Error_interrupt 1879 .weak MCM_interrupt 1880 .weak FTFE_interrupt 1881 .weak Read_Collision_interrupt 1882 .weak LVD_LVW_interrupt 1883 .weak LLWU_interrupt 1884 .weak WDOG_EWM_interrupt 1885 .weak RNG_interrupt 1886 .weak I2C0_interrupt 1887 .weak I2C1_interrupt 1888 .weak SPI0_interrupt 1889 .weak SPI1_interrupt 1890 .weak I2S0_Tx_interrupt 1891 .weak I2S0_Rx_interrupt 1892 .weak UART0_LON_interrupt 1893 .weak UART0_RX_TX_interrupt 1894 .weak UART0_ERR_interrupt 1895 .weak UART1_RX_TX_interrupt 1896 .weak UART1_ERR_interrupt 1897 .weak UART2_RX_TX_interrupt 1898 .weak UART2_ERR_interrupt 1899 .weak UART3_RX_TX_interrupt 1900 .weak UART3_ERR_interrupt 1901 .weak ADC0_interrupt 1902 .weak CMP0_interrupt 1903 .weak CMP1_interrupt 1904 .weak FTM0_interrupt 1905 .weak FTM1_interrupt 1906 .weak FTM2_interrupt 1907 .weak CMT_interrupt 1908 .weak RTC_interrupt 1909 .weak RTC_Seconds_interrupt 1910 .weak PIT0_interrupt 1911 .weak PIT1_interrupt 1912 .weak PIT2_interrupt 1913 .weak PIT3_interrupt 1914 .weak PDB0_interrupt 1915 .weak USB0_interrupt 1916 .weak USBDCD_interrupt 1917 .weak RESERVED71_interrupt 1918 .weak DAC0_interrupt 1919 .weak MCG_interrupt 1920 .weak LPTMR0_interrupt 1921 .weak PORTA_interrupt 1922 .weak PORTB_interrupt 1923 .weak PORTC_interrupt 1924 .weak PORTD_interrupt 1925 .weak PORTE_interrupt 1926 .weak SWI_interrupt 1927 .weak SPI2_interrupt 1928 .weak UART4_RX_TX_interrupt 1929 .weak UART4_ERR_interrupt 1930 .weak UART5_RX_TX_interrupt 1931 .weak UART5_ERR_interrupt 1932 .weak CMP2_interrupt 1933 .weak FTM3_interrupt 1934 .weak DAC1_interrupt 1935 .weak ADC1_interrupt 1936 .weak I2C2_interrupt 1937 .weak CAN0_ORed_Message_buffer_interrupt 1938 .weak CAN0_Bus_Off_interrupt 1939 .weak CAN0_Error_interrupt 1940 .weak CAN0_Tx_Warning_interrupt 1941 .weak CAN0_Rx_Warning_interrupt 1942 .weak CAN0_Wake_Up_interrupt 1943 .weak SDHC_interrupt 1944 .weak ENET_1588_Timer_interrupt 1945 .weak ENET_Transmit_interrupt 1946 .weak ENET_Receive_interrupt 1947 .weak ENET_Error_interrupt 1948 .set NonMaskableInt_interrupt, HaltProc 1949 .set HardFault_interrupt, HaltProc 1950 .set MemoryManagement_interrupt, HaltProc 1951 .set BusFault_interrupt, HaltProc 1952 .set UsageFault_interrupt, HaltProc 1953 .set SVCall_interrupt, HaltProc 1954 .set DebugMonitor_interrupt, HaltProc 1955 .set PendSV_interrupt, HaltProc 1956 .set SysTick_interrupt, HaltProc 1957 .set DMA0_interrupt, HaltProc 1958 .set DMA1_interrupt, HaltProc 1959 .set DMA2_interrupt, HaltProc 1960 .set DMA3_interrupt, HaltProc 1961 .set DMA4_interrupt, HaltProc 1962 .set DMA5_interrupt, HaltProc 1963 .set DMA6_interrupt, HaltProc 1964 .set DMA7_interrupt, HaltProc 1965 .set DMA8_interrupt, HaltProc 1966 .set DMA9_interrupt, HaltProc 1967 .set DMA10_interrupt, HaltProc 1968 .set DMA11_interrupt, HaltProc 1969 .set DMA12_interrupt, HaltProc 1970 .set DMA13_interrupt, HaltProc 1971 .set DMA14_interrupt, HaltProc 1972 .set DMA15_interrupt, HaltProc 1973 .set DMA_Error_interrupt, HaltProc 1974 .set MCM_interrupt, HaltProc 1975 .set FTFE_interrupt, HaltProc 1976 .set Read_Collision_interrupt, HaltProc 1977 .set LVD_LVW_interrupt, HaltProc 1978 .set LLWU_interrupt, HaltProc 1979 .set WDOG_EWM_interrupt, HaltProc 1980 .set RNG_interrupt, HaltProc 1981 .set I2C0_interrupt, HaltProc 1982 .set I2C1_interrupt, HaltProc 1983 .set SPI0_interrupt, HaltProc 1984 .set SPI1_interrupt, HaltProc 1985 .set I2S0_Tx_interrupt, HaltProc 1986 .set I2S0_Rx_interrupt, HaltProc 1987 .set UART0_LON_interrupt, HaltProc 1988 .set UART0_RX_TX_interrupt, HaltProc 1989 .set UART0_ERR_interrupt, HaltProc 1990 .set UART1_RX_TX_interrupt, HaltProc 1991 .set UART1_ERR_interrupt, HaltProc 1992 .set UART2_RX_TX_interrupt, HaltProc 1993 .set UART2_ERR_interrupt, HaltProc 1994 .set UART3_RX_TX_interrupt, HaltProc 1995 .set UART3_ERR_interrupt, HaltProc 1996 .set ADC0_interrupt, HaltProc 1997 .set CMP0_interrupt, HaltProc 1998 .set CMP1_interrupt, HaltProc 1999 .set FTM0_interrupt, HaltProc 2000 .set FTM1_interrupt, HaltProc 2001 .set FTM2_interrupt, HaltProc 2002 .set CMT_interrupt, HaltProc 2003 .set RTC_interrupt, HaltProc 2004 .set RTC_Seconds_interrupt, HaltProc 2005 .set PIT0_interrupt, HaltProc 2006 .set PIT1_interrupt, HaltProc 2007 .set PIT2_interrupt, HaltProc 2008 .set PIT3_interrupt, HaltProc 2009 .set PDB0_interrupt, HaltProc 2010 .set USB0_interrupt, HaltProc 2011 .set USBDCD_interrupt, HaltProc 2012 .set RESERVED71_interrupt, HaltProc 2013 .set DAC0_interrupt, HaltProc 2014 .set MCG_interrupt, HaltProc 2015 .set LPTMR0_interrupt, HaltProc 2016 .set PORTA_interrupt, HaltProc 2017 .set PORTB_interrupt, HaltProc 2018 .set PORTC_interrupt, HaltProc 2019 .set PORTD_interrupt, HaltProc 2020 .set PORTE_interrupt, HaltProc 2021 .set SWI_interrupt, HaltProc 2022 .set SPI2_interrupt, HaltProc 2023 .set UART4_RX_TX_interrupt, HaltProc 2024 .set UART4_ERR_interrupt, HaltProc 2025 .set UART5_RX_TX_interrupt, HaltProc 2026 .set UART5_ERR_interrupt, HaltProc 2027 .set CMP2_interrupt, HaltProc 2028 .set FTM3_interrupt, HaltProc 2029 .set DAC1_interrupt, HaltProc 2030 .set ADC1_interrupt, HaltProc 2031 .set I2C2_interrupt, HaltProc 2032 .set CAN0_ORed_Message_buffer_interrupt, HaltProc 2033 .set CAN0_Bus_Off_interrupt, HaltProc 2034 .set CAN0_Error_interrupt, HaltProc 2035 .set CAN0_Tx_Warning_interrupt, HaltProc 2036 .set CAN0_Rx_Warning_interrupt, HaltProc 2037 .set CAN0_Wake_Up_interrupt, HaltProc 2038 .set SDHC_interrupt, HaltProc 2039 .set ENET_1588_Timer_interrupt, HaltProc 2040 .set ENET_Transmit_interrupt, HaltProc 2041 .set ENET_Receive_interrupt, HaltProc 2042 .set ENET_Error_interrupt, HaltProc 2043 .text 2044end; 2045end. 2046