1{ 2Register definitions and utility code for STM32F756 3 4Created by Jeppe Johansen 2015 - jeppe@j-software.dk 5} 6unit stm32f756; 7 8{$goto on} 9 10interface 11 12{$PACKRECORDS C} 13 14(** 15 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals 16 *) 17 18const 19 __CM7_REV = $0000; (*!< Cortex-M7 revision r0p0 *) 20 __MPU_PRESENT = true; (*!< CM7 provides an MPU *) 21 __NVIC_PRIO_BITS = 4; (*!< CM7 uses 4 Bits for the Priority Levels *) 22 __Vendor_SysTickConfig = 0; (*!< Set to 1 if different SysTick Config is used *) 23 __FPU_PRESENT = true; (*!< FPU present *) 24 CACHE_PRESENT = true; (*!< CM7 instruction cache present *) 25 __DCACHE_PRESENT = true; (*!< CM7 data cache present *) 26 27 28 (** @addtogroup Peripheral_registers_structures 29 * @{ 30 *) 31 32 (** 33 * @brief Analog to Digital Converter 34 *) 35 36type 37 ADC_TypeDef = record 38 SR: longword; (*!< ADC status register, Address offset: 0x00 *) 39 CR1: longword; (*!< ADC control register 1, Address offset: 0x04 *) 40 CR2: longword; (*!< ADC control register 2, Address offset: 0x08 *) 41 SMPR1: longword; (*!< ADC sample time register 1, Address offset: 0x0C *) 42 SMPR2: longword; (*!< ADC sample time register 2, Address offset: 0x10 *) 43 JOFR1: longword; (*!< ADC injected channel data offset register 1, Address offset: 0x14 *) 44 JOFR2: longword; (*!< ADC injected channel data offset register 2, Address offset: 0x18 *) 45 JOFR3: longword; (*!< ADC injected channel data offset register 3, Address offset: 0x1C *) 46 JOFR4: longword; (*!< ADC injected channel data offset register 4, Address offset: 0x20 *) 47 HTR: longword; (*!< ADC watchdog higher threshold register, Address offset: 0x24 *) 48 LTR: longword; (*!< ADC watchdog lower threshold register, Address offset: 0x28 *) 49 SQR1: longword; (*!< ADC regular sequence register 1, Address offset: 0x2C *) 50 SQR2: longword; (*!< ADC regular sequence register 2, Address offset: 0x30 *) 51 SQR3: longword; (*!< ADC regular sequence register 3, Address offset: 0x34 *) 52 JSQR: longword; (*!< ADC injected sequence register, Address offset: 0x38 *) 53 JDR1: longword; (*!< ADC injected data register 1, Address offset: 0x3C *) 54 JDR2: longword; (*!< ADC injected data register 2, Address offset: 0x40 *) 55 JDR3: longword; (*!< ADC injected data register 3, Address offset: 0x44 *) 56 JDR4: longword; (*!< ADC injected data register 4, Address offset: 0x48 *) 57 DR: longword; (*!< ADC regular data register, Address offset: 0x4C *) 58 end; 59 60 ADC_Common_TypeDef = record 61 CSR: longword; (*!< ADC Common status register, Address offset: ADC1 base address + 0x300 *) 62 CCR: longword; (*!< ADC common control register, Address offset: ADC1 base address + 0x304 *) 63 CDR: longword; (*!< ADC common regular data register for dual 64 AND triple modes, Address offset: ADC1 base address + 0x308 *) 65 end; 66 67 68 (** 69 * @brief Controller Area Network TxMailBox 70 *) 71 72 CAN_TxMailBox_TypeDef = record 73 TIR: longword; (*!< CAN TX mailbox identifier register *) 74 TDTR: longword; (*!< CAN mailbox data length control and time stamp register *) 75 TDLR: longword; (*!< CAN mailbox data low register *) 76 TDHR: longword; (*!< CAN mailbox data high register *) 77 end; 78 79 (** 80 * @brief Controller Area Network FIFOMailBox 81 *) 82 83 CAN_FIFOMailBox_TypeDef = record 84 RIR: longword; (*!< CAN receive FIFO mailbox identifier register *) 85 RDTR: longword; (*!< CAN receive FIFO mailbox data length control and time stamp register *) 86 RDLR: longword; (*!< CAN receive FIFO mailbox data low register *) 87 RDHR: longword; (*!< CAN receive FIFO mailbox data high register *) 88 end; 89 90 (** 91 * @brief Controller Area Network FilterRegister 92 *) 93 94 CAN_FilterRegister_TypeDef = record 95 FR1: longword; (*!< CAN Filter bank register 1 *) 96 FR2: longword; (*!< CAN Filter bank register 1 *) 97 end; 98 99 (** 100 * @brief Controller Area Network 101 *) 102 103 CAN_TypeDef = record 104 MCR: longword; (*!< CAN master control register, Address offset: 0x00 *) 105 MSR: longword; (*!< CAN master status register, Address offset: 0x04 *) 106 TSR: longword; (*!< CAN transmit status register, Address offset: 0x08 *) 107 RF0R: longword; (*!< CAN receive FIFO 0 register, Address offset: 0x0C *) 108 RF1R: longword; (*!< CAN receive FIFO 1 register, Address offset: 0x10 *) 109 IER: longword; (*!< CAN interrupt enable register, Address offset: 0x14 *) 110 ESR: longword; (*!< CAN error status register, Address offset: 0x18 *) 111 BTR: longword; (*!< CAN bit timing register, Address offset: 0x1C *) 112 RESERVED0: array [0..87] of longword; (*!< Reserved, 0x020 - 0x17F *) 113 sTxMailBox: array [0..2] of CAN_TxMailBox_TypeDef; (*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC *) 114 sFIFOMailBox: array [0..1] of CAN_FIFOMailBox_TypeDef; (*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC *) 115 RESERVED1: array [0..11] of longword; (*!< Reserved, 0x1D0 - 0x1FF *) 116 FMR: longword; (*!< CAN filter master register, Address offset: 0x200 *) 117 FM1R: longword; (*!< CAN filter mode register, Address offset: 0x204 *) 118 RESERVED2: longword; (*!< Reserved, 0x208 *) 119 FS1R: longword; (*!< CAN filter scale register, Address offset: 0x20C *) 120 RESERVED3: longword; (*!< Reserved, 0x210 *) 121 FFA1R: longword; (*!< CAN filter FIFO assignment register, Address offset: 0x214 *) 122 RESERVED4: longword; (*!< Reserved, 0x218 *) 123 FA1R: longword; (*!< CAN filter activation register, Address offset: 0x21C *) 124 RESERVED5: array [0..7] of longword; (*!< Reserved, 0x220-0x23F *) 125 sFilterRegister: array [0..27] of CAN_FilterRegister_TypeDef; (*!< CAN Filter Register, Address offset: 0x240-0x31C *) 126 end; 127 128 (** 129 * @brief HDMI-CEC 130 *) 131 132 CEC_TypeDef = record 133 CR: longword; (*!< CEC control register, Address offset:0x00 *) 134 CFGR: longword; (*!< CEC configuration register, Address offset:0x04 *) 135 TXDR: longword; (*!< CEC Tx data register , Address offset:0x08 *) 136 RXDR: longword; (*!< CEC Rx Data Register, Address offset:0x0C *) 137 ISR: longword; (*!< CEC Interrupt and Status Register, Address offset:0x10 *) 138 IER: longword; (*!< CEC interrupt enable register, Address offset:0x14 *) 139 end; 140 141 142 (** 143 * @brief CRC calculation unit 144 *) 145 146 CRC_TypeDef = record 147 DR: longword; (*!< CRC Data register, Address offset: 0x00 *) 148 IDR: byte; (*!< CRC Independent data register, Address offset: 0x04 *) 149 RESERVED0: byte; (*!< Reserved, 0x05 *) 150 RESERVED1: word; (*!< Reserved, 0x06 *) 151 CR: longword; (*!< CRC Control register, Address offset: 0x08 *) 152 RESERVED2: longword; (*!< Reserved, 0x0C *) 153 INIT: longword; (*!< Initial CRC value register, Address offset: 0x10 *) 154 POL: longword; (*!< CRC polynomial register, Address offset: 0x14 *) 155 end; 156 157 (** 158 * @brief Digital to Analog Converter 159 *) 160 161 DAC_TypeDef = record 162 CR: longword; (*!< DAC control register, Address offset: 0x00 *) 163 SWTRIGR: longword; (*!< DAC software trigger register, Address offset: 0x04 *) 164 DHR12R1: longword; (*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 *) 165 DHR12L1: longword; (*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C *) 166 DHR8R1: longword; (*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 *) 167 DHR12R2: longword; (*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 *) 168 DHR12L2: longword; (*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 *) 169 DHR8R2: longword; (*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C *) 170 DHR12RD: longword; (*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 *) 171 DHR12LD: longword; (*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 *) 172 DHR8RD: longword; (*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 *) 173 DOR1: longword; (*!< DAC channel1 data output register, Address offset: 0x2C *) 174 DOR2: longword; (*!< DAC channel2 data output register, Address offset: 0x30 *) 175 SR: longword; (*!< DAC status register, Address offset: 0x34 *) 176 end; 177 178 (** 179 * @brief Debug MCU 180 *) 181 182 DBGMCU_TypeDef = record 183 IDCODE: longword; (*!< MCU device ID code, Address offset: 0x00 *) 184 CR: longword; (*!< Debug MCU configuration register, Address offset: 0x04 *) 185 APB1FZ: longword; (*!< Debug MCU APB1 freeze register, Address offset: 0x08 *) 186 APB2FZ: longword; (*!< Debug MCU APB2 freeze register, Address offset: 0x0C *) 187 end; 188 189 (** 190 * @brief DCMI 191 *) 192 193 DCMI_TypeDef = record 194 CR: longword; (*!< DCMI control register 1, Address offset: 0x00 *) 195 SR: longword; (*!< DCMI status register, Address offset: 0x04 *) 196 RISR: longword; (*!< DCMI raw interrupt status register, Address offset: 0x08 *) 197 IER: longword; (*!< DCMI interrupt enable register, Address offset: 0x0C *) 198 MISR: longword; (*!< DCMI masked interrupt status register, Address offset: 0x10 *) 199 ICR: longword; (*!< DCMI interrupt clear register, Address offset: 0x14 *) 200 ESCR: longword; (*!< DCMI embedded synchronization code register, Address offset: 0x18 *) 201 ESUR: longword; (*!< DCMI embedded synchronization unmask register, Address offset: 0x1C *) 202 CWSTRTR: longword; (*!< DCMI crop window start, Address offset: 0x20 *) 203 CWSIZER: longword; (*!< DCMI crop window size, Address offset: 0x24 *) 204 DR: longword; (*!< DCMI data register, Address offset: 0x28 *) 205 end; 206 207 (** 208 * @brief DMA Controller 209 *) 210 211 DMA_Stream_TypeDef = record 212 CR: longword; (*!< DMA stream x configuration register *) 213 NDTR: longword; (*!< DMA stream x number of data register *) 214 PAR: longword; (*!< DMA stream x peripheral address register *) 215 M0AR: longword; (*!< DMA stream x memory 0 address register *) 216 M1AR: longword; (*!< DMA stream x memory 1 address register *) 217 FCR: longword; (*!< DMA stream x FIFO control register *) 218 end; 219 220 DMA_TypeDef = record 221 LISR: longword; (*!< DMA low interrupt status register, Address offset: 0x00 *) 222 HISR: longword; (*!< DMA high interrupt status register, Address offset: 0x04 *) 223 LIFCR: longword; (*!< DMA low interrupt flag clear register, Address offset: 0x08 *) 224 HIFCR: longword; (*!< DMA high interrupt flag clear register, Address offset: 0x0C *) 225 end; 226 227 228 (** 229 * @brief DMA2D Controller 230 *) 231 232 DMA2D_TypeDef = record 233 CR: longword; (*!< DMA2D Control Register, Address offset: 0x00 *) 234 ISR: longword; (*!< DMA2D Interrupt Status Register, Address offset: 0x04 *) 235 IFCR: longword; (*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 *) 236 FGMAR: longword; (*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C *) 237 FGOR: longword; (*!< DMA2D Foreground Offset Register, Address offset: 0x10 *) 238 BGMAR: longword; (*!< DMA2D Background Memory Address Register, Address offset: 0x14 *) 239 BGOR: longword; (*!< DMA2D Background Offset Register, Address offset: 0x18 *) 240 FGPFCCR: longword; (*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C *) 241 FGCOLR: longword; (*!< DMA2D Foreground Color Register, Address offset: 0x20 *) 242 BGPFCCR: longword; (*!< DMA2D Background PFC Control Register, Address offset: 0x24 *) 243 BGCOLR: longword; (*!< DMA2D Background Color Register, Address offset: 0x28 *) 244 FGCMAR: longword; (*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C *) 245 BGCMAR: longword; (*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 *) 246 OPFCCR: longword; (*!< DMA2D Output PFC Control Register, Address offset: 0x34 *) 247 OCOLR: longword; (*!< DMA2D Output Color Register, Address offset: 0x38 *) 248 OMAR: longword; (*!< DMA2D Output Memory Address Register, Address offset: 0x3C *) 249 OOR: longword; (*!< DMA2D Output Offset Register, Address offset: 0x40 *) 250 NLR: longword; (*!< DMA2D Number of Line Register, Address offset: 0x44 *) 251 LWR: longword; (*!< DMA2D Line Watermark Register, Address offset: 0x48 *) 252 AMTCR: longword; (*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C *) 253 RESERVED: array [0..235] of longword; (*!< Reserved, 0x50-0x3FF *) 254 FGCLUT: array [0..255] of longword; (*!< DMA2D Foreground CLUT, Address offset:400-7FF *) 255 BGCLUT: array [0..255] of longword; (*!< DMA2D Background CLUT, Address offset:800-BFF *) 256 end; 257 258 259 (** 260 * @brief Ethernet MAC 261 *) 262 263 ETH_TypeDef = record 264 MACCR: longword; 265 MACFFR: longword; 266 MACHTHR: longword; 267 MACHTLR: longword; 268 MACMIIAR: longword; 269 MACMIIDR: longword; 270 MACFCR: longword; 271 MACVLANTR: longword; (* 8 *) 272 RESERVED0: array [0..1] of longword; 273 MACRWUFFR: longword; (* 11 *) 274 MACPMTCSR: longword; 275 RESERVED1: array [0..1] of longword; 276 MACSR: longword; (* 15 *) 277 MACIMR: longword; 278 MACA0HR: longword; 279 MACA0LR: longword; 280 MACA1HR: longword; 281 MACA1LR: longword; 282 MACA2HR: longword; 283 MACA2LR: longword; 284 MACA3HR: longword; 285 MACA3LR: longword; (* 24 *) 286 RESERVED2: array [0..39] of longword; 287 MMCCR: longword; (* 65 *) 288 MMCRIR: longword; 289 MMCTIR: longword; 290 MMCRIMR: longword; 291 MMCTIMR: longword; (* 69 *) 292 RESERVED3: array [0..13] of longword; 293 MMCTGFSCCR: longword; (* 84 *) 294 MMCTGFMSCCR: longword; 295 RESERVED4: array [0..4] of longword; 296 MMCTGFCR: longword; 297 RESERVED5: array [0..9] of longword; 298 MMCRFCECR: longword; 299 MMCRFAECR: longword; 300 RESERVED6: array [0..9] of longword; 301 MMCRGUFCR: longword; 302 RESERVED7: array [0..333] of longword; 303 PTPTSCR: longword; 304 PTPSSIR: longword; 305 PTPTSHR: longword; 306 PTPTSLR: longword; 307 PTPTSHUR: longword; 308 PTPTSLUR: longword; 309 PTPTSAR: longword; 310 PTPTTHR: longword; 311 PTPTTLR: longword; 312 RESERVED8: longword; 313 PTPTSSR: longword; 314 RESERVED9: array [0..564] of longword; 315 DMABMR: longword; 316 DMATPDR: longword; 317 DMARPDR: longword; 318 DMARDLAR: longword; 319 DMATDLAR: longword; 320 DMASR: longword; 321 DMAOMR: longword; 322 DMAIER: longword; 323 DMAMFBOCR: longword; 324 DMARSWTR: longword; 325 RESERVED10: array [0..7] of longword; 326 DMACHTDR: longword; 327 DMACHRDR: longword; 328 DMACHTBAR: longword; 329 DMACHRBAR: longword; 330 end; 331 332 (** 333 * @brief External Interrupt/Event Controller 334 *) 335 336 EXTI_TypeDef = record 337 IMR: longword; (*!< EXTI Interrupt mask register, Address offset: 0x00 *) 338 EMR: longword; (*!< EXTI Event mask register, Address offset: 0x04 *) 339 RTSR: longword; (*!< EXTI Rising trigger selection register, Address offset: 0x08 *) 340 FTSR: longword; (*!< EXTI Falling trigger selection register, Address offset: 0x0C *) 341 SWIER: longword; (*!< EXTI Software interrupt event register, Address offset: 0x10 *) 342 PR: longword; (*!< EXTI Pending register, Address offset: 0x14 *) 343 end; 344 345 (** 346 * @brief FLASH Registers 347 *) 348 349 FLASH_TypeDef = record 350 ACR: longword; (*!< FLASH access control register, Address offset: 0x00 *) 351 KEYR: longword; (*!< FLASH key register, Address offset: 0x04 *) 352 OPTKEYR: longword; (*!< FLASH option key register, Address offset: 0x08 *) 353 SR: longword; (*!< FLASH status register, Address offset: 0x0C *) 354 CR: longword; (*!< FLASH control register, Address offset: 0x10 *) 355 OPTCR: longword; (*!< FLASH option control register , Address offset: 0x14 *) 356 OPTCR1: longword; (*!< FLASH option control register 1 , Address offset: 0x18 *) 357 end; 358 359 360 (** 361 * @brief Flexible Memory Controller 362 *) 363 364 FMC_Bank1_TypeDef = record 365 BTCR: array [0..7] of longword; (*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C *) 366 end; 367 368 (** 369 * @brief Flexible Memory Controller Bank1E 370 *) 371 372 FMC_Bank1E_TypeDef = record 373 BWTR: array [0..6] of longword; (*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C *) 374 end; 375 376 (** 377 * @brief Flexible Memory Controller Bank3 378 *) 379 380 FMC_Bank3_TypeDef = record 381 PCR: longword; (*!< NAND Flash control register, Address offset: 0x80 *) 382 SR: longword; (*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 *) 383 PMEM: longword; (*!< NAND Flash Common memory space timing register, Address offset: 0x88 *) 384 PATT: longword; (*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C *) 385 RESERVED0: longword; (*!< Reserved, 0x90 *) 386 ECCR: longword; (*!< NAND Flash ECC result registers, Address offset: 0x94 *) 387 end; 388 389 (** 390 * @brief Flexible Memory Controller Bank5_6 391 *) 392 393 FMC_Bank5_6_TypeDef = record 394 SDCR: array [0..1] of longword; (*!< SDRAM Control registers , Address offset: 0x140-0x144 *) 395 SDTR: array [0..1] of longword; (*!< SDRAM Timing registers , Address offset: 0x148-0x14C *) 396 SDCMR: longword; (*!< SDRAM Command Mode register, Address offset: 0x150 *) 397 SDRTR: longword; (*!< SDRAM Refresh Timer register, Address offset: 0x154 *) 398 SDSR: longword; (*!< SDRAM Status register, Address offset: 0x158 *) 399 end; 400 401 402 (** 403 * @brief General Purpose I/O 404 *) 405 406 GPIO_TypeDef = record 407 MODER: longword; (*!< GPIO port mode register, Address offset: 0x00 *) 408 OTYPER: longword; (*!< GPIO port output type register, Address offset: 0x04 *) 409 OSPEEDR: longword; (*!< GPIO port output speed register, Address offset: 0x08 *) 410 PUPDR: longword; (*!< GPIO port pull-up/pull-down register, Address offset: 0x0C *) 411 IDR: longword; (*!< GPIO port input data register, Address offset: 0x10 *) 412 ODR: longword; (*!< GPIO port output data register, Address offset: 0x14 *) 413 BSRR: longword; (*!< GPIO port bit set/reset register, Address offset: 0x18 *) 414 LCKR: longword; (*!< GPIO port configuration lock register, Address offset: 0x1C *) 415 AFR: array [0..1] of longword; (*!< GPIO alternate function registers, Address offset: 0x20-0x24 *) 416 end; 417 418 (** 419 * @brief System configuration controller 420 *) 421 422 SYSCFG_TypeDef = record 423 MEMRMP: longword; (*!< SYSCFG memory remap register, Address offset: 0x00 *) 424 PMC: longword; (*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 *) 425 EXTICR: array [0..3] of longword; (*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 *) 426 RESERVED: array [0..1] of longword; (*!< Reserved, 0x18-0x1C *) 427 CMPCR: longword; (*!< SYSCFG Compensation cell control register, Address offset: 0x20 *) 428 end; 429 430 (** 431 * @brief Inter-integrated Circuit Interface 432 *) 433 434 I2C_TypeDef = record 435 CR1: longword; (*!< I2C Control register 1, Address offset: 0x00 *) 436 CR2: longword; (*!< I2C Control register 2, Address offset: 0x04 *) 437 OAR1: longword; (*!< I2C Own address 1 register, Address offset: 0x08 *) 438 OAR2: longword; (*!< I2C Own address 2 register, Address offset: 0x0C *) 439 TIMINGR: longword; (*!< I2C Timing register, Address offset: 0x10 *) 440 TIMEOUTR: longword; (*!< I2C Timeout register, Address offset: 0x14 *) 441 ISR: longword; (*!< I2C Interrupt and status register, Address offset: 0x18 *) 442 ICR: longword; (*!< I2C Interrupt clear register, Address offset: 0x1C *) 443 PECR: longword; (*!< I2C PEC register, Address offset: 0x20 *) 444 RXDR: longword; (*!< I2C Receive data register, Address offset: 0x24 *) 445 TXDR: longword; (*!< I2C Transmit data register, Address offset: 0x28 *) 446 end; 447 448 (** 449 * @brief Independent WATCHDOG 450 *) 451 452 IWDG_TypeDef = record 453 KR: longword; (*!< IWDG Key register, Address offset: 0x00 *) 454 PR: longword; (*!< IWDG Prescaler register, Address offset: 0x04 *) 455 RLR: longword; (*!< IWDG Reload register, Address offset: 0x08 *) 456 SR: longword; (*!< IWDG Status register, Address offset: 0x0C *) 457 WINR: longword; (*!< IWDG Window register, Address offset: 0x10 *) 458 end; 459 460 461 (** 462 * @brief LCD-TFT Display Controller 463 *) 464 465 LTDC_TypeDef = record 466 RESERVED0: array [0..1] of longword; (*!< Reserved, 0x00-0x04 *) 467 SSCR: longword; (*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 *) 468 BPCR: longword; (*!< LTDC Back Porch Configuration Register, Address offset: 0x0C *) 469 AWCR: longword; (*!< LTDC Active Width Configuration Register, Address offset: 0x10 *) 470 TWCR: longword; (*!< LTDC Total Width Configuration Register, Address offset: 0x14 *) 471 GCR: longword; (*!< LTDC Global Control Register, Address offset: 0x18 *) 472 RESERVED1: array [0..1] of longword; (*!< Reserved, 0x1C-0x20 *) 473 SRCR: longword; (*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 *) 474 RESERVED2: array [0..0] of longword; (*!< Reserved, 0x28 *) 475 BCCR: longword; (*!< LTDC Background Color Configuration Register, Address offset: 0x2C *) 476 RESERVED3: array [0..0] of longword; (*!< Reserved, 0x30 *) 477 IER: longword; (*!< LTDC Interrupt Enable Register, Address offset: 0x34 *) 478 ISR: longword; (*!< LTDC Interrupt Status Register, Address offset: 0x38 *) 479 ICR: longword; (*!< LTDC Interrupt Clear Register, Address offset: 0x3C *) 480 LIPCR: longword; (*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 *) 481 CPSR: longword; (*!< LTDC Current Position Status Register, Address offset: 0x44 *) 482 CDSR: longword; (*!< LTDC Current Display Status Register, Address offset: 0x48 *) 483 end; 484 485 (** 486 * @brief LCD-TFT Display layer x Controller 487 *) 488 489 LTDC_Layer_TypeDef = record 490 CR: longword; (*!< LTDC Layerx Control Register Address offset: 0x84 *) 491 WHPCR: longword; (*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 *) 492 WVPCR: longword; (*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C *) 493 CKCR: longword; (*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 *) 494 PFCR: longword; (*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 *) 495 CACR: longword; (*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 *) 496 DCCR: longword; (*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C *) 497 BFCR: longword; (*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 *) 498 RESERVED0: array [0..1] of longword; (*!< Reserved *) 499 CFBAR: longword; (*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC *) 500 CFBLR: longword; (*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 *) 501 CFBLNR: longword; (*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 *) 502 RESERVED1: array [0..2] of longword; (*!< Reserved *) 503 CLUTWR: longword; (*!< LTDC Layerx CLUT Write Register Address offset: 0x144 *) 504 end; 505 506 507 (** 508 * @brief Power Control 509 *) 510 511 PWR_TypeDef = record 512 CR1: longword; (*!< PWR power control register 1, Address offset: 0x00 *) 513 CSR1: longword; (*!< PWR power control/status register 2, Address offset: 0x04 *) 514 CR2: longword; (*!< PWR power control register 2, Address offset: 0x08 *) 515 CSR2: longword; (*!< PWR power control/status register 2, Address offset: 0x0C *) 516 end; 517 518 519 (** 520 * @brief Reset and Clock Control 521 *) 522 523 RCC_TypeDef = record 524 CR: longword; (*!< RCC clock control register, Address offset: 0x00 *) 525 PLLCFGR: longword; (*!< RCC PLL configuration register, Address offset: 0x04 *) 526 CFGR: longword; (*!< RCC clock configuration register, Address offset: 0x08 *) 527 CIR: longword; (*!< RCC clock interrupt register, Address offset: 0x0C *) 528 AHB1RSTR: longword; (*!< RCC AHB1 peripheral reset register, Address offset: 0x10 *) 529 AHB2RSTR: longword; (*!< RCC AHB2 peripheral reset register, Address offset: 0x14 *) 530 AHB3RSTR: longword; (*!< RCC AHB3 peripheral reset register, Address offset: 0x18 *) 531 RESERVED0: longword; (*!< Reserved, 0x1C *) 532 APB1RSTR: longword; (*!< RCC APB1 peripheral reset register, Address offset: 0x20 *) 533 APB2RSTR: longword; (*!< RCC APB2 peripheral reset register, Address offset: 0x24 *) 534 RESERVED1: array [0..1] of longword; (*!< Reserved, 0x28-0x2C *) 535 AHB1ENR: longword; (*!< RCC AHB1 peripheral clock register, Address offset: 0x30 *) 536 AHB2ENR: longword; (*!< RCC AHB2 peripheral clock register, Address offset: 0x34 *) 537 AHB3ENR: longword; (*!< RCC AHB3 peripheral clock register, Address offset: 0x38 *) 538 RESERVED2: longword; (*!< Reserved, 0x3C *) 539 APB1ENR: longword; (*!< RCC APB1 peripheral clock enable register, Address offset: 0x40 *) 540 APB2ENR: longword; (*!< RCC APB2 peripheral clock enable register, Address offset: 0x44 *) 541 RESERVED3: array [0..1] of longword; (*!< Reserved, 0x48-0x4C *) 542 AHB1LPENR: longword; (*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 *) 543 AHB2LPENR: longword; (*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 *) 544 AHB3LPENR: longword; (*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 *) 545 RESERVED4: longword; (*!< Reserved, 0x5C *) 546 APB1LPENR: longword; (*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 *) 547 APB2LPENR: longword; (*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 *) 548 RESERVED5: array [0..1] of longword; (*!< Reserved, 0x68-0x6C *) 549 BDCR: longword; (*!< RCC Backup domain control register, Address offset: 0x70 *) 550 CSR: longword; (*!< RCC clock control & status register, Address offset: 0x74 *) 551 RESERVED6: array [0..1] of longword; (*!< Reserved, 0x78-0x7C *) 552 SSCGR: longword; (*!< RCC spread spectrum clock generation register, Address offset: 0x80 *) 553 PLLI2SCFGR: longword; (*!< RCC PLLI2S configuration register, Address offset: 0x84 *) 554 PLLSAICFGR: longword; (*!< RCC PLLSAI configuration register, Address offset: 0x88 *) 555 DCKCFGR1: longword; (*!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C *) 556 DCKCFGR2: longword; (*!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 *) 557 end; 558 559 (** 560 * @brief Real-Time Clock 561 *) 562 563 RTC_TypeDef = record 564 TR: longword; (*!< RTC time register, Address offset: 0x00 *) 565 DR: longword; (*!< RTC date register, Address offset: 0x04 *) 566 CR: longword; (*!< RTC control register, Address offset: 0x08 *) 567 ISR: longword; (*!< RTC initialization and status register, Address offset: 0x0C *) 568 PRER: longword; (*!< RTC prescaler register, Address offset: 0x10 *) 569 WUTR: longword; (*!< RTC wakeup timer register, Address offset: 0x14 *) 570 reserved: longword; (*!< Reserved *) 571 ALRMAR: longword; (*!< RTC alarm A register, Address offset: 0x1C *) 572 ALRMBR: longword; (*!< RTC alarm B register, Address offset: 0x20 *) 573 WPR: longword; (*!< RTC write protection register, Address offset: 0x24 *) 574 SSR: longword; (*!< RTC sub second register, Address offset: 0x28 *) 575 SHIFTR: longword; (*!< RTC shift control register, Address offset: 0x2C *) 576 TSTR: longword; (*!< RTC time stamp time register, Address offset: 0x30 *) 577 TSDR: longword; (*!< RTC time stamp date register, Address offset: 0x34 *) 578 TSSSR: longword; (*!< RTC time-stamp sub second register, Address offset: 0x38 *) 579 CALR: longword; (*!< RTC calibration register, Address offset: 0x3C *) 580 TAMPCR: longword; (*!< RTC tamper configuration register, Address offset: 0x40 *) 581 ALRMASSR: longword; (*!< RTC alarm A sub second register, Address offset: 0x44 *) 582 ALRMBSSR: longword; (*!< RTC alarm B sub second register, Address offset: 0x48 *) 583 OR_: longword; (*!< RTC option register, Address offset: 0x4C *) 584 BKP0R: longword; (*!< RTC backup register 0, Address offset: 0x50 *) 585 BKP1R: longword; (*!< RTC backup register 1, Address offset: 0x54 *) 586 BKP2R: longword; (*!< RTC backup register 2, Address offset: 0x58 *) 587 BKP3R: longword; (*!< RTC backup register 3, Address offset: 0x5C *) 588 BKP4R: longword; (*!< RTC backup register 4, Address offset: 0x60 *) 589 BKP5R: longword; (*!< RTC backup register 5, Address offset: 0x64 *) 590 BKP6R: longword; (*!< RTC backup register 6, Address offset: 0x68 *) 591 BKP7R: longword; (*!< RTC backup register 7, Address offset: 0x6C *) 592 BKP8R: longword; (*!< RTC backup register 8, Address offset: 0x70 *) 593 BKP9R: longword; (*!< RTC backup register 9, Address offset: 0x74 *) 594 BKP10R: longword; (*!< RTC backup register 10, Address offset: 0x78 *) 595 BKP11R: longword; (*!< RTC backup register 11, Address offset: 0x7C *) 596 BKP12R: longword; (*!< RTC backup register 12, Address offset: 0x80 *) 597 BKP13R: longword; (*!< RTC backup register 13, Address offset: 0x84 *) 598 BKP14R: longword; (*!< RTC backup register 14, Address offset: 0x88 *) 599 BKP15R: longword; (*!< RTC backup register 15, Address offset: 0x8C *) 600 BKP16R: longword; (*!< RTC backup register 16, Address offset: 0x90 *) 601 BKP17R: longword; (*!< RTC backup register 17, Address offset: 0x94 *) 602 BKP18R: longword; (*!< RTC backup register 18, Address offset: 0x98 *) 603 BKP19R: longword; (*!< RTC backup register 19, Address offset: 0x9C *) 604 BKP20R: longword; (*!< RTC backup register 20, Address offset: 0xA0 *) 605 BKP21R: longword; (*!< RTC backup register 21, Address offset: 0xA4 *) 606 BKP22R: longword; (*!< RTC backup register 22, Address offset: 0xA8 *) 607 BKP23R: longword; (*!< RTC backup register 23, Address offset: 0xAC *) 608 BKP24R: longword; (*!< RTC backup register 24, Address offset: 0xB0 *) 609 BKP25R: longword; (*!< RTC backup register 25, Address offset: 0xB4 *) 610 BKP26R: longword; (*!< RTC backup register 26, Address offset: 0xB8 *) 611 BKP27R: longword; (*!< RTC backup register 27, Address offset: 0xBC *) 612 BKP28R: longword; (*!< RTC backup register 28, Address offset: 0xC0 *) 613 BKP29R: longword; (*!< RTC backup register 29, Address offset: 0xC4 *) 614 BKP30R: longword; (*!< RTC backup register 30, Address offset: 0xC8 *) 615 BKP31R: longword; (*!< RTC backup register 31, Address offset: 0xCC *) 616 end; 617 618 619 (** 620 * @brief Serial Audio Interface 621 *) 622 623 SAI_TypeDef = record 624 GCR: longword; (*!< SAI global configuration register, Address offset: 0x00 *) 625 end; 626 627 SAI_Block_TypeDef = record 628 CR1: longword; (*!< SAI block x configuration register 1, Address offset: 0x04 *) 629 CR2: longword; (*!< SAI block x configuration register 2, Address offset: 0x08 *) 630 FRCR: longword; (*!< SAI block x frame configuration register, Address offset: 0x0C *) 631 SLOTR: longword; (*!< SAI block x slot register, Address offset: 0x10 *) 632 IMR: longword; (*!< SAI block x interrupt mask register, Address offset: 0x14 *) 633 SR: longword; (*!< SAI block x status register, Address offset: 0x18 *) 634 CLRFR: longword; (*!< SAI block x clear flag register, Address offset: 0x1C *) 635 DR: longword; (*!< SAI block x data register, Address offset: 0x20 *) 636 end; 637 638 (** 639 * @brief SPDIF-RX Interface 640 *) 641 642 SPDIFRX_TypeDef = record 643 CR: longword; (*!< Control register, Address offset: 0x00 *) 644 IMR: longword; (*!< Interrupt mask register, Address offset: 0x04 *) 645 SR: longword; (*!< Status register, Address offset: 0x08 *) 646 IFCR: longword; (*!< Interrupt Flag Clear register, Address offset: 0x0C *) 647 DR: longword; (*!< Data input register, Address offset: 0x10 *) 648 CSR: longword; (*!< Channel Status register, Address offset: 0x14 *) 649 DIR: longword; (*!< Debug Information register, Address offset: 0x18 *) 650 end; 651 652 653 (** 654 * @brief SD host Interface 655 *) 656 657 SDMMC_TypeDef = record 658 POWER: longword; (*!< SDMMC power control register, Address offset: 0x00 *) 659 CLKCR: longword; (*!< SDMMClock control register, Address offset: 0x04 *) 660 ARG: longword; (*!< SDMMC argument register, Address offset: 0x08 *) 661 CMD: longword; (*!< SDMMC command register, Address offset: 0x0C *) 662 RESPCMD: longword; (*!< SDMMC command response register, Address offset: 0x10 *) 663 RESP1: longword; (*!< SDMMC response 1 register, Address offset: 0x14 *) 664 RESP2: longword; (*!< SDMMC response 2 register, Address offset: 0x18 *) 665 RESP3: longword; (*!< SDMMC response 3 register, Address offset: 0x1C *) 666 RESP4: longword; (*!< SDMMC response 4 register, Address offset: 0x20 *) 667 DTIMER: longword; (*!< SDMMC data timer register, Address offset: 0x24 *) 668 DLEN: longword; (*!< SDMMC data length register, Address offset: 0x28 *) 669 DCTRL: longword; (*!< SDMMC data control register, Address offset: 0x2C *) 670 DCOUNT: longword; (*!< SDMMC data counter register, Address offset: 0x30 *) 671 STA: longword; (*!< SDMMC status register, Address offset: 0x34 *) 672 ICR: longword; (*!< SDMMC interrupt clear register, Address offset: 0x38 *) 673 MASK: longword; (*!< SDMMC mask register, Address offset: 0x3C *) 674 RESERVED0: array [0..1] of longword; (*!< Reserved, 0x40-0x44 *) 675 FIFOCNT: longword; (*!< SDMMC FIFO counter register, Address offset: 0x48 *) 676 RESERVED1: array [0..12] of longword; (*!< Reserved, 0x4C-0x7C *) 677 FIFO: longword; (*!< SDMMC data FIFO register, Address offset: 0x80 *) 678 end; 679 680 (** 681 * @brief Serial Peripheral Interface 682 *) 683 684 SPI_TypeDef = record 685 CR1: longword; (*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 *) 686 CR2: longword; (*!< SPI control register 2, Address offset: 0x04 *) 687 SR: longword; (*!< SPI status register, Address offset: 0x08 *) 688 DR: longword; (*!< SPI data register, Address offset: 0x0C *) 689 CRCPR: longword; (*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 *) 690 RXCRCR: longword; (*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 *) 691 TXCRCR: longword; (*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 *) 692 I2SCFGR: longword; (*!< SPI_I2S configuration register, Address offset: 0x1C *) 693 I2SPR: longword; (*!< SPI_I2S prescaler register, Address offset: 0x20 *) 694 end; 695 696 (** 697 * @brief QUAD Serial Peripheral Interface 698 *) 699 700 QUADSPI_TypeDef = record 701 CR: longword; (*!< QUADSPI Control register, Address offset: 0x00 *) 702 DCR: longword; (*!< QUADSPI Device Configuration register, Address offset: 0x04 *) 703 SR: longword; (*!< QUADSPI Status register, Address offset: 0x08 *) 704 FCR: longword; (*!< QUADSPI Flag Clear register, Address offset: 0x0C *) 705 DLR: longword; (*!< QUADSPI Data Length register, Address offset: 0x10 *) 706 CCR: longword; (*!< QUADSPI Communication Configuration register, Address offset: 0x14 *) 707 AR: longword; (*!< QUADSPI Address register, Address offset: 0x18 *) 708 ABR: longword; (*!< QUADSPI Alternate Bytes register, Address offset: 0x1C *) 709 DR: longword; (*!< QUADSPI Data register, Address offset: 0x20 *) 710 PSMKR: longword; (*!< QUADSPI Polling Status Mask register, Address offset: 0x24 *) 711 PSMAR: longword; (*!< QUADSPI Polling Status Match register, Address offset: 0x28 *) 712 PIR: longword; (*!< QUADSPI Polling Interval register, Address offset: 0x2C *) 713 LPTR: longword; (*!< QUADSPI Low Power Timeout register, Address offset: 0x30 *) 714 end; 715 716 (** 717 * @brief TIM 718 *) 719 720 TIM_TypeDef = record 721 CR1: longword; (*!< TIM control register 1, Address offset: 0x00 *) 722 CR2: longword; (*!< TIM control register 2, Address offset: 0x04 *) 723 SMCR: longword; (*!< TIM slave mode control register, Address offset: 0x08 *) 724 DIER: longword; (*!< TIM DMA/interrupt enable register, Address offset: 0x0C *) 725 SR: longword; (*!< TIM status register, Address offset: 0x10 *) 726 EGR: longword; (*!< TIM event generation register, Address offset: 0x14 *) 727 CCMR1: longword; (*!< TIM capture/compare mode register 1, Address offset: 0x18 *) 728 CCMR2: longword; (*!< TIM capture/compare mode register 2, Address offset: 0x1C *) 729 CCER: longword; (*!< TIM capture/compare enable register, Address offset: 0x20 *) 730 CNT: longword; (*!< TIM counter register, Address offset: 0x24 *) 731 PSC: longword; (*!< TIM prescaler, Address offset: 0x28 *) 732 ARR: longword; (*!< TIM auto-reload register, Address offset: 0x2C *) 733 RCR: longword; (*!< TIM repetition counter register, Address offset: 0x30 *) 734 CCR1: longword; (*!< TIM capture/compare register 1, Address offset: 0x34 *) 735 CCR2: longword; (*!< TIM capture/compare register 2, Address offset: 0x38 *) 736 CCR3: longword; (*!< TIM capture/compare register 3, Address offset: 0x3C *) 737 CCR4: longword; (*!< TIM capture/compare register 4, Address offset: 0x40 *) 738 BDTR: longword; (*!< TIM break and dead-time register, Address offset: 0x44 *) 739 DCR: longword; (*!< TIM DMA control register, Address offset: 0x48 *) 740 DMAR: longword; (*!< TIM DMA address for full transfer, Address offset: 0x4C *) 741 OR_: longword; (*!< TIM option register, Address offset: 0x50 *) 742 CCMR3: longword; (*!< TIM capture/compare mode register 3, Address offset: 0x54 *) 743 CCR5: longword; (*!< TIM capture/compare mode register5, Address offset: 0x58 *) 744 CCR6: longword; (*!< TIM capture/compare mode register6, Address offset: 0x5C *) 745 end; 746 747 (** 748 * @brief LPTIMIMER 749 *) 750 751 LPTIM_TypeDef = record 752 ISR: longword; (*!< LPTIM Interrupt and Status register, Address offset: 0x00 *) 753 ICR: longword; (*!< LPTIM Interrupt Clear register, Address offset: 0x04 *) 754 IER: longword; (*!< LPTIM Interrupt Enable register, Address offset: 0x08 *) 755 CFGR: longword; (*!< LPTIM Configuration register, Address offset: 0x0C *) 756 CR: longword; (*!< LPTIM Control register, Address offset: 0x10 *) 757 CMP: longword; (*!< LPTIM Compare register, Address offset: 0x14 *) 758 ARR: longword; (*!< LPTIM Autoreload register, Address offset: 0x18 *) 759 CNT: longword; (*!< LPTIM Counter register, Address offset: 0x1C *) 760 OR_: longword; (*!< LPTIM Option register, Address offset: 0x20 *) 761 end; 762 763 764 (** 765 * @brief Universal Synchronous Asynchronous Receiver Transmitter 766 *) 767 768 USART_TypeDef = record 769 CR1: longword; (*!< USART Control register 1, Address offset: 0x00 *) 770 CR2: longword; (*!< USART Control register 2, Address offset: 0x04 *) 771 CR3: longword; (*!< USART Control register 3, Address offset: 0x08 *) 772 BRR: longword; (*!< USART Baud rate register, Address offset: 0x0C *) 773 GTPR: longword; (*!< USART Guard time and prescaler register, Address offset: 0x10 *) 774 RTOR: longword; (*!< USART Receiver Time Out register, Address offset: 0x14 *) 775 RQR: longword; (*!< USART Request register, Address offset: 0x18 *) 776 ISR: longword; (*!< USART Interrupt and status register, Address offset: 0x1C *) 777 ICR: longword; (*!< USART Interrupt flag Clear register, Address offset: 0x20 *) 778 RDR: longword; (*!< USART Receive Data register, Address offset: 0x24 *) 779 TDR: longword; (*!< USART Transmit Data register, Address offset: 0x28 *) 780 end; 781 782 783 (** 784 * @brief Window WATCHDOG 785 *) 786 787 WWDG_TypeDef = record 788 CR: longword; (*!< WWDG Control register, Address offset: 0x00 *) 789 CFR: longword; (*!< WWDG Configuration register, Address offset: 0x04 *) 790 SR: longword; (*!< WWDG Status register, Address offset: 0x08 *) 791 end; 792 793 (** 794 * @brief Crypto Processor 795 *) 796 797 CRYP_TypeDef = record 798 CR: longword; (*!< CRYP control register, Address offset: 0x00 *) 799 SR: longword; (*!< CRYP status register, Address offset: 0x04 *) 800 DR: longword; (*!< CRYP data input register, Address offset: 0x08 *) 801 DOUT: longword; (*!< CRYP data output register, Address offset: 0x0C *) 802 DMACR: longword; (*!< CRYP DMA control register, Address offset: 0x10 *) 803 IMSCR: longword; (*!< CRYP interrupt mask set/clear register, Address offset: 0x14 *) 804 RISR: longword; (*!< CRYP raw interrupt status register, Address offset: 0x18 *) 805 MISR: longword; (*!< CRYP masked interrupt status register, Address offset: 0x1C *) 806 K0LR: longword; (*!< CRYP key left register 0, Address offset: 0x20 *) 807 K0RR: longword; (*!< CRYP key right register 0, Address offset: 0x24 *) 808 K1LR: longword; (*!< CRYP key left register 1, Address offset: 0x28 *) 809 K1RR: longword; (*!< CRYP key right register 1, Address offset: 0x2C *) 810 K2LR: longword; (*!< CRYP key left register 2, Address offset: 0x30 *) 811 K2RR: longword; (*!< CRYP key right register 2, Address offset: 0x34 *) 812 K3LR: longword; (*!< CRYP key left register 3, Address offset: 0x38 *) 813 K3RR: longword; (*!< CRYP key right register 3, Address offset: 0x3C *) 814 IV0LR: longword; (*!< CRYP initialization vector left-word register 0, Address offset: 0x40 *) 815 IV0RR: longword; (*!< CRYP initialization vector right-word register 0, Address offset: 0x44 *) 816 IV1LR: longword; (*!< CRYP initialization vector left-word register 1, Address offset: 0x48 *) 817 IV1RR: longword; (*!< CRYP initialization vector right-word register 1, Address offset: 0x4C *) 818 CSGCMCCM0R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 *) 819 CSGCMCCM1R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 *) 820 CSGCMCCM2R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 *) 821 CSGCMCCM3R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C *) 822 CSGCMCCM4R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 *) 823 CSGCMCCM5R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 *) 824 CSGCMCCM6R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 *) 825 CSGCMCCM7R: longword; (*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C *) 826 CSGCM0R: longword; (*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 *) 827 CSGCM1R: longword; (*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 *) 828 CSGCM2R: longword; (*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 *) 829 CSGCM3R: longword; (*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C *) 830 CSGCM4R: longword; (*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 *) 831 CSGCM5R: longword; (*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 *) 832 CSGCM6R: longword; (*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 *) 833 CSGCM7R: longword; (*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C *) 834 end; 835 836 (** 837 * @brief HASH 838 *) 839 840 HASH_TypeDef = record 841 CR: longword; (*!< HASH control register, Address offset: 0x00 *) 842 DIN: longword; (*!< HASH data input register, Address offset: 0x04 *) 843 STR: longword; (*!< HASH start register, Address offset: 0x08 *) 844 HR: array [0..4] of longword; (*!< HASH digest registers, Address offset: 0x0C-0x1C *) 845 IMR: longword; (*!< HASH interrupt enable register, Address offset: 0x20 *) 846 SR: longword; (*!< HASH status register, Address offset: 0x24 *) 847 RESERVED: array [0..51] of longword; (*!< Reserved, 0x28-0xF4 *) 848 CSR: array [0..53] of longword; (*!< HASH context swap registers, Address offset: 0x0F8-0x1CC *) 849 end; 850 851 (** 852 * @brief HASH_DIGEST 853 *) 854 855 HASH_DIGEST_TypeDef = record 856 HR: array [0..7] of longword; (*!< HASH digest registers, Address offset: 0x310-0x32C *) 857 end; 858 859 (** 860 * @brief RNG 861 *) 862 863 RNG_TypeDef = record 864 CR: longword; (*!< RNG control register, Address offset: 0x00 *) 865 SR: longword; (*!< RNG status register, Address offset: 0x04 *) 866 DR: longword; (*!< RNG data register, Address offset: 0x08 *) 867 end; 868 869 (** 870 * @} 871 *) 872 873 (** 874 * @brief USB_OTG_Core_Registers 875 *) 876 877 USB_OTG_GlobalTypeDef = record 878 GOTGCTL: longword; (*!< USB_OTG Control and Status Register 000h *) 879 GOTGINT: longword; (*!< USB_OTG Interrupt Register 004h *) 880 GAHBCFG: longword; (*!< Core AHB Configuration Register 008h *) 881 GUSBCFG: longword; (*!< Core USB Configuration Register 00Ch *) 882 GRSTCTL: longword; (*!< Core Reset Register 010h *) 883 GINTSTS: longword; (*!< Core Interrupt Register 014h *) 884 GINTMSK: longword; (*!< Core Interrupt Mask Register 018h *) 885 GRXSTSR: longword; (*!< Receive Sts Q Read Register 01Ch *) 886 GRXSTSP: longword; (*!< Receive Sts Q Read & POP Register 020h *) 887 GRXFSIZ: longword; (*!< Receive FIFO Size Register 024h *) 888 DIEPTXF0_HNPTXFSIZ: longword; (*!< EP0 / Non Periodic Tx FIFO Size Register 028h *) 889 HNPTXSTS: longword; (*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch *) 890 Reserved30: array [0..1] of longword; (*!< Reserved 030h *) 891 GCCFG: longword; (*!< General Purpose IO Register 038h *) 892 CID: longword; (*!< User ID Register 03Ch *) 893 Reserved5: array [0..2] of longword; (*!< Reserved 040h-048h *) 894 GHWCFG3: longword; (*!< User HW config3 04Ch *) 895 Reserved6: longword; (*!< Reserved 050h *) 896 GLPMCFG: longword; (*!< LPM Register 054h *) 897 GPWRDN: longword; (*!< Power Down Register 058h *) 898 GDFIFOCFG: longword; (*!< DFIFO Software Config Register 05Ch *) 899 GADPCTL: longword; (*!< ADP Timer, Control and Status Register 60Ch *) 900 Reserved43: array [0..38] of longword; (*!< Reserved 058h-0FFh *) 901 HPTXFSIZ: longword; (*!< Host Periodic Tx FIFO Size Reg 100h *) 902 DIEPTXF: array [0..14] of longword; (*!< dev Periodic Transmit FIFO *) 903 end; 904 905 906 (** 907 * @brief USB_OTG_device_Registers 908 *) 909 910 USB_OTG_DeviceTypeDef = record 911 DCFG: longword; (*!< dev Configuration Register 800h *) 912 DCTL: longword; (*!< dev Control Register 804h *) 913 DSTS: longword; (*!< dev Status Register (RO) 808h *) 914 Reserved0C: longword; (*!< Reserved 80Ch *) 915 DIEPMSK: longword; (*!< dev IN Endpoint Mask 810h *) 916 DOEPMSK: longword; (*!< dev OUT Endpoint Mask 814h *) 917 DAINT: longword; (*!< dev All Endpoints Itr Reg 818h *) 918 DAINTMSK: longword; (*!< dev All Endpoints Itr Mask 81Ch *) 919 Reserved20: longword; (*!< Reserved 820h *) 920 Reserved9: longword; (*!< Reserved 824h *) 921 DVBUSDIS: longword; (*!< dev VBUS discharge Register 828h *) 922 DVBUSPULSE: longword; (*!< dev VBUS Pulse Register 82Ch *) 923 DTHRCTL: longword; (*!< dev threshold 830h *) 924 DIEPEMPMSK: longword; (*!< dev empty msk 834h *) 925 DEACHINT: longword; (*!< dedicated EP interrupt 838h *) 926 DEACHMSK: longword; (*!< dedicated EP msk 83Ch *) 927 Reserved40: longword; (*!< dedicated EP mask 840h *) 928 DINEP1MSK: longword; (*!< dedicated EP mask 844h *) 929 Reserved44: array [0..14] of longword; (*!< Reserved 844-87Ch *) 930 DOUTEP1MSK: longword; (*!< dedicated EP msk 884h *) 931 end; 932 933 934 (** 935 * @brief USB_OTG_IN_Endpoint-Specific_Register 936 *) 937 938 USB_OTG_INEndpointTypeDef = record 939 DIEPCTL: longword; (*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h *) 940 Reserved04: longword; (*!< Reserved 900h + (ep_num * 20h) + 04h *) 941 DIEPINT: longword; (*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h *) 942 Reserved0C: longword; (*!< Reserved 900h + (ep_num * 20h) + 0Ch *) 943 DIEPTSIZ: longword; (*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h *) 944 DIEPDMA: longword; (*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h *) 945 DTXFSTS: longword; (*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h *) 946 Reserved18: longword; (*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch *) 947 end; 948 949 950 (** 951 * @brief USB_OTG_OUT_Endpoint-Specific_Registers 952 *) 953 954 USB_OTG_OUTEndpointTypeDef = record 955 DOEPCTL: longword; (*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h *) 956 Reserved04: longword; (*!< Reserved B00h + (ep_num * 20h) + 04h *) 957 DOEPINT: longword; (*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h *) 958 Reserved0C: longword; (*!< Reserved B00h + (ep_num * 20h) + 0Ch *) 959 DOEPTSIZ: longword; (*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h *) 960 DOEPDMA: longword; (*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h *) 961 Reserved18: array [0..1] of longword; (*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch *) 962 end; 963 964 965 (** 966 * @brief USB_OTG_Host_Mode_Register_Structures 967 *) 968 969 USB_OTG_HostTypeDef = record 970 HCFG: longword; (*!< Host Configuration Register 400h *) 971 HFIR: longword; (*!< Host Frame Interval Register 404h *) 972 HFNUM: longword; (*!< Host Frame Nbr/Frame Remaining 408h *) 973 Reserved40C: longword; (*!< Reserved 40Ch *) 974 HPTXSTS: longword; (*!< Host Periodic Tx FIFO/ Queue Status 410h *) 975 HAINT: longword; (*!< Host All Channels Interrupt Register 414h *) 976 HAINTMSK: longword; (*!< Host All Channels Interrupt Mask 418h *) 977 end; 978 979 (** 980 * @brief USB_OTG_Host_Channel_Specific_Registers 981 *) 982 983 USB_OTG_HostChannelTypeDef = record 984 HCCHAR: longword; (*!< Host Channel Characteristics Register 500h *) 985 HCSPLT: longword; (*!< Host Channel Split Control Register 504h *) 986 HCINT: longword; (*!< Host Channel Interrupt Register 508h *) 987 HCINTMSK: longword; (*!< Host Channel Interrupt Mask Register 50Ch *) 988 HCTSIZ: longword; (*!< Host Channel Transfer Size Register 510h *) 989 HCDMA: longword; (*!< Host Channel DMA Address Register 514h *) 990 Reserved: array [0..1] of longword; (*!< Reserved *) 991 end; 992 993 (** 994 * @} 995 *) 996 997 998 (** @addtogroup Peripheral_memory_map 999 * @{ 1000 *) 1001 1002const 1003 RAMITCM_BASE = $00000000; (*!< Base address of :16KB RAM reserved for CPU execution/instruction accessible over ITCM *) 1004 FLASHITCM_BASE = $00200000; (*!< Base address of :(up to 1 MB) embedded FLASH memory accessible over ITCM *) 1005 FLASHAXI_BASE = $08000000; (*!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI *) 1006 RAMDTCM_BASE = $20000000; (*!< Base address of : 64KB system data RAM accessible over DTCM *) 1007 SRAM1_BASE = $20010000; (*!< Base address of : 240KB RAM1 accessible over AXI/AHB *) 1008 SRAM2_BASE = $2004C000; (*!< Base address of : 16KB RAM2 accessible over AXI/AHB *) 1009 PERIPH_BASE = $40000000; (*!< Base address of : AHB/ABP Peripherals *) 1010 BKPSRAM_BASE = $40024000; (*!< Base address of : Backup SRAM(4 KB) *) 1011 QSPI_BASE = $90000000; (*!< Base address of : QSPI memories accessible over AXI *) 1012 FMC_R_BASE = $A0000000; (*!< Base address of : FMC Control registers *) 1013 QSPI_R_BASE = $A0001000; (*!< Base address of : QSPI Control registers *) 1014 FLASH_END = $080FFFFF; (*!< FLASH end address *) 1015 (* Legacy define *) 1016 1017 FLASH_BASE = FLASHAXI_BASE; 1018 (*!< Peripheral memory map *) 1019 1020 APB1PERIPH_BASE = PERIPH_BASE; 1021 APB2PERIPH_BASE = (PERIPH_BASE + $00010000); 1022 AHB1PERIPH_BASE = (PERIPH_BASE + $00020000); 1023 AHB2PERIPH_BASE = (PERIPH_BASE + $10000000); 1024 (*!< APB1 peripherals *) 1025 1026 TIM2_BASE = (APB1PERIPH_BASE + $0000); 1027 TIM3_BASE = (APB1PERIPH_BASE + $0400); 1028 TIM4_BASE = (APB1PERIPH_BASE + $0800); 1029 TIM5_BASE = (APB1PERIPH_BASE + $0C00); 1030 TIM6_BASE = (APB1PERIPH_BASE + $1000); 1031 TIM7_BASE = (APB1PERIPH_BASE + $1400); 1032 TIM12_BASE = (APB1PERIPH_BASE + $1800); 1033 TIM13_BASE = (APB1PERIPH_BASE + $1C00); 1034 TIM14_BASE = (APB1PERIPH_BASE + $2000); 1035 LPTIM1_BASE = (APB1PERIPH_BASE + $2400); 1036 RTC_BASE = (APB1PERIPH_BASE + $2800); 1037 WWDG_BASE = (APB1PERIPH_BASE + $2C00); 1038 IWDG_BASE = (APB1PERIPH_BASE + $3000); 1039 SPI2_BASE = (APB1PERIPH_BASE + $3800); 1040 SPI3_BASE = (APB1PERIPH_BASE + $3C00); 1041 SPDIFRX_BASE = (APB1PERIPH_BASE + $4000); 1042 USART2_BASE = (APB1PERIPH_BASE + $4400); 1043 USART3_BASE = (APB1PERIPH_BASE + $4800); 1044 UART4_BASE = (APB1PERIPH_BASE + $4C00); 1045 UART5_BASE = (APB1PERIPH_BASE + $5000); 1046 I2C1_BASE = (APB1PERIPH_BASE + $5400); 1047 I2C2_BASE = (APB1PERIPH_BASE + $5800); 1048 I2C3_BASE = (APB1PERIPH_BASE + $5C00); 1049 I2C4_BASE = (APB1PERIPH_BASE + $6000); 1050 CAN1_BASE = (APB1PERIPH_BASE + $6400); 1051 CAN2_BASE = (APB1PERIPH_BASE + $6800); 1052 CEC_BASE = (APB1PERIPH_BASE + $6C00); 1053 PWR_BASE = (APB1PERIPH_BASE + $7000); 1054 DAC_BASE = (APB1PERIPH_BASE + $7400); 1055 UART7_BASE = (APB1PERIPH_BASE + $7800); 1056 UART8_BASE = (APB1PERIPH_BASE + $7C00); 1057 (*!< APB2 peripherals *) 1058 1059 TIM1_BASE = (APB2PERIPH_BASE + $0000); 1060 TIM8_BASE = (APB2PERIPH_BASE + $0400); 1061 USART1_BASE = (APB2PERIPH_BASE + $1000); 1062 USART6_BASE = (APB2PERIPH_BASE + $1400); 1063 ADC1_BASE = (APB2PERIPH_BASE + $2000); 1064 ADC2_BASE = (APB2PERIPH_BASE + $2100); 1065 ADC3_BASE = (APB2PERIPH_BASE + $2200); 1066 ADC_BASE = (APB2PERIPH_BASE + $2300); 1067 SDMMC1_BASE = (APB2PERIPH_BASE + $2C00); 1068 SPI1_BASE = (APB2PERIPH_BASE + $3000); 1069 SPI4_BASE = (APB2PERIPH_BASE + $3400); 1070 SYSCFG_BASE = (APB2PERIPH_BASE + $3800); 1071 EXTI_BASE = (APB2PERIPH_BASE + $3C00); 1072 TIM9_BASE = (APB2PERIPH_BASE + $4000); 1073 TIM10_BASE = (APB2PERIPH_BASE + $4400); 1074 TIM11_BASE = (APB2PERIPH_BASE + $4800); 1075 SPI5_BASE = (APB2PERIPH_BASE + $5000); 1076 SPI6_BASE = (APB2PERIPH_BASE + $5400); 1077 SAI1_BASE = (APB2PERIPH_BASE + $5800); 1078 SAI2_BASE = (APB2PERIPH_BASE + $5C00); 1079 SAI1_Block_A_BASE = (SAI1_BASE + $004); 1080 SAI1_Block_B_BASE = (SAI1_BASE + $024); 1081 SAI2_Block_A_BASE = (SAI2_BASE + $004); 1082 SAI2_Block_B_BASE = (SAI2_BASE + $024); 1083 LTDC_BASE = (APB2PERIPH_BASE + $6800); 1084 LTDC_Layer1_BASE = (LTDC_BASE + $84); 1085 LTDC_Layer2_BASE = (LTDC_BASE + $104); 1086 (*!< AHB1 peripherals *) 1087 1088 GPIOA_BASE = (AHB1PERIPH_BASE + $0000); 1089 GPIOB_BASE = (AHB1PERIPH_BASE + $0400); 1090 GPIOC_BASE = (AHB1PERIPH_BASE + $0800); 1091 GPIOD_BASE = (AHB1PERIPH_BASE + $0C00); 1092 GPIOE_BASE = (AHB1PERIPH_BASE + $1000); 1093 GPIOF_BASE = (AHB1PERIPH_BASE + $1400); 1094 GPIOG_BASE = (AHB1PERIPH_BASE + $1800); 1095 GPIOH_BASE = (AHB1PERIPH_BASE + $1C00); 1096 GPIOI_BASE = (AHB1PERIPH_BASE + $2000); 1097 GPIOJ_BASE = (AHB1PERIPH_BASE + $2400); 1098 GPIOK_BASE = (AHB1PERIPH_BASE + $2800); 1099 CRC_BASE = (AHB1PERIPH_BASE + $3000); 1100 RCC_BASE = (AHB1PERIPH_BASE + $3800); 1101 FLASH_R_BASE = (AHB1PERIPH_BASE + $3C00); 1102 DMA1_BASE = (AHB1PERIPH_BASE + $6000); 1103 DMA1_Stream0_BASE = (DMA1_BASE + $010); 1104 DMA1_Stream1_BASE = (DMA1_BASE + $028); 1105 DMA1_Stream2_BASE = (DMA1_BASE + $040); 1106 DMA1_Stream3_BASE = (DMA1_BASE + $058); 1107 DMA1_Stream4_BASE = (DMA1_BASE + $070); 1108 DMA1_Stream5_BASE = (DMA1_BASE + $088); 1109 DMA1_Stream6_BASE = (DMA1_BASE + $0A0); 1110 DMA1_Stream7_BASE = (DMA1_BASE + $0B8); 1111 DMA2_BASE = (AHB1PERIPH_BASE + $6400); 1112 DMA2_Stream0_BASE = (DMA2_BASE + $010); 1113 DMA2_Stream1_BASE = (DMA2_BASE + $028); 1114 DMA2_Stream2_BASE = (DMA2_BASE + $040); 1115 DMA2_Stream3_BASE = (DMA2_BASE + $058); 1116 DMA2_Stream4_BASE = (DMA2_BASE + $070); 1117 DMA2_Stream5_BASE = (DMA2_BASE + $088); 1118 DMA2_Stream6_BASE = (DMA2_BASE + $0A0); 1119 DMA2_Stream7_BASE = (DMA2_BASE + $0B8); 1120 ETH_BASE = (AHB1PERIPH_BASE + $8000); 1121 ETH_MAC_BASE = (ETH_BASE); 1122 ETH_MMC_BASE = (ETH_BASE + $0100); 1123 ETH_PTP_BASE = (ETH_BASE + $0700); 1124 ETH_DMA_BASE = (ETH_BASE + $1000); 1125 DMA2D_BASE = (AHB1PERIPH_BASE + $B000); 1126 (*!< AHB2 peripherals *) 1127 1128 DCMI_BASE = (AHB2PERIPH_BASE + $50000); 1129 CRYP_BASE = (AHB2PERIPH_BASE + $60000); 1130 HASH_BASE = (AHB2PERIPH_BASE + $60400); 1131 HASH_DIGEST_BASE = (AHB2PERIPH_BASE + $60710); 1132 RNG_BASE = (AHB2PERIPH_BASE + $60800); 1133 (*!< FMC Bankx registers base address *) 1134 1135 FMC_Bank1_R_BASE = (FMC_R_BASE + $0000); 1136 FMC_Bank1E_R_BASE = (FMC_R_BASE + $0104); 1137 FMC_Bank3_R_BASE = (FMC_R_BASE + $0080); 1138 FMC_Bank5_6_R_BASE = (FMC_R_BASE + $0140); 1139 (* Debug MCU registers base address *) 1140 1141 DBGMCU_BASE = $E0042000; 1142 (*!< USB registers base address *) 1143 1144 USB_OTG_HS_PERIPH_BASE = $40040000; 1145 USB_OTG_FS_PERIPH_BASE = $50000000; 1146 USB_OTG_GLOBAL_BASE = $000; 1147 USB_OTG_DEVICE_BASE = $800; 1148 USB_OTG_IN_ENDPOINT_BASE = $900; 1149 USB_OTG_OUT_ENDPOINT_BASE = $B00; 1150 USB_OTG_EP_REG_SIZE = $20; 1151 USB_OTG_HOST_BASE = $400; 1152 USB_OTG_HOST_PORT_BASE = $440; 1153 USB_OTG_HOST_CHANNEL_BASE = $500; 1154 USB_OTG_HOST_CHANNEL_SIZE = $20; 1155 USB_OTG_PCGCCTL_BASE = $E00; 1156 USB_OTG_FIFO_BASE = $1000; 1157 USB_OTG_FIFO_SIZE = $1000; 1158 1159var 1160 TIM2: TIM_TypeDef absolute TIM2_BASE; 1161 TIM3: TIM_TypeDef absolute TIM3_BASE; 1162 TIM4: TIM_TypeDef absolute TIM4_BASE; 1163 TIM5: TIM_TypeDef absolute TIM5_BASE; 1164 TIM6: TIM_TypeDef absolute TIM6_BASE; 1165 TIM7: TIM_TypeDef absolute TIM7_BASE; 1166 TIM12: TIM_TypeDef absolute TIM12_BASE; 1167 TIM13: TIM_TypeDef absolute TIM13_BASE; 1168 TIM14: TIM_TypeDef absolute TIM14_BASE; 1169 LPTIM1: LPTIM_TypeDef absolute LPTIM1_BASE; 1170 RTC: RTC_TypeDef absolute RTC_BASE; 1171 WWDG: WWDG_TypeDef absolute WWDG_BASE; 1172 IWDG: IWDG_TypeDef absolute IWDG_BASE; 1173 SPI2: SPI_TypeDef absolute SPI2_BASE; 1174 SPI3: SPI_TypeDef absolute SPI3_BASE; 1175 SPDIFRX: SPDIFRX_TypeDef absolute SPDIFRX_BASE; 1176 USART2: USART_TypeDef absolute USART2_BASE; 1177 USART3: USART_TypeDef absolute USART3_BASE; 1178 UART4: USART_TypeDef absolute UART4_BASE; 1179 UART5: USART_TypeDef absolute UART5_BASE; 1180 I2C1: I2C_TypeDef absolute I2C1_BASE; 1181 I2C2: I2C_TypeDef absolute I2C2_BASE; 1182 I2C3: I2C_TypeDef absolute I2C3_BASE; 1183 I2C4: I2C_TypeDef absolute I2C4_BASE; 1184 CAN1: CAN_TypeDef absolute CAN1_BASE; 1185 CAN2: CAN_TypeDef absolute CAN2_BASE; 1186 CEC: CEC_TypeDef absolute CEC_BASE; 1187 PWR: PWR_TypeDef absolute PWR_BASE; 1188 DAC: DAC_TypeDef absolute DAC_BASE; 1189 UART7: USART_TypeDef absolute UART7_BASE; 1190 UART8: USART_TypeDef absolute UART8_BASE; 1191 TIM1: TIM_TypeDef absolute TIM1_BASE; 1192 TIM8: TIM_TypeDef absolute TIM8_BASE; 1193 USART1: USART_TypeDef absolute USART1_BASE; 1194 USART6: USART_TypeDef absolute USART6_BASE; 1195 ADC: ADC_Common_TypeDef absolute ADC_BASE; 1196 ADC1: ADC_TypeDef absolute ADC1_BASE; 1197 ADC2: ADC_TypeDef absolute ADC2_BASE; 1198 ADC3: ADC_TypeDef absolute ADC3_BASE; 1199 SDMMC1: SDMMC_TypeDef absolute SDMMC1_BASE; 1200 SPI1: SPI_TypeDef absolute SPI1_BASE; 1201 SPI4: SPI_TypeDef absolute SPI4_BASE; 1202 SYSCFG: SYSCFG_TypeDef absolute SYSCFG_BASE; 1203 EXTI: EXTI_TypeDef absolute EXTI_BASE; 1204 TIM9: TIM_TypeDef absolute TIM9_BASE; 1205 TIM10: TIM_TypeDef absolute TIM10_BASE; 1206 TIM11: TIM_TypeDef absolute TIM11_BASE; 1207 SPI5: SPI_TypeDef absolute SPI5_BASE; 1208 SPI6: SPI_TypeDef absolute SPI6_BASE; 1209 SAI1: SAI_TypeDef absolute SAI1_BASE; 1210 SAI2: SAI_TypeDef absolute SAI2_BASE; 1211 SAI1_Block_A: SAI_Block_TypeDef absolute SAI1_Block_A_BASE; 1212 SAI1_Block_B: SAI_Block_TypeDef absolute SAI1_Block_B_BASE; 1213 SAI2_Block_A: SAI_Block_TypeDef absolute SAI2_Block_A_BASE; 1214 SAI2_Block_B: SAI_Block_TypeDef absolute SAI2_Block_B_BASE; 1215 LTDC: LTDC_TypeDef absolute LTDC_BASE; 1216 LTDC_Layer1: LTDC_Layer_TypeDef absolute LTDC_Layer1_BASE; 1217 LTDC_Layer2: LTDC_Layer_TypeDef absolute LTDC_Layer2_BASE; 1218 GPIOA: GPIO_TypeDef absolute GPIOA_BASE; 1219 GPIOB: GPIO_TypeDef absolute GPIOB_BASE; 1220 GPIOC: GPIO_TypeDef absolute GPIOC_BASE; 1221 GPIOD: GPIO_TypeDef absolute GPIOD_BASE; 1222 GPIOE: GPIO_TypeDef absolute GPIOE_BASE; 1223 GPIOF: GPIO_TypeDef absolute GPIOF_BASE; 1224 GPIOG: GPIO_TypeDef absolute GPIOG_BASE; 1225 GPIOH: GPIO_TypeDef absolute GPIOH_BASE; 1226 GPIOI: GPIO_TypeDef absolute GPIOI_BASE; 1227 GPIOJ: GPIO_TypeDef absolute GPIOJ_BASE; 1228 GPIOK: GPIO_TypeDef absolute GPIOK_BASE; 1229 CRC: CRC_TypeDef absolute CRC_BASE; 1230 RCC: RCC_TypeDef absolute RCC_BASE; 1231 FLASH: FLASH_TypeDef absolute FLASH_R_BASE; 1232 DMA1: DMA_TypeDef absolute DMA1_BASE; 1233 DMA1_Stream0: DMA_Stream_TypeDef absolute DMA1_Stream0_BASE; 1234 DMA1_Stream1: DMA_Stream_TypeDef absolute DMA1_Stream1_BASE; 1235 DMA1_Stream2: DMA_Stream_TypeDef absolute DMA1_Stream2_BASE; 1236 DMA1_Stream3: DMA_Stream_TypeDef absolute DMA1_Stream3_BASE; 1237 DMA1_Stream4: DMA_Stream_TypeDef absolute DMA1_Stream4_BASE; 1238 DMA1_Stream5: DMA_Stream_TypeDef absolute DMA1_Stream5_BASE; 1239 DMA1_Stream6: DMA_Stream_TypeDef absolute DMA1_Stream6_BASE; 1240 DMA1_Stream7: DMA_Stream_TypeDef absolute DMA1_Stream7_BASE; 1241 DMA2: DMA_TypeDef absolute DMA2_BASE; 1242 DMA2_Stream0: DMA_Stream_TypeDef absolute DMA2_Stream0_BASE; 1243 DMA2_Stream1: DMA_Stream_TypeDef absolute DMA2_Stream1_BASE; 1244 DMA2_Stream2: DMA_Stream_TypeDef absolute DMA2_Stream2_BASE; 1245 DMA2_Stream3: DMA_Stream_TypeDef absolute DMA2_Stream3_BASE; 1246 DMA2_Stream4: DMA_Stream_TypeDef absolute DMA2_Stream4_BASE; 1247 DMA2_Stream5: DMA_Stream_TypeDef absolute DMA2_Stream5_BASE; 1248 DMA2_Stream6: DMA_Stream_TypeDef absolute DMA2_Stream6_BASE; 1249 DMA2_Stream7: DMA_Stream_TypeDef absolute DMA2_Stream7_BASE; 1250 ETH: ETH_TypeDef absolute ETH_BASE; 1251 DMA2D: DMA2D_TypeDef absolute DMA2D_BASE; 1252 DCMI: DCMI_TypeDef absolute DCMI_BASE; 1253 CRYP: CRYP_TypeDef absolute CRYP_BASE; 1254 HASH: HASH_TypeDef absolute HASH_BASE; 1255 HASH_DIGEST: HASH_DIGEST_TypeDef absolute HASH_DIGEST_BASE; 1256 RNG: RNG_TypeDef absolute RNG_BASE; 1257 FMC_Bank1: FMC_Bank1_TypeDef absolute FMC_Bank1_R_BASE; 1258 FMC_Bank1E: FMC_Bank1E_TypeDef absolute FMC_Bank1E_R_BASE; 1259 FMC_Bank3: FMC_Bank3_TypeDef absolute FMC_Bank3_R_BASE; 1260 FMC_Bank5_6: FMC_Bank5_6_TypeDef absolute FMC_Bank5_6_R_BASE; 1261 QUADSPI: QUADSPI_TypeDef absolute QSPI_R_BASE; 1262 DBGMCU: DBGMCU_TypeDef absolute DBGMCU_BASE; 1263 USB_OTG_FS: USB_OTG_GlobalTypeDef absolute USB_OTG_FS_PERIPH_BASE; 1264 USB_OTG_HS: USB_OTG_GlobalTypeDef absolute USB_OTG_HS_PERIPH_BASE; 1265 1266implementation 1267 1268procedure NMI_Interrupt; external name 'NMI_Interrupt'; 1269procedure HardFault_Interrupt; external name 'HardFault_Interrupt'; 1270procedure MemManage_Interrupt; external name 'MemManage_Interrupt'; 1271procedure BusFault_Interrupt; external name 'BusFault_Interrupt'; 1272procedure UsageFault_Interrupt; external name 'UsageFault_Interrupt'; 1273procedure SVC_Interrupt; external name 'SVC_Interrupt'; 1274procedure DebugMon_Interrupt; external name 'DebugMon_Interrupt'; 1275procedure PendSV_Interrupt; external name 'PendSV_Interrupt'; 1276procedure SysTick_Interrupt; external name 'SysTick_Interrupt'; 1277procedure WWDG_Interrupt; external name 'WWDG_Interrupt'; 1278procedure PVD_Interrupt; external name 'PVD_Interrupt'; 1279procedure TAMP_STAMP_Interrupt; external name 'TAMP_STAMP_Interrupt'; 1280procedure RTC_WKUP_Interrupt; external name 'RTC_WKUP_Interrupt'; 1281procedure FLASH_Interrupt; external name 'FLASH_Interrupt'; 1282procedure RCC_Interrupt; external name 'RCC_Interrupt'; 1283procedure EXTI0_Interrupt; external name 'EXTI0_Interrupt'; 1284procedure EXTI1_Interrupt; external name 'EXTI1_Interrupt'; 1285procedure EXTI2_Interrupt; external name 'EXTI2_Interrupt'; 1286procedure EXTI3_Interrupt; external name 'EXTI3_Interrupt'; 1287procedure EXTI4_Interrupt; external name 'EXTI4_Interrupt'; 1288procedure DMA1_Stream0_Interrupt; external name 'DMA1_Stream0_Interrupt'; 1289procedure DMA1_Stream1_Interrupt; external name 'DMA1_Stream1_Interrupt'; 1290procedure DMA1_Stream2_Interrupt; external name 'DMA1_Stream2_Interrupt'; 1291procedure DMA1_Stream3_Interrupt; external name 'DMA1_Stream3_Interrupt'; 1292procedure DMA1_Stream4_Interrupt; external name 'DMA1_Stream4_Interrupt'; 1293procedure DMA1_Stream5_Interrupt; external name 'DMA1_Stream5_Interrupt'; 1294procedure DMA1_Stream6_Interrupt; external name 'DMA1_Stream6_Interrupt'; 1295procedure ADC_Interrupt; external name 'ADC_Interrupt'; 1296procedure CAN1_TX_Interrupt; external name 'CAN1_TX_Interrupt'; 1297procedure CAN1_RX0_Interrupt; external name 'CAN1_RX0_Interrupt'; 1298procedure CAN1_RX1_Interrupt; external name 'CAN1_RX1_Interrupt'; 1299procedure CAN1_SCE_Interrupt; external name 'CAN1_SCE_Interrupt'; 1300procedure EXTI9_5_Interrupt; external name 'EXTI9_5_Interrupt'; 1301procedure TIM1_BRK_TIM9_Interrupt; external name 'TIM1_BRK_TIM9_Interrupt'; 1302procedure TIM1_UP_TIM10_Interrupt; external name 'TIM1_UP_TIM10_Interrupt'; 1303procedure TIM1_TRG_COM_TIM11_Interrupt; external name 'TIM1_TRG_COM_TIM11_Interrupt'; 1304procedure TIM1_CC_Interrupt; external name 'TIM1_CC_Interrupt'; 1305procedure TIM2_Interrupt; external name 'TIM2_Interrupt'; 1306procedure TIM3_Interrupt; external name 'TIM3_Interrupt'; 1307procedure TIM4_Interrupt; external name 'TIM4_Interrupt'; 1308procedure I2C1_EV_Interrupt; external name 'I2C1_EV_Interrupt'; 1309procedure I2C1_ER_Interrupt; external name 'I2C1_ER_Interrupt'; 1310procedure I2C2_EV_Interrupt; external name 'I2C2_EV_Interrupt'; 1311procedure I2C2_ER_Interrupt; external name 'I2C2_ER_Interrupt'; 1312procedure SPI1_Interrupt; external name 'SPI1_Interrupt'; 1313procedure SPI2_Interrupt; external name 'SPI2_Interrupt'; 1314procedure USART1_Interrupt; external name 'USART1_Interrupt'; 1315procedure USART2_Interrupt; external name 'USART2_Interrupt'; 1316procedure USART3_Interrupt; external name 'USART3_Interrupt'; 1317procedure EXTI15_10_Interrupt; external name 'EXTI15_10_Interrupt'; 1318procedure RTC_Alarm_Interrupt; external name 'RTC_Alarm_Interrupt'; 1319procedure OTG_FS_WKUP_Interrupt; external name 'OTG_FS_WKUP_Interrupt'; 1320procedure TIM8_BRK_TIM12_Interrupt; external name 'TIM8_BRK_TIM12_Interrupt'; 1321procedure TIM8_UP_TIM13_Interrupt; external name 'TIM8_UP_TIM13_Interrupt'; 1322procedure TIM8_TRG_COM_TIM14_Interrupt; external name 'TIM8_TRG_COM_TIM14_Interrupt'; 1323procedure TIM8_CC_Interrupt; external name 'TIM8_CC_Interrupt'; 1324procedure DMA1_Stream7_Interrupt; external name 'DMA1_Stream7_Interrupt'; 1325procedure FMC_Interrupt; external name 'FMC_Interrupt'; 1326procedure SDMMC1_Interrupt; external name 'SDMMC1_Interrupt'; 1327procedure TIM5_Interrupt; external name 'TIM5_Interrupt'; 1328procedure SPI3_Interrupt; external name 'SPI3_Interrupt'; 1329procedure UART4_Interrupt; external name 'UART4_Interrupt'; 1330procedure UART5_Interrupt; external name 'UART5_Interrupt'; 1331procedure TIM6_DAC_Interrupt; external name 'TIM6_DAC_Interrupt'; 1332procedure TIM7_Interrupt; external name 'TIM7_Interrupt'; 1333procedure DMA2_Stream0_Interrupt; external name 'DMA2_Stream0_Interrupt'; 1334procedure DMA2_Stream1_Interrupt; external name 'DMA2_Stream1_Interrupt'; 1335procedure DMA2_Stream2_Interrupt; external name 'DMA2_Stream2_Interrupt'; 1336procedure DMA2_Stream3_Interrupt; external name 'DMA2_Stream3_Interrupt'; 1337procedure DMA2_Stream4_Interrupt; external name 'DMA2_Stream4_Interrupt'; 1338procedure ETH_Interrupt; external name 'ETH_Interrupt'; 1339procedure ETH_WKUP_Interrupt; external name 'ETH_WKUP_Interrupt'; 1340procedure CAN2_TX_Interrupt; external name 'CAN2_TX_Interrupt'; 1341procedure CAN2_RX0_Interrupt; external name 'CAN2_RX0_Interrupt'; 1342procedure CAN2_RX1_Interrupt; external name 'CAN2_RX1_Interrupt'; 1343procedure CAN2_SCE_Interrupt; external name 'CAN2_SCE_Interrupt'; 1344procedure OTG_FS_Interrupt; external name 'OTG_FS_Interrupt'; 1345procedure DMA2_Stream5_Interrupt; external name 'DMA2_Stream5_Interrupt'; 1346procedure DMA2_Stream6_Interrupt; external name 'DMA2_Stream6_Interrupt'; 1347procedure DMA2_Stream7_Interrupt; external name 'DMA2_Stream7_Interrupt'; 1348procedure USART6_Interrupt; external name 'USART6_Interrupt'; 1349procedure I2C3_EV_Interrupt; external name 'I2C3_EV_Interrupt'; 1350procedure I2C3_ER_Interrupt; external name 'I2C3_ER_Interrupt'; 1351procedure OTG_HS_EP1_OUT_Interrupt; external name 'OTG_HS_EP1_OUT_Interrupt'; 1352procedure OTG_HS_EP1_IN_Interrupt; external name 'OTG_HS_EP1_IN_Interrupt'; 1353procedure OTG_HS_WKUP_Interrupt; external name 'OTG_HS_WKUP_Interrupt'; 1354procedure OTG_HS_Interrupt; external name 'OTG_HS_Interrupt'; 1355procedure DCMI_Interrupt; external name 'DCMI_Interrupt'; 1356procedure CRYP_Interrupt; external name 'CRYP_Interrupt'; 1357procedure HASH_RNG_Interrupt; external name 'HASH_RNG_Interrupt'; 1358procedure FPU_Interrupt; external name 'FPU_Interrupt'; 1359procedure UART7_Interrupt; external name 'UART7_Interrupt'; 1360procedure UART8_Interrupt; external name 'UART8_Interrupt'; 1361procedure SPI4_Interrupt; external name 'SPI4_Interrupt'; 1362procedure SPI5_Interrupt; external name 'SPI5_Interrupt'; 1363procedure SPI6_Interrupt; external name 'SPI6_Interrupt'; 1364procedure SAI1_Interrupt; external name 'SAI1_Interrupt'; 1365procedure LTDC_Interrupt; external name 'LTDC_Interrupt'; 1366procedure LTDC_ER_Interrupt; external name 'LTDC_ER_Interrupt'; 1367procedure DMA2D_Interrupt; external name 'DMA2D_Interrupt'; 1368procedure SAI2_Interrupt; external name 'SAI2_Interrupt'; 1369procedure QUADSPI_Interrupt; external name 'QUADSPI_Interrupt'; 1370procedure LPTIM1_Interrupt; external name 'LPTIM1_Interrupt'; 1371procedure CEC_Interrupt; external name 'CEC_Interrupt'; 1372procedure I2C4_EV_Interrupt; external name 'I2C4_EV_Interrupt'; 1373procedure I2C4_ER_Interrupt; external name 'I2C4_ER_Interrupt'; 1374procedure SPDIF_RX_Interrupt; external name 'SPDIF_RX_Interrupt'; 1375 1376{$i cortexm4f_start.inc} 1377 1378procedure Vectors; assembler; nostackframe; 1379label interrupt_vectors; 1380asm 1381 .section ".init.interrupt_vectors" 1382interrupt_vectors: 1383 .long _stack_top 1384 .long Startup 1385 1386 .long NMI_Interrupt 1387 .long HardFault_Interrupt 1388 .long MemManage_Interrupt 1389 .long BusFault_Interrupt 1390 .long UsageFault_Interrupt 1391 .long 0 1392 .long 0 1393 .long 0 1394 .long 0 1395 .long SVC_Interrupt 1396 .long DebugMon_Interrupt 1397 .long 0 1398 .long PendSV_Interrupt 1399 .long SysTick_Interrupt 1400 1401 (* External Interrupts *) 1402 .long WWDG_Interrupt 1403 .long PVD_Interrupt 1404 .long TAMP_STAMP_Interrupt 1405 .long RTC_WKUP_Interrupt 1406 .long FLASH_Interrupt 1407 .long RCC_Interrupt 1408 .long EXTI0_Interrupt 1409 .long EXTI1_Interrupt 1410 .long EXTI2_Interrupt 1411 .long EXTI3_Interrupt 1412 .long EXTI4_Interrupt 1413 .long DMA1_Stream0_Interrupt 1414 .long DMA1_Stream1_Interrupt 1415 .long DMA1_Stream2_Interrupt 1416 .long DMA1_Stream3_Interrupt 1417 .long DMA1_Stream4_Interrupt 1418 .long DMA1_Stream5_Interrupt 1419 .long DMA1_Stream6_Interrupt 1420 .long ADC_Interrupt 1421 .long CAN1_TX_Interrupt 1422 .long CAN1_RX0_Interrupt 1423 .long CAN1_RX1_Interrupt 1424 .long CAN1_SCE_Interrupt 1425 .long EXTI9_5_Interrupt 1426 .long TIM1_BRK_TIM9_Interrupt 1427 .long TIM1_UP_TIM10_Interrupt 1428 .long TIM1_TRG_COM_TIM11_Interrupt 1429 .long TIM1_CC_Interrupt 1430 .long TIM2_Interrupt 1431 .long TIM3_Interrupt 1432 .long TIM4_Interrupt 1433 .long I2C1_EV_Interrupt 1434 .long I2C1_ER_Interrupt 1435 .long I2C2_EV_Interrupt 1436 .long I2C2_ER_Interrupt 1437 .long SPI1_Interrupt 1438 .long SPI2_Interrupt 1439 .long USART1_Interrupt 1440 .long USART2_Interrupt 1441 .long USART3_Interrupt 1442 .long EXTI15_10_Interrupt 1443 .long RTC_Alarm_Interrupt 1444 .long OTG_FS_WKUP_Interrupt 1445 .long TIM8_BRK_TIM12_Interrupt 1446 .long TIM8_UP_TIM13_Interrupt 1447 .long TIM8_TRG_COM_TIM14_Interrupt 1448 .long TIM8_CC_Interrupt 1449 .long DMA1_Stream7_Interrupt 1450 .long FMC_Interrupt 1451 .long SDMMC1_Interrupt 1452 .long TIM5_Interrupt 1453 .long SPI3_Interrupt 1454 .long UART4_Interrupt 1455 .long UART5_Interrupt 1456 .long TIM6_DAC_Interrupt 1457 .long TIM7_Interrupt 1458 .long DMA2_Stream0_Interrupt 1459 .long DMA2_Stream1_Interrupt 1460 .long DMA2_Stream2_Interrupt 1461 .long DMA2_Stream3_Interrupt 1462 .long DMA2_Stream4_Interrupt 1463 .long ETH_Interrupt 1464 .long ETH_WKUP_Interrupt 1465 .long CAN2_TX_Interrupt 1466 .long CAN2_RX0_Interrupt 1467 .long CAN2_RX1_Interrupt 1468 .long CAN2_SCE_Interrupt 1469 .long OTG_FS_Interrupt 1470 .long DMA2_Stream5_Interrupt 1471 .long DMA2_Stream6_Interrupt 1472 .long DMA2_Stream7_Interrupt 1473 .long USART6_Interrupt 1474 .long I2C3_EV_Interrupt 1475 .long I2C3_ER_Interrupt 1476 .long OTG_HS_EP1_OUT_Interrupt 1477 .long OTG_HS_EP1_IN_Interrupt 1478 .long OTG_HS_WKUP_Interrupt 1479 .long OTG_HS_Interrupt 1480 .long DCMI_Interrupt 1481 .long CRYP_Interrupt 1482 .long HASH_RNG_Interrupt 1483 .long FPU_Interrupt 1484 .long UART7_Interrupt 1485 .long UART8_Interrupt 1486 .long SPI4_Interrupt 1487 .long SPI5_Interrupt 1488 .long SPI6_Interrupt 1489 .long SAI1_Interrupt 1490 .long LTDC_Interrupt 1491 .long LTDC_ER_Interrupt 1492 .long DMA2D_Interrupt 1493 .long SAI2_Interrupt 1494 .long QUADSPI_Interrupt 1495 .long LPTIM1_Interrupt 1496 .long CEC_Interrupt 1497 .long I2C4_EV_Interrupt 1498 .long I2C4_ER_Interrupt 1499 .long SPDIF_RX_Interrupt 1500 1501 .weak NMI_Interrupt 1502 .weak HardFault_Interrupt 1503 .weak MemManage_Interrupt 1504 .weak BusFault_Interrupt 1505 .weak UsageFault_Interrupt 1506 .weak SVC_Interrupt 1507 .weak DebugMon_Interrupt 1508 .weak PendSV_Interrupt 1509 .weak SysTick_Interrupt 1510 .weak WWDG_Interrupt 1511 .weak PVD_Interrupt 1512 .weak TAMP_STAMP_Interrupt 1513 .weak RTC_WKUP_Interrupt 1514 .weak FLASH_Interrupt 1515 .weak RCC_Interrupt 1516 .weak EXTI0_Interrupt 1517 .weak EXTI1_Interrupt 1518 .weak EXTI2_Interrupt 1519 .weak EXTI3_Interrupt 1520 .weak EXTI4_Interrupt 1521 .weak DMA1_Stream0_Interrupt 1522 .weak DMA1_Stream1_Interrupt 1523 .weak DMA1_Stream2_Interrupt 1524 .weak DMA1_Stream3_Interrupt 1525 .weak DMA1_Stream4_Interrupt 1526 .weak DMA1_Stream5_Interrupt 1527 .weak DMA1_Stream6_Interrupt 1528 .weak ADC_Interrupt 1529 .weak CAN1_TX_Interrupt 1530 .weak CAN1_RX0_Interrupt 1531 .weak CAN1_RX1_Interrupt 1532 .weak CAN1_SCE_Interrupt 1533 .weak EXTI9_5_Interrupt 1534 .weak TIM1_BRK_TIM9_Interrupt 1535 .weak TIM1_UP_TIM10_Interrupt 1536 .weak TIM1_TRG_COM_TIM11_Interrupt 1537 .weak TIM1_CC_Interrupt 1538 .weak TIM2_Interrupt 1539 .weak TIM3_Interrupt 1540 .weak TIM4_Interrupt 1541 .weak I2C1_EV_Interrupt 1542 .weak I2C1_ER_Interrupt 1543 .weak I2C2_EV_Interrupt 1544 .weak I2C2_ER_Interrupt 1545 .weak SPI1_Interrupt 1546 .weak SPI2_Interrupt 1547 .weak USART1_Interrupt 1548 .weak USART2_Interrupt 1549 .weak USART3_Interrupt 1550 .weak EXTI15_10_Interrupt 1551 .weak RTC_Alarm_Interrupt 1552 .weak OTG_FS_WKUP_Interrupt 1553 .weak TIM8_BRK_TIM12_Interrupt 1554 .weak TIM8_UP_TIM13_Interrupt 1555 .weak TIM8_TRG_COM_TIM14_Interrupt 1556 .weak TIM8_CC_Interrupt 1557 .weak DMA1_Stream7_Interrupt 1558 .weak FMC_Interrupt 1559 .weak SDMMC1_Interrupt 1560 .weak TIM5_Interrupt 1561 .weak SPI3_Interrupt 1562 .weak UART4_Interrupt 1563 .weak UART5_Interrupt 1564 .weak TIM6_DAC_Interrupt 1565 .weak TIM7_Interrupt 1566 .weak DMA2_Stream0_Interrupt 1567 .weak DMA2_Stream1_Interrupt 1568 .weak DMA2_Stream2_Interrupt 1569 .weak DMA2_Stream3_Interrupt 1570 .weak DMA2_Stream4_Interrupt 1571 .weak ETH_Interrupt 1572 .weak ETH_WKUP_Interrupt 1573 .weak CAN2_TX_Interrupt 1574 .weak CAN2_RX0_Interrupt 1575 .weak CAN2_RX1_Interrupt 1576 .weak CAN2_SCE_Interrupt 1577 .weak OTG_FS_Interrupt 1578 .weak DMA2_Stream5_Interrupt 1579 .weak DMA2_Stream6_Interrupt 1580 .weak DMA2_Stream7_Interrupt 1581 .weak USART6_Interrupt 1582 .weak I2C3_EV_Interrupt 1583 .weak I2C3_ER_Interrupt 1584 .weak OTG_HS_EP1_OUT_Interrupt 1585 .weak OTG_HS_EP1_IN_Interrupt 1586 .weak OTG_HS_WKUP_Interrupt 1587 .weak OTG_HS_Interrupt 1588 .weak DCMI_Interrupt 1589 .weak CRYP_Interrupt 1590 .weak HASH_RNG_Interrupt 1591 .weak FPU_Interrupt 1592 .weak UART7_Interrupt 1593 .weak UART8_Interrupt 1594 .weak SPI4_Interrupt 1595 .weak SPI5_Interrupt 1596 .weak SPI6_Interrupt 1597 .weak SAI1_Interrupt 1598 .weak LTDC_Interrupt 1599 .weak LTDC_ER_Interrupt 1600 .weak DMA2D_Interrupt 1601 .weak SAI2_Interrupt 1602 .weak QUADSPI_Interrupt 1603 .weak LPTIM1_Interrupt 1604 .weak CEC_Interrupt 1605 .weak I2C4_EV_Interrupt 1606 .weak I2C4_ER_Interrupt 1607 .weak SPDIF_RX_Interrupt 1608 1609 .set NMI_Interrupt, HaltProc 1610 .set HardFault_Interrupt, HaltProc 1611 .set MemManage_Interrupt, HaltProc 1612 .set BusFault_Interrupt, HaltProc 1613 .set UsageFault_Interrupt, HaltProc 1614 .set SVC_Interrupt, HaltProc 1615 .set DebugMon_Interrupt, HaltProc 1616 .set PendSV_Interrupt, HaltProc 1617 .set SysTick_Interrupt, HaltProc 1618 .set WWDG_Interrupt, HaltProc 1619 .set PVD_Interrupt, HaltProc 1620 .set TAMP_STAMP_Interrupt, HaltProc 1621 .set RTC_WKUP_Interrupt, HaltProc 1622 .set FLASH_Interrupt, HaltProc 1623 .set RCC_Interrupt, HaltProc 1624 .set EXTI0_Interrupt, HaltProc 1625 .set EXTI1_Interrupt, HaltProc 1626 .set EXTI2_Interrupt, HaltProc 1627 .set EXTI3_Interrupt, HaltProc 1628 .set EXTI4_Interrupt, HaltProc 1629 .set DMA1_Stream0_Interrupt, HaltProc 1630 .set DMA1_Stream1_Interrupt, HaltProc 1631 .set DMA1_Stream2_Interrupt, HaltProc 1632 .set DMA1_Stream3_Interrupt, HaltProc 1633 .set DMA1_Stream4_Interrupt, HaltProc 1634 .set DMA1_Stream5_Interrupt, HaltProc 1635 .set DMA1_Stream6_Interrupt, HaltProc 1636 .set ADC_Interrupt, HaltProc 1637 .set CAN1_TX_Interrupt, HaltProc 1638 .set CAN1_RX0_Interrupt, HaltProc 1639 .set CAN1_RX1_Interrupt, HaltProc 1640 .set CAN1_SCE_Interrupt, HaltProc 1641 .set EXTI9_5_Interrupt, HaltProc 1642 .set TIM1_BRK_TIM9_Interrupt, HaltProc 1643 .set TIM1_UP_TIM10_Interrupt, HaltProc 1644 .set TIM1_TRG_COM_TIM11_Interrupt, HaltProc 1645 .set TIM1_CC_Interrupt, HaltProc 1646 .set TIM2_Interrupt, HaltProc 1647 .set TIM3_Interrupt, HaltProc 1648 .set TIM4_Interrupt, HaltProc 1649 .set I2C1_EV_Interrupt, HaltProc 1650 .set I2C1_ER_Interrupt, HaltProc 1651 .set I2C2_EV_Interrupt, HaltProc 1652 .set I2C2_ER_Interrupt, HaltProc 1653 .set SPI1_Interrupt, HaltProc 1654 .set SPI2_Interrupt, HaltProc 1655 .set USART1_Interrupt, HaltProc 1656 .set USART2_Interrupt, HaltProc 1657 .set USART3_Interrupt, HaltProc 1658 .set EXTI15_10_Interrupt, HaltProc 1659 .set RTC_Alarm_Interrupt, HaltProc 1660 .set OTG_FS_WKUP_Interrupt, HaltProc 1661 .set TIM8_BRK_TIM12_Interrupt, HaltProc 1662 .set TIM8_UP_TIM13_Interrupt, HaltProc 1663 .set TIM8_TRG_COM_TIM14_Interrupt, HaltProc 1664 .set TIM8_CC_Interrupt, HaltProc 1665 .set DMA1_Stream7_Interrupt, HaltProc 1666 .set FMC_Interrupt, HaltProc 1667 .set SDMMC1_Interrupt, HaltProc 1668 .set TIM5_Interrupt, HaltProc 1669 .set SPI3_Interrupt, HaltProc 1670 .set UART4_Interrupt, HaltProc 1671 .set UART5_Interrupt, HaltProc 1672 .set TIM6_DAC_Interrupt, HaltProc 1673 .set TIM7_Interrupt, HaltProc 1674 .set DMA2_Stream0_Interrupt, HaltProc 1675 .set DMA2_Stream1_Interrupt, HaltProc 1676 .set DMA2_Stream2_Interrupt, HaltProc 1677 .set DMA2_Stream3_Interrupt, HaltProc 1678 .set DMA2_Stream4_Interrupt, HaltProc 1679 .set ETH_Interrupt, HaltProc 1680 .set ETH_WKUP_Interrupt, HaltProc 1681 .set CAN2_TX_Interrupt, HaltProc 1682 .set CAN2_RX0_Interrupt, HaltProc 1683 .set CAN2_RX1_Interrupt, HaltProc 1684 .set CAN2_SCE_Interrupt, HaltProc 1685 .set OTG_FS_Interrupt, HaltProc 1686 .set DMA2_Stream5_Interrupt, HaltProc 1687 .set DMA2_Stream6_Interrupt, HaltProc 1688 .set DMA2_Stream7_Interrupt, HaltProc 1689 .set USART6_Interrupt, HaltProc 1690 .set I2C3_EV_Interrupt, HaltProc 1691 .set I2C3_ER_Interrupt, HaltProc 1692 .set OTG_HS_EP1_OUT_Interrupt, HaltProc 1693 .set OTG_HS_EP1_IN_Interrupt, HaltProc 1694 .set OTG_HS_WKUP_Interrupt, HaltProc 1695 .set OTG_HS_Interrupt, HaltProc 1696 .set DCMI_Interrupt, HaltProc 1697 .set CRYP_Interrupt, HaltProc 1698 .set HASH_RNG_Interrupt, HaltProc 1699 .set FPU_Interrupt, HaltProc 1700 .set UART7_Interrupt, HaltProc 1701 .set UART8_Interrupt, HaltProc 1702 .set SPI4_Interrupt, HaltProc 1703 .set SPI5_Interrupt, HaltProc 1704 .set SPI6_Interrupt, HaltProc 1705 .set SAI1_Interrupt, HaltProc 1706 .set LTDC_Interrupt, HaltProc 1707 .set LTDC_ER_Interrupt, HaltProc 1708 .set DMA2D_Interrupt, HaltProc 1709 .set SAI2_Interrupt, HaltProc 1710 .set QUADSPI_Interrupt, HaltProc 1711 .set LPTIM1_Interrupt, HaltProc 1712 .set CEC_Interrupt, HaltProc 1713 .set I2C4_EV_Interrupt, HaltProc 1714 .set I2C4_ER_Interrupt, HaltProc 1715 .set SPDIF_RX_Interrupt, HaltProc 1716 1717 .text 1718end; 1719 1720end. 1721