1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2020 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_PROTOS_H 23 #define GCC_AARCH64_PROTOS_H 24 25 #include "input.h" 26 27 /* SYMBOL_SMALL_ABSOLUTE: Generate symbol accesses through 28 high and lo relocs that calculate the base address using a PC 29 relative reloc. 30 So to get the address of foo, we generate 31 adrp x0, foo 32 add x0, x0, :lo12:foo 33 34 To load or store something to foo, we could use the corresponding 35 load store variants that generate an 36 ldr x0, [x0,:lo12:foo] 37 or 38 str x1, [x0, :lo12:foo] 39 40 This corresponds to the small code model of the compiler. 41 42 SYMBOL_SMALL_GOT_4G: Similar to the one above but this 43 gives us the GOT entry of the symbol being referred to : 44 Thus calculating the GOT entry for foo is done using the 45 following sequence of instructions. The ADRP instruction 46 gets us to the page containing the GOT entry of the symbol 47 and the got_lo12 gets us the actual offset in it, together 48 the base and offset, we can address 4G size GOT table. 49 50 adrp x0, :got:foo 51 ldr x0, [x0, :gotoff_lo12:foo] 52 53 This corresponds to the small PIC model of the compiler. 54 55 SYMBOL_SMALL_GOT_28K: Similar to SYMBOL_SMALL_GOT_4G, but used for symbol 56 restricted within 28K GOT table size. 57 58 ldr reg, [gp, #:gotpage_lo15:sym] 59 60 This corresponds to -fpic model for small memory model of the compiler. 61 62 SYMBOL_SMALL_TLSGD 63 SYMBOL_SMALL_TLSDESC 64 SYMBOL_SMALL_TLSIE 65 SYMBOL_TINY_TLSIE 66 SYMBOL_TLSLE12 67 SYMBOL_TLSLE24 68 SYMBOL_TLSLE32 69 SYMBOL_TLSLE48 70 Each of these represents a thread-local symbol, and corresponds to the 71 thread local storage relocation operator for the symbol being referred to. 72 73 SYMBOL_TINY_ABSOLUTE 74 75 Generate symbol accesses as a PC relative address using a single 76 instruction. To compute the address of symbol foo, we generate: 77 78 ADR x0, foo 79 80 SYMBOL_TINY_GOT 81 82 Generate symbol accesses via the GOT using a single PC relative 83 instruction. To compute the address of symbol foo, we generate: 84 85 ldr t0, :got:foo 86 87 The value of foo can subsequently read using: 88 89 ldrb t0, [t0] 90 91 SYMBOL_FORCE_TO_MEM : Global variables are addressed using 92 constant pool. All variable addresses are spilled into constant 93 pools. The constant pools themselves are addressed using PC 94 relative accesses. This only works for the large code model. 95 */ 96 enum aarch64_symbol_type 97 { 98 SYMBOL_SMALL_ABSOLUTE, 99 SYMBOL_SMALL_GOT_28K, 100 SYMBOL_SMALL_GOT_4G, 101 SYMBOL_SMALL_TLSGD, 102 SYMBOL_SMALL_TLSDESC, 103 SYMBOL_SMALL_TLSIE, 104 SYMBOL_TINY_ABSOLUTE, 105 SYMBOL_TINY_GOT, 106 SYMBOL_TINY_TLSIE, 107 SYMBOL_TLSLE12, 108 SYMBOL_TLSLE24, 109 SYMBOL_TLSLE32, 110 SYMBOL_TLSLE48, 111 SYMBOL_FORCE_TO_MEM 112 }; 113 114 /* Classifies the type of an address query. 115 116 ADDR_QUERY_M 117 Query what is valid for an "m" constraint and a memory_operand 118 (the rules are the same for both). 119 120 ADDR_QUERY_LDP_STP 121 Query what is valid for a load/store pair. 122 123 ADDR_QUERY_LDP_STP_N 124 Query what is valid for a load/store pair, but narrow the incoming mode 125 for address checking. This is used for the store_pair_lanes patterns. 126 127 ADDR_QUERY_ANY 128 Query what is valid for at least one memory constraint, which may 129 allow things that "m" doesn't. For example, the SVE LDR and STR 130 addressing modes allow a wider range of immediate offsets than "m" 131 does. */ 132 enum aarch64_addr_query_type { 133 ADDR_QUERY_M, 134 ADDR_QUERY_LDP_STP, 135 ADDR_QUERY_LDP_STP_N, 136 ADDR_QUERY_ANY 137 }; 138 139 /* Enumerates values that can be arbitrarily mixed into a calculation 140 in order to make the result of the calculation unique to its use case. 141 142 AARCH64_SALT_SSP_SET 143 AARCH64_SALT_SSP_TEST 144 Used when calculating the address of the stack protection canary value. 145 There is a separate value for setting and testing the canary, meaning 146 that these two operations produce unique addresses: they are different 147 from each other, and from all other address calculations. 148 149 The main purpose of this is to prevent the SET address being spilled 150 to the stack and reloaded for the TEST, since that would give an 151 attacker the opportunity to change the address of the expected 152 canary value. */ 153 enum aarch64_salt_type { 154 AARCH64_SALT_SSP_SET, 155 AARCH64_SALT_SSP_TEST 156 }; 157 158 /* A set of tuning parameters contains references to size and time 159 cost models and vectors for address cost calculations, register 160 move costs and memory move costs. */ 161 162 /* Scaled addressing modes can vary cost depending on the mode of the 163 value to be loaded/stored. QImode values cannot use scaled 164 addressing modes. */ 165 166 struct scale_addr_mode_cost 167 { 168 const int hi; 169 const int si; 170 const int di; 171 const int ti; 172 }; 173 174 /* Additional cost for addresses. */ 175 struct cpu_addrcost_table 176 { 177 const struct scale_addr_mode_cost addr_scale_costs; 178 const int pre_modify; 179 const int post_modify; 180 const int register_offset; 181 const int register_sextend; 182 const int register_zextend; 183 const int imm_offset; 184 }; 185 186 /* Additional costs for register copies. Cost is for one register. */ 187 struct cpu_regmove_cost 188 { 189 const int GP2GP; 190 const int GP2FP; 191 const int FP2GP; 192 const int FP2FP; 193 }; 194 195 /* Cost for vector insn classes. */ 196 struct cpu_vector_cost 197 { 198 const int scalar_int_stmt_cost; /* Cost of any int scalar operation, 199 excluding load and store. */ 200 const int scalar_fp_stmt_cost; /* Cost of any fp scalar operation, 201 excluding load and store. */ 202 const int scalar_load_cost; /* Cost of scalar load. */ 203 const int scalar_store_cost; /* Cost of scalar store. */ 204 const int vec_int_stmt_cost; /* Cost of any int vector operation, 205 excluding load, store, permute, 206 vector-to-scalar and 207 scalar-to-vector operation. */ 208 const int vec_fp_stmt_cost; /* Cost of any fp vector operation, 209 excluding load, store, permute, 210 vector-to-scalar and 211 scalar-to-vector operation. */ 212 const int vec_permute_cost; /* Cost of permute operation. */ 213 const int vec_to_scalar_cost; /* Cost of vec-to-scalar operation. */ 214 const int scalar_to_vec_cost; /* Cost of scalar-to-vector 215 operation. */ 216 const int vec_align_load_cost; /* Cost of aligned vector load. */ 217 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 218 const int vec_unalign_store_cost; /* Cost of unaligned vector store. */ 219 const int vec_store_cost; /* Cost of vector store. */ 220 const int cond_taken_branch_cost; /* Cost of taken branch. */ 221 const int cond_not_taken_branch_cost; /* Cost of not taken branch. */ 222 }; 223 224 /* Branch costs. */ 225 struct cpu_branch_cost 226 { 227 const int predictable; /* Predictable branch or optimizing for size. */ 228 const int unpredictable; /* Unpredictable branch or optimizing for speed. */ 229 }; 230 231 /* Control approximate alternatives to certain FP operators. */ 232 #define AARCH64_APPROX_MODE(MODE) \ 233 ((MIN_MODE_FLOAT <= (MODE) && (MODE) <= MAX_MODE_FLOAT) \ 234 ? ((uint64_t) 1 << ((MODE) - MIN_MODE_FLOAT)) \ 235 : (MIN_MODE_VECTOR_FLOAT <= (MODE) && (MODE) <= MAX_MODE_VECTOR_FLOAT) \ 236 ? ((uint64_t) 1 << ((MODE) - MIN_MODE_VECTOR_FLOAT \ 237 + MAX_MODE_FLOAT - MIN_MODE_FLOAT + 1)) \ 238 : (0)) 239 #define AARCH64_APPROX_NONE ((uint64_t) 0) 240 #define AARCH64_APPROX_ALL (~(uint64_t) 0) 241 242 /* Allowed modes for approximations. */ 243 struct cpu_approx_modes 244 { 245 const uint64_t division; /* Division. */ 246 const uint64_t sqrt; /* Square root. */ 247 const uint64_t recip_sqrt; /* Reciprocal square root. */ 248 }; 249 250 /* Cache prefetch settings for prefetch-loop-arrays. */ 251 struct cpu_prefetch_tune 252 { 253 const int num_slots; 254 const int l1_cache_size; 255 const int l1_cache_line_size; 256 const int l2_cache_size; 257 /* Whether software prefetch hints should be issued for non-constant 258 strides. */ 259 const bool prefetch_dynamic_strides; 260 /* The minimum constant stride beyond which we should use prefetch 261 hints for. */ 262 const int minimum_stride; 263 const int default_opt_level; 264 }; 265 266 struct tune_params 267 { 268 const struct cpu_cost_table *insn_extra_cost; 269 const struct cpu_addrcost_table *addr_cost; 270 const struct cpu_regmove_cost *regmove_cost; 271 const struct cpu_vector_cost *vec_costs; 272 const struct cpu_branch_cost *branch_costs; 273 const struct cpu_approx_modes *approx_modes; 274 /* Width of the SVE registers or SVE_NOT_IMPLEMENTED if not applicable. 275 Only used for tuning decisions, does not disable VLA 276 vectorization. */ 277 enum aarch64_sve_vector_bits_enum sve_width; 278 int memmov_cost; 279 int issue_rate; 280 unsigned int fusible_ops; 281 const char *function_align; 282 const char *jump_align; 283 const char *loop_align; 284 int int_reassoc_width; 285 int fp_reassoc_width; 286 int vec_reassoc_width; 287 int min_div_recip_mul_sf; 288 int min_div_recip_mul_df; 289 /* Value for aarch64_case_values_threshold; or 0 for the default. */ 290 unsigned int max_case_values; 291 /* An enum specifying how to take into account CPU autoprefetch capabilities 292 during instruction scheduling: 293 - AUTOPREFETCHER_OFF: Do not take autoprefetch capabilities into account. 294 - AUTOPREFETCHER_WEAK: Attempt to sort sequences of loads/store in order of 295 offsets but allow the pipeline hazard recognizer to alter that order to 296 maximize multi-issue opportunities. 297 - AUTOPREFETCHER_STRONG: Attempt to sort sequences of loads/store in order of 298 offsets and prefer this even if it restricts multi-issue opportunities. */ 299 300 enum aarch64_autoprefetch_model 301 { 302 AUTOPREFETCHER_OFF, 303 AUTOPREFETCHER_WEAK, 304 AUTOPREFETCHER_STRONG 305 } autoprefetcher_model; 306 307 unsigned int extra_tuning_flags; 308 309 /* Place prefetch struct pointer at the end to enable type checking 310 errors when tune_params misses elements (e.g., from erroneous merges). */ 311 const struct cpu_prefetch_tune *prefetch; 312 }; 313 314 /* Classifies an address. 315 316 ADDRESS_REG_IMM 317 A simple base register plus immediate offset. 318 319 ADDRESS_REG_WB 320 A base register indexed by immediate offset with writeback. 321 322 ADDRESS_REG_REG 323 A base register indexed by (optionally scaled) register. 324 325 ADDRESS_REG_UXTW 326 A base register indexed by (optionally scaled) zero-extended register. 327 328 ADDRESS_REG_SXTW 329 A base register indexed by (optionally scaled) sign-extended register. 330 331 ADDRESS_LO_SUM 332 A LO_SUM rtx with a base register and "LO12" symbol relocation. 333 334 ADDRESS_SYMBOLIC: 335 A constant symbolic address, in pc-relative literal pool. */ 336 337 enum aarch64_address_type { 338 ADDRESS_REG_IMM, 339 ADDRESS_REG_WB, 340 ADDRESS_REG_REG, 341 ADDRESS_REG_UXTW, 342 ADDRESS_REG_SXTW, 343 ADDRESS_LO_SUM, 344 ADDRESS_SYMBOLIC 345 }; 346 347 /* Address information. */ 348 struct aarch64_address_info { 349 enum aarch64_address_type type; 350 rtx base; 351 rtx offset; 352 poly_int64 const_offset; 353 int shift; 354 enum aarch64_symbol_type symbol_type; 355 }; 356 357 #define AARCH64_FUSION_PAIR(x, name) \ 358 AARCH64_FUSE_##name##_index, 359 /* Supported fusion operations. */ 360 enum aarch64_fusion_pairs_index 361 { 362 #include "aarch64-fusion-pairs.def" 363 AARCH64_FUSE_index_END 364 }; 365 366 #define AARCH64_FUSION_PAIR(x, name) \ 367 AARCH64_FUSE_##name = (1u << AARCH64_FUSE_##name##_index), 368 /* Supported fusion operations. */ 369 enum aarch64_fusion_pairs 370 { 371 AARCH64_FUSE_NOTHING = 0, 372 #include "aarch64-fusion-pairs.def" 373 AARCH64_FUSE_ALL = (1u << AARCH64_FUSE_index_END) - 1 374 }; 375 376 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \ 377 AARCH64_EXTRA_TUNE_##name##_index, 378 /* Supported tuning flags indexes. */ 379 enum aarch64_extra_tuning_flags_index 380 { 381 #include "aarch64-tuning-flags.def" 382 AARCH64_EXTRA_TUNE_index_END 383 }; 384 385 386 #define AARCH64_EXTRA_TUNING_OPTION(x, name) \ 387 AARCH64_EXTRA_TUNE_##name = (1u << AARCH64_EXTRA_TUNE_##name##_index), 388 /* Supported tuning flags. */ 389 enum aarch64_extra_tuning_flags 390 { 391 AARCH64_EXTRA_TUNE_NONE = 0, 392 #include "aarch64-tuning-flags.def" 393 AARCH64_EXTRA_TUNE_ALL = (1u << AARCH64_EXTRA_TUNE_index_END) - 1 394 }; 395 396 /* Enum describing the various ways that the 397 aarch64_parse_{arch,tune,cpu,extension} functions can fail. 398 This way their callers can choose what kind of error to give. */ 399 400 enum aarch64_parse_opt_result 401 { 402 AARCH64_PARSE_OK, /* Parsing was successful. */ 403 AARCH64_PARSE_MISSING_ARG, /* Missing argument. */ 404 AARCH64_PARSE_INVALID_FEATURE, /* Invalid feature modifier. */ 405 AARCH64_PARSE_INVALID_ARG /* Invalid arch, tune, cpu arg. */ 406 }; 407 408 /* Enum to distinguish which type of check is to be done in 409 aarch64_simd_valid_immediate. This is used as a bitmask where 410 AARCH64_CHECK_MOV has both bits set. Thus AARCH64_CHECK_MOV will 411 perform all checks. Adding new types would require changes accordingly. */ 412 enum simd_immediate_check { 413 AARCH64_CHECK_ORR = 1 << 0, 414 AARCH64_CHECK_BIC = 1 << 1, 415 AARCH64_CHECK_MOV = AARCH64_CHECK_ORR | AARCH64_CHECK_BIC 416 }; 417 418 /* The key type that -msign-return-address should use. */ 419 enum aarch64_key_type { 420 AARCH64_KEY_A, 421 AARCH64_KEY_B 422 }; 423 424 extern enum aarch64_key_type aarch64_ra_sign_key; 425 426 extern struct tune_params aarch64_tune_params; 427 428 /* The available SVE predicate patterns, known in the ACLE as "svpattern". */ 429 #define AARCH64_FOR_SVPATTERN(T) \ 430 T (POW2, pow2, 0) \ 431 T (VL1, vl1, 1) \ 432 T (VL2, vl2, 2) \ 433 T (VL3, vl3, 3) \ 434 T (VL4, vl4, 4) \ 435 T (VL5, vl5, 5) \ 436 T (VL6, vl6, 6) \ 437 T (VL7, vl7, 7) \ 438 T (VL8, vl8, 8) \ 439 T (VL16, vl16, 9) \ 440 T (VL32, vl32, 10) \ 441 T (VL64, vl64, 11) \ 442 T (VL128, vl128, 12) \ 443 T (VL256, vl256, 13) \ 444 T (MUL4, mul4, 29) \ 445 T (MUL3, mul3, 30) \ 446 T (ALL, all, 31) 447 448 /* The available SVE prefetch operations, known in the ACLE as "svprfop". */ 449 #define AARCH64_FOR_SVPRFOP(T) \ 450 T (PLDL1KEEP, pldl1keep, 0) \ 451 T (PLDL1STRM, pldl1strm, 1) \ 452 T (PLDL2KEEP, pldl2keep, 2) \ 453 T (PLDL2STRM, pldl2strm, 3) \ 454 T (PLDL3KEEP, pldl3keep, 4) \ 455 T (PLDL3STRM, pldl3strm, 5) \ 456 T (PSTL1KEEP, pstl1keep, 8) \ 457 T (PSTL1STRM, pstl1strm, 9) \ 458 T (PSTL2KEEP, pstl2keep, 10) \ 459 T (PSTL2STRM, pstl2strm, 11) \ 460 T (PSTL3KEEP, pstl3keep, 12) \ 461 T (PSTL3STRM, pstl3strm, 13) 462 463 #define AARCH64_SVENUM(UPPER, LOWER, VALUE) AARCH64_SV_##UPPER = VALUE, 464 enum aarch64_svpattern { 465 AARCH64_FOR_SVPATTERN (AARCH64_SVENUM) 466 AARCH64_NUM_SVPATTERNS 467 }; 468 469 enum aarch64_svprfop { 470 AARCH64_FOR_SVPRFOP (AARCH64_SVENUM) 471 AARCH64_NUM_SVPRFOPS 472 }; 473 #undef AARCH64_SVENUM 474 475 /* It's convenient to divide the built-in function codes into groups, 476 rather than having everything in a single enum. This type enumerates 477 those groups. */ 478 enum aarch64_builtin_class 479 { 480 AARCH64_BUILTIN_GENERAL, 481 AARCH64_BUILTIN_SVE 482 }; 483 484 /* Built-in function codes are structured so that the low 485 AARCH64_BUILTIN_SHIFT bits contain the aarch64_builtin_class 486 and the upper bits contain a group-specific subcode. */ 487 const unsigned int AARCH64_BUILTIN_SHIFT = 1; 488 489 /* Mask that selects the aarch64_builtin_class part of a function code. */ 490 const unsigned int AARCH64_BUILTIN_CLASS = (1 << AARCH64_BUILTIN_SHIFT) - 1; 491 492 void aarch64_post_cfi_startproc (void); 493 poly_int64 aarch64_initial_elimination_offset (unsigned, unsigned); 494 int aarch64_get_condition_code (rtx); 495 bool aarch64_address_valid_for_prefetch_p (rtx, bool); 496 bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode); 497 unsigned HOST_WIDE_INT aarch64_and_split_imm1 (HOST_WIDE_INT val_in); 498 unsigned HOST_WIDE_INT aarch64_and_split_imm2 (HOST_WIDE_INT val_in); 499 bool aarch64_and_bitmask_imm (unsigned HOST_WIDE_INT val_in, machine_mode mode); 500 int aarch64_branch_cost (bool, bool); 501 enum aarch64_symbol_type aarch64_classify_symbolic_expression (rtx); 502 opt_machine_mode aarch64_vq_mode (scalar_mode); 503 opt_machine_mode aarch64_full_sve_mode (scalar_mode); 504 bool aarch64_can_const_movi_rtx_p (rtx x, machine_mode mode); 505 bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT); 506 bool aarch64_const_vec_all_same_in_range_p (rtx, HOST_WIDE_INT, 507 HOST_WIDE_INT); 508 bool aarch64_constant_address_p (rtx); 509 bool aarch64_emit_approx_div (rtx, rtx, rtx); 510 bool aarch64_emit_approx_sqrt (rtx, rtx, bool); 511 void aarch64_expand_call (rtx, rtx, rtx, bool); 512 bool aarch64_expand_cpymem (rtx *); 513 bool aarch64_float_const_zero_rtx_p (rtx); 514 bool aarch64_float_const_rtx_p (rtx); 515 bool aarch64_function_arg_regno_p (unsigned); 516 bool aarch64_fusion_enabled_p (enum aarch64_fusion_pairs); 517 bool aarch64_gen_cpymemqi (rtx *); 518 bool aarch64_is_extend_from_extract (scalar_int_mode, rtx, rtx); 519 bool aarch64_is_long_call_p (rtx); 520 bool aarch64_is_noplt_call_p (rtx); 521 bool aarch64_label_mentioned_p (rtx); 522 void aarch64_declare_function_name (FILE *, const char*, tree); 523 void aarch64_asm_output_alias (FILE *, const tree, const tree); 524 void aarch64_asm_output_external (FILE *, tree, const char*); 525 bool aarch64_legitimate_pic_operand_p (rtx); 526 bool aarch64_mask_and_shift_for_ubfiz_p (scalar_int_mode, rtx, rtx); 527 bool aarch64_masks_and_shift_for_bfi_p (scalar_int_mode, unsigned HOST_WIDE_INT, 528 unsigned HOST_WIDE_INT, 529 unsigned HOST_WIDE_INT); 530 bool aarch64_zero_extend_const_eq (machine_mode, rtx, machine_mode, rtx); 531 bool aarch64_move_imm (HOST_WIDE_INT, machine_mode); 532 machine_mode aarch64_sve_int_mode (machine_mode); 533 opt_machine_mode aarch64_sve_pred_mode (unsigned int); 534 machine_mode aarch64_sve_pred_mode (machine_mode); 535 opt_machine_mode aarch64_sve_data_mode (scalar_mode, poly_uint64); 536 bool aarch64_sve_mode_p (machine_mode); 537 HOST_WIDE_INT aarch64_fold_sve_cnt_pat (aarch64_svpattern, unsigned int); 538 bool aarch64_sve_cnt_immediate_p (rtx); 539 bool aarch64_sve_scalar_inc_dec_immediate_p (rtx); 540 bool aarch64_sve_addvl_addpl_immediate_p (rtx); 541 bool aarch64_sve_vector_inc_dec_immediate_p (rtx); 542 int aarch64_add_offset_temporaries (rtx); 543 void aarch64_split_add_offset (scalar_int_mode, rtx, rtx, rtx, rtx, rtx); 544 bool aarch64_mov_operand_p (rtx, machine_mode); 545 rtx aarch64_reverse_mask (machine_mode, unsigned int); 546 bool aarch64_offset_7bit_signed_scaled_p (machine_mode, poly_int64); 547 bool aarch64_offset_9bit_signed_unscaled_p (machine_mode, poly_int64); 548 char *aarch64_output_sve_prefetch (const char *, rtx, const char *); 549 char *aarch64_output_sve_cnt_immediate (const char *, const char *, rtx); 550 char *aarch64_output_sve_cnt_pat_immediate (const char *, const char *, rtx *); 551 char *aarch64_output_sve_scalar_inc_dec (rtx); 552 char *aarch64_output_sve_addvl_addpl (rtx); 553 char *aarch64_output_sve_vector_inc_dec (const char *, rtx); 554 char *aarch64_output_scalar_simd_mov_immediate (rtx, scalar_int_mode); 555 char *aarch64_output_simd_mov_immediate (rtx, unsigned, 556 enum simd_immediate_check w = AARCH64_CHECK_MOV); 557 char *aarch64_output_sve_mov_immediate (rtx); 558 char *aarch64_output_sve_ptrues (rtx); 559 bool aarch64_pad_reg_upward (machine_mode, const_tree, bool); 560 bool aarch64_regno_ok_for_base_p (int, bool); 561 bool aarch64_regno_ok_for_index_p (int, bool); 562 bool aarch64_reinterpret_float_as_int (rtx value, unsigned HOST_WIDE_INT *fail); 563 bool aarch64_simd_check_vect_par_cnst_half (rtx op, machine_mode mode, 564 bool high); 565 bool aarch64_simd_scalar_immediate_valid_for_move (rtx, scalar_int_mode); 566 bool aarch64_simd_shift_imm_p (rtx, machine_mode, bool); 567 bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *); 568 bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *, 569 enum simd_immediate_check w = AARCH64_CHECK_MOV); 570 rtx aarch64_check_zero_based_sve_index_immediate (rtx); 571 bool aarch64_sve_index_immediate_p (rtx); 572 bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool); 573 bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool); 574 bool aarch64_sve_bitmask_immediate_p (rtx); 575 bool aarch64_sve_dup_immediate_p (rtx); 576 bool aarch64_sve_cmp_immediate_p (rtx, bool); 577 bool aarch64_sve_float_arith_immediate_p (rtx, bool); 578 bool aarch64_sve_float_mul_immediate_p (rtx); 579 bool aarch64_split_dimode_const_store (rtx, rtx); 580 bool aarch64_symbolic_address_p (rtx); 581 bool aarch64_uimm12_shift (HOST_WIDE_INT); 582 int aarch64_movk_shift (const wide_int_ref &, const wide_int_ref &); 583 bool aarch64_use_return_insn_p (void); 584 const char *aarch64_output_casesi (rtx *); 585 586 unsigned int aarch64_tlsdesc_abi_id (); 587 enum aarch64_symbol_type aarch64_classify_symbol (rtx, HOST_WIDE_INT); 588 enum aarch64_symbol_type aarch64_classify_tls_symbol (rtx); 589 enum reg_class aarch64_regno_regclass (unsigned); 590 int aarch64_asm_preferred_eh_data_format (int, int); 591 int aarch64_fpconst_pow_of_2 (rtx); 592 int aarch64_fpconst_pow2_recip (rtx); 593 machine_mode aarch64_hard_regno_caller_save_mode (unsigned, unsigned, 594 machine_mode); 595 int aarch64_uxt_size (int, HOST_WIDE_INT); 596 int aarch64_vec_fpconst_pow_of_2 (rtx); 597 rtx aarch64_eh_return_handler_rtx (void); 598 rtx aarch64_mask_from_zextract_ops (rtx, rtx); 599 const char *aarch64_output_move_struct (rtx *operands); 600 rtx aarch64_return_addr_rtx (void); 601 rtx aarch64_return_addr (int, rtx); 602 rtx aarch64_simd_gen_const_vector_dup (machine_mode, HOST_WIDE_INT); 603 bool aarch64_simd_mem_operand_p (rtx); 604 bool aarch64_sve_ld1r_operand_p (rtx); 605 bool aarch64_sve_ld1rq_operand_p (rtx); 606 bool aarch64_sve_ld1ro_operand_p (rtx, scalar_mode); 607 bool aarch64_sve_ldff1_operand_p (rtx); 608 bool aarch64_sve_ldnf1_operand_p (rtx); 609 bool aarch64_sve_ldr_operand_p (rtx); 610 bool aarch64_sve_prefetch_operand_p (rtx, machine_mode); 611 bool aarch64_sve_struct_memory_operand_p (rtx); 612 rtx aarch64_simd_vect_par_cnst_half (machine_mode, int, bool); 613 rtx aarch64_gen_stepped_int_parallel (unsigned int, int, int); 614 bool aarch64_stepped_int_parallel_p (rtx, int); 615 rtx aarch64_tls_get_addr (void); 616 unsigned aarch64_dbx_register_number (unsigned); 617 unsigned aarch64_trampoline_size (void); 618 void aarch64_asm_output_labelref (FILE *, const char *); 619 void aarch64_cpu_cpp_builtins (cpp_reader *); 620 const char * aarch64_gen_far_branch (rtx *, int, const char *, const char *); 621 const char * aarch64_output_probe_stack_range (rtx, rtx); 622 const char * aarch64_output_probe_sve_stack_clash (rtx, rtx, rtx, rtx); 623 void aarch64_err_no_fpadvsimd (machine_mode); 624 void aarch64_expand_epilogue (bool); 625 rtx aarch64_ptrue_all (unsigned int); 626 opt_machine_mode aarch64_ptrue_all_mode (rtx); 627 rtx aarch64_convert_sve_data_to_pred (rtx, machine_mode, rtx); 628 rtx aarch64_expand_sve_dupq (rtx, machine_mode, rtx); 629 void aarch64_expand_mov_immediate (rtx, rtx); 630 rtx aarch64_stack_protect_canary_mem (machine_mode, rtx, aarch64_salt_type); 631 rtx aarch64_ptrue_reg (machine_mode); 632 rtx aarch64_pfalse_reg (machine_mode); 633 bool aarch64_sve_same_pred_for_ptest_p (rtx *, rtx *); 634 void aarch64_emit_sve_pred_move (rtx, rtx, rtx); 635 void aarch64_expand_sve_mem_move (rtx, rtx, machine_mode); 636 bool aarch64_maybe_expand_sve_subreg_move (rtx, rtx); 637 rtx aarch64_replace_reg_mode (rtx, machine_mode); 638 void aarch64_split_sve_subreg_move (rtx, rtx, rtx); 639 void aarch64_expand_prologue (void); 640 void aarch64_expand_vector_init (rtx, rtx); 641 void aarch64_sve_expand_vector_init (rtx, rtx); 642 void aarch64_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, 643 const_tree, unsigned, bool = false); 644 void aarch64_init_expanders (void); 645 void aarch64_init_simd_builtins (void); 646 void aarch64_emit_call_insn (rtx); 647 void aarch64_register_pragmas (void); 648 void aarch64_relayout_simd_types (void); 649 void aarch64_reset_previous_fndecl (void); 650 bool aarch64_return_address_signing_enabled (void); 651 bool aarch64_bti_enabled (void); 652 void aarch64_save_restore_target_globals (tree); 653 void aarch64_addti_scratch_regs (rtx, rtx, rtx *, 654 rtx *, rtx *, 655 rtx *, rtx *, 656 rtx *); 657 void aarch64_subvti_scratch_regs (rtx, rtx, rtx *, 658 rtx *, rtx *, 659 rtx *, rtx *, rtx *); 660 void aarch64_expand_subvti (rtx, rtx, rtx, 661 rtx, rtx, rtx, rtx, bool); 662 663 664 /* Initialize builtins for SIMD intrinsics. */ 665 void init_aarch64_simd_builtins (void); 666 667 void aarch64_simd_emit_reg_reg_move (rtx *, machine_mode, unsigned int); 668 669 /* Expand builtins for SIMD intrinsics. */ 670 rtx aarch64_simd_expand_builtin (int, tree, rtx); 671 672 void aarch64_simd_lane_bounds (rtx, HOST_WIDE_INT, HOST_WIDE_INT, const_tree); 673 rtx aarch64_endian_lane_rtx (machine_mode, unsigned int); 674 675 void aarch64_split_128bit_move (rtx, rtx); 676 677 bool aarch64_split_128bit_move_p (rtx, rtx); 678 679 bool aarch64_mov128_immediate (rtx); 680 681 void aarch64_split_simd_combine (rtx, rtx, rtx); 682 683 void aarch64_split_simd_move (rtx, rtx); 684 685 /* Check for a legitimate floating point constant for FMOV. */ 686 bool aarch64_float_const_representable_p (rtx); 687 688 extern int aarch64_epilogue_uses (int); 689 690 #if defined (RTX_CODE) 691 void aarch64_gen_unlikely_cbranch (enum rtx_code, machine_mode cc_mode, 692 rtx label_ref); 693 bool aarch64_legitimate_address_p (machine_mode, rtx, bool, 694 aarch64_addr_query_type = ADDR_QUERY_M); 695 machine_mode aarch64_select_cc_mode (RTX_CODE, rtx, rtx); 696 rtx aarch64_gen_compare_reg (RTX_CODE, rtx, rtx); 697 rtx aarch64_load_tp (rtx); 698 699 void aarch64_expand_compare_and_swap (rtx op[]); 700 void aarch64_split_compare_and_swap (rtx op[]); 701 702 void aarch64_split_atomic_op (enum rtx_code, rtx, rtx, rtx, rtx, rtx, rtx); 703 704 bool aarch64_gen_adjusted_ldpstp (rtx *, bool, scalar_mode, RTX_CODE); 705 706 void aarch64_expand_sve_vec_cmp_int (rtx, rtx_code, rtx, rtx); 707 bool aarch64_expand_sve_vec_cmp_float (rtx, rtx_code, rtx, rtx, bool); 708 void aarch64_expand_sve_vcond (machine_mode, machine_mode, rtx *); 709 710 bool aarch64_prepare_sve_int_fma (rtx *, rtx_code); 711 bool aarch64_prepare_sve_cond_int_fma (rtx *, rtx_code); 712 #endif /* RTX_CODE */ 713 714 bool aarch64_process_target_attr (tree); 715 void aarch64_override_options_internal (struct gcc_options *); 716 717 const char *aarch64_general_mangle_builtin_type (const_tree); 718 void aarch64_general_init_builtins (void); 719 tree aarch64_general_fold_builtin (unsigned int, tree, unsigned int, tree *); 720 gimple *aarch64_general_gimple_fold_builtin (unsigned int, gcall *); 721 rtx aarch64_general_expand_builtin (unsigned int, tree, rtx, int); 722 tree aarch64_general_builtin_decl (unsigned, bool); 723 tree aarch64_general_builtin_rsqrt (unsigned int); 724 tree aarch64_builtin_vectorized_function (unsigned int, tree, tree); 725 726 namespace aarch64_sve { 727 void init_builtins (); 728 void handle_arm_sve_h (); 729 tree builtin_decl (unsigned, bool); 730 bool builtin_type_p (const_tree); 731 bool builtin_type_p (const_tree, unsigned int *, unsigned int *); 732 const char *mangle_builtin_type (const_tree); 733 tree resolve_overloaded_builtin (location_t, unsigned int, 734 vec<tree, va_gc> *); 735 bool check_builtin_call (location_t, vec<location_t>, unsigned int, 736 tree, unsigned int, tree *); 737 gimple *gimple_fold_builtin (unsigned int, gimple_stmt_iterator *, gcall *); 738 rtx expand_builtin (unsigned int, tree, rtx); 739 tree handle_arm_sve_vector_bits_attribute (tree *, tree, tree, int, bool *); 740 #ifdef GCC_TARGET_H 741 bool verify_type_context (location_t, type_context_kind, const_tree, bool); 742 #endif 743 } 744 745 extern void aarch64_split_combinev16qi (rtx operands[3]); 746 extern void aarch64_expand_vec_perm (rtx, rtx, rtx, rtx, unsigned int); 747 extern void aarch64_expand_sve_vec_perm (rtx, rtx, rtx, rtx); 748 extern bool aarch64_madd_needs_nop (rtx_insn *); 749 extern void aarch64_final_prescan_insn (rtx_insn *); 750 void aarch64_atomic_assign_expand_fenv (tree *, tree *, tree *); 751 int aarch64_ccmp_mode_to_code (machine_mode mode); 752 753 bool extract_base_offset_in_addr (rtx mem, rtx *base, rtx *offset); 754 bool aarch64_operands_ok_for_ldpstp (rtx *, bool, machine_mode); 755 bool aarch64_operands_adjust_ok_for_ldpstp (rtx *, bool, scalar_mode); 756 void aarch64_swap_ldrstr_operands (rtx *, bool); 757 758 extern void aarch64_asm_output_pool_epilogue (FILE *, const char *, 759 tree, HOST_WIDE_INT); 760 761 762 extern bool aarch64_classify_address (struct aarch64_address_info *, rtx, 763 machine_mode, bool, 764 aarch64_addr_query_type = ADDR_QUERY_M); 765 766 /* Defined in common/config/aarch64-common.c. */ 767 bool aarch64_handle_option (struct gcc_options *, struct gcc_options *, 768 const struct cl_decoded_option *, location_t); 769 const char *aarch64_rewrite_selected_cpu (const char *name); 770 enum aarch64_parse_opt_result aarch64_parse_extension (const char *, 771 uint64_t *, 772 std::string *); 773 void aarch64_get_all_extension_candidates (auto_vec<const char *> *candidates); 774 std::string aarch64_get_extension_string_for_isa_flags (uint64_t, uint64_t); 775 776 /* Defined in aarch64-d.c */ 777 extern void aarch64_d_target_versions (void); 778 779 rtl_opt_pass *make_pass_fma_steering (gcc::context *); 780 rtl_opt_pass *make_pass_track_speculation (gcc::context *); 781 rtl_opt_pass *make_pass_tag_collision_avoidance (gcc::context *); 782 rtl_opt_pass *make_pass_insert_bti (gcc::context *ctxt); 783 784 poly_uint64 aarch64_regmode_natural_size (machine_mode); 785 786 bool aarch64_high_bits_all_ones_p (HOST_WIDE_INT); 787 788 struct atomic_ool_names 789 { 790 const char *str[5][4]; 791 }; 792 793 rtx aarch64_atomic_ool_func(machine_mode mode, rtx model_rtx, 794 const atomic_ool_names *names); 795 extern const atomic_ool_names aarch64_ool_swp_names; 796 extern const atomic_ool_names aarch64_ool_ldadd_names; 797 extern const atomic_ool_names aarch64_ool_ldset_names; 798 extern const atomic_ool_names aarch64_ool_ldclr_names; 799 extern const atomic_ool_names aarch64_ool_ldeor_names; 800 801 tree aarch64_resolve_overloaded_builtin_general (location_t, tree, void *); 802 803 const char *aarch64_sls_barrier (int); 804 const char *aarch64_indirect_call_asm (rtx); 805 extern bool aarch64_harden_sls_retbr_p (void); 806 extern bool aarch64_harden_sls_blr_p (void); 807 808 #endif /* GCC_AARCH64_PROTOS_H */ 809