1;; Predicate definitions for Synopsys DesignWare ARC. 2;; Copyright (C) 2007-2021 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_predicate "dest_reg_operand" 21 (match_code "reg,subreg") 22{ 23 return register_operand (op, mode); 24}) 25 26(define_predicate "mpy_dest_reg_operand" 27 (match_code "reg,subreg") 28{ 29 return register_operand (op, mode); 30}) 31 32 33;; Returns 1 if OP is a symbol reference. 34(define_predicate "symbolic_operand" 35 (match_code "symbol_ref, label_ref, const") 36) 37 38;; Acceptable arguments to the call insn. 39(define_predicate "call_address_operand" 40 (ior (match_code "const_int, reg") 41 (match_operand 0 "symbolic_operand") 42 (match_test "CONSTANT_P (op) 43 && arc_legitimate_constant_p (VOIDmode, op)")) 44) 45 46(define_predicate "call_operand" 47 (and (match_code "mem") 48 (match_test "call_address_operand (XEXP (op, 0), mode)")) 49) 50 51;; Return true if OP is a unsigned 6-bit immediate (u6) value. 52(define_predicate "u6_immediate_operand" 53 (and (match_code "const_int") 54 (match_test "UNSIGNED_INT6 (INTVAL (op))")) 55) 56 57;; Return true if OP is a short immediate (shimm) value. 58(define_predicate "short_immediate_operand" 59 (and (match_code "const_int") 60 (match_test "SMALL_INT (INTVAL (op))")) 61) 62 63(define_predicate "p2_immediate_operand" 64 (and (match_code "const_int") 65 (match_test "((INTVAL (op) - 1) & INTVAL (op)) == 0") 66 (match_test "INTVAL (op)")) 67) 68 69;; Return true if OP will require a long immediate (limm) value. 70;; This is currently only used when calculating length attributes. 71(define_predicate "long_immediate_operand" 72 (match_code "symbol_ref, label_ref, const, const_double, const_int") 73{ 74 switch (GET_CODE (op)) 75 { 76 case SYMBOL_REF : 77 case LABEL_REF : 78 case CONST : 79 return 1; 80 case CONST_INT : 81 return !SIGNED_INT12 (INTVAL (op)); 82 case CONST_DOUBLE : 83 /* These can happen because large unsigned 32 bit constants are 84 represented this way (the multiplication patterns can cause these 85 to be generated). They also occur for SFmode values. */ 86 return 1; 87 default: 88 break; 89 } 90 return 0; 91} 92) 93 94;; Return true if OP is a MEM that when used as a load or store address will 95;; require an 8 byte insn. 96;; Load and store instructions don't allow the same possibilities but they're 97;; similar enough that this one function will do. 98;; This is currently only used when calculating length attributes. */ 99(define_predicate "long_immediate_loadstore_operand" 100 (match_code "mem") 101{ 102 int size = GET_MODE_SIZE (GET_MODE (op)); 103 104 op = XEXP (op, 0); 105 if (TARGET_NPS_CMEM && cmem_address (op, SImode)) 106 return 0; 107 switch (GET_CODE (op)) 108 { 109 case SYMBOL_REF : 110 case LABEL_REF : 111 case CONST : 112 return 1; 113 case CONST_INT : 114 /* This must be handled as "st c,[limm]". Ditto for load. 115 Technically, the assembler could translate some possibilities to 116 "st c,[limm/2 + limm/2]" if limm/2 will fit in a shimm, but we don't 117 assume that it does. */ 118 return 1; 119 case CONST_DOUBLE : 120 /* These can happen because large unsigned 32 bit constants are 121 represented this way (the multiplication patterns can cause these 122 to be generated). They also occur for SFmode values. */ 123 return 1; 124 case REG : 125 return 0; 126 case PLUS : 127 { 128 rtx x = XEXP (op, 1); 129 130 if ((GET_CODE (XEXP (op, 0)) == MULT) 131 && REG_P (XEXP (XEXP (op, 0), 0)) 132 && CONSTANT_P (x)) 133 return 1; 134 135 if (GET_CODE (x) == CONST) 136 { 137 x = XEXP (x, 0); 138 if (GET_CODE (x) == PLUS) 139 x = XEXP (x, 0); 140 } 141 if (CONST_INT_P (x)) 142 return (!SMALL_INT (INTVAL (x)) 143 && (size <= 1 || size > 4 144 || (INTVAL (x) & (size - 1)) != 0 145 || !SMALL_INT (INTVAL (x) / size))); 146 else if (GET_CODE (x) == SYMBOL_REF) 147 return TARGET_NO_SDATA_SET || !SYMBOL_REF_SMALL_P (x); 148 return 0; 149 } 150 default: 151 break; 152 } 153 return 0; 154} 155) 156 157;; Return true if OP is any of R0-R3,R12-R15 for ARCompact 16-bit 158;; instructions 159(define_predicate "compact_register_operand" 160 (match_code "reg, subreg") 161 { 162 if ((GET_MODE (op) != mode) && (mode != VOIDmode)) 163 return 0; 164 165 return (GET_CODE (op) == REG) 166 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 167 || COMPACT_GP_REG_P (REGNO (op))) ; 168 } 169) 170 171(define_predicate "compact_hreg_operand" 172 (match_code "reg, subreg") 173 { 174 if ((GET_MODE (op) != mode) && (mode != VOIDmode)) 175 return 0; 176 177 return (GET_CODE (op) == REG) 178 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 179 || (TARGET_V2 && REGNO (op) <= 31 && REGNO (op) != 30) 180 || !TARGET_V2); 181 } 182) 183 184;; Return true if OP is an acceptable memory operand for ARCompact 185;; 16-bit store instructions 186(define_predicate "compact_store_memory_operand" 187 (match_code "mem") 188{ 189 rtx addr, plus0, plus1; 190 int size, off; 191 192 if (mode == VOIDmode) 193 mode = GET_MODE (op); 194 195 /* .di instructions have no 16-bit form. */ 196 if (MEM_VOLATILE_P (op) && !TARGET_VOLATILE_CACHE_SET) 197 return 0; 198 199 /* likewise for uncached types. */ 200 if (arc_is_uncached_mem_p (op)) 201 return 0; 202 203 size = GET_MODE_SIZE (mode); 204 205 /* dword operations really put out 2 instructions, so eliminate them. */ 206 if (size > UNITS_PER_WORD) 207 return 0; 208 209 /* Decode the address now. */ 210 addr = XEXP (op, 0); 211 switch (GET_CODE (addr)) 212 { 213 case REG: 214 return (REGNO (addr) >= FIRST_PSEUDO_REGISTER 215 || COMPACT_GP_REG_P (REGNO (addr)) 216 || (SP_REG_P (REGNO (addr)) && (size != 2))); 217 /* stw_s does not support SP as a parameter. */ 218 case PLUS: 219 plus0 = XEXP (addr, 0); 220 plus1 = XEXP (addr, 1); 221 222 if ((GET_CODE (plus0) == REG) 223 && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) 224 || COMPACT_GP_REG_P (REGNO (plus0))) 225 && (GET_CODE (plus1) == CONST_INT)) 226 { 227 off = INTVAL (plus1); 228 229 /* Negative offset is not supported in 16-bit load/store insns. */ 230 if (off < 0) 231 return 0; 232 233 switch (size) 234 { 235 case 1: 236 return (off < 32); 237 case 2: 238 return ((off < 64) && (off % 2 == 0)); 239 case 4: 240 return ((off < 128) && (off % 4 == 0)); 241 } 242 } 243 244 if ((GET_CODE (plus0) == REG) 245 && ((REGNO (plus0) >= FIRST_PSEUDO_REGISTER) 246 || SP_REG_P (REGNO (plus0))) 247 && (GET_CODE (plus1) == CONST_INT)) 248 { 249 off = INTVAL (plus1); 250 251 return ((size != 2) && (off >= 0 && off < 128) && (off % 4 == 0)); 252 } 253 default: 254 break; 255 } 256 return 0; 257 } 258) 259 260;; Return true if OP is an acceptable argument for a single word 261;; move source. 262(define_predicate "move_src_operand" 263 (match_code "symbol_ref, label_ref, const, const_int, const_double, reg, subreg, mem") 264{ 265 switch (GET_CODE (op)) 266 { 267 case SYMBOL_REF : 268 if (SYMBOL_REF_TLS_MODEL (op)) 269 return 0; 270 return 1; 271 case LABEL_REF : 272 return 1; 273 case CONST : 274 return arc_legitimate_constant_p (mode, op); 275 case CONST_INT : 276 return (LARGE_INT (INTVAL (op))); 277 case CONST_DOUBLE : 278 /* We can handle DImode integer constants in SImode if the value 279 (signed or unsigned) will fit in 32 bits. This is needed because 280 large unsigned 32 bit constants are represented as CONST_DOUBLEs. */ 281 if (mode == SImode) 282 return arc_double_limm_p (op); 283 /* We can handle 32 bit floating point constants. */ 284 if (mode == SFmode) 285 return GET_MODE (op) == SFmode; 286 return 0; 287 case REG : 288 if (REGNO (op) == LP_COUNT) 289 return 1; 290 return register_operand (op, mode); 291 case SUBREG : 292 /* (subreg (mem ...) ...) can occur here if the inner part was once a 293 pseudo-reg and is now a stack slot. */ 294 if (GET_CODE (SUBREG_REG (op)) == MEM) 295 return address_operand (XEXP (SUBREG_REG (op), 0), mode); 296 else 297 return register_operand (op, mode); 298 case MEM : 299 return address_operand (XEXP (op, 0), mode); 300 default : 301 return 0; 302 } 303} 304) 305 306;; Return true if OP is an acceptable argument for a double word 307;; move source. 308(define_predicate "move_double_src_operand" 309 (match_code "reg, subreg, mem, const_int, const_double") 310{ 311 switch (GET_CODE (op)) 312 { 313 case REG : 314 return register_operand (op, mode); 315 case SUBREG : 316 /* (subreg (mem ...) ...) can occur here if the inner part was once a 317 pseudo-reg and is now a stack slot. */ 318 if (GET_CODE (SUBREG_REG (op)) == MEM) 319 return address_operand (XEXP (SUBREG_REG (op), 0), mode); 320 else 321 return register_operand (op, mode); 322 case MEM : 323 return address_operand (XEXP (op, 0), mode); 324 case CONST_INT : 325 case CONST_DOUBLE : 326 return 1; 327 default : 328 return 0; 329 } 330} 331) 332 333;; Return true if OP is an acceptable argument for a move destination. 334(define_predicate "move_dest_operand" 335 (match_code "reg, subreg, mem") 336{ 337 switch (GET_CODE (op)) 338 { 339 case REG : 340 /* Program Counter register cannot be the target of a move. It is 341 a readonly register. */ 342 if (REGNO (op) == PCL_REG) 343 return 0; 344 else if (TARGET_MULMAC_32BY16_SET 345 && (REGNO (op) == MUL32x16_REG || REGNO (op) == R57_REG)) 346 return 0; 347 else if (TARGET_MUL64_SET 348 && (REGNO (op) == R57_REG || REGNO (op) == MUL64_OUT_REG 349 || REGNO (op) == R59_REG)) 350 return 0; 351 else if (REGNO (op) == LP_COUNT) 352 return 1; 353 else 354 return dest_reg_operand (op, mode); 355 case SUBREG : 356 /* (subreg (mem ...) ...) can occur here if the inner part was once a 357 pseudo-reg and is now a stack slot. */ 358 if (GET_CODE (SUBREG_REG (op)) == MEM) 359 return address_operand (XEXP (SUBREG_REG (op), 0), mode); 360 else 361 return dest_reg_operand (op, mode); 362 case MEM : 363 { 364 rtx addr = XEXP (op, 0); 365 366 if (GET_CODE (addr) == PLUS 367 && (GET_CODE (XEXP (addr, 0)) == MULT 368 || (!CONST_INT_P (XEXP (addr, 1)) 369 && (TARGET_NO_SDATA_SET 370 || GET_CODE (XEXP (addr, 1)) != SYMBOL_REF 371 || !SYMBOL_REF_SMALL_P (XEXP (addr, 1)))))) 372 return 0; 373 if ((GET_CODE (addr) == PRE_MODIFY || GET_CODE (addr) == POST_MODIFY) 374 && (GET_CODE (XEXP (addr, 1)) != PLUS 375 || !CONST_INT_P (XEXP (XEXP (addr, 1), 1)))) 376 return 0; 377 /* CONST_INT / CONST_DOUBLE is fine, but the PIC CONST ([..] UNSPEC)) 378 constructs are effectively indexed. */ 379 if (flag_pic) 380 { 381 rtx ad0 = addr; 382 while (GET_CODE (ad0) == PLUS) 383 ad0 = XEXP (ad0, 0); 384 if (GET_CODE (ad0) == CONST || GET_CODE (ad0) == UNSPEC) 385 return 0; 386 } 387 return address_operand (addr, mode); 388 } 389 default : 390 return 0; 391 } 392 393} 394) 395 396;; Return true if OP is a non-volatile non-immediate operand. 397;; Volatile memory refs require a special "cache-bypass" instruction 398;; and only the standard movXX patterns are set up to handle them. 399(define_predicate "nonvol_nonimm_operand" 400 (and (match_code "subreg, reg, mem") 401 (match_test "(GET_CODE (op) != MEM || !MEM_VOLATILE_P (op)) && nonimmediate_operand (op, mode)") 402 (match_test "!arc_is_uncached_mem_p (op)")) 403) 404 405;; Return 1 if OP is a comparison operator valid for the mode of CC. 406;; This allows the use of MATCH_OPERATOR to recognize all the branch insns. 407 408(define_predicate "proper_comparison_operator" 409 (match_code "eq, ne, le, lt, ge, gt, leu, ltu, geu, gtu, unordered, ordered, uneq, unge, ungt, unle, unlt, ltgt") 410{ 411 enum rtx_code code = GET_CODE (op); 412 413 if (!COMPARISON_P (op)) 414 return 0; 415 416 /* After generic flag-setting insns, we can use eq / ne / pl / mi / pnz . 417 There are some creative uses for hi / ls after shifts, but these are 418 hard to understand for the compiler and could be at best the target of 419 a peephole. */ 420 switch (GET_MODE (XEXP (op, 0))) 421 { 422 case E_CC_ZNmode: 423 return (code == EQ || code == NE || code == GE || code == LT 424 || code == GT); 425 case E_CC_Zmode: 426 return code == EQ || code == NE; 427 case E_CC_Cmode: 428 return code == LTU || code == GEU; 429 case E_CC_FP_GTmode: 430 return code == GT || code == UNLE; 431 case E_CC_FP_GEmode: 432 return code == GE || code == UNLT; 433 case E_CC_FP_ORDmode: 434 return code == ORDERED || code == UNORDERED; 435 case E_CC_FP_UNEQmode: 436 return code == UNEQ || code == LTGT; 437 case E_CC_FPXmode: 438 return (code == EQ || code == NE || code == UNEQ || code == LTGT 439 || code == ORDERED || code == UNORDERED); 440 441 case E_CC_FPUmode: 442 case E_CC_FPUEmode: 443 return 1; 444 case E_CC_FPU_UNEQmode: 445 return 1; 446 447 case E_CCmode: 448 case E_SImode: /* Used for BRcc. */ 449 return 1; 450 /* From combiner. */ 451 case E_QImode: case E_HImode: case E_DImode: case E_SFmode: case E_DFmode: 452 return 0; 453 case E_VOIDmode: 454 return 0; 455 default: 456 gcc_unreachable (); 457 } 458}) 459 460(define_predicate "equality_comparison_operator" 461 (match_code "eq, ne")) 462 463(define_predicate "ge_lt_comparison_operator" 464 (match_code "ge, lt")) 465 466(define_predicate "brcc_nolimm_operator" 467 (ior (match_test "REG_P (XEXP (op, 1))") 468 (and (match_code "eq, ne, lt, ge, ltu, geu") 469 (match_test "CONST_INT_P (XEXP (op, 1))") 470 (match_test "u6_immediate_operand (XEXP (op, 1), SImode)")) 471 (and (match_code "le, gt, leu, gtu") 472 (match_test "CONST_INT_P (XEXP (op, 1))") 473 (match_test "UNSIGNED_INT6 (INTVAL (XEXP (op, 1)) + 1)")))) 474 475;; Return TRUE if this is the condition code register, if we aren't given 476;; a mode, accept any CCmode register 477(define_special_predicate "cc_register" 478 (match_code "reg") 479{ 480 if (mode == VOIDmode) 481 { 482 mode = GET_MODE (op); 483 if (GET_MODE_CLASS (mode) != MODE_CC) 484 return FALSE; 485 } 486 487 if (mode == GET_MODE (op) && GET_CODE (op) == REG && REGNO (op) == CC_REG) 488 return TRUE; 489 490 return FALSE; 491}) 492 493;; Return TRUE if this is the condition code register; if we aren't given 494;; a mode, accept any CCmode register. If we are given a mode, accept 495;; modes that set a subset of flags. 496(define_special_predicate "cc_set_register" 497 (match_code "reg") 498{ 499 machine_mode rmode = GET_MODE (op); 500 501 if (mode == VOIDmode) 502 { 503 mode = rmode; 504 if (GET_MODE_CLASS (mode) != MODE_CC) 505 return FALSE; 506 } 507 508 if (REGNO (op) != CC_REG) 509 return FALSE; 510 if (mode == rmode 511 || (mode == CC_ZNmode && rmode == CC_Zmode) 512 || (mode == CCmode && rmode == CC_Zmode) 513 || (mode == CCmode && rmode == CC_ZNmode) 514 || (mode == CCmode && rmode == CC_Cmode)) 515 return TRUE; 516 517 return FALSE; 518}) 519 520; Accept CC_REG in modes which provide the flags needed for MODE. */ 521(define_special_predicate "cc_use_register" 522 (match_code "reg") 523{ 524 if (REGNO (op) != CC_REG) 525 return 0; 526 if (GET_MODE (op) == mode) 527 return 1; 528 switch (mode) 529 { 530 case E_CC_Zmode: 531 if (GET_MODE (op) == CC_ZNmode) 532 return 1; 533 /* Fall through. */ 534 case E_CC_ZNmode: case E_CC_Cmode: 535 return GET_MODE (op) == CCmode; 536 default: 537 gcc_unreachable (); 538 } 539}) 540 541(define_special_predicate "zn_compare_operator" 542 (match_code "compare") 543{ 544 return GET_MODE (op) == CC_ZNmode || GET_MODE (op) == CC_Zmode; 545}) 546 547;; Return true if OP is a shift operator. 548(define_predicate "shift_operator" 549 (match_code "ashiftrt, lshiftrt, ashift") 550) 551 552;; Return true if OP is a left shift operator that can be implemented in 553;; four insn words or less without a barrel shifter or multiplier. 554(define_predicate "shiftl4_operator" 555 (and (match_code "ashift") 556 (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") 557 (match_test "UINTVAL (XEXP (op, 1)) <= 9U 558 || INTVAL (XEXP (op, 1)) == 29 559 || INTVAL (XEXP (op, 1)) == 30 560 || INTVAL (XEXP (op, 1)) == 31"))) 561 562;; Return true if OP is a right shift operator that can be implemented in 563;; four insn words or less without a barrel shifter or multiplier. 564(define_predicate "shiftr4_operator" 565 (and (match_code "ashiftrt, lshiftrt") 566 (match_test "const_int_operand (XEXP (op, 1), VOIDmode) ") 567 (match_test "UINTVAL (XEXP (op, 1)) <= 4U 568 || INTVAL (XEXP (op, 1)) == 30 569 || INTVAL (XEXP (op, 1)) == 31"))) 570 571;; Return true if OP is a shift operator that can be implemented in 572;; four insn words or less without a barrel shifter or multiplier. 573(define_predicate "shift4_operator" 574 (ior (match_operand 0 "shiftl4_operator") 575 (match_operand 0 "shiftr4_operator"))) 576 577(define_predicate "mult_operator" 578 (and (match_code "mult") (match_test "TARGET_MPY")) 579) 580 581(define_predicate "commutative_operator" 582 (ior (match_code "plus,ior,xor,and") 583 (match_operand 0 "mult_operator") 584 (and (match_code "ss_plus") 585 (match_test "TARGET_ARC700 || TARGET_EA_SET"))) 586) 587 588(define_predicate "commutative_operator_sans_mult" 589 (ior (match_code "plus,ior,xor,and") 590 (and (match_code "ss_plus") 591 (match_test "TARGET_ARC700 || TARGET_EA_SET"))) 592) 593 594(define_predicate "noncommutative_operator" 595 (ior (and (match_code "ashift,ashiftrt,lshiftrt,rotatert") 596 (match_test "TARGET_BARREL_SHIFTER")) 597 (match_code "minus") 598 (and (match_code "ss_minus") 599 (match_test "TARGET_ARC700 || TARGET_EA_SET"))) 600) 601 602(define_predicate "unary_operator" 603 (ior (match_code "abs,neg,not,sign_extend,zero_extend") 604 (and (ior (match_code "ss_neg") 605 (and (match_code "ss_truncate") 606 (match_test "GET_MODE (XEXP (op, 0)) == HImode"))) 607 (match_test "TARGET_ARC700 || TARGET_EA_SET"))) 608) 609 610(define_predicate "_1_2_3_operand" 611 (and (match_code "const_int") 612 (match_test "INTVAL (op) == 1 || INTVAL (op) == 2 || INTVAL (op) == 3")) 613) 614 615(define_predicate "_2_4_8_operand" 616 (and (match_code "const_int") 617 (match_test "INTVAL (op) == 2 || INTVAL (op) == 4 || INTVAL (op) == 8")) 618) 619 620(define_predicate "arc_double_register_operand" 621 (match_code "reg") 622{ 623 if ((GET_MODE (op) != mode) && (mode != VOIDmode)) 624 return 0; 625 626 return (GET_CODE (op) == REG 627 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 628 || REGNO_REG_CLASS (REGNO (op)) == DOUBLE_REGS)); 629}) 630 631(define_predicate "shouldbe_register_operand" 632 (match_code "reg,subreg,mem") 633{ 634 return ((reload_in_progress || reload_completed) 635 ? general_operand : register_operand) (op, mode); 636}) 637 638(define_predicate "vector_register_operand" 639 (match_code "reg") 640{ 641 if ((GET_MODE (op) != mode) && (mode != VOIDmode)) 642 return 0; 643 644 return (GET_CODE (op) == REG 645 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 646 || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); 647}) 648 649(define_predicate "vector_register_or_memory_operand" 650 ( ior (match_code "reg") 651 (match_code "mem")) 652{ 653 if ((GET_MODE (op) != mode) && (mode != VOIDmode)) 654 return 0; 655 656 if ((GET_CODE (op) == MEM) 657 && (mode == V8HImode) 658 && GET_CODE (XEXP (op,0)) == REG) 659 return 1; 660 661 return (GET_CODE (op) == REG 662 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 663 || REGNO_REG_CLASS (REGNO (op)) == SIMD_VR_REGS)); 664}) 665 666(define_predicate "arc_dpfp_operator" 667 (match_code "plus, mult,minus") 668) 669 670(define_predicate "arc_simd_dma_register_operand" 671 (match_code "reg") 672{ 673 if ((GET_MODE (op) != mode) && (mode != VOIDmode)) 674 return 0; 675 676 return (GET_CODE (op) == REG 677 && (REGNO (op) >= FIRST_PSEUDO_REGISTER 678 || REGNO_REG_CLASS (REGNO (op)) == SIMD_DMA_CONFIG_REGS)); 679}) 680 681(define_predicate "acc1_operand" 682 (and (match_code "reg") 683 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 56 : 57)"))) 684 685(define_predicate "acc2_operand" 686 (and (match_code "reg") 687 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 57 : 56)"))) 688 689(define_predicate "mlo_operand" 690 (and (match_code "reg") 691 (match_test "REGNO (op) == R58_REG"))) 692 693(define_predicate "mhi_operand" 694 (and (match_code "reg") 695 (match_test "REGNO (op) == R59_REG"))) 696 697(define_predicate "accl_operand" 698 (and (match_code "reg") 699 (match_test "REGNO (op) == (TARGET_BIG_ENDIAN ? 59 : 58)") 700 (match_test "TARGET_V2"))) 701 702; Unfortunately, we cannot allow a const_int_operand before reload, because 703; reload needs a non-void mode to guide it how to reload the inside of a 704; {sign_}extend. 705(define_predicate "extend_operand" 706 (ior (match_operand 0 "register_operand") 707 (and (match_operand 0 "immediate_operand") 708 (ior (not (match_operand 0 "const_int_operand")) 709 (match_test "reload_in_progress || reload_completed"))))) 710 711(define_predicate "millicode_store_operation" 712 (match_code "parallel") 713{ 714 return arc_check_millicode (op, 0, 0); 715}) 716 717(define_predicate "millicode_load_operation" 718 (match_code "parallel") 719{ 720 return arc_check_millicode (op, 2, 2); 721}) 722 723(define_predicate "millicode_load_clob_operation" 724 (match_code "parallel") 725{ 726 return arc_check_millicode (op, 0, 1); 727}) 728 729(define_special_predicate "immediate_usidi_operand" 730 (if_then_else 731 (match_code "const_int") 732 (match_test "INTVAL (op) >= 0") 733 (and (match_test "const_double_operand (op, mode)") 734 (match_test "CONST_DOUBLE_HIGH (op) == 0")))) 735 736(define_predicate "short_const_int_operand" 737 (and (match_operand 0 "const_int_operand") 738 (match_test "satisfies_constraint_C16 (op)"))) 739 740(define_predicate "mem_noofs_operand" 741 (and (match_code "mem") 742 (match_code "reg" "0"))) 743 744(define_predicate "any_mem_operand" 745 (match_code "mem")) 746 747; Special predicate to match even-odd double register pair 748(define_predicate "even_register_operand" 749 (match_code "reg") 750 { 751 if ((GET_MODE (op) != mode) && (mode != VOIDmode)) 752 return 0; 753 754 return (REG_P (op) && ((REGNO (op) >= FIRST_PSEUDO_REGISTER) 755 || ((REGNO (op) & 1) == 0))); 756 }) 757 758(define_predicate "double_register_operand" 759 (ior (match_test "even_register_operand (op, mode)") 760 (match_test "arc_double_register_operand (op, mode)"))) 761 762(define_predicate "cmem_address_0" 763 (and (match_code "symbol_ref") 764 (match_test "SYMBOL_REF_FLAGS (op) & SYMBOL_FLAG_CMEM"))) 765 766(define_predicate "cmem_address_1" 767 (and (match_code "plus") 768 (match_test "cmem_address_0 (XEXP (op, 0), SImode)"))) 769 770(define_predicate "cmem_address_2" 771 (and (match_code "const") 772 (match_test "cmem_address_1 (XEXP (op, 0), SImode)"))) 773 774(define_predicate "cmem_address" 775 (ior (match_operand:SI 0 "cmem_address_0") 776 (match_operand:SI 0 "cmem_address_1") 777 (match_operand:SI 0 "cmem_address_2"))) 778 779(define_predicate "short_unsigned_const_operand" 780 (and (match_code "const_int") 781 (match_test "satisfies_constraint_J16 (op)"))) 782 783(define_predicate "arc_short_operand" 784 (ior (match_test "register_operand (op, mode)") 785 (match_test "short_unsigned_const_operand (op, mode)"))) 786 787(define_special_predicate "push_multi_operand" 788 (match_code "parallel") 789 { 790 return arc_check_multi (op, true); 791}) 792 793(define_special_predicate "pop_multi_operand" 794 (match_code "parallel") 795 { 796 return arc_check_multi (op, false); 797}) 798 799(define_predicate "arc_nonmemory_operand" 800 (ior (match_test "register_operand (op, mode)") 801 (and (match_code "const_int, symbol_ref") 802 (match_test "!optimize_size")))) 803