1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2021 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha@arm.com) 6 Minor hacks by Nick Clifton (nickc@cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 /* Target hooks for D language. */ 51 #define TARGET_D_CPU_VERSIONS arm_d_target_versions 52 #define TARGET_D_REGISTER_CPU_TARGET_INFO arm_d_register_target_info 53 54 #include "config/arm/arm-opts.h" 55 56 /* The processor for which instructions should be scheduled. */ 57 extern enum processor_type arm_tune; 58 59 typedef enum arm_cond_code 60 { 61 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 62 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 63 } 64 arm_cc; 65 66 extern arm_cc arm_current_cc; 67 68 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 69 70 /* The maximum number of instructions that is beneficial to 71 conditionally execute. */ 72 #undef MAX_CONDITIONAL_EXECUTE 73 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 74 75 extern int arm_target_label; 76 extern int arm_ccfsm_state; 77 extern GTY(()) rtx arm_target_insn; 78 /* Callback to output language specific object attributes. */ 79 extern void (*arm_lang_output_object_attributes_hook)(void); 80 81 /* This type is the user-visible __fp16. We need it in a few places in 82 the backend. Defined in arm-builtins.c. */ 83 extern tree arm_fp16_type_node; 84 85 /* This type is the user-visible __bf16. We need it in a few places in 86 the backend. Defined in arm-builtins.c. */ 87 extern tree arm_bf16_type_node; 88 extern tree arm_bf16_ptr_type_node; 89 90 91 #undef CPP_SPEC 92 #define CPP_SPEC "%(subtarget_cpp_spec) \ 93 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 94 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 95 %{mbig-endian:%{mlittle-endian: \ 96 %e-mbig-endian and -mlittle-endian may not be used together}}" 97 98 #ifndef CC1_SPEC 99 #define CC1_SPEC "" 100 #endif 101 102 /* This macro defines names of additional specifications to put in the specs 103 that can be used in various specifications like CC1_SPEC. Its definition 104 is an initializer with a subgrouping for each command option. 105 106 Each subgrouping contains a string constant, that defines the 107 specification name, and a string constant that used by the GCC driver 108 program. 109 110 Do not define this macro if it does not need to do anything. */ 111 #define EXTRA_SPECS \ 112 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 113 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 114 SUBTARGET_EXTRA_SPECS 115 116 #ifndef SUBTARGET_EXTRA_SPECS 117 #define SUBTARGET_EXTRA_SPECS 118 #endif 119 120 #ifndef SUBTARGET_CPP_SPEC 121 #define SUBTARGET_CPP_SPEC "" 122 #endif 123 124 /* Tree Target Specification. */ 125 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 126 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 127 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 128 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 129 130 /* Run-time Target Specification. */ 131 /* Use hardware floating point instructions. -mgeneral-regs-only prevents 132 the use of floating point instructions and registers but does not prevent 133 emission of floating point pcs attributes. */ 134 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 135 && bitmap_bit_p (arm_active_target.isa, \ 136 isa_bit_vfpv2) \ 137 && TARGET_32BIT) 138 139 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ 140 && !TARGET_GENERAL_REGS_ONLY) 141 142 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) 143 /* User has permitted use of FP instructions, if they exist for this 144 target. */ 145 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 146 /* Use hardware floating point calling convention. */ 147 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 148 #define TARGET_IWMMXT (arm_arch_iwmmxt) 149 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 150 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ 151 && !TARGET_GENERAL_REGS_ONLY) 152 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ 153 && !TARGET_GENERAL_REGS_ONLY) 154 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 155 #define TARGET_ARM (! TARGET_THUMB) 156 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 157 #define TARGET_BACKTRACE (crtl->is_leaf \ 158 ? TARGET_TPCS_LEAF_FRAME \ 159 : TARGET_TPCS_FRAME) 160 #define TARGET_AAPCS_BASED \ 161 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 162 163 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 164 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 165 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 166 167 /* Only 16-bit thumb code. */ 168 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 169 /* Arm or Thumb-2 32-bit code. */ 170 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 171 /* 32-bit Thumb-2 code. */ 172 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 173 /* Thumb-1 only. */ 174 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 175 176 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ 177 && !TARGET_THUMB1) 178 179 #define TARGET_CRC32 (arm_arch_crc) 180 181 /* Thumb-2 but also has some conditional arithmetic instructions like csinc, 182 csinv, etc. */ 183 #define TARGET_COND_ARITH (arm_arch8_1m_main) 184 185 /* The following two macros concern the ability to execute coprocessor 186 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 187 only ever tested when we know we are generating for VFP hardware; we need 188 to be more careful with TARGET_NEON as noted below. */ 189 190 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 191 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 192 193 /* FPU supports VFPv3 instructions. */ 194 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 195 196 /* FPU supports FPv5 instructions. */ 197 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 198 199 /* FPU only supports VFP single-precision instructions. */ 200 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 201 202 /* FPU supports VFP double-precision instructions. */ 203 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 204 205 /* FPU supports half-precision floating-point with NEON element load/store. */ 206 #define TARGET_NEON_FP16 \ 207 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 208 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 209 210 /* FPU supports VFP half-precision floating-point conversions. */ 211 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 212 213 /* FPU supports converting between HFmode and DFmode in a single hardware 214 step. */ 215 #define TARGET_FP16_TO_DOUBLE \ 216 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 217 218 /* FPU supports fused-multiply-add operations. */ 219 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 220 221 /* FPU supports Crypto extensions. */ 222 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 223 224 /* FPU supports Neon instructions. The setting of this macro gets 225 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 226 and TARGET_HARD_FLOAT to ensure that NEON instructions are 227 available. */ 228 #define TARGET_NEON \ 229 (TARGET_32BIT && TARGET_HARD_FLOAT \ 230 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 231 232 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 233 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 234 235 /* Supports the Dot Product AdvSIMD extensions. */ 236 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ 237 && bitmap_bit_p (arm_active_target.isa, \ 238 isa_bit_dotprod) \ 239 && arm_arch8_2) 240 241 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ 242 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) 243 244 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 245 and later. */ 246 #define TARGET_VFP_FP16INST \ 247 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 248 249 /* Target supports the floating point FP16 instructions from ARMv8.2-A 250 and later. */ 251 #define TARGET_FP16FML (TARGET_NEON \ 252 && bitmap_bit_p (arm_active_target.isa, \ 253 isa_bit_fp16fml) \ 254 && arm_arch8_2) 255 256 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 257 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 258 259 /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */ 260 #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm) 261 262 /* FPU supports Brain half-precision floating-point (BFloat16) extension. */ 263 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \ 264 && arm_arch8_2 && arm_arch_bf16) 265 #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \ 266 && arm_arch8_2 && arm_arch_bf16) 267 268 /* Q-bit is present. */ 269 #define TARGET_ARM_QBIT \ 270 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) 271 /* Saturation operation, e.g. SSAT. */ 272 #define TARGET_ARM_SAT \ 273 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 274 /* "DSP" multiply instructions, eg. SMULxy. */ 275 #define TARGET_DSP_MULTIPLY \ 276 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) 277 /* Integer SIMD instructions, and extend-accumulate instructions. */ 278 #define TARGET_INT_SIMD \ 279 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 280 281 /* Should MOVW/MOVT be used in preference to a constant pool. */ 282 #define TARGET_USE_MOVT \ 283 (TARGET_HAVE_MOVT \ 284 && (arm_disable_literal_pool \ 285 || (!optimize_size && !current_tune->prefer_constant_pool))) 286 287 /* Nonzero if this chip provides the DMB instruction. */ 288 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 289 290 /* Nonzero if this chip implements a memory barrier via CP15. */ 291 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 292 && ! TARGET_THUMB1) 293 294 /* Nonzero if this chip implements a memory barrier instruction. */ 295 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 296 297 /* Nonzero if this chip supports ldrex and strex */ 298 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 299 || arm_arch7 \ 300 || (arm_arch8 && !arm_arch_notm)) 301 302 /* Nonzero if this chip supports LPAE. */ 303 #define TARGET_HAVE_LPAE (arm_arch_lpae) 304 305 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 306 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 307 || arm_arch7 \ 308 || (arm_arch8 && !arm_arch_notm)) 309 310 /* Nonzero if this chip supports ldrexd and strexd. */ 311 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 312 || arm_arch7) && arm_arch_notm) 313 314 /* Nonzero if this chip supports load-acquire and store-release. */ 315 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 316 317 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 318 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 319 && TARGET_32BIT \ 320 && arm_arch_notm) 321 322 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 323 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 324 325 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 326 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 327 328 /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions 329 instructions (most are floating-point related). */ 330 #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) 331 332 #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 333 && bitmap_bit_p (arm_active_target.isa, \ 334 isa_bit_mve) \ 335 && !TARGET_GENERAL_REGS_ONLY) 336 337 #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 338 && bitmap_bit_p (arm_active_target.isa, \ 339 isa_bit_mve_float) \ 340 && !TARGET_GENERAL_REGS_ONLY) 341 342 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM 343 alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few 344 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All 345 the VFP instructions, RTL patterns and register are guarded by 346 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers 347 between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE 348 hereafter. */ 349 350 #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 351 && bitmap_bit_p (arm_active_target.isa, \ 352 isa_bit_vfp_base) \ 353 && !TARGET_GENERAL_REGS_ONLY) 354 355 /* Nonzero if integer division instructions supported. */ 356 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 357 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 358 359 /* Nonzero if disallow volatile memory access in IT block. */ 360 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 361 362 /* Nonzero if chip supports the Custom Datapath Extension. */ 363 #define TARGET_CDE (arm_arch_cde && arm_arch8 && !arm_arch_notm) 364 365 /* Should constant I be slplit for OP. */ 366 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 367 ((optimize >= 2) \ 368 && can_create_pseudo_p () \ 369 && !const_ok_for_op (i, op)) 370 371 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 372 then TARGET_AAPCS_BASED must be true -- but the converse does not 373 hold. TARGET_BPABI implies the use of the BPABI runtime library, 374 etc., in addition to just the AAPCS calling conventions. */ 375 #ifndef TARGET_BPABI 376 #define TARGET_BPABI false 377 #endif 378 379 /* Transform lane numbers on big endian targets. This is used to allow for the 380 endianness difference between NEON architectural lane numbers and those 381 used in RTL */ 382 #define NEON_ENDIAN_LANE_N(mode, n) \ 383 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 384 385 /* Support for a compile-time default CPU, et cetera. The rules are: 386 --with-arch is ignored if -march or -mcpu are specified. 387 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 388 by --with-arch. 389 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 390 by -march). 391 --with-float is ignored if -mfloat-abi is specified. 392 --with-fpu is ignored if -mfpu is specified. 393 --with-abi is ignored if -mabi is specified. 394 --with-tls is ignored if -mtls-dialect is specified. 395 Note: --with-mode is not handled here, that has a special rule 396 TARGET_MODE_CHECK that also takes into account the selected CPU and 397 architecture. */ 398 #define OPTION_DEFAULT_SPECS \ 399 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 400 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 401 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 402 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 403 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 404 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 405 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 406 407 extern const struct arm_fpu_desc 408 { 409 const char *name; 410 enum isa_feature isa_bits[isa_num_bits]; 411 } all_fpus[]; 412 413 /* Which floating point hardware to schedule for. */ 414 extern int arm_fpu_attr; 415 416 #ifndef TARGET_DEFAULT_FLOAT_ABI 417 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 418 #endif 419 420 #ifndef ARM_DEFAULT_ABI 421 #define ARM_DEFAULT_ABI ARM_ABI_APCS 422 #endif 423 424 /* AAPCS based ABIs use short enums by default. */ 425 #ifndef ARM_DEFAULT_SHORT_ENUMS 426 #define ARM_DEFAULT_SHORT_ENUMS \ 427 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 428 #endif 429 430 /* Map each of the micro-architecture variants to their corresponding 431 major architecture revision. */ 432 433 enum base_architecture 434 { 435 BASE_ARCH_0 = 0, 436 BASE_ARCH_2 = 2, 437 BASE_ARCH_3 = 3, 438 BASE_ARCH_3M = 3, 439 BASE_ARCH_4 = 4, 440 BASE_ARCH_4T = 4, 441 BASE_ARCH_5T = 5, 442 BASE_ARCH_5TE = 5, 443 BASE_ARCH_5TEJ = 5, 444 BASE_ARCH_6 = 6, 445 BASE_ARCH_6J = 6, 446 BASE_ARCH_6KZ = 6, 447 BASE_ARCH_6K = 6, 448 BASE_ARCH_6T2 = 6, 449 BASE_ARCH_6M = 6, 450 BASE_ARCH_6Z = 6, 451 BASE_ARCH_7 = 7, 452 BASE_ARCH_7A = 7, 453 BASE_ARCH_7R = 7, 454 BASE_ARCH_7M = 7, 455 BASE_ARCH_7EM = 7, 456 BASE_ARCH_8A = 8, 457 BASE_ARCH_8M_BASE = 8, 458 BASE_ARCH_8M_MAIN = 8, 459 BASE_ARCH_8R = 8 460 }; 461 462 /* The major revision number of the ARM Architecture implemented by the target. */ 463 extern enum base_architecture arm_base_arch; 464 465 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 466 extern int arm_arch4; 467 468 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 469 extern int arm_arch4t; 470 471 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ 472 extern int arm_arch5t; 473 474 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ 475 extern int arm_arch5te; 476 477 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 478 extern int arm_arch6; 479 480 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 481 extern int arm_arch6k; 482 483 /* Nonzero if instructions present in ARMv6-M can be used. */ 484 extern int arm_arch6m; 485 486 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 487 extern int arm_arch7; 488 489 /* Nonzero if instructions not present in the 'M' profile can be used. */ 490 extern int arm_arch_notm; 491 492 /* Nonzero if instructions present in ARMv7E-M can be used. */ 493 extern int arm_arch7em; 494 495 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 496 extern int arm_arch8; 497 498 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 499 extern int arm_arch8_1; 500 501 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 502 extern int arm_arch8_2; 503 504 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ 505 extern int arm_arch8_3; 506 507 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ 508 extern int arm_arch8_4; 509 510 /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline 511 extensions. */ 512 extern int arm_arch8_1m_main; 513 514 /* Nonzero if this chip supports the FP16 instructions extension of ARM 515 Architecture 8.2. */ 516 extern int arm_fp16_inst; 517 518 /* Nonzero if this chip can benefit from load scheduling. */ 519 extern int arm_ld_sched; 520 521 /* Nonzero if this chip is a StrongARM. */ 522 extern int arm_tune_strongarm; 523 524 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 525 extern int arm_arch_iwmmxt; 526 527 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 528 extern int arm_arch_iwmmxt2; 529 530 /* Nonzero if this chip is an XScale. */ 531 extern int arm_arch_xscale; 532 533 /* Nonzero if tuning for XScale. */ 534 extern int arm_tune_xscale; 535 536 /* Nonzero if tuning for stores via the write buffer. */ 537 extern int arm_tune_wbuf; 538 539 /* Nonzero if tuning for Cortex-A9. */ 540 extern int arm_tune_cortex_a9; 541 542 /* Nonzero if we should define __THUMB_INTERWORK__ in the 543 preprocessor. 544 XXX This is a bit of a hack, it's intended to help work around 545 problems in GLD which doesn't understand that armv5t code is 546 interworking clean. */ 547 extern int arm_cpp_interwork; 548 549 /* Nonzero if chip supports Thumb 1. */ 550 extern int arm_arch_thumb1; 551 552 /* Nonzero if chip supports Thumb 2. */ 553 extern int arm_arch_thumb2; 554 555 /* Nonzero if chip supports integer division instruction in ARM mode. */ 556 extern int arm_arch_arm_hwdiv; 557 558 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 559 extern int arm_arch_thumb_hwdiv; 560 561 /* Nonzero if chip disallows volatile memory access in IT block. */ 562 extern int arm_arch_no_volatile_ce; 563 564 /* Nonzero if we shouldn't use literal pools. */ 565 #ifndef USED_FOR_TARGET 566 extern bool arm_disable_literal_pool; 567 #endif 568 569 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 570 extern int arm_arch_crc; 571 572 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 573 extern int arm_arch_cmse; 574 575 /* Nonzero if chip supports the I8MM instructions. */ 576 extern int arm_arch_i8mm; 577 578 /* Nonzero if chip supports the BFloat16 instructions. */ 579 extern int arm_arch_bf16; 580 581 /* Nonzero if chip supports the Custom Datapath Extension. */ 582 extern int arm_arch_cde; 583 extern int arm_arch_cde_coproc; 584 extern const int arm_arch_cde_coproc_bits[]; 585 #define ARM_CDE_CONST_COPROC 7 586 #define ARM_CCDE_CONST_1 ((1 << 13) - 1) 587 #define ARM_CCDE_CONST_2 ((1 << 9 ) - 1) 588 #define ARM_CCDE_CONST_3 ((1 << 6 ) - 1) 589 #define ARM_VCDE_CONST_1 ((1 << 11) - 1) 590 #define ARM_VCDE_CONST_2 ((1 << 6 ) - 1) 591 #define ARM_VCDE_CONST_3 ((1 << 3 ) - 1) 592 #define ARM_MVE_CDE_CONST_1 ((1 << 12) - 1) 593 #define ARM_MVE_CDE_CONST_2 ((1 << 7 ) - 1) 594 #define ARM_MVE_CDE_CONST_3 ((1 << 4 ) - 1) 595 596 #ifndef TARGET_DEFAULT 597 #define TARGET_DEFAULT (MASK_APCS_FRAME) 598 #endif 599 600 /* Nonzero if PIC code requires explicit qualifiers to generate 601 PLT and GOT relocs rather than the assembler doing so implicitly. 602 Subtargets can override these if required. */ 603 #ifndef NEED_GOT_RELOC 604 #define NEED_GOT_RELOC 0 605 #endif 606 #ifndef NEED_PLT_RELOC 607 #define NEED_PLT_RELOC 0 608 #endif 609 610 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 611 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 612 #endif 613 614 /* Nonzero if we need to refer to the GOT with a PC-relative 615 offset. In other words, generate 616 617 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 618 619 rather than 620 621 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 622 623 The default is true, which matches NetBSD. Subtargets can 624 override this if required. */ 625 #ifndef GOT_PCREL 626 #define GOT_PCREL 1 627 #endif 628 629 /* Target machine storage Layout. */ 630 631 /* Nonzero if this chip provides Armv8.1-M Mainline 632 LOB (low overhead branch features) extension instructions. */ 633 #define TARGET_HAVE_LOB (arm_arch8_1m_main) 634 635 /* Define this macro if it is advisable to hold scalars in registers 636 in a wider mode than that declared by the program. In such cases, 637 the value is constrained to be within the bounds of the declared 638 type, but kept valid in the wider mode. The signedness of the 639 extension may differ from that of the type. */ 640 641 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 642 if (GET_MODE_CLASS (MODE) == MODE_INT \ 643 && GET_MODE_SIZE (MODE) < 4) \ 644 { \ 645 (MODE) = SImode; \ 646 } 647 648 /* Define this if most significant bit is lowest numbered 649 in instructions that operate on numbered bit-fields. */ 650 #define BITS_BIG_ENDIAN 0 651 652 /* Define this if most significant byte of a word is the lowest numbered. 653 Most ARM processors are run in little endian mode, so that is the default. 654 If you want to have it run-time selectable, change the definition in a 655 cover file to be TARGET_BIG_ENDIAN. */ 656 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 657 658 /* Define this if most significant word of a multiword number is the lowest 659 numbered. */ 660 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 661 662 #define UNITS_PER_WORD 4 663 664 /* True if natural alignment is used for doubleword types. */ 665 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 666 667 #define DOUBLEWORD_ALIGNMENT 64 668 669 #define PARM_BOUNDARY 32 670 671 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 672 673 #define PREFERRED_STACK_BOUNDARY \ 674 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 675 676 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 677 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 678 679 /* The lowest bit is used to indicate Thumb-mode functions, so the 680 vbit must go into the delta field of pointers to member 681 functions. */ 682 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 683 684 #define EMPTY_FIELD_BOUNDARY 32 685 686 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 687 688 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 689 690 /* XXX Blah -- this macro is used directly by libobjc. Since it 691 supports no vector modes, cut out the complexity and fall back 692 on BIGGEST_FIELD_ALIGNMENT. */ 693 #ifdef IN_TARGET_LIBS 694 #define BIGGEST_FIELD_ALIGNMENT 64 695 #endif 696 697 /* Align definitions of arrays, unions and structures so that 698 initializations and copies can be made more efficient. This is not 699 ABI-changing, so it only affects places where we can see the 700 definition. Increasing the alignment tends to introduce padding, 701 so don't do this when optimizing for size/conserving stack space. */ 702 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 703 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 704 && (TREE_CODE (EXP) == ARRAY_TYPE \ 705 || TREE_CODE (EXP) == UNION_TYPE \ 706 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 707 708 /* Align global data. */ 709 #define DATA_ALIGNMENT(EXP, ALIGN) \ 710 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 711 712 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 713 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 714 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 715 716 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 717 value set in previous versions of this toolchain was 8, which produces more 718 compact structures. The command line option -mstructure_size_boundary=<n> 719 can be used to change this value. For compatibility with the ARM SDK 720 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 721 0020D) page 2-20 says "Structures are aligned on word boundaries". 722 The AAPCS specifies a value of 8. */ 723 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 724 725 /* This is the value used to initialize arm_structure_size_boundary. If a 726 particular arm target wants to change the default value it should change 727 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 728 for an example of this. */ 729 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 730 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 731 #endif 732 733 /* Nonzero if move instructions will actually fail to work 734 when given unaligned data. */ 735 #define STRICT_ALIGNMENT 1 736 737 /* wchar_t is unsigned under the AAPCS. */ 738 #ifndef WCHAR_TYPE 739 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 740 741 #define WCHAR_TYPE_SIZE BITS_PER_WORD 742 #endif 743 744 /* Sized for fixed-point types. */ 745 746 #define SHORT_FRACT_TYPE_SIZE 8 747 #define FRACT_TYPE_SIZE 16 748 #define LONG_FRACT_TYPE_SIZE 32 749 #define LONG_LONG_FRACT_TYPE_SIZE 64 750 751 #define SHORT_ACCUM_TYPE_SIZE 16 752 #define ACCUM_TYPE_SIZE 32 753 #define LONG_ACCUM_TYPE_SIZE 64 754 #define LONG_LONG_ACCUM_TYPE_SIZE 64 755 756 #define MAX_FIXED_MODE_SIZE 64 757 758 #ifndef SIZE_TYPE 759 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 760 #endif 761 762 #ifndef PTRDIFF_TYPE 763 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 764 #endif 765 766 /* AAPCS requires that structure alignment is affected by bitfields. */ 767 #ifndef PCC_BITFIELD_TYPE_MATTERS 768 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 769 #endif 770 771 /* The maximum size of the sync library functions supported. */ 772 #ifndef MAX_SYNC_LIBFUNC_SIZE 773 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 774 #endif 775 776 777 /* Standard register usage. */ 778 779 /* Register allocation in ARM Procedure Call Standard 780 (S - saved over call, F - Frame-related). 781 782 r0 * argument word/integer result 783 r1-r3 argument word 784 785 r4-r8 S register variable 786 r9 S (rfp) register variable (real frame pointer) 787 788 r10 F S (sl) stack limit (used by -mapcs-stack-check) 789 r11 F S (fp) argument pointer 790 r12 (ip) temp workspace 791 r13 F S (sp) lower end of current stack frame 792 r14 (lr) link address/workspace 793 r15 F (pc) program counter 794 795 cc This is NOT a real register, but is used internally 796 to represent things that use or set the condition 797 codes. 798 sfp This isn't either. It is used during rtl generation 799 since the offset between the frame pointer and the 800 auto's isn't known until after register allocation. 801 afp Nor this, we only need this because of non-local 802 goto. Without it fp appears to be used and the 803 elimination code won't get rid of sfp. It tracks 804 fp exactly at all times. 805 apsrq Nor this, it is used to track operations on the Q bit 806 of APSR by ACLE saturating intrinsics. 807 apsrge Nor this, it is used to track operations on the GE bits 808 of APSR by ACLE SIMD32 intrinsics 809 810 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 811 812 /* s0-s15 VFP scratch (aka d0-d7). 813 s16-s31 S VFP variable (aka d8-d15). 814 vfpcc Not a real register. Represents the VFP condition 815 code flags. 816 vpr Used to represent MVE VPR predication. */ 817 818 /* The stack backtrace structure is as follows: 819 fp points to here: | save code pointer | [fp] 820 | return link value | [fp, #-4] 821 | return sp value | [fp, #-8] 822 | return fp value | [fp, #-12] 823 [| saved r10 value |] 824 [| saved r9 value |] 825 [| saved r8 value |] 826 [| saved r7 value |] 827 [| saved r6 value |] 828 [| saved r5 value |] 829 [| saved r4 value |] 830 [| saved r3 value |] 831 [| saved r2 value |] 832 [| saved r1 value |] 833 [| saved r0 value |] 834 r0-r3 are not normally saved in a C function. */ 835 836 /* 1 for registers that have pervasive standard uses 837 and are not available for the register allocator. */ 838 #define FIXED_REGISTERS \ 839 { \ 840 /* Core regs. */ \ 841 0,0,0,0,0,0,0,0, \ 842 0,0,0,0,0,1,0,1, \ 843 /* VFP regs. */ \ 844 1,1,1,1,1,1,1,1, \ 845 1,1,1,1,1,1,1,1, \ 846 1,1,1,1,1,1,1,1, \ 847 1,1,1,1,1,1,1,1, \ 848 1,1,1,1,1,1,1,1, \ 849 1,1,1,1,1,1,1,1, \ 850 1,1,1,1,1,1,1,1, \ 851 1,1,1,1,1,1,1,1, \ 852 /* IWMMXT regs. */ \ 853 1,1,1,1,1,1,1,1, \ 854 1,1,1,1,1,1,1,1, \ 855 1,1,1,1, \ 856 /* Specials. */ \ 857 1,1,1,1,1,1,1 \ 858 } 859 860 /* 1 for registers not available across function calls. 861 These must include the FIXED_REGISTERS and also any 862 registers that can be used without being saved. 863 The latter must include the registers where values are returned 864 and the register where structure-value addresses are passed. 865 Aside from that, you can include as many other registers as you like. 866 The CC is not preserved over function calls on the ARM 6, so it is 867 easier to assume this for all. SFP is preserved, since FP is. */ 868 #define CALL_USED_REGISTERS \ 869 { \ 870 /* Core regs. */ \ 871 1,1,1,1,0,0,0,0, \ 872 0,0,0,0,1,1,1,1, \ 873 /* VFP Regs. */ \ 874 1,1,1,1,1,1,1,1, \ 875 1,1,1,1,1,1,1,1, \ 876 1,1,1,1,1,1,1,1, \ 877 1,1,1,1,1,1,1,1, \ 878 1,1,1,1,1,1,1,1, \ 879 1,1,1,1,1,1,1,1, \ 880 1,1,1,1,1,1,1,1, \ 881 1,1,1,1,1,1,1,1, \ 882 /* IWMMXT regs. */ \ 883 1,1,1,1,1,1,1,1, \ 884 1,1,1,1,1,1,1,1, \ 885 1,1,1,1, \ 886 /* Specials. */ \ 887 1,1,1,1,1,1,1 \ 888 } 889 890 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 891 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 892 #endif 893 894 /* These are a couple of extensions to the formats accepted 895 by asm_fprintf: 896 %@ prints out ASM_COMMENT_START 897 %r prints out REGISTER_PREFIX reg_names[arg] */ 898 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 899 case '@': \ 900 fputs (ASM_COMMENT_START, FILE); \ 901 break; \ 902 \ 903 case 'r': \ 904 fputs (REGISTER_PREFIX, FILE); \ 905 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 906 break; 907 908 /* Round X up to the nearest word. */ 909 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 910 911 /* Convert fron bytes to ints. */ 912 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 913 914 /* The number of (integer) registers required to hold a quantity of type MODE. 915 Also used for VFP registers. */ 916 #define ARM_NUM_REGS(MODE) \ 917 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 918 919 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 920 #define ARM_NUM_REGS2(MODE, TYPE) \ 921 ARM_NUM_INTS ((MODE) == BLKmode ? \ 922 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 923 924 /* The number of (integer) argument register available. */ 925 #define NUM_ARG_REGS 4 926 927 /* And similarly for the VFP. */ 928 #define NUM_VFP_ARG_REGS 16 929 930 /* Return the register number of the N'th (integer) argument. */ 931 #define ARG_REGISTER(N) (N - 1) 932 933 /* Specify the registers used for certain standard purposes. 934 The values of these macros are register numbers. */ 935 936 /* The number of the last argument register. */ 937 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 938 939 /* The numbers of the Thumb register ranges. */ 940 #define FIRST_LO_REGNUM 0 941 #define LAST_LO_REGNUM 7 942 #define FIRST_HI_REGNUM 8 943 #define LAST_HI_REGNUM 11 944 945 /* Overridden by config/arm/bpabi.h. */ 946 #ifndef ARM_UNWIND_INFO 947 #define ARM_UNWIND_INFO 0 948 #endif 949 950 /* Use r0 and r1 to pass exception handling information. */ 951 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 952 953 /* The register that holds the return address in exception handlers. */ 954 #define ARM_EH_STACKADJ_REGNUM 2 955 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 956 957 #ifndef ARM_TARGET2_DWARF_FORMAT 958 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 959 #endif 960 961 /* ttype entries (the only interesting data references used) 962 use TARGET2 relocations. */ 963 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 964 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 965 : DW_EH_PE_absptr) 966 967 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 968 as an invisible last argument (possible since varargs don't exist in 969 Pascal), so the following is not true. */ 970 #define STATIC_CHAIN_REGNUM 12 971 972 /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ 973 #define FDPIC_REGNUM 9 974 975 /* Define this to be where the real frame pointer is if it is not possible to 976 work out the offset between the frame pointer and the automatic variables 977 until after register allocation has taken place. FRAME_POINTER_REGNUM 978 should point to a special register that we will make sure is eliminated. 979 980 For the Thumb we have another problem. The TPCS defines the frame pointer 981 as r11, and GCC believes that it is always possible to use the frame pointer 982 as base register for addressing purposes. (See comments in 983 find_reloads_address()). But - the Thumb does not allow high registers, 984 including r11, to be used as base address registers. Hence our problem. 985 986 The solution used here, and in the old thumb port is to use r7 instead of 987 r11 as the hard frame pointer and to have special code to generate 988 backtrace structures on the stack (if required to do so via a command line 989 option) using r11. This is the only 'user visible' use of r11 as a frame 990 pointer. */ 991 #define ARM_HARD_FRAME_POINTER_REGNUM 11 992 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 993 994 #define HARD_FRAME_POINTER_REGNUM \ 995 (TARGET_ARM \ 996 ? ARM_HARD_FRAME_POINTER_REGNUM \ 997 : THUMB_HARD_FRAME_POINTER_REGNUM) 998 999 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1000 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1001 1002 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1003 1004 /* Register to use for pushing function arguments. */ 1005 #define STACK_POINTER_REGNUM SP_REGNUM 1006 1007 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1008 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1009 1010 /* Need to sync with WCGR in iwmmxt.md. */ 1011 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1012 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1013 1014 #define IS_IWMMXT_REGNUM(REGNUM) \ 1015 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1016 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1017 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1018 1019 /* Base register for access to local variables of the function. */ 1020 #define FRAME_POINTER_REGNUM 102 1021 1022 /* Base register for access to arguments of the function. */ 1023 #define ARG_POINTER_REGNUM 103 1024 1025 #define FIRST_VFP_REGNUM 16 1026 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1027 #define LAST_VFP_REGNUM \ 1028 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1029 1030 #define IS_VFP_REGNUM(REGNUM) \ 1031 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1032 1033 /* VFP registers are split into two types: those defined by VFP versions < 3 1034 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1035 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1036 in various parts of the backend, we implement as "fake" single-precision 1037 registers (which would be S32-S63, but cannot be used in that way). The 1038 following macros define these ranges of registers. */ 1039 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1040 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1041 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1042 1043 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1044 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1045 1046 /* DFmode values are only valid in even register pairs. */ 1047 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1048 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1049 1050 /* Neon Quad values must start at a multiple of four registers. */ 1051 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1052 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1053 1054 /* Neon structures of vectors must be in even register pairs and there 1055 must be enough registers available. Because of various patterns 1056 requiring quad registers, we require them to start at a multiple of 1057 four. */ 1058 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1059 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1060 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1061 1062 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP 1063 + 1 APSRQ + 1 APSRGE + 1 VPR. */ 1064 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1065 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1066 #define FIRST_PSEUDO_REGISTER 107 1067 1068 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1069 1070 /* Value should be nonzero if functions must have frame pointers. 1071 Zero means the frame pointer need not be set up (and parms may be accessed 1072 via the stack pointer) in functions that seem suitable. 1073 If we have to have a frame pointer we might as well make use of it. 1074 APCS says that the frame pointer does not need to be pushed in leaf 1075 functions, or simple tail call functions. */ 1076 1077 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1078 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1079 #endif 1080 1081 #define VALID_IWMMXT_REG_MODE(MODE) \ 1082 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1083 1084 /* Modes valid for Neon D registers. */ 1085 #define VALID_NEON_DREG_MODE(MODE) \ 1086 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1087 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \ 1088 || (MODE) == V4BFmode) 1089 1090 /* Modes valid for Neon Q registers. */ 1091 #define VALID_NEON_QREG_MODE(MODE) \ 1092 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1093 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ 1094 || (MODE) == V8BFmode) 1095 1096 #define VALID_MVE_MODE(MODE) \ 1097 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1098 || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ 1099 || (MODE) == V2DFmode) 1100 1101 #define VALID_MVE_SI_MODE(MODE) \ 1102 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1103 || (MODE) == V16QImode) 1104 1105 #define VALID_MVE_SF_MODE(MODE) \ 1106 ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) 1107 1108 /* Structure modes valid for Neon registers. */ 1109 #define VALID_NEON_STRUCT_MODE(MODE) \ 1110 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1111 || (MODE) == CImode || (MODE) == XImode) 1112 1113 #define VALID_MVE_STRUCT_MODE(MODE) \ 1114 ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) 1115 1116 /* The conditions under which vector modes are supported for general 1117 arithmetic using Neon. */ 1118 1119 #define ARM_HAVE_NEON_V8QI_ARITH TARGET_NEON 1120 #define ARM_HAVE_NEON_V4HI_ARITH TARGET_NEON 1121 #define ARM_HAVE_NEON_V2SI_ARITH TARGET_NEON 1122 1123 #define ARM_HAVE_NEON_V16QI_ARITH TARGET_NEON 1124 #define ARM_HAVE_NEON_V8HI_ARITH TARGET_NEON 1125 #define ARM_HAVE_NEON_V4SI_ARITH TARGET_NEON 1126 #define ARM_HAVE_NEON_V2DI_ARITH TARGET_NEON 1127 1128 /* HF operations have their own flush-to-zero control (FPSCR.FZ16). */ 1129 #define ARM_HAVE_NEON_V4HF_ARITH TARGET_NEON_FP16INST 1130 #define ARM_HAVE_NEON_V8HF_ARITH TARGET_NEON_FP16INST 1131 1132 /* SF operations always flush to zero, regardless of FPSCR.FZ, so we can 1133 only use them for general arithmetic when -funsafe-math-optimizations 1134 is in effect. */ 1135 #define ARM_HAVE_NEON_V2SF_ARITH \ 1136 (TARGET_NEON && flag_unsafe_math_optimizations) 1137 #define ARM_HAVE_NEON_V4SF_ARITH ARM_HAVE_NEON_V2SF_ARITH 1138 1139 /* The conditions under which vector modes are supported for general 1140 arithmetic by any vector extension. */ 1141 1142 #define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT) 1143 #define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT) 1144 #define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT) 1145 1146 #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE) 1147 #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE) 1148 #define ARM_HAVE_V4SI_ARITH (ARM_HAVE_NEON_V4SI_ARITH || TARGET_HAVE_MVE) 1149 #define ARM_HAVE_V2DI_ARITH ARM_HAVE_NEON_V2DI_ARITH 1150 1151 #define ARM_HAVE_V4HF_ARITH ARM_HAVE_NEON_V4HF_ARITH 1152 #define ARM_HAVE_V2SF_ARITH ARM_HAVE_NEON_V2SF_ARITH 1153 1154 #define ARM_HAVE_V8HF_ARITH (ARM_HAVE_NEON_V8HF_ARITH || TARGET_HAVE_MVE_FLOAT) 1155 #define ARM_HAVE_V4SF_ARITH (ARM_HAVE_NEON_V4SF_ARITH || TARGET_HAVE_MVE_FLOAT) 1156 1157 /* The conditions under which vector modes are supported by load/store 1158 instructions using Neon. */ 1159 1160 #define ARM_HAVE_NEON_V8QI_LDST TARGET_NEON 1161 #define ARM_HAVE_NEON_V16QI_LDST TARGET_NEON 1162 #define ARM_HAVE_NEON_V4HI_LDST TARGET_NEON 1163 #define ARM_HAVE_NEON_V8HI_LDST TARGET_NEON 1164 #define ARM_HAVE_NEON_V2SI_LDST TARGET_NEON 1165 #define ARM_HAVE_NEON_V4SI_LDST TARGET_NEON 1166 #define ARM_HAVE_NEON_V4HF_LDST TARGET_NEON_FP16INST 1167 #define ARM_HAVE_NEON_V8HF_LDST TARGET_NEON_FP16INST 1168 #define ARM_HAVE_NEON_V4BF_LDST TARGET_BF16_SIMD 1169 #define ARM_HAVE_NEON_V8BF_LDST TARGET_BF16_SIMD 1170 #define ARM_HAVE_NEON_V2SF_LDST TARGET_NEON 1171 #define ARM_HAVE_NEON_V4SF_LDST TARGET_NEON 1172 #define ARM_HAVE_NEON_DI_LDST TARGET_NEON 1173 #define ARM_HAVE_NEON_V2DI_LDST TARGET_NEON 1174 1175 /* The conditions under which vector modes are supported by load/store 1176 instructions by any vector extension. */ 1177 1178 #define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) 1179 #define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) 1180 #define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) 1181 1182 #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) 1183 #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) 1184 #define ARM_HAVE_V4SI_LDST (ARM_HAVE_NEON_V4SI_LDST || TARGET_HAVE_MVE) 1185 #define ARM_HAVE_DI_LDST ARM_HAVE_NEON_DI_LDST 1186 #define ARM_HAVE_V2DI_LDST ARM_HAVE_NEON_V2DI_LDST 1187 1188 #define ARM_HAVE_V4HF_LDST ARM_HAVE_NEON_V4HF_LDST 1189 #define ARM_HAVE_V2SF_LDST ARM_HAVE_NEON_V2SF_LDST 1190 1191 #define ARM_HAVE_V4BF_LDST ARM_HAVE_NEON_V4BF_LDST 1192 #define ARM_HAVE_V8BF_LDST ARM_HAVE_NEON_V8BF_LDST 1193 1194 #define ARM_HAVE_V8HF_LDST (ARM_HAVE_NEON_V8HF_LDST || TARGET_HAVE_MVE_FLOAT) 1195 #define ARM_HAVE_V4SF_LDST (ARM_HAVE_NEON_V4SF_LDST || TARGET_HAVE_MVE_FLOAT) 1196 1197 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1198 extern int arm_regs_in_sequence[]; 1199 1200 /* The order in which register should be allocated. It is good to use ip 1201 since no saving is required (though calls clobber it) and it never contains 1202 function parameters. It is quite good to use lr since other calls may 1203 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1204 least likely to contain a function parameter; in addition results are 1205 returned in r0. 1206 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1207 then D8-D15. The reason for doing this is to attempt to reduce register 1208 pressure when both single- and double-precision registers are used in a 1209 function. */ 1210 1211 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1212 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1213 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1214 1215 #define REG_ALLOC_ORDER \ 1216 { \ 1217 /* General registers. */ \ 1218 3, 2, 1, 0, 12, 14, 4, 5, \ 1219 6, 7, 8, 9, 10, 11, \ 1220 /* High VFP registers. */ \ 1221 VREG(32), VREG(33), VREG(34), VREG(35), \ 1222 VREG(36), VREG(37), VREG(38), VREG(39), \ 1223 VREG(40), VREG(41), VREG(42), VREG(43), \ 1224 VREG(44), VREG(45), VREG(46), VREG(47), \ 1225 VREG(48), VREG(49), VREG(50), VREG(51), \ 1226 VREG(52), VREG(53), VREG(54), VREG(55), \ 1227 VREG(56), VREG(57), VREG(58), VREG(59), \ 1228 VREG(60), VREG(61), VREG(62), VREG(63), \ 1229 /* VFP argument registers. */ \ 1230 VREG(15), VREG(14), VREG(13), VREG(12), \ 1231 VREG(11), VREG(10), VREG(9), VREG(8), \ 1232 VREG(7), VREG(6), VREG(5), VREG(4), \ 1233 VREG(3), VREG(2), VREG(1), VREG(0), \ 1234 /* VFP call-saved registers. */ \ 1235 VREG(16), VREG(17), VREG(18), VREG(19), \ 1236 VREG(20), VREG(21), VREG(22), VREG(23), \ 1237 VREG(24), VREG(25), VREG(26), VREG(27), \ 1238 VREG(28), VREG(29), VREG(30), VREG(31), \ 1239 /* IWMMX registers. */ \ 1240 WREG(0), WREG(1), WREG(2), WREG(3), \ 1241 WREG(4), WREG(5), WREG(6), WREG(7), \ 1242 WREG(8), WREG(9), WREG(10), WREG(11), \ 1243 WREG(12), WREG(13), WREG(14), WREG(15), \ 1244 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1245 /* Registers not for general use. */ \ 1246 CC_REGNUM, VFPCC_REGNUM, \ 1247 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1248 SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ 1249 APSRGE_REGNUM, VPR_REGNUM \ 1250 } 1251 1252 #define IS_VPR_REGNUM(REGNUM) \ 1253 ((REGNUM) == VPR_REGNUM) 1254 1255 /* Use different register alloc ordering for Thumb. */ 1256 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1257 1258 /* Tell IRA to use the order we define when optimizing for size. */ 1259 #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun) 1260 1261 /* Interrupt functions can only use registers that have already been 1262 saved by the prologue, even if they would normally be 1263 call-clobbered. */ 1264 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1265 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1266 df_regs_ever_live_p (DST)) 1267 1268 /* Register and constant classes. */ 1269 1270 /* Register classes. */ 1271 enum reg_class 1272 { 1273 NO_REGS, 1274 LO_REGS, 1275 STACK_REG, 1276 BASE_REGS, 1277 HI_REGS, 1278 CALLER_SAVE_REGS, 1279 EVEN_REG, 1280 GENERAL_REGS, 1281 CORE_REGS, 1282 VFP_D0_D7_REGS, 1283 VFP_LO_REGS, 1284 VFP_HI_REGS, 1285 VFP_REGS, 1286 IWMMXT_REGS, 1287 IWMMXT_GR_REGS, 1288 CC_REG, 1289 VFPCC_REG, 1290 SFP_REG, 1291 AFP_REG, 1292 VPR_REG, 1293 ALL_REGS, 1294 LIM_REG_CLASSES 1295 }; 1296 1297 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1298 1299 /* Give names of register classes as strings for dump file. */ 1300 #define REG_CLASS_NAMES \ 1301 { \ 1302 "NO_REGS", \ 1303 "LO_REGS", \ 1304 "STACK_REG", \ 1305 "BASE_REGS", \ 1306 "HI_REGS", \ 1307 "CALLER_SAVE_REGS", \ 1308 "EVEN_REG", \ 1309 "GENERAL_REGS", \ 1310 "CORE_REGS", \ 1311 "VFP_D0_D7_REGS", \ 1312 "VFP_LO_REGS", \ 1313 "VFP_HI_REGS", \ 1314 "VFP_REGS", \ 1315 "IWMMXT_REGS", \ 1316 "IWMMXT_GR_REGS", \ 1317 "CC_REG", \ 1318 "VFPCC_REG", \ 1319 "SFP_REG", \ 1320 "AFP_REG", \ 1321 "VPR_REG", \ 1322 "ALL_REGS" \ 1323 } 1324 1325 /* Define which registers fit in which classes. 1326 This is an initializer for a vector of HARD_REG_SET 1327 of length N_REG_CLASSES. */ 1328 #define REG_CLASS_CONTENTS \ 1329 { \ 1330 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1331 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1332 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1333 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1334 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1335 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1336 { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ 1337 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1338 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1339 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1340 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1341 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1342 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1343 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1344 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1345 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1346 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1347 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1348 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1349 { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ 1350 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \ 1351 } 1352 1353 #define FP_SYSREGS \ 1354 DEF_FP_SYSREG (FPSCR) \ 1355 DEF_FP_SYSREG (FPSCR_nzcvqc) \ 1356 DEF_FP_SYSREG (VPR) \ 1357 DEF_FP_SYSREG (P0) \ 1358 DEF_FP_SYSREG (FPCXTNS) \ 1359 DEF_FP_SYSREG (FPCXTS) 1360 1361 #define DEF_FP_SYSREG(reg) reg ## _ENUM, 1362 enum vfp_sysregs_encoding { 1363 FP_SYSREGS 1364 NB_FP_SYSREGS 1365 }; 1366 #undef DEF_FP_SYSREG 1367 extern const char *fp_sysreg_names[NB_FP_SYSREGS]; 1368 1369 /* Any of the VFP register classes. */ 1370 #define IS_VFP_CLASS(X) \ 1371 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1372 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1373 1374 /* The same information, inverted: 1375 Return the class number of the smallest class containing 1376 reg number REGNO. This could be a conditional expression 1377 or could index an array. */ 1378 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1379 1380 /* The class value for index registers, and the one for base regs. */ 1381 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1382 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1383 1384 /* For the Thumb the high registers cannot be used as base registers 1385 when addressing quantities in QI or HI mode; if we don't know the 1386 mode, then we must be conservative. For MVE we need to load from 1387 memory to low regs based on given modes i.e [Rn], Rn <= LO_REGS. */ 1388 #define MODE_BASE_REG_CLASS(MODE) \ 1389 (TARGET_HAVE_MVE ? arm_mode_base_reg_class (MODE) \ 1390 :(TARGET_32BIT ? CORE_REGS \ 1391 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1392 : LO_REGS)) 1393 1394 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS 1395 instead of BASE_REGS. */ 1396 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1397 1398 /* When this hook returns true for MODE, the compiler allows 1399 registers explicitly used in the rtl to be used as spill registers 1400 but prevents the compiler from extending the lifetime of these 1401 registers. */ 1402 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1403 arm_small_register_classes_for_mode_p 1404 1405 /* Must leave BASE_REGS reloads alone */ 1406 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1407 (lra_in_progress ? NO_REGS \ 1408 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1409 ? ((true_regnum (X) == -1 ? LO_REGS \ 1410 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1411 : NO_REGS)) \ 1412 : NO_REGS)) 1413 1414 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1415 (lra_in_progress ? NO_REGS \ 1416 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1417 ? ((true_regnum (X) == -1 ? LO_REGS \ 1418 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1419 : NO_REGS)) \ 1420 : NO_REGS) 1421 1422 /* Return the register class of a scratch register needed to copy IN into 1423 or out of a register in CLASS in MODE. If it can be done directly, 1424 NO_REGS is returned. */ 1425 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1426 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1427 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1428 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1429 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1430 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1431 : TARGET_32BIT \ 1432 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1433 ? GENERAL_REGS : NO_REGS) \ 1434 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1435 1436 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1437 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1438 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1439 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1440 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1441 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1442 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1443 (TARGET_32BIT ? \ 1444 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1445 && CONSTANT_P (X)) \ 1446 ? GENERAL_REGS : \ 1447 (((MODE) == HImode && ! arm_arch4 \ 1448 && (MEM_P (X) \ 1449 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1450 && true_regnum (X) == -1))) \ 1451 ? GENERAL_REGS : NO_REGS) \ 1452 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1453 1454 /* Return the maximum number of consecutive registers 1455 needed to represent mode MODE in a register of class CLASS. 1456 ARM regs are UNITS_PER_WORD bits. 1457 FIXME: Is this true for iWMMX? */ 1458 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1459 (ARM_NUM_REGS (MODE)) 1460 1461 /* If defined, gives a class of registers that cannot be used as the 1462 operand of a SUBREG that changes the mode of the object illegally. */ 1463 1464 /* Stack layout; function entry, exit and calling. */ 1465 1466 /* Define this if pushing a word on the stack 1467 makes the stack pointer a smaller address. */ 1468 #define STACK_GROWS_DOWNWARD 1 1469 1470 /* Define this to nonzero if the nominal address of the stack frame 1471 is at the high-address end of the local variables; 1472 that is, each additional local variable allocated 1473 goes at a more negative offset in the frame. */ 1474 #define FRAME_GROWS_DOWNWARD 1 1475 1476 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1477 When present, it is one word in size, and sits at the top of the frame, 1478 between the soft frame pointer and either r7 or r11. 1479 1480 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1481 and only then if some outgoing arguments are passed on the stack. It would 1482 be tempting to also check whether the stack arguments are passed by indirect 1483 calls, but there seems to be no reason in principle why a post-reload pass 1484 couldn't convert a direct call into an indirect one. */ 1485 #define CALLER_INTERWORKING_SLOT_SIZE \ 1486 (TARGET_CALLER_INTERWORKING \ 1487 && maybe_ne (crtl->outgoing_args_size, 0) \ 1488 ? UNITS_PER_WORD : 0) 1489 1490 /* If we generate an insn to push BYTES bytes, 1491 this says how many the stack pointer really advances by. */ 1492 /* The push insns do not do this rounding implicitly. 1493 So don't define this. */ 1494 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1495 1496 /* Define this if the maximum size of all the outgoing args is to be 1497 accumulated and pushed during the prologue. The amount can be 1498 found in the variable crtl->outgoing_args_size. */ 1499 #define ACCUMULATE_OUTGOING_ARGS 1 1500 1501 /* Offset of first parameter from the argument pointer register value. */ 1502 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1503 1504 /* Amount of memory needed for an untyped call to save all possible return 1505 registers. */ 1506 #define APPLY_RESULT_SIZE arm_apply_result_size() 1507 1508 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1509 values must be in memory. On the ARM, they need only do so if larger 1510 than a word, or if they contain elements offset from zero in the struct. */ 1511 #define DEFAULT_PCC_STRUCT_RETURN 0 1512 1513 /* These bits describe the different types of function supported 1514 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1515 normal function and an interworked function, for example. Knowing the 1516 type of a function is important for determining its prologue and 1517 epilogue sequences. 1518 Note value 7 is currently unassigned. Also note that the interrupt 1519 function types all have bit 2 set, so that they can be tested for easily. 1520 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1521 machine_function structure is initialized (to zero) func_type will 1522 default to unknown. This will force the first use of arm_current_func_type 1523 to call arm_compute_func_type. */ 1524 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1525 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1526 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1527 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1528 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1529 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1530 1531 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1532 1533 /* In addition functions can have several type modifiers, 1534 outlined by these bit masks: */ 1535 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1536 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1537 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1538 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1539 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1540 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1541 1542 /* Some macros to test these flags. */ 1543 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1544 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1545 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1546 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1547 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1548 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1549 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1550 1551 1552 /* Structure used to hold the function stack frame layout. Offsets are 1553 relative to the stack pointer on function entry. Positive offsets are 1554 in the direction of stack growth. 1555 Only soft_frame is used in thumb mode. */ 1556 1557 typedef struct GTY(()) arm_stack_offsets 1558 { 1559 int saved_args; /* ARG_POINTER_REGNUM. */ 1560 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1561 int saved_regs; 1562 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1563 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1564 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1565 unsigned int saved_regs_mask; 1566 } 1567 arm_stack_offsets; 1568 1569 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1570 /* A C structure for machine-specific, per-function data. 1571 This is added to the cfun structure. */ 1572 typedef struct GTY(()) machine_function 1573 { 1574 /* Additional stack adjustment in __builtin_eh_throw. */ 1575 rtx eh_epilogue_sp_ofs; 1576 /* Records if LR has to be saved for far jumps. */ 1577 int far_jump_used; 1578 /* Records if ARG_POINTER was ever live. */ 1579 int arg_pointer_live; 1580 /* Records if the save of LR has been eliminated. */ 1581 int lr_save_eliminated; 1582 /* The size of the stack frame. Only valid after reload. */ 1583 arm_stack_offsets stack_offsets; 1584 /* Records the type of the current function. */ 1585 unsigned long func_type; 1586 /* Record if the function has a variable argument list. */ 1587 int uses_anonymous_args; 1588 /* Records if sibcalls are blocked because an argument 1589 register is needed to preserve stack alignment. */ 1590 int sibcall_blocked; 1591 /* The PIC register for this function. This might be a pseudo. */ 1592 rtx pic_reg; 1593 /* Labels for per-function Thumb call-via stubs. One per potential calling 1594 register. We can never call via LR or PC. We can call via SP if a 1595 trampoline happens to be on the top of the stack. */ 1596 rtx call_via[14]; 1597 /* Set to 1 when a return insn is output, this means that the epilogue 1598 is not needed. */ 1599 int return_used_this_function; 1600 /* When outputting Thumb-1 code, record the last insn that provides 1601 information about condition codes, and the comparison operands. */ 1602 rtx thumb1_cc_insn; 1603 rtx thumb1_cc_op0; 1604 rtx thumb1_cc_op1; 1605 /* Also record the CC mode that is supported. */ 1606 machine_mode thumb1_cc_mode; 1607 /* Set to 1 after arm_reorg has started. */ 1608 int after_arm_reorg; 1609 /* The number of bytes used to store the static chain register on the 1610 stack, above the stack frame. */ 1611 int static_chain_stack_bytes; 1612 } 1613 machine_function; 1614 #endif 1615 1616 #define ARM_Q_BIT_READ (arm_q_bit_access ()) 1617 #define ARM_GE_BITS_READ (arm_ge_bits_access ()) 1618 1619 /* As in the machine_function, a global set of call-via labels, for code 1620 that is in text_section. */ 1621 extern GTY(()) rtx thumb_call_via_label[14]; 1622 1623 /* The number of potential ways of assigning to a co-processor. */ 1624 #define ARM_NUM_COPROC_SLOTS 1 1625 1626 /* Enumeration of procedure calling standard variants. We don't really 1627 support all of these yet. */ 1628 enum arm_pcs 1629 { 1630 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1631 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1632 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1633 /* This must be the last AAPCS variant. */ 1634 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1635 ARM_PCS_ATPCS, /* ATPCS. */ 1636 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1637 ARM_PCS_UNKNOWN 1638 }; 1639 1640 /* Default procedure calling standard of current compilation unit. */ 1641 extern enum arm_pcs arm_pcs_default; 1642 1643 #if !defined (USED_FOR_TARGET) 1644 /* A C type for declaring a variable that is used as the first argument of 1645 `FUNCTION_ARG' and other related values. */ 1646 typedef struct 1647 { 1648 /* This is the number of registers of arguments scanned so far. */ 1649 int nregs; 1650 /* This is the number of iWMMXt register arguments scanned so far. */ 1651 int iwmmxt_nregs; 1652 int named_count; 1653 int nargs; 1654 /* Which procedure call variant to use for this call. */ 1655 enum arm_pcs pcs_variant; 1656 1657 /* AAPCS related state tracking. */ 1658 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1659 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1660 this argument, or -1 if using core 1661 registers. */ 1662 int aapcs_ncrn; 1663 int aapcs_next_ncrn; 1664 rtx aapcs_reg; /* Register assigned to this argument. */ 1665 int aapcs_partial; /* How many bytes are passed in regs (if 1666 split between core regs and stack. 1667 Zero otherwise. */ 1668 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1669 int can_split; /* Argument can be split between core regs 1670 and the stack. */ 1671 /* Private data for tracking VFP register allocation */ 1672 unsigned aapcs_vfp_regs_free; 1673 unsigned aapcs_vfp_reg_alloc; 1674 int aapcs_vfp_rcount; 1675 MACHMODE aapcs_vfp_rmode; 1676 } CUMULATIVE_ARGS; 1677 #endif 1678 1679 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1680 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1681 1682 /* For AAPCS, padding should never be below the argument. For other ABIs, 1683 * mimic the default. */ 1684 #define PAD_VARARGS_DOWN \ 1685 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1686 1687 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1688 for a call to a function whose data type is FNTYPE. 1689 For a library call, FNTYPE is 0. 1690 On the ARM, the offset starts at 0. */ 1691 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1692 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1693 1694 /* 1 if N is a possible register number for function argument passing. 1695 On the ARM, r0-r3 are used to pass args. */ 1696 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1697 (IN_RANGE ((REGNO), 0, 3) \ 1698 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1699 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1700 || (TARGET_IWMMXT_ABI \ 1701 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1702 1703 1704 /* If your target environment doesn't prefix user functions with an 1705 underscore, you may wish to re-define this to prevent any conflicts. */ 1706 #ifndef ARM_MCOUNT_NAME 1707 #define ARM_MCOUNT_NAME "*mcount" 1708 #endif 1709 1710 /* Call the function profiler with a given profile label. The Acorn 1711 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1712 On the ARM the full profile code will look like: 1713 .data 1714 LP1 1715 .word 0 1716 .text 1717 mov ip, lr 1718 bl mcount 1719 .word LP1 1720 1721 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1722 will output the .text section. 1723 1724 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1725 ``prof'' doesn't seem to mind about this! 1726 1727 Note - this version of the code is designed to work in both ARM and 1728 Thumb modes. */ 1729 #ifndef ARM_FUNCTION_PROFILER 1730 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1731 { \ 1732 char temp[20]; \ 1733 rtx sym; \ 1734 \ 1735 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1736 IP_REGNUM, LR_REGNUM); \ 1737 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1738 fputc ('\n', STREAM); \ 1739 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1740 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1741 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1742 } 1743 #endif 1744 1745 #ifdef THUMB_FUNCTION_PROFILER 1746 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1747 if (TARGET_ARM) \ 1748 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1749 else \ 1750 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1751 #else 1752 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1753 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1754 #endif 1755 1756 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1757 the stack pointer does not matter. The value is tested only in 1758 functions that have frame pointers. 1759 No definition is equivalent to always zero. 1760 1761 On the ARM, the function epilogue recovers the stack pointer from the 1762 frame. */ 1763 #define EXIT_IGNORE_STACK 1 1764 1765 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1766 1767 /* Determine if the epilogue should be output as RTL. 1768 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1769 #define USE_RETURN_INSN(ISCOND) \ 1770 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1771 1772 /* Definitions for register eliminations. 1773 1774 This is an array of structures. Each structure initializes one pair 1775 of eliminable registers. The "from" register number is given first, 1776 followed by "to". Eliminations of the same "from" register are listed 1777 in order of preference. 1778 1779 We have two registers that can be eliminated on the ARM. First, the 1780 arg pointer register can often be eliminated in favor of the stack 1781 pointer register. Secondly, the pseudo frame pointer register can always 1782 be eliminated; it is replaced with either the stack or the real frame 1783 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1784 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1785 1786 #define ELIMINABLE_REGS \ 1787 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1788 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1789 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1790 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1791 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1792 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1793 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1794 1795 /* Define the offset between two registers, one to be eliminated, and the 1796 other its replacement, at the start of a routine. */ 1797 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1798 if (TARGET_ARM) \ 1799 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1800 else \ 1801 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1802 1803 /* Special case handling of the location of arguments passed on the stack. */ 1804 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1805 1806 /* Initialize data used by insn expanders. This is called from insn_emit, 1807 once for every function before code is generated. */ 1808 #define INIT_EXPANDERS arm_init_expanders () 1809 1810 /* Length in units of the trampoline for entering a nested function. */ 1811 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20)) 1812 1813 /* Alignment required for a trampoline in bits. */ 1814 #define TRAMPOLINE_ALIGNMENT 32 1815 1816 /* Addressing modes, and classification of registers for them. */ 1817 #define HAVE_POST_INCREMENT 1 1818 #define HAVE_PRE_INCREMENT TARGET_32BIT 1819 #define HAVE_POST_DECREMENT TARGET_32BIT 1820 #define HAVE_PRE_DECREMENT TARGET_32BIT 1821 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1822 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1823 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1824 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1825 1826 enum arm_auto_incmodes 1827 { 1828 ARM_POST_INC, 1829 ARM_PRE_INC, 1830 ARM_POST_DEC, 1831 ARM_PRE_DEC 1832 }; 1833 1834 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1835 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1836 #define USE_LOAD_POST_INCREMENT(mode) \ 1837 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1838 #define USE_LOAD_PRE_INCREMENT(mode) \ 1839 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1840 #define USE_LOAD_POST_DECREMENT(mode) \ 1841 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1842 #define USE_LOAD_PRE_DECREMENT(mode) \ 1843 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1844 1845 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1846 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1847 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1848 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1849 1850 /* Macros to check register numbers against specific register classes. */ 1851 1852 /* These assume that REGNO is a hard or pseudo reg number. 1853 They give nonzero only if REGNO is a hard reg of the suitable class 1854 or a pseudo reg currently allocated to a suitable hard reg. */ 1855 #define TEST_REGNO(R, TEST, VALUE) \ 1856 ((R TEST VALUE) \ 1857 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1858 1859 /* Don't allow the pc to be used. */ 1860 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1861 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1862 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1863 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1864 1865 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1866 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1867 || (GET_MODE_SIZE (MODE) >= 4 \ 1868 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1869 1870 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1871 (TARGET_THUMB1 \ 1872 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1873 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1874 1875 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1876 For Thumb, we cannot use SP + reg, so reject SP. */ 1877 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1878 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1879 1880 /* For ARM code, we don't care about the mode, but for Thumb, the index 1881 must be suitable for use in a QImode load. */ 1882 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1883 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1884 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1885 1886 /* Maximum number of registers that can appear in a valid memory address. 1887 Shifts in addresses can't be by a register. */ 1888 #define MAX_REGS_PER_ADDRESS 2 1889 1890 /* Recognize any constant value that is a valid address. */ 1891 /* XXX We can address any constant, eventually... */ 1892 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1893 #define CONSTANT_ADDRESS_P(X) \ 1894 (GET_CODE (X) == SYMBOL_REF \ 1895 && (CONSTANT_POOL_ADDRESS_P (X) \ 1896 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1897 1898 /* True if SYMBOL + OFFSET constants must refer to something within 1899 SYMBOL's section. */ 1900 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1901 1902 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1903 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1904 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1905 #endif 1906 1907 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1908 #define SUBTARGET_NAME_ENCODING_LENGTHS 1909 #endif 1910 1911 /* This is a C fragment for the inside of a switch statement. 1912 Each case label should return the number of characters to 1913 be stripped from the start of a function's name, if that 1914 name starts with the indicated character. */ 1915 #define ARM_NAME_ENCODING_LENGTHS \ 1916 case '*': return 1; \ 1917 SUBTARGET_NAME_ENCODING_LENGTHS 1918 1919 /* This is how to output a reference to a user-level label named NAME. 1920 `assemble_name' uses this. */ 1921 #undef ASM_OUTPUT_LABELREF 1922 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1923 arm_asm_output_labelref (FILE, NAME) 1924 1925 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1926 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1927 if (TARGET_THUMB2) \ 1928 thumb2_asm_output_opcode (STREAM); 1929 1930 /* The EABI specifies that constructors should go in .init_array. 1931 Other targets use .ctors for compatibility. */ 1932 #ifndef ARM_EABI_CTORS_SECTION_OP 1933 #define ARM_EABI_CTORS_SECTION_OP \ 1934 "\t.section\t.init_array,\"aw\",%init_array" 1935 #endif 1936 #ifndef ARM_EABI_DTORS_SECTION_OP 1937 #define ARM_EABI_DTORS_SECTION_OP \ 1938 "\t.section\t.fini_array,\"aw\",%fini_array" 1939 #endif 1940 #define ARM_CTORS_SECTION_OP \ 1941 "\t.section\t.ctors,\"aw\",%progbits" 1942 #define ARM_DTORS_SECTION_OP \ 1943 "\t.section\t.dtors,\"aw\",%progbits" 1944 1945 /* Define CTORS_SECTION_ASM_OP. */ 1946 #undef CTORS_SECTION_ASM_OP 1947 #undef DTORS_SECTION_ASM_OP 1948 #ifndef IN_LIBGCC2 1949 # define CTORS_SECTION_ASM_OP \ 1950 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1951 # define DTORS_SECTION_ASM_OP \ 1952 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1953 #else /* !defined (IN_LIBGCC2) */ 1954 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1955 so we cannot use the definition above. */ 1956 # ifdef __ARM_EABI__ 1957 /* The .ctors section is not part of the EABI, so we do not define 1958 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1959 from trying to use it. We do define it when doing normal 1960 compilation, as .init_array can be used instead of .ctors. */ 1961 /* There is no need to emit begin or end markers when using 1962 init_array; the dynamic linker will compute the size of the 1963 array itself based on special symbols created by the static 1964 linker. However, we do need to arrange to set up 1965 exception-handling here. */ 1966 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1967 # define CTOR_LIST_END /* empty */ 1968 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1969 # define DTOR_LIST_END /* empty */ 1970 # else /* !defined (__ARM_EABI__) */ 1971 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1972 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1973 # endif /* !defined (__ARM_EABI__) */ 1974 #endif /* !defined (IN_LIBCC2) */ 1975 1976 /* True if the operating system can merge entities with vague linkage 1977 (e.g., symbols in COMDAT group) during dynamic linking. */ 1978 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1979 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1980 #endif 1981 1982 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1983 1984 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1985 and check its validity for a certain class. 1986 We have two alternate definitions for each of them. 1987 The usual definition accepts all pseudo regs; the other rejects 1988 them unless they have been allocated suitable hard regs. 1989 The symbol REG_OK_STRICT causes the latter definition to be used. 1990 Thumb-2 has the same restrictions as arm. */ 1991 #ifndef REG_OK_STRICT 1992 1993 #define ARM_REG_OK_FOR_BASE_P(X) \ 1994 (REGNO (X) <= LAST_ARM_REGNUM \ 1995 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1996 || REGNO (X) == FRAME_POINTER_REGNUM \ 1997 || REGNO (X) == ARG_POINTER_REGNUM) 1998 1999 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2000 ((REGNO (X) <= LAST_ARM_REGNUM \ 2001 && REGNO (X) != STACK_POINTER_REGNUM) \ 2002 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2003 || REGNO (X) == FRAME_POINTER_REGNUM \ 2004 || REGNO (X) == ARG_POINTER_REGNUM) 2005 2006 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2007 (REGNO (X) <= LAST_LO_REGNUM \ 2008 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2009 || (GET_MODE_SIZE (MODE) >= 4 \ 2010 && (REGNO (X) == STACK_POINTER_REGNUM \ 2011 || (X) == hard_frame_pointer_rtx \ 2012 || (X) == arg_pointer_rtx))) 2013 2014 #define REG_STRICT_P 0 2015 2016 #else /* REG_OK_STRICT */ 2017 2018 #define ARM_REG_OK_FOR_BASE_P(X) \ 2019 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2020 2021 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2022 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 2023 2024 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2025 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2026 2027 #define REG_STRICT_P 1 2028 2029 #endif /* REG_OK_STRICT */ 2030 2031 /* Now define some helpers in terms of the above. */ 2032 2033 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2034 (TARGET_THUMB1 \ 2035 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2036 : ARM_REG_OK_FOR_BASE_P (X)) 2037 2038 /* For 16-bit Thumb, a valid index register is anything that can be used in 2039 a byte load instruction. */ 2040 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2041 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2042 2043 /* Nonzero if X is a hard reg that can be used as an index 2044 or if it is a pseudo reg. On the Thumb, the stack pointer 2045 is not suitable. */ 2046 #define REG_OK_FOR_INDEX_P(X) \ 2047 (TARGET_THUMB1 \ 2048 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2049 : ARM_REG_OK_FOR_INDEX_P (X)) 2050 2051 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2052 For Thumb, we cannot use SP + reg, so reject SP. */ 2053 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2054 REG_OK_FOR_INDEX_P (X) 2055 2056 #define ARM_BASE_REGISTER_RTX_P(X) \ 2057 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 2058 2059 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2060 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2061 2062 /* Specify the machine mode that this machine uses 2063 for the index in the tablejump instruction. */ 2064 #define CASE_VECTOR_MODE Pmode 2065 2066 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ 2067 || (TARGET_THUMB1 \ 2068 && (optimize_size || flag_pic))) \ 2069 && (!target_pure_code)) 2070 2071 2072 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2073 (TARGET_THUMB1 \ 2074 ? (min >= 0 && max < 512 \ 2075 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2076 : min >= -256 && max < 256 \ 2077 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2078 : min >= 0 && max < 8192 \ 2079 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2080 : min >= -4096 && max < 4096 \ 2081 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2082 : SImode) \ 2083 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2084 : (max >= 0x200) ? HImode \ 2085 : QImode)) 2086 2087 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2088 unsigned is probably best, but may break some code. */ 2089 #ifndef DEFAULT_SIGNED_CHAR 2090 #define DEFAULT_SIGNED_CHAR 0 2091 #endif 2092 2093 /* Max number of bytes we can move from memory to memory 2094 in one reasonably fast instruction. */ 2095 #define MOVE_MAX 4 2096 2097 #undef MOVE_RATIO 2098 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2099 2100 /* Define if operations between registers always perform the operation 2101 on the full register even if a narrower mode is specified. */ 2102 #define WORD_REGISTER_OPERATIONS 1 2103 2104 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2105 will either zero-extend or sign-extend. The value of this macro should 2106 be the code that says which one of the two operations is implicitly 2107 done, UNKNOWN if none. */ 2108 #define LOAD_EXTEND_OP(MODE) \ 2109 (TARGET_THUMB ? ZERO_EXTEND : \ 2110 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2111 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2112 2113 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2114 #define SLOW_BYTE_ACCESS 0 2115 2116 /* Immediate shift counts are truncated by the output routines (or was it 2117 the assembler?). Shift counts in a register are truncated by ARM. Note 2118 that the native compiler puts too large (> 32) immediate shift counts 2119 into a register and shifts by the register, letting the ARM decide what 2120 to do instead of doing that itself. */ 2121 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2122 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2123 On the arm, Y in a register is used modulo 256 for the shift. Only for 2124 rotates is modulo 32 used. */ 2125 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2126 2127 /* Calling from registers is a massive pain. */ 2128 #define NO_FUNCTION_CSE 1 2129 2130 /* The machine modes of pointers and functions */ 2131 #define Pmode SImode 2132 #define FUNCTION_MODE Pmode 2133 2134 #define ARM_FRAME_RTX(X) \ 2135 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2136 || (X) == arg_pointer_rtx) 2137 2138 /* Try to generate sequences that don't involve branches, we can then use 2139 conditional instructions. */ 2140 #define BRANCH_COST(speed_p, predictable_p) \ 2141 ((arm_branch_cost != -1) ? arm_branch_cost : \ 2142 (current_tune->branch_cost (speed_p, predictable_p))) 2143 2144 /* False if short circuit operation is preferred. */ 2145 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2146 ((optimize_size) \ 2147 ? (TARGET_THUMB ? false : true) \ 2148 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 2149 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 2150 2151 2152 /* Position Independent Code. */ 2153 /* We decide which register to use based on the compilation options and 2154 the assembler in use; this is more general than the APCS restriction of 2155 using sb (r9) all the time. */ 2156 extern unsigned arm_pic_register; 2157 2158 /* The register number of the register used to address a table of static 2159 data addresses in memory. */ 2160 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2161 2162 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT 2163 entries would need to handle saving and restoring it). */ 2164 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC 2165 2166 /* We can't directly access anything that contains a symbol, 2167 nor can we indirect via the constant pool. One exception is 2168 UNSPEC_TLS, which is always PIC. */ 2169 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2170 (!(symbol_mentioned_p (X) \ 2171 || label_mentioned_p (X) \ 2172 || (GET_CODE (X) == SYMBOL_REF \ 2173 && CONSTANT_POOL_ADDRESS_P (X) \ 2174 && (symbol_mentioned_p (get_pool_constant (X)) \ 2175 || label_mentioned_p (get_pool_constant (X))))) \ 2176 || tls_mentioned_p (X)) 2177 2178 /* We may want to save the PIC register if it is a dedicated one. */ 2179 #define PIC_REGISTER_MAY_NEED_SAVING \ 2180 (flag_pic \ 2181 && !TARGET_SINGLE_PIC_BASE \ 2182 && !TARGET_FDPIC \ 2183 && arm_pic_register != INVALID_REGNUM) 2184 2185 /* We need to know when we are making a constant pool; this determines 2186 whether data needs to be in the GOT or can be referenced via a GOT 2187 offset. */ 2188 extern int making_const_table; 2189 2190 /* Handle pragmas for compatibility with Intel's compilers. */ 2191 /* Also abuse this to register additional C specific EABI attributes. */ 2192 #define REGISTER_TARGET_PRAGMAS() do { \ 2193 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2194 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2195 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2196 arm_lang_object_attributes_init(); \ 2197 arm_register_target_pragmas(); \ 2198 } while (0) 2199 2200 /* Condition code information. */ 2201 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2202 return the mode to be used for the comparison. */ 2203 2204 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2205 2206 #define REVERSIBLE_CC_MODE(MODE) 1 2207 2208 #define REVERSE_CONDITION(CODE,MODE) \ 2209 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2210 ? reverse_condition_maybe_unordered (code) \ 2211 : reverse_condition (code)) 2212 2213 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2214 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2215 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2216 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2217 2218 #define CC_STATUS_INIT \ 2219 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2220 2221 #undef ASM_APP_ON 2222 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2223 "\t.syntax divided\n") 2224 2225 #undef ASM_APP_OFF 2226 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2227 "\t.thumb\n\t.syntax unified\n") 2228 2229 /* Output a push or a pop instruction (only used when profiling). 2230 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2231 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2232 that r7 isn't used by the function profiler, so we can use it as a 2233 scratch reg. WARNING: This isn't safe in the general case! It may be 2234 sensitive to future changes in final.c:profile_function. */ 2235 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2236 do \ 2237 { \ 2238 if (TARGET_THUMB1 \ 2239 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2240 { \ 2241 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2242 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2243 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2244 } \ 2245 else \ 2246 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2247 } while (0) 2248 2249 2250 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2251 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2252 do \ 2253 { \ 2254 if (TARGET_THUMB1 \ 2255 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2256 { \ 2257 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2258 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2259 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2260 } \ 2261 else \ 2262 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2263 } while (0) 2264 2265 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2266 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2267 2268 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2269 default alignment from elfos.h. */ 2270 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2271 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2272 2273 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2274 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2275 ? 1 : 0) 2276 2277 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2278 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2279 2280 /* For aliases of functions we use .thumb_set instead. */ 2281 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2282 do \ 2283 { \ 2284 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2285 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2286 \ 2287 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2288 { \ 2289 fprintf (FILE, "\t.thumb_set "); \ 2290 assemble_name (FILE, LABEL1); \ 2291 fprintf (FILE, ","); \ 2292 assemble_name (FILE, LABEL2); \ 2293 fprintf (FILE, "\n"); \ 2294 } \ 2295 else \ 2296 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2297 } \ 2298 while (0) 2299 2300 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2301 /* To support -falign-* switches we need to use .p2align so 2302 that alignment directives in code sections will be padded 2303 with no-op instructions, rather than zeroes. */ 2304 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2305 if ((LOG) != 0) \ 2306 { \ 2307 if ((MAX_SKIP) == 0) \ 2308 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2309 else \ 2310 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2311 (int) (LOG), (int) (MAX_SKIP)); \ 2312 } 2313 #endif 2314 2315 /* Add two bytes to the length of conditionally executed Thumb-2 2316 instructions for the IT instruction. */ 2317 #define ADJUST_INSN_LENGTH(insn, length) \ 2318 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2319 length += 2; 2320 2321 /* Only perform branch elimination (by making instructions conditional) if 2322 we're optimizing. For Thumb-2 check if any IT instructions need 2323 outputting. */ 2324 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2325 if (TARGET_ARM && optimize) \ 2326 arm_final_prescan_insn (INSN); \ 2327 else if (TARGET_THUMB2) \ 2328 thumb2_final_prescan_insn (INSN); \ 2329 else if (TARGET_THUMB1) \ 2330 thumb1_final_prescan_insn (INSN) 2331 2332 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2333 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2334 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2335 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2336 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2337 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2338 : 0)))) 2339 2340 /* A C expression whose value is RTL representing the value of the return 2341 address for the frame COUNT steps up from the current frame. */ 2342 2343 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2344 arm_return_addr (COUNT, FRAME) 2345 2346 /* Mask of the bits in the PC that contain the real return address 2347 when running in 26-bit mode. */ 2348 #define RETURN_ADDR_MASK26 (0x03fffffc) 2349 2350 /* Pick up the return address upon entry to a procedure. Used for 2351 dwarf2 unwind information. This also enables the table driven 2352 mechanism. */ 2353 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2354 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2355 2356 /* Used to mask out junk bits from the return address, such as 2357 processor state, interrupt status, condition codes and the like. */ 2358 #define MASK_RETURN_ADDR \ 2359 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2360 in 26 bit mode, the condition codes must be masked out of the \ 2361 return address. This does not apply to ARM6 and later processors \ 2362 when running in 32 bit mode. */ \ 2363 ((arm_arch4 || TARGET_THUMB) \ 2364 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2365 : arm_gen_return_addr_mask ()) 2366 2367 2368 /* Do not emit .note.GNU-stack by default. */ 2369 #ifndef NEED_INDICATE_EXEC_STACK 2370 #define NEED_INDICATE_EXEC_STACK 0 2371 #endif 2372 2373 #define TARGET_ARM_ARCH \ 2374 (arm_base_arch) \ 2375 2376 /* The highest Thumb instruction set version supported by the chip. */ 2377 #define TARGET_ARM_ARCH_ISA_THUMB \ 2378 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2379 2380 /* Expands to an upper-case char of the target's architectural 2381 profile. */ 2382 #define TARGET_ARM_ARCH_PROFILE \ 2383 (arm_active_target.profile) 2384 2385 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2386 Bit 0 for bytes, up to bit 3 for double-words. */ 2387 #define TARGET_ARM_FEATURE_LDREX \ 2388 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2389 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2390 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2391 2392 /* Set as a bit mask indicating the available widths of hardware floating 2393 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2394 32-bit support, bit 3 indicates 64-bit support. */ 2395 #define TARGET_ARM_FP \ 2396 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2397 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2398 : 0) 2399 2400 2401 /* Set as a bit mask indicating the available widths of floating point 2402 types for hardware NEON floating point. This is the same as 2403 TARGET_ARM_FP without the 64-bit bit set. */ 2404 #define TARGET_NEON_FP \ 2405 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2406 : 0) 2407 2408 /* Name of the automatic fpu-selection option. */ 2409 #define FPUTYPE_AUTO "auto" 2410 2411 /* The maximum number of parallel loads or stores we support in an ldm/stm 2412 instruction. */ 2413 #define MAX_LDM_STM_OPS 4 2414 2415 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2416 extern const char *arm_rewrite_march (int argc, const char **argv); 2417 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2418 #define ASM_CPU_SPEC_FUNCTIONS \ 2419 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2420 { "rewrite_march", arm_rewrite_march }, \ 2421 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2422 2423 #define ASM_CPU_SPEC \ 2424 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2425 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2426 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2427 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2428 " }" 2429 2430 extern const char *arm_target_mode (int argc, const char **argv); 2431 #define TARGET_MODE_SPEC_FUNCTIONS \ 2432 { "target_mode_check", arm_target_mode }, 2433 2434 /* -mcpu=native handling only makes sense with compiler running on 2435 an ARM chip. */ 2436 #if defined(__arm__) 2437 extern const char *host_detect_local_cpu (int argc, const char **argv); 2438 #define HAVE_LOCAL_CPU_DETECT 2439 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2440 { "local_cpu_detect", host_detect_local_cpu }, 2441 # define MCPU_MTUNE_NATIVE_SPECS \ 2442 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2443 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2444 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2445 #else 2446 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2447 # define MCPU_MTUNE_NATIVE_SPECS "" 2448 #endif 2449 2450 const char *arm_canon_arch_option (int argc, const char **argv); 2451 const char *arm_canon_arch_multilib_option (int argc, const char **argv); 2452 2453 #define CANON_ARCH_SPEC_FUNCTION \ 2454 { "canon_arch", arm_canon_arch_option }, 2455 2456 #define CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2457 { "canon_arch_multilib", arm_canon_arch_multilib_option }, 2458 2459 const char *arm_be8_option (int argc, const char **argv); 2460 #define BE8_SPEC_FUNCTION \ 2461 { "be8_linkopt", arm_be8_option }, 2462 2463 # define EXTRA_SPEC_FUNCTIONS \ 2464 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2465 ASM_CPU_SPEC_FUNCTIONS \ 2466 CANON_ARCH_SPEC_FUNCTION \ 2467 CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2468 TARGET_MODE_SPEC_FUNCTIONS \ 2469 BE8_SPEC_FUNCTION 2470 2471 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2472 via the configuration option --with-mode or via the command line. The 2473 function target_mode_check is called to do the check with either: 2474 - an array of -march values if any is given; 2475 - an array of -mcpu values if any is given; 2476 - an empty array. */ 2477 #define TARGET_MODE_SPECS \ 2478 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2479 2480 /* Generate a canonical string to represent the architecture selected. */ 2481 #define ARCH_CANONICAL_SPECS \ 2482 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2483 " %{march=*: arch %*} " \ 2484 " %{mfpu=*: fpu %*} " \ 2485 " %{mfloat-abi=*: abi %*}" \ 2486 " %<march=*) " 2487 2488 /* Generate a canonical string to represent the architecture selected ignoring 2489 the options not required for multilib linking. */ 2490 #define MULTILIB_ARCH_CANONICAL_SPECS \ 2491 "-mlibarch=%:canon_arch_multilib(%{mcpu=*: cpu %*} " \ 2492 " %{march=*: arch %*} " \ 2493 " %{mfpu=*: fpu %*} " \ 2494 " %{mfloat-abi=*: abi %*}" \ 2495 " %<mlibarch=*) " 2496 2497 /* Complete set of specs for the driver. Commas separate the 2498 individual rules so that any option suppression (%<opt...)is 2499 completed before starting subsequent rules. */ 2500 #define DRIVER_SELF_SPECS \ 2501 MCPU_MTUNE_NATIVE_SPECS, \ 2502 TARGET_MODE_SPECS, \ 2503 MULTILIB_ARCH_CANONICAL_SPECS, \ 2504 ARCH_CANONICAL_SPECS 2505 2506 #define TARGET_SUPPORTS_WIDE_INT 1 2507 2508 /* For switching between functions with different target attributes. */ 2509 #define SWITCHABLE_TARGET 1 2510 2511 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2512 representation for SHF_ARM_PURECODE in GCC. */ 2513 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2514 2515 #endif /* ! GCC_ARM_H */ 2516