1 /* Common hooks of Andes NDS32 cpu for GNU compiler
2 Copyright (C) 2012-2021 Free Software Foundation, Inc.
3 Contributed by Andes Technology Corporation.
4
5 This file is part of GCC.
6
7 GCC is free software; you can redistribute it and/or modify it
8 under the terms of the GNU General Public License as published
9 by the Free Software Foundation; either version 3, or (at your
10 option) any later version.
11
12 GCC is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
20
21 #include "config.h"
22 #include "system.h"
23 #include "coretypes.h"
24 #include "diagnostic-core.h"
25 #include "tm.h"
26 #include "common/common-target.h"
27 #include "common/common-target-def.h"
28 #include "opts.h"
29 #include "flags.h"
30
31 /* ------------------------------------------------------------------------ */
32
33 /* Implement TARGET_HANDLE_OPTION. */
34 static bool
nds32_handle_option(struct gcc_options * opts ATTRIBUTE_UNUSED,struct gcc_options * opts_set ATTRIBUTE_UNUSED,const struct cl_decoded_option * decoded,location_t loc)35 nds32_handle_option (struct gcc_options *opts ATTRIBUTE_UNUSED,
36 struct gcc_options *opts_set ATTRIBUTE_UNUSED,
37 const struct cl_decoded_option *decoded,
38 location_t loc)
39 {
40 size_t code = decoded->opt_index;
41 int value = decoded->value;
42
43 switch (code)
44 {
45 case OPT_misr_vector_size_:
46 /* Check the valid vector size: 4 or 16. */
47 if (value != 4 && value != 16)
48 {
49 error_at (loc, "%<-misr-vector-size=%d%> argument must be 4 or 16", value);
50 return false;
51 }
52
53 return true;
54
55 case OPT_misr_secure_:
56 /* Check the valid security level: 0 1 2 3. */
57 if (value < 0 || value > 3)
58 {
59 error_at (loc, "%<-misr-secure=%d%> argument not in between 0 and 3",
60 value);
61 return false;
62 }
63 return true;
64
65 case OPT_mcache_block_size_:
66 /* Check valid value: 4 8 16 32 64 128 256 512. */
67 if (exact_log2 (value) < 2 || exact_log2 (value) > 9)
68 {
69 error_at (loc, "for the option %<-mcache-block-size=X%>, the valid X "
70 "must be: 4, 8, 16, 32, 64, 128, 256, or 512");
71 return false;
72 }
73
74 return true;
75
76 default:
77 return true;
78 }
79 }
80
81 /* ------------------------------------------------------------------------ */
82
83 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
84 static const struct default_options nds32_option_optimization_table[] =
85 {
86 #if TARGET_LINUX_ABI == 0
87 /* Disable -fdelete-null-pointer-checks by default in ELF toolchain. */
88 { OPT_LEVELS_ALL, OPT_fdelete_null_pointer_checks,
89 NULL, 0 },
90 #endif
91 /* Enable -fsched-pressure by default at -O1 and above. */
92 { OPT_LEVELS_1_PLUS, OPT_fsched_pressure, NULL, 1 },
93 /* Enable -fomit-frame-pointer by default at all optimization levels. */
94 { OPT_LEVELS_ALL, OPT_fomit_frame_pointer, NULL, 1 },
95 /* Enable -mrelax-hint by default at all optimization levels. */
96 { OPT_LEVELS_ALL, OPT_mrelax_hint, NULL, 1 },
97 /* Enalbe -malways-align by default at -O1 and above, but not -Os or -Og. */
98 { OPT_LEVELS_1_PLUS_SPEED_ONLY, OPT_malways_align, NULL, 1 },
99 /* Enable -mv3push by default at -Os, but it is useless under V2 ISA. */
100 { OPT_LEVELS_SIZE, OPT_mv3push, NULL, 1 },
101
102 { OPT_LEVELS_NONE, 0, NULL, 0 }
103 };
104
105 /* ------------------------------------------------------------------------ */
106
107 /* Implement TARGET_EXCEPT_UNWIND_INFO. */
108 static enum unwind_info_type
nds32_except_unwind_info(struct gcc_options * opts ATTRIBUTE_UNUSED)109 nds32_except_unwind_info (struct gcc_options *opts ATTRIBUTE_UNUSED)
110 {
111 if (TARGET_LINUX_ABI)
112 return UI_DWARF2;
113
114 return UI_SJLJ;
115 }
116
117 /* ------------------------------------------------------------------------ */
118
119
120 /* Run-time Target Specification. */
121
122 /* The default target flags consist of
123 TARGET_CPU_DEFAULT and other MASK_XXX flags.
124
125 The value of TARGET_CPU_DEFAULT is set by
126 the process of 'configure' and 'make' stage.
127 Please check gcc/config.gcc for more implementation detail.
128
129 Other MASK_XXX flags are set individually.
130 By default we enable
131 TARGET_16_BIT : Generate 16/32 bit mixed length instruction.
132 TARGET_EXT_PERF : Generate performance extention instrcution.
133 TARGET_EXT_PERF2 : Generate performance extention version 2 instrcution.
134 TARGET_EXT_STRING : Generate string extention instrcution.
135 TARGET_HW_ABS : Generate hardware abs instruction.
136 TARGET_CMOV : Generate conditional move instruction. */
137 #undef TARGET_DEFAULT_TARGET_FLAGS
138 #define TARGET_DEFAULT_TARGET_FLAGS \
139 (TARGET_CPU_DEFAULT \
140 | TARGET_DEFAULT_FPU_ISA \
141 | TARGET_DEFAULT_FPU_FMA \
142 | MASK_16_BIT \
143 | MASK_EXT_PERF \
144 | MASK_EXT_PERF2 \
145 | MASK_EXT_STRING \
146 | MASK_HW_ABS \
147 | MASK_CMOV)
148
149 #undef TARGET_HANDLE_OPTION
150 #define TARGET_HANDLE_OPTION nds32_handle_option
151
152 #undef TARGET_OPTION_OPTIMIZATION_TABLE
153 #define TARGET_OPTION_OPTIMIZATION_TABLE nds32_option_optimization_table
154
155
156 /* Defining the Output Assembler Language. */
157
158 #undef TARGET_EXCEPT_UNWIND_INFO
159 #define TARGET_EXCEPT_UNWIND_INFO nds32_except_unwind_info
160
161 /* ------------------------------------------------------------------------ */
162
163 struct gcc_targetm_common targetm_common = TARGETM_COMMON_INITIALIZER;
164
165 /* ------------------------------------------------------------------------ */
166