1;; Scheduling description for Alpha EV6. 2;; Copyright (C) 2002-2021 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20; EV6 can issue 4 insns per clock. It's out-of-order, so this isn't 21; expected to help over-much, but a precise description can be important 22; for software pipelining. 23; 24; EV6 has two symmetric pairs ("clusters") of two asymmetric integer 25; units ("upper" and "lower"), yielding pipe names U0, U1, L0, L1. 26; 27; ??? The clusters have independent register files that are re-synced 28; every cycle. Thus there is one additional cycle of latency between 29; insns issued on different clusters. Possibly model that by duplicating 30; all EBOX insn_reservations that can issue to either cluster, increasing 31; all latencies by one, and adding bypasses within the cluster. 32; 33; ??? In addition, instruction order affects cluster issue. 34 35(define_automaton "ev6_0,ev6_1") 36(define_cpu_unit "ev6_u0,ev6_u1,ev6_l0,ev6_l1" "ev6_0") 37(define_reservation "ev6_u" "ev6_u0|ev6_u1") 38(define_reservation "ev6_l" "ev6_l0|ev6_l1") 39(define_reservation "ev6_ebox" "ev6_u|ev6_l") 40 41(define_cpu_unit "ev6_fa" "ev6_1") 42(define_cpu_unit "ev6_fm,ev6_fst0,ev6_fst1" "ev6_0") 43(define_reservation "ev6_fst" "ev6_fst0|ev6_fst1") 44 45; Assume type "multi" single issues. 46(define_insn_reservation "ev6_multi" 1 47 (and (eq_attr "tune" "ev6") 48 (eq_attr "type" "multi")) 49 "ev6_u0+ev6_u1+ev6_l0+ev6_l1+ev6_fa+ev6_fm+ev6_fst0+ev6_fst1") 50 51; Integer loads take at least 3 clocks, and only issue to lower units. 52; adjust_cost still factors in user-specified memory latency, so return 1 here. 53(define_insn_reservation "ev6_ild" 1 54 (and (eq_attr "tune" "ev6") 55 (eq_attr "type" "ild,ldsym,ld_l")) 56 "ev6_l") 57 58(define_insn_reservation "ev6_ist" 1 59 (and (eq_attr "tune" "ev6") 60 (eq_attr "type" "ist,st_c")) 61 "ev6_l") 62 63(define_insn_reservation "ev6_mb" 1 64 (and (eq_attr "tune" "ev6") 65 (eq_attr "type" "mb")) 66 "ev6_l1") 67 68; FP loads take at least 4 clocks. adjust_cost still factors 69; in user-specified memory latency, so return 2 here. 70(define_insn_reservation "ev6_fld" 2 71 (and (eq_attr "tune" "ev6") 72 (eq_attr "type" "fld")) 73 "ev6_l") 74 75; The FPU communicates with memory and the integer register file 76; via two fp store units. We need a slot in the fst immediately, and 77; a slot in LOW after the operand data is ready. At which point the 78; data may be moved either to the store queue or the integer register 79; file and the insn retired. 80 81(define_insn_reservation "ev6_fst" 3 82 (and (eq_attr "tune" "ev6") 83 (eq_attr "type" "fst")) 84 "ev6_fst,nothing,ev6_l") 85 86; Arithmetic goes anywhere. 87(define_insn_reservation "ev6_arith" 1 88 (and (eq_attr "tune" "ev6") 89 (eq_attr "type" "iadd,ilog,icmp")) 90 "ev6_ebox") 91 92; Motion video insns also issue only to U0, and take three ticks. 93(define_insn_reservation "ev6_mvi" 3 94 (and (eq_attr "tune" "ev6") 95 (eq_attr "type" "mvi")) 96 "ev6_u0") 97 98; Shifts issue to upper units. 99(define_insn_reservation "ev6_shift" 1 100 (and (eq_attr "tune" "ev6") 101 (eq_attr "type" "shift")) 102 "ev6_u") 103 104; Multiplies issue only to U1, and all take 7 ticks. 105(define_insn_reservation "ev6_imul" 7 106 (and (eq_attr "tune" "ev6") 107 (eq_attr "type" "imul")) 108 "ev6_u1") 109 110; Conditional moves decompose into two independent primitives, each taking 111; one cycle. Since ev6 is out-of-order, we can't see anything but two cycles. 112(define_insn_reservation "ev6_icmov" 2 113 (and (eq_attr "tune" "ev6") 114 (eq_attr "type" "icmov")) 115 "ev6_ebox,ev6_ebox") 116 117; Integer branches issue to upper units 118(define_insn_reservation "ev6_ibr" 1 119 (and (eq_attr "tune" "ev6") 120 (eq_attr "type" "ibr,callpal")) 121 "ev6_u") 122 123; Calls only issue to L0. 124(define_insn_reservation "ev6_jsr" 1 125 (and (eq_attr "tune" "ev6") 126 (eq_attr "type" "jsr")) 127 "ev6_l0") 128 129; Ftoi/itof only issue to lower pipes. 130(define_insn_reservation "ev6_itof" 3 131 (and (eq_attr "tune" "ev6") 132 (eq_attr "type" "itof")) 133 "ev6_l") 134 135(define_insn_reservation "ev6_ftoi" 3 136 (and (eq_attr "tune" "ev6") 137 (eq_attr "type" "ftoi")) 138 "ev6_fst,nothing,ev6_l") 139 140(define_insn_reservation "ev6_fmul" 4 141 (and (eq_attr "tune" "ev6") 142 (eq_attr "type" "fmul")) 143 "ev6_fm") 144 145(define_insn_reservation "ev6_fadd" 4 146 (and (eq_attr "tune" "ev6") 147 (eq_attr "type" "fadd,fcpys,fbr")) 148 "ev6_fa") 149 150(define_bypass 6 "ev6_fmul,ev6_fadd" "ev6_fst,ev6_ftoi") 151 152(define_insn_reservation "ev6_fcmov" 8 153 (and (eq_attr "tune" "ev6") 154 (eq_attr "type" "fcmov")) 155 "ev6_fa,nothing*3,ev6_fa") 156 157(define_bypass 10 "ev6_fcmov" "ev6_fst,ev6_ftoi") 158 159(define_insn_reservation "ev6_fdivsf" 12 160 (and (eq_attr "tune" "ev6") 161 (and (eq_attr "type" "fdiv") 162 (eq_attr "opsize" "si"))) 163 "ev6_fa*9") 164 165(define_insn_reservation "ev6_fdivdf" 15 166 (and (eq_attr "tune" "ev6") 167 (and (eq_attr "type" "fdiv") 168 (eq_attr "opsize" "di"))) 169 "ev6_fa*12") 170 171(define_insn_reservation "ev6_sqrtsf" 18 172 (and (eq_attr "tune" "ev6") 173 (and (eq_attr "type" "fsqrt") 174 (eq_attr "opsize" "si"))) 175 "ev6_fa*15") 176 177(define_insn_reservation "ev6_sqrtdf" 33 178 (and (eq_attr "tune" "ev6") 179 (and (eq_attr "type" "fsqrt") 180 (eq_attr "opsize" "di"))) 181 "ev6_fa*30") 182