1 /* { dg-do assemble } */ 2 /* { dg-require-effective-target arm_v8_1m_mve_ok } */ 3 /* { dg-add-options arm_v8_1m_mve } */ 4 /* { dg-additional-options "-O3" } */ 5 6 #include <stdint.h> 7 8 #define FUNC(SIGN, TYPE, BITS, NB, OP, NAME) \ 9 void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a, TYPE##BITS##_t *b) { \ 10 int i; \ 11 for (i=0; i<NB; i++) { \ 12 dest[i] = a[i] OP b[i]; \ 13 } \ 14 } 15 16 #define FUNC_IMM(SIGN, TYPE, BITS, NB, OP, NAME) \ 17 void test_ ## NAME ##_ ## SIGN ## BITS ## x ## NB (TYPE##BITS##_t * __restrict__ dest, TYPE##BITS##_t *a) { \ 18 int i; \ 19 for (i=0; i<NB; i++) { \ 20 dest[i] = a[i] OP 5; \ 21 } \ 22 } 23 24 /* 64-bit vectors. */ 25 FUNC(s, int, 32, 2, <<, vshl) 26 FUNC(u, uint, 32, 2, <<, vshl) 27 FUNC(s, int, 16, 4, <<, vshl) 28 FUNC(u, uint, 16, 4, <<, vshl) 29 FUNC(s, int, 8, 8, <<, vshl) 30 FUNC(u, uint, 8, 8, <<, vshl) 31 32 /* 128-bit vectors. */ 33 FUNC(s, int, 32, 4, <<, vshl) 34 FUNC(u, uint, 32, 4, <<, vshl) 35 FUNC(s, int, 16, 8, <<, vshl) /* FIXME: not vectorized */ 36 FUNC(u, uint, 16, 8, <<, vshl) /* FIXME: not vectorized */ 37 FUNC(s, int, 8, 16, <<, vshl) /* FIXME: not vectorized */ 38 FUNC(u, uint, 8, 16, <<, vshl) /* FIXME: not vectorized */ 39 40 /* 64-bit vectors. */ 41 FUNC_IMM(s, int, 32, 2, <<, vshlimm) 42 FUNC_IMM(u, uint, 32, 2, <<, vshlimm) 43 FUNC_IMM(s, int, 16, 4, <<, vshlimm) 44 FUNC_IMM(u, uint, 16, 4, <<, vshlimm) 45 FUNC_IMM(s, int, 8, 8, <<, vshlimm) 46 FUNC_IMM(u, uint, 8, 8, <<, vshlimm) 47 48 /* 128-bit vectors. */ 49 FUNC_IMM(s, int, 32, 4, <<, vshlimm) 50 FUNC_IMM(u, uint, 32, 4, <<, vshlimm) 51 FUNC_IMM(s, int, 16, 8, <<, vshlimm) 52 FUNC_IMM(u, uint, 16, 8, <<, vshlimm) 53 FUNC_IMM(s, int, 8, 16, <<, vshlimm) 54 FUNC_IMM(u, uint, 8, 16, <<, vshlimm) 55 56 /* MVE has only 128-bit vectors, so we can vectorize only half of the 57 functions above. */ 58 /* We only emit vshl.u, which is equivalent to vshl.s anyway. */ 59 /* { dg-final { scan-assembler-times {vshl.u[0-9]+\tq[0-9]+, q[0-9]+} 2 } } */ 60 61 /* We emit vshl.i when the shift amount is an immediate. */ 62 /* { dg-final { scan-assembler-times {vshl.i[0-9]+\tq[0-9]+, q[0-9]+} 6 } } */ 63