1;; Constraint definitions for MIPS.
2;; Copyright (C) 2006-2013 Free Software Foundation, Inc.
3;;
4;; This file is part of GCC.
5;;
6;; GCC is free software; you can redistribute it and/or modify
7;; it under the terms of the GNU General Public License as published by
8;; the Free Software Foundation; either version 3, or (at your option)
9;; any later version.
10;;
11;; GCC is distributed in the hope that it will be useful,
12;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14;; GNU General Public License for more details.
15;;
16;; You should have received a copy of the GNU General Public License
17;; along with GCC; see the file COPYING3.  If not see
18;; <http://www.gnu.org/licenses/>.
19
20;; Register constraints
21
22(define_register_constraint "d" "BASE_REG_CLASS"
23  "An address register.  This is equivalent to @code{r} unless
24   generating MIPS16 code.")
25
26(define_register_constraint "t" "T_REG"
27  "@internal")
28
29(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
30  "A floating-point register (if available).")
31
32(define_register_constraint "h" "NO_REGS"
33  "Formerly the @code{hi} register.  This constraint is no longer supported.")
34
35(define_register_constraint "l" "TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
36  "The @code{lo} register.  Use this register to store values that are
37   no bigger than a word.")
38
39(define_register_constraint "x" "MD_REGS"
40  "The concatenated @code{hi} and @code{lo} registers.  Use this register
41   to store doubleword values.")
42
43(define_register_constraint "b" "ALL_REGS"
44  "@internal")
45
46;; MIPS16 code always calls through a MIPS16 register; see mips_emit_call_insn
47;; for details.
48(define_register_constraint "c" "TARGET_MIPS16 ? M16_REGS
49				 : TARGET_USE_PIC_FN_ADDR_REG ? PIC_FN_ADDR_REG
50				 : GR_REGS"
51  "A register suitable for use in an indirect jump.  This will always be
52   @code{$25} for @option{-mabicalls}.")
53
54(define_register_constraint "e" "LEA_REGS"
55  "@internal")
56
57(define_register_constraint "j" "PIC_FN_ADDR_REG"
58  "@internal")
59
60;; Don't use this constraint in gcc code!  It runs the risk of
61;; introducing a spill failure; see tls_get_tp_<mode>.
62(define_register_constraint "v" "V1_REG"
63  "Register @code{$3}.  Do not use this constraint in new code;
64   it is retained only for compatibility with glibc.")
65
66(define_register_constraint "y" "GR_REGS"
67  "Equivalent to @code{r}; retained for backwards compatibility.")
68
69(define_register_constraint "z" "ST_REGS"
70  "A floating-point condition code register.")
71
72(define_register_constraint "A" "DSP_ACC_REGS"
73  "@internal")
74
75(define_register_constraint "a" "ACC_REGS"
76  "@internal")
77
78(define_register_constraint "B" "COP0_REGS"
79  "@internal")
80
81(define_register_constraint "C" "COP2_REGS"
82  "@internal")
83
84(define_register_constraint "D" "COP3_REGS"
85  "@internal")
86
87;; Registers that can be used as the target of multiply-accumulate
88;; instructions.  The core MIPS32 ISA provides a hi/lo madd,
89;; but the DSP version allows any accumulator target.
90(define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")
91
92(define_constraint "kf"
93  "@internal"
94  (match_operand 0 "force_to_mem_operand"))
95
96;; This is a normal rather than a register constraint because we can
97;; never use the stack pointer as a reload register.
98(define_constraint "ks"
99  "@internal"
100  (and (match_code "reg")
101       (match_test "REGNO (op) == STACK_POINTER_REGNUM")))
102
103;; Integer constraints
104
105(define_constraint "I"
106  "A signed 16-bit constant (for arithmetic instructions)."
107  (and (match_code "const_int")
108       (match_test "SMALL_OPERAND (ival)")))
109
110(define_constraint "J"
111  "Integer zero."
112  (and (match_code "const_int")
113       (match_test "ival == 0")))
114
115(define_constraint "K"
116  "An unsigned 16-bit constant (for logic instructions)."
117  (and (match_code "const_int")
118       (match_test "SMALL_OPERAND_UNSIGNED (ival)")))
119
120(define_constraint "L"
121  "A signed 32-bit constant in which the lower 16 bits are zero.
122   Such constants can be loaded using @code{lui}."
123  (and (match_code "const_int")
124       (match_test "LUI_OPERAND (ival)")))
125
126(define_constraint "M"
127  "A constant that cannot be loaded using @code{lui}, @code{addiu}
128   or @code{ori}."
129  (and (match_code "const_int")
130       (not (match_test "SMALL_OPERAND (ival)"))
131       (not (match_test "SMALL_OPERAND_UNSIGNED (ival)"))
132       (not (match_test "LUI_OPERAND (ival)"))))
133
134(define_constraint "N"
135  "A constant in the range -65535 to -1 (inclusive)."
136  (and (match_code "const_int")
137       (match_test "ival >= -0xffff && ival < 0")))
138
139(define_constraint "O"
140  "A signed 15-bit constant."
141  (and (match_code "const_int")
142       (match_test "ival >= -0x4000 && ival < 0x4000")))
143
144(define_constraint "P"
145  "A constant in the range 1 to 65535 (inclusive)."
146  (and (match_code "const_int")
147       (match_test "ival > 0 && ival < 0x10000")))
148
149;; Floating-point constraints
150
151(define_constraint "G"
152  "Floating-point zero."
153  (and (match_code "const_double")
154       (match_test "op == CONST0_RTX (mode)")))
155
156;; General constraints
157
158(define_constraint "Q"
159  "@internal"
160  (match_operand 0 "const_arith_operand"))
161
162(define_memory_constraint "R"
163  "An address that can be used in a non-macro load or store."
164  (and (match_code "mem")
165       (match_test "mips_address_insns (XEXP (op, 0), mode, false) == 1")))
166
167(define_constraint "S"
168  "@internal
169   A constant call address."
170  (and (match_operand 0 "call_insn_operand")
171       (match_test "CONSTANT_P (op)")))
172
173(define_constraint "T"
174  "@internal
175   A constant @code{move_operand} that cannot be safely loaded into @code{$25}
176   using @code{la}."
177  (and (match_operand 0 "move_operand")
178       (match_test "CONSTANT_P (op)")
179       (match_test "mips_dangerous_for_la25_p (op)")))
180
181(define_constraint "U"
182  "@internal
183   A constant @code{move_operand} that can be safely loaded into @code{$25}
184   using @code{la}."
185  (and (match_operand 0 "move_operand")
186       (match_test "CONSTANT_P (op)")
187       (not (match_test "mips_dangerous_for_la25_p (op)"))))
188
189(define_memory_constraint "W"
190  "@internal
191   A memory address based on a member of @code{BASE_REG_CLASS}.  This is
192   true for all non-mips16 references (although it can sometimes be implicit
193   if @samp{!TARGET_EXPLICIT_RELOCS}).  For MIPS16, it excludes stack and
194   constant-pool references."
195  (and (match_code "mem")
196       (match_operand 0 "memory_operand")
197       (ior (not (match_test "TARGET_MIPS16"))
198	    (and (not (match_operand 0 "stack_operand"))
199		 (not (match_test "CONSTANT_P (XEXP (op, 0))"))))))
200
201(define_constraint "YG"
202  "@internal
203   A vector zero."
204  (and (match_code "const_vector")
205       (match_test "op == CONST0_RTX (mode)")))
206
207(define_constraint "YA"
208  "@internal
209   An unsigned 6-bit constant."
210  (and (match_code "const_int")
211       (match_test "UIMM6_OPERAND (ival)")))
212
213(define_constraint "YB"
214  "@internal
215   A signed 10-bit constant."
216  (and (match_code "const_int")
217       (match_test "IMM10_OPERAND (ival)")))
218
219(define_constraint "Yb"
220   "@internal"
221   (match_operand 0 "qi_mask_operand"))
222
223(define_constraint "Yh"
224   "@internal"
225    (match_operand 0 "hi_mask_operand"))
226
227(define_constraint "Yw"
228   "@internal"
229    (match_operand 0 "si_mask_operand"))
230
231(define_constraint "Yx"
232   "@internal"
233   (match_operand 0 "low_bitmask_operand"))
234
235(define_memory_constraint "ZR"
236 "@internal
237  An address valid for loading/storing register exclusive"
238 (match_operand 0 "mem_noofs_operand"))
239