1 /* Definitions of Tensilica's Xtensa target machine for GNU compiler. 2 Copyright (C) 2001-2016 Free Software Foundation, Inc. 3 Contributed by Bob Wilson (bwilson@tensilica.com) at Tensilica. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 3, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 /* Get Xtensa configuration settings */ 22 #include "xtensa-config.h" 23 24 /* External variables defined in xtensa.c. */ 25 26 /* Macros used in the machine description to select various Xtensa 27 configuration options. */ 28 #ifndef XCHAL_HAVE_MUL32_HIGH 29 #define XCHAL_HAVE_MUL32_HIGH 0 30 #endif 31 #ifndef XCHAL_HAVE_RELEASE_SYNC 32 #define XCHAL_HAVE_RELEASE_SYNC 0 33 #endif 34 #ifndef XCHAL_HAVE_S32C1I 35 #define XCHAL_HAVE_S32C1I 0 36 #endif 37 #ifndef XCHAL_HAVE_THREADPTR 38 #define XCHAL_HAVE_THREADPTR 0 39 #endif 40 #ifndef XCHAL_HAVE_FP_POSTINC 41 #define XCHAL_HAVE_FP_POSTINC 0 42 #endif 43 #define TARGET_BIG_ENDIAN XCHAL_HAVE_BE 44 #define TARGET_DENSITY XCHAL_HAVE_DENSITY 45 #define TARGET_MAC16 XCHAL_HAVE_MAC16 46 #define TARGET_MUL16 XCHAL_HAVE_MUL16 47 #define TARGET_MUL32 XCHAL_HAVE_MUL32 48 #define TARGET_MUL32_HIGH XCHAL_HAVE_MUL32_HIGH 49 #define TARGET_DIV32 XCHAL_HAVE_DIV32 50 #define TARGET_NSA XCHAL_HAVE_NSA 51 #define TARGET_MINMAX XCHAL_HAVE_MINMAX 52 #define TARGET_SEXT XCHAL_HAVE_SEXT 53 #define TARGET_BOOLEANS XCHAL_HAVE_BOOLEANS 54 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP 55 #define TARGET_HARD_FLOAT_DIV XCHAL_HAVE_FP_DIV 56 #define TARGET_HARD_FLOAT_RECIP XCHAL_HAVE_FP_RECIP 57 #define TARGET_HARD_FLOAT_SQRT XCHAL_HAVE_FP_SQRT 58 #define TARGET_HARD_FLOAT_RSQRT XCHAL_HAVE_FP_RSQRT 59 #define TARGET_HARD_FLOAT_POSTINC XCHAL_HAVE_FP_POSTINC 60 #define TARGET_ABS XCHAL_HAVE_ABS 61 #define TARGET_ADDX XCHAL_HAVE_ADDX 62 #define TARGET_RELEASE_SYNC XCHAL_HAVE_RELEASE_SYNC 63 #define TARGET_S32C1I XCHAL_HAVE_S32C1I 64 #define TARGET_ABSOLUTE_LITERALS XSHAL_USE_ABSOLUTE_LITERALS 65 #define TARGET_THREADPTR XCHAL_HAVE_THREADPTR 66 #define TARGET_LOOPS XCHAL_HAVE_LOOPS 67 #define TARGET_WINDOWED_ABI (XSHAL_ABI == XTHAL_ABI_WINDOWED) 68 #define TARGET_DEBUG XCHAL_HAVE_DEBUG 69 70 #define TARGET_DEFAULT \ 71 ((XCHAL_HAVE_L32R ? 0 : MASK_CONST16) | \ 72 MASK_SERIALIZE_VOLATILE) 73 74 #ifndef HAVE_AS_TLS 75 #define HAVE_AS_TLS 0 76 #endif 77 78 79 /* Target CPU builtins. */ 80 #define TARGET_CPU_CPP_BUILTINS() \ 81 do { \ 82 builtin_assert ("cpu=xtensa"); \ 83 builtin_assert ("machine=xtensa"); \ 84 builtin_define ("__xtensa__"); \ 85 builtin_define ("__XTENSA__"); \ 86 builtin_define (TARGET_WINDOWED_ABI ? \ 87 "__XTENSA_WINDOWED_ABI__" : "__XTENSA_CALL0_ABI__");\ 88 builtin_define (TARGET_BIG_ENDIAN ? "__XTENSA_EB__" : "__XTENSA_EL__"); \ 89 if (!TARGET_HARD_FLOAT) \ 90 builtin_define ("__XTENSA_SOFT_FLOAT__"); \ 91 } while (0) 92 93 #define CPP_SPEC " %(subtarget_cpp_spec) " 94 95 #ifndef SUBTARGET_CPP_SPEC 96 #define SUBTARGET_CPP_SPEC "" 97 #endif 98 99 #define EXTRA_SPECS \ 100 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, 101 102 /* Target machine storage layout */ 103 104 /* Define this if most significant bit is lowest numbered 105 in instructions that operate on numbered bit-fields. */ 106 #define BITS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 107 108 /* Define this if most significant byte of a word is the lowest numbered. */ 109 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 110 111 /* Define this if most significant word of a multiword number is the lowest. */ 112 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 113 114 #define MAX_BITS_PER_WORD 32 115 116 /* Width of a word, in units (bytes). */ 117 #define UNITS_PER_WORD 4 118 #define MIN_UNITS_PER_WORD 4 119 120 /* Width of a floating point register. */ 121 #define UNITS_PER_FPREG 4 122 123 /* Size in bits of various types on the target machine. */ 124 #define INT_TYPE_SIZE 32 125 #define SHORT_TYPE_SIZE 16 126 #define LONG_TYPE_SIZE 32 127 #define LONG_LONG_TYPE_SIZE 64 128 #define FLOAT_TYPE_SIZE 32 129 #define DOUBLE_TYPE_SIZE 64 130 #define LONG_DOUBLE_TYPE_SIZE 64 131 132 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 133 #define POINTER_BOUNDARY 32 134 135 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 136 #define PARM_BOUNDARY 32 137 138 /* Allocation boundary (in *bits*) for the code of a function. */ 139 #define FUNCTION_BOUNDARY 32 140 141 /* Alignment of field after 'int : 0' in a structure. */ 142 #define EMPTY_FIELD_BOUNDARY 32 143 144 /* Every structure's size must be a multiple of this. */ 145 #define STRUCTURE_SIZE_BOUNDARY 8 146 147 /* There is no point aligning anything to a rounder boundary than this. */ 148 #define BIGGEST_ALIGNMENT 128 149 150 /* Set this nonzero if move instructions will actually fail to work 151 when given unaligned data. */ 152 #define STRICT_ALIGNMENT 1 153 154 /* Promote integer modes smaller than a word to SImode. Set UNSIGNEDP 155 for QImode, because there is no 8-bit load from memory with sign 156 extension. Otherwise, leave UNSIGNEDP alone, since Xtensa has 16-bit 157 loads both with and without sign extension. */ 158 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 159 do { \ 160 if (GET_MODE_CLASS (MODE) == MODE_INT \ 161 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 162 { \ 163 if ((MODE) == QImode) \ 164 (UNSIGNEDP) = 1; \ 165 (MODE) = SImode; \ 166 } \ 167 } while (0) 168 169 /* Imitate the way many other C compilers handle alignment of 170 bitfields and the structures that contain them. */ 171 #define PCC_BITFIELD_TYPE_MATTERS 1 172 173 /* Align string constants and constructors to at least a word boundary. 174 The typical use of this macro is to increase alignment for string 175 constants to be word aligned so that 'strcpy' calls that copy 176 constants can be done inline. */ 177 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 178 (!optimize_size && \ 179 (TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \ 180 && (ALIGN) < BITS_PER_WORD \ 181 ? BITS_PER_WORD \ 182 : (ALIGN)) 183 184 /* Align arrays, unions and records to at least a word boundary. 185 One use of this macro is to increase alignment of medium-size 186 data to make it all fit in fewer cache lines. Another is to 187 cause character arrays to be word-aligned so that 'strcpy' calls 188 that copy constants to character arrays can be done inline. */ 189 #undef DATA_ALIGNMENT 190 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 191 (!optimize_size && (((ALIGN) < BITS_PER_WORD) \ 192 && (TREE_CODE (TYPE) == ARRAY_TYPE \ 193 || TREE_CODE (TYPE) == UNION_TYPE \ 194 || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 195 196 /* Operations between registers always perform the operation 197 on the full register even if a narrower mode is specified. */ 198 #define WORD_REGISTER_OPERATIONS 1 199 200 /* Xtensa loads are zero-extended by default. */ 201 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 202 203 /* Standard register usage. */ 204 205 /* Number of actual hardware registers. 206 The hardware registers are assigned numbers for the compiler 207 from 0 to just below FIRST_PSEUDO_REGISTER. 208 All registers that the compiler knows about must be given numbers, 209 even those that are not normally considered general registers. 210 211 The fake frame pointer and argument pointer will never appear in 212 the generated code, since they will always be eliminated and replaced 213 by either the stack pointer or the hard frame pointer. 214 215 0 - 15 AR[0] - AR[15] 216 16 FRAME_POINTER (fake = initial sp) 217 17 ARG_POINTER (fake = initial sp + framesize) 218 18 BR[0] for floating-point CC 219 19 - 34 FR[0] - FR[15] 220 35 MAC16 accumulator */ 221 222 #define FIRST_PSEUDO_REGISTER 36 223 224 /* Return the stabs register number to use for REGNO. */ 225 #define DBX_REGISTER_NUMBER(REGNO) xtensa_dbx_register_number (REGNO) 226 227 /* 1 for registers that have pervasive standard uses 228 and are not available for the register allocator. */ 229 #define FIXED_REGISTERS \ 230 { \ 231 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 232 1, 1, 0, \ 233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 234 0, \ 235 } 236 237 /* 1 for registers not available across function calls. 238 These must include the FIXED_REGISTERS and also any 239 registers that can be used without being saved. 240 The latter must include the registers where values are returned 241 and the register where structure-value addresses are passed. 242 Aside from that, you can include as many other registers as you like. 243 244 The value encoding is the following: 245 1: register is used by all ABIs; 246 bit 1 is set: register is used by windowed ABI; 247 bit 2 is set: register is used by call0 ABI. 248 249 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 250 251 #define CALL_USED_REGISTERS \ 252 { \ 253 1, 1, 4, 4, 4, 4, 4, 4, 1, 1, 1, 1, 2, 2, 2, 2, \ 254 1, 1, 1, \ 255 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 256 1, \ 257 } 258 259 /* For non-leaf procedures on Xtensa processors, the allocation order 260 is as specified below by REG_ALLOC_ORDER. For leaf procedures, we 261 want to use the lowest numbered registers first to minimize 262 register window overflows. However, local-alloc is not smart 263 enough to consider conflicts with incoming arguments. If an 264 incoming argument in a2 is live throughout the function and 265 local-alloc decides to use a2, then the incoming argument must 266 either be spilled or copied to another register. To get around 267 this, we define ADJUST_REG_ALLOC_ORDER to redefine 268 reg_alloc_order for leaf functions such that lowest numbered 269 registers are used first with the exception that the incoming 270 argument registers are not used until after other register choices 271 have been exhausted. */ 272 273 #define REG_ALLOC_ORDER \ 274 { 8, 9, 10, 11, 12, 13, 14, 15, 7, 6, 5, 4, 3, 2, \ 275 18, \ 276 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, \ 277 0, 1, 16, 17, \ 278 35, \ 279 } 280 281 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 282 283 /* For Xtensa, the only point of this is to prevent GCC from otherwise 284 giving preference to call-used registers. To minimize window 285 overflows for the AR registers, we want to give preference to the 286 lower-numbered AR registers. For other register files, which are 287 not windowed, we still prefer call-used registers, if there are any. */ 288 extern const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER]; 289 #define LEAF_REGISTERS xtensa_leaf_regs 290 291 /* For Xtensa, no remapping is necessary, but this macro must be 292 defined if LEAF_REGISTERS is defined. */ 293 #define LEAF_REG_REMAP(REGNO) (REGNO) 294 295 /* This must be declared if LEAF_REGISTERS is set. */ 296 extern int leaf_function; 297 298 /* Internal macros to classify a register number. */ 299 300 /* 16 address registers + fake registers */ 301 #define GP_REG_FIRST 0 302 #define GP_REG_LAST 17 303 #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1) 304 305 /* Coprocessor registers */ 306 #define BR_REG_FIRST 18 307 #define BR_REG_LAST 18 308 #define BR_REG_NUM (BR_REG_LAST - BR_REG_FIRST + 1) 309 310 /* 16 floating-point registers */ 311 #define FP_REG_FIRST 19 312 #define FP_REG_LAST 34 313 #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1) 314 315 /* MAC16 accumulator */ 316 #define ACC_REG_FIRST 35 317 #define ACC_REG_LAST 35 318 #define ACC_REG_NUM (ACC_REG_LAST - ACC_REG_FIRST + 1) 319 320 #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM) 321 #define BR_REG_P(REGNO) ((unsigned) ((REGNO) - BR_REG_FIRST) < BR_REG_NUM) 322 #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM) 323 #define ACC_REG_P(REGNO) ((unsigned) ((REGNO) - ACC_REG_FIRST) < ACC_REG_NUM) 324 325 /* Return number of consecutive hard regs needed starting at reg REGNO 326 to hold something of mode MODE. */ 327 #define HARD_REGNO_NREGS(REGNO, MODE) \ 328 (FP_REG_P (REGNO) ? \ 329 ((GET_MODE_SIZE (MODE) + UNITS_PER_FPREG - 1) / UNITS_PER_FPREG) : \ 330 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 331 332 /* Value is 1 if hard register REGNO can hold a value of machine-mode 333 MODE. */ 334 extern char xtensa_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER]; 335 336 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 337 xtensa_hard_regno_mode_ok[(int) (MODE)][(REGNO)] 338 339 /* Value is 1 if it is a good idea to tie two pseudo registers 340 when one has mode MODE1 and one has mode MODE2. 341 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 342 for any hard reg, then this must be 0 for correct output. */ 343 #define MODES_TIEABLE_P(MODE1, MODE2) \ 344 ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \ 345 GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 346 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \ 347 GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)) 348 349 /* Register to use for pushing function arguments. */ 350 #define STACK_POINTER_REGNUM (GP_REG_FIRST + 1) 351 352 /* Base register for access to local variables of the function. */ 353 #define HARD_FRAME_POINTER_REGNUM (GP_REG_FIRST + \ 354 (TARGET_WINDOWED_ABI ? 7 : 15)) 355 356 /* The register number of the frame pointer register, which is used to 357 access automatic variables in the stack frame. For Xtensa, this 358 register never appears in the output. It is always eliminated to 359 either the stack pointer or the hard frame pointer. */ 360 #define FRAME_POINTER_REGNUM (GP_REG_FIRST + 16) 361 362 /* Base register for access to arguments of the function. */ 363 #define ARG_POINTER_REGNUM (GP_REG_FIRST + 17) 364 365 /* For now we don't try to use the full set of boolean registers. Without 366 software pipelining of FP operations, there's not much to gain and it's 367 a real pain to get them reloaded. */ 368 #define FPCC_REGNUM (BR_REG_FIRST + 0) 369 370 /* It is as good or better to call a constant function address than to 371 call an address kept in a register. */ 372 #define NO_FUNCTION_CSE 1 373 374 /* Xtensa processors have "register windows". GCC does not currently 375 take advantage of the possibility for variable-sized windows; instead, 376 we use a fixed window size of 8. */ 377 378 #define INCOMING_REGNO(OUT) \ 379 (TARGET_WINDOWED_ABI ? \ 380 ((GP_REG_P (OUT) && \ 381 ((unsigned) ((OUT) - GP_REG_FIRST) >= WINDOW_SIZE)) ? \ 382 (OUT) - WINDOW_SIZE : (OUT)) : (OUT)) 383 384 #define OUTGOING_REGNO(IN) \ 385 (TARGET_WINDOWED_ABI ? \ 386 ((GP_REG_P (IN) && \ 387 ((unsigned) ((IN) - GP_REG_FIRST) < WINDOW_SIZE)) ? \ 388 (IN) + WINDOW_SIZE : (IN)) : (IN)) 389 390 391 /* Define the classes of registers for register constraints in the 392 machine description. */ 393 enum reg_class 394 { 395 NO_REGS, /* no registers in set */ 396 BR_REGS, /* coprocessor boolean registers */ 397 FP_REGS, /* floating point registers */ 398 ACC_REG, /* MAC16 accumulator */ 399 SP_REG, /* sp register (aka a1) */ 400 RL_REGS, /* preferred reload regs (not sp or fp) */ 401 GR_REGS, /* integer registers except sp */ 402 AR_REGS, /* all integer registers */ 403 ALL_REGS, /* all registers */ 404 LIM_REG_CLASSES /* max value + 1 */ 405 }; 406 407 #define N_REG_CLASSES (int) LIM_REG_CLASSES 408 409 #define GENERAL_REGS AR_REGS 410 411 /* An initializer containing the names of the register classes as C 412 string constants. These names are used in writing some of the 413 debugging dumps. */ 414 #define REG_CLASS_NAMES \ 415 { \ 416 "NO_REGS", \ 417 "BR_REGS", \ 418 "FP_REGS", \ 419 "ACC_REG", \ 420 "SP_REG", \ 421 "RL_REGS", \ 422 "GR_REGS", \ 423 "AR_REGS", \ 424 "ALL_REGS" \ 425 } 426 427 /* Contents of the register classes. The Nth integer specifies the 428 contents of class N. The way the integer MASK is interpreted is 429 that register R is in the class if 'MASK & (1 << R)' is 1. */ 430 #define REG_CLASS_CONTENTS \ 431 { \ 432 { 0x00000000, 0x00000000 }, /* no registers */ \ 433 { 0x00040000, 0x00000000 }, /* coprocessor boolean registers */ \ 434 { 0xfff80000, 0x00000007 }, /* floating-point registers */ \ 435 { 0x00000000, 0x00000008 }, /* MAC16 accumulator */ \ 436 { 0x00000002, 0x00000000 }, /* stack pointer register */ \ 437 { 0x0000fffd, 0x00000000 }, /* preferred reload registers */ \ 438 { 0x0000fffd, 0x00000000 }, /* general-purpose registers */ \ 439 { 0x0003ffff, 0x00000000 }, /* integer registers */ \ 440 { 0xffffffff, 0x0000000f } /* all registers */ \ 441 } 442 443 /* A C expression whose value is a register class containing hard 444 register REGNO. In general there is more that one such class; 445 choose a class which is "minimal", meaning that no smaller class 446 also contains the register. */ 447 #define REGNO_REG_CLASS(REGNO) xtensa_regno_to_class (REGNO) 448 449 /* Use the Xtensa AR register file for base registers. 450 No index registers. */ 451 #define BASE_REG_CLASS AR_REGS 452 #define INDEX_REG_CLASS NO_REGS 453 454 /* The small_register_classes_for_mode_p hook must always return true for 455 Xtrnase, because all of the 16 AR registers may be explicitly used in 456 the RTL, as either incoming or outgoing arguments. */ 457 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 458 459 /* Stack layout; function entry, exit and calling. */ 460 461 #define STACK_GROWS_DOWNWARD 1 462 463 /* Offset within stack frame to start allocating local variables at. */ 464 #define STARTING_FRAME_OFFSET \ 465 crtl->outgoing_args_size 466 467 /* The ARG_POINTER and FRAME_POINTER are not real Xtensa registers, so 468 they are eliminated to either the stack pointer or hard frame pointer. */ 469 #define ELIMINABLE_REGS \ 470 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 471 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 472 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 473 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} 474 475 /* Specify the initial difference between the specified pair of registers. */ 476 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 477 do { \ 478 long frame_size = compute_frame_size (get_frame_size ()); \ 479 switch (FROM) \ 480 { \ 481 case FRAME_POINTER_REGNUM: \ 482 (OFFSET) = 0; \ 483 break; \ 484 case ARG_POINTER_REGNUM: \ 485 (OFFSET) = frame_size; \ 486 break; \ 487 default: \ 488 gcc_unreachable (); \ 489 } \ 490 } while (0) 491 492 /* If defined, the maximum amount of space required for outgoing 493 arguments will be computed and placed into the variable 494 'crtl->outgoing_args_size'. No space will be pushed 495 onto the stack for each call; instead, the function prologue 496 should increase the stack frame size by this amount. */ 497 #define ACCUMULATE_OUTGOING_ARGS 1 498 499 /* Offset from the argument pointer register to the first argument's 500 address. On some machines it may depend on the data type of the 501 function. If 'ARGS_GROW_DOWNWARD', this is the offset to the 502 location above the first argument's address. */ 503 #define FIRST_PARM_OFFSET(FNDECL) 0 504 505 /* Align stack frames on 128 bits for Xtensa. This is necessary for 506 128-bit datatypes defined in TIE (e.g., for Vectra). */ 507 #define STACK_BOUNDARY 128 508 509 /* Use a fixed register window size of 8. */ 510 #define WINDOW_SIZE (TARGET_WINDOWED_ABI ? 8 : 0) 511 512 /* Symbolic macros for the registers used to return integer, floating 513 point, and values of coprocessor and user-defined modes. */ 514 #define GP_RETURN (GP_REG_FIRST + 2 + WINDOW_SIZE) 515 #define GP_OUTGOING_RETURN (GP_REG_FIRST + 2) 516 517 /* Symbolic macros for the first/last argument registers. */ 518 #define GP_ARG_FIRST (GP_REG_FIRST + 2) 519 #define GP_ARG_LAST (GP_REG_FIRST + 7) 520 #define GP_OUTGOING_ARG_FIRST (GP_REG_FIRST + 2 + WINDOW_SIZE) 521 #define GP_OUTGOING_ARG_LAST (GP_REG_FIRST + 7 + WINDOW_SIZE) 522 523 #define MAX_ARGS_IN_REGISTERS 6 524 525 /* Don't worry about compatibility with PCC. */ 526 #define DEFAULT_PCC_STRUCT_RETURN 0 527 528 /* A C expression that is nonzero if REGNO is the number of a hard 529 register in which function arguments are sometimes passed. This 530 does *not* include implicit arguments such as the static chain and 531 the structure-value address. On many machines, no registers can be 532 used for this purpose since all function arguments are pushed on 533 the stack. */ 534 #define FUNCTION_ARG_REGNO_P(N) \ 535 ((N) >= GP_OUTGOING_ARG_FIRST && (N) <= GP_OUTGOING_ARG_LAST) 536 537 /* Record the number of argument words seen so far, along with a flag to 538 indicate whether these are incoming arguments. (FUNCTION_INCOMING_ARG 539 is used for both incoming and outgoing args, so a separate flag is 540 needed. */ 541 typedef struct xtensa_args 542 { 543 int arg_words; 544 int incoming; 545 } CUMULATIVE_ARGS; 546 547 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 548 init_cumulative_args (&CUM, 0) 549 550 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 551 init_cumulative_args (&CUM, 1) 552 553 /* Profiling Xtensa code is typically done with the built-in profiling 554 feature of Tensilica's instruction set simulator, which does not 555 require any compiler support. Profiling code on a real (i.e., 556 non-simulated) Xtensa processor is currently only supported by 557 GNU/Linux with glibc. The glibc version of _mcount doesn't require 558 counter variables. The _mcount function needs the current PC and 559 the current return address to identify an arc in the call graph. 560 Pass the current return address as the first argument; the current 561 PC is available as a0 in _mcount's register window. Both of these 562 values contain window size information in the two most significant 563 bits; we assume that _mcount will mask off those bits. The call to 564 _mcount uses a window size of 8 to make sure that it doesn't clobber 565 any incoming argument values. */ 566 567 #define NO_PROFILE_COUNTERS 1 568 569 #define FUNCTION_PROFILER(FILE, LABELNO) \ 570 do { \ 571 fprintf (FILE, "\t%s\ta10, a0\n", TARGET_DENSITY ? "mov.n" : "mov"); \ 572 if (flag_pic) \ 573 { \ 574 fprintf (FILE, "\tmovi\ta%d, _mcount@PLT\n", WINDOW_SIZE); \ 575 fprintf (FILE, "\tcallx%d\ta%d\n", WINDOW_SIZE, WINDOW_SIZE); \ 576 } \ 577 else \ 578 fprintf (FILE, "\tcall%d\t_mcount\n", WINDOW_SIZE); \ 579 } while (0) 580 581 /* Stack pointer value doesn't matter at exit. */ 582 #define EXIT_IGNORE_STACK 1 583 584 /* Size in bytes of the trampoline, as an integer. Make sure this is 585 a multiple of TRAMPOLINE_ALIGNMENT to avoid -Wpadded warnings. */ 586 #define TRAMPOLINE_SIZE (TARGET_WINDOWED_ABI ? \ 587 (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? \ 588 60 : 52) : \ 589 (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS ? \ 590 32 : 24)) 591 592 /* Alignment required for trampolines, in bits. */ 593 #define TRAMPOLINE_ALIGNMENT 32 594 595 /* If defined, a C expression that produces the machine-specific code 596 to setup the stack so that arbitrary frames can be accessed. 597 598 On Xtensa, a stack back-trace must always begin from the stack pointer, 599 so that the register overflow save area can be located. However, the 600 stack-walking code in GCC always begins from the hard_frame_pointer 601 register, not the stack pointer. The frame pointer is usually equal 602 to the stack pointer, but the __builtin_return_address and 603 __builtin_frame_address functions will not work if count > 0 and 604 they are called from a routine that uses alloca. These functions 605 are not guaranteed to work at all if count > 0 so maybe that is OK. 606 607 A nicer solution would be to allow the architecture-specific files to 608 specify whether to start from the stack pointer or frame pointer. That 609 would also allow us to skip the machine->accesses_prev_frame stuff that 610 we currently need to ensure that there is a frame pointer when these 611 builtin functions are used. */ 612 613 #define SETUP_FRAME_ADDRESSES xtensa_setup_frame_addresses 614 615 /* A C expression whose value is RTL representing the address in a 616 stack frame where the pointer to the caller's frame is stored. 617 Assume that FRAMEADDR is an RTL expression for the address of the 618 stack frame itself. 619 620 For Xtensa, there is no easy way to get the frame pointer if it is 621 not equivalent to the stack pointer. Moreover, the result of this 622 macro is used for continuing to walk back up the stack, so it must 623 return the stack pointer address. Thus, there is some inconsistency 624 here in that __builtin_frame_address will return the frame pointer 625 when count == 0 and the stack pointer when count > 0. */ 626 627 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 628 gen_rtx_PLUS (Pmode, frame, GEN_INT (-3 * UNITS_PER_WORD)) 629 630 /* Define this if the return address of a particular stack frame is 631 accessed from the frame pointer of the previous stack frame. */ 632 #define RETURN_ADDR_IN_PREVIOUS_FRAME TARGET_WINDOWED_ABI 633 634 /* A C expression whose value is RTL representing the value of the 635 return address for the frame COUNT steps up from the current 636 frame, after the prologue. */ 637 #define RETURN_ADDR_RTX xtensa_return_addr 638 639 /* Addressing modes, and classification of registers for them. */ 640 641 /* C expressions which are nonzero if register number NUM is suitable 642 for use as a base or index register in operand addresses. */ 643 644 #define REGNO_OK_FOR_INDEX_P(NUM) 0 645 #define REGNO_OK_FOR_BASE_P(NUM) \ 646 (GP_REG_P (NUM) || GP_REG_P ((unsigned) reg_renumber[NUM])) 647 648 /* C expressions that are nonzero if X (assumed to be a `reg' RTX) is 649 valid for use as a base or index register. */ 650 651 #ifdef REG_OK_STRICT 652 #define REG_OK_STRICT_FLAG 1 653 #else 654 #define REG_OK_STRICT_FLAG 0 655 #endif 656 657 #define BASE_REG_P(X, STRICT) \ 658 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 659 || REGNO_OK_FOR_BASE_P (REGNO (X))) 660 661 #define REG_OK_FOR_INDEX_P(X) 0 662 #define REG_OK_FOR_BASE_P(X) BASE_REG_P (X, REG_OK_STRICT_FLAG) 663 664 /* Maximum number of registers that can appear in a valid memory address. */ 665 #define MAX_REGS_PER_ADDRESS 1 666 667 /* A C expression that is 1 if the RTX X is a constant which is a 668 valid address. This is defined to be the same as 'CONSTANT_P (X)', 669 but rejecting CONST_DOUBLE. */ 670 #define CONSTANT_ADDRESS_P(X) \ 671 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 672 || GET_CODE (X) == CONST_INT || GET_CODE (X) == HIGH \ 673 || (GET_CODE (X) == CONST))) 674 675 /* A C expression that is nonzero if X is a legitimate immediate 676 operand on the target machine when generating position independent 677 code. */ 678 #define LEGITIMATE_PIC_OPERAND_P(X) \ 679 ((GET_CODE (X) != SYMBOL_REF \ 680 || (SYMBOL_REF_LOCAL_P (X) && !SYMBOL_REF_EXTERNAL_P (X))) \ 681 && GET_CODE (X) != LABEL_REF \ 682 && GET_CODE (X) != CONST) 683 684 /* Specify the machine mode that this machine uses 685 for the index in the tablejump instruction. */ 686 #define CASE_VECTOR_MODE (SImode) 687 688 /* Define this as 1 if 'char' should by default be signed; else as 0. */ 689 #define DEFAULT_SIGNED_CHAR 0 690 691 /* Max number of bytes we can move from memory to memory 692 in one reasonably fast instruction. */ 693 #define MOVE_MAX 4 694 #define MAX_MOVE_MAX 4 695 696 /* Prefer word-sized loads. */ 697 #define SLOW_BYTE_ACCESS 1 698 699 /* Shift instructions ignore all but the low-order few bits. */ 700 #define SHIFT_COUNT_TRUNCATED 1 701 702 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 703 is done just by pretending it is already truncated. */ 704 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 705 706 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 707 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) 708 709 /* Specify the machine mode that pointers have. 710 After generation of rtl, the compiler makes no further distinction 711 between pointers and any other objects of this machine mode. */ 712 #define Pmode SImode 713 714 /* A function address in a call instruction is a word address (for 715 indexing purposes) so give the MEM rtx a words's mode. */ 716 #define FUNCTION_MODE SImode 717 718 #define BRANCH_COST(speed_p, predictable_p) 3 719 720 /* How to refer to registers in assembler output. 721 This sequence is indexed by compiler's hard-register-number (see above). */ 722 #define REGISTER_NAMES \ 723 { \ 724 "a0", "sp", "a2", "a3", "a4", "a5", "a6", "a7", \ 725 "a8", "a9", "a10", "a11", "a12", "a13", "a14", "a15", \ 726 "fp", "argp", "b0", \ 727 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", \ 728 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", \ 729 "acc" \ 730 } 731 732 /* If defined, a C initializer for an array of structures containing a 733 name and a register number. This macro defines additional names 734 for hard registers, thus allowing the 'asm' option in declarations 735 to refer to registers using alternate names. */ 736 #define ADDITIONAL_REGISTER_NAMES \ 737 { \ 738 { "a1", 1 + GP_REG_FIRST } \ 739 } 740 741 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 742 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 743 744 /* Globalizing directive for a label. */ 745 #define GLOBAL_ASM_OP "\t.global\t" 746 747 /* Declare an uninitialized external linkage data object. */ 748 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 749 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 750 751 /* This is how to output an element of a case-vector that is absolute. */ 752 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \ 753 fprintf (STREAM, "%s%sL%u\n", integer_asm_op (4, TRUE), \ 754 LOCAL_LABEL_PREFIX, VALUE) 755 756 /* This is how to output an element of a case-vector that is relative. 757 This is used for pc-relative code. */ 758 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 759 do { \ 760 fprintf (STREAM, "%s%sL%u-%sL%u\n", integer_asm_op (4, TRUE), \ 761 LOCAL_LABEL_PREFIX, (VALUE), \ 762 LOCAL_LABEL_PREFIX, (REL)); \ 763 } while (0) 764 765 /* This is how to output an assembler line that says to advance the 766 location counter to a multiple of 2**LOG bytes. */ 767 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \ 768 do { \ 769 if ((LOG) != 0) \ 770 fprintf (STREAM, "\t.align\t%d\n", 1 << (LOG)); \ 771 } while (0) 772 773 /* Indicate that jump tables go in the text section. This is 774 necessary when compiling PIC code. */ 775 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 776 777 778 /* Define the strings to put out for each section in the object file. */ 779 #define TEXT_SECTION_ASM_OP "\t.text" 780 #define DATA_SECTION_ASM_OP "\t.data" 781 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 782 783 784 /* Define output to appear before the constant pool. */ 785 #define ASM_OUTPUT_POOL_PROLOGUE(FILE, FUNNAME, FUNDECL, SIZE) \ 786 do { \ 787 if ((SIZE) > 0 || !TARGET_WINDOWED_ABI) \ 788 { \ 789 resolve_unique_section ((FUNDECL), 0, flag_function_sections); \ 790 switch_to_section (function_section (FUNDECL)); \ 791 fprintf (FILE, "\t.literal_position\n"); \ 792 } \ 793 } while (0) 794 795 796 /* A C statement (with or without semicolon) to output a constant in 797 the constant pool, if it needs special treatment. */ 798 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, JUMPTO) \ 799 do { \ 800 xtensa_output_literal (FILE, X, MODE, LABELNO); \ 801 goto JUMPTO; \ 802 } while (0) 803 804 /* How to start an assembler comment. */ 805 #define ASM_COMMENT_START "#" 806 807 /* Exception handling. Xtensa uses much of the standard DWARF2 unwinding 808 machinery, but the variable size register window save areas are too 809 complicated to efficiently describe with CFI entries. The CFA must 810 still be specified in DWARF so that DW_AT_frame_base is set correctly 811 for debugging. */ 812 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, 0) 813 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (0) 814 #define DWARF_ALT_FRAME_RETURN_COLUMN 16 815 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN \ 816 + (TARGET_WINDOWED_ABI ? 0 : 1)) 817 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) + 2 : INVALID_REGNUM) 818 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 819 (flag_pic \ 820 ? (((GLOBAL) ? DW_EH_PE_indirect : 0) \ 821 | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 822 : DW_EH_PE_absptr) 823 824 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, GP_REG_FIRST + 10) 825 826 /* Emit a PC-relative relocation. */ 827 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 828 do { \ 829 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 830 assemble_name (FILE, LABEL); \ 831 fputs ("@pcrel", FILE); \ 832 } while (0) 833 834 /* Xtensa constant pool breaks the devices in crtstuff.c to control 835 section in where code resides. We have to write it as asm code. Use 836 a MOVI and let the assembler relax it -- for the .init and .fini 837 sections, the assembler knows to put the literal in the right 838 place. */ 839 #if defined(__XTENSA_WINDOWED_ABI__) 840 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 841 asm (SECTION_OP "\n\ 842 movi\ta8, " USER_LABEL_PREFIX #FUNC "\n\ 843 callx8\ta8\n" \ 844 TEXT_SECTION_ASM_OP); 845 #elif defined(__XTENSA_CALL0_ABI__) 846 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 847 asm (SECTION_OP "\n\ 848 movi\ta0, " USER_LABEL_PREFIX #FUNC "\n\ 849 callx0\ta0\n" \ 850 TEXT_SECTION_ASM_OP); 851 #endif 852