1 /* Definitions of target machine for GNU compiler for Renesas / SuperH SH. 2 Copyright (C) 1993-2019 Free Software Foundation, Inc. 3 Contributed by Steve Chamberlain (sac@cygnus.com). 4 Improved by Jim Wilson (wilson@cygnus.com). 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #ifndef GCC_SH_H 23 #define GCC_SH_H 24 25 #include "config/vxworks-dummy.h" 26 27 /* Unfortunately, insn-attrtab.c doesn't include insn-codes.h. We can't 28 include it here, because bconfig.h is also included by gencodes.c . */ 29 /* ??? No longer true. */ 30 extern int code_for_indirect_jump_scratch; 31 32 #define TARGET_CPU_CPP_BUILTINS() sh_cpu_cpp_builtins (pfile) 33 34 /* Value should be nonzero if functions must have frame pointers. 35 Zero means the frame pointer need not be set up (and parms may be accessed 36 via the stack pointer) in functions that seem suitable. */ 37 38 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 39 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 40 #endif 41 42 43 /* Nonzero if this is an ELF target - compile time only */ 44 #define TARGET_ELF 0 45 46 /* Nonzero if we should generate code using type 2E insns. */ 47 #define TARGET_SH2E (TARGET_SH2 && TARGET_SH_E) 48 49 /* Nonzero if we should generate code using type 2A insns. */ 50 #define TARGET_SH2A TARGET_HARD_SH2A 51 /* Nonzero if we should generate code using type 2A SF insns. */ 52 #define TARGET_SH2A_SINGLE (TARGET_SH2A && TARGET_SH2E) 53 /* Nonzero if we should generate code using type 2A DF insns. */ 54 #define TARGET_SH2A_DOUBLE (TARGET_HARD_SH2A_DOUBLE && TARGET_SH2A) 55 56 /* Nonzero if we should generate code using type 3E insns. */ 57 #define TARGET_SH3E (TARGET_SH3 && TARGET_SH_E) 58 59 /* Nonzero if we schedule for a superscalar implementation. */ 60 #define TARGET_SUPERSCALAR (TARGET_HARD_SH4 || TARGET_SH2A) 61 62 /* Nonzero if a double-precision FPU is available. */ 63 #define TARGET_FPU_DOUBLE (TARGET_SH4 || TARGET_SH2A_DOUBLE) 64 65 /* Nonzero if an FPU is available. */ 66 #define TARGET_FPU_ANY (TARGET_SH2E || TARGET_FPU_DOUBLE) 67 68 /* Nonzero if we're generating code for SH4a, unless the use of the 69 FPU is disabled (which makes it compatible with SH4al-dsp). */ 70 #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY) 71 72 73 /* This is not used by the SH2E calling convention */ 74 #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ 75 (! TARGET_SH2E \ 76 && ! (TARGET_HITACHI || sh_attr_renesas_p (FUN_DECL))) 77 78 #ifndef TARGET_CPU_DEFAULT 79 #define TARGET_CPU_DEFAULT SELECT_SH1 80 #define SUPPORT_SH1 1 81 #define SUPPORT_SH2E 1 82 #define SUPPORT_SH4 1 83 #define SUPPORT_SH4_SINGLE 1 84 #define SUPPORT_SH2A 1 85 #define SUPPORT_SH2A_SINGLE 1 86 #endif 87 88 #define TARGET_DIVIDE_CALL_DIV1 (sh_div_strategy == SH_DIV_CALL_DIV1) 89 #define TARGET_DIVIDE_CALL_FP (sh_div_strategy == SH_DIV_CALL_FP) 90 #define TARGET_DIVIDE_CALL_TABLE (sh_div_strategy == SH_DIV_CALL_TABLE) 91 92 #define SELECT_SH1 (MASK_SH1) 93 #define SELECT_SH2 (MASK_SH2 | SELECT_SH1) 94 #define SELECT_SH2E (MASK_SH_E | MASK_SH2 | MASK_SH1 \ 95 | MASK_FPU_SINGLE) 96 #define SELECT_SH2A (MASK_SH_E | MASK_HARD_SH2A \ 97 | MASK_HARD_SH2A_DOUBLE \ 98 | MASK_SH2 | MASK_SH1) 99 #define SELECT_SH2A_NOFPU (MASK_HARD_SH2A | MASK_SH2 | MASK_SH1) 100 #define SELECT_SH2A_SINGLE_ONLY (MASK_SH_E | MASK_HARD_SH2A | MASK_SH2 \ 101 | MASK_SH1 | MASK_FPU_SINGLE \ 102 | MASK_FPU_SINGLE_ONLY) 103 #define SELECT_SH2A_SINGLE (MASK_SH_E | MASK_HARD_SH2A \ 104 | MASK_FPU_SINGLE | MASK_HARD_SH2A_DOUBLE \ 105 | MASK_SH2 | MASK_SH1) 106 #define SELECT_SH3 (MASK_SH3 | SELECT_SH2) 107 #define SELECT_SH3E (MASK_SH_E | MASK_FPU_SINGLE | SELECT_SH3) 108 #define SELECT_SH4_NOFPU (MASK_HARD_SH4 | SELECT_SH3) 109 #define SELECT_SH4_SINGLE_ONLY (MASK_HARD_SH4 | SELECT_SH3E \ 110 | MASK_FPU_SINGLE_ONLY) 111 #define SELECT_SH4 (MASK_SH4 | MASK_SH_E | MASK_HARD_SH4 \ 112 | SELECT_SH3) 113 #define SELECT_SH4_SINGLE (MASK_FPU_SINGLE | SELECT_SH4) 114 #define SELECT_SH4A_NOFPU (MASK_SH4A | SELECT_SH4_NOFPU) 115 #define SELECT_SH4A_SINGLE_ONLY (MASK_SH4A | SELECT_SH4_SINGLE_ONLY) 116 #define SELECT_SH4A (MASK_SH4A | SELECT_SH4) 117 #define SELECT_SH4A_SINGLE (MASK_SH4A | SELECT_SH4_SINGLE) 118 119 #if SUPPORT_SH1 120 #define SUPPORT_SH2 1 121 #endif 122 #if SUPPORT_SH2 123 #define SUPPORT_SH3 1 124 #define SUPPORT_SH2A_NOFPU 1 125 #endif 126 #if SUPPORT_SH3 127 #define SUPPORT_SH4_NOFPU 1 128 #endif 129 #if SUPPORT_SH4_NOFPU 130 #define SUPPORT_SH4A_NOFPU 1 131 #define SUPPORT_SH4AL 1 132 #endif 133 134 #if SUPPORT_SH2E 135 #define SUPPORT_SH3E 1 136 #define SUPPORT_SH2A_SINGLE_ONLY 1 137 #endif 138 #if SUPPORT_SH3E 139 #define SUPPORT_SH4_SINGLE_ONLY 1 140 #endif 141 #if SUPPORT_SH4_SINGLE_ONLY 142 #define SUPPORT_SH4A_SINGLE_ONLY 1 143 #endif 144 145 #if SUPPORT_SH4 146 #define SUPPORT_SH4A 1 147 #endif 148 149 #if SUPPORT_SH4_SINGLE 150 #define SUPPORT_SH4A_SINGLE 1 151 #endif 152 153 /* Reset all target-selection flags. */ 154 #define MASK_ARCH (MASK_SH1 | MASK_SH2 | MASK_SH3 | MASK_SH_E | MASK_SH4 \ 155 | MASK_HARD_SH2A | MASK_HARD_SH2A_DOUBLE | MASK_SH4A \ 156 | MASK_HARD_SH4 | MASK_FPU_SINGLE \ 157 | MASK_FPU_SINGLE_ONLY) 158 159 /* This defaults us to big-endian. */ 160 #ifndef TARGET_ENDIAN_DEFAULT 161 #define TARGET_ENDIAN_DEFAULT 0 162 #endif 163 164 #ifndef TARGET_OPT_DEFAULT 165 #define TARGET_OPT_DEFAULT 0 166 #endif 167 168 #define TARGET_DEFAULT \ 169 (TARGET_CPU_DEFAULT | TARGET_ENDIAN_DEFAULT | TARGET_OPT_DEFAULT) 170 171 #ifndef SH_MULTILIB_CPU_DEFAULT 172 #define SH_MULTILIB_CPU_DEFAULT "m1" 173 #endif 174 175 #if TARGET_ENDIAN_DEFAULT 176 #define MULTILIB_DEFAULTS { "ml", SH_MULTILIB_CPU_DEFAULT } 177 #else 178 #define MULTILIB_DEFAULTS { "mb", SH_MULTILIB_CPU_DEFAULT } 179 #endif 180 181 #define CPP_SPEC " %(subtarget_cpp_spec) " 182 183 #ifndef SUBTARGET_CPP_SPEC 184 #define SUBTARGET_CPP_SPEC "" 185 #endif 186 187 #ifndef SUBTARGET_EXTRA_SPECS 188 #define SUBTARGET_EXTRA_SPECS 189 #endif 190 191 #define EXTRA_SPECS \ 192 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 193 { "link_emul_prefix", LINK_EMUL_PREFIX }, \ 194 { "link_default_cpu_emul", LINK_DEFAULT_CPU_EMUL }, \ 195 { "subtarget_link_emul_suffix", SUBTARGET_LINK_EMUL_SUFFIX }, \ 196 { "subtarget_link_spec", SUBTARGET_LINK_SPEC }, \ 197 { "subtarget_asm_endian_spec", SUBTARGET_ASM_ENDIAN_SPEC }, \ 198 { "subtarget_asm_relax_spec", SUBTARGET_ASM_RELAX_SPEC }, \ 199 { "subtarget_asm_isa_spec", SUBTARGET_ASM_ISA_SPEC }, \ 200 { "subtarget_asm_spec", SUBTARGET_ASM_SPEC }, \ 201 SUBTARGET_EXTRA_SPECS 202 203 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 204 #define SUBTARGET_ASM_RELAX_SPEC "%{!m1:%{!m2:%{!m3*:-isa=sh4-up}}}" 205 #else 206 #define SUBTARGET_ASM_RELAX_SPEC "%{m4*:-isa=sh4-up}" 207 #endif 208 209 /* Define which ISA type to pass to the assembler. 210 For SH4 we pass SH4A to allow using some instructions that are available 211 on some SH4 variants, but officially are part of the SH4A ISA. */ 212 #define SH_ASM_SPEC \ 213 "%(subtarget_asm_endian_spec) %{mrelax:-relax %(subtarget_asm_relax_spec)} \ 214 %(subtarget_asm_isa_spec) %(subtarget_asm_spec) \ 215 %{m1:--isa=sh} \ 216 %{m2:--isa=sh2} \ 217 %{m2e:--isa=sh2e} \ 218 %{m3:--isa=sh3} \ 219 %{m3e:--isa=sh3e} \ 220 %{m4:--isa=sh4a} \ 221 %{m4-single:--isa=sh4a} \ 222 %{m4-single-only:--isa=sh4a} \ 223 %{m4-nofpu:--isa=sh4a-nofpu} \ 224 %{m4a:--isa=sh4a} \ 225 %{m4a-single:--isa=sh4a} \ 226 %{m4a-single-only:--isa=sh4a} \ 227 %{m4a-nofpu:--isa=sh4a-nofpu} \ 228 %{m2a:--isa=sh2a} \ 229 %{m2a-single:--isa=sh2a} \ 230 %{m2a-single-only:--isa=sh2a} \ 231 %{m2a-nofpu:--isa=sh2a-nofpu} \ 232 %{m4al:-dsp}" 233 234 #define ASM_SPEC SH_ASM_SPEC 235 236 #ifndef SUBTARGET_ASM_ENDIAN_SPEC 237 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN 238 #define SUBTARGET_ASM_ENDIAN_SPEC "%{mb:-big} %{!mb:-little}" 239 #else 240 #define SUBTARGET_ASM_ENDIAN_SPEC "%{ml:-little} %{!ml:-big}" 241 #endif 242 #endif 243 244 #if STRICT_NOFPU == 1 245 /* Strict nofpu means that the compiler should tell the assembler 246 to reject FPU instructions. E.g. from ASM inserts. */ 247 #if TARGET_CPU_DEFAULT & MASK_HARD_SH4 && !(TARGET_CPU_DEFAULT & MASK_SH_E) 248 #define SUBTARGET_ASM_ISA_SPEC "%{!m1:%{!m2:%{!m3*:%{m4-nofpu|!m4*:-isa=sh4-nofpu}}}}" 249 #else 250 251 #define SUBTARGET_ASM_ISA_SPEC \ 252 "%{m4-nofpu:-isa=sh4-nofpu} " ASM_ISA_DEFAULT_SPEC 253 #endif 254 #else /* ! STRICT_NOFPU */ 255 #define SUBTARGET_ASM_ISA_SPEC ASM_ISA_DEFAULT_SPEC 256 #endif 257 258 #ifndef SUBTARGET_ASM_SPEC 259 #define SUBTARGET_ASM_SPEC "%{mfdpic:--fdpic}" 260 #endif 261 262 #if TARGET_ENDIAN_DEFAULT == MASK_LITTLE_ENDIAN 263 #define LINK_EMUL_PREFIX "sh%{!mb:l}" 264 #else 265 #define LINK_EMUL_PREFIX "sh%{ml:l}" 266 #endif 267 268 #define LINK_DEFAULT_CPU_EMUL "" 269 #define ASM_ISA_DEFAULT_SPEC "" 270 271 #define SUBTARGET_LINK_EMUL_SUFFIX "%{mfdpic:_fd}" 272 #define SUBTARGET_LINK_SPEC "" 273 274 /* Go via SH_LINK_SPEC to avoid code replication. */ 275 #define LINK_SPEC SH_LINK_SPEC 276 277 #define SH_LINK_SPEC "\ 278 -m %(link_emul_prefix)\ 279 %{!m1:%{!m2:%{!m3*:%{!m4*:%(link_default_cpu_emul)}}}}\ 280 %(subtarget_link_emul_suffix) \ 281 %{mrelax:-relax} %(subtarget_link_spec)" 282 283 #ifndef SH_DIV_STR_FOR_SIZE 284 #define SH_DIV_STR_FOR_SIZE "call" 285 #endif 286 287 /* SH2A does not support little-endian. Catch such combinations 288 taking into account the default configuration. */ 289 #if TARGET_ENDIAN_DEFAULT == MASK_BIG_ENDIAN 290 #define IS_LITTLE_ENDIAN_OPTION "%{ml:" 291 #else 292 #define IS_LITTLE_ENDIAN_OPTION "%{!mb:" 293 #endif 294 295 #if TARGET_CPU_DEFAULT & MASK_HARD_SH2A 296 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ 297 "%{m2a*|!m1:%{!m2*:%{!m3*:%{!m4*:%eSH2a does not support little-endian}}}}}" 298 #else 299 #define UNSUPPORTED_SH2A IS_LITTLE_ENDIAN_OPTION \ 300 "%{m2a*:%eSH2a does not support little-endian}}" 301 #endif 302 303 #ifdef FDPIC_DEFAULT 304 #define FDPIC_SELF_SPECS "%{!mno-fdpic:-mfdpic}" 305 #else 306 #define FDPIC_SELF_SPECS 307 #endif 308 309 #undef DRIVER_SELF_SPECS 310 #define DRIVER_SELF_SPECS UNSUPPORTED_SH2A SUBTARGET_DRIVER_SELF_SPECS \ 311 FDPIC_SELF_SPECS 312 313 #undef SUBTARGET_DRIVER_SELF_SPECS 314 #define SUBTARGET_DRIVER_SELF_SPECS 315 316 #define ASSEMBLER_DIALECT assembler_dialect 317 318 extern int assembler_dialect; 319 320 enum sh_divide_strategy_e { 321 /* SH1 .. SH4 strategies. Because of the small number of registers 322 available, the compiler uses knowledge of the actual set of registers 323 being clobbered by the different functions called. */ 324 SH_DIV_CALL_DIV1, /* No FPU, medium size, highest latency. */ 325 SH_DIV_CALL_FP, /* FPU needed, small size, high latency. */ 326 SH_DIV_CALL_TABLE, /* No FPU, large size, medium latency. */ 327 SH_DIV_INTRINSIC 328 }; 329 330 extern enum sh_divide_strategy_e sh_div_strategy; 331 332 #ifndef SH_DIV_STRATEGY_DEFAULT 333 #define SH_DIV_STRATEGY_DEFAULT SH_DIV_CALL_DIV1 334 #endif 335 336 #ifdef __cplusplus 337 338 /* Atomic model. */ 339 struct sh_atomic_model 340 { 341 enum enum_type 342 { 343 none = 0, 344 soft_gusa, 345 hard_llcs, 346 soft_tcb, 347 soft_imask, 348 349 num_models 350 }; 351 352 /* If strict is set, disallow mixing of different models, as it would 353 happen on SH4A. */ 354 bool strict; 355 enum_type type; 356 357 /* Name string as it was specified on the command line. */ 358 const char* name; 359 360 /* Name string as it is used in C/C++ defines. */ 361 const char* cdef_name; 362 363 /* GBR offset variable for TCB model. */ 364 int tcb_gbr_offset; 365 }; 366 367 extern const sh_atomic_model& selected_atomic_model (void); 368 369 /* Shortcuts to check the currently selected atomic model. */ 370 #define TARGET_ATOMIC_ANY \ 371 (selected_atomic_model ().type != sh_atomic_model::none) 372 373 #define TARGET_ATOMIC_STRICT \ 374 (selected_atomic_model ().strict) 375 376 #define TARGET_ATOMIC_SOFT_GUSA \ 377 (selected_atomic_model ().type == sh_atomic_model::soft_gusa) 378 379 #define TARGET_ATOMIC_HARD_LLCS \ 380 (selected_atomic_model ().type == sh_atomic_model::hard_llcs) 381 382 #define TARGET_ATOMIC_SOFT_TCB \ 383 (selected_atomic_model ().type == sh_atomic_model::soft_tcb) 384 385 #define TARGET_ATOMIC_SOFT_TCB_GBR_OFFSET_RTX \ 386 GEN_INT (selected_atomic_model ().tcb_gbr_offset) 387 388 #define TARGET_ATOMIC_SOFT_IMASK \ 389 (selected_atomic_model ().type == sh_atomic_model::soft_imask) 390 391 #endif // __cplusplus 392 393 #define SUBTARGET_OVERRIDE_OPTIONS (void) 0 394 395 396 /* Target machine storage layout. */ 397 398 #define TARGET_BIG_ENDIAN (!TARGET_LITTLE_ENDIAN) 399 400 #define SH_REG_MSW_OFFSET (TARGET_LITTLE_ENDIAN ? 1 : 0) 401 #define SH_REG_LSW_OFFSET (TARGET_LITTLE_ENDIAN ? 0 : 1) 402 403 /* Define this if most significant bit is lowest numbered 404 in instructions that operate on numbered bit-fields. */ 405 #define BITS_BIG_ENDIAN 0 406 407 /* Define this if most significant byte of a word is the lowest numbered. */ 408 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN 409 410 /* Define this if most significant word of a multiword number is the lowest 411 numbered. */ 412 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN 413 414 #define MAX_BITS_PER_WORD 64 415 416 /* Width in bits of an `int'. We want just 32-bits, even if words are 417 longer. */ 418 #define INT_TYPE_SIZE 32 419 420 /* Width in bits of a `long'. */ 421 #define LONG_TYPE_SIZE (32) 422 423 /* Width in bits of a `long long'. */ 424 #define LONG_LONG_TYPE_SIZE 64 425 426 /* Width in bits of a `long double'. */ 427 #define LONG_DOUBLE_TYPE_SIZE 64 428 429 /* Width of a word, in units (bytes). */ 430 #define UNITS_PER_WORD (4) 431 #define MIN_UNITS_PER_WORD 4 432 433 /* Scaling factor for Dwarf data offsets for CFI information. 434 The dwarf2out.c default would use -UNITS_PER_WORD. */ 435 #define DWARF_CIE_DATA_ALIGNMENT -4 436 437 /* Width in bits of a pointer. 438 See also the macro `Pmode' defined below. */ 439 #define POINTER_SIZE (32) 440 441 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 442 #define PARM_BOUNDARY (32) 443 444 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 445 #define STACK_BOUNDARY BIGGEST_ALIGNMENT 446 447 /* The log (base 2) of the cache line size, in bytes. Processors prior to 448 SH2 have no actual cache, but they fetch code in chunks of 4 bytes. 449 The SH2/3 have 16 byte cache lines, and the SH4 has a 32 byte cache line */ 450 #define CACHE_LOG (TARGET_HARD_SH4 ? 5 : TARGET_SH2 ? 4 : 2) 451 452 /* ABI given & required minimum allocation boundary (in *bits*) for the 453 code of a function. */ 454 #define FUNCTION_BOUNDARY (16) 455 456 /* Alignment of field after `int : 0' in a structure. */ 457 #define EMPTY_FIELD_BOUNDARY 32 458 459 /* No data type wants to be aligned rounder than this. */ 460 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_DOUBLE ? 64 : 32) 461 462 /* The best alignment to use in cases where we have a choice. */ 463 #define FASTEST_ALIGNMENT (32) 464 465 /* get_mode_alignment assumes complex values are always held in multiple 466 registers, but that is not the case on the SH; CQImode and CHImode are 467 held in a single integer register. */ 468 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 469 ((GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_INT \ 470 || GET_MODE_CLASS (TYPE_MODE (TYPE)) == MODE_COMPLEX_FLOAT) \ 471 ? (unsigned) MIN (BIGGEST_ALIGNMENT, \ 472 GET_MODE_BITSIZE (as_a <fixed_size_mode> \ 473 (TYPE_MODE (TYPE)))) \ 474 : (unsigned) DATA_ALIGNMENT(TYPE, ALIGN)) 475 476 /* Make arrays of chars word-aligned for the same reasons. */ 477 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 478 (TREE_CODE (TYPE) == ARRAY_TYPE \ 479 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 480 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 481 482 /* Number of bits which any structure or union's size must be a 483 multiple of. Each structure or union's size is rounded up to a 484 multiple of this. */ 485 #define STRUCTURE_SIZE_BOUNDARY (TARGET_PADSTRUCT ? 32 : 8) 486 487 /* Set this nonzero if move instructions will actually fail to work 488 when given unaligned data. */ 489 #define STRICT_ALIGNMENT 1 490 491 /* If LABEL_AFTER_BARRIER demands an alignment, return its base 2 logarithm. */ 492 #define LABEL_ALIGN_AFTER_BARRIER(LABEL_AFTER_BARRIER) \ 493 barrier_align (LABEL_AFTER_BARRIER) 494 495 #define LOOP_ALIGN(A_LABEL) sh_loop_align (A_LABEL) 496 497 #define LABEL_ALIGN(A_LABEL) \ 498 ( \ 499 (PREV_INSN (A_LABEL) \ 500 && NONJUMP_INSN_P (PREV_INSN (A_LABEL)) \ 501 && GET_CODE (PATTERN (PREV_INSN (A_LABEL))) == UNSPEC_VOLATILE \ 502 && XINT (PATTERN (PREV_INSN (A_LABEL)), 1) == UNSPECV_ALIGN) \ 503 /* explicit alignment insn in constant tables. */ \ 504 ? INTVAL (XVECEXP (PATTERN (PREV_INSN (A_LABEL)), 0, 0)) \ 505 : 0) 506 507 /* Jump tables must be 32 bit aligned, no matter the size of the element. */ 508 #define ADDR_VEC_ALIGN(ADDR_VEC) 2 509 510 /* The base two logarithm of the known minimum alignment of an insn length. */ 511 #define INSN_LENGTH_ALIGNMENT(A_INSN) \ 512 (NONJUMP_INSN_P (A_INSN) \ 513 ? 1 \ 514 : JUMP_P (A_INSN) || CALL_P (A_INSN) \ 515 ? 1 \ 516 : CACHE_LOG) 517 518 /* Standard register usage. */ 519 520 /* Register allocation for the Renesas calling convention: 521 522 r0 arg return 523 r1..r3 scratch 524 r4..r7 args in 525 r8..r13 call saved 526 r14 frame pointer/call saved 527 r15 stack pointer 528 ap arg pointer (doesn't really exist, always eliminated) 529 pr subroutine return address 530 t t bit 531 mach multiply/accumulate result, high part 532 macl multiply/accumulate result, low part. 533 fpul fp/int communication register 534 rap return address pointer register 535 fr0 fp arg return 536 fr1..fr3 scratch floating point registers 537 fr4..fr11 fp args in 538 fr12..fr15 call saved floating point registers */ 539 540 #define MAX_REGISTER_NAME_LENGTH 6 541 extern char sh_register_names[][MAX_REGISTER_NAME_LENGTH + 1]; 542 543 #define SH_REGISTER_NAMES_INITIALIZER \ 544 { \ 545 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 546 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 547 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", \ 548 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", \ 549 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39", \ 550 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47", \ 551 "r48", "r49", "r50", "r51", "r52", "r53", "r54", "r55", \ 552 "r56", "r57", "r58", "r59", "r60", "r61", "r62", "r63", \ 553 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", \ 554 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", \ 555 "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", \ 556 "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", \ 557 "fr32", "fr33", "fr34", "fr35", "fr36", "fr37", "fr38", "fr39", \ 558 "fr40", "fr41", "fr42", "fr43", "fr44", "fr45", "fr46", "fr47", \ 559 "fr48", "fr49", "fr50", "fr51", "fr52", "fr53", "fr54", "fr55", \ 560 "fr56", "fr57", "fr58", "fr59", "fr60", "fr61", "fr62", "fr63", \ 561 "tr0", "tr1", "tr2", "tr3", "tr4", "tr5", "tr6", "tr7", \ 562 "xd0", "xd2", "xd4", "xd6", "xd8", "xd10", "xd12", "xd14", \ 563 "gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", \ 564 "rap", "sfp", "fpscr0", "fpscr1" \ 565 } 566 567 #define REGNAMES_ARR_INDEX_1(index) \ 568 (sh_register_names[index]) 569 #define REGNAMES_ARR_INDEX_2(index) \ 570 REGNAMES_ARR_INDEX_1 ((index)), REGNAMES_ARR_INDEX_1 ((index)+1) 571 #define REGNAMES_ARR_INDEX_4(index) \ 572 REGNAMES_ARR_INDEX_2 ((index)), REGNAMES_ARR_INDEX_2 ((index)+2) 573 #define REGNAMES_ARR_INDEX_8(index) \ 574 REGNAMES_ARR_INDEX_4 ((index)), REGNAMES_ARR_INDEX_4 ((index)+4) 575 #define REGNAMES_ARR_INDEX_16(index) \ 576 REGNAMES_ARR_INDEX_8 ((index)), REGNAMES_ARR_INDEX_8 ((index)+8) 577 #define REGNAMES_ARR_INDEX_32(index) \ 578 REGNAMES_ARR_INDEX_16 ((index)), REGNAMES_ARR_INDEX_16 ((index)+16) 579 #define REGNAMES_ARR_INDEX_64(index) \ 580 REGNAMES_ARR_INDEX_32 ((index)), REGNAMES_ARR_INDEX_32 ((index)+32) 581 582 #define REGISTER_NAMES \ 583 { \ 584 REGNAMES_ARR_INDEX_64 (0), \ 585 REGNAMES_ARR_INDEX_64 (64), \ 586 REGNAMES_ARR_INDEX_8 (128), \ 587 REGNAMES_ARR_INDEX_8 (136), \ 588 REGNAMES_ARR_INDEX_8 (144), \ 589 REGNAMES_ARR_INDEX_4 (152) \ 590 } 591 592 #define ADDREGNAMES_SIZE 32 593 #define MAX_ADDITIONAL_REGISTER_NAME_LENGTH 4 594 extern char sh_additional_register_names[ADDREGNAMES_SIZE] \ 595 [MAX_ADDITIONAL_REGISTER_NAME_LENGTH + 1]; 596 597 #define SH_ADDITIONAL_REGISTER_NAMES_INITIALIZER \ 598 { \ 599 "dr0", "dr2", "dr4", "dr6", "dr8", "dr10", "dr12", "dr14", \ 600 "dr16", "dr18", "dr20", "dr22", "dr24", "dr26", "dr28", "dr30", \ 601 "dr32", "dr34", "dr36", "dr38", "dr40", "dr42", "dr44", "dr46", \ 602 "dr48", "dr50", "dr52", "dr54", "dr56", "dr58", "dr60", "dr62" \ 603 } 604 605 #define ADDREGNAMES_REGNO(index) \ 606 ((index < 32) ? (FIRST_FP_REG + (index) * 2) \ 607 : (-1)) 608 609 #define ADDREGNAMES_ARR_INDEX_1(index) \ 610 { (sh_additional_register_names[index]), ADDREGNAMES_REGNO (index) } 611 #define ADDREGNAMES_ARR_INDEX_2(index) \ 612 ADDREGNAMES_ARR_INDEX_1 ((index)), ADDREGNAMES_ARR_INDEX_1 ((index)+1) 613 #define ADDREGNAMES_ARR_INDEX_4(index) \ 614 ADDREGNAMES_ARR_INDEX_2 ((index)), ADDREGNAMES_ARR_INDEX_2 ((index)+2) 615 #define ADDREGNAMES_ARR_INDEX_8(index) \ 616 ADDREGNAMES_ARR_INDEX_4 ((index)), ADDREGNAMES_ARR_INDEX_4 ((index)+4) 617 #define ADDREGNAMES_ARR_INDEX_16(index) \ 618 ADDREGNAMES_ARR_INDEX_8 ((index)), ADDREGNAMES_ARR_INDEX_8 ((index)+8) 619 #define ADDREGNAMES_ARR_INDEX_32(index) \ 620 ADDREGNAMES_ARR_INDEX_16 ((index)), ADDREGNAMES_ARR_INDEX_16 ((index)+16) 621 622 #define ADDITIONAL_REGISTER_NAMES \ 623 { \ 624 ADDREGNAMES_ARR_INDEX_32 (0) \ 625 } 626 627 /* Number of actual hardware registers. 628 The hardware registers are assigned numbers for the compiler 629 from 0 to just below FIRST_PSEUDO_REGISTER. 630 All registers that the compiler knows about must be given numbers, 631 even those that are not normally considered general registers. */ 632 633 /* There are many other relevant definitions in sh.md's md_constants. */ 634 635 #define FIRST_GENERAL_REG R0_REG 636 #define LAST_GENERAL_REG (FIRST_GENERAL_REG + (15)) 637 #define FIRST_FP_REG DR0_REG 638 #define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)) 639 #define FIRST_XD_REG XD0_REG 640 #define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1)) 641 642 /* Registers that can be accessed through bank0 or bank1 depending on sr.md. */ 643 #define FIRST_BANKED_REG R0_REG 644 #define LAST_BANKED_REG R7_REG 645 646 #define BANKED_REGISTER_P(REGNO) \ 647 IN_RANGE ((REGNO), \ 648 (unsigned HOST_WIDE_INT) FIRST_BANKED_REG, \ 649 (unsigned HOST_WIDE_INT) LAST_BANKED_REG) 650 651 #define GENERAL_REGISTER_P(REGNO) \ 652 IN_RANGE ((REGNO), \ 653 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ 654 (unsigned HOST_WIDE_INT) LAST_GENERAL_REG) 655 656 #define GENERAL_OR_AP_REGISTER_P(REGNO) \ 657 (GENERAL_REGISTER_P (REGNO) || ((REGNO) == AP_REG) \ 658 || ((REGNO) == FRAME_POINTER_REGNUM)) 659 660 #define FP_REGISTER_P(REGNO) \ 661 ((int) (REGNO) >= FIRST_FP_REG && (int) (REGNO) <= LAST_FP_REG) 662 663 #define XD_REGISTER_P(REGNO) \ 664 ((int) (REGNO) >= FIRST_XD_REG && (int) (REGNO) <= LAST_XD_REG) 665 666 #define FP_OR_XD_REGISTER_P(REGNO) \ 667 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO)) 668 669 #define FP_ANY_REGISTER_P(REGNO) \ 670 (FP_REGISTER_P (REGNO) || XD_REGISTER_P (REGNO) || (REGNO) == FPUL_REG) 671 672 #define SPECIAL_REGISTER_P(REGNO) \ 673 ((REGNO) == GBR_REG || (REGNO) == T_REG \ 674 || (REGNO) == MACH_REG || (REGNO) == MACL_REG \ 675 || (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG) 676 677 #define VALID_REGISTER_P(REGNO) \ 678 (GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \ 679 || XD_REGISTER_P (REGNO) \ 680 || (REGNO) == AP_REG || (REGNO) == RAP_REG \ 681 || (REGNO) == FRAME_POINTER_REGNUM \ 682 || ((SPECIAL_REGISTER_P (REGNO) || (REGNO) == PR_REG)) \ 683 || (TARGET_SH2E && (REGNO) == FPUL_REG)) 684 685 /* The mode that should be generally used to store a register by 686 itself in the stack, or to load it back. */ 687 #define REGISTER_NATURAL_MODE(REGNO) \ 688 (FP_REGISTER_P (REGNO) ? E_SFmode \ 689 : XD_REGISTER_P (REGNO) ? E_DFmode : E_SImode) 690 691 692 #define FIRST_PSEUDO_REGISTER 156 693 694 /* Don't count soft frame pointer. */ 695 #define DWARF_FRAME_REGISTERS (153) 696 697 /* 1 for registers that have pervasive standard uses 698 and are not available for the register allocator. 699 700 Mach register is fixed 'cause it's only 10 bits wide for SH1. 701 It is 32 bits wide for SH2. */ 702 #define FIXED_REGISTERS \ 703 { \ 704 /* Regular registers. */ \ 705 0, 0, 0, 0, 0, 0, 0, 0, \ 706 0, 0, 0, 0, 0, 0, 0, 1, \ 707 /* r16 is reserved, r18 is the former pr. */ \ 708 1, 0, 0, 0, 0, 0, 0, 0, \ 709 /* r24 is reserved for the OS; r25, for the assembler or linker. */ \ 710 /* r26 is a global variable data pointer; r27 is for constants. */ \ 711 1, 1, 1, 1, 0, 0, 0, 0, \ 712 0, 0, 0, 0, 0, 0, 0, 0, \ 713 0, 0, 0, 0, 0, 0, 0, 0, \ 714 0, 0, 0, 0, 0, 0, 0, 0, \ 715 0, 0, 0, 0, 0, 0, 0, 1, \ 716 /* FP registers. */ \ 717 0, 0, 0, 0, 0, 0, 0, 0, \ 718 0, 0, 0, 0, 0, 0, 0, 0, \ 719 0, 0, 0, 0, 0, 0, 0, 0, \ 720 0, 0, 0, 0, 0, 0, 0, 0, \ 721 0, 0, 0, 0, 0, 0, 0, 0, \ 722 0, 0, 0, 0, 0, 0, 0, 0, \ 723 0, 0, 0, 0, 0, 0, 0, 0, \ 724 0, 0, 0, 0, 0, 0, 0, 0, \ 725 /* Branch target registers. */ \ 726 0, 0, 0, 0, 0, 0, 0, 0, \ 727 /* XD registers. */ \ 728 0, 0, 0, 0, 0, 0, 0, 0, \ 729 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 730 1, 1, 1, 1, 1, 1, 0, 1, \ 731 /*"rap", "sfp","fpscr0","fpscr1" */ \ 732 1, 1, 1, 1, \ 733 } 734 735 /* 1 for registers not available across function calls. 736 These must include the FIXED_REGISTERS and also any 737 registers that can be used without being saved. 738 The latter must include the registers where values are returned 739 and the register where structure-value addresses are passed. 740 Aside from that, you can include as many other registers as you like. */ 741 #define CALL_USED_REGISTERS \ 742 { \ 743 /* Regular registers. */ \ 744 1, 1, 1, 1, 1, 1, 1, 1, \ 745 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ 746 Only the lower 32bits of R10-R14 are guaranteed to be preserved \ 747 across SH5 function calls. */ \ 748 0, 0, 0, 0, 0, 0, 0, 1, \ 749 1, 1, 1, 1, 1, 1, 1, 1, \ 750 1, 1, 1, 1, 0, 0, 0, 0, \ 751 0, 0, 0, 0, 1, 1, 1, 1, \ 752 1, 1, 1, 1, 0, 0, 0, 0, \ 753 0, 0, 0, 0, 0, 0, 0, 0, \ 754 0, 0, 0, 0, 1, 1, 1, 1, \ 755 /* FP registers. */ \ 756 1, 1, 1, 1, 1, 1, 1, 1, \ 757 1, 1, 1, 1, 0, 0, 0, 0, \ 758 1, 1, 1, 1, 1, 1, 1, 1, \ 759 1, 1, 1, 1, 1, 1, 1, 1, \ 760 1, 1, 1, 1, 0, 0, 0, 0, \ 761 0, 0, 0, 0, 0, 0, 0, 0, \ 762 0, 0, 0, 0, 0, 0, 0, 0, \ 763 0, 0, 0, 0, 0, 0, 0, 0, \ 764 /* Branch target registers. */ \ 765 1, 1, 1, 1, 1, 0, 0, 0, \ 766 /* XD registers. */ \ 767 1, 1, 1, 1, 1, 1, 0, 0, \ 768 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 769 1, 1, 1, 1, 1, 1, 1, 1, \ 770 /*"rap", "sfp","fpscr0","fpscr1" */ \ 771 1, 1, 1, 1, \ 772 } 773 774 /* CALL_REALLY_USED_REGISTERS is used as a default setting, which is then 775 overridden by -fcall-saved-* and -fcall-used-* options and then by 776 TARGET_CONDITIONAL_REGISTER_USAGE. There we might want to make a 777 register call-used, yet fixed, like PIC_OFFSET_TABLE_REGNUM. */ 778 #define CALL_REALLY_USED_REGISTERS \ 779 { \ 780 /* Regular registers. */ \ 781 1, 1, 1, 1, 1, 1, 1, 1, \ 782 /* R8 and R9 are call-clobbered on SH5, but not on earlier SH ABIs. \ 783 Only the lower 32bits of R10-R14 are guaranteed to be preserved \ 784 across SH5 function calls. */ \ 785 0, 0, 0, 0, 0, 0, 0, 1, \ 786 1, 1, 1, 1, 1, 1, 1, 1, \ 787 1, 1, 1, 1, 0, 0, 0, 0, \ 788 0, 0, 0, 0, 1, 1, 1, 1, \ 789 1, 1, 1, 1, 0, 0, 0, 0, \ 790 0, 0, 0, 0, 0, 0, 0, 0, \ 791 0, 0, 0, 0, 1, 1, 1, 1, \ 792 /* FP registers. */ \ 793 1, 1, 1, 1, 1, 1, 1, 1, \ 794 1, 1, 1, 1, 0, 0, 0, 0, \ 795 1, 1, 1, 1, 1, 1, 1, 1, \ 796 1, 1, 1, 1, 1, 1, 1, 1, \ 797 1, 1, 1, 1, 0, 0, 0, 0, \ 798 0, 0, 0, 0, 0, 0, 0, 0, \ 799 0, 0, 0, 0, 0, 0, 0, 0, \ 800 0, 0, 0, 0, 0, 0, 0, 0, \ 801 /* Branch target registers. */ \ 802 1, 1, 1, 1, 1, 0, 0, 0, \ 803 /* XD registers. */ \ 804 1, 1, 1, 1, 1, 1, 0, 0, \ 805 /*"gbr", "ap", "pr", "t", "mach", "macl", "fpul", "fpscr", */ \ 806 0, 1, 1, 1, 1, 1, 1, 1, \ 807 /*"rap", "sfp","fpscr0","fpscr1" */ \ 808 1, 1, 0, 0, \ 809 } 810 811 /* Specify the modes required to caller save a given hard regno. */ 812 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 813 sh_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 814 815 /* A C expression that is nonzero if hard register NEW_REG can be 816 considered for use as a rename register for OLD_REG register */ 817 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 818 sh_hard_regno_rename_ok (OLD_REG, NEW_REG) 819 820 /* Specify the registers used for certain standard purposes. 821 The values of these macros are register numbers. */ 822 823 /* Define this if the program counter is overloaded on a register. */ 824 /* #define PC_REGNUM 15*/ 825 826 /* Register to use for pushing function arguments. */ 827 #define STACK_POINTER_REGNUM SP_REG 828 829 /* Base register for access to local variables of the function. */ 830 #define HARD_FRAME_POINTER_REGNUM FP_REG 831 832 /* Base register for access to local variables of the function. */ 833 #define FRAME_POINTER_REGNUM 153 834 835 /* Fake register that holds the address on the stack of the 836 current function's return address. */ 837 #define RETURN_ADDRESS_POINTER_REGNUM RAP_REG 838 839 /* Register to hold the addressing base for position independent 840 code access to data items. */ 841 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? PIC_REG : INVALID_REGNUM) 842 843 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT 844 entries would need to handle saving and restoring it). */ 845 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC 846 847 #define GOT_SYMBOL_NAME "*_GLOBAL_OFFSET_TABLE_" 848 849 /* Definitions for register eliminations. 850 851 We have three registers that can be eliminated on the SH. First, the 852 frame pointer register can often be eliminated in favor of the stack 853 pointer register. Secondly, the argument pointer register can always be 854 eliminated; it is replaced with either the stack or frame pointer. 855 Third, there is the return address pointer, which can also be replaced 856 with either the stack or the frame pointer. 857 858 This is an array of structures. Each structure initializes one pair 859 of eliminable registers. The "from" register number is given first, 860 followed by "to". Eliminations of the same "from" register are listed 861 in order of preference. 862 863 If you add any registers here that are not actually hard registers, 864 and that have any alternative of elimination that doesn't always 865 apply, you need to amend calc_live_regs to exclude it, because 866 reload spills all eliminable registers where it sees an 867 can_eliminate == 0 entry, thus making them 'live' . 868 If you add any hard registers that can be eliminated in different 869 ways, you have to patch reload to spill them only when all alternatives 870 of elimination fail. */ 871 #define ELIMINABLE_REGS \ 872 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 873 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 874 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 875 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 876 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 877 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 878 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM},} 879 880 /* Define the offset between two registers, one to be eliminated, and the other 881 its replacement, at the start of a routine. */ 882 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 883 OFFSET = initial_elimination_offset ((FROM), (TO)) 884 885 /* Base register for access to arguments of the function. */ 886 #define ARG_POINTER_REGNUM AP_REG 887 888 /* Register in which the static-chain is passed to a function. */ 889 #define STATIC_CHAIN_REGNUM (3) 890 891 /* Don't default to pcc-struct-return, because we have already specified 892 exactly how to return structures in the TARGET_RETURN_IN_MEMORY 893 target hook. */ 894 #define DEFAULT_PCC_STRUCT_RETURN 0 895 896 897 /* Define the classes of registers for register constraints in the 898 machine description. Also define ranges of constants. 899 900 One of the classes must always be named ALL_REGS and include all hard regs. 901 If there is more than one class, another class must be named NO_REGS 902 and contain no registers. 903 904 The name GENERAL_REGS must be the name of a class (or an alias for 905 another name such as ALL_REGS). This is the class of registers 906 that is allowed by "g" or "r" in a register constraint. 907 Also, registers outside this class are allocated only when 908 instructions express preferences for them. 909 910 The classes must be numbered in nondecreasing order; that is, 911 a larger-numbered class must never be contained completely 912 in a smaller-numbered class. 913 914 For any two classes, it is very desirable that there be another 915 class that represents their union. 916 917 The SH has two sorts of general registers, R0 and the rest. R0 can 918 be used as the destination of some of the arithmetic ops. There are 919 also some special purpose registers; the T bit register, the 920 Procedure Return Register and the Multiply Accumulate Registers. 921 922 Place GENERAL_REGS after FPUL_REGS so that it will be preferred by 923 reg_class_subunion. We don't want to have an actual union class 924 of these, because it would only be used when both classes are calculated 925 to give the same cost, but there is only one FPUL register. 926 Besides, regclass fails to notice the different REGISTER_MOVE_COSTS 927 applying to the actual instruction alternative considered. E.g., the 928 y/r alternative of movsi_ie is considered to have no more cost that 929 the r/r alternative, which is patently untrue. */ 930 enum reg_class 931 { 932 NO_REGS, 933 R0_REGS, 934 PR_REGS, 935 T_REGS, 936 MAC_REGS, 937 FPUL_REGS, 938 SIBCALL_REGS, 939 NON_SP_REGS, 940 GENERAL_REGS, 941 FP0_REGS, 942 FP_REGS, 943 DF_REGS, 944 FPSCR_REGS, 945 GENERAL_FP_REGS, 946 GENERAL_DF_REGS, 947 TARGET_REGS, 948 ALL_REGS, 949 LIM_REG_CLASSES 950 }; 951 952 #define N_REG_CLASSES (int) LIM_REG_CLASSES 953 954 /* Give names of register classes as strings for dump file. */ 955 #define REG_CLASS_NAMES \ 956 { \ 957 "NO_REGS", \ 958 "R0_REGS", \ 959 "PR_REGS", \ 960 "T_REGS", \ 961 "MAC_REGS", \ 962 "FPUL_REGS", \ 963 "SIBCALL_REGS", \ 964 "NON_SP_REGS", \ 965 "GENERAL_REGS", \ 966 "FP0_REGS", \ 967 "FP_REGS", \ 968 "DF_REGS", \ 969 "FPSCR_REGS", \ 970 "GENERAL_FP_REGS", \ 971 "GENERAL_DF_REGS", \ 972 "TARGET_REGS", \ 973 "ALL_REGS", \ 974 } 975 976 /* Define which registers fit in which classes. 977 This is an initializer for a vector of HARD_REG_SET 978 of length N_REG_CLASSES. */ 979 #define REG_CLASS_CONTENTS \ 980 { \ 981 /* NO_REGS: */ \ 982 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 983 /* R0_REGS: */ \ 984 { 0x00000001, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 985 /* PR_REGS: */ \ 986 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00040000 }, \ 987 /* T_REGS: */ \ 988 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00080000 }, \ 989 /* MAC_REGS: */ \ 990 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00300000 }, \ 991 /* FPUL_REGS: */ \ 992 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00400000 }, \ 993 /* SIBCALL_REGS: Initialized in TARGET_CONDITIONAL_REGISTER_USAGE. */ \ 994 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, \ 995 /* NON_SP_REGS: */ \ 996 { 0xffff7fff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ 997 /* GENERAL_REGS: */ \ 998 { 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x03020000 }, \ 999 /* FP0_REGS: */ \ 1000 { 0x00000000, 0x00000000, 0x00000001, 0x00000000, 0x00000000 }, \ 1001 /* FP_REGS: */ \ 1002 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ 1003 /* DF_REGS: */ \ 1004 { 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x0000ff00 }, \ 1005 /* FPSCR_REGS: */ \ 1006 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00800000 }, \ 1007 /* GENERAL_FP_REGS: */ \ 1008 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x03020000 }, \ 1009 /* GENERAL_DF_REGS: */ \ 1010 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0302ff00 }, \ 1011 /* TARGET_REGS: */ \ 1012 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x000000ff }, \ 1013 /* ALL_REGS: */ \ 1014 { 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0fffffff }, \ 1015 } 1016 1017 /* The same information, inverted: 1018 Return the class number of the smallest class containing 1019 reg number REGNO. This could be a conditional expression 1020 or could index an array. */ 1021 extern enum reg_class regno_reg_class[FIRST_PSEUDO_REGISTER]; 1022 #define REGNO_REG_CLASS(REGNO) regno_reg_class[(REGNO)] 1023 1024 /* When this hook returns true for MODE, the compiler allows 1025 registers explicitly used in the rtl to be used as spill registers 1026 but prevents the compiler from extending the lifetime of these 1027 registers. */ 1028 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1029 sh_small_register_classes_for_mode_p 1030 1031 /* The order in which register should be allocated. */ 1032 /* Sometimes FP0_REGS becomes the preferred class of a floating point pseudo, 1033 and GENERAL_FP_REGS the alternate class. Since FP0 is likely to be 1034 spilled or used otherwise, we better have the FP_REGS allocated first. */ 1035 #define REG_ALLOC_ORDER \ 1036 {/* Caller-saved FPRs */ \ 1037 65, 66, 67, 68, 69, 70, 71, 64, \ 1038 72, 73, 74, 75, 80, 81, 82, 83, \ 1039 84, 85, 86, 87, 88, 89, 90, 91, \ 1040 92, 93, 94, 95, 96, 97, 98, 99, \ 1041 /* Callee-saved FPRs */ \ 1042 76, 77, 78, 79,100,101,102,103, \ 1043 104,105,106,107,108,109,110,111, \ 1044 112,113,114,115,116,117,118,119, \ 1045 120,121,122,123,124,125,126,127, \ 1046 136,137,138,139,140,141,142,143, \ 1047 /* FPSCR */ 151, \ 1048 /* Caller-saved GPRs (except 8/9 on SH1-4) */ \ 1049 1, 2, 3, 7, 6, 5, 4, 0, \ 1050 8, 9, 17, 19, 20, 21, 22, 23, \ 1051 36, 37, 38, 39, 40, 41, 42, 43, \ 1052 60, 61, 62, \ 1053 /* SH1-4 callee-saved saved GPRs / SH5 partially-saved GPRs */ \ 1054 10, 11, 12, 13, 14, 18, \ 1055 /* SH5 callee-saved GPRs */ \ 1056 28, 29, 30, 31, 32, 33, 34, 35, \ 1057 44, 45, 46, 47, 48, 49, 50, 51, \ 1058 52, 53, 54, 55, 56, 57, 58, 59, \ 1059 /* FPUL */ 150, \ 1060 /* Fixed registers */ \ 1061 15, 16, 24, 25, 26, 27, 63,144, \ 1062 145,146,147,148,149,152,153,154,155 } 1063 1064 /* The class value for index registers, and the one for base regs. */ 1065 #define INDEX_REG_CLASS R0_REGS 1066 #define BASE_REG_CLASS GENERAL_REGS 1067 1068 /* Defines for sh.md and constraints.md. */ 1069 1070 #define CONST_OK_FOR_I08(VALUE) (((HOST_WIDE_INT)(VALUE))>= -128 \ 1071 && ((HOST_WIDE_INT)(VALUE)) <= 127) 1072 1073 #define CONST_OK_FOR_K08(VALUE) (((HOST_WIDE_INT)(VALUE))>= 0 \ 1074 && ((HOST_WIDE_INT)(VALUE)) <= 255) 1075 1076 #define ZERO_EXTRACT_ANDMASK(EXTRACT_SZ_RTX, EXTRACT_POS_RTX)\ 1077 (((1 << INTVAL (EXTRACT_SZ_RTX)) - 1) << INTVAL (EXTRACT_POS_RTX)) 1078 1079 /* Return the maximum number of consecutive registers 1080 needed to represent mode MODE in a register of class CLASS. 1081 1082 If TARGET_SHMEDIA, we need two FP registers per word. 1083 Otherwise we will need at most one register per word. */ 1084 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1085 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1086 1087 /* Stack layout; function entry, exit and calling. */ 1088 1089 /* Define the number of registers that can hold parameters. 1090 These macros are used only in other macro definitions below. */ 1091 #define NPARM_REGS(MODE) \ 1092 (TARGET_FPU_ANY && (MODE) == SFmode \ 1093 ? 8 \ 1094 : TARGET_FPU_DOUBLE \ 1095 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1096 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 1097 ? 8 \ 1098 : 4) 1099 1100 #define FIRST_PARM_REG (FIRST_GENERAL_REG + 4) 1101 #define FIRST_RET_REG (FIRST_GENERAL_REG + 0) 1102 1103 #define FIRST_FP_PARM_REG (FIRST_FP_REG + 4) 1104 #define FIRST_FP_RET_REG FIRST_FP_REG 1105 1106 /* Define this if pushing a word on the stack 1107 makes the stack pointer a smaller address. */ 1108 #define STACK_GROWS_DOWNWARD 1 1109 1110 /* Define this macro to nonzero if the addresses of local variable slots 1111 are at negative offsets from the frame pointer. */ 1112 #define FRAME_GROWS_DOWNWARD 1 1113 1114 /* If we generate an insn to push BYTES bytes, 1115 this says how many the stack pointer really advances by. */ 1116 /* Don't define PUSH_ROUNDING, since the hardware doesn't do this. 1117 When PUSH_ROUNDING is not defined, PARM_BOUNDARY will cause gcc to 1118 do correct alignment. */ 1119 #if 0 1120 #define PUSH_ROUNDING(NPUSHED) (((NPUSHED) + 3) & ~3) 1121 #endif 1122 1123 /* Offset of first parameter from the argument pointer register value. */ 1124 #define FIRST_PARM_OFFSET(FNDECL) 0 1125 1126 /* Value is the number of bytes of arguments automatically popped when 1127 calling a subroutine. 1128 CUM is the accumulated argument list. */ 1129 #define CALL_POPS_ARGS(CUM) (0) 1130 1131 /* Some subroutine macros specific to this machine. */ 1132 1133 #define BASE_RETURN_VALUE_REG(MODE) \ 1134 ((TARGET_FPU_ANY && ((MODE) == SFmode)) \ 1135 ? FIRST_FP_RET_REG \ 1136 : TARGET_FPU_ANY && (MODE) == SCmode \ 1137 ? FIRST_FP_RET_REG \ 1138 : (TARGET_FPU_DOUBLE \ 1139 && ((MODE) == DFmode || (MODE) == SFmode \ 1140 || (MODE) == DCmode || (MODE) == SCmode )) \ 1141 ? FIRST_FP_RET_REG \ 1142 : FIRST_RET_REG) 1143 1144 #define BASE_ARG_REG(MODE) \ 1145 ((TARGET_SH2E && ((MODE) == SFmode)) \ 1146 ? FIRST_FP_PARM_REG \ 1147 : TARGET_FPU_DOUBLE \ 1148 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1149 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)\ 1150 ? FIRST_FP_PARM_REG \ 1151 : FIRST_PARM_REG) 1152 1153 /* 1 if N is a possible register number for function argument passing. */ 1154 /* ??? There are some callers that pass REGNO as int, and others that pass 1155 it as unsigned. We get warnings unless we do casts everywhere. */ 1156 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1157 (((unsigned) (REGNO) >= (unsigned) FIRST_PARM_REG \ 1158 && (unsigned) (REGNO) < (unsigned) (FIRST_PARM_REG + NPARM_REGS (SImode)))\ 1159 || (TARGET_FPU_ANY \ 1160 && (unsigned) (REGNO) >= (unsigned) FIRST_FP_PARM_REG \ 1161 && (unsigned) (REGNO) < (unsigned) (FIRST_FP_PARM_REG \ 1162 + NPARM_REGS (SFmode)))) 1163 1164 #ifdef __cplusplus 1165 1166 /* Define a data type for recording info about an argument list 1167 during the scan of that argument list. This data type should 1168 hold all necessary information about the function itself 1169 and about the args processed so far, enough to enable macros 1170 such as FUNCTION_ARG to determine where the next arg should go. 1171 1172 On SH, this is a single integer, which is a number of words 1173 of arguments scanned so far (including the invisible argument, 1174 if any, which holds the structure-value-address). 1175 Thus NARGREGS or more means all following args should go on the stack. */ 1176 1177 enum sh_arg_class { SH_ARG_INT = 0, SH_ARG_FLOAT = 1 }; 1178 1179 struct sh_args 1180 { 1181 /* How many SH_ARG_INT and how many SH_ARG_FLOAT args there are. */ 1182 int arg_count[2]; 1183 1184 bool force_mem; 1185 1186 /* Nonzero if a prototype is available for the function. */ 1187 bool prototype_p; 1188 1189 /* The number of an odd floating-point register, that should be used 1190 for the next argument of type float. */ 1191 int free_single_fp_reg; 1192 1193 /* Whether we're processing an outgoing function call. */ 1194 bool outgoing; 1195 1196 /* This is set to nonzero when the call in question must use the Renesas ABI, 1197 even without the -mrenesas option. */ 1198 bool renesas_abi; 1199 }; 1200 1201 typedef sh_args CUMULATIVE_ARGS; 1202 1203 /* Set when processing a function with interrupt attribute. */ 1204 extern bool current_function_interrupt; 1205 1206 #endif // __cplusplus 1207 1208 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1209 for a call to a function whose data type is FNTYPE. 1210 For a library call, FNTYPE is 0. 1211 1212 On SH, the offset always starts at 0: the first parm reg is always 1213 the same reg for a given argument class. 1214 1215 For TARGET_HITACHI, the structure value pointer is passed in memory. */ 1216 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1217 sh_init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL),\ 1218 (N_NAMED_ARGS), VOIDmode) 1219 1220 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1221 sh_init_cumulative_args (& (CUM), NULL_TREE, (LIBNAME), NULL_TREE, 0, (MODE)) 1222 1223 /* By accident we got stuck with passing SCmode on SH4 little endian 1224 in two registers that are nominally successive - which is different from 1225 two single SFmode values, where we take endianness translation into 1226 account. That does not work at all if an odd number of registers is 1227 already in use, so that got fixed, but library functions are still more 1228 likely to use complex numbers without mixing them with SFmode arguments 1229 (which in C would have to be structures), so for the sake of ABI 1230 compatibility the way SCmode values are passed when an even number of 1231 FP registers is in use remains different from a pair of SFmode values for 1232 now. 1233 I.e.: 1234 foo (double); a: fr5,fr4 1235 foo (float a, float b); a: fr5 b: fr4 1236 foo (__complex float a); a.real fr4 a.imag: fr5 - for consistency, 1237 this should be the other way round... 1238 foo (float a, __complex float b); a: fr5 b.real: fr4 b.imag: fr7 */ 1239 #define FUNCTION_ARG_SCmode_WART 1 1240 1241 /* Minimum alignment for an argument to be passed by callee-copy 1242 reference. We need such arguments to be aligned to 8 byte 1243 boundaries, because they'll be loaded using quad loads. */ 1244 #define SH_MIN_ALIGN_FOR_CALLEE_COPY (8 * BITS_PER_UNIT) 1245 1246 /* Perform any needed actions needed for a function that is receiving a 1247 variable number of arguments. */ 1248 1249 /* Call the function profiler with a given profile label. 1250 We use two .aligns, so as to make sure that both the .long is aligned 1251 on a 4 byte boundary, and that the .long is a fixed distance (2 bytes) 1252 from the trapa instruction. */ 1253 #define FUNCTION_PROFILER(STREAM,LABELNO) \ 1254 { \ 1255 fprintf((STREAM), "\t.align\t2\n"); \ 1256 fprintf((STREAM), "\ttrapa\t#33\n"); \ 1257 fprintf((STREAM), "\t.align\t2\n"); \ 1258 asm_fprintf((STREAM), "\t.long\t%LLP%d\n", (LABELNO)); \ 1259 } 1260 1261 /* Define this macro if the code for function profiling should come 1262 before the function prologue. Normally, the profiling code comes 1263 after. */ 1264 #define PROFILE_BEFORE_PROLOGUE 1265 1266 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1267 the stack pointer does not matter. The value is tested only in 1268 functions that have frame pointers. 1269 No definition is equivalent to always zero. */ 1270 #define EXIT_IGNORE_STACK 1 1271 1272 /* 1273 On the SH, the trampoline looks like 1274 2 0002 D202 mov.l l2,r2 1275 1 0000 D301 mov.l l1,r3 1276 3 0004 422B jmp @r2 1277 4 0006 0009 nop 1278 5 0008 00000000 l1: .long area 1279 6 000c 00000000 l2: .long function */ 1280 1281 /* Length in units of the trampoline for entering a nested function. */ 1282 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : 16) 1283 1284 /* Alignment required for a trampoline in bits. */ 1285 #define TRAMPOLINE_ALIGNMENT \ 1286 ((CACHE_LOG < 3 \ 1287 || (optimize_size && ! (TARGET_HARD_SH4))) ? 32 \ 1288 : 64) 1289 1290 /* A C expression whose value is RTL representing the value of the return 1291 address for the frame COUNT steps up from the current frame. 1292 FRAMEADDR is already the frame pointer of the COUNT frame, so we 1293 can ignore COUNT. */ 1294 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1295 (((COUNT) == 0) ? sh_get_pr_initial_val () : NULL_RTX) 1296 1297 /* A C expression whose value is RTL representing the location of the 1298 incoming return address at the beginning of any function, before the 1299 prologue. This RTL is either a REG, indicating that the return 1300 value is saved in REG, or a MEM representing a location in 1301 the stack. */ 1302 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, PR_REG) 1303 1304 /* Addressing modes, and classification of registers for them. */ 1305 #define HAVE_POST_INCREMENT TARGET_SH1 1306 #define HAVE_PRE_DECREMENT TARGET_SH1 1307 1308 #define USE_LOAD_POST_INCREMENT(mode) TARGET_SH1 1309 #define USE_LOAD_PRE_DECREMENT(mode) TARGET_SH2A 1310 #define USE_STORE_POST_INCREMENT(mode) TARGET_SH2A 1311 #define USE_STORE_PRE_DECREMENT(mode) TARGET_SH1 1312 1313 /* If a memory clear move would take CLEAR_RATIO or more simple 1314 move-instruction pairs, we will do a setmem instead. */ 1315 1316 #define CLEAR_RATIO(speed) ((speed) ? 15 : 3) 1317 1318 /* Macros to check register numbers against specific register classes. */ 1319 1320 /* These assume that REGNO is a hard or pseudo reg number. 1321 They give nonzero only if REGNO is a hard reg of the suitable class 1322 or a pseudo reg currently allocated to a suitable hard reg. 1323 Since they use reg_renumber, they are safe only once reg_renumber 1324 has been allocated, which happens in reginfo.c during register 1325 allocation. */ 1326 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1327 (GENERAL_OR_AP_REGISTER_P (REGNO) \ 1328 || GENERAL_OR_AP_REGISTER_P (reg_renumber[(REGNO)])) 1329 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1330 ((REGNO) == R0_REG || (unsigned) reg_renumber[(REGNO)] == R0_REG) 1331 1332 /* True if SYMBOL + OFFSET constants must refer to something within 1333 SYMBOL's section. */ 1334 #define SH_OFFSETS_MUST_BE_WITHIN_SECTIONS_P TARGET_FDPIC 1335 1336 /* Maximum number of registers that can appear in a valid memory 1337 address. */ 1338 #define MAX_REGS_PER_ADDRESS 2 1339 1340 /* Recognize any constant value that is a valid address. */ 1341 #define CONSTANT_ADDRESS_P(X) (GET_CODE (X) == LABEL_REF) 1342 1343 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1344 and check its validity for a certain class. 1345 The suitable hard regs are always accepted and all pseudo regs 1346 are also accepted if STRICT is not set. */ 1347 1348 /* Nonzero if X is a reg that can be used as a base reg. */ 1349 #define REG_OK_FOR_BASE_P(X, STRICT) \ 1350 (GENERAL_OR_AP_REGISTER_P (REGNO (X)) \ 1351 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1352 1353 /* Nonzero if X is a reg that can be used as an index. */ 1354 #define REG_OK_FOR_INDEX_P(X, STRICT) \ 1355 ((REGNO (X) == R0_REG) \ 1356 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1357 1358 /* Nonzero if X/OFFSET is a reg that can be used as an index. */ 1359 #define SUBREG_OK_FOR_INDEX_P(X, OFFSET, STRICT) \ 1360 ((REGNO (X) == R0_REG && OFFSET == 0) \ 1361 || (!STRICT && REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1362 1363 /* Macros for extra constraints. */ 1364 1365 #define IS_PC_RELATIVE_LOAD_ADDR_P(OP) \ 1366 ((GET_CODE ((OP)) == LABEL_REF) \ 1367 || (GET_CODE ((OP)) == CONST \ 1368 && GET_CODE (XEXP ((OP), 0)) == PLUS \ 1369 && GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF \ 1370 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) 1371 1372 #define IS_NON_EXPLICIT_CONSTANT_P(OP) \ 1373 (CONSTANT_P (OP) \ 1374 && !CONST_INT_P (OP) \ 1375 && GET_CODE (OP) != CONST_DOUBLE \ 1376 && (!flag_pic \ 1377 || (LEGITIMATE_PIC_OPERAND_P (OP) \ 1378 && !PIC_ADDR_P (OP) \ 1379 && GET_CODE (OP) != LABEL_REF))) 1380 1381 #define GOT_ENTRY_P(OP) \ 1382 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1383 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOT) 1384 1385 #define GOTPLT_ENTRY_P(OP) \ 1386 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1387 && XINT (XEXP ((OP), 0), 1) == UNSPEC_GOTPLT) 1388 1389 #define UNSPEC_GOTOFF_P(OP) \ 1390 (GET_CODE (OP) == UNSPEC && XINT ((OP), 1) == UNSPEC_GOTOFF) 1391 1392 #define GOTOFF_P(OP) \ 1393 (GET_CODE (OP) == CONST \ 1394 && (UNSPEC_GOTOFF_P (XEXP ((OP), 0)) \ 1395 || (GET_CODE (XEXP ((OP), 0)) == PLUS \ 1396 && UNSPEC_GOTOFF_P (XEXP (XEXP ((OP), 0), 0)) \ 1397 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1))))) 1398 1399 #define PIC_ADDR_P(OP) \ 1400 (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1401 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PIC) 1402 1403 #define PCREL_SYMOFF_P(OP) \ 1404 (GET_CODE (OP) == CONST \ 1405 && GET_CODE (XEXP ((OP), 0)) == UNSPEC \ 1406 && XINT (XEXP ((OP), 0), 1) == UNSPEC_PCREL_SYMOFF) 1407 1408 #define NON_PIC_REFERENCE_P(OP) \ 1409 (GET_CODE (OP) == LABEL_REF || GET_CODE (OP) == SYMBOL_REF \ 1410 || (GET_CODE (OP) == CONST \ 1411 && (GET_CODE (XEXP ((OP), 0)) == LABEL_REF \ 1412 || GET_CODE (XEXP ((OP), 0)) == SYMBOL_REF)) \ 1413 || (GET_CODE (OP) == CONST && GET_CODE (XEXP ((OP), 0)) == PLUS \ 1414 && (GET_CODE (XEXP (XEXP ((OP), 0), 0)) == SYMBOL_REF \ 1415 || GET_CODE (XEXP (XEXP ((OP), 0), 0)) == LABEL_REF) \ 1416 && CONST_INT_P (XEXP (XEXP ((OP), 0), 1)))) 1417 1418 #define PIC_REFERENCE_P(OP) \ 1419 (GOT_ENTRY_P (OP) || GOTPLT_ENTRY_P (OP) \ 1420 || GOTOFF_P (OP) || PIC_ADDR_P (OP)) 1421 1422 #define MAYBE_BASE_REGISTER_RTX_P(X, STRICT) \ 1423 ((REG_P (X) && REG_OK_FOR_BASE_P (X, STRICT)) \ 1424 || (GET_CODE (X) == SUBREG \ 1425 && REG_P (SUBREG_REG (X)) \ 1426 && REG_OK_FOR_BASE_P (SUBREG_REG (X), STRICT))) 1427 1428 /* Since this must be r0, which is a single register class, we must check 1429 SUBREGs more carefully, to be sure that we don't accept one that extends 1430 outside the class. */ 1431 #define MAYBE_INDEX_REGISTER_RTX_P(X, STRICT) \ 1432 ((REG_P (X) && REG_OK_FOR_INDEX_P (X, STRICT)) \ 1433 || (GET_CODE (X) == SUBREG \ 1434 && REG_P (SUBREG_REG (X)) \ 1435 && SUBREG_OK_FOR_INDEX_P (SUBREG_REG (X), SUBREG_BYTE (X), STRICT))) 1436 1437 #ifdef REG_OK_STRICT 1438 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, true) 1439 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, true) 1440 #else 1441 #define BASE_REGISTER_RTX_P(X) MAYBE_BASE_REGISTER_RTX_P(X, false) 1442 #define INDEX_REGISTER_RTX_P(X) MAYBE_INDEX_REGISTER_RTX_P(X, false) 1443 #endif 1444 1445 1446 /* A C compound statement that attempts to replace X, which is an address 1447 that needs reloading, with a valid memory address for an operand of 1448 mode MODE. WIN is a C statement label elsewhere in the code. */ 1449 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1450 do { \ 1451 if (sh_legitimize_reload_address (&(X), (MODE), (OPNUM), (TYPE))) \ 1452 goto WIN; \ 1453 } while (0) 1454 1455 /* Specify the machine mode that this machine uses 1456 for the index in the tablejump instruction. */ 1457 #define CASE_VECTOR_MODE ((! optimize || TARGET_BIGTABLE) ? SImode : HImode) 1458 1459 #define CASE_VECTOR_SHORTEN_MODE(MIN_OFFSET, MAX_OFFSET, BODY) \ 1460 ((MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 127 \ 1461 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 0, QImode) \ 1462 : (MIN_OFFSET) >= 0 && (MAX_OFFSET) <= 255 \ 1463 ? (ADDR_DIFF_VEC_FLAGS (BODY).offset_unsigned = 1, QImode) \ 1464 : (MIN_OFFSET) >= -32768 && (MAX_OFFSET) <= 32767 ? HImode \ 1465 : SImode) 1466 1467 /* Define as C expression which evaluates to nonzero if the tablejump 1468 instruction expects the table to contain offsets from the address of the 1469 table. 1470 Do not define this if the table should contain absolute addresses. */ 1471 #define CASE_VECTOR_PC_RELATIVE 1 1472 1473 /* Define it here, so that it doesn't get bumped to 64-bits on SHmedia. */ 1474 #define FLOAT_TYPE_SIZE 32 1475 1476 /* Since the SH2e has only `float' support, it is desirable to make all 1477 floating point types equivalent to `float'. */ 1478 #define DOUBLE_TYPE_SIZE (TARGET_FPU_SINGLE_ONLY ? 32 : 64) 1479 1480 /* 'char' is signed by default. */ 1481 #define DEFAULT_SIGNED_CHAR 1 1482 1483 /* The type of size_t unsigned int. */ 1484 #define SIZE_TYPE ("unsigned int") 1485 1486 #undef PTRDIFF_TYPE 1487 #define PTRDIFF_TYPE ("int") 1488 1489 #define WCHAR_TYPE "short unsigned int" 1490 #define WCHAR_TYPE_SIZE 16 1491 1492 #define SH_ELF_WCHAR_TYPE "long int" 1493 1494 /* Max number of bytes we can move from memory to memory 1495 in one reasonably fast instruction. */ 1496 #define MOVE_MAX (4) 1497 1498 /* Maximum value possibly taken by MOVE_MAX. Must be defined whenever 1499 MOVE_MAX is not a compile-time constant. */ 1500 #define MAX_MOVE_MAX 8 1501 1502 /* Max number of bytes we want move_by_pieces to be able to copy 1503 efficiently. */ 1504 #define MOVE_MAX_PIECES (TARGET_SH4 ? 8 : 4) 1505 1506 /* Define if operations between registers always perform the operation 1507 on the full register even if a narrower mode is specified. */ 1508 #define WORD_REGISTER_OPERATIONS 1 1509 1510 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1511 will either zero-extend or sign-extend. The value of this macro should 1512 be the code that says which one of the two operations is implicitly 1513 done, UNKNOWN if none. */ 1514 #define LOAD_EXTEND_OP(MODE) ((MODE) != SImode ? SIGN_EXTEND : UNKNOWN) 1515 1516 /* Define if loading short immediate values into registers sign extends. */ 1517 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 1518 1519 /* Nonzero if access to memory by bytes is no faster than for words. */ 1520 #define SLOW_BYTE_ACCESS 1 1521 1522 /* Nonzero if the target supports dynamic shift instructions 1523 like shad and shld. */ 1524 #define TARGET_DYNSHIFT (TARGET_SH3 || TARGET_SH2A) 1525 1526 /* The cost of using the dynamic shift insns (shad, shld) are the same 1527 if they are available. If they are not available a library function will 1528 be emitted instead, which is more expensive. */ 1529 #define SH_DYNAMIC_SHIFT_COST (TARGET_DYNSHIFT ? 1 : 20) 1530 1531 /* Defining SHIFT_COUNT_TRUNCATED tells the combine pass that code like 1532 (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1533 This is not generally true when hardware dynamic shifts (shad, shld) are 1534 used, because they check the sign bit _before_ the modulo op. The sign 1535 bit determines whether it is a left shift or a right shift: 1536 if (Y < 0) 1537 return X << (Y & 31); 1538 else 1539 return X >> (-Y) & 31); 1540 1541 The dynamic shift library routines in lib1funcs.S do not use the sign bit 1542 like the hardware dynamic shifts and truncate the shift count to 31. 1543 We define SHIFT_COUNT_TRUNCATED to 0 and express the implied shift count 1544 truncation in the library function call patterns, as this gives slightly 1545 more compact code. */ 1546 #define SHIFT_COUNT_TRUNCATED (0) 1547 1548 /* Define this if addresses of constant functions 1549 shouldn't be put through pseudo regs where they can be cse'd. 1550 Desirable on machines where ordinary constants are expensive 1551 but a CALL with constant address is cheap. */ 1552 /*#define NO_FUNCTION_CSE 1*/ 1553 1554 /* The machine modes of pointers and functions. */ 1555 #define Pmode (SImode) 1556 #define FUNCTION_MODE Pmode 1557 1558 /* The multiply insn on the SH1 and the divide insns on the SH1 and SH2 1559 are actually function calls with some special constraints on arguments 1560 and register usage. 1561 1562 These macros tell reorg that the references to arguments and 1563 register clobbers for insns of type sfunc do not appear to happen 1564 until after the millicode call. This allows reorg to put insns 1565 which set the argument registers into the delay slot of the millicode 1566 call -- thus they act more like traditional CALL_INSNs. 1567 1568 get_attr_is_sfunc will try to recognize the given insn, so make sure to 1569 filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns 1570 in particular. */ 1571 1572 #define INSN_SETS_ARE_DELAYED(X) \ 1573 ((NONJUMP_INSN_P (X) \ 1574 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1575 && GET_CODE (PATTERN (X)) != USE \ 1576 && GET_CODE (PATTERN (X)) != CLOBBER \ 1577 && get_attr_is_sfunc (X))) 1578 1579 #define INSN_REFERENCES_ARE_DELAYED(X) \ 1580 ((NONJUMP_INSN_P (X) \ 1581 && GET_CODE (PATTERN (X)) != SEQUENCE \ 1582 && GET_CODE (PATTERN (X)) != USE \ 1583 && GET_CODE (PATTERN (X)) != CLOBBER \ 1584 && get_attr_is_sfunc (X))) 1585 1586 1587 /* Position Independent Code. */ 1588 1589 /* We can't directly access anything that contains a symbol, 1590 nor can we indirect via the constant pool. */ 1591 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1592 ((! nonpic_symbol_mentioned_p (X) \ 1593 && (GET_CODE (X) != SYMBOL_REF \ 1594 || ! CONSTANT_POOL_ADDRESS_P (X) \ 1595 || ! nonpic_symbol_mentioned_p (get_pool_constant (X))))) 1596 1597 #define SYMBOLIC_CONST_P(X) \ 1598 ((GET_CODE (X) == SYMBOL_REF || GET_CODE (X) == LABEL_REF) \ 1599 && nonpic_symbol_mentioned_p (X)) 1600 1601 /* Compute extra cost of moving data between one register class 1602 and another. */ 1603 1604 /* If SECONDARY*_RELOAD_CLASS says something about the src/dst pair, regclass 1605 uses this information. Hence, the general register <-> floating point 1606 register information here is not used for SFmode. */ 1607 #define REGCLASS_HAS_GENERAL_REG(CLASS) \ 1608 ((CLASS) == GENERAL_REGS || (CLASS) == R0_REGS || (CLASS) == NON_SP_REGS \ 1609 || ((CLASS) == SIBCALL_REGS)) 1610 1611 #define REGCLASS_HAS_FP_REG(CLASS) \ 1612 ((CLASS) == FP0_REGS || (CLASS) == FP_REGS \ 1613 || (CLASS) == DF_REGS) 1614 1615 /* ??? Perhaps make MEMORY_MOVE_COST depend on compiler option? This 1616 would be so that people with slow memory systems could generate 1617 different code that does fewer memory accesses. */ 1618 1619 /* A C expression for the cost of a branch instruction. A value of 1 1620 is the default; other values are interpreted relative to that. */ 1621 #define BRANCH_COST(speed_p, predictable_p) sh_branch_cost 1622 1623 /* Assembler output control. */ 1624 1625 /* A C string constant describing how to begin a comment in the target 1626 assembler language. The compiler assumes that the comment will end at 1627 the end of the line. */ 1628 #define ASM_COMMENT_START "!" 1629 1630 #define ASM_APP_ON "" 1631 #define ASM_APP_OFF "" 1632 #define FILE_ASM_OP "\t.file\n" 1633 #define SET_ASM_OP "\t.set\t" 1634 1635 /* How to change between sections. */ 1636 #define TEXT_SECTION_ASM_OP "\t.text" 1637 #define DATA_SECTION_ASM_OP "\t.data" 1638 1639 #if defined CRT_BEGIN || defined CRT_END 1640 /* Arrange for TEXT_SECTION_ASM_OP to be a compile-time constant. */ 1641 #undef TEXT_SECTION_ASM_OP 1642 #define TEXT_SECTION_ASM_OP "\t.text" 1643 #endif 1644 1645 #ifndef BSS_SECTION_ASM_OP 1646 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 1647 #endif 1648 1649 #ifndef ASM_OUTPUT_ALIGNED_BSS 1650 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1651 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 1652 #endif 1653 1654 /* Define this so that jump tables go in same section as the current function, 1655 which could be text or it could be a user defined section. */ 1656 #define JUMP_TABLES_IN_TEXT_SECTION 1 1657 1658 #undef DO_GLOBAL_CTORS_BODY 1659 #define DO_GLOBAL_CTORS_BODY \ 1660 { \ 1661 typedef void (*pfunc) (void); \ 1662 extern pfunc __ctors[]; \ 1663 extern pfunc __ctors_end[]; \ 1664 pfunc *p; \ 1665 for (p = __ctors_end; p > __ctors; ) \ 1666 { \ 1667 (*--p)(); \ 1668 } \ 1669 } 1670 1671 #undef DO_GLOBAL_DTORS_BODY 1672 #define DO_GLOBAL_DTORS_BODY \ 1673 { \ 1674 typedef void (*pfunc) (void); \ 1675 extern pfunc __dtors[]; \ 1676 extern pfunc __dtors_end[]; \ 1677 pfunc *p; \ 1678 for (p = __dtors; p < __dtors_end; p++) \ 1679 { \ 1680 (*p)(); \ 1681 } \ 1682 } 1683 1684 #define ASM_OUTPUT_REG_PUSH(file, v) \ 1685 { \ 1686 fprintf ((file), "\tmov.l\tr%d,@-r15\n", (v)); \ 1687 } 1688 1689 #define ASM_OUTPUT_REG_POP(file, v) \ 1690 { \ 1691 fprintf ((file), "\tmov.l\t@r15+,r%d\n", (v)); \ 1692 } 1693 1694 /* DBX register number for a given compiler register number. */ 1695 /* GDB has FPUL at 23 and FP0 at 25, so we must add one to all FP registers 1696 to match gdb. */ 1697 /* expand_builtin_init_dwarf_reg_sizes uses this to test if a 1698 register exists, so we should return -1 for invalid register numbers. */ 1699 #define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO) 1700 1701 #define SH_DBX_REGISTER_NUMBER(REGNO) \ 1702 (IN_RANGE ((REGNO), \ 1703 (unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \ 1704 FIRST_GENERAL_REG + 15U) \ 1705 ? ((unsigned) (REGNO) - FIRST_GENERAL_REG) \ 1706 : ((int) (REGNO) >= FIRST_FP_REG \ 1707 && ((int) (REGNO) \ 1708 <= (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1)))) \ 1709 ? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \ 1710 : XD_REGISTER_P (REGNO) \ 1711 ? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \ 1712 : (REGNO) == PR_REG \ 1713 ? (17) \ 1714 : (REGNO) == GBR_REG \ 1715 ? (18) \ 1716 : (REGNO) == MACH_REG \ 1717 ? (20) \ 1718 : (REGNO) == MACL_REG \ 1719 ? (21) \ 1720 : (REGNO) == T_REG \ 1721 ? (22) \ 1722 : (REGNO) == FPUL_REG \ 1723 ? (23) \ 1724 : (REGNO) == FPSCR_REG \ 1725 ? (24) \ 1726 : (unsigned) -1) 1727 1728 /* This is how to output an assembler line 1729 that says to advance the location counter 1730 to a multiple of 2**LOG bytes. */ 1731 1732 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1733 if ((LOG) != 0) \ 1734 fprintf ((FILE), "\t.align %d\n", (LOG)) 1735 1736 /* Globalizing directive for a label. */ 1737 #define GLOBAL_ASM_OP "\t.global\t" 1738 1739 /* #define ASM_OUTPUT_CASE_END(STREAM,NUM,TABLE) */ 1740 1741 /* Output a relative address table. */ 1742 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM,BODY,VALUE,REL) \ 1743 switch (GET_MODE (BODY)) \ 1744 { \ 1745 case E_SImode: \ 1746 asm_fprintf ((STREAM), "\t.long\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1747 break; \ 1748 case E_HImode: \ 1749 asm_fprintf ((STREAM), "\t.word\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1750 break; \ 1751 case E_QImode: \ 1752 asm_fprintf ((STREAM), "\t.byte\t%LL%d-%LL%d\n", (VALUE),(REL)); \ 1753 break; \ 1754 default: \ 1755 break; \ 1756 } 1757 1758 /* Output an absolute table element. */ 1759 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM,VALUE) \ 1760 do { \ 1761 if (! optimize || TARGET_BIGTABLE) \ 1762 asm_fprintf ((STREAM), "\t.long\t%LL%d\n", (VALUE)); \ 1763 else \ 1764 asm_fprintf ((STREAM), "\t.word\t%LL%d\n", (VALUE)); \ 1765 } while (0) 1766 1767 /* A C statement to be executed just prior to the output of 1768 assembler code for INSN, to modify the extracted operands so 1769 they will be output differently. 1770 1771 Here the argument OPVEC is the vector containing the operands 1772 extracted from INSN, and NOPERANDS is the number of elements of 1773 the vector which contain meaningful data for this insn. 1774 The contents of this vector are what will be used to convert the insn 1775 template into assembler code, so you can change the assembler output 1776 by changing the contents of the vector. */ 1777 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 1778 final_prescan_insn ((INSN), (OPVEC), (NOPERANDS)) 1779 1780 /* Which processor to schedule for. The elements of the enumeration must 1781 match exactly the cpu attribute in the sh.md file. */ 1782 enum processor_type { 1783 PROCESSOR_SH1, 1784 PROCESSOR_SH2, 1785 PROCESSOR_SH2E, 1786 PROCESSOR_SH2A, 1787 PROCESSOR_SH3, 1788 PROCESSOR_SH3E, 1789 PROCESSOR_SH4, 1790 PROCESSOR_SH4A 1791 }; 1792 1793 #define sh_cpu_attr ((enum attr_cpu)sh_cpu) 1794 extern enum processor_type sh_cpu; 1795 1796 enum mdep_reorg_phase_e 1797 { 1798 SH_BEFORE_MDEP_REORG, 1799 SH_INSERT_USES_LABELS, 1800 SH_SHORTEN_BRANCHES0, 1801 SH_FIXUP_PCLOAD, 1802 SH_SHORTEN_BRANCHES1, 1803 SH_AFTER_MDEP_REORG 1804 }; 1805 1806 extern enum mdep_reorg_phase_e mdep_reorg_phase; 1807 1808 /* Handle Renesas compiler's pragmas. */ 1809 #define REGISTER_TARGET_PRAGMAS() do { \ 1810 c_register_pragma (0, "interrupt", sh_pr_interrupt); \ 1811 c_register_pragma (0, "trapa", sh_pr_trapa); \ 1812 c_register_pragma (0, "nosave_low_regs", sh_pr_nosave_low_regs); \ 1813 } while (0) 1814 1815 extern tree sh_deferred_function_attributes; 1816 extern tree *sh_deferred_function_attributes_tail; 1817 1818 1819 1820 /* Instructions with unfilled delay slots take up an 1821 extra two bytes for the nop in the delay slot. 1822 sh-dsp parallel processing insns are four bytes long. */ 1823 #define ADJUST_INSN_LENGTH(X, LENGTH) \ 1824 (LENGTH) += sh_insn_length_adjustment (X); 1825 1826 /* Define this macro if it is advisable to hold scalars in registers 1827 in a wider mode than that declared by the program. In such cases, 1828 the value is constrained to be within the bounds of the declared 1829 type, but kept valid in the wider mode. The signedness of the 1830 extension may differ from that of the type. 1831 1832 Leaving the unsignedp unchanged gives better code than always setting it 1833 to 0. This is despite the fact that we have only signed char and short 1834 load instructions. */ 1835 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1836 if (GET_MODE_CLASS (MODE) == MODE_INT \ 1837 && GET_MODE_SIZE (MODE) < 4/* ! UNITS_PER_WORD */)\ 1838 (UNSIGNEDP) = ((MODE) == SImode ? 0 : (UNSIGNEDP)), (MODE) = SImode; 1839 1840 #define MAX_FIXED_MODE_SIZE (64) 1841 1842 /* Better to allocate once the maximum space for outgoing args in the 1843 prologue rather than duplicate around each call. */ 1844 #define ACCUMULATE_OUTGOING_ARGS TARGET_ACCUMULATE_OUTGOING_ARGS 1845 1846 #define NUM_MODES_FOR_MODE_SWITCHING { FP_MODE_NONE } 1847 1848 #define OPTIMIZE_MODE_SWITCHING(ENTITY) (TARGET_FPU_DOUBLE) 1849 1850 #define ACTUAL_NORMAL_MODE(ENTITY) \ 1851 (TARGET_FPU_SINGLE ? FP_MODE_SINGLE : FP_MODE_DOUBLE) 1852 1853 #define NORMAL_MODE(ENTITY) \ 1854 (sh_cfun_interrupt_handler_p () \ 1855 ? (TARGET_FMOVD ? FP_MODE_DOUBLE : FP_MODE_NONE) \ 1856 : ACTUAL_NORMAL_MODE (ENTITY)) 1857 1858 #define EPILOGUE_USES(REGNO) (TARGET_FPU_ANY && REGNO == FPSCR_REG) 1859 1860 #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (PR_REG)) 1861 1862 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 4U : INVALID_REGNUM) 1863 1864 #define EH_RETURN_STACKADJ_REGNO STATIC_CHAIN_REGNUM 1865 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_STACKADJ_REGNO) 1866 1867 /* We have to distinguish between code and data, so that we apply 1868 datalabel where and only where appropriate. Use sdataN for data. */ 1869 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1870 ((TARGET_FDPIC \ 1871 ? ((GLOBAL) ? DW_EH_PE_indirect | DW_EH_PE_datarel : DW_EH_PE_pcrel) \ 1872 : ((flag_pic && (GLOBAL) ? DW_EH_PE_indirect : 0) \ 1873 | (flag_pic ? DW_EH_PE_pcrel : DW_EH_PE_absptr))) \ 1874 | ((CODE) ? 0 : DW_EH_PE_sdata4)) 1875 1876 /* Handle special EH pointer encodings. Absolute, pc-relative, and 1877 indirect are handled automatically. */ 1878 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 1879 do { \ 1880 if (((ENCODING) & 0xf) != DW_EH_PE_sdata4 \ 1881 && ((ENCODING) & 0xf) != DW_EH_PE_sdata8) \ 1882 { \ 1883 gcc_assert (GET_CODE (ADDR) == SYMBOL_REF); \ 1884 SYMBOL_REF_FLAGS (ADDR) |= SYMBOL_FLAG_FUNCTION; \ 1885 if (0) goto DONE; \ 1886 } \ 1887 if (TARGET_FDPIC \ 1888 && ((ENCODING) & 0xf0) == (DW_EH_PE_indirect | DW_EH_PE_datarel)) \ 1889 { \ 1890 fputs ("\t.ualong ", FILE); \ 1891 output_addr_const (FILE, ADDR); \ 1892 if (GET_CODE (ADDR) == SYMBOL_REF && SYMBOL_REF_FUNCTION_P (ADDR)) \ 1893 fputs ("@GOTFUNCDESC", FILE); \ 1894 else \ 1895 fputs ("@GOT", FILE); \ 1896 goto DONE; \ 1897 } \ 1898 } while (0) 1899 1900 #if (defined CRT_BEGIN || defined CRT_END) 1901 /* SH constant pool breaks the devices in crtstuff.c to control section 1902 in where code resides. We have to write it as asm code. */ 1903 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 1904 asm (SECTION_OP "\n\ 1905 mov.l 1f,r1\n\ 1906 mova 2f,r0\n\ 1907 braf r1\n\ 1908 lds r0,pr\n\ 1909 0: .p2align 2\n\ 1910 1: .long " USER_LABEL_PREFIX #FUNC " - 0b\n\ 1911 2:\n" TEXT_SECTION_ASM_OP); 1912 #endif /* (defined CRT_BEGIN || defined CRT_END) */ 1913 1914 #endif /* ! GCC_SH_H */ 1915