1 /* { dg-do compile { target { ! ia32 } } } */
2 /* { dg-options "-O2 -mavx512vl -mno-avx512dq -masm=att" } */
3
4 typedef int V1 __attribute__((vector_size (32)));
5 typedef long long V2 __attribute__((vector_size (32)));
6 typedef float V3 __attribute__((vector_size (32)));
7 typedef double V4 __attribute__((vector_size (32)));
8
9 void
f1(V1 x,int y)10 f1 (V1 x, int y)
11 {
12 register V1 a __asm ("xmm16");
13 a = x;
14 asm volatile ("" : "+v" (a));
15 a[3] = y;
16 asm volatile ("" : "+v" (a));
17 }
18
19 void
f2(V1 x,int y)20 f2 (V1 x, int y)
21 {
22 register V1 a __asm ("xmm16");
23 a = x;
24 asm volatile ("" : "+v" (a));
25 a[6] = y;
26 asm volatile ("" : "+v" (a));
27 }
28
29 void
f3(V2 x,long long y)30 f3 (V2 x, long long y)
31 {
32 register V2 a __asm ("xmm16");
33 a = x;
34 asm volatile ("" : "+v" (a));
35 a[1] = y;
36 asm volatile ("" : "+v" (a));
37 }
38
39 void
f4(V2 x,long long y)40 f4 (V2 x, long long y)
41 {
42 register V2 a __asm ("xmm16");
43 a = x;
44 asm volatile ("" : "+v" (a));
45 a[3] = y;
46 asm volatile ("" : "+v" (a));
47 }
48
49 void
f5(V3 x,float y)50 f5 (V3 x, float y)
51 {
52 register V3 a __asm ("xmm16");
53 a = x;
54 asm volatile ("" : "+v" (a));
55 a[3] = y;
56 asm volatile ("" : "+v" (a));
57 }
58
59 void
f6(V3 x,float y)60 f6 (V3 x, float y)
61 {
62 register V3 a __asm ("xmm16");
63 a = x;
64 asm volatile ("" : "+v" (a));
65 a[6] = y;
66 asm volatile ("" : "+v" (a));
67 }
68
69 void
f7(V4 x,double y)70 f7 (V4 x, double y)
71 {
72 register V4 a __asm ("xmm16");
73 a = x;
74 asm volatile ("" : "+v" (a));
75 a[1] = y;
76 asm volatile ("" : "+v" (a));
77 }
78
79 void
f8(V4 x,double y)80 f8 (V4 x, double y)
81 {
82 register V4 a __asm ("xmm16");
83 a = x;
84 asm volatile ("" : "+v" (a));
85 a[3] = y;
86 asm volatile ("" : "+v" (a));
87 }
88
89 /* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x0\[^\n\r]*%ymm16" 2 } } */
90 /* { dg-final { scan-assembler-times "vinserti32x4\[^\n\r]*0x1\[^\n\r]*%ymm16" 2 } } */
91 /* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\r]*0x0\[^\n\r]*%ymm16" 2 } } */
92 /* { dg-final { scan-assembler-times "vinsertf32x4\[^\n\r]*0x1\[^\n\r]*%ymm16" 2 } } */
93 /* { dg-final { scan-assembler-times "vextracti32x4\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 2 } } */
94 /* { dg-final { scan-assembler-times "vextractf32x4\[^\n\r]*0x1\[^\n\r]*%\[yz]mm16" 2 } } */
95 /* { dg-final { scan-assembler-not "vinserti64x2" } } */
96 /* { dg-final { scan-assembler-not "vinsertf64x2" } } */
97 /* { dg-final { scan-assembler-not "vextracti64x2" } } */
98 /* { dg-final { scan-assembler-not "vextracti64x2" } } */
99