1 /* Machine description for AArch64 architecture. 2 Copyright (C) 2009-2016 Free Software Foundation, Inc. 3 Contributed by ARM Ltd. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, but 13 WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #ifndef GCC_AARCH64_H 23 #define GCC_AARCH64_H 24 25 /* Target CPU builtins. */ 26 #define TARGET_CPU_CPP_BUILTINS() \ 27 aarch64_cpu_cpp_builtins (pfile) 28 29 30 31 #define REGISTER_TARGET_PRAGMAS() aarch64_register_pragmas () 32 33 /* Target machine storage layout. */ 34 35 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 36 if (GET_MODE_CLASS (MODE) == MODE_INT \ 37 && GET_MODE_SIZE (MODE) < 4) \ 38 { \ 39 if (MODE == QImode || MODE == HImode) \ 40 { \ 41 MODE = SImode; \ 42 } \ 43 } 44 45 /* Bits are always numbered from the LSBit. */ 46 #define BITS_BIG_ENDIAN 0 47 48 /* Big/little-endian flavour. */ 49 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 50 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 51 52 /* AdvSIMD is supported in the default configuration, unless disabled by 53 -mgeneral-regs-only or by the +nosimd extension. */ 54 #define TARGET_SIMD (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_SIMD) 55 #define TARGET_FLOAT (!TARGET_GENERAL_REGS_ONLY && AARCH64_ISA_FP) 56 57 #define UNITS_PER_WORD 8 58 59 #define UNITS_PER_VREG 16 60 61 #define PARM_BOUNDARY 64 62 63 #define STACK_BOUNDARY 128 64 65 #define FUNCTION_BOUNDARY 32 66 67 #define EMPTY_FIELD_BOUNDARY 32 68 69 #define BIGGEST_ALIGNMENT 128 70 71 #define SHORT_TYPE_SIZE 16 72 73 #define INT_TYPE_SIZE 32 74 75 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 76 77 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 78 79 #define LONG_LONG_TYPE_SIZE 64 80 81 #define FLOAT_TYPE_SIZE 32 82 83 #define DOUBLE_TYPE_SIZE 64 84 85 #define LONG_DOUBLE_TYPE_SIZE 128 86 87 /* The architecture reserves all bits of the address for hardware use, 88 so the vbit must go into the delta field of pointers to member 89 functions. This is the same config as that in the AArch32 90 port. */ 91 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 92 93 /* Make strings word-aligned so that strcpy from constants will be 94 faster. */ 95 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 96 ((TREE_CODE (EXP) == STRING_CST \ 97 && !optimize_size \ 98 && (ALIGN) < BITS_PER_WORD) \ 99 ? BITS_PER_WORD : ALIGN) 100 101 #define DATA_ALIGNMENT(EXP, ALIGN) \ 102 ((((ALIGN) < BITS_PER_WORD) \ 103 && (TREE_CODE (EXP) == ARRAY_TYPE \ 104 || TREE_CODE (EXP) == UNION_TYPE \ 105 || TREE_CODE (EXP) == RECORD_TYPE)) \ 106 ? BITS_PER_WORD : (ALIGN)) 107 108 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 109 110 #define STRUCTURE_SIZE_BOUNDARY 8 111 112 /* Defined by the ABI */ 113 #define WCHAR_TYPE "unsigned int" 114 #define WCHAR_TYPE_SIZE 32 115 116 /* Using long long breaks -ansi and -std=c90, so these will need to be 117 made conditional for an LLP64 ABI. */ 118 119 #define SIZE_TYPE "long unsigned int" 120 121 #define PTRDIFF_TYPE "long int" 122 123 #define PCC_BITFIELD_TYPE_MATTERS 1 124 125 /* Major revision number of the ARM Architecture implemented by the target. */ 126 extern unsigned aarch64_architecture_version; 127 128 /* Instruction tuning/selection flags. */ 129 130 /* Bit values used to identify processor capabilities. */ 131 #define AARCH64_FL_SIMD (1 << 0) /* Has SIMD instructions. */ 132 #define AARCH64_FL_FP (1 << 1) /* Has FP. */ 133 #define AARCH64_FL_CRYPTO (1 << 2) /* Has crypto. */ 134 #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ 135 /* ARMv8.1 architecture extensions. */ 136 #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ 137 #define AARCH64_FL_V8_1 (1 << 5) /* Has ARMv8.1 extensions. */ 138 139 /* Has FP and SIMD. */ 140 #define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD) 141 142 /* Has FP without SIMD. */ 143 #define AARCH64_FL_FPQ16 (AARCH64_FL_FP & ~AARCH64_FL_SIMD) 144 145 /* Architecture flags that effect instruction selection. */ 146 #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) 147 #define AARCH64_FL_FOR_ARCH8_1 \ 148 (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1) 149 150 /* Macros to test ISA flags. */ 151 152 #define AARCH64_ISA_CRC (aarch64_isa_flags & AARCH64_FL_CRC) 153 #define AARCH64_ISA_CRYPTO (aarch64_isa_flags & AARCH64_FL_CRYPTO) 154 #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) 155 #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) 156 #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) 157 #define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_V8_1) 158 159 /* Crypto is an optional extension to AdvSIMD. */ 160 #define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO) 161 162 /* CRC instructions that can be enabled through +crc arch extension. */ 163 #define TARGET_CRC32 (AARCH64_ISA_CRC) 164 165 /* Atomic instructions that can be enabled through the +lse extension. */ 166 #define TARGET_LSE (AARCH64_ISA_LSE) 167 168 /* Make sure this is always defined so we don't have to check for ifdefs 169 but rather use normal ifs. */ 170 #ifndef TARGET_FIX_ERR_A53_835769_DEFAULT 171 #define TARGET_FIX_ERR_A53_835769_DEFAULT 0 172 #else 173 #undef TARGET_FIX_ERR_A53_835769_DEFAULT 174 #define TARGET_FIX_ERR_A53_835769_DEFAULT 1 175 #endif 176 177 /* Apply the workaround for Cortex-A53 erratum 835769. */ 178 #define TARGET_FIX_ERR_A53_835769 \ 179 ((aarch64_fix_a53_err835769 == 2) \ 180 ? TARGET_FIX_ERR_A53_835769_DEFAULT : aarch64_fix_a53_err835769) 181 182 /* Make sure this is always defined so we don't have to check for ifdefs 183 but rather use normal ifs. */ 184 #ifndef TARGET_FIX_ERR_A53_843419_DEFAULT 185 #define TARGET_FIX_ERR_A53_843419_DEFAULT 0 186 #else 187 #undef TARGET_FIX_ERR_A53_843419_DEFAULT 188 #define TARGET_FIX_ERR_A53_843419_DEFAULT 1 189 #endif 190 191 /* Apply the workaround for Cortex-A53 erratum 843419. */ 192 #define TARGET_FIX_ERR_A53_843419 \ 193 ((aarch64_fix_a53_err843419 == 2) \ 194 ? TARGET_FIX_ERR_A53_843419_DEFAULT : aarch64_fix_a53_err843419) 195 196 /* ARMv8.1 Adv.SIMD support. */ 197 #define TARGET_SIMD_RDMA (TARGET_SIMD && AARCH64_ISA_RDMA) 198 199 /* Standard register usage. */ 200 201 /* 31 64-bit general purpose registers R0-R30: 202 R30 LR (link register) 203 R29 FP (frame pointer) 204 R19-R28 Callee-saved registers 205 R18 The platform register; use as temporary register. 206 R17 IP1 The second intra-procedure-call temporary register 207 (can be used by call veneers and PLT code); otherwise use 208 as a temporary register 209 R16 IP0 The first intra-procedure-call temporary register (can 210 be used by call veneers and PLT code); otherwise use as a 211 temporary register 212 R9-R15 Temporary registers 213 R8 Structure value parameter / temporary register 214 R0-R7 Parameter/result registers 215 216 SP stack pointer, encoded as X/R31 where permitted. 217 ZR zero register, encoded as X/R31 elsewhere 218 219 32 x 128-bit floating-point/vector registers 220 V16-V31 Caller-saved (temporary) registers 221 V8-V15 Callee-saved registers 222 V0-V7 Parameter/result registers 223 224 The vector register V0 holds scalar B0, H0, S0 and D0 in its least 225 significant bits. Unlike AArch32 S1 is not packed into D0, 226 etc. */ 227 228 /* Note that we don't mark X30 as a call-clobbered register. The idea is 229 that it's really the call instructions themselves which clobber X30. 230 We don't care what the called function does with it afterwards. 231 232 This approach makes it easier to implement sibcalls. Unlike normal 233 calls, sibcalls don't clobber X30, so the register reaches the 234 called function intact. EPILOGUE_USES says that X30 is useful 235 to the called function. */ 236 237 #define FIXED_REGISTERS \ 238 { \ 239 0, 0, 0, 0, 0, 0, 0, 0, /* R0 - R7 */ \ 240 0, 0, 0, 0, 0, 0, 0, 0, /* R8 - R15 */ \ 241 0, 0, 0, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 242 0, 0, 0, 0, 0, 1, 0, 1, /* R24 - R30, SP */ \ 243 0, 0, 0, 0, 0, 0, 0, 0, /* V0 - V7 */ \ 244 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 245 0, 0, 0, 0, 0, 0, 0, 0, /* V16 - V23 */ \ 246 0, 0, 0, 0, 0, 0, 0, 0, /* V24 - V31 */ \ 247 1, 1, 1, /* SFP, AP, CC */ \ 248 } 249 250 #define CALL_USED_REGISTERS \ 251 { \ 252 1, 1, 1, 1, 1, 1, 1, 1, /* R0 - R7 */ \ 253 1, 1, 1, 1, 1, 1, 1, 1, /* R8 - R15 */ \ 254 1, 1, 1, 0, 0, 0, 0, 0, /* R16 - R23 */ \ 255 0, 0, 0, 0, 0, 1, 1, 1, /* R24 - R30, SP */ \ 256 1, 1, 1, 1, 1, 1, 1, 1, /* V0 - V7 */ \ 257 0, 0, 0, 0, 0, 0, 0, 0, /* V8 - V15 */ \ 258 1, 1, 1, 1, 1, 1, 1, 1, /* V16 - V23 */ \ 259 1, 1, 1, 1, 1, 1, 1, 1, /* V24 - V31 */ \ 260 1, 1, 1, /* SFP, AP, CC */ \ 261 } 262 263 #define REGISTER_NAMES \ 264 { \ 265 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", \ 266 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", \ 267 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", \ 268 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", \ 269 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", \ 270 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", \ 271 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", \ 272 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", \ 273 "sfp", "ap", "cc", \ 274 } 275 276 /* Generate the register aliases for core register N */ 277 #define R_ALIASES(N) {"r" # N, R0_REGNUM + (N)}, \ 278 {"w" # N, R0_REGNUM + (N)} 279 280 #define V_ALIASES(N) {"q" # N, V0_REGNUM + (N)}, \ 281 {"d" # N, V0_REGNUM + (N)}, \ 282 {"s" # N, V0_REGNUM + (N)}, \ 283 {"h" # N, V0_REGNUM + (N)}, \ 284 {"b" # N, V0_REGNUM + (N)} 285 286 /* Provide aliases for all of the ISA defined register name forms. 287 These aliases are convenient for use in the clobber lists of inline 288 asm statements. */ 289 290 #define ADDITIONAL_REGISTER_NAMES \ 291 { R_ALIASES(0), R_ALIASES(1), R_ALIASES(2), R_ALIASES(3), \ 292 R_ALIASES(4), R_ALIASES(5), R_ALIASES(6), R_ALIASES(7), \ 293 R_ALIASES(8), R_ALIASES(9), R_ALIASES(10), R_ALIASES(11), \ 294 R_ALIASES(12), R_ALIASES(13), R_ALIASES(14), R_ALIASES(15), \ 295 R_ALIASES(16), R_ALIASES(17), R_ALIASES(18), R_ALIASES(19), \ 296 R_ALIASES(20), R_ALIASES(21), R_ALIASES(22), R_ALIASES(23), \ 297 R_ALIASES(24), R_ALIASES(25), R_ALIASES(26), R_ALIASES(27), \ 298 R_ALIASES(28), R_ALIASES(29), R_ALIASES(30), {"wsp", R0_REGNUM + 31}, \ 299 V_ALIASES(0), V_ALIASES(1), V_ALIASES(2), V_ALIASES(3), \ 300 V_ALIASES(4), V_ALIASES(5), V_ALIASES(6), V_ALIASES(7), \ 301 V_ALIASES(8), V_ALIASES(9), V_ALIASES(10), V_ALIASES(11), \ 302 V_ALIASES(12), V_ALIASES(13), V_ALIASES(14), V_ALIASES(15), \ 303 V_ALIASES(16), V_ALIASES(17), V_ALIASES(18), V_ALIASES(19), \ 304 V_ALIASES(20), V_ALIASES(21), V_ALIASES(22), V_ALIASES(23), \ 305 V_ALIASES(24), V_ALIASES(25), V_ALIASES(26), V_ALIASES(27), \ 306 V_ALIASES(28), V_ALIASES(29), V_ALIASES(30), V_ALIASES(31) \ 307 } 308 309 /* Say that the epilogue uses the return address register. Note that 310 in the case of sibcalls, the values "used by the epilogue" are 311 considered live at the start of the called function. */ 312 313 #define EPILOGUE_USES(REGNO) \ 314 (epilogue_completed && (REGNO) == LR_REGNUM) 315 316 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 317 the stack pointer does not matter. The value is tested only in 318 functions that have frame pointers. */ 319 #define EXIT_IGNORE_STACK 1 320 321 #define STATIC_CHAIN_REGNUM R18_REGNUM 322 #define HARD_FRAME_POINTER_REGNUM R29_REGNUM 323 #define FRAME_POINTER_REGNUM SFP_REGNUM 324 #define STACK_POINTER_REGNUM SP_REGNUM 325 #define ARG_POINTER_REGNUM AP_REGNUM 326 #define FIRST_PSEUDO_REGISTER 67 327 328 /* The number of (integer) argument register available. */ 329 #define NUM_ARG_REGS 8 330 #define NUM_FP_ARG_REGS 8 331 332 /* A Homogeneous Floating-Point or Short-Vector Aggregate may have at most 333 four members. */ 334 #define HA_MAX_NUM_FLDS 4 335 336 /* External dwarf register number scheme. These number are used to 337 identify registers in dwarf debug information, the values are 338 defined by the AArch64 ABI. The numbering scheme is independent of 339 GCC's internal register numbering scheme. */ 340 341 #define AARCH64_DWARF_R0 0 342 343 /* The number of R registers, note 31! not 32. */ 344 #define AARCH64_DWARF_NUMBER_R 31 345 346 #define AARCH64_DWARF_SP 31 347 #define AARCH64_DWARF_V0 64 348 349 /* The number of V registers. */ 350 #define AARCH64_DWARF_NUMBER_V 32 351 352 /* For signal frames we need to use an alternative return column. This 353 value must not correspond to a hard register and must be out of the 354 range of DWARF_FRAME_REGNUM(). */ 355 #define DWARF_ALT_FRAME_RETURN_COLUMN \ 356 (AARCH64_DWARF_V0 + AARCH64_DWARF_NUMBER_V) 357 358 /* We add 1 extra frame register for use as the 359 DWARF_ALT_FRAME_RETURN_COLUMN. */ 360 #define DWARF_FRAME_REGISTERS (DWARF_ALT_FRAME_RETURN_COLUMN + 1) 361 362 363 #define DBX_REGISTER_NUMBER(REGNO) aarch64_dbx_register_number (REGNO) 364 /* Provide a definition of DWARF_FRAME_REGNUM here so that fallback unwinders 365 can use DWARF_ALT_FRAME_RETURN_COLUMN defined below. This is just the same 366 as the default definition in dwarf2out.c. */ 367 #undef DWARF_FRAME_REGNUM 368 #define DWARF_FRAME_REGNUM(REGNO) DBX_REGISTER_NUMBER (REGNO) 369 370 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 371 372 #define HARD_REGNO_NREGS(REGNO, MODE) aarch64_hard_regno_nregs (REGNO, MODE) 373 374 #define HARD_REGNO_MODE_OK(REGNO, MODE) aarch64_hard_regno_mode_ok (REGNO, MODE) 375 376 #define MODES_TIEABLE_P(MODE1, MODE2) aarch64_modes_tieable_p (MODE1, MODE2) 377 378 #define DWARF2_UNWIND_INFO 1 379 380 /* Use R0 through R3 to pass exception handling information. */ 381 #define EH_RETURN_DATA_REGNO(N) \ 382 ((N) < 4 ? ((unsigned int) R0_REGNUM + (N)) : INVALID_REGNUM) 383 384 /* Select a format to encode pointers in exception handling data. */ 385 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 386 aarch64_asm_preferred_eh_data_format ((CODE), (GLOBAL)) 387 388 /* Output the assembly strings we want to add to a function definition. */ 389 #define ASM_DECLARE_FUNCTION_NAME(STR, NAME, DECL) \ 390 aarch64_declare_function_name (STR, NAME, DECL) 391 392 /* For EH returns X4 contains the stack adjustment. */ 393 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, R4_REGNUM) 394 #define EH_RETURN_HANDLER_RTX aarch64_eh_return_handler_rtx () 395 396 /* Don't use __builtin_setjmp until we've defined it. */ 397 #undef DONT_USE_BUILTIN_SETJMP 398 #define DONT_USE_BUILTIN_SETJMP 1 399 400 /* Register in which the structure value is to be returned. */ 401 #define AARCH64_STRUCT_VALUE_REGNUM R8_REGNUM 402 403 /* Non-zero if REGNO is part of the Core register set. 404 405 The rather unusual way of expressing this check is to avoid 406 warnings when building the compiler when R0_REGNUM is 0 and REGNO 407 is unsigned. */ 408 #define GP_REGNUM_P(REGNO) \ 409 (((unsigned) (REGNO - R0_REGNUM)) <= (R30_REGNUM - R0_REGNUM)) 410 411 #define FP_REGNUM_P(REGNO) \ 412 (((unsigned) (REGNO - V0_REGNUM)) <= (V31_REGNUM - V0_REGNUM)) 413 414 #define FP_LO_REGNUM_P(REGNO) \ 415 (((unsigned) (REGNO - V0_REGNUM)) <= (V15_REGNUM - V0_REGNUM)) 416 417 418 /* Register and constant classes. */ 419 420 enum reg_class 421 { 422 NO_REGS, 423 TAILCALL_ADDR_REGS, 424 GENERAL_REGS, 425 STACK_REG, 426 POINTER_REGS, 427 FP_LO_REGS, 428 FP_REGS, 429 ALL_REGS, 430 LIM_REG_CLASSES /* Last */ 431 }; 432 433 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 434 435 #define REG_CLASS_NAMES \ 436 { \ 437 "NO_REGS", \ 438 "TAILCALL_ADDR_REGS", \ 439 "GENERAL_REGS", \ 440 "STACK_REG", \ 441 "POINTER_REGS", \ 442 "FP_LO_REGS", \ 443 "FP_REGS", \ 444 "ALL_REGS" \ 445 } 446 447 #define REG_CLASS_CONTENTS \ 448 { \ 449 { 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 450 { 0x0004ffff, 0x00000000, 0x00000000 }, /* TAILCALL_ADDR_REGS */\ 451 { 0x7fffffff, 0x00000000, 0x00000003 }, /* GENERAL_REGS */ \ 452 { 0x80000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 453 { 0xffffffff, 0x00000000, 0x00000003 }, /* POINTER_REGS */ \ 454 { 0x00000000, 0x0000ffff, 0x00000000 }, /* FP_LO_REGS */ \ 455 { 0x00000000, 0xffffffff, 0x00000000 }, /* FP_REGS */ \ 456 { 0xffffffff, 0xffffffff, 0x00000007 } /* ALL_REGS */ \ 457 } 458 459 #define REGNO_REG_CLASS(REGNO) aarch64_regno_regclass (REGNO) 460 461 #define INDEX_REG_CLASS GENERAL_REGS 462 #define BASE_REG_CLASS POINTER_REGS 463 464 /* Register pairs used to eliminate unneeded registers that point into 465 the stack frame. */ 466 #define ELIMINABLE_REGS \ 467 { \ 468 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 469 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 470 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 471 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 472 } 473 474 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 475 (OFFSET) = aarch64_initial_elimination_offset (FROM, TO) 476 477 /* CPU/ARCH option handling. */ 478 #include "config/aarch64/aarch64-opts.h" 479 480 enum target_cpus 481 { 482 #define AARCH64_CORE(NAME, INTERNAL_IDENT, SCHED, ARCH, FLAGS, COSTS, IMP, PART) \ 483 TARGET_CPU_##INTERNAL_IDENT, 484 #include "aarch64-cores.def" 485 #undef AARCH64_CORE 486 TARGET_CPU_generic 487 }; 488 489 /* If there is no CPU defined at configure, use generic as default. */ 490 #ifndef TARGET_CPU_DEFAULT 491 #define TARGET_CPU_DEFAULT \ 492 (TARGET_CPU_generic | (AARCH64_CPU_DEFAULT_FLAGS << 6)) 493 #endif 494 495 /* If inserting NOP before a mult-accumulate insn remember to adjust the 496 length so that conditional branching code is updated appropriately. */ 497 #define ADJUST_INSN_LENGTH(insn, length) \ 498 do \ 499 { \ 500 if (aarch64_madd_needs_nop (insn)) \ 501 length += 4; \ 502 } while (0) 503 504 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 505 aarch64_final_prescan_insn (INSN); \ 506 507 /* The processor for which instructions should be scheduled. */ 508 extern enum aarch64_processor aarch64_tune; 509 510 /* RTL generation support. */ 511 #define INIT_EXPANDERS aarch64_init_expanders () 512 513 514 /* Stack layout; function entry, exit and calling. */ 515 #define STACK_GROWS_DOWNWARD 1 516 517 #define FRAME_GROWS_DOWNWARD 1 518 519 #define STARTING_FRAME_OFFSET 0 520 521 #define ACCUMULATE_OUTGOING_ARGS 1 522 523 #define FIRST_PARM_OFFSET(FNDECL) 0 524 525 /* Fix for VFP */ 526 #define LIBCALL_VALUE(MODE) \ 527 gen_rtx_REG (MODE, FLOAT_MODE_P (MODE) ? V0_REGNUM : R0_REGNUM) 528 529 #define DEFAULT_PCC_STRUCT_RETURN 0 530 531 #ifdef HOST_WIDE_INT 532 struct GTY (()) aarch64_frame 533 { 534 HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; 535 536 /* The number of extra stack bytes taken up by register varargs. 537 This area is allocated by the callee at the very top of the 538 frame. This value is rounded up to a multiple of 539 STACK_BOUNDARY. */ 540 HOST_WIDE_INT saved_varargs_size; 541 542 HOST_WIDE_INT saved_regs_size; 543 /* Padding if needed after the all the callee save registers have 544 been saved. */ 545 HOST_WIDE_INT padding0; 546 HOST_WIDE_INT hardfp_offset; /* HARD_FRAME_POINTER_REGNUM */ 547 548 /* Offset from the base of the frame (incomming SP) to the 549 hard_frame_pointer. This value is always a multiple of 550 STACK_BOUNDARY. */ 551 HOST_WIDE_INT hard_fp_offset; 552 553 /* The size of the frame. This value is the offset from base of the 554 * frame (incomming SP) to the stack_pointer. This value is always 555 * a multiple of STACK_BOUNDARY. */ 556 557 unsigned wb_candidate1; 558 unsigned wb_candidate2; 559 560 HOST_WIDE_INT frame_size; 561 562 bool laid_out; 563 }; 564 565 typedef struct GTY (()) machine_function 566 { 567 struct aarch64_frame frame; 568 } machine_function; 569 #endif 570 571 /* Which ABI to use. */ 572 enum aarch64_abi_type 573 { 574 AARCH64_ABI_LP64 = 0, 575 AARCH64_ABI_ILP32 = 1 576 }; 577 578 #ifndef AARCH64_ABI_DEFAULT 579 #define AARCH64_ABI_DEFAULT AARCH64_ABI_LP64 580 #endif 581 582 #define TARGET_ILP32 (aarch64_abi & AARCH64_ABI_ILP32) 583 584 enum arm_pcs 585 { 586 ARM_PCS_AAPCS64, /* Base standard AAPCS for 64 bit. */ 587 ARM_PCS_UNKNOWN 588 }; 589 590 591 592 593 /* We can't use machine_mode inside a generator file because it 594 hasn't been created yet; we shouldn't be using any code that 595 needs the real definition though, so this ought to be safe. */ 596 #ifdef GENERATOR_FILE 597 #define MACHMODE int 598 #else 599 #include "insn-modes.h" 600 #define MACHMODE machine_mode 601 #endif 602 603 #ifndef USED_FOR_TARGET 604 /* AAPCS related state tracking. */ 605 typedef struct 606 { 607 enum arm_pcs pcs_variant; 608 int aapcs_arg_processed; /* No need to lay out this argument again. */ 609 int aapcs_ncrn; /* Next Core register number. */ 610 int aapcs_nextncrn; /* Next next core register number. */ 611 int aapcs_nvrn; /* Next Vector register number. */ 612 int aapcs_nextnvrn; /* Next Next Vector register number. */ 613 rtx aapcs_reg; /* Register assigned to this argument. This 614 is NULL_RTX if this parameter goes on 615 the stack. */ 616 MACHMODE aapcs_vfp_rmode; 617 int aapcs_stack_words; /* If the argument is passed on the stack, this 618 is the number of words needed, after rounding 619 up. Only meaningful when 620 aapcs_reg == NULL_RTX. */ 621 int aapcs_stack_size; /* The total size (in words, per 8 byte) of the 622 stack arg area so far. */ 623 } CUMULATIVE_ARGS; 624 #endif 625 626 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 627 (aarch64_pad_arg_upward (MODE, TYPE) ? upward : downward) 628 629 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 630 (aarch64_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 631 632 #define PAD_VARARGS_DOWN 0 633 634 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 635 aarch64_init_cumulative_args (&(CUM), FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) 636 637 #define FUNCTION_ARG_REGNO_P(REGNO) \ 638 aarch64_function_arg_regno_p(REGNO) 639 640 641 /* ISA Features. */ 642 643 /* Addressing modes, etc. */ 644 #define HAVE_POST_INCREMENT 1 645 #define HAVE_PRE_INCREMENT 1 646 #define HAVE_POST_DECREMENT 1 647 #define HAVE_PRE_DECREMENT 1 648 #define HAVE_POST_MODIFY_DISP 1 649 #define HAVE_PRE_MODIFY_DISP 1 650 651 #define MAX_REGS_PER_ADDRESS 2 652 653 #define CONSTANT_ADDRESS_P(X) aarch64_constant_address_p(X) 654 655 /* Try a machine-dependent way of reloading an illegitimate address 656 operand. If we find one, push the reload and jump to WIN. This 657 macro is used in only one place: `find_reloads_address' in reload.c. */ 658 659 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 660 do { \ 661 rtx new_x = aarch64_legitimize_reload_address (&(X), MODE, OPNUM, TYPE, \ 662 IND_L); \ 663 if (new_x) \ 664 { \ 665 X = new_x; \ 666 goto WIN; \ 667 } \ 668 } while (0) 669 670 #define REGNO_OK_FOR_BASE_P(REGNO) \ 671 aarch64_regno_ok_for_base_p (REGNO, true) 672 673 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 674 aarch64_regno_ok_for_index_p (REGNO, true) 675 676 #define LEGITIMATE_PIC_OPERAND_P(X) \ 677 aarch64_legitimate_pic_operand_p (X) 678 679 #define CASE_VECTOR_MODE Pmode 680 681 #define DEFAULT_SIGNED_CHAR 0 682 683 /* An integer expression for the size in bits of the largest integer machine 684 mode that should actually be used. We allow pairs of registers. */ 685 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 686 687 /* Maximum bytes moved by a single instruction (load/store pair). */ 688 #define MOVE_MAX (UNITS_PER_WORD * 2) 689 690 /* The base cost overhead of a memcpy call, for MOVE_RATIO and friends. */ 691 #define AARCH64_CALL_RATIO 8 692 693 /* MOVE_RATIO dictates when we will use the move_by_pieces infrastructure. 694 move_by_pieces will continually copy the largest safe chunks. So a 695 7-byte copy is a 4-byte + 2-byte + byte copy. This proves inefficient 696 for both size and speed of copy, so we will instead use the "movmem" 697 standard name to implement the copy. This logic does not apply when 698 targeting -mstrict-align, so keep a sensible default in that case. */ 699 #define MOVE_RATIO(speed) \ 700 (!STRICT_ALIGNMENT ? 2 : (((speed) ? 15 : AARCH64_CALL_RATIO) / 2)) 701 702 /* For CLEAR_RATIO, when optimizing for size, give a better estimate 703 of the length of a memset call, but use the default otherwise. */ 704 #define CLEAR_RATIO(speed) \ 705 ((speed) ? 15 : AARCH64_CALL_RATIO) 706 707 /* SET_RATIO is similar to CLEAR_RATIO, but for a non-zero constant, so when 708 optimizing for size adjust the ratio to account for the overhead of loading 709 the constant. */ 710 #define SET_RATIO(speed) \ 711 ((speed) ? 15 : AARCH64_CALL_RATIO - 2) 712 713 /* Disable auto-increment in move_by_pieces et al. Use of auto-increment is 714 rarely a good idea in straight-line code since it adds an extra address 715 dependency between each instruction. Better to use incrementing offsets. */ 716 #define USE_LOAD_POST_INCREMENT(MODE) 0 717 #define USE_LOAD_POST_DECREMENT(MODE) 0 718 #define USE_LOAD_PRE_INCREMENT(MODE) 0 719 #define USE_LOAD_PRE_DECREMENT(MODE) 0 720 #define USE_STORE_POST_INCREMENT(MODE) 0 721 #define USE_STORE_POST_DECREMENT(MODE) 0 722 #define USE_STORE_PRE_INCREMENT(MODE) 0 723 #define USE_STORE_PRE_DECREMENT(MODE) 0 724 725 /* ?? #define WORD_REGISTER_OPERATIONS */ 726 727 /* Define if loading from memory in MODE, an integral mode narrower than 728 BITS_PER_WORD will either zero-extend or sign-extend. The value of this 729 macro should be the code that says which one of the two operations is 730 implicitly done, or UNKNOWN if none. */ 731 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 732 733 /* Define this macro to be non-zero if instructions will fail to work 734 if given data not on the nominal alignment. */ 735 #define STRICT_ALIGNMENT TARGET_STRICT_ALIGN 736 737 /* Define this macro to be non-zero if accessing less than a word of 738 memory is no faster than accessing a word of memory, i.e., if such 739 accesses require more than one instruction or if there is no 740 difference in cost. 741 Although there's no difference in instruction count or cycles, 742 in AArch64 we don't want to expand to a sub-word to a 64-bit access 743 if we don't have to, for power-saving reasons. */ 744 #define SLOW_BYTE_ACCESS 0 745 746 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 747 748 #define NO_FUNCTION_CSE 1 749 750 /* Specify the machine mode that the hardware addresses have. 751 After generation of rtl, the compiler makes no further distinction 752 between pointers and any other objects of this machine mode. */ 753 #define Pmode DImode 754 755 /* A C expression whose value is zero if pointers that need to be extended 756 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 757 greater then zero if they are zero-extended and less then zero if the 758 ptr_extend instruction should be used. */ 759 #define POINTERS_EXTEND_UNSIGNED 1 760 761 /* Mode of a function address in a call instruction (for indexing purposes). */ 762 #define FUNCTION_MODE Pmode 763 764 #define SELECT_CC_MODE(OP, X, Y) aarch64_select_cc_mode (OP, X, Y) 765 766 #define REVERSIBLE_CC_MODE(MODE) 1 767 768 #define REVERSE_CONDITION(CODE, MODE) \ 769 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 770 ? reverse_condition_maybe_unordered (CODE) \ 771 : reverse_condition (CODE)) 772 773 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 774 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 775 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 776 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 777 778 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 779 780 #define RETURN_ADDR_RTX aarch64_return_addr 781 782 /* 3 insns + padding + 2 pointer-sized entries. */ 783 #define TRAMPOLINE_SIZE (TARGET_ILP32 ? 24 : 32) 784 785 /* Trampolines contain dwords, so must be dword aligned. */ 786 #define TRAMPOLINE_ALIGNMENT 64 787 788 /* Put trampolines in the text section so that mapping symbols work 789 correctly. */ 790 #define TRAMPOLINE_SECTION text_section 791 792 /* To start with. */ 793 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 794 (aarch64_branch_cost (SPEED_P, PREDICTABLE_P)) 795 796 797 /* Assembly output. */ 798 799 /* For now we'll make all jump tables pc-relative. */ 800 #define CASE_VECTOR_PC_RELATIVE 1 801 802 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 803 ((min < -0x1fff0 || max > 0x1fff0) ? SImode \ 804 : (min < -0x1f0 || max > 0x1f0) ? HImode \ 805 : QImode) 806 807 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 808 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 809 810 #define MCOUNT_NAME "_mcount" 811 812 #define NO_PROFILE_COUNTERS 1 813 814 /* Emit rtl for profiling. Output assembler code to FILE 815 to call "_mcount" for profiling a function entry. */ 816 #define PROFILE_HOOK(LABEL) \ 817 { \ 818 rtx fun, lr; \ 819 lr = get_hard_reg_initial_val (Pmode, LR_REGNUM); \ 820 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_NAME); \ 821 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lr, Pmode); \ 822 } 823 824 /* All the work done in PROFILE_HOOK, but still required. */ 825 #define FUNCTION_PROFILER(STREAM, LABELNO) do { } while (0) 826 827 /* For some reason, the Linux headers think they know how to define 828 these macros. They don't!!! */ 829 #undef ASM_APP_ON 830 #undef ASM_APP_OFF 831 #define ASM_APP_ON "\t" ASM_COMMENT_START " Start of user assembly\n" 832 #define ASM_APP_OFF "\t" ASM_COMMENT_START " End of user assembly\n" 833 834 #define CONSTANT_POOL_BEFORE_FUNCTION 0 835 836 /* This definition should be relocated to aarch64-elf-raw.h. This macro 837 should be undefined in aarch64-linux.h and a clear_cache pattern 838 implmented to emit either the call to __aarch64_sync_cache_range() 839 directly or preferably the appropriate sycall or cache clear 840 instructions inline. */ 841 #define CLEAR_INSN_CACHE(beg, end) \ 842 extern void __aarch64_sync_cache_range (void *, void *); \ 843 __aarch64_sync_cache_range (beg, end) 844 845 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 846 aarch64_cannot_change_mode_class (FROM, TO, CLASS) 847 848 #define SHIFT_COUNT_TRUNCATED !TARGET_SIMD 849 850 /* Choose appropriate mode for caller saves, so we do the minimum 851 required size of load/store. */ 852 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 853 aarch64_hard_regno_caller_save_mode ((REGNO), (NREGS), (MODE)) 854 855 /* Callee only saves lower 64-bits of a 128-bit register. Tell the 856 compiler the callee clobbers the top 64-bits when restoring the 857 bottom 64-bits. */ 858 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 859 (FP_REGNUM_P (REGNO) && GET_MODE_SIZE (MODE) > 8) 860 861 #undef SWITCHABLE_TARGET 862 #define SWITCHABLE_TARGET 1 863 864 /* Check TLS Descriptors mechanism is selected. */ 865 #define TARGET_TLS_DESC (aarch64_tls_dialect == TLS_DESCRIPTORS) 866 867 extern enum aarch64_code_model aarch64_cmodel; 868 869 /* When using the tiny addressing model conditional and unconditional branches 870 can span the whole of the available address space (1MB). */ 871 #define HAS_LONG_COND_BRANCH \ 872 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 873 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 874 875 #define HAS_LONG_UNCOND_BRANCH \ 876 (aarch64_cmodel == AARCH64_CMODEL_TINY \ 877 || aarch64_cmodel == AARCH64_CMODEL_TINY_PIC) 878 879 #define TARGET_SUPPORTS_WIDE_INT 1 880 881 /* Modes valid for AdvSIMD D registers, i.e. that fit in half a Q register. */ 882 #define AARCH64_VALID_SIMD_DREG_MODE(MODE) \ 883 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 884 || (MODE) == V2SFmode || (MODE) == V4HFmode || (MODE) == DImode \ 885 || (MODE) == DFmode) 886 887 /* Modes valid for AdvSIMD Q registers. */ 888 #define AARCH64_VALID_SIMD_QREG_MODE(MODE) \ 889 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 890 || (MODE) == V4SFmode || (MODE) == V8HFmode || (MODE) == V2DImode \ 891 || (MODE) == V2DFmode) 892 893 #define ENDIAN_LANE_N(mode, n) \ 894 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 895 896 /* Support for a configure-time default CPU, etc. We currently support 897 --with-arch and --with-cpu. Both are ignored if either is specified 898 explicitly on the command line at run time. */ 899 #define OPTION_DEFAULT_SPECS \ 900 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 901 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, 902 903 #define MCPU_TO_MARCH_SPEC \ 904 " %{mcpu=*:-march=%:rewrite_mcpu(%{mcpu=*:%*})}" 905 906 extern const char *aarch64_rewrite_mcpu (int argc, const char **argv); 907 #define MCPU_TO_MARCH_SPEC_FUNCTIONS \ 908 { "rewrite_mcpu", aarch64_rewrite_mcpu }, 909 910 #if defined(__aarch64__) 911 extern const char *host_detect_local_cpu (int argc, const char **argv); 912 # define EXTRA_SPEC_FUNCTIONS \ 913 { "local_cpu_detect", host_detect_local_cpu }, \ 914 MCPU_TO_MARCH_SPEC_FUNCTIONS 915 916 # define MCPU_MTUNE_NATIVE_SPECS \ 917 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 918 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 919 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 920 #else 921 # define MCPU_MTUNE_NATIVE_SPECS "" 922 # define EXTRA_SPEC_FUNCTIONS MCPU_TO_MARCH_SPEC_FUNCTIONS 923 #endif 924 925 #define ASM_CPU_SPEC \ 926 MCPU_TO_MARCH_SPEC 927 928 #define EXTRA_SPECS \ 929 { "asm_cpu_spec", ASM_CPU_SPEC } 930 931 #define ASM_OUTPUT_POOL_EPILOGUE aarch64_asm_output_pool_epilogue 932 933 /* This type is the user-visible __fp16, and a pointer to that type. We 934 need it in many places in the backend. Defined in aarch64-builtins.c. */ 935 extern tree aarch64_fp16_type_node; 936 extern tree aarch64_fp16_ptr_type_node; 937 938 /* The generic unwind code in libgcc does not initialize the frame pointer. 939 So in order to unwind a function using a frame pointer, the very first 940 function that is unwound must save the frame pointer. That way the frame 941 pointer is restored and its value is now valid - otherwise _Unwind_GetGR 942 crashes. Libgcc can now be safely built with -fomit-frame-pointer. */ 943 #define LIBGCC2_UNWIND_ATTRIBUTE \ 944 __attribute__((optimize ("no-omit-frame-pointer"))) 945 946 #endif /* GCC_AARCH64_H */ 947