1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. 2 Copyright (C) 1987-2016 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 /* We need to have MOTOROLA always defined (either 0 or 1) because we use 21 if-statements and ?: on it. This way we have compile-time error checking 22 for both the MOTOROLA and MIT code paths. We do rely on the host compiler 23 to optimize away all constant tests. */ 24 #if MOTOROLA /* Use the Motorola assembly syntax. */ 25 #else 26 # define MOTOROLA 0 /* Use the MIT assembly syntax. */ 27 #endif 28 29 /* Handle --with-cpu default option from configure script. */ 30 #define OPTION_DEFAULT_SPECS \ 31 { "cpu", "%{!m68020-40:%{!m68020-60:\ 32 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}" }, 33 34 /* Pass flags to gas indicating which type of processor we have. This 35 can be simplified when we can rely on the assembler supporting .cpu 36 and .arch directives. */ 37 38 #define ASM_CPU_SPEC "\ 39 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \ 40 %{m68020-40:-m68040}%{m68020-60:-m68040}\ 41 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\ 42 " 43 #define ASM_PCREL_SPEC "%{" FPIE_OR_FPIC_SPEC ":--pcrel} \ 44 %{mpcrel:%{" NO_FPIE_AND_FPIC_SPEC ":--pcrel}} \ 45 %{msep-data|mid-shared-library:--pcrel} \ 46 " 47 48 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)" 49 50 #define EXTRA_SPECS \ 51 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 52 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \ 53 SUBTARGET_EXTRA_SPECS 54 55 #define SUBTARGET_EXTRA_SPECS 56 57 /* Note that some other tm.h files include this one and then override 58 many of the definitions that relate to assembler syntax. */ 59 60 #define TARGET_CPU_CPP_BUILTINS() \ 61 do \ 62 { \ 63 builtin_define ("__m68k__"); \ 64 builtin_define_std ("mc68000"); \ 65 /* The other mc680x0 macros have traditionally been derived \ 66 from the tuning setting. For example, -m68020-60 defines \ 67 m68060, even though it generates pure 68020 code. */ \ 68 switch (m68k_tune) \ 69 { \ 70 case u68010: \ 71 builtin_define_std ("mc68010"); \ 72 break; \ 73 \ 74 case u68020: \ 75 builtin_define_std ("mc68020"); \ 76 break; \ 77 \ 78 case u68030: \ 79 builtin_define_std ("mc68030"); \ 80 break; \ 81 \ 82 case u68040: \ 83 builtin_define_std ("mc68040"); \ 84 break; \ 85 \ 86 case u68060: \ 87 builtin_define_std ("mc68060"); \ 88 break; \ 89 \ 90 case u68020_60: \ 91 builtin_define_std ("mc68060"); \ 92 /* Fall through. */ \ 93 case u68020_40: \ 94 builtin_define_std ("mc68040"); \ 95 builtin_define_std ("mc68030"); \ 96 builtin_define_std ("mc68020"); \ 97 break; \ 98 \ 99 case ucpu32: \ 100 builtin_define_std ("mc68332"); \ 101 builtin_define_std ("mcpu32"); \ 102 builtin_define_std ("mc68020"); \ 103 break; \ 104 \ 105 case ucfv1: \ 106 builtin_define ("__mcfv1__"); \ 107 break; \ 108 \ 109 case ucfv2: \ 110 builtin_define ("__mcfv2__"); \ 111 break; \ 112 \ 113 case ucfv3: \ 114 builtin_define ("__mcfv3__"); \ 115 break; \ 116 \ 117 case ucfv4: \ 118 builtin_define ("__mcfv4__"); \ 119 break; \ 120 \ 121 case ucfv4e: \ 122 builtin_define ("__mcfv4e__"); \ 123 break; \ 124 \ 125 case ucfv5: \ 126 builtin_define ("__mcfv5__"); \ 127 break; \ 128 \ 129 default: \ 130 break; \ 131 } \ 132 \ 133 if (TARGET_68881) \ 134 builtin_define ("__HAVE_68881__"); \ 135 \ 136 if (TARGET_COLDFIRE) \ 137 { \ 138 const char *tmp; \ 139 \ 140 tmp = m68k_cpp_cpu_ident ("cf"); \ 141 if (tmp) \ 142 builtin_define (tmp); \ 143 tmp = m68k_cpp_cpu_family ("cf"); \ 144 if (tmp) \ 145 builtin_define (tmp); \ 146 builtin_define ("__mcoldfire__"); \ 147 \ 148 if (TARGET_ISAC) \ 149 builtin_define ("__mcfisac__"); \ 150 else if (TARGET_ISAB) \ 151 { \ 152 builtin_define ("__mcfisab__"); \ 153 /* ISA_B: Legacy 5407 defines. */ \ 154 builtin_define ("__mcf5400__"); \ 155 builtin_define ("__mcf5407__"); \ 156 } \ 157 else if (TARGET_ISAAPLUS) \ 158 { \ 159 builtin_define ("__mcfisaaplus__"); \ 160 /* ISA_A+: legacy defines. */ \ 161 builtin_define ("__mcf528x__"); \ 162 builtin_define ("__mcf5200__"); \ 163 } \ 164 else \ 165 { \ 166 builtin_define ("__mcfisaa__"); \ 167 /* ISA_A: legacy defines. */ \ 168 switch (m68k_tune) \ 169 { \ 170 case ucfv2: \ 171 builtin_define ("__mcf5200__"); \ 172 break; \ 173 \ 174 case ucfv3: \ 175 builtin_define ("__mcf5307__"); \ 176 builtin_define ("__mcf5300__"); \ 177 break; \ 178 \ 179 default: \ 180 break; \ 181 } \ 182 } \ 183 } \ 184 \ 185 if (TARGET_COLDFIRE_FPU) \ 186 builtin_define ("__mcffpu__"); \ 187 \ 188 if (TARGET_CF_HWDIV) \ 189 builtin_define ("__mcfhwdiv__"); \ 190 \ 191 if (TARGET_FIDOA) \ 192 builtin_define ("__mfido__"); \ 193 \ 194 builtin_assert ("cpu=m68k"); \ 195 builtin_assert ("machine=m68k"); \ 196 } \ 197 while (0) 198 199 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI 200 quantities. */ 201 #define INT_OP_STANDARD 0 /* .byte, .short, .long */ 202 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ 203 #define INT_OP_NO_DOT 2 /* byte, short, long */ 204 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ 205 206 /* Set the default. */ 207 #define INT_OP_GROUP INT_OP_DOT_WORD 208 209 /* Bit values used by m68k-devices.def to identify processor capabilities. */ 210 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */ 211 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */ 212 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */ 213 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */ 214 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */ 215 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */ 216 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */ 217 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */ 218 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */ 219 #define FL_ISA_68000 (1 << 9) 220 #define FL_ISA_68010 (1 << 10) 221 #define FL_ISA_68020 (1 << 11) 222 #define FL_ISA_68040 (1 << 12) 223 #define FL_ISA_A (1 << 13) 224 #define FL_ISA_APLUS (1 << 14) 225 #define FL_ISA_B (1 << 15) 226 #define FL_ISA_C (1 << 16) 227 #define FL_FIDOA (1 << 17) 228 #define FL_CAS (1 << 18) /* Support cas insn. */ 229 #define FL_MMU 0 /* Used by multilib machinery. */ 230 #define FL_UCLINUX 0 /* Used by multilib machinery. */ 231 232 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) 233 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) 234 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0) 235 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) 236 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) 237 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881) 238 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0) 239 #define TARGET_CAS ((m68k_cpu_flags & FL_CAS) != 0) 240 241 /* Size (in bytes) of FPU registers. */ 242 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) 243 244 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0) 245 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) 246 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) 247 248 /* Some instructions are common to more than one ISA. */ 249 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC) 250 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC) 251 #define ISA_HAS_TAS (!TARGET_COLDFIRE || TARGET_ISAB || TARGET_ISAC) 252 253 #define TUNE_68000 (m68k_tune == u68000) 254 #define TUNE_68010 (m68k_tune == u68010) 255 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010) 256 #define TUNE_68030 (m68k_tune == u68030 \ 257 || m68k_tune == u68020_40 \ 258 || m68k_tune == u68020_60) 259 #define TUNE_68040 (m68k_tune == u68040 \ 260 || m68k_tune == u68020_40 \ 261 || m68k_tune == u68020_60) 262 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60) 263 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060) 264 #define TUNE_CPU32 (m68k_tune == ucpu32) 265 #define TUNE_CFV1 (m68k_tune == ucfv1) 266 #define TUNE_CFV2 (m68k_tune == ucfv2) 267 #define TUNE_CFV3 (m68k_tune == ucfv3) 268 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e) 269 270 #define TUNE_MAC ((m68k_tune_flags & FL_CF_MAC) != 0) 271 #define TUNE_EMAC ((m68k_tune_flags & FL_CF_EMAC) != 0) 272 273 /* These are meant to be redefined in the host dependent files */ 274 #define SUBTARGET_OVERRIDE_OPTIONS 275 276 /* target machine storage layout */ 277 278 /* "long double" is the same as "double" on ColdFire and fido 279 targets. */ 280 281 #define LONG_DOUBLE_TYPE_SIZE \ 282 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80) 283 284 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp 285 instructions, we get proper intermediate rounding, otherwise we 286 get extended precision results. */ 287 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2) 288 289 #define BITS_BIG_ENDIAN 1 290 #define BYTES_BIG_ENDIAN 1 291 #define WORDS_BIG_ENDIAN 1 292 293 #define UNITS_PER_WORD 4 294 295 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 296 #define STACK_BOUNDARY 16 297 #define FUNCTION_BOUNDARY 16 298 #define EMPTY_FIELD_BOUNDARY 16 299 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */ 300 #define PREFERRED_STACK_BOUNDARY \ 301 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16) 302 303 /* No data type wants to be aligned rounder than this. 304 Most published ABIs say that ints should be aligned on 16-bit 305 boundaries, but CPUs with 32-bit busses get better performance 306 aligned on 32-bit boundaries. */ 307 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) 308 309 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) 310 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1 311 312 #define DWARF_CIE_DATA_ALIGNMENT -2 313 314 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 315 316 /* Define these to avoid dependence on meaning of `int'. */ 317 #define WCHAR_TYPE "long int" 318 #define WCHAR_TYPE_SIZE 32 319 320 /* Maximum number of library IDs we permit with -mid-shared-library. */ 321 #define MAX_LIBRARY_ID 255 322 323 324 /* Standard register usage. */ 325 326 /* For the m68k, we give the data registers numbers 0-7, 327 the address registers numbers 010-017 (8-15), 328 and the 68881 floating point registers numbers 020-027 (16-23). 329 We also have a fake `arg-pointer' register 030 (24) used for 330 register elimination. */ 331 #define FIRST_PSEUDO_REGISTER 25 332 333 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */ 334 #define PIC_OFFSET_TABLE_REGNUM \ 335 (!flag_pic ? INVALID_REGNUM \ 336 : reload_completed ? REGNO (pic_offset_table_rtx) \ 337 : PIC_REG) 338 339 /* 1 for registers that have pervasive standard uses 340 and are not available for the register allocator. 341 On the m68k, only the stack pointer is such. 342 Our fake arg-pointer is obviously fixed as well. */ 343 #define FIXED_REGISTERS \ 344 {/* Data registers. */ \ 345 0, 0, 0, 0, 0, 0, 0, 0, \ 346 \ 347 /* Address registers. */ \ 348 0, 0, 0, 0, 0, 0, 0, 1, \ 349 \ 350 /* Floating point registers \ 351 (if available). */ \ 352 0, 0, 0, 0, 0, 0, 0, 0, \ 353 \ 354 /* Arg pointer. */ \ 355 1 } 356 357 /* 1 for registers not available across function calls. 358 These must include the FIXED_REGISTERS and also any 359 registers that can be used without being saved. 360 The latter must include the registers where values are returned 361 and the register where structure-value addresses are passed. 362 Aside from that, you can include as many other registers as you like. */ 363 #define CALL_USED_REGISTERS \ 364 {/* Data registers. */ \ 365 1, 1, 0, 0, 0, 0, 0, 0, \ 366 \ 367 /* Address registers. */ \ 368 1, 1, 0, 0, 0, 0, 0, 1, \ 369 \ 370 /* Floating point registers \ 371 (if available). */ \ 372 1, 1, 0, 0, 0, 0, 0, 0, \ 373 \ 374 /* Arg pointer. */ \ 375 1 } 376 377 #define REG_ALLOC_ORDER \ 378 { /* d0/d1/a0/a1 */ \ 379 0, 1, 8, 9, \ 380 /* d2-d7 */ \ 381 2, 3, 4, 5, 6, 7, \ 382 /* a2-a7/arg */ \ 383 10, 11, 12, 13, 14, 15, 24, \ 384 /* fp0-fp7 */ \ 385 16, 17, 18, 19, 20, 21, 22, 23\ 386 } 387 388 389 /* On the m68k, ordinary registers hold 32 bits worth; 390 for the 68881 registers, a single register is always enough for 391 anything that can be stored in them at all. */ 392 #define HARD_REGNO_NREGS(REGNO, MODE) \ 393 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 394 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 395 396 /* A C expression that is nonzero if hard register NEW_REG can be 397 considered for use as a rename register for OLD_REG register. */ 398 399 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 400 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) 401 402 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 403 m68k_regno_mode_ok ((REGNO), (MODE)) 404 405 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 406 m68k_secondary_reload_class (CLASS, MODE, X) 407 408 #define MODES_TIEABLE_P(MODE1, MODE2) \ 409 (! TARGET_HARD_FLOAT \ 410 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 411 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 412 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 413 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) 414 415 /* Specify the registers used for certain standard purposes. 416 The values of these macros are register numbers. */ 417 418 #define STACK_POINTER_REGNUM SP_REG 419 420 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS 421 ABI uses %a6 for shared library calls, therefore the frame 422 pointer is shifted to %a5 on this target. */ 423 #define FRAME_POINTER_REGNUM A6_REG 424 425 /* Base register for access to arguments of the function. 426 * This isn't a hardware register. It will be eliminated to the 427 * stack pointer or frame pointer. 428 */ 429 #define ARG_POINTER_REGNUM 24 430 431 #define STATIC_CHAIN_REGNUM A0_REG 432 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0" 433 434 /* Register in which address to store a structure value 435 is passed to a function. */ 436 #define M68K_STRUCT_VALUE_REGNUM A1_REG 437 438 439 440 /* The m68k has three kinds of registers, so eight classes would be 441 a complete set. One of them is not needed. */ 442 enum reg_class { 443 NO_REGS, DATA_REGS, 444 ADDR_REGS, FP_REGS, 445 GENERAL_REGS, DATA_OR_FP_REGS, 446 ADDR_OR_FP_REGS, ALL_REGS, 447 LIM_REG_CLASSES }; 448 449 #define N_REG_CLASSES (int) LIM_REG_CLASSES 450 451 #define REG_CLASS_NAMES \ 452 { "NO_REGS", "DATA_REGS", \ 453 "ADDR_REGS", "FP_REGS", \ 454 "GENERAL_REGS", "DATA_OR_FP_REGS", \ 455 "ADDR_OR_FP_REGS", "ALL_REGS" } 456 457 #define REG_CLASS_CONTENTS \ 458 { \ 459 {0x00000000}, /* NO_REGS */ \ 460 {0x000000ff}, /* DATA_REGS */ \ 461 {0x0100ff00}, /* ADDR_REGS */ \ 462 {0x00ff0000}, /* FP_REGS */ \ 463 {0x0100ffff}, /* GENERAL_REGS */ \ 464 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ 465 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \ 466 {0x01ffffff}, /* ALL_REGS */ \ 467 } 468 469 extern enum reg_class regno_reg_class[]; 470 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)]) 471 #define INDEX_REG_CLASS GENERAL_REGS 472 #define BASE_REG_CLASS ADDR_REGS 473 474 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 475 m68k_preferred_reload_class (X, CLASS) 476 477 /* On the m68k, this is the size of MODE in words, 478 except in the FP regs, where a single reg is always enough. */ 479 #define CLASS_MAX_NREGS(CLASS, MODE) \ 480 ((CLASS) == FP_REGS ? 1 \ 481 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 482 483 /* Moves between fp regs and other regs are two insns. */ 484 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 485 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) 486 487 488 /* Stack layout; function entry, exit and calling. */ 489 490 #define STACK_GROWS_DOWNWARD 1 491 #define FRAME_GROWS_DOWNWARD 1 492 #define STARTING_FRAME_OFFSET 0 493 494 /* On the 680x0, sp@- in a byte insn really pushes a word. 495 On the ColdFire, sp@- in a byte insn pushes just a byte. */ 496 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) 497 498 #define FIRST_PARM_OFFSET(FNDECL) 8 499 500 /* On the m68k the return value defaults to D0. */ 501 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 502 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG) 503 504 /* On the m68k the return value defaults to D0. */ 505 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG) 506 507 /* On the m68k, D0 is usually the only register used. */ 508 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG) 509 510 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 511 more than one register. 512 XXX This macro is m68k specific and used only for m68kemb.h. */ 513 #define NEEDS_UNTYPED_CALL 0 514 515 /* On the m68k, all arguments are usually pushed on the stack. */ 516 #define FUNCTION_ARG_REGNO_P(N) 0 517 518 /* On the m68k, this is a single integer, which is a number of bytes 519 of arguments scanned so far. */ 520 #define CUMULATIVE_ARGS int 521 522 /* On the m68k, the offset starts at 0. */ 523 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 524 ((CUM) = 0) 525 526 #define FUNCTION_PROFILER(FILE, LABELNO) \ 527 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) 528 529 #define EXIT_IGNORE_STACK 1 530 531 /* Output assembler code for a block containing the constant parts 532 of a trampoline, leaving space for the variable parts. 533 534 On the m68k, the trampoline looks like this: 535 movl #STATIC,a0 536 jmp FUNCTION 537 538 WARNING: Targets that may run on 68040+ cpus must arrange for 539 the instruction cache to be flushed. Previous incarnations of 540 the m68k trampoline code attempted to get around this by either 541 using an out-of-line transfer function or pc-relative data, but 542 the fact remains that the code to jump to the transfer function 543 or the code to load the pc-relative data needs to be flushed 544 just as much as the "variable" portion of the trampoline. 545 Recognizing that a cache flush is going to be required anyway, 546 dispense with such notions and build a smaller trampoline. 547 548 Since more instructions are required to move a template into 549 place than to create it on the spot, don't use a template. */ 550 551 #define TRAMPOLINE_SIZE 12 552 #define TRAMPOLINE_ALIGNMENT 16 553 554 /* Targets redefine this to invoke code to either flush the cache, 555 or enable stack execution (or both). */ 556 #ifndef FINALIZE_TRAMPOLINE 557 #define FINALIZE_TRAMPOLINE(TRAMP) 558 #endif 559 560 /* This is the library routine that is used to transfer control from the 561 trampoline to the actual nested function. It is defined for backward 562 compatibility, for linking with object code that used the old trampoline 563 definition. 564 565 A colon is used with no explicit operands to cause the template string 566 to be scanned for %-constructs. 567 568 The function name __transfer_from_trampoline is not actually used. 569 The function definition just permits use of "asm with operands" 570 (though the operand list is empty). */ 571 #define TRANSFER_FROM_TRAMPOLINE \ 572 void \ 573 __transfer_from_trampoline () \ 574 { \ 575 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \ 576 asm (GLOBAL_ASM_OP "___trampoline"); \ 577 asm ("___trampoline:"); \ 578 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ 579 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ 580 asm ("rts":); \ 581 } 582 583 /* There are two registers that can always be eliminated on the m68k. 584 The frame pointer and the arg pointer can be replaced by either the 585 hard frame pointer or to the stack pointer, depending upon the 586 circumstances. The hard frame pointer is not used before reload and 587 so it is not eligible for elimination. */ 588 #define ELIMINABLE_REGS \ 589 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 590 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ 591 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} 592 593 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 594 (OFFSET) = m68k_initial_elimination_offset(FROM, TO) 595 596 /* Addressing modes, and classification of registers for them. */ 597 598 #define HAVE_POST_INCREMENT 1 599 #define HAVE_PRE_DECREMENT 1 600 601 /* Macros to check register numbers against specific register classes. */ 602 603 /* True for data registers, D0 through D7. */ 604 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7) 605 606 /* True for address registers, A0 through A7. */ 607 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15) 608 609 /* True for integer registers, D0 through D7 and A0 through A7. */ 610 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15) 611 612 /* True for floating point registers, FP0 through FP7. */ 613 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23) 614 615 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 616 (INT_REGNO_P (REGNO) \ 617 || INT_REGNO_P (reg_renumber[REGNO])) 618 619 #define REGNO_OK_FOR_BASE_P(REGNO) \ 620 (ADDRESS_REGNO_P (REGNO) \ 621 || ADDRESS_REGNO_P (reg_renumber[REGNO])) 622 623 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ 624 (INT_REGNO_P (REGNO) \ 625 || REGNO == ARG_POINTER_REGNUM \ 626 || REGNO >= FIRST_PSEUDO_REGISTER) 627 628 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ 629 (ADDRESS_REGNO_P (REGNO) \ 630 || REGNO == ARG_POINTER_REGNUM \ 631 || REGNO >= FIRST_PSEUDO_REGISTER) 632 633 /* Now macros that check whether X is a register and also, 634 strictly, whether it is in a specified class. 635 636 These macros are specific to the m68k, and may be used only 637 in code for printing assembler insns and in conditions for 638 define_optimization. */ 639 640 /* 1 if X is a data register. */ 641 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X))) 642 643 /* 1 if X is an fp register. */ 644 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 645 646 /* 1 if X is an address register */ 647 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X))) 648 649 /* True if SYMBOL + OFFSET constants must refer to something within 650 SYMBOL's section. */ 651 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 652 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 653 #endif 654 655 #define MAX_REGS_PER_ADDRESS 2 656 657 #define CONSTANT_ADDRESS_P(X) \ 658 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 659 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 660 || GET_CODE (X) == HIGH) \ 661 && m68k_legitimate_constant_p (Pmode, X)) 662 663 #ifndef REG_OK_STRICT 664 #define REG_STRICT_P 0 665 #else 666 #define REG_STRICT_P 1 667 #endif 668 669 #define LEGITIMATE_PIC_OPERAND_P(X) \ 670 (!symbolic_operand (X, VOIDmode) \ 671 || (TARGET_PCREL && REG_STRICT_P) \ 672 || m68k_tls_reference_p (X, true)) 673 674 #define REG_OK_FOR_BASE_P(X) \ 675 m68k_legitimate_base_reg_p (X, REG_STRICT_P) 676 677 #define REG_OK_FOR_INDEX_P(X) \ 678 m68k_legitimate_index_reg_p (X, REG_STRICT_P) 679 680 681 /* This address is OK as it stands. */ 682 #define PIC_CASE_VECTOR_ADDRESS(index) index 683 #define CASE_VECTOR_MODE HImode 684 #define CASE_VECTOR_PC_RELATIVE 1 685 686 #define DEFAULT_SIGNED_CHAR 1 687 #define MOVE_MAX 4 688 #define SLOW_BYTE_ACCESS 0 689 690 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 691 692 /* The 68020 BFFFO and ColdFire FF1 instructions return 32 for zero. */ 693 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 694 695 #define STORE_FLAG_VALUE (-1) 696 697 #define Pmode SImode 698 #define FUNCTION_MODE QImode 699 700 701 /* Tell final.c how to eliminate redundant test instructions. */ 702 703 /* Here we define machine-dependent flags and fields in cc_status 704 (see `conditions.h'). */ 705 706 /* Set if the cc value is actually in the 68881, so a floating point 707 conditional branch must be output. */ 708 #define CC_IN_68881 04000 709 710 /* On the 68000, all the insns to store in an address register fail to 711 set the cc's. However, in some cases these instructions can make it 712 possibly invalid to use the saved cc's. In those cases we clear out 713 some or all of the saved cc's so they won't be used. */ 714 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) 715 716 /* The shift instructions always clear the overflow bit. */ 717 #define CC_OVERFLOW_UNUSABLE 01000 718 719 /* The shift instructions use the carry bit in a way not compatible with 720 conditional branches. conditions.h uses CC_NO_OVERFLOW for this purpose. 721 Rename it to something more understandable. */ 722 #define CC_NO_CARRY CC_NO_OVERFLOW 723 724 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 725 do { if (cc_prev_status.flags & CC_IN_68881) \ 726 return FLOAT; \ 727 if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 728 return NO_OV; \ 729 return NORMAL; } while (0) 730 731 /* Control the assembler format that we output. */ 732 733 #define ASM_APP_ON "#APP\n" 734 #define ASM_APP_OFF "#NO_APP\n" 735 #define TEXT_SECTION_ASM_OP "\t.text" 736 #define DATA_SECTION_ASM_OP "\t.data" 737 #define GLOBAL_ASM_OP "\t.globl\t" 738 #define REGISTER_PREFIX "" 739 #define LOCAL_LABEL_PREFIX "" 740 #define USER_LABEL_PREFIX "_" 741 #define IMMEDIATE_PREFIX "#" 742 743 #define REGISTER_NAMES \ 744 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \ 745 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \ 746 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \ 747 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \ 748 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \ 749 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \ 750 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \ 751 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \ 752 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" } 753 754 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp" 755 756 /* Return a register name by index, handling %fp nicely. 757 We don't replace %fp for targets that don't map it to %a6 758 since it may confuse GAS. */ 759 #define M68K_REGNAME(r) ( \ 760 ((FRAME_POINTER_REGNUM == A6_REG) \ 761 && ((r) == FRAME_POINTER_REGNUM) \ 762 && frame_pointer_needed) ? \ 763 M68K_FP_REG_NAME : reg_names[(r)]) 764 765 /* On the Sun-3, the floating point registers have numbers 766 18 to 25, not 16 to 23 as they do in the compiler. */ 767 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 768 769 /* Before the prologue, RA is at 0(%sp). */ 770 #define INCOMING_RETURN_ADDR_RTX \ 771 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 772 773 /* After the prologue, RA is at 4(AP) in the current frame. */ 774 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 775 ((COUNT) == 0 \ 776 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 777 UNITS_PER_WORD)) \ 778 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) 779 780 /* We must not use the DBX register numbers for the DWARF 2 CFA column 781 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 782 Instead use the identity mapping. */ 783 #define DWARF_FRAME_REGNUM(REG) \ 784 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM) 785 786 /* The return column was originally 24, but gcc used 25 for a while too. 787 Define both registers 24 and 25 as Pmode ones and use 24 in our own 788 unwind information. */ 789 #define DWARF_FRAME_REGISTERS 25 790 #define DWARF_FRAME_RETURN_COLUMN 24 791 #define DWARF_ALT_FRAME_RETURN_COLUMN 25 792 793 /* Before the prologue, the top of the frame is at 4(%sp). */ 794 #define INCOMING_FRAME_SP_OFFSET 4 795 796 #define EPILOGUE_USES(REGNO) m68k_epilogue_uses (REGNO) 797 798 /* Describe how we implement __builtin_eh_return. */ 799 #define EH_RETURN_DATA_REGNO(N) \ 800 ((N) < 2 ? (N) : INVALID_REGNUM) 801 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG) 802 #define EH_RETURN_HANDLER_RTX \ 803 gen_rtx_MEM (Pmode, \ 804 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ 805 plus_constant (Pmode, EH_RETURN_STACKADJ_RTX, \ 806 UNITS_PER_WORD))) 807 808 /* Select a format to encode pointers in exception handling data. CODE 809 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 810 true if the symbol may be affected by dynamic relocations. 811 812 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support 813 a read-only text segment without imposing a fixed gap between the 814 text and data segments. As a result, the text segment cannot refer 815 to anything in the data segment, even in PC-relative form. Because 816 .eh_frame refers to both code and data, it follows that .eh_frame 817 must be in the data segment itself, and that the offset between 818 .eh_frame and code will not be a link-time constant. 819 820 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel 821 | DW_EH_PE_indirect for all code references. However, gcc currently 822 handles indirect references using a per-TU constant pool. This means 823 that if a function and its eh_frame are removed by the linker, the 824 eh_frame's indirect references to the removed function will not be 825 removed, leading to an unresolved symbol error. 826 827 It isn't clear that any -msep-data or -mid-shared-library target 828 would benefit from a read-only .eh_frame anyway. In particular, 829 no known target that supports these options has a feature like 830 PT_GNU_RELRO. Without any such feature to motivate them, indirect 831 references would be unnecessary bloat, so we simply use an absolute 832 pointer for code and global references. We still use pc-relative 833 references to data, as this avoids a relocation. */ 834 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 835 (flag_pic \ 836 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \ 837 && ((GLOBAL) || (CODE))) \ 838 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 839 : DW_EH_PE_absptr) 840 841 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 842 asm_fprintf (FILE, "%U%s", NAME) 843 844 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 845 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) 846 847 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 848 asm_fprintf (FILE, (MOTOROLA \ 849 ? "\tmove.l %s,-(%Rsp)\n" \ 850 : "\tmovel %s,%Rsp@-\n"), \ 851 reg_names[REGNO]) 852 853 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 854 asm_fprintf (FILE, (MOTOROLA \ 855 ? "\tmove.l (%Rsp)+,%s\n" \ 856 : "\tmovel %Rsp@+,%s\n"), \ 857 reg_names[REGNO]) 858 859 /* The m68k does not use absolute case-vectors, but we must define this macro 860 anyway. */ 861 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 862 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) 863 864 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 865 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) 866 867 /* We don't have a way to align to more than a two-byte boundary, so do the 868 best we can and don't complain. */ 869 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 870 if ((LOG) >= 1) \ 871 fprintf (FILE, "\t.even\n"); 872 873 #ifdef HAVE_GAS_BALIGN_AND_P2ALIGN 874 /* Use "move.l %a4,%a4" to advance within code. */ 875 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ 876 if ((LOG) > 0) \ 877 fprintf ((FILE), "\t.balignw %u,0x284c\n", 1 << (LOG)); 878 #endif 879 880 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 881 fprintf (FILE, "\t.skip %u\n", (int)(SIZE)) 882 883 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 884 ( fputs (".comm ", (FILE)), \ 885 assemble_name ((FILE), (NAME)), \ 886 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 887 888 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 889 ( fputs (".lcomm ", (FILE)), \ 890 assemble_name ((FILE), (NAME)), \ 891 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 892 893 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 894 m68k_final_prescan_insn (INSN, OPVEC, NOPERANDS) 895 896 /* On the 68000, we use several CODE characters: 897 '.' for dot needed in Motorola-style opcode names. 898 '-' for an operand pushing on the stack: 899 sp@-, -(sp) or -(%sp) depending on the style of syntax. 900 '+' for an operand pushing on the stack: 901 sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 902 '@' for a reference to the top word on the stack: 903 sp@, (sp) or (%sp) depending on the style of syntax. 904 '#' for an immediate operand prefix (# in MIT and Motorola syntax 905 but & in SGS syntax). 906 '!' for the fpcr register (used in some float-to-fixed conversions). 907 '$' for the letter `s' in an op code, but only on the 68040. 908 '&' for the letter `d' in an op code, but only on the 68040. 909 '/' for register prefix needed by longlong.h. 910 '?' for m68k_library_id_string 911 912 'b' for byte insn (no effect, on the Sun; this is for the ISI). 913 'd' to force memory addressing to be absolute, not relative. 914 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 915 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 916 or print pair of registers as rx:ry. */ 917 918 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 919 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 920 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ 921 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?') 922 923 924 /* See m68k.c for the m68k specific codes. */ 925 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 926 927 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 928 929 #include "config/m68k/m68k-opts.h" 930 931 enum fpu_type 932 { 933 FPUTYPE_NONE, 934 FPUTYPE_68881, 935 FPUTYPE_COLDFIRE 936 }; 937 938 enum m68k_function_kind 939 { 940 m68k_fk_normal_function, 941 m68k_fk_interrupt_handler, 942 m68k_fk_interrupt_thread 943 }; 944 945 /* Variables in m68k.c; see there for details. */ 946 extern enum target_device m68k_cpu; 947 extern enum uarch_type m68k_tune; 948 extern enum fpu_type m68k_fpu; 949 extern unsigned int m68k_cpu_flags; 950 extern unsigned int m68k_tune_flags; 951 extern const char *m68k_symbolic_call; 952 extern const char *m68k_symbolic_jump; 953 954 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR, 955 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P }; 956 957 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; 958 959 /* ??? HOST_WIDE_INT is not being defined for auto-generated files. 960 Workaround that. */ 961 #ifdef HOST_WIDE_INT 962 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } 963 M68K_CONST_METHOD; 964 965 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT); 966 #endif 967 968 extern void m68k_emit_move_double (rtx [2]); 969 970 extern int m68k_sched_address_bypass_p (rtx_insn *, rtx_insn *); 971 extern int m68k_sched_indexed_address_bypass_p (rtx_insn *, rtx_insn *); 972 973 #define CPU_UNITS_QUERY 1 974