1; Options for the SH port of the compiler.
2
3; Copyright (C) 2005-2016 Free Software Foundation, Inc.
4;
5; This file is part of GCC.
6;
7; GCC is free software; you can redistribute it and/or modify it under
8; the terms of the GNU General Public License as published by the Free
9; Software Foundation; either version 3, or (at your option) any later
10; version.
11;
12; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13; WARRANTY; without even the implied warranty of MERCHANTABILITY or
14; FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
15; for more details.
16;
17; You should have received a copy of the GNU General Public License
18; along with GCC; see the file COPYING3.  If not see
19; <http://www.gnu.org/licenses/>.
20
21;; Used for various architecture options.
22Mask(SH_E)
23
24;; Set if the default precision of the FPU is single.
25Mask(FPU_SINGLE)
26
27;; Set if the a double-precision FPU is present but is restricted to
28;; single precision usage only.
29Mask(FPU_SINGLE_ONLY)
30
31;; Set if we should generate code using type 2A insns.
32Mask(HARD_SH2A)
33
34;; Set if we should generate code using type 2A DF insns.
35Mask(HARD_SH2A_DOUBLE)
36
37;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
38Mask(HARD_SH4)
39
40;; Set if we should generate code for a SH5 CPU (either ISA).
41Mask(SH5)
42
43;; Set if we should save all target registers.
44Mask(SAVE_ALL_TARGET_REGS)
45
46m1
47Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
48Generate SH1 code.
49
50m2
51Target RejectNegative Mask(SH2) Condition(SUPPORT_SH2)
52Generate SH2 code.
53
54m2a
55Target RejectNegative Condition(SUPPORT_SH2A)
56Generate default double-precision SH2a-FPU code.
57
58m2a-nofpu
59Target RejectNegative Condition(SUPPORT_SH2A_NOFPU)
60Generate SH2a FPU-less code.
61
62m2a-single
63Target RejectNegative Condition(SUPPORT_SH2A_SINGLE)
64Generate default single-precision SH2a-FPU code.
65
66m2a-single-only
67Target RejectNegative Condition(SUPPORT_SH2A_SINGLE_ONLY)
68Generate only single-precision SH2a-FPU code.
69
70m2e
71Target RejectNegative Condition(SUPPORT_SH2E)
72Generate SH2e code.
73
74m3
75Target RejectNegative Mask(SH3) Condition(SUPPORT_SH3)
76Generate SH3 code.
77
78m3e
79Target RejectNegative Condition(SUPPORT_SH3E)
80Generate SH3e code.
81
82m4
83Target RejectNegative Mask(SH4) Condition(SUPPORT_SH4)
84Generate SH4 code.
85
86m4-100
87Target RejectNegative Condition(SUPPORT_SH4)
88Generate SH4-100 code.
89
90m4-200
91Target RejectNegative Condition(SUPPORT_SH4)
92Generate SH4-200 code.
93
94;; TARGET_SH4_300 indicates if we have the ST40-300 instruction set and
95;; pipeline - irrespective of ABI.
96m4-300
97Target RejectNegative Condition(SUPPORT_SH4) Var(TARGET_SH4_300)
98Generate SH4-300 code.
99
100m4-nofpu
101Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
102Generate SH4 FPU-less code.
103
104m4-100-nofpu
105Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
106Generate SH4-100 FPU-less code.
107
108m4-200-nofpu
109Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
110Generate SH4-200 FPU-less code.
111
112m4-300-nofpu
113Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300)
114Generate SH4-300 FPU-less code.
115
116m4-340
117Target RejectNegative Condition(SUPPORT_SH4_NOFPU) Var(TARGET_SH4_300)
118Generate code for SH4 340 series (MMU/FPU-less).
119;; passes -isa=sh4-nommu-nofpu to the assembler.
120
121m4-400
122Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
123Generate code for SH4 400 series (MMU/FPU-less).
124;; passes -isa=sh4-nommu-nofpu to the assembler.
125
126m4-500
127Target RejectNegative Condition(SUPPORT_SH4_NOFPU)
128Generate code for SH4 500 series (FPU-less).
129;; passes -isa=sh4-nofpu to the assembler.
130
131m4-single
132Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
133Generate default single-precision SH4 code.
134
135m4-100-single
136Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
137Generate default single-precision SH4-100 code.
138
139m4-200-single
140Target RejectNegative Condition(SUPPORT_SH4_SINGLE)
141Generate default single-precision SH4-200 code.
142
143m4-300-single
144Target RejectNegative Condition(SUPPORT_SH4_SINGLE) Var(TARGET_SH4_300)
145Generate default single-precision SH4-300 code.
146
147m4-single-only
148Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
149Generate only single-precision SH4 code.
150
151m4-100-single-only
152Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
153Generate only single-precision SH4-100 code.
154
155m4-200-single-only
156Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY)
157Generate only single-precision SH4-200 code.
158
159m4-300-single-only
160Target RejectNegative Condition(SUPPORT_SH4_SINGLE_ONLY) Var(TARGET_SH4_300)
161Generate only single-precision SH4-300 code.
162
163m4a
164Target RejectNegative Mask(SH4A) Condition(SUPPORT_SH4A)
165Generate SH4a code.
166
167m4a-nofpu
168Target RejectNegative Condition(SUPPORT_SH4A_NOFPU)
169Generate SH4a FPU-less code.
170
171m4a-single
172Target RejectNegative Condition(SUPPORT_SH4A_SINGLE)
173Generate default single-precision SH4a code.
174
175m4a-single-only
176Target RejectNegative Condition(SUPPORT_SH4A_SINGLE_ONLY)
177Generate only single-precision SH4a code.
178
179m4al
180Target RejectNegative Condition(SUPPORT_SH4AL)
181Generate SH4al-dsp code.
182
183m5-32media
184Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
185Generate 32-bit SHmedia code.
186
187m5-32media-nofpu
188Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
189Generate 32-bit FPU-less SHmedia code.
190
191m5-64media
192Target RejectNegative Condition(SUPPORT_SH5_64MEDIA)
193Generate 64-bit SHmedia code.
194
195m5-64media-nofpu
196Target RejectNegative Condition(SUPPORT_SH5_64MEDIA_NOFPU)
197Generate 64-bit FPU-less SHmedia code.
198
199m5-compact
200Target RejectNegative Condition(SUPPORT_SH5_32MEDIA)
201Generate SHcompact code.
202
203m5-compact-nofpu
204Target RejectNegative Condition(SUPPORT_SH5_32MEDIA_NOFPU)
205Generate FPU-less SHcompact code.
206
207maccumulate-outgoing-args
208Target Report Var(TARGET_ACCUMULATE_OUTGOING_ARGS) Init(1)
209Reserve space for outgoing arguments in the function prologue.
210
211madjust-unroll
212Target Ignore
213Does nothing.  Preserved for backward compatibility.
214
215mb
216Target Report RejectNegative InverseMask(LITTLE_ENDIAN)
217Generate code in big endian mode.
218
219mbigtable
220Target Report RejectNegative Mask(BIGTABLE)
221Generate 32-bit offsets in switch tables.
222
223mbitops
224Target Report RejectNegative Mask(BITOPS)
225Generate bit instructions.
226
227mbranch-cost=
228Target RejectNegative Joined UInteger Var(sh_branch_cost) Init(-1)
229Cost to assume for a branch insn.
230
231mzdcbranch
232Target Report Var(TARGET_ZDCBRANCH)
233Assume that zero displacement conditional branches are fast.
234
235mcbranchdi
236Target Undocumented Var(TARGET_CBRANCHDI4) Warn(%qs is deprecated and has no effect)
237Enable cbranchdi4 pattern.
238
239mcmpeqdi
240Target Undocumented Var(TARGET_CMPEQDI_T) Warn(%qs is deprecated and has no effect)
241Emit cmpeqdi_t pattern even when -mcbranchdi is in effect.
242
243mcbranch-force-delay-slot
244Target Report RejectNegative Var(TARGET_CBRANCH_FORCE_DELAY_SLOT) Init(0)
245Force the usage of delay slots for conditional branches.
246
247mcut2-workaround
248Target RejectNegative Var(TARGET_SH5_CUT2_WORKAROUND)
249Enable SH5 cut2 workaround.
250
251mdalign
252Target Report RejectNegative Mask(ALIGN_DOUBLE)
253Align doubles at 64-bit boundaries.
254
255mdiv=
256Target RejectNegative Joined Var(sh_div_str) Init("")
257Division strategy, one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, inv:call2, inv:fp, call-div1, call-fp, call-table.
258
259mdivsi3_libfunc=
260Target RejectNegative Joined Var(sh_divsi3_libfunc) Init("")
261Specify name for 32 bit signed division function.
262
263mfdpic
264Target Report Var(TARGET_FDPIC) Init(0)
265Generate ELF FDPIC code.
266
267mfmovd
268Target RejectNegative Mask(FMOVD)
269Enable the use of 64-bit floating point registers in fmov instructions.  See -mdalign if 64-bit alignment is required.
270
271mfixed-range=
272Target RejectNegative Joined Var(sh_fixed_range_str)
273Specify range of registers to make fixed.
274
275mgettrcost=
276Target RejectNegative Joined UInteger Var(sh_gettrcost) Init(-1)
277Cost to assume for gettr insn.
278
279mhitachi
280Target Report RejectNegative Mask(HITACHI)
281Follow Renesas (formerly Hitachi) / SuperH calling conventions.
282
283mieee
284Target Var(TARGET_IEEE)
285Increase the IEEE compliance for floating-point comparisons.
286
287mindexed-addressing
288Target Report Mask(ALLOW_INDEXED_ADDRESS) Condition(SUPPORT_ANY_SH5_32MEDIA)
289Enable the use of the indexed addressing mode for SHmedia32/SHcompact.
290
291minline-ic_invalidate
292Target Report Var(TARGET_INLINE_IC_INVALIDATE)
293inline code to invalidate instruction cache entries after setting up nested function trampolines.
294
295minvalid-symbols
296Target Report Mask(INVALID_SYMBOLS) Condition(SUPPORT_ANY_SH5)
297Assume symbols might be invalid.
298
299misize
300Target Report RejectNegative Mask(DUMPISIZE)
301Annotate assembler instructions with estimated addresses.
302
303ml
304Target Report RejectNegative Mask(LITTLE_ENDIAN)
305Generate code in little endian mode.
306
307mnomacsave
308Target Report RejectNegative Mask(NOMACSAVE)
309Mark MAC register as call-clobbered.
310
311;; ??? This option is not useful, but is retained in case there are people
312;; who are still relying on it.  It may be deleted in the future.
313mpadstruct
314Target Report RejectNegative Mask(PADSTRUCT)
315Make structs a multiple of 4 bytes (warning: ABI altered).
316
317mprefergot
318Target Report RejectNegative Mask(PREFERGOT)
319Emit function-calls using global offset table when generating PIC.
320
321mpt-fixed
322Target Report Mask(PT_FIXED) Condition(SUPPORT_ANY_SH5)
323Assume pt* instructions won't trap
324
325mrelax
326Target Report RejectNegative Mask(RELAX)
327Shorten address references during linking.
328
329mrenesas
330Target Mask(HITACHI)
331Follow Renesas (formerly Hitachi) / SuperH calling conventions.
332
333msoft-atomic
334Target Undocumented Alias(matomic-model=, soft-gusa, none)
335Deprecated.  Use -matomic= instead to select the atomic model.
336
337matomic-model=
338Target Report RejectNegative Joined Var(sh_atomic_model_str)
339Specify the model for atomic operations.
340
341mtas
342Target Report RejectNegative Var(TARGET_ENABLE_TAS)
343Use tas.b instruction for __atomic_test_and_set.
344
345mspace
346Target RejectNegative Alias(Os)
347Deprecated.  Use -Os instead.
348
349multcost=
350Target RejectNegative Joined UInteger Var(sh_multcost) Init(-1)
351Cost to assume for a multiply insn.
352
353musermode
354Target Var(TARGET_USERMODE)
355Don't generate privileged-mode only code; implies -mno-inline-ic_invalidate if the inline code would not work in user mode.
356
357;; We might want to enable this by default for TARGET_HARD_SH4, because
358;; zero-offset branches have zero latency.  Needs some benchmarking.
359mpretend-cmove
360Target Var(TARGET_PRETEND_CMOVE)
361Pretend a branch-around-a-move is a conditional move.
362
363mfsca
364Target Var(TARGET_FSCA)
365Enable the use of the fsca instruction.
366
367mfsrra
368Target Var(TARGET_FSRRA)
369Enable the use of the fsrra instruction.
370
371mlra
372Target Report Var(sh_lra_flag) Init(0) Save
373Use LRA instead of reload (transitional).
374