1 /* This testcase generates MMX instructions together with x87 instructions.
2    Currently, there is no "emms" generated to switch between register sets,
3    so the testcase fails for targets where MMX insns are enabled.  */
4 /* { dg-options "-mno-mmx -Wno-psabi" { target { x86_64-*-* i?86-*-* } } } */
5 
6 extern void abort (void);
7 
8 typedef int V2SI __attribute__ ((vector_size (8)));
9 typedef unsigned int V2USI __attribute__ ((vector_size (8)));
10 typedef float V2SF __attribute__ ((vector_size (8)));
11 typedef short V2HI __attribute__ ((vector_size (4)));
12 typedef unsigned int V2UHI __attribute__ ((vector_size (4)));
13 
14 long long
test1(V2SF x)15 test1 (V2SF x)
16 {
17   return (long long) (V2SI) x;
18 }
19 
20 long long
test2(V2SF x)21 test2 (V2SF x)
22 {
23   return (long long) x;
24 }
25 
26 long long
test3(V2SI x)27 test3 (V2SI x)
28 {
29   return (long long) (V2SF) x;
30 }
31 
32 int
main(void)33 main (void)
34 {
35   if (sizeof (short) != 2 || sizeof (int) != 4 || sizeof (long long) != 8)
36     return 0;
37 
38   V2SF x = { 2.0, 2.0 };
39   union { long long l; float f[2]; int i[2]; } u;
40   u.l = test1 (x);
41   if (u.f[0] != 2.0 || u.f[1] != 2.0)
42     abort ();
43 
44   V2SF y = { 6.0, 6.0 };
45   u.l = test2 (y);
46   if (u.f[0] != 6.0 || u.f[1] != 6.0)
47     abort ();
48 
49   V2SI z = { 4, 4 };
50   u.l = test3 (z);
51   if (u.i[0] != 4 || u.i[1] != 4)
52     abort ();
53   return 0;
54 }
55