1; Adapteva EPIPHANY CPU description. -*- Scheme -*-
2; Copyright 1998, 1999, 2000, 2001, 2003, 2006, 2007, 2008, 2009, 2010, 2011
3; Free Software Foundation, Inc.
4;
5; Contributed by Embecosm on behalf of Adapteva, Inc.
6; This file is part of the GNU Binutils and of GDB.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 3 of the License, or
11; (at your option) any later version.
12;
13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16; GNU General Public License for more details.
17;
18; You should have received a copy of the GNU General Public License
19; along with this program; if not, write to the Free Software
20; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21; MA 02110-1301, USA.
22
23(include "simplify.inc")
24					; define-arch must appear first
25
26(define-arch
27  (name epiphany) ; name of cpu family
28  (comment "Adapteva, Inc. EPIPHANY family")
29  (default-alignment aligned)
30  (insn-lsb0? #t)
31
32					; - a 16/32 bit instruction machine (the default)
33
34  (machs epiphany32)
35  (isas epiphany)
36  )
37
38					; Attributes.
39
40(define-attr
41  (for insn)
42  (type boolean)
43  (name SHORT-INSN)
44  (comment "instruction is a 16 bit form")
45  )
46
47;; 3 bit add/sub immediate forms - useful for relaxing into 11 bit form
48(define-attr
49  (for insn)
50  (type boolean)
51  (name IMM3)
52  (comment "instruction has a 3 bit immediate form")
53  )
54
55;; 8 bit mov immediate forms - useful for relaxing into 16 bit form
56(define-attr
57  (for insn)
58  (type boolean)
59  (name IMM8)
60  (comment "instruction has a 8 bit immediate form")
61  )
62
63					; Instruction set parameters.
64
65(define-isa
66  (name epiphany)
67  (comment "Adapteva, Inc. EPIPHANY32 ISA")
68
69  (default-insn-word-bitsize 32)
70  (default-insn-bitsize 32)
71  (base-insn-bitsize 32)
72  (decode-assist (3 2 1 0))  ; CGEN can figure this out
73  (liw-insns 1)				; # instructions fetched at once
74  )
75
76					; Cpu family definitions.
77
78
79(define-cpu
80					; cpu names must be distinct from the architecture name and machine names.
81  (name epiphanybf)
82  (comment "Adapteva, Inc. EPIPHANY Family")
83  (endian little)
84  (word-bitsize 32)
85  )
86
87(define-cpu
88  (name epiphanymf)
89  (comment "Adapteva, Inc. EPIPHANY Family")
90  (endian little)
91  (word-bitsize 32)
92  )
93
94
95(define-mach
96  (name epiphany32)
97  (comment "Adapteva EPIPHANY")
98  (cpu epiphanybf)
99  )
100
101
102					; Model descriptions.
103
104(define-model
105  (name epiphany32) (comment "Adapteva EPIPHANY 32/16") (attrs)
106  (mach epiphany32)
107
108  (unit u-exec "Execution Unit" ()
109	1 1 ; issue done
110	() ; state
111	() ; inputs
112	() ; outputs
113	() ; profile action (default)
114	)
115  )
116
117
118
119					; Instruction fields.
120					;
121					; Attributes:
122					; XXX: what EPIPHANY attrs
123					; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
124					; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
125					; RESERVED: bits are not used to decode insn, must be all 0
126					; RELOC: there is a relocation associated with this field
127
128(define-attr
129  (for ifield operand)
130  (type boolean)
131  (name RELOC)
132  (comment "there is a reloc associated with this field (experiment)")
133  )
134
135;; define the fields of the instruction.
136;;   name            description              ATTR  MSB LEN
137(dnf f-opc	  "primary opcode"	       ()     3 4)
138(dnf f-opc-4-1    "secondary opcode"           ()     4 1)
139(dnf f-opc-6-3    "secondary opcode"           ()     6 3) ;;
140(dnf f-opc-8-5    "tertiary opcode"            ()     8 5) ;;
141(dnf f-opc-19-4   "additional opcode bits"     ()    19 4)
142(dnf f-condcode   "condition codes" 	       ()     7 4)
143(dnf f-secondary-ccs "flag for secondary ccs"  ()     7 1)
144(dnf f-shift      "shift amount"               ()     9 5)
145(dnf f-wordsize   "load/store size"            ()     6 2)
146(dnf f-store      "load/store flag"            ()     4 1) ;; 0==load,1==store
147(dnf f-opc-8-1    "opcode bits"                ()     8 1)
148(dnf f-opc-31-32  "all opcode set"             ()     31 32)
149
150(df f-simm8	  "branch displacement"   (PCREL-ADDR RELOC) 15 8 INT
151    ((value pc) (sra SI (sub SI value pc) 1))
152    ((value pc) (add SI (sll SI value 1) pc)))
153
154(df f-simm24     "branch displacement"	  (PCREL-ADDR RELOC) 31 24 INT
155    ((value pc) (sra SI (sub SI value pc) 1))
156    ((value pc) (add SI (sll SI value 1) pc)))
157
158(df f-sdisp3     "signed immediate 3 bit"      ()     9 3  INT #f #f)
159
160(dnf f-disp3      "address offset"             ()     9 3)
161(dnf f-disp8      "address offset"             ()    23 8)
162
163(dnf f-imm8      "move/add/sub imm8"           ()    12 8)
164(dnf f-imm-27-8  "move/add/sub imm16"          ()    27 8)
165(dnf f-addsubx   "+/- index address"           ()    20 1)
166(dnf f-subd      "+/- displ address"           ()    24 1)
167(dnf f-pm        "post-modify immediate"       ()    25 1)
168
169(dnf f-rm        "short rm"                    ()     9 3)   ;; RM
170(dnf f-rn        "short rn"                    ()    12 3)   ;; RN
171(dnf f-rd        "short rd"                    ()    15 3)   ;; RD
172
173(dnf f-rm-x       "extension rm"               ()    25 3)   ;; RM
174(dnf f-rn-x       "extension rn"               ()    28 3)   ;; RN
175(dnf f-rd-x       "extension rd"               ()    31 3)   ;; RD
176
177(dnf f-dc-9-1     "DC"                 (RESERVED)     9 1)
178
179(dnf f-sn        "short sn"                    ()    12 3)   ;; SN
180(dnf f-sd        "short sd"                    ()    15 3)   ;; SD
181
182(dnf f-sn-x       "extension sn"               ()    28 3)   ;; SN
183(dnf f-sd-x       "extension sd"               ()    31 3)   ;; SD
184
185
186
187(dnf f-dc-7-4     "movts zeros"                 ()     7 4)
188(dnf f-trap-swi-9-1     "trap or swi"                 ()     9 1)
189(dnf f-gien-gidis-9-1     "gien or gidis"                 ()     9 1)
190
191
192(dnf f-dc-15-3    "DC"                 (RESERVED)    15 3)
193(dnf f-dc-15-7    "DC"                 (RESERVED)    15 7)
194(dnf f-dc-15-6    "DC"                 ()            15 6)
195(dnf f-trap-num   "trap number"                ()    15 6)
196
197(dnf f-dc-20-1    "DC"                 (RESERVED)    20 1)
198
199(dnf f-dc-21-1    "DC"                 (RESERVED)    21 1)
200(dnf f-dc-21-2    "DC"                 (RESERVED)    21 2)
201
202(dnf f-dc-22-3    "DC"                 (RESERVED)    22 3)
203(dnf f-dc-22-2    "DC"                 (RESERVED)    22 2)
204(dnf f-dc-22-1    "DC"                 (RESERVED)    22 1)
205
206(dnf f-dc-25-6    "DC"                 (RESERVED)    25 6)
207(dnf f-dc-25-4    "DC"                 (RESERVED)    25 4)
208(dnf f-dc-25-2    "DC"                 (RESERVED)    25 2)
209(dnf f-dc-25-1    "DC"                 (RESERVED)    25 1)
210
211(dnf f-dc-28-1    "DC"                 (RESERVED)    28 1)
212(dnf f-dc-31-3    "DC"                 (RESERVED)    31 3)
213
214(dnmf f-disp11 "Unsigned offset for load/store" () UINT (f-disp3 f-disp8)
215      (sequence ()
216		(set (ifield f-disp8) (and (srl (ifield f-disp11) 3) (const 255)))
217		(set (ifield f-disp3) (and (ifield f-disp11) 7)))
218      (sequence ()
219		(set (ifield f-disp11) (or (sll (ifield f-disp8) 3)
220					   (ifield f-disp3)))
221		)
222      )
223
224
225(dnmf f-sdisp11 "Signed offset for load/store" () INT (f-disp3 f-disp8)
226      (sequence ()			;encode
227		(set (ifield f-disp8) (and #xff (srl SI (ifield f-sdisp11) 3)))
228		(set (ifield f-disp3)  (and SI (ifield f-sdisp11) 7)))
229      (sequence ()			;decode
230		(set (ifield f-sdisp11)
231		     (sra SI (sll SI (or SI (sll (ifield f-disp8) 3)
232					 (ifield f-disp3))
233				  21)
234			  21)))
235      )
236
237(dnmf f-imm16 "Short immediate for move/add/sub" () UINT (f-imm8 f-imm-27-8)
238      (sequence ()
239		(set (ifield f-imm8) (and (ifield f-imm16) #xff))
240		(set (ifield f-imm-27-8) (srl (ifield f-imm16) 8)))
241      (sequence ()
242		(set (ifield f-imm16) (or (sll (ifield f-imm-27-8) 8)
243					  (ifield f-imm8))))
244      )
245
246
247;; 32 bit instructions have the register number broken into two non-contiguous fields
248
249(define-pmacro (x-reg-field reg)
250  (define-multi-ifield
251    (name (.sym "f-" reg "6"))
252    (mode UINT)
253    (subfields (.sym "f-" reg "-x") (.sym "f-" reg))
254    (insert (sequence ()
255		      (set (ifield (.sym "f-" reg))   (and (ifield (.sym "f-" reg "6"))
256							   (const 7)))
257		      (set (ifield (.sym "f-" reg "-x"))  (srl (ifield (.sym "f-" reg "6"))
258							       (const 3)))
259		      ))
260    (extract (sequence ()
261		       (set (ifield (.sym "f-" reg "6")) (or (sll (ifield (.sym "f-" reg "-x"))
262								  (const 3))
263							     (ifield (.sym "f-" reg))))
264		       ))
265    )
266  )
267
268(x-reg-field rd)			; f-rd6
269(x-reg-field rn)			; f-rn6
270(x-reg-field rm)			; f-rm6
271(x-reg-field sd)			; f-sd6
272(x-reg-field sn)			; f-sn6
273
274
275;;;;;;;;;;
276					; Enums. ;
277;;;;;;;;;;
278
279					; insn-opc: bits 3..0 - major family selector
280(define-normal-insn-enum insn-opc "opc enums" () OP4_ f-opc
281  (
282   BRANCH16  ;; 0000
283   LDSTR16X  ;; 0001
284   FLOW16    ;; 0010
285   IMM16     ;; 0011
286   LDSTR16D  ;; 0100
287   LDSTR16P  ;; 0101
288   LSHIFT16  ;; 0110 - logical shift
289   DSP16     ;; 0111 - 3 reg DSP 16 bit insns
290   BRANCH    ;; 1000
291   LDSTRX    ;; 1001
292   ALU16     ;; 1010 - 3 reg 16 bit
293   IMM32     ;; 1011
294   LDSTRD    ;; 1100
295   LDSTRP    ;; 1101
296   ASHIFT16  ;; 1110   ASR, BITR
297   MISC      ;; 1111 - 32 bit shifts, 3 reg ALU, 3 reg DSP, FLOW, BITR
298   )
299  )
300
301(define-normal-insn-enum insn-wordsize "memory access width" () OPW_ f-wordsize
302					; specifies the size of a memory load/store operation
303  (BYTE SHORT WORD DOUBLE)
304  )
305
306(define-normal-insn-enum insn-memory-access "memory access direction" () OP_ f-store
307					; load=0, store=1
308  (LOAD STORE)
309  )
310
311					; enum for trap codes used by simulator
312(define-normal-insn-enum trap-codes "trap instruction dispatch code" () TRAP_ f-trap-num
313  (write read open exit pass fail close other)
314  )
315
316					; cond branch: bits 7..4
317					;
318(define-normal-insn-enum insn-cond "branch conditions" () OPC_ f-condcode
319  (EQ NE GTU GTEU LTEU LTU GT GTE LT LTE BEQ BNE BLT BLTE B BL))
320
321					; dsp 3 operand opcodes
322(define-normal-insn-enum insn-bop "binary operator subcodes" () OPB_ f-opc-6-3
323  (EOR ADD LSL SUB LSR AND ASR ORR))
324
325					; dsp 3 operand opcodes
326(define-normal-insn-enum insn-bopext "binary operator subcodes" () OPBE_ f-opc-6-3
327  (FEXT FDEP LFSR - - - - -))
328
329
330(define-normal-insn-enum insn-fop "floating operators" () OPF_ f-opc-6-3
331  (ADD SUB MUL MADD MSUB FLOAT FIX FABS))
332
333(define-normal-insn-enum insn-fopexn "extended floating operators" () OPF_ f-opc-6-3
334  (FRECIP FSQRT - - - - - -))
335
336
337
338
339; Immediate operation secondary opcodes
340(define-normal-insn-enum insn-immop "immediate operators" () OPI_ f-opc-6-3
341  (- ADD - SUB - - - TRAP) ; TRAP is special extension for simulator
342  )
343
344					; don't care fields
345(define-normal-insn-enum insn-dc-25-2 "don't cares" () OPI_25_2_ f-dc-25-2
346  (MBZ))
347
348; General Register keyword names.
349(define-keyword
350  (name gr-names)
351  (print-name h-registers)
352  (prefix "")
353  (values
354; some preferred aliases
355   (fp 11) (sp 13) (lr 14)
356; the default register names
357   (r0  0)  (r1  1)  (r2  2)  (r3  3)  (r4  4)  (r5  5)  (r6  6)  (r7  7)
358   (r8  8)  (r9  9) (r10 10) (r11 11) (r12 12) (r13 13) (r14 14) (r15 15)
359   (r16 16) (r17 17) (r18 18) (r19 19) (r20 20) (r21 21) (r22 22) (r23 23)
360   (r24 24) (r25 25) (r26 26) (r27 27) (r28 28) (r29 29) (r30 30) (r31 31)
361   (r32 32) (r33 33) (r34 34) (r35 35) (r36 36) (r37 37) (r38 38) (r39 39)
362   (r40 40) (r41 41) (r42 42) (r43 43) (r44 44) (r45 45) (r46 46) (r47 47)
363   (r48 48) (r49 49) (r50 50) (r51 51) (r52 52) (r53 53) (r54 54) (r55 55)
364   (r56 56) (r57 57) (r58 58) (r59 59) (r60 60) (r61 61) (r62 62) (r63 63)
365; some less popular aliases
366   (a1  0) (a2  1) (a3  2) (a4  3) (v1  4) (v2  5) (v3  6) (v4  7)
367   (v5  8) (v6  9) (v7 10) (v8 11)
368   (sb 9) (sl 10) (ip 12)
369   )
370  )
371
372(define-normal-insn-enum post-index "+/- index register" () DIR_ f-addsubx (POSTINC POSTDEC))
373
374(define-normal-insn-enum disp-post-modify "postmodify displacement" () PMOD_ f-pm (DISP POST))
375
376;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
377					; Hardware pieces.
378;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
379
380;; 64 general-purpose registers
381(define-hardware
382  (name h-registers)
383  (comment "all addressable registers")
384  (type register SI (64))
385  (attrs PROFILE CACHE-ADDR)
386  (indices extern-keyword gr-names)
387  )
388
389
390
391;; Same 64 registers as floating point registers
392(define-hardware
393  (name h-fpregisters)
394  (comment "all GPRs as float values")
395  (type register SF (64))
396  (attrs PROFILE VIRTUAL)
397  (indices extern-keyword gr-names)
398  (get (index) (subword SF (reg h-registers index) 0))
399  (set (index newval) (set (reg h-registers index) (subword SI newval 0)))
400  )
401
402;; define processor status bits as physical hardware
403
404(define-pmacro (psw-h-bit name cmt)
405  (dsh name cmt () (register BI)))
406
407(psw-h-bit h-zbit "integer zero bit")
408(psw-h-bit h-nbit "integer neg bit")
409(psw-h-bit h-cbit "integer carry bit")
410(psw-h-bit h-vbit "integer overflow bit")
411(psw-h-bit h-vsbit "integer overflow sticky")
412
413
414(psw-h-bit h-bzbit "floating point zero bit")
415(psw-h-bit h-bnbit "floating point neg bit")
416(psw-h-bit h-bvbit "floating point ovfl bit")
417(psw-h-bit h-bubit "floating point underfl bit")
418(psw-h-bit h-bibit "floating point invalid bit")
419(psw-h-bit h-bcbit "floating point carry bit")
420
421(psw-h-bit h-bvsbit "floating point overflow sticky")
422(psw-h-bit h-bisbit  "floating point invalid sticky")
423(psw-h-bit h-busbit  "floating point underflow sticky")
424
425(psw-h-bit h-expcause0bit  "exceprion cause bit0")
426(psw-h-bit h-expcause1bit  "exceprion cause bit1")
427(psw-h-bit h-expcause2bit  "external load stalled bit")
428(psw-h-bit h-extFstallbit  "external fetch stalled bit")
429
430(psw-h-bit h-trmbit  "0=round to nearest, 1=trunacte select bit")
431(psw-h-bit h-invExcEnbit  "invalid exception enable bit")
432(psw-h-bit h-ovfExcEnbit  "overflow exception enable bit")
433(psw-h-bit h-unExcEnbit  "underflow exception enablebit ")
434
435(psw-h-bit h-timer0bit0  "timer 0 mode selection 0")
436(psw-h-bit h-timer0bit1  "timer 0 mode selection 1")
437(psw-h-bit h-timer0bit2  "timer 0 mode selection 2")
438(psw-h-bit h-timer0bit3  "timer 0 mode selection 3")
439(psw-h-bit h-timer1bit0  "timer 1 mode selection 0")
440(psw-h-bit h-timer1bit1  "timer 1 mode selection 1")
441(psw-h-bit h-timer1bit2  "timer 1 mode selection 2")
442(psw-h-bit h-timer1bit3  "timer 1 mode selection 3")
443
444(psw-h-bit h-mbkptEnbit  "multicore bkpt enable")
445(psw-h-bit h-clockGateEnbit  "clock gating enable bkpt enable")
446
447
448(psw-h-bit h-coreCfgResBit12 "core config bit 12")
449(psw-h-bit h-coreCfgResBit13 "core config bit 13")
450(psw-h-bit h-coreCfgResBit14 "core config bit 14")
451(psw-h-bit h-coreCfgResBit15 "core config bit 15")
452(psw-h-bit h-coreCfgResBit16 "core config bit 16")
453
454
455(psw-h-bit h-coreCfgResBit20 "core config bit 20")
456(psw-h-bit h-coreCfgResBit21 "core config bit 21")
457
458(psw-h-bit h-coreCfgResBit24 "core config bit 24")
459(psw-h-bit h-coreCfgResBit25 "core config bit 25")
460(psw-h-bit h-coreCfgResBit26 "core config bit 26")
461(psw-h-bit h-coreCfgResBit27 "core config bit 27")
462(psw-h-bit h-coreCfgResBit28 "core config bit 28")
463(psw-h-bit h-coreCfgResBit29 "core config bit 29")
464(psw-h-bit h-coreCfgResBit30 "core config bit 30")
465(psw-h-bit h-coreCfgResBit31 "core config bit 31")
466
467
468(psw-h-bit h-arithmetic-modebit0  "arithmetic mode bit0")
469(psw-h-bit h-arithmetic-modebit1  "arithmetic mode bit1")
470(psw-h-bit h-arithmetic-modebit2  "arithmetic mode bit2")
471
472
473(psw-h-bit h-gidisablebit "global interrupt disable bit")
474(psw-h-bit h-kmbit "kernel mode bit")
475(psw-h-bit h-caibit "core active indicator mode bit")
476(psw-h-bit h-sflagbit "sflag bit")
477
478
479					; Define operands for each of the physical bits
480(define-pmacro (psw-bit name hname cmt)
481  (dnop name cmt (SEM-ONLY) hname f-nil)
482  )
483
484(psw-bit zbit h-zbit "integer zero bit")
485(psw-bit nbit h-nbit "integer neg bit")
486(psw-bit cbit h-cbit "integer carry bit")
487(psw-bit vbit h-vbit "integer overflow bit")
488
489(psw-bit bzbit  h-bzbit "floating point zero bit")
490(psw-bit bnbit  h-bnbit "floating point neg bit")
491(psw-bit bvbit  h-bvbit "floating point ovfl bit")
492(psw-bit bcbit  h-bcbit "floating point carry bit")
493
494(psw-bit bubit h-bubit "floating point underfl bit")
495(psw-bit bibit h-bibit "floating point invalid bit")
496
497
498(psw-bit vsbit  h-vsbit  "integer overflow sticky")
499(psw-bit bvsbit h-bvsbit "floating point overflow sticky")
500(psw-bit bisbit  h-bisbit  "floating point invalid sticky")
501(psw-bit busbit  h-busbit  "floating point underflow sticky")
502(psw-bit expcause0bit h-expcause0bit  "exceprion cause bit0")
503(psw-bit expcause1bit h-expcause1bit  "exceprion cause bit1")
504
505
506(psw-bit expcause2bit  h-expcause2bit  "external load stalled bit")
507(psw-bit extFstallbit  h-extFstallbit  "external fetch stalled bit")
508
509(psw-bit trmbit  h-trmbit  "0=round to nearest, 1=trunacte selct bit")
510(psw-bit invExcEnbit  h-invExcEnbit  "invalid exception enable bit")
511(psw-bit ovfExcEnbit  h-ovfExcEnbit  "overflow exception enable bit")
512(psw-bit unExcEnbit  h-unExcEnbit  "underflow exception enable bit")
513
514(psw-bit timer0bit0  h-timer0bit0  "timer 0 mode selection 0")
515(psw-bit timer0bit1  h-timer0bit1  "timer 0 mode selection 1")
516(psw-bit timer0bit2  h-timer0bit2  "timer 0 mode selection 2")
517(psw-bit timer0bit3  h-timer0bit3  "timer 0 mode selection 3")
518
519(psw-bit timer1bit0  h-timer1bit0  "timer 1 mode selection 0")
520(psw-bit timer1bit1  h-timer1bit1  "timer 1 mode selection 1")
521(psw-bit timer1bit2  h-timer1bit2  "timer 1 mode selection 2")
522(psw-bit timer1bit3  h-timer1bit3  "timer 1 mode selection 3")
523
524(psw-bit mbkptEnbit  h-mbkptEnbit "multicore bkpt enable")
525(psw-bit clockGateEnbit  h-clockGateEnbit "clock gate enable enable")
526
527(psw-bit arithmetic-modebit0  h-arithmetic-modebit0  "arithmetic mode bit0")
528(psw-bit arithmetic-modebit1  h-arithmetic-modebit1  "arithmetic mode bit1")
529(psw-bit arithmetic-modebit2  h-arithmetic-modebit2  "arithmetic mode bit2")
530
531(psw-bit coreCfgResBit12  h-coreCfgResBit12 "core config bit 12")
532(psw-bit coreCfgResBit13  h-coreCfgResBit13 "core config bit 13")
533(psw-bit coreCfgResBit14  h-coreCfgResBit14 "core config bit 14")
534(psw-bit coreCfgResBit15  h-coreCfgResBit15 "core config bit 15")
535(psw-bit coreCfgResBit16  h-coreCfgResBit16 "core config bit 16")
536
537(psw-bit coreCfgResBit20  h-coreCfgResBit20 "core config bit 20")
538(psw-bit coreCfgResBit21  h-coreCfgResBit21 "core config bit 21")
539
540(psw-bit coreCfgResBit24  h-coreCfgResBit24 "core config bit 24")
541(psw-bit coreCfgResBit25  h-coreCfgResBit25 "core config bit 25")
542(psw-bit coreCfgResBit26  h-coreCfgResBit26 "core config bit 26")
543(psw-bit coreCfgResBit27  h-coreCfgResBit27 "core config bit 27")
544(psw-bit coreCfgResBit28  h-coreCfgResBit28 "core config bit 28")
545(psw-bit coreCfgResBit29  h-coreCfgResBit29 "core config bit 29")
546(psw-bit coreCfgResBit30  h-coreCfgResBit30 "core config bit 30")
547(psw-bit coreCfgResBit31  h-coreCfgResBit31 "core config bit 31")
548
549
550(psw-bit gidisablebit h-gidisablebit "global interrupt disable bit")
551(psw-bit kmbit h-kmbit "kernel mode bit")
552(psw-bit caibit h-caibit "core actibe indicator bit")
553(psw-bit sflagbit h-sflagbit "sflag bit")
554
555
556
557
558;; Special registers - accessed via MOVTS and MOVFS.
559;;
560;;  "Core control and status" in group MR0=0, MR1=0
561
562(define-keyword
563  (name cr-names)
564  (print-name h-core-registers)
565  (prefix "")
566  (values  (config         0)
567	   (status         1) ; unified condition codes
568	   (pc             2) ; virtualized PC
569	   (debug          3);
570	   (iab            4)
571	   (lc             5);loop counter            Not impemented
572	   (ls             6);loop start address      Not impemented
573	   (le             7);loop end address        Not impemented
574	   (iret           8)
575	   (imask          9)
576	   (ilat           10)
577	   (ilatst         11)
578	   (ilatcl         12)
579	   (ipend          13)
580	   (ctimer0        14)
581	   (ctimer1        15)
582	   (hstatus        16)
583	   )
584  )
585;; DMA registers in group MR0=1, MR1=0
586
587(define-keyword
588  (name crdma-names)
589  (print-name h-coredma-registers)
590  (prefix "")
591  (values
592
593
594   (dma0config     0)
595   (dma0stride     1)
596   (dma0count      2)
597
598   (dma0srcaddr    3)
599   (dma0dstaddr    4)
600
601   (dma0auto0      5)
602   (dma0auto1      6)
603
604   (dma0status     7)
605
606   (dma1config     8)
607   (dma1stride     9)
608   (dma1count      10)
609
610   (dma1srcaddr    11)
611   (dma1dstaddr    12)
612
613   (dma1auto0      13)
614   (dma1auto1      14)
615
616   (dma1status     15)
617
618   )
619  )
620;; mem configuration registers in group MR0=0, MR1=1
621
622(define-keyword
623  (name crmem-names)
624  (print-name h-coremem-registers)
625  (prefix "")
626  (values
627   (memconfig     0)
628   (memstatus     1)
629   (memprotect    2)
630   (memreserve    3)
631   )
632  )
633
634;; mesh configuration registers in group MR0=1, MR1=1
635
636(define-keyword
637  (name crmesh-names)
638  (print-name h-coremesh-registers)
639  (prefix "")
640
641  (values
642
643
644   (meshconfig    0)
645   (coreid    1)
646   (meshmulticast 2)
647   (swreset   3)
648   )
649  )
650
651
652
653
654;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
655					; PC is a byte-addressed register
656;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
657
658(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
659
660;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
661					; Memory Effective Address wants to be visible
662;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
663
664(dnh h-memaddr "memory effective address" (PROFILE) (register SI) () () ())
665(dnop memaddr "memory effective address" (SEM-ONLY) h-memaddr f-nil)
666
667;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
668					; Special Core Registers
669;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
670;; STATUS
671;; [0]=core active indicator
672;; [1]=global interrupt disable
673;; [2]=processor mode(1=user mode, 0=kernel mode)
674;; [3]=wired AND global flag
675
676;; [4]=integer zero                        zbit
677;; [5]=integer negative                    nbit
678;; [6]=integer carry                       cbit
679;; [7]=integer overflow                    vbit
680
681;; [8]=fpu zero flag                       bzbit
682;; [9]=fpu negative flag                   bnbit
683;; [10]=fpu overflow flag                  bvbit
684;; [11]=fpu carry flag(not used)           bcbit
685
686;; [12]=ialu overflow flag(sticky)         vsbit
687;; [13]=fpu invalid flag(sticky)           bisbit
688;; [14]=fpu overflow flag(sticky)          bvsbit
689;; [15]=fpu underflow flag(sticky)         busbit
690
691;; [17:16]=exception cause 00=no exception 01=load-store exception 10=fpu exception 11=unimplemented instruction
692;;                                         expcause1bit
693;;                                         expcause0bit
694
695;; [18]=external load stalled              expcause2bit
696;; [19]=external fetch stalled             extFstallbit
697
698;; [31:20]=RESERVED
699
700
701
702
703
704(define-hardware
705  (name h-core-registers)
706  (comment "Special Core Registers")
707  (type register USI (17))
708  (attrs)
709  (indices extern-keyword cr-names)
710  (get (index)
711       (cond USI
712	 ((eq index (const 1)) ; STATUS reg ?
713	  (or (or (or (or (sll USI kmbit (const 2))
714			  (sll USI gidisablebit (const 1)))
715		      (or (or (sll USI expcause1bit (const 17))
716			      (sll USI expcause0bit (const 16)))
717			  (or (sll USI expcause2bit (const 18))
718			      (sll USI extFstallbit (const 19)))))
719		  (or (or (or (sll USI busbit (const 15))
720			      (sll USI bisbit (const 13)))
721			  (or (sll USI bvsbit (const 14))
722			      (sll USI vsbit (const 12))))
723		      (or (or (sll USI bvbit (const 10))
724			      (sll USI bcbit (const 11)))
725			  (or (sll USI bnbit (const 9))
726			      (sll USI bzbit (const 8))))))
727	      (or (or (or (sll USI vbit (const 7))
728			  (sll USI cbit (const 6)))
729		      (or (sll USI nbit (const 5))
730			  (sll USI zbit (const 4))))
731		  (or (sll USI sflagbit (const 3))
732		      (sll USI (const 1) (const 0)))))) ;caibit
733	 ((eq index (const 0)) ; Config reg ?
734	  (or (or (or (or (or (or (sll USI timer0bit2 (const 6))
735				  (sll USI timer0bit3 (const 7)))
736			      (or (or (sll USI coreCfgResBit28 (const 28))
737				      (sll USI coreCfgResBit29 (const 29)))
738				  (or (sll USI coreCfgResBit30 (const 30))
739				      (sll USI coreCfgResBit31 (const 31)))))
740			  (or (or (sll USI coreCfgResBit24 (const 24))
741				  (sll USI coreCfgResBit25 (const 25)))
742			      (or (sll USI coreCfgResBit26 (const 26))
743				  (sll USI coreCfgResBit27 (const 27)))))
744		      (or (or (sll USI timer0bit0 (const 4))
745			      (sll USI timer0bit1 (const 5)))
746			  (or (sll USI coreCfgResBit14 (const 14))
747			      (sll USI coreCfgResBit15 (const 15)))))
748		  (or (or (or (or (sll USI timer1bit2 (const 10))
749				  (sll USI timer1bit3 (const 11)))
750			      (or (sll USI coreCfgResBit12 (const 12))
751				  (sll USI coreCfgResBit13 (const 13))))
752			  (or (sll USI clockGateEnbit (const 22))
753			      (sll USI mbkptEnbit (const 23))))
754		      (or (or (sll USI timer1bit0 (const 8))
755			      (sll USI timer1bit1 (const 9)))
756			  (or (sll USI coreCfgResBit20 (const 20))
757			      (sll USI coreCfgResBit21 (const 21))))))
758	      (or (or (sll USI invExcEnbit (const 1))
759		      (sll USI ovfExcEnbit (const 2)))
760		  (or (or (sll USI trmbit (const 0))
761			  (sll USI unExcEnbit (const 3)))
762		      (or (or (sll USI arithmetic-modebit0 (const 17))
763			      (sll USI arithmetic-modebit1 (const 18)))
764			  (or (sll USI arithmetic-modebit2 (const 19))
765			      (sll USI coreCfgResBit16 (const 16)))))))) ;config reg
766
767	 ((eq index (const 2)) (raw-reg USI h-pc)) ;PC reg
768
769	 (else (raw-reg USI h-core-registers index))))
770
771  (set (index val)
772       (cond VOID
773	 ((eq index (const 0)) ; CONFIG reg
774	  (sequence ()
775	    (set trmbit      (and (const 1) (srl val (const 0))))
776	    (set invExcEnbit (and (const 1) (srl val (const 1))))
777	    (set ovfExcEnbit (and (const 1) (srl val (const 2))))
778	    (set unExcEnbit  (and (const 1) (srl val (const 3))))
779	    (set timer0bit0  (and (const 1) (srl val (const 4))))
780	    (set timer0bit1  (and (const 1) (srl val (const 5))))
781	    (set timer0bit2  (and (const 1) (srl val (const 6))))
782	    (set timer0bit3  (and (const 1) (srl val (const 7))))
783	    (set timer1bit0  (and (const 1) (srl val (const 8))))
784	    (set timer1bit1  (and (const 1) (srl val (const 9))))
785	    (set timer1bit2  (and (const 1) (srl val (const 10))))
786	    (set timer1bit3  (and (const 1) (srl val (const 11))))
787
788	    (set coreCfgResBit12 (and (const 1) (srl val (const 12))))
789	    (set coreCfgResBit13 (and (const 1) (srl val (const 13))))
790	    (set coreCfgResBit14 (and (const 1) (srl val (const 14))))
791	    (set coreCfgResBit15 (and (const 1) (srl val (const 15))))
792	    (set coreCfgResBit16 (and (const 1) (srl val (const 16))))
793
794	    (set arithmetic-modebit0 (and (const 1) (srl val (const 17))))
795	    (set arithmetic-modebit1 (and (const 1) (srl val (const 18))))
796	    (set arithmetic-modebit2 (and (const 1) (srl val (const 19))))
797
798	    (set coreCfgResBit20 (and (const 1) (srl val (const 20))))
799	    (set coreCfgResBit21 (and (const 1) (srl val (const 21))))
800
801	    (set clockGateEnbit  (and (const 1) (srl val (const 22))))
802	    (set mbkptEnbit      (and (const 1) (srl val (const 23))))
803
804	    (set coreCfgResBit24 (and (const 1) (srl val (const 24))))
805	    (set coreCfgResBit25 (and (const 1) (srl val (const 25))))
806	    (set coreCfgResBit26 (and (const 1) (srl val (const 26))))
807	    (set coreCfgResBit27 (and (const 1) (srl val (const 27))))
808	    (set coreCfgResBit28 (and (const 1) (srl val (const 28))))
809	    (set coreCfgResBit29 (and (const 1) (srl val (const 29))))
810	    (set coreCfgResBit30 (and (const 1) (srl val (const 30))))
811	    (set coreCfgResBit31 (and (const 1) (srl val (const 31))))
812
813	    (set (raw-reg USI h-core-registers index) val)
814	    ;; check LSB of CONFIG for rounding mode
815	    (c-call "epiphany_set_rounding_mode" val)
816	  )
817	 )
818	 ((eq index (const 1))	;STATUS reg ; TODO check which bits can be set or clear
819	  (sequence ((USI newval))
820	    (set newval (and val (const #xfff2)))
821	    (set extFstallbit  (and (const 1) (srl newval (const 19))))
822	    (set expcause2bit  (and (const 1) (srl newval (const 18))))
823	    (set expcause1bit  (and (const 1) (srl newval (const 17))))
824	    (set expcause0bit  (and (const 1) (srl newval (const 16))))
825	    (set busbit (and (const 1) (srl newval (const 15))))
826	    (set bisbit (and (const 1) (srl newval (const 13))))
827	    (set bvsbit (and (const 1) (srl newval (const 14))))
828	    (set vsbit  (and (const 1) (srl newval (const 12))))
829	    (set bvbit  (and (const 1) (srl newval (const 10))))
830	    (set bcbit  (and (const 1) (srl newval (const 11))))
831	    (set bnbit  (and (const 1) (srl newval (const 9))))
832	    (set bzbit  (and (const 1) (srl newval (const 8))))
833	    (set vbit   (and (const 1) (srl newval (const 7))))
834	    (set cbit   (and (const 1) (srl newval (const 6))))
835	    (set nbit   (and (const 1) (srl newval (const 5))))
836	    (set zbit   (and (const 1) (srl newval (const 4))))
837	    (set sflagbit (and (const 1) (srl newval (const 3))))
838	    (set kmbit  (and (const 1) (srl newval (const 2))))
839	    ;;(set gie    (and (const 1) (srl newval (const 1))))
840	    (set (raw-reg SI h-core-registers (const 1)) newval)
841	   ))
842	 ;; causes simulator errors
843	 ;;	     ((eq index (const 2))	;PC reg
844	 ;;	      (set pc val))
845
846	 (else (set (raw-reg USI h-core-registers index) val))
847       ))
848)
849					; (define-pmacro (hcr-config) (reg h-core-registers 0)) etc.
850(.splice begin (.unsplice (.map
851			   (.pmacro (xname xnum)
852				    (define-pmacro ((.sym hcr- xname)) (reg h-core-registers xnum)))
853
854			   (
855			    config
856			    status
857			    pc
858			    debug
859			    iab
860			    lc
861			    ls
862			    le
863			    iret
864			    imask
865			    ilat
866			    ilatst
867			    ilatcl
868			    ipend
869			    ctimer0
870			    ctimer1
871			    hstatus
872
873
874
875			    )
876
877			   (0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
878			      )
879			   )))
880
881
882
883;; DMA registers in MMR space
884(define-hardware
885  (name h-coredma-registers)
886  (comment "DMA registers in MMR space")
887  (type register USI (16))
888  (attrs)
889  (indices extern-keyword crdma-names)
890  )
891
892;; MEM registers in MMR space
893(define-hardware
894  (name h-coremem-registers)
895  (comment "MEM registers in MMR space")
896  (type register USI (4))
897  (attrs)
898  (indices extern-keyword crmem-names)
899  )
900
901;; MEM registers in MMR space
902(define-hardware
903  (name h-coremesh-registers)
904  (comment "MESH registers in MMR space")
905  (type register USI (4))
906  (attrs)
907  (indices extern-keyword crmesh-names)
908  )
909
910
911
912					; Operands
913
914					; Branch displacements
915(define-operand
916  (name simm24)
917  (comment "branch address pc-relative")
918  (attrs RELAX)
919  (type h-iaddr)
920  (index f-simm24)
921  (handlers (parse "branch_addr")))
922
923(define-operand
924  (name simm8)
925  (comment "branch address pc-relative")
926  (attrs RELAX)
927  (type h-iaddr)
928  (index f-simm8)
929  (handlers (parse "branch_addr")))
930
931
932;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
933					; Register operands
934;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
935
936(define-pmacro (short-regs nm group hw cmt)
937  (define-operand
938    (name nm)
939    (comment cmt)
940    (attrs)
941    (type hw)
942    (index (.sym "f-r" group))
943    (handlers (parse "shortregs") (print "keyword"))
944    )
945  )
946
947(define-pmacro (short-regs-core nm group hw cmt)
948  (define-operand
949    (name nm)
950    (comment cmt)
951    (attrs)
952    (type hw)
953    (index (.sym "f-s" group))
954    (handlers (parse "shortregs") (print "keyword"))
955    )
956  )
957
958
959					; short regs (0-7)
960(short-regs rd d h-registers "destination register")
961(short-regs rn n h-registers "source register")
962(short-regs rm m h-registers "source register")
963
964(short-regs frd d h-fpregisters "fp destination register")
965(short-regs frn n h-fpregisters "fp source register")
966(short-regs frm m h-fpregisters "fp source register")
967
968					; long regs (0-63)
969(dnop rd6 "destination register" () h-registers f-rd6)
970(dnop rn6 "source register"      () h-registers f-rn6)
971(dnop rm6 "source register"      () h-registers f-rm6)
972
973(dnop frd6 "fp destination register" () h-fpregisters f-rd6)
974(dnop frn6 "fp source register"      () h-fpregisters f-rn6)
975(dnop frm6 "fp source register"      () h-fpregisters f-rm6)
976
977					; special regs (0-7)
978(short-regs-core sd d h-core-registers "special destination")
979(short-regs-core sn n h-core-registers "special source")
980
981					; special regs (long form)
982(dnop sd6 "special destination register" () h-core-registers f-sd6)
983(dnop sn6 "special source register"      () h-core-registers f-sn6)
984
985(dnop sddma "dma register" () h-coredma-registers f-sd6)
986(dnop sndma "dma register"      () h-coredma-registers f-sn6)
987(dnop sdmem "mem register" () h-coremem-registers f-sd6)
988(dnop snmem "mem register"      () h-coremem-registers f-sn6)
989(dnop sdmesh "mesh register" () h-coremesh-registers f-sd6)
990(dnop snmesh "mesh register"      () h-coremesh-registers f-sn6)
991
992					; Immediate literals - but don't allow register names!
993(define-pmacro (dimmop nm cmt hwtype idx)
994  (define-operand (name nm) (comment cmt) (type hwtype) (index idx)
995    (attrs RELAX)
996    (handlers (parse "simm_not_reg")
997	      (print "simm_not_reg")))
998  )
999
1000(dimmop simm3   "signed 3-bit literal"    h-sint f-sdisp3)
1001(dimmop simm11  "signed 11-bit literal"   h-sint f-sdisp11)
1002(dnop disp3  "short data displacement"   () h-uint f-disp3)
1003(dnop trapnum6 "parameter for swi or trap" () h-uint f-trap-num)
1004
1005(define-pmacro (duimmop nm cmt hwtype idx)
1006  (define-operand (name nm) (comment cmt) (type hwtype) (index idx)
1007    (attrs)
1008    (handlers (parse "uimm_not_reg")
1009	      (print "uimm_not_reg")))
1010  )
1011
1012(duimmop swi_num "unsigned 6-bit swi#" h-uint f-trap-num)
1013(duimmop disp11 "sign-magnitude data displacement" h-uint f-disp11)
1014
1015(dnop shift   "immediate shift amount"   () h-uint f-shift)
1016
1017(define-operand (name imm16) (comment "16-bit unsigned literal") (attrs RELAX)
1018  (type h-addr) (index f-imm16) (handlers (parse "imm16")))
1019(define-operand (name imm8) (comment "8-bit unsigned literal") (attrs RELAX)
1020  (type h-addr) (index f-imm8) (handlers (parse "imm8")))
1021
1022(define-operand
1023  (name direction)
1024  (comment "+/- indexing")
1025  (attrs)
1026  (type h-uint)
1027  (index f-addsubx)
1028  (handlers (parse "postindex")
1029	    (print "postindex")))
1030
1031(define-operand
1032  (name dpmi)
1033  (comment "+/- magnitude immediate displacement")
1034  (attrs)
1035  (type h-uint)
1036  (index f-subd)
1037  (handlers (parse "postindex")
1038	    (print "postindex")))
1039
1040
1041
1042;; call exception macro - no check for imask
1043(define-pmacro (call-exception vaddr bit-in-ilat)
1044  (if (eq gidisablebit 0)
1045      (if (eq (and (hcr-imask) bit-in-ilat) 0)
1046	  (sequence ()
1047		    (set kmbit 1)
1048		    (set gidisablebit 1)
1049		    (set (hcr-iret) (add pc (const 2)))
1050		    (set (hcr-ipend) (or (hcr-ipend) (const bit-in-ilat)))
1051		    (set pc (const vaddr))
1052
1053		    )
1054	  ;; schedule interrupt
1055	  (set (hcr-ilat) (or (hcr-ilat) (const  bit-in-ilat)))
1056	  )
1057      )
1058  )
1059
1060
1061;;      (lc             5);loop counter            Not impemented
1062;;       (ls             6);loop start address      Not impemented
1063;;       (le             7);loop end address        Not impemented
1064
1065;;have callback to adjust pc in case od events ( HW loops ... )
1066(define-pmacro (dni_wrapper isnid stdrdesc attr_ strassembl iopcode proceed null_b)
1067  (begin
1068    (dni isnid stdrdesc attr_ strassembl iopcode
1069	 (sequence () proceed
1070		   (sequence ((USI tmpPC))
1071			     ;;(set tmpPC  (c-call  USI "epiphany_post_isn_callback" pc))
1072
1073			     (if (eq pc (hcr-le))
1074				 (set (hcr-lc) (sub (hcr-lc) #x1)))
1075			     (if (and
1076				   (eq pc (hcr-le))
1077				   (not (eq (hcr-lc) #x0)))
1078				 (set pc (hcr-ls)))
1079			     )
1080		   )
1081	 null_b)
1082    )
1083  )
1084
1085
1086
1087
1088
1089;; Some handy macros
1090;;
1091
1092;; define instructions
1093;;   Short (16 bit forms) must appear first so that instruction
1094;;   selection can reject them and match long forms when registers
1095;;   or immediates exceed the values in the 16 bit instructions
1096
1097
1098;; B<COND> SIMM8
1099;; B<COND> SIMM24
1100
1101(define-pmacro (br-insn name cond g-op)
1102  (begin
1103					; the 16-bit versions of branch
1104    (dni (.sym "b" name "16")
1105	 (.str "Conditional Branch - 16 bit" name)
1106	 (COND-CTI SHORT-INSN)
1107	 (.str "b" name ".s $simm8")
1108	 (+ OP4_BRANCH16 (.sym "OPC_" cond) simm8)
1109	 (if (g-op)
1110	     (set pc simm8)
1111	     )
1112	 ()
1113	 )
1114
1115    (dnmi (.sym "b" name "16r") "relaxable conditional branch"
1116	  (COND-CTI RELAXABLE)
1117	  (.str "b" name " $simm8")
1118	  (emit (.sym "b" name "16") simm8)
1119	  )
1120
1121    (dni (.sym "b" name)
1122	 (.str "Conditional Branch " name)
1123	 (COND-CTI)
1124	 (.str "b" name ".l $simm24")
1125	 (+ OP4_BRANCH (.sym "OPC_" cond) simm24)
1126	 (if (g-op)
1127	     (set pc simm24)
1128	     )
1129	 ()
1130	 )
1131
1132    (dnmi (.sym "b" name "32r") "relaxable conditional branch"
1133	  (COND-CTI RELAXED)
1134	  (.str "b" name " $simm24")
1135	  (emit (.sym "b" name) simm24)
1136	  )
1137    )
1138  )
1139
1140
1141					; basic conditional branches for integer arithmetic
1142(br-insn "eq"	 EQ	(.pmacro () (eq zbit #x1)))
1143(br-insn "ne"	 NE	(.pmacro () (eq zbit #x0)))
1144(br-insn "gtu"   GTU	(.pmacro () (and BI cbit (not BI zbit))))
1145(br-insn "gteu"  GTEU	(.pmacro () (eq cbit #x1)))
1146(br-insn "lteu"  LTEU	(.pmacro () (or BI (not BI cbit) zbit)))
1147(br-insn "ltu"   LTU	(.pmacro () (eq cbit #x0)))
1148(br-insn "gt"	 GT	(.pmacro () (and BI (not BI zbit) (eq vbit nbit))))
1149(br-insn "gte"   GTE	(.pmacro () (eq vbit nbit)))
1150(br-insn "lt"	 LT	(.pmacro () (xor BI vbit nbit)))
1151(br-insn "lte"   LTE	(.pmacro () (or BI zbit (xor vbit nbit))))
1152
1153
1154					; floating point condition codes (floating point instructions)
1155(br-insn "beq"   BEQ    (.pmacro () (or BI bzbit bzbit)))
1156(br-insn "bne"   BNE    (.pmacro () (not BI bzbit)))
1157(br-insn "blt"   BLT    (.pmacro () (and BI bnbit (not bzbit))))
1158(br-insn "blte"  BLTE   (.pmacro () (or BI bnbit bzbit)))
1159
1160					; unconditional branches
1161(dni b16 "short unconditional branch" (UNCOND-CTI SHORT-INSN)
1162     "b.s $simm8"
1163     (+ OP4_BRANCH16 OPC_B simm8)
1164     (set pc simm8)
1165     ()
1166     )
1167
1168(dnmi b16r "relaxable b16"
1169      (UNCOND-CTI RELAXABLE)
1170      "b $simm8"
1171      (emit b16 simm8)
1172      )
1173
1174(dni b "long unconditional branch" (UNCOND-CTI)
1175     "b.l $simm24"
1176     (+ OP4_BRANCH OPC_B simm24)
1177     (set pc simm24)
1178     ()
1179     )
1180
1181(dnmi b32r "relaxable b"
1182      (UNCOND-CTI RELAXED)
1183      "b $simm24"
1184      (emit b simm24))
1185
1186;; BL R,ADDR
1187
1188(dni bl16 "branch and link"
1189     (UNCOND-CTI SHORT-INSN)
1190     ("bl.s $simm8")
1191     (+ OP4_BRANCH16 OPC_BL simm8)
1192     (sequence ()
1193	       (set (reg h-registers 14) (add pc (const 2)))
1194	       (set pc simm8))
1195     ()
1196     )
1197
1198(dnmi bl16r "bl16 relaxable"
1199      (UNCOND-CTI RELAXABLE)
1200      "bl $simm8"
1201      (emit bl16 simm8))
1202
1203(dni bl "branch and link"
1204     (UNCOND-CTI)
1205     ("bl.l $simm24")
1206     (+ OP4_BRANCH OPC_BL simm24)
1207     (sequence ()
1208	       (set (reg h-registers 14) (add pc (const 4)))
1209	       (set pc simm24))
1210     ()
1211     )
1212
1213(dnmi blr "bl relaxable"
1214      (UNCOND-CTI RELAXED)
1215      "bl $simm24"
1216      (emit bl simm24))
1217
1218;; JUMP <RN>
1219(dni jr16 "unconditional jump 16"
1220     (UNCOND-CTI SHORT-INSN)
1221     ("jr $rn")
1222     (+ OP4_FLOW16 (f-opc-8-5 #x14) (f-dc-15-3 #x0) (f-dc-9-1 #x0) rn)
1223     (set pc rn)
1224     ()
1225     )
1226
1227;; RTS / JR
1228;; ??? Putting a constant into a multi-ifield does not work -
1229;; the constant gets inserted in full into each part.
1230					;(dnmi rts "return from subroutine"
1231					;     (UNCOND-CTI)
1232					;     ("rts")
1233					;     (emit jr (rn6 14)) ; jr lr  / jr r14
1234					;)
1235;; RTS / JR
1236(dni rts "return from subroutine"
1237     (ALIAS UNCOND-CTI)
1238     ("rts")
1239     (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) (f-rn 6) (f-rn-x 1)
1240	(f-dc-9-1 #x0)
1241	(f-dc-15-3 #x0)
1242	(f-dc-25-6 #x0)
1243	(f-dc-31-3 #x0)
1244	)
1245     (set pc (reg h-registers 14))
1246     ()
1247     )
1248
1249(dni jr "unconditional jump"
1250     (UNCOND-CTI)
1251     ("jr $rn6")
1252     (+ OP4_MISC (f-opc-8-5 #x14) (f-opc-19-4 #x2) rn6
1253	(f-dc-9-1 #x0)
1254	(f-dc-15-3 #x0)
1255	(f-dc-25-6 #x0)
1256	(f-dc-31-3 #x0)
1257	)
1258     (set pc rn6)
1259     ()
1260     )
1261
1262
1263;; JALR <RN>
1264(dni jalr16 "jump and link register"
1265     (UNCOND-CTI SHORT-INSN)
1266     ("jalr $rn")
1267     (+ OP4_FLOW16  (f-opc-8-5 #x15) (f-dc-15-3 #x0) (f-dc-9-1 #x0)  rn)
1268     (sequence ()
1269	       (set (reg h-registers 14) (add pc (const 2)))
1270	       (set pc rn)
1271	       )
1272     ()
1273     )
1274
1275(dni jalr "jump and link register"
1276     (UNCOND-CTI)
1277     ("jalr $rn6")
1278     (+ OP4_MISC
1279	(f-opc-8-5 #x15)
1280	(f-opc-19-4 #x2)
1281	rn6
1282	(f-dc-9-1 #x0)
1283	(f-dc-15-3 #x0)
1284	(f-dc-25-6 #x0)
1285	(f-dc-31-3 #x0)
1286
1287	)
1288     (sequence ()
1289	       (set (reg h-registers 14) (add pc (const 4)))
1290	       (set pc rn6))
1291     ()
1292     )
1293
1294
1295;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1296					;  Load/Store Memory Instructions
1297;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1298
1299
1300(define-pmacro (callMisaligmentExceptionIfNeeded sel  addr isAligmentAccess)
1301  (sequence ((BI scale))
1302    (set isAligmentAccess
1303	 (case BI sel
1304	   ((OPW_BYTE)	(eq (and addr #x0) #x0))
1305	   ((OPW_SHORT)	(eq (and addr #x1) #x0))
1306	   ((OPW_WORD)	(eq (and addr #x3) #x0))
1307	   (else	(eq (and addr #x7) #x0))))
1308    (if (not BI isAligmentAccess)
1309	(call-exception #x4 #x2))
1310  )
1311)
1312
1313
1314
1315;; helper to convert size selector OPW_<mode> into a literal scale factor
1316(define-pmacro (ConvertSelectorToShift sel scale)
1317  (set scale
1318       (case SI sel
1319	 ((OPW_BYTE)	(const 0))
1320	 ((OPW_SHORT)	(const 1))
1321	 ((OPW_WORD)	(const 2))
1322	 (else	(const 3))))
1323)
1324
1325;; common load macros from effective address, handling 8/16/32/64 bits
1326(define-pmacro (load-double-from-ea regnum eff-addr mode sel)
1327  (sequence ((SI loadaddr) (BI isAligmentAccess))
1328	    (set loadaddr eff-addr)
1329	    (callMisaligmentExceptionIfNeeded sel  loadaddr isAligmentAccess)
1330
1331	    (if (not (not BI isAligmentAccess))
1332		(sequence ()
1333			  (set memaddr loadaddr)
1334			  (set regnum (mem SI loadaddr))
1335			  (set loadaddr (add loadaddr (const 4)))
1336			  (set memaddr loadaddr)
1337			  (set (reg h-registers
1338				    (add (index-of regnum)
1339					 (const 1)))
1340			       (mem SI loadaddr))
1341
1342			  )
1343		)
1344	    )
1345  )
1346
1347(define-pmacro (load-from-ea regnum eff-addr mode sel)
1348  (sequence ((BI isAligmentAccess))
1349
1350	    (callMisaligmentExceptionIfNeeded sel eff-addr   isAligmentAccess)
1351	    (if (not (not BI isAligmentAccess))
1352		(sequence ()
1353			  (set memaddr eff-addr)
1354			  (set regnum (zext SI (mem mode eff-addr)))
1355			  )
1356		)
1357	    )
1358  ) ;; 8/16/32 bit cases
1359
1360
1361;; common store to effective address, handling 8/16/32/64 bit data
1362(define-pmacro (store-double-to-ea eff-addr regnum mode sel)
1363  (sequence ((SI storeaddr) (BI isAligmentAccess))
1364	    (set storeaddr eff-addr)
1365	    (callMisaligmentExceptionIfNeeded sel storeaddr isAligmentAccess)
1366	    (if (not (not BI isAligmentAccess))
1367		(sequence ()
1368			  (set memaddr storeaddr)
1369			  (set (mem SI storeaddr) regnum)
1370			  (set storeaddr (add storeaddr (const 4)))
1371			  (set memaddr storeaddr)
1372			  (set (mem SI storeaddr)
1373			       (reg h-registers (add (index-of regnum) (const 1))))
1374			  )
1375		)
1376	    )
1377  )
1378
1379(define-pmacro (store-to-ea eff-addr regnum mode sel)
1380  (sequence ((BI isAligmentAccess))
1381	    (callMisaligmentExceptionIfNeeded sel eff-addr   isAligmentAccess)
1382	    (if (not (not BI isAligmentAccess))
1383		(sequence ()
1384			  (set memaddr eff-addr)
1385			  (set (mem mode eff-addr) regnum)
1386			  )
1387		)
1388	    )
1389  )	;8/16/32 bit cases
1390
1391
1392(define-pmacro (load-insn name mode sel sem-op)
1393  (begin
1394    (dni_wrapper (.sym name "x16.s")
1395		 (.str "load " mode " indexed")
1396		 (SHORT-INSN)
1397		 (.str name " $rd,[$rn,$rm]")
1398		 (+ OP4_LDSTR16X sel OP_LOAD rd rn rm)
1399		 (sequence ()
1400			   (sem-op rd (add rn rm) mode sel))
1401		 ()
1402		 )
1403
1404
1405    (dni_wrapper (.sym name "p16.s")
1406		 (.str "load " mode " postmodify")
1407		 (SHORT-INSN)
1408		 (.str name " $rd,[$rn],$rm")
1409		 (+ OP4_LDSTR16P sel OP_LOAD rd rn rm)
1410		 (sequence ((SI tmprm))
1411			   (set tmprm rm)
1412			   (sem-op rd rn mode sel)
1413			   (set rn (add rn tmprm)))
1414		 ()
1415		 )
1416
1417
1418    (dni_wrapper (.sym name "x.l")
1419		 (.str "load " mode " indexed")
1420		 ()
1421		 (.str name " $rd6,[$rn6,$direction$rm6]")
1422		 (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6)
1423		 (sequence ()
1424			   (if (ifield f-addsubx)
1425			       (sem-op rd6 (sub rn6 rm6) mode sel)
1426			       (sem-op rd6 (add rn6 rm6) mode sel)))
1427		 ()
1428		 )
1429
1430    (dnmi (.sym name "x")
1431	  (.str "load " mode " indexed")
1432	  (NO-DIS)
1433	  (.str name ".l $rd6,[$rn6,$direction$rm6]")
1434	  (emit  (.sym name "x.l") rd6 rn6 direction rm6)
1435	  )
1436
1437
1438
1439    (dni_wrapper (.sym name "p.l")
1440		 (.str "load " mode " postmodify")
1441		 ()
1442		 (.str name " $rd6,[$rn6],$direction$rm6")
1443		 (+ OP4_LDSTRP sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6)
1444		 (sequence ((SI tmprm))
1445			   (set tmprm rm6)
1446			   (sem-op rd6 rn6 mode sel)
1447			   (if (ifield f-addsubx)
1448			       (set rn6 (sub rn6 tmprm))
1449			       (set rn6 (add rn6 tmprm)))
1450			   )
1451		 ()
1452		 )
1453
1454
1455    (dnmi (.sym name "p")
1456	  (.str "load " mode " postmodify")
1457	  (NO-DIS)
1458	  (.str name ".l $rd6,[$rn6],$direction$rm6")
1459	  (emit  (.sym name "p.l") rd6 rn6 direction rm6)
1460	  )
1461
1462
1463    ;;immediate modes last so reg forms found first.
1464    (dni_wrapper (.sym name "d16.s")
1465		 (.str "load " mode " displacement")
1466		 (SHORT-INSN IMM3)
1467		 (.str name " $rd,[$rn,$disp3]")
1468		 (+ OP4_LDSTR16D sel OP_LOAD rd rn disp3) ;; convert size to 'B'
1469		 (sequence ((SI effa)
1470			    (SI scale))
1471			   (ConvertSelectorToShift sel scale)
1472			   (set effa (add rn (sll disp3 scale)))
1473			   (sem-op rd effa mode sel)
1474			   )
1475		 ()
1476		 )
1477
1478
1479    (dni_wrapper (.sym name "d.l")
1480		 (.str "load " mode " displacement")
1481		 ()
1482		 (.str name " $rd6,[$rn6,$dpmi$disp11]")
1483		 (+ OP4_LDSTRD sel OP_LOAD PMOD_DISP rd6 rn6 dpmi disp11)
1484		 (sequence ((SI effa)
1485			    (SI scale))
1486			   (ConvertSelectorToShift sel scale)
1487			   (if dpmi
1488			       (set effa (sub rn6 (sll disp11 scale)))
1489			       (set effa (add rn6 (sll disp11 scale)))
1490			       )
1491			   (sem-op rd6 effa mode sel)
1492			   )
1493		 ()
1494		 )
1495
1496    (dnmi (.sym name "d")
1497	  (.str "load " mode " displacement")
1498	  (NO-DIS)
1499	  (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
1500	  (emit  (.sym name "d.l") rd6 rn6  dpmi disp11)
1501	  )
1502
1503
1504
1505    (dni_wrapper (.sym name "dpm.l")
1506		 (.str "load " mode " displacement post-modify")
1507		 ()
1508		 (.str name " $rd6,[$rn6],$dpmi$disp11")
1509		 (+ OP4_LDSTRD sel OP_LOAD PMOD_POST rd6 rn6 dpmi disp11)
1510		 (sequence ((SI scale))
1511			   (ConvertSelectorToShift sel scale)
1512			   (sem-op rd6 rn6 mode sel)
1513			   (if dpmi
1514			       (set rn6 (sub rn6 (sll disp11 scale)))
1515			       (set rn6 (add rn6 (sll disp11 scale)))
1516			       )
1517			   )
1518		 ()
1519		 )
1520
1521    (dnmi (.sym name "dpm")
1522	  (.str "load " mode " displacement post-modify")
1523	  (NO-DIS)
1524	  (.str name ".l $rd6,[$rn6],$dpmi$disp11")
1525	  (emit  (.sym name "dpm.l") rd6 rn6  dpmi disp11)
1526	  )
1527
1528
1529    ;; ;; macro form with a zero displacement
1530    (dnmi (.sym name "ds0") "load with 0 disp"
1531	  (SHORT-INSN IMM3)
1532	  (.str name " $rd,[$rn]")
1533	  (emit (.sym name "d16.s") rd rn (disp3 0))
1534	  )
1535    (dnmi (.sym name "dl0") "load with 0 disp"
1536    	  (NO-DIS)
1537	  (.str name " $rd6,[$rn6]")
1538	  (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
1539	  )
1540    (dnmi (.sym name "dl0.l") "load with 0 disp"
1541    	  (NO-DIS)
1542	  (.str name ".l $rd6,[$rn6]")
1543	  (emit (.sym name "d.l") rd6 rn6 (dpmi 0) (disp11 0))
1544	  )
1545
1546
1547    )
1548  )
1549
1550(load-insn ldrb QI OPW_BYTE load-from-ea)
1551(load-insn ldrh HI OPW_SHORT load-from-ea)
1552(load-insn ldr  SI OPW_WORD  load-from-ea)
1553(load-insn ldrd DI OPW_DOUBLE load-double-from-ea)
1554
1555
1556
1557
1558;; TMP = MEM[RD+RM];    /* Copy content of memory to tmp.  */
1559;; if (~TMP)            /* Check if memory location is zero.  */
1560;;   MEM[RD+RM] = RD;   /* If zero, write RD to memory.  */
1561;; RD = TMP;            /* Always write tmp into RD (NOTE it's destructive).  */
1562
1563
1564(define-pmacro (testset-insn name mode sel)
1565  (begin
1566
1567
1568    (dni_wrapper (.sym name "t")
1569		 (.str "testset " mode " indexed")
1570		 ()
1571		 (.str name " $rd6,[$rn6,$direction$rm6]")
1572		 (+ OP4_LDSTRX sel OP_LOAD (f-opc-19-4 #x0) (f-dc-22-1 #x0) (f-dc-21-1 #x1)
1573		    rd6 rn6 direction rm6)
1574		 (sequence ((SI tmemaddr) (SI tmpValReg))
1575
1576			   ;;back up register
1577			   (set tmpValReg rd6)
1578
1579			   (if (ifield f-addsubx)
1580			       (set  tmemaddr  (sub rn6 rm6))
1581			       (set  tmemaddr  (add rn6 rm6))
1582			       )
1583			   ;;always update rd
1584			   (load-from-ea rd6 tmemaddr  mode sel)
1585			   ;;if zero
1586			   (if  rd6
1587				(nop)
1588				(set (mem mode tmemaddr) tmpValReg)
1589				)
1590
1591			   )
1592		 ()
1593		 )
1594
1595
1596    (dnmi  (.sym name "t.l")
1597	   (.str "testset " mode ".l indexed")
1598	   (NO-DIS)
1599	   (.str name ".l $rd6,[$rn6,$direction$rm6]")
1600	   (emit (.sym name "t") rd6 rn6 direction rm6)
1601	   )
1602
1603
1604    )
1605  )
1606
1607(testset-insn testsetb QI OPW_BYTE)
1608(testset-insn testseth HI OPW_SHORT)
1609(testset-insn testset  SI OPW_WORD)
1610;;no double mode support, since we have to send the src address, data
1611;;(testset-insn testsetd DI OPW_DOUBLE load-double-from-ea)
1612
1613
1614
1615;; need 16 bit forms too
1616(define-pmacro (store-insn name mode sel sem-op)
1617  (begin
1618    (dni_wrapper (.sym name "x16")
1619		 (.str "store" mode " indexed")
1620		 (SHORT-INSN)
1621		 (.str name " $rd,[$rn,$rm]")
1622		 (+ OP4_LDSTR16X sel OP_STORE rd rn rm)
1623		 (sequence ()
1624			   (sem-op (add rn rm) rd mode sel)
1625			   )
1626		 ()
1627		 )
1628
1629    (dni_wrapper (.sym name "x")
1630		 (.str "store" mode " indexed")
1631		 ()
1632		 (.str name " $rd6,[$rn6,$direction$rm6]")
1633		 (+ OP4_LDSTRX sel OP_STORE (f-opc-19-4 #x0)  (f-dc-22-1 #x0) (f-dc-21-1 #x0) rd6 rn6 direction rm6)
1634		 (sequence ()
1635			   (if (ifield f-addsubx)
1636			       (sem-op (sub rn6 rm6) rd6 mode sel)
1637			       (sem-op (add rn6 rm6) rd6 mode sel)
1638			       ))
1639		 ()
1640		 )
1641
1642    (dnmi (.sym name "x.l")
1643	  (.str "store" mode " indexed")
1644	  (NO-DIS)
1645	  (.str name ".l $rd6,[$rn6,$direction$rm6]")
1646	  (emit  (.sym name "x")  rd6 rn6 direction rm6)
1647	  )
1648
1649
1650
1651
1652
1653    (dni_wrapper (.sym name "p16")
1654		 (.str "store " mode " postmodify")
1655		 (SHORT-INSN)
1656		 (.str name " $rd,[$rn],$rm")
1657		 (+ OP4_LDSTR16P sel OP_STORE rd rn rm)
1658		 (sequence ()
1659			   (sem-op rn rd mode sel)
1660			   (set rn (add rn rm))
1661			   )
1662		 ()
1663		 )
1664
1665    (dni_wrapper (.sym name "p")
1666		 (.str "store " mode " postmodify")
1667		 ()
1668		 (.str name " $rd6,[$rn6],$direction$rm6")
1669		 (+ OP4_LDSTRP sel OP_STORE (f-opc-19-4 #x0) (f-dc-22-2 #x0) rd6 rn6 direction rm6)
1670		 (sequence ()
1671			   (sem-op rn6 rd6 mode sel)
1672			   (if (ifield f-addsubx)
1673			       (set rn6	(sub rn6 rm6))
1674			       (set rn6 (add rn6 rm6)))
1675			   )
1676		 ()
1677		 )
1678    (dnmi (.sym name "p.l")
1679	  (.str "store " mode " postmodify")
1680	  (NO-DIS)
1681	  (.str name ".l $rd6,[$rn6],$direction$rm6")
1682	  (emit (.sym name "p") rd6 rn6 direction rm6)
1683	  )
1684
1685    (dni_wrapper (.sym name "d16")
1686		 (.str "store " mode " displacement")
1687		 (SHORT-INSN IMM3)
1688		 (.str name " $rd,[$rn,$disp3]")
1689		 (+ OP4_LDSTR16D sel OP_STORE rd rn disp3) ;; convert size to 'B'
1690		 (sequence ((SI effa)
1691			    (SI scale))
1692			   (ConvertSelectorToShift sel scale)
1693			   (set effa (add rn (sll disp3 scale)))
1694			   (sem-op effa rd mode sel)
1695			   )
1696		 ()
1697		 )
1698
1699    (dni_wrapper (.sym name "d")
1700		 (.str "store " mode " displacement")
1701		 ()
1702		 (.str name " $rd6,[$rn6,$dpmi$disp11]")
1703		 (+ OP4_LDSTRD sel OP_STORE PMOD_DISP rd6 rn6 dpmi disp11)
1704		 (sequence ((SI effa)
1705			    (SI scale))
1706			   (ConvertSelectorToShift sel scale)
1707			   (if dpmi
1708			       (set effa (sub rn6 (sll disp11 scale)))
1709			       (set effa (add rn6 (sll disp11 scale)))
1710			       )
1711			   (sem-op effa rd6 mode sel)
1712			   )
1713		 ()
1714		 )
1715
1716    (dnmi (.sym name "d.l")
1717	  (.str "store " mode " displacement")
1718	  (NO-DIS)
1719	  (.str name ".l $rd6,[$rn6,$dpmi$disp11]")
1720	  (emit (.sym name "d") rd6 rn6 dpmi disp11)
1721	  )
1722
1723
1724    (dni_wrapper (.sym name "dpm")
1725		 (.str "store " mode " displacement post-modify")
1726		 ()
1727		 (.str name " $rd6,[$rn6],$dpmi$disp11")
1728		 (+ OP4_LDSTRD sel OP_STORE PMOD_POST rd6 rn6 dpmi disp11) ;; convert size to 'B'
1729		 (sequence ((SI scale))
1730			   (ConvertSelectorToShift sel scale)
1731			   (sem-op rn6 rd6 mode sel)
1732			   (if dpmi
1733			       (set rn6 (sub rn6 (sll disp11 scale)))
1734			       (set rn6 (add rn6 (sll disp11 scale)))
1735			       )
1736			   )
1737		 ()
1738		 )
1739    (dnmi (.sym name "dpm.l")
1740	  (.str "store " mode " displacement post-modify")
1741	  (NO-DIS)
1742	  (.str name ".l $rd6,[$rn6],$dpmi$disp11")
1743	  (emit (.sym name "dpm") rd6 rn6 dpmi disp11)
1744	  )
1745
1746    ;; macro form with a zero displacement
1747    (dnmi (.sym name "ds0") "store w 0 disp"
1748	  (SHORT-INSN IMM3)
1749	  (.str name " $rd,[$rn]")
1750	  (emit (.sym name "d16") rd rn (disp3 0))
1751	  )
1752
1753    (dnmi (.sym name "dl0")  "store w 0 disp"
1754	  ()
1755	  (.str name " $rd6,[$rn6]")
1756	  (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0))
1757	  )
1758
1759    (dnmi (.sym name "dl0.l")  "store w 0 disp"
1760	  (NO-DIS)
1761	  (.str name ".l $rd6,[$rn6]")
1762	  (emit (.sym name "d") rd6 rn6 (dpmi 0) (disp11 0))
1763	  )
1764
1765
1766
1767    )
1768  )
1769
1770(store-insn strb QI OPW_BYTE store-to-ea)
1771(store-insn strh HI OPW_SHORT store-to-ea)
1772(store-insn str  SI OPW_WORD store-to-ea)
1773(store-insn strd DI OPW_DOUBLE store-double-to-ea)
1774
1775;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1776;; MOV<COND> RD,RN
1777;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1778
1779(define-pmacro (move-insns name cond g-op)
1780  (begin
1781    (dni_wrapper (.sym "cmov16" cond)
1782		 (.str "move register " cond)
1783		 (SHORT-INSN)
1784		 (.str "mov" name " $rd,$rn")
1785		 (+ OP4_FLOW16 (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) rd rn)
1786		 (if (g-op)
1787		     (set rd rn))
1788		 ()
1789		 )
1790
1791    (dni_wrapper (.sym "cmov" cond)
1792		 (.str "move register " cond)
1793		 ()
1794		 (.str "mov" name " $rd6,$rn6")
1795		 (+ OP4_MISC (.sym "OPC_" cond) (f-opc-8-1 #x0) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-6 #x0) rd6 rn6)
1796		 (if (g-op)
1797		     (set rd6 rn6))
1798		 ()
1799		 )
1800    (dnmi (.sym "cmov.l" cond)
1801	  (.str "move register " cond)
1802	  (NO-DIS)
1803	  (.str "mov" name ".l $rd6,$rn6")
1804	  (emit (.sym "cmov" cond) rd6 rn6)
1805	  )
1806
1807
1808
1809    )
1810  )
1811
1812					; basic conditional moves
1813(move-insns "eq"    EQ	   (.pmacro () (eq zbit #x1)))
1814(move-insns "ne"    NE	   (.pmacro () (eq zbit #x0)))
1815(move-insns "gtu"   GTU	   (.pmacro () (and BI cbit (not BI zbit))))
1816(move-insns "gteu"  GTEU   (.pmacro () (eq cbit #x1)))
1817(move-insns "lteu"  LTEU   (.pmacro () (or BI (not BI cbit) zbit)))
1818(move-insns "ltu"   LTU	   (.pmacro () (eq cbit #x0)))
1819(move-insns "gt"    GT	   (.pmacro () (and BI (not BI zbit) (eq vbit nbit))))
1820(move-insns "gte"   GTE	   (.pmacro () (eq vbit nbit)))
1821(move-insns "lt"    LT	   (.pmacro () (xor BI vbit nbit)))
1822(move-insns "lte"   LTE	   (.pmacro () (or BI zbit (xor vbit nbit))))
1823
1824					; unconditional move
1825(move-insns ""      B      (.pmacro () #x1))
1826
1827
1828					; floating point condition codes (floating point instructions)
1829(move-insns "beq"   BEQ    (.pmacro () (or BI bzbit bzbit)))
1830(move-insns "bne"   BNE    (.pmacro () (not BI bzbit)))
1831(move-insns "blt"   BLT    (.pmacro () (and BI bnbit (not bzbit))))
1832(move-insns "blte"  BLTE   (.pmacro () (or BI bnbit bzbit)))
1833
1834;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1835;; MOVTS RD,RN
1836;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1837
1838;; 16 bits form exists for group zero ( M1 and M0 equals to zero ) only
1839
1840(dni_wrapper movts16
1841	     "move to special reg"
1842	     (SHORT-INSN)
1843	     "movts $sn,$rd"
1844	     (+ OP4_FLOW16 (f-opc-8-5 #x10) (f-dc-9-1 #x0) rd sn) ;; rd is source for movts
1845	     (set sn rd)
1846	     ()
1847	     )
1848
1849(define-pmacro (op-mmr-movts name sdreg code)
1850  (begin
1851
1852    (dni_wrapper (.sym "movts" name)
1853		 (.str "move to " name)
1854		 ()
1855		 (.str "movts $" sdreg ",$rd6")
1856		 (+ OP4_MISC (f-dc-7-4 #x0) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) sdreg rd6);; rd is source for movts
1857		 (set sdreg rd6)
1858		 ()
1859		 )
1860
1861    (dnmi (.sym "movts.l" name)
1862	  (.str "move to " name)
1863	  (NO-DIS)
1864	  (.str "movts.l $" sdreg ",$rd6")
1865	  (emit (.sym "movts" name) sdreg rd6)
1866	  )
1867
1868
1869
1870
1871    )
1872  )
1873
1874(op-mmr-movts  6    sn6    #x0)
1875(op-mmr-movts  dma  sndma  #x1)
1876(op-mmr-movts  mem  snmem  #x2)
1877(op-mmr-movts  mesh snmesh #x3)
1878
1879;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1880;; MOVFS
1881;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1882(dni_wrapper movfs16
1883	     "move from special register"
1884	     (SHORT-INSN)
1885	     "movfs $rd,$sn"
1886	     (+ OP4_FLOW16 (f-opc-8-5 #x11) (f-dc-9-1 #x0) rd sn)
1887	     (set rd sn)
1888	     ()
1889	     )
1890
1891
1892
1893(define-pmacro (op-mmr-movfs name snreg code)
1894  (begin
1895
1896    (dni_wrapper (.sym "movfs" name)
1897		 (.str "move from " name)
1898		 ()
1899		 (.str "movfs $rd6,$" snreg)
1900		 (+ OP4_MISC (f-dc-7-4 #x1) (f-opc-8-1 #x1) (f-dc-9-1 #x0) (f-opc-19-4 #x2) (f-dc-25-4 #x0) (f-dc-21-2 code) rd6 snreg)
1901		 (set rd6 snreg)
1902		 ()
1903		 )
1904
1905    (dnmi (.sym "movfs.l" name)
1906	  (.str "move from " name)
1907	  (NO-DIS)
1908	  (.str "movfs.l $rd6,$" snreg)
1909	  (emit (.sym "movfs" name) rd6 snreg)
1910	  )
1911
1912
1913
1914    )
1915  )
1916
1917(op-mmr-movfs  6    sn6    #x0)
1918(op-mmr-movfs  dma  sndma  #x1)
1919(op-mmr-movfs  mem  snmem  #x2)
1920(op-mmr-movfs  mesh snmesh #x3)
1921
1922
1923
1924
1925
1926;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1927;; NOP 0x1a2
1928;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1929(dni_wrapper nop
1930	     "no-operation"
1931	     (SHORT-INSN)
1932	     "nop"
1933	     (+ OP4_FLOW16 (f-opc-8-5 #x1a) (f-dc-15-7 #x0))
1934	     (nop)
1935	     ()
1936	     )
1937
1938
1939;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1940;; SNOP 0x3a2
1941;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1942(dni_wrapper snop
1943	     "no-operation"
1944	     (SHORT-INSN)
1945	     "snop"
1946	     (+ OP4_FLOW16 (f-opc-8-5 #x3a) (f-dc-15-7 #x0))
1947	     (nop)
1948	     ()
1949	     )
1950
1951
1952;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1953;; UNIMPL
1954;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1955(dni_wrapper unimpl
1956	     "not-implemented"
1957	     ()
1958	     "unimpl"
1959	     (+ (f-opc-31-32  #x000F000F))
1960	     (nop)
1961	     ()
1962	     )
1963
1964;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1965;; IDLE
1966;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1967
1968(dni idle "idle until interrupt" () "idle"
1969     (+ OP4_FLOW16 (f-opc-8-5 #x1b) (f-dc-15-7 #x0))
1970     ;;     (set pc pc)	;; should branch to self until interrupt, but not modeling interrupts
1971     (sequence ()
1972       (set caibit 0)
1973       (c-code "sim_engine_halt (CPU_STATE (current_cpu), current_cpu, NULL, \
1974		pc, sim_exited, 0);"))
1975     ()
1976     )
1977
1978;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1979;; BKPT
1980;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1981
1982(dni bkpt
1983     "breakpoint"
1984     (SHORT-INSN)
1985     "bkpt"
1986     (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x0))
1987     (sequence ()
1988     	 (c-call  "epiphany_break" pc)
1989     	(set pc pc)
1990     	)
1991     ()
1992     )
1993
1994;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1995;; MBKPT
1996;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1997
1998(dni mbkpt
1999     "multicorebreakpoint"
2000     (SHORT-INSN)
2001     "mbkpt"
2002     (+ OP4_FLOW16 (f-opc-8-5 #x1c) (f-dc-15-7 #x1))
2003     ;;;(c-call "epiphany_break" pc)
2004     (nop) ;; ignore the multi core break point in the simulator
2005     ()
2006     )
2007
2008;;;;;;;;;;;;;;;;
2009;; RTI
2010;;;;;;;;;;;;;;;;
2011
2012(dni rti "return from interrupt" (SHORT-INSN UNCOND-CTI)
2013     "rti"
2014     (+ OP4_FLOW16 (f-opc-8-5 #x1d) (f-dc-15-7 #x0))
2015     (sequence ()
2016	       ;; 	(set (hcr-ipend)
2017	       ;; 	     (xor (hcr-ipend)
2018	       ;; 		  (sll (const 1)
2019	       ;; 		       (sub (c-raw-call SI "ffs" (and (hcr-ipend) (not (hcr-imask))))
2020	       ;; 			    (const 1)))))
2021
2022	       (set (hcr-ipend)
2023		    (c-call SI "epiphany_rti" (hcr-ipend) (hcr-imask)))
2024	       (set gidisablebit 0)
2025	       (set kmbit 0)
2026					;(set caibit 1)
2027	       (set pc (hcr-iret)))
2028     ()
2029     )
2030;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2031;; WAND is a wired flag that runs around the chip
2032;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2033(dni_wrapper wand     "wand"
2034	     (SHORT-INSN)
2035	     "wand"
2036	     (+ OP4_FLOW16 (f-opc-8-5 #x18) (f-dc-15-7 #x0))
2037	     (set sflagbit 1)
2038	     ()
2039	     )
2040
2041;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2042;; Sync likes wand, but wired OR
2043;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2044(dni_wrapper sync     "sync"
2045	     (SHORT-INSN)
2046	     "sync"
2047	     (+ OP4_FLOW16 (f-opc-8-5 #x1f) (f-dc-15-7 #x0))
2048	     (nop);;TODO
2049	     ()
2050	     )
2051
2052;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2053;; GIE
2054;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2055(dni_wrapper gien     "global interrupt enable"
2056	     (SHORT-INSN)
2057	     "gie"
2058	     (+ OP4_FLOW16 (f-gien-gidis-9-1 #x0) (f-opc-8-5 #x19) (f-dc-15-6 #x0))
2059	     (set gidisablebit 0)
2060	     ()
2061	     )
2062
2063;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2064;; GIDIS
2065;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2066(dni_wrapper gidis     "global interrupt disable"
2067	     (SHORT-INSN)
2068	     "gid"
2069	     (+ OP4_FLOW16 (f-gien-gidis-9-1 #x1) (f-opc-8-5 #x19) (f-dc-15-6 #x0))
2070	     (set gidisablebit 1)
2071	     ()
2072	     )
2073
2074
2075
2076;;;;;;;;;;;;;;;;
2077;; SWI
2078;;;;;;;;;;;;;;;;
2079
2080;; Model only immediate 'fire' exception, if gien cleared or masked don't fire and don't check later - no ilat like behavior
2081(dni swi_num "software interrupt" (SHORT-INSN UNCOND-CTI)
2082     "swi $swi_num"
2083     (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0)  swi_num)
2084     (sequence ()  (call-exception #x24  #x80))
2085     ;;      (if (eq gie 1)
2086     ;; 	 (sequence ()
2087     ;; 		   (set kmbit 1)
2088     ;; 		   (set gie 0)
2089     ;; 		   (set (hcr-iret) (add pc (const 2)))
2090     ;; 		   (set (hcr-ipend) (or (hcr-ipend) (const #x80)))
2091     ;; 		   (set pc (const #x1c))
2092
2093     ;; 			   )
2094     ;; 	 ;; schedule interrupt
2095     ;; 	 (set (hcr-ilat) (or (hcr-ilat) (const #x80)))
2096     ;; 	 )
2097     ()
2098     )
2099(dni swi "software interrupt" (ALIAS SHORT-INSN UNCOND-CTI)
2100     "swi"
2101     (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x0) (f-dc-15-6 #x0))
2102     (sequence ()  (call-exception #x24  #x80))
2103     ()
2104     )
2105
2106
2107;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2108;; TRAP #disp3 - simulator only and chip as well - make the same grouop as swi
2109;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2110
2111;; Only defining 16-bit form of this instruction.  It exists to support the
2112;; simulator, by giving us a simple input/output mechanism beyond returning values
2113;; in registers or memory.
2114;; TRAP #N  - special sw trap for simulator support;  allows simple i/o using fixed arguments
2115;; TRAP #0  - write (r0=i/o channel, r1=addr, r2=len) returns status in r0
2116;; TRAP #1  - read  (r0=i/o channel, r1=addr, r2=len) returns length or -<code> on error
2117;; TRAP #2  - open  (r0=string path, r1=mode) returns channel# or -<code> on error
2118;; TRAP #3  - exit  (r0=status code) never returns.
2119;; TRAP #4  - print "pass\n" and exit
2120;; TRAP #5  - print "fail\n" and exit
2121;; TRAP #6  - close  (r0=i/o channel)
2122
2123(dni trap16 "trap to simulator"
2124     (SHORT-INSN UNCOND-CTI)
2125     "trap $trapnum6"
2126     (+ OP4_FLOW16 (f-opc-8-5 #x1e) (f-trap-swi-9-1 #x1)  trapnum6) ;;  (+ OP4_IMM16 OPI_TRAP (f-rd 0) (f-rn 0) disp3)
2127     (set (reg SI h-registers 0) (c-call SI "epiphany_trap" pc trapnum6))
2128     ()
2129     )
2130
2131
2132;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2133;; Integer arithmetic instructions 3 address forms
2134;;   both 16 and 32 bit forms
2135;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2136
2137(define-pmacro (op-rrr name sem-op cond-op)
2138  (begin
2139    (dni_wrapper (.sym name "16")
2140		 (.str name)
2141		 (SHORT-INSN)
2142		 (.str name " $rd,$rn,$rm")
2143		 (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
2144		 (sequence ()
2145			   (cond-op rn rm)
2146			   (set rd (sem-op SI rn rm))
2147			   (set zbit (zflag rd))
2148			   (set nbit (nflag rd))
2149			   )
2150		 ()
2151		 )
2152
2153    (dni_wrapper (.sym name)
2154		 (.str name)
2155		 ()
2156		 (.str name " $rd6,$rn6,$rm6")
2157		 (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6)
2158		 (sequence ()
2159			   (cond-op rn6 rm6)
2160			   (set rd6 (sem-op SI rn6 rm6))
2161			   (set zbit (zflag rd6))
2162			   (set nbit (nflag rd6))
2163			   )
2164		 ()
2165		 )
2166
2167    (dnmi (.sym name ".l")
2168	  (.str name)
2169	  (NO-DIS)
2170	  (.str name ".l $rd6,$rn6,$rm6")
2171	  (emit (.sym name) rd6 rn6 rm6)
2172	  )
2173
2174
2175
2176    )
2177  )
2178
2179;; submacros to set condition codes
2180;;  NZ are always set to reflect the sign and value of the result
2181;;  CV are a function of the operator
2182(define-pmacro (add-vc a b) (sequence ()
2183				      (set cbit (add-cflag SI a b 0))
2184				      (set vbit (add-oflag SI a b 0))
2185				      (set vsbit (or BI vsbit vbit))
2186				      ))
2187
2188(define-pmacro (sub-vc a b) (sequence ()
2189				      (set cbit (not (sub-cflag SI a b 0)))
2190				      (set vbit (sub-oflag SI a b 0))
2191				      (set vsbit (or vsbit vbit))
2192				      ))
2193
2194(define-pmacro (logic-vc a b) (sequence ()
2195					(set cbit 0)
2196					(set vbit 0)
2197					))
2198
2199(op-rrr add add add-vc)
2200(op-rrr sub sub sub-vc)
2201(op-rrr and and logic-vc)
2202(op-rrr orr  or  logic-vc)
2203(op-rrr eor xor logic-vc)
2204
2205;; Integer arithmetic immediate forms
2206
2207(define-pmacro (op-rri name code cond-op)
2208  (begin
2209    (dni_wrapper (.sym name "i16")
2210		 (.str name)
2211		 (SHORT-INSN IMM3)
2212		 (.str name ".s $rd,$rn,$simm3")
2213		 (+ OP4_IMM16 code rd rn simm3)
2214		 (sequence ()
2215			   (cond-op rn simm3)
2216			   (set rd (name SI rn simm3))
2217			   (set zbit (zflag rd))
2218			   (set nbit (nflag rd))
2219			   )
2220		 ()
2221		 )
2222
2223
2224    (dni_wrapper (.sym name "i")
2225		 (.str name)
2226		 ()
2227		 (.str name ".l $rd6,$rn6,$simm11")
2228		 (+ OP4_IMM32 code OPI_25_2_MBZ rd6 rn6 simm11)
2229		 (sequence ()
2230			   (cond-op rn6 simm11)
2231			   (set rd6 (name SI rn6 simm11))
2232			   (set zbit (zflag rd6))
2233			   (set nbit (nflag rd6))
2234			   )
2235		 ()
2236		 )
2237
2238    ;;    (dnmi (.sym name "ri") "relaxed arithmetic immediate" (RELAXED)
2239    ;;	  (.str name " $rd6,$rn6,$simm11")
2240    ;;	  (emit (.sym name "i") rd6 rn6 simm11))
2241    )
2242  )
2243
2244(op-rri add OPI_ADD add-vc)
2245(op-rri sub OPI_SUB sub-vc)
2246
2247(dnmi addir "relaxable short immediate add" (RELAXABLE IMM3)
2248      "add $rd,$rn,$simm3"
2249      (emit addi16 rd rn simm3))
2250
2251(dnmi addi32r "relaxed long immediate add" (RELAXED)
2252      "add $rd6,$rn6,$simm11"
2253      (emit addi rd6 rn6 simm11))
2254
2255;; Again, but not relaxable so that full sized registers are handled
2256(dnmi addi32m "relaxed long immediate add" ()
2257      "add $rd6,$rn6,$simm11"
2258      (emit addi rd6 rn6 simm11))
2259
2260
2261(dnmi subir "relaxable short immediate sub" (RELAXABLE IMM3)
2262      "sub $rd,$rn,$simm3"
2263      (emit subi16 rd rn simm3))
2264
2265(dnmi subi32r "relaxed long immediate sub" (RELAXED)
2266      "sub $rd6,$rn6,$simm11"
2267      (emit subi rd6 rn6 simm11))
2268
2269(dnmi subi32m "relaxed long immediate sub" ()
2270      "sub $rd6,$rn6,$simm11"
2271      (emit subi rd6 rn6 simm11))
2272
2273
2274;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2275;; Shift instructions 3 address forms
2276;;   both 16 and 32 bit forms
2277;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2278
2279(define-pmacro (shift-rrr name sem-op)
2280  (begin
2281    (dni_wrapper (.sym name "16")
2282		 (.str name)
2283		 (SHORT-INSN)
2284		 (.str name " $rd,$rn,$rm")
2285		 (+ OP4_ALU16 (.sym "OPB_" (.upcase (.str name))) rd rn rm)
2286		 (sequence ()
2287			   (logic-vc rn rm)
2288			   (set rd (sem-op SI rn (and rm (const 31))))
2289			   (set zbit (zflag rd))
2290			   (set nbit (nflag rd))
2291			   )
2292		 ()
2293		 )
2294
2295    (dni_wrapper (.sym name)
2296		 (.str name)
2297		 ()
2298		 (.str name " $rd6,$rn6,$rm6")
2299		 (+ OP4_MISC (.sym "OPB_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-3 #x0) rd6 rn6 rm6)
2300		 (sequence ()
2301			   (logic-vc rn6 rm6)
2302			   (set rd6 (sem-op SI rn6 (and rm6 (const 31))))
2303			   (set zbit (zflag rd6))
2304			   (set nbit (nflag rd6))
2305			   )
2306		 ()
2307		 )
2308
2309    (dnmi (.sym name ".l")
2310	  (.str name)
2311	  (NO-DIS)
2312	  (.str name ".l $rd6,$rn6,$rm6")
2313	  (emit (.sym name) rd6 rn6 rm6)
2314	  )
2315    )
2316  )
2317
2318(shift-rrr asr sra)
2319(shift-rrr lsr srl)
2320(shift-rrr lsl sll)
2321
2322(define-pmacro (op-shift-rri name shortcode f5 longcode sem-op)
2323  (begin
2324    (dni_wrapper (.sym name "i16")
2325		 (.str name)
2326		 (SHORT-INSN)
2327		 (.str name " $rd,$rn,$shift")
2328		 (+ shortcode (f-opc-4-1 f5) rd rn shift)
2329		 (sequence ()
2330			   (logic-vc rn shift)
2331			   (set rd (sem-op SI rn shift))
2332			   (set zbit (zflag rd))
2333			   (set nbit (nflag rd))
2334			   )
2335		 ()
2336		 )
2337    (dni_wrapper (.sym name "i32")
2338		 (.str name)
2339		 ()
2340		 (.str name " $rd6,$rn6,$shift")
2341		 (+ OP4_MISC (f-opc-4-1 f5) (f-opc-19-4 longcode) (f-dc-25-6 0) rd6 rn6 shift)
2342		 (sequence ()
2343			   (logic-vc rn6 shift)
2344			   (set rd6 (sem-op SI rn6 shift))
2345			   (set zbit (zflag rd6))
2346			   (set nbit (nflag rd6))
2347			   )
2348		 ()
2349		 )
2350
2351    (dnmi (.sym name "i32.l")
2352	  (.str name)
2353	  (NO-DIS)
2354	  (.str name ".l $rd6,$rn6,$shift")
2355	  (emit (.sym name "i32") rd6  rn6 shift)
2356	  )
2357
2358
2359    )
2360  )
2361
2362(op-shift-rri lsr OP4_LSHIFT16 0 #x6 srl)
2363(op-shift-rri lsl OP4_LSHIFT16 1 #x6 sll)
2364(op-shift-rri asr OP4_ASHIFT16 0 #xe sra)
2365
2366;; BITR - bitreversal (FFT)
2367;;
2368;; From Dr Dobbs et al.
2369;;
2370;; unsigned int v;
2371;; v = ((v >> 1) & 0x55555555) | ((v & 0x55555555) << 1);  ;; swap odd-even bits
2372;; v = ((v >> 2) & 0x33333333) | ((v & 0x33333333) << 2);  ;; swap pairs
2373;; v = ((v >> 4) & 0x0f0f0f0f) | ((v & 0x0f0f0f0f) << 4);  ;; swap nibbles
2374;; v = ((v >> 8) & 0x00ff00ff) | ((v & 0x00ff00ff) << 8);  ;; swap bytes
2375;; v =  (v >> 16)              |  (v               << 16); ;; swap halves
2376(define-pmacro (bit-reversal dest src)
2377  (sequence ((SI v))
2378	    (set v src)
2379	    (set v (or (and (srl v 1) #x55555555) (sll (and v #x55555555) 1)))
2380	    (set v (or (and (srl v 2) #x33333333) (sll (and v #x33333333) 2)))
2381	    (set v (or (and (srl v 4) #x0f0f0f0f) (sll (and v #x0f0f0f0f) 4)))
2382	    (set v (or (and (srl v 8) #x00ff00ff) (sll (and v #x00ff00ff) 8)))
2383	    (set v (or      (srl v 16)            (sll      v            16)))
2384	    (set dest v)
2385	    ))
2386
2387(dni_wrapper bitr16 "bit reverse short"
2388	     (SHORT-INSN)
2389	     ("bitr $rd,$rn")
2390	     (+ OP4_ASHIFT16 (f-opc-4-1 1) rd rn (f-shift 0))
2391	     (sequence ()
2392		       (bit-reversal rd rn)
2393		       (set zbit (zflag rd))
2394		       (set nbit (nflag rd))
2395		       (set cbit 0)
2396		       (set vbit 0)
2397		       )
2398	     ()
2399	     )
2400
2401(dni_wrapper bitr "bit reverse"
2402	     ()
2403	     ("bitr $rd6,$rn6")
2404	     (+ OP4_MISC (f-opc-4-1 1) (f-opc-19-4 #xe) (f-dc-25-6 0) rd6 rn6 (f-shift 0))
2405	     (sequence ()
2406		       (bit-reversal rd6 rn6)
2407		       (set zbit (zflag rd6))
2408		       (set nbit (nflag rd6))
2409		       (set cbit 0)
2410		       (set vbit 0)
2411		       )
2412	     ()
2413	     )
2414(dnmi bitrl "bit reverse l"
2415      (NO-DIS)
2416      ("bitr.l $rd6,$rn6")
2417      (emit bitr rd6 rn6)
2418      )
2419
2420;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2421;; Integer arithmetic instructions
2422;; Extended operation
2423;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2424
2425(define-pmacro (op-iextrrr  name  cond-op)
2426  (begin
2427
2428    (dni_wrapper (.sym name)
2429		 (.str name)
2430		 ()
2431		 (.str name " $rd6,$rn6,$rm6")
2432		 (+ OP4_MISC (.sym "OPBE_" (.upcase (.str name))) (f-opc-19-4 #xa) (f-dc-22-2 #x0)  (f-dc-20-1 #x1)
2433		    rd6 rn6 rm6)
2434		 (sequence ()
2435			   ;;  TODO cond operation (cond-op rn6 rm6)
2436			   ;;(set rd6 (sem-op SI rn6 rm6))
2437			   (set zbit (zflag rd6))
2438			   (set nbit (nflag rd6))
2439			   )
2440		 ()
2441		 )
2442
2443    (dnmi (.sym name ".l")
2444	  (.str name)
2445	  (NO-DIS)
2446	  (.str name ".l $rd6,$rn6,$rm6")
2447	  (emit (.sym name) rd6  rn6 rm6)
2448	  )
2449    )
2450  )
2451
2452(op-iextrrr fext  sub-vc)
2453(op-iextrrr fdep  sub-vc)
2454(op-iextrrr lfsr  sub-vc)
2455
2456
2457
2458;; Immediate moves.  The 8 bit form is relaxed if it doesn't fit or is external
2459;; Move RD,#IMM
2460(dni_wrapper mov8
2461	     "mov imm8"
2462	     (SHORT-INSN)
2463	     "mov.b $rd,$imm8"
2464	     (+ OP4_IMM16 (f-opc-4-1 #x0) rd imm8)
2465	     (set rd (zext SI imm8))
2466	     ()
2467	     )
2468
2469(dnmi mov8r "mov imm8 relaxable"
2470      (RELAXABLE)
2471      "mov $rd,$imm8"
2472      (emit mov8 rd imm8))
2473
2474(dni_wrapper mov16
2475	     "mov imm16"
2476	     ()
2477	     "mov.l $rd6,$imm16"
2478	     (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x0) rd6 imm16)
2479	     (set rd6 (zext SI imm16))
2480	     ()
2481	     )
2482
2483(dnmi mov16r "mov imm16 relaxable"
2484      ()
2485      "mov $rd6,$imm16"
2486      (emit mov16 rd6 imm16))
2487
2488;; MOVE TO HIGH WORD
2489(dni_wrapper movt
2490	     "movt imm16"
2491	     ()
2492	     "movt $rd6,$imm16"
2493	     (+ OP4_IMM32 (f-opc-4-1 #x0) (f-opc-19-4 #x2) (f-dc-28-1 #x1) rd6 imm16)
2494	     (set rd6 (or (and SI rd6 (const #xffff)) ; keep low bits of rd
2495			  (sll SI imm16 (const 16)))) ; replacing just high bits
2496	     ()
2497	     )
2498(dnmi movtl
2499      "movt imm16"
2500      (NO-DIS)
2501      "movt.l $rd6,$imm16"
2502      (emit movt rd6 imm16)
2503      )
2504
2505
2506
2507;; FLOATING POINT OPERATIONS
2508;; TWO operands
2509(define-pmacro (op-two_operands-float name code)
2510  (begin
2511    (dni_wrapper
2512      (.sym "f_" name "f16")
2513      (.str "f_" name)
2514      (SHORT-INSN)
2515      (.str "f" name " $rd,$rn,$rm")
2516      (+ OP4_DSP16 code rd rn rm)
2517      (sequence ()
2518	(if
2519	  (eq  arithmetic-modebit2 0)
2520	  (sequence ((SF fptemp) (SI sdtmp))
2521	    (set sdtmp  (c-call SI (.str "epiphany_f" name) rd rn rm))
2522
2523	    ;;All bits are calculated in C
2524	    (set bzbit  (c-call BI "get_epiphany_fzeroflag" sdtmp))
2525	    (set bnbit  (c-call BI "get_epiphany_fnegativeflag" sdtmp))
2526	    (set bvbit  (c-call BI "get_epiphany_foverflowflag" sdtmp))
2527	    (set bubit  (c-call BI "get_epiphany_funderflowflag" sdtmp))
2528	    (set bibit  (c-call BI "get_epiphany_finvalidflag" sdtmp))
2529	    (set bvsbit (or bvsbit bvbit))
2530	    (set busbit (or busbit bubit))
2531	    (set bisbit (or bisbit bibit))
2532	    (set rd sdtmp)
2533	    (if (or (and invExcEnbit bisbit)
2534		    (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit)))
2535		(sequence ()
2536		  (set expcause0bit (const 1))
2537		  (set expcause1bit (const 1))
2538		  (call-exception #x4 #x2)))
2539	    ))
2540	(if (eq arithmetic-modebit2 1)
2541	    (sequence ((SI sdtmp))
2542	      (set sdtmp  (c-call SI (.str "epiphany_i" name) rd rn rm))
2543	      ;; carry is not connected inb the design (set bcbit bcbit)
2544	      (set bzbit (zflag sdtmp))
2545	      (set bnbit (nflag sdtmp))
2546	      (set rd sdtmp)))
2547	)
2548
2549      ()
2550      )
2551    (dnmi (.sym "i_" name "f16")
2552	  (.str "i_" name)
2553	  (SHORT-INSN NO-DIS)
2554	  (.str "i" name " $rd,$rn,$rm")
2555	  (emit (.sym "f_" name "f16") rd rn rm)
2556    )
2557
2558
2559    (dni_wrapper
2560      (.sym "f_" name "f32")
2561      (.str "f_" name)
2562      ()
2563      (.str "f" name " $rd6,$rn6,$rm6")
2564      (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rm6)
2565      (sequence ()
2566	(if
2567	  (eq arithmetic-modebit2 0)
2568	  (sequence ((SF fptemp) (SI sdtmp))
2569	    (set sdtmp  (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6))
2570
2571	    ;;All bits are calculated in C
2572	    (set bzbit  (c-call BI "get_epiphany_fzeroflag" sdtmp))
2573	    (set bnbit  (c-call BI "get_epiphany_fnegativeflag" sdtmp))
2574	    (set bvbit  (c-call BI "get_epiphany_foverflowflag" sdtmp))
2575	    (set bubit  (c-call BI "get_epiphany_funderflowflag" sdtmp))
2576	    (set bibit  (c-call BI "get_epiphany_finvalidflag" sdtmp))
2577	    (set bvsbit (or bvsbit bvbit))
2578	    (set busbit (or busbit bubit))
2579	    (set bisbit (or bisbit bibit))
2580
2581	    (set rd6 sdtmp)
2582
2583	    (if (or (and invExcEnbit bisbit)
2584		    (or (and ovfExcEnbit bvsbit) (and unExcEnbit busbit)))
2585		(sequence ()
2586		  (set expcause0bit (const 1))
2587		  (set expcause1bit (const 1))
2588		  (call-exception #x4 #x2)))
2589	    )
2590	  )
2591	(if (eq arithmetic-modebit2 1)
2592	    (sequence ((SI sdtmp))
2593	      (set sdtmp (c-call SI (.str "epiphany_i" name) rd6 rn6 rm6))
2594	      ;; carry is not connected inb the design (set bcbit bcbit)
2595	      (set bzbit (zflag sdtmp))
2596	      (set bnbit (nflag sdtmp))
2597	      (set rd6 sdtmp)
2598	      )
2599	    )
2600	)
2601      ()
2602      )
2603
2604    (dnmi (.sym "f_" name "f32.l")
2605	  (.str "f_" name)
2606	  (NO-DIS)
2607	  (.str "f" name ".l $rd6,$rn6,$rm6")
2608	  (emit  (.sym "f_" name "f32") rd6  rn6 rm6)
2609	  )
2610    (dnmi (.sym "i_" name "f32")
2611	  (.str "i_" name)
2612	  (NO-DIS)
2613	  (.str "i" name " $rd6,$rn6,$rm6")
2614	  (emit  (.sym "f_" name "f32") rd6  rn6 rm6)
2615	  )
2616    (dnmi (.sym "i_" name "f32.l")
2617	  (.str "i_" name)
2618	  (NO-DIS)
2619	  (.str "i" name ".l $rd6,$rn6,$rm6")
2620	  (emit  (.sym "f_" name "f32") rd6  rn6 rm6)
2621	  )
2622
2623
2624
2625    )
2626  )
2627
2628(op-two_operands-float add OPF_ADD)
2629(op-two_operands-float sub OPF_SUB)
2630(op-two_operands-float mul OPF_MUL)
2631(op-two_operands-float madd OPF_MADD)
2632(op-two_operands-float msub OPF_MSUB)
2633
2634;; ONE operands
2635;; FABS
2636(define-pmacro (op-fabs-float name code)
2637  (begin
2638    (dni_wrapper (.sym "f_" name "f16")
2639		 (.str "f_" name)
2640		 (SHORT-INSN)
2641		 (.str "f" name " rd,rn")
2642		 (+ OP4_DSP16 code rd rn rn)
2643		 (sequence ((SF fptemp) (SI sdtmp))
2644
2645		   ;(set sdtmp  (and rn  #x7fffffff))
2646		   (set sdtmp  (c-call SI (.str "epiphany_fabs") rd rn rn))
2647
2648
2649		   (set bnbit  (const SI 0))
2650		   (set bzbit (eq SI sdtmp  (const SI 0)))
2651
2652		   ;;TODO subnormal ??
2653		   (set bvsbit (or bvsbit bvbit))
2654		   (set busbit (or busbit bubit))
2655		   (set bisbit (or bisbit bibit))
2656
2657		   (set rd sdtmp)
2658		   )
2659		 ()
2660		 )
2661
2662    (dni_wrapper (.sym "f_" name "f32")
2663		 (.str "f_" name)
2664		 ()
2665		 (.str "f" name " $rd6,$rn6")
2666		 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
2667		 (sequence ((SF fptemp) (SI sdtmp))
2668
2669
2670		   ;(set sdtmp   (and rn6  #x7fffffff))
2671
2672		   (set sdtmp  (c-call SI (.str "epiphany_fabs") rd6 rn6 rn6))
2673
2674
2675		   (set bnbit   (const SI 0))
2676		   (set bzbit (eq SI sdtmp  (const SI 0)))
2677
2678		   (set bvsbit (or bvsbit bvbit))
2679		   (set busbit (or busbit bubit))
2680		   (set bisbit (or bisbit bibit))
2681
2682		   (set rd6 sdtmp)
2683
2684		   )
2685		 ()
2686		 )
2687
2688    (dnmi  (.sym "f_" name "f32.l")
2689	   (.str "f_" name)
2690	   (NO-DIS)
2691	   (.str "f" name ".l $rd6,$rn6")
2692	   (emit (.sym "f_" name "f32") rd6  rn6)
2693	   )
2694
2695
2696    )
2697  )
2698
2699(op-fabs-float abs OPF_FABS)
2700
2701
2702(define-pmacro (op-fix2float-float name code)
2703  (begin
2704    (dni_wrapper (.sym "f_" name "f16")
2705		 (.str "f_" name)
2706		 (SHORT-INSN)
2707		 (.str "f" name " $rd,$rn")
2708		 (+ OP4_DSP16 code frd frn frn)
2709		 (sequence ((SF fptemp) (SI sdtmp))
2710
2711		   (set sdtmp  (c-call SI (.str "epiphany_f" name) rd rn rn))
2712
2713		   (set bnbit (lt SI sdtmp  (const SI 0)))
2714		   (set bzbit (eq SI sdtmp  (const SI 0)))
2715
2716		   (set bvsbit (or bvsbit bvbit))
2717		   (set busbit (or busbit bubit))
2718		   (set bisbit (or bisbit bibit))
2719
2720		   (set rd sdtmp)
2721		   )
2722		 ()
2723		 )
2724
2725
2726    (dni_wrapper (.sym "f_" name "f32")
2727		 (.str "f_" name)
2728		 ()
2729		 (.str "f" name " $rd6,$rn6")
2730		 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
2731		 (sequence ((SF fptemp) (SI sdtmp))
2732
2733		   (set sdtmp  (c-call SI (.str "epiphany_f" name) rd6 rn6 rn6))
2734
2735		   (set bnbit (lt SI sdtmp  (const SI 0)))
2736		   (set bzbit (eq SI sdtmp  (const SI 0)))
2737
2738		   (set bvsbit (or bvsbit bvbit))
2739		   (set busbit (or busbit bubit))
2740		   (set bisbit (or bisbit bibit))
2741
2742		   (set rd6 sdtmp)
2743
2744		   )
2745		 ()
2746		 )
2747
2748    (dnmi (.sym "f_" name "f32.l")
2749	  (.str "f_" name)
2750	  (NO-DIS)
2751	  (.str "f" name ".l $rd6,$rn6")
2752	  (emit (.sym "f_" name "f32")  rd6 rn6)
2753	  )
2754    )
2755  )
2756
2757(op-fix2float-float loat OPF_FLOAT)
2758
2759(define-pmacro (op-float2fix-float name code)
2760  (begin
2761    (dni_wrapper (.sym "f_" name "f16")
2762		 (.str "f_" name)
2763		 (SHORT-INSN)
2764		 (.str "f" name " $rd,$rn")
2765		 (+ OP4_DSP16 code rd rn rn)
2766		 (sequence ((SF fptemp) (SI sdtmp))
2767
2768		   (set sdtmp  (c-call SI (.str "epiphany_f" name) rd rn rn))
2769
2770		   (set bzbit (zflag sdtmp))
2771		   (set bnbit (nflag sdtmp))
2772
2773		   (set bvbit  (c-call BI "get_epiphany_foverflowflag" sdtmp))
2774		   (set bubit  (c-call BI "get_epiphany_funderflowflag" sdtmp))
2775		   (set bibit  (c-call BI "get_epiphany_finvalidflag" sdtmp))
2776
2777		   (set bvsbit (or bvsbit bvbit))
2778		   (set busbit (or busbit bubit))
2779		   (set bisbit (or bisbit bibit))
2780
2781		   (set rd6 sdtmp)
2782
2783		   (if (or (and invExcEnbit bisbit)
2784			   (or (and ovfExcEnbit busbit)
2785			       (and unExcEnbit bvsbit)))
2786		       (sequence ()
2787			 (set expcause0bit (const 1))
2788			 (set expcause1bit (const 1))
2789			 (call-exception #x4 #x2)))
2790		   (set rd sdtmp)
2791		   )
2792		 ()
2793		 )
2794
2795
2796
2797    (dni_wrapper (.sym "f_" name "f32")
2798		 (.str "f_" name)
2799		 ()
2800		 (.str "f" name " $rd6,$rn6")
2801		 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) rd6 rn6 rn6)
2802		 (sequence ((SF fptemp) (SI sdtmp))
2803
2804		   (set sdtmp  (c-call SI (.str "epiphany_f" name) rd6 rn6 rm6))
2805
2806		   (set bzbit (zflag sdtmp))
2807		   (set bnbit (nflag sdtmp))
2808
2809		   (set bvbit  (c-call BI "get_epiphany_foverflowflag" sdtmp))
2810		   (set bubit  (c-call BI "get_epiphany_funderflowflag" sdtmp))
2811		   (set bibit  (c-call BI "get_epiphany_finvalidflag" sdtmp))
2812
2813		   (set bvsbit (or bvsbit bvbit))
2814		   (set busbit (or busbit bubit))
2815		   (set bisbit (or bisbit bibit))
2816
2817		   (set rd6 sdtmp)
2818
2819		   (if (or (and invExcEnbit bisbit)
2820			   (or (and ovfExcEnbit busbit)
2821			       (and unExcEnbit bvsbit)))
2822		       (sequence ()
2823			 (set expcause0bit (const 1))
2824			 (set expcause1bit (const 1))
2825			 (call-exception #x4 #x2))
2826		       )
2827
2828		   )
2829		 ()
2830		 )
2831
2832    (dnmi (.sym "f_" name "f32.l")
2833	  (.str "f_" name)
2834	  (NO-DIS)
2835	  (.str "f" name ".l $rd6,$rn6")
2836	  (emit (.sym "f_" name "f32") rd6  rn6)
2837	  )
2838
2839
2840    )
2841  )
2842
2843
2844
2845
2846
2847(op-float2fix-float ix OPF_FIX)
2848
2849;; MAC (Multiply and Accumulate Instructions
2850;; (define-pmacro (op-mac-float name code)
2851;;   (begin
2852;;     (dni_wrapper (.sym "fm" name "f16")
2853;; 	 (.str "fm" name)
2854;; 	 (SHORT-INSN)
2855;; 	 (.str "fm" name " $frd,$frn,$frm")
2856;; 	 (+ OP4_DSP16 code frd frn frm)
2857;; 	 (sequence ((SF fptemp))
2858;; 		   (set bvbit 0)
2859;; 		   (set busbit 0)
2860;;                    (set fptemp (c-call SF (.str "epiphany_fm" name) frd frm frn))
2861;; 		   (set bnbit (lt SF fptemp (const SF 0)))
2862;; 		   (set bzbit (eq SF fptemp (const SF 0)))
2863;; 		   (set bvsbit (or bvsbit bvbit))
2864;;                    (set frd fptemp)
2865;; ;		   (set rd (subword SI frd 0))
2866;; 		   )
2867;; 	 ()
2868;; 	 )
2869
2870;;     (dni_wrapper (.sym "fm" name "f32")
2871;; 	 (.str "fm" name)
2872;; 	 ()
2873;; 	 (.str "fm" name " $frd6,$frn6,$frm6")
2874;; 	 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-3 #x0) frd6 frn6 frm6)
2875;; 	 (sequence ((SF fptemp))
2876;; 		   (set bvbit 0)
2877;; 		   (set busbit 0)
2878;;                    (set fptemp (c-call SF (.str "epiphany_fm" name) frd6 frm6 frn6))
2879;; 		   (set bnbit (lt SF fptemp (const SF 0)))
2880;; 		   (set bzbit (eq SF fptemp (const SF 0)))
2881;; 		   (set bvsbit (or bvsbit bvbit))
2882;;                    (set frd6 fptemp)
2883;; ;		   (set rd6 (subword SI frd6 0))
2884;; 		   )
2885;; 	 ()
2886;; 	 )
2887;;     )
2888;; )
2889
2890
2891
2892
2893
2894
2895
2896					; extended floating point operation
2897
2898
2899(define-pmacro (op-fextop-float name code)
2900  (begin
2901
2902    (dni_wrapper (.sym "f_" name "f32")
2903		 (.str "f_" name)
2904		 ()
2905		 (.str "f" name " $frd6,$frn6")
2906		 (+ OP4_MISC code (f-opc-19-4 #x7) (f-dc-22-2 #x0) (f-dc-20-1 #x1) frd6 frn6 frn6)
2907		 (sequence ((SF fptemp))
2908			   (set bvbit 0)
2909			   (set busbit 0)
2910			   (set fptemp (c-call SF (.str "epiphany_f" name) frn6))
2911			   (set bnbit (lt SF fptemp (const SF 0)))
2912			   (set bzbit (eq SF fptemp (const SF 0)))
2913			   (set bvsbit (or bvsbit bvbit))
2914			   (set frd6 fptemp)
2915
2916			   )
2917		 ()
2918		 )
2919
2920
2921    (dnmi (.sym "f_" name "f32.l")
2922	  (.str "f_" name)
2923	  (NO-DIS)
2924	  (.str "f" name ".l $frd6,$frn6")
2925	  (emit (.sym "f_" name "f32") frd6 frn6)
2926	  )
2927    )
2928  )
2929
2930(op-fextop-float recip OPF_FRECIP)
2931(op-fextop-float sqrt  OPF_FSQRT)
2932
2933
2934
2935
2936
2937