1; Toshiba MeP Media Engine architecture description.  -*- Scheme -*-
2; Copyright 2011 Free Software Foundation, Inc.
3;
4; Contributed by Red Hat Inc;
5;
6; This file is part of the GNU Binutils.
7;
8; This program is free software; you can redistribute it and/or modify
9; it under the terms of the GNU General Public License as published by
10; the Free Software Foundation; either version 3 of the License, or
11; (at your option) any later version.
12;
13; This program is distributed in the hope that it will be useful,
14; but WITHOUT ANY WARRANTY; without even the implied warranty of
15; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16; GNU General Public License for more details.
17;
18; You should have received a copy of the GNU General Public License
19; along with this program; if not, write to the Free Software
20; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21; MA 02110-1301, USA.
22
23(include "simplify.inc")
24
25(define-pmacro isa-enum ()
26  (isas mep
27; begin-isa-enum
28	ext_core1 ext_cop1_16 ext_cop1_32 ext_cop1_48 ext_cop1_64
29; end-isa-enum
30  )
31)
32
33(define-arch
34  (name mep)
35  (comment "Toshiba MeP Media Engine")
36  (insn-lsb0? #f) ;; work around cgen limitation
37  (machs mep h1 c5)
38  isa-enum
39)
40
41(define-isa
42  (name mep)
43  (comment "MeP core instruction set")
44  (default-insn-word-bitsize 32)
45  (default-insn-bitsize 32)
46  (base-insn-bitsize 32)
47)
48
49; begin-isas
50(define-isa
51  (name ext_core1)
52  (comment "MeP core extension instruction set")
53  (default-insn-word-bitsize 32)
54  (default-insn-bitsize 32)
55  (base-insn-bitsize 32)
56)
57
58(define-isa
59  (name ext_cop1_16)
60  (comment "MeP coprocessor instruction set")
61  (default-insn-word-bitsize 32)
62  (default-insn-bitsize 32)
63  (base-insn-bitsize 32)
64)
65
66(define-isa
67  (name ext_cop1_32)
68  (comment "MeP coprocessor instruction set")
69  (default-insn-word-bitsize 32)
70  (default-insn-bitsize 32)
71  (base-insn-bitsize 32)
72)
73
74(define-isa
75  (name ext_cop1_48)
76  (comment "MeP coprocessor instruction set")
77  (default-insn-word-bitsize 32)
78  (default-insn-bitsize 32)
79  (base-insn-bitsize 32)
80)
81
82(define-isa
83  (name ext_cop1_64)
84  (comment "MeP coprocessor instruction set")
85  (default-insn-word-bitsize 32)
86  (default-insn-bitsize 32)
87  (base-insn-bitsize 32)
88)
89
90(define-pmacro all-mep-isas () (ISA mep,ext_core1,ext_cop1_16,ext_cop1_32,ext_cop1_48,ext_cop1_64))
91
92(define-pmacro all-mep-core-isas () (ISA mep,ext_core1,ext_cop1_32))
93
94(define-pmacro all-core-isa-list () mep,ext_core1)
95; end-isas
96
97(define-cpu
98  (name mepf)
99  (comment "MeP family")
100  (endian either)
101  (insn-chunk-bitsize 16)
102  (word-bitsize 32)
103)
104
105(define-mach
106  (name mep)
107  (comment "MeP media engine")
108  (cpu mepf)
109  isa-enum
110)
111
112(define-mach
113  (name h1)
114  (comment "H1 media engine")
115  (cpu mepf)
116  isa-enum
117)
118
119(define-mach
120  (name c5)
121  (comment "C5 media engine")
122  (cpu mepf)
123  isa-enum
124)
125
126(define-model
127  (name mep)
128  (comment "MeP media engine processor")
129  (mach c5) ; mach gets changed by MeP-Integrator
130
131  (unit u-exec "execution unit" ()
132	1 1 ; issue done
133	() () () ())
134
135  ; Branch unit
136  (unit u-branch "Branch Unit" ()
137	0 0 ; issue done
138	() ; state
139	() ; inputs
140	((pc)) ; outputs
141	() ; profile action (default)
142	)
143
144  ; Multiply unit
145  (unit u-multiply "Multiply Unit" ()
146	0 0 ; issue done
147	() ; state
148	() ; inputs
149	() ; outputs
150	() ; profile action (default)
151	)
152
153  ; Divide unit
154  (unit u-divide "Divide Unit" ()
155	0 0 ; issue done
156	() ; state
157	() ; inputs
158	() ; outputs
159	() ; profile action (default)
160	)
161
162  ; Stcb unit
163  (unit u-stcb "stcb Unit" ()
164	0 0 ; issue done
165	() ; state
166	() ; inputs
167	() ; outputs
168	() ; profile action (default)
169	)
170
171  ; Ldcb unit
172  (unit u-ldcb "ldcb Unit" ()
173	0 0 ; issue done
174	() ; state
175	() ; inputs
176	() ; outputs
177	() ; profile action (default)
178	)
179
180  ; Load gpr unit
181  (unit u-load-gpr "Load into GPR Unit" ()
182	0 0 ; issue done
183	() ; state
184	() ; inputs
185	((loadreg INT -1)) ; outputs
186	() ; profile action (default)
187	)
188
189  (unit u-ldcb-gpr "Ldcb into GPR Unit" ()
190	0 0 ; issue done
191	() ; state
192	() ; inputs
193	((loadreg INT -1)) ; outputs
194	() ; profile action (default)
195	)
196
197  ; Multiply into GPR unit
198  (unit u-mul-gpr "Multiply into GPR Unit" ()
199	0 0 ; issue done
200	() ; state
201	() ; inputs
202	((resultreg INT -1)) ; outputs
203	() ; profile action (default)
204	)
205
206  ; Use gpr unit -- stalls if GPR not ready
207  (unit u-use-gpr "Use GPR Unit" ()
208	0 0 ; issue done
209	() ; state
210	((usereg INT -1)) ; inputs
211	() ; outputs
212	() ; profile action (default)
213	)
214
215  ; Use ctrl-reg unit -- stalls if CTRL-REG not ready
216  (unit u-use-ctrl-reg "Use CTRL-REG Unit" ()
217	0 0 ; issue done
218	() ; state
219	((usereg INT -1)) ; inputs
220	() ; outputs
221	() ; profile action (default)
222	)
223
224  ; Store ctrl-reg unit -- stalls if CTRL-REG not ready
225  (unit u-store-ctrl-reg "Store CTRL-REG Unit" ()
226	0 0 ; issue done
227	() ; state
228	() ; inputs
229	((storereg INT -1)) ; outputs
230	() ; profile action (default)
231	)
232)
233
234; Hardware elements.
235
236(dnh h-pc "program counter" (PC PROFILE all-mep-isas) (pc) () () ())
237
238(define-hardware
239  (name h-gpr)
240  (comment "General purpose registers")
241  (attrs all-mep-isas CACHE-ADDR PROFILE)
242  (type register SI (16))
243  (indices keyword "$"
244	   (("0" 0) ("1" 1) ("2" 2) ("3" 3) ("4" 4) ("5" 5)
245	    ("6" 6) ("7" 7) ("8" 8) ("9" 9) ("10" 10) ("11" 11)
246	    ; "$8" is the preferred name for register 8, but "$tp", "$gp"
247	    ; and "$sp" are preferred for their respective registers.
248	    (fp  8) (tp 13) (gp 14) (sp 15)
249	    ("12" 12) ("13" 13) ("14" 14) ("15" 15)))
250)
251
252(define-hardware
253  (name h-csr)
254  (comment "Control/special registers")
255  (attrs all-mep-isas PROFILE)
256  (type register SI (32))
257  (indices keyword "$"
258	   ((pc 0)   (lp 1)   (sar 2)   (rpb  4) (rpe 5)   (rpc 6)
259	    (hi 7)   (lo 8)   (mb0 12)  (me0 13) (mb1 14)  (me1 15)
260	    (psw 16) (id 17)  (tmp 18)  (epc 19) (exc 20)  (cfg 21)
261	    (npc 23) (dbg 24) (depc 25) (opt 26) (rcfg 27) (ccfg 28)
262; begin-extra-csr-registers
263	    (vid 22)
264; end-extra-csr-registers
265  ))
266  (get (index) (c-call SI "cgen_get_csr_value" index))
267  (set (index newval) (c-call VOID "cgen_set_csr_value" index newval))
268)
269
270(define-pmacro (-reg-pair n) ((.sym n) n))
271(define-hardware
272  (name h-cr64)
273  (comment "64-bit coprocessor registers")
274  (attrs all-mep-isas)
275  ; This assumes that the data path of the co-pro is 64 bits.
276  (type register DI (32))
277  (indices keyword "$c" (.map -reg-pair (.iota 32)))
278  (set (index newval) (c-call VOID "h_cr64_queue_set" index newval))
279)
280(define-hardware
281  (name h-cr64-w)
282  (comment "64-bit coprocessor registers, pending writes")
283  (attrs all-mep-isas)
284  ; This assumes that the data path of the co-pro is 64 bits.
285  (type register DI (32))
286)
287
288(define-hardware
289  (name h-cr)
290  (comment "32-bit coprocessor registers")
291  (attrs all-mep-isas VIRTUAL)
292  (type register SI (32))
293  (indices keyword "$c" (.map -reg-pair (.iota 32)))
294  (set (index newval) (c-call VOID "h_cr64_set" index (ext DI newval)))
295  (get (index) (trunc SI (c-call DI "h_cr64_get" index)))
296)
297
298;; Given a coprocessor control register number N, expand to a
299;; name/index pair: ($ccrN N)
300(define-pmacro (-ccr-reg-pair n) ((.sym "$ccr" n) n))
301
302(define-hardware
303  (name h-ccr)
304  (comment "Coprocessor control registers")
305  (attrs all-mep-isas)
306  (type register SI (64))
307  (indices keyword "" (.map -ccr-reg-pair (.iota 64)))
308  (set (index newval) (c-call VOID "h_ccr_queue_set" index newval))
309)
310(define-hardware
311  (name h-ccr-w)
312  (comment "Coprocessor control registers, pending writes")
313  (attrs all-mep-isas)
314  (type register SI (64))
315)
316
317
318; Instruction fields.  Bit numbering reversed.
319
320; Conventions:
321;
322; N = number of bits in value
323; A = alignment (2 or 4, omit for 1)
324; B = leftmost (i.e. closest to zero) bit position
325;
326; -- Generic Fields (f-*) --
327; N		number of bits in *value* (1-24)
328; [us]		signed vs unsigned
329; B		position of left-most bit (4-16)
330; aA		opt. alignment (2=drop 1 lsb, 4=drop 2 lsbs, etc)
331; n		opt. for noncontiguous fields
332; f-foo-{hi,lo}	msb/lsb parts of field f-foo
333;
334; -- Operands --
335; pcrelNaA	PC-relative branch target (signed)
336; pcabsNaA	Absolute branch target (unsigned)
337;
338; [us]dispNaA	[un]signed displacement
339; [us]immN	[un]signed immediate value
340; addrNaA	absolute address (unsigned)
341;
342; Additional prefixes may be used for special cases.
343
344(dnf f-major   "major opcode"            (all-mep-core-isas)    0  4)
345
346(dnf f-rn      "register n"              (all-mep-core-isas)    4  4)
347(dnf f-rn3     "register 0-7"            (all-mep-core-isas)    5  3)
348(dnf f-rm      "register m"              (all-mep-core-isas)    8  4)
349(dnf f-rl      "register l"              (all-mep-core-isas)   12  4)
350(dnf f-sub2    "sub opcode (2 bits)"     (all-mep-core-isas)   14  2)
351(dnf f-sub3    "sub opcode (3 bits)"     (all-mep-core-isas)   13  3)
352(dnf f-sub4    "sub opcode (4 bits)"     (all-mep-core-isas)   12  4)
353(dnf f-ext     "extended field"          (all-mep-core-isas)   16  8)
354(dnf f-ext4    "extended field 16:4"     (all-mep-core-isas)   16  4)
355(dnf f-ext62   "extended field 20:2"     (all-mep-core-isas)   20  2)
356(dnf f-crn     "copro register n"        (all-mep-core-isas)    4  4)
357
358(df f-csrn-hi "cr hi 1u15" (all-mep-core-isas) 15 1 UINT #f #f)
359(df f-csrn-lo "cr lo 4u8"  (all-mep-core-isas)  8 4 UINT #f #f)
360(define-multi-ifield
361  (name f-csrn)
362  (comment "control reg")
363  (attrs all-mep-core-isas)
364  (mode UINT)
365  (subfields f-csrn-hi f-csrn-lo)
366  (insert (sequence ()
367		    (set (ifield f-csrn-lo) (and (ifield f-csrn) #xf))
368		    (set (ifield f-csrn-hi) (srl (ifield f-csrn) 4))))
369  (extract (set (ifield f-csrn)
370		(or (sll (ifield f-csrn-hi) 4) (ifield f-csrn-lo))))
371  )
372
373(df f-crnx-hi "crx hi 1u28" (all-mep-core-isas) 28 1 UINT #f #f)
374(df f-crnx-lo "crx lo 4u4"  (all-mep-core-isas)  4 4 UINT #f #f)
375(define-multi-ifield
376  (name f-crnx)
377  (comment "copro register n (0-31)")
378  (attrs all-mep-core-isas)
379  (mode UINT)
380  (subfields f-crnx-hi f-crnx-lo)
381  (insert (sequence ()
382		    (set (ifield f-crnx-lo) (and (ifield f-crnx) #xf))
383		    (set (ifield f-crnx-hi) (srl (ifield f-crnx) 4))))
384  (extract (set (ifield f-crnx)
385		(or (sll (ifield f-crnx-hi) 4) (ifield f-crnx-lo))))
386  )
387
388; Miscellaneous fields.
389
390(define-pmacro (dnfb n)
391  (dnf (.sym f- n) (.str "bit " n) (all-mep-isas) n 1))
392
393; Define small fields used throughout the instruction set description.
394; Each field (eg. `f-N') is at single bit field at position N.
395
396(dnfb  0)
397(dnfb  1)
398(dnfb  2)
399(dnfb  3)
400(dnfb  4)
401(dnfb  5)
402(dnfb  6)
403(dnfb  7)
404(dnfb  8)
405(dnfb  9)
406(dnfb  10)
407(dnfb  11)
408(dnfb  12)
409(dnfb  13)
410(dnfb  14)
411(dnfb  15)
412(dnfb  16)
413(dnfb  17)
414(dnfb  18)
415(dnfb  19)
416(dnfb  20)
417(dnfb  21)
418(dnfb  22)
419(dnfb  23)
420(dnfb  24)
421(dnfb  25)
422(dnfb  26)
423(dnfb  27)
424(dnfb  28)
425(dnfb  29)
426(dnfb  30)
427(dnfb  31)
428
429; Branch/Jump target addresses
430
431(df f-8s8a2 "pc-rel addr (8 bits)"    (all-mep-core-isas PCREL-ADDR)  8  7 INT
432    ((value pc) (sra SI (sub SI value    pc) 1))
433    ((value pc) (add SI (sll SI value 1) pc)))
434
435(df f-12s4a2 "pc-rel addr (12 bits)"  (all-mep-core-isas PCREL-ADDR)  4 11 INT
436    ((value pc) (sra SI (sub SI value    pc) 1))
437    ((value pc) (add SI (sll SI value 1) pc)))
438
439(df f-17s16a2 "pc-rel addr (17 bits)" (all-mep-core-isas PCREL-ADDR) 16 16 INT
440    ((value pc) (sra SI (sub SI value    pc) 1))
441    ((value pc) (add SI (sll SI value 1) pc)))
442
443(df f-24s5a2n-hi "24s5a2n hi 16s16" (all-mep-core-isas PCREL-ADDR) 16 16  INT #f #f)
444(df f-24s5a2n-lo "24s5a2n lo 7s5a2" (all-mep-core-isas PCREL-ADDR)  5  7 UINT #f #f)
445(define-multi-ifield
446  (name f-24s5a2n)
447  (comment "pc-rel addr (24 bits align 2)")
448  (attrs all-mep-core-isas PCREL-ADDR)
449  (mode INT)
450  (subfields f-24s5a2n-hi f-24s5a2n-lo)
451  (insert (sequence ()
452		    (set (ifield f-24s5a2n)
453			 (sub (ifield f-24s5a2n) pc))
454		    (set (ifield f-24s5a2n-lo)
455			 (srl (and (ifield f-24s5a2n) #xfe) 1))
456		    (set (ifield f-24s5a2n-hi)
457			 (sra INT (ifield f-24s5a2n) 8))))
458  (extract (set (ifield f-24s5a2n)
459		(add SI (or (sll (ifield f-24s5a2n-hi) 8)
460			    (sll (ifield f-24s5a2n-lo) 1))
461		     pc)))
462  )
463
464(df f-24u5a2n-hi "24u5a2n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
465(df f-24u5a2n-lo "24u5a2n lo 7u5a2" (all-mep-core-isas)  5  7 UINT #f #f)
466(define-multi-ifield
467  (name f-24u5a2n)
468  (comment "abs jump target (24 bits, alignment 2)")
469  (attrs all-mep-core-isas ABS-ADDR)
470  (mode UINT)
471  (subfields f-24u5a2n-hi f-24u5a2n-lo)
472  (insert (sequence ()
473		    (set (ifield f-24u5a2n-lo)
474			 (srl (and (ifield f-24u5a2n) #xff) 1))
475		    (set (ifield f-24u5a2n-hi)
476			 (srl (ifield f-24u5a2n) 8))
477		    ))
478  (extract (set (ifield f-24u5a2n)
479		(or (sll (ifield f-24u5a2n-hi) 8)
480		    (sll (ifield f-24u5a2n-lo) 1))))
481  )
482
483; Displacement fields.
484
485(df f-2u6     "SAR offset (2 bits)"    (all-mep-core-isas)  6  2 UINT #f #f)
486(df f-7u9     "tp-rel b (7 bits)"      (all-mep-core-isas)  9  7 UINT #f #f)
487(df f-7u9a2   "tp-rel h (7 bits)"      (all-mep-core-isas)  9  6 UINT
488    ((value pc) (srl SI value 1))
489    ((value pc) (sll SI value 1)))
490(df f-7u9a4   "tp/sp-rel w (7 bits)"   (all-mep-core-isas)  9  5 UINT
491    ((value pc) (srl SI value 2))
492    ((value pc) (sll SI value 2)))
493(df f-16s16   "general 16-bit s-val"   (all-mep-core-isas) 16 16  INT #f #f)
494
495; Immediate fields.
496
497(df f-2u10   "swi level (2 bits)"      (all-mep-core-isas) 10  2 UINT #f #f)
498(df f-3u5    "bit offset (3 bits)"     (all-mep-core-isas)  5  3 UINT #f #f)
499(df f-4u8    "bCC const (4 bits)"      (all-mep-core-isas)  8  4 UINT #f #f)
500(df f-5u8    "slt & shifts (5 bits)"   (all-mep-core-isas)  8  5 UINT #f #f)
501(df f-5u24   "clip immediate (5 bits)" (all-mep-core-isas) 24  5 UINT #f #f)
502(df f-6s8    "add immediate (6 bits)"  (all-mep-core-isas)  8  6  INT #f #f)
503(df f-8s8    "add imm (8 bits)"        (all-mep-core-isas)  8  8  INT #f #f)
504(df f-16u16  "general 16-bit u-val"    (all-mep-core-isas) 16 16 UINT #f #f)
505(df f-12u16  "cmov fixed 1"            (all-mep-core-isas) 16 12 UINT #f #f)
506(df f-3u29   "cmov fixed 2"            (all-mep-core-isas) 29  3 UINT #f #f)
507
508
509; These are all for the coprocessor opcodes
510
511; The field is like IJKiiiiiii where I and J are toggled if K is set,
512; for compatibility with older cores.
513(define-pmacro (compute-cdisp10 val)
514  (cond SI
515	((and SI (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x200)
516	 (sub (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)) #x400))
517	(else
518	 (cond SI ((and SI val #x80) (xor SI val #x300)) (else val)))
519	)
520  )
521(define-pmacro (extend-cdisp10 val)
522  (cond SI
523	((and SI (compute-cdisp10 val) #x200)
524	 (sub (and SI (compute-cdisp10 val) #x3ff) #x400))
525	(else
526	 (and SI (compute-cdisp10 val) #x3ff))
527	)
528  )
529
530(df f-cdisp10    "cop imm10"          (all-mep-core-isas)   22  10 INT
531    ((value pc) (extend-cdisp10 value))
532    ((value pc) (extend-cdisp10 value))
533    )
534
535; Non-contiguous fields.
536
537(df f-24u8a4n-hi "24u8a4n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
538(df f-24u8a4n-lo "24u8a4n lo 8u8a4" (all-mep-core-isas)  8  6 UINT #f #f)
539(define-multi-ifield
540  (name f-24u8a4n)
541  (comment "absolute 24-bit address")
542  (attrs all-mep-core-isas)
543  (mode UINT)
544  (subfields f-24u8a4n-hi f-24u8a4n-lo)
545  (insert (sequence ()
546		    (set (ifield f-24u8a4n-hi) (srl (ifield f-24u8a4n) 8))
547		    (set (ifield f-24u8a4n-lo) (srl (and (ifield f-24u8a4n) #xfc) 2))))
548  (extract (set (ifield f-24u8a4n)
549		(or (sll (ifield f-24u8a4n-hi) 8)
550		    (sll (ifield f-24u8a4n-lo) 2))))
551  )
552
553(df f-24u8n-hi "24u8n hi 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
554(df f-24u8n-lo "24u8n lo  8u8"  (all-mep-core-isas)  8  8 UINT #f #f)
555(define-multi-ifield
556  (name f-24u8n)
557  (comment "24-bit constant")
558  (attrs all-mep-core-isas)
559  (mode UINT)
560  (subfields f-24u8n-hi f-24u8n-lo)
561  (insert (sequence ()
562		    (set (ifield f-24u8n-hi) (srl (ifield f-24u8n) 8))
563		    (set (ifield f-24u8n-lo) (and (ifield f-24u8n) #xff))))
564  (extract (set (ifield f-24u8n)
565		(or (sll (ifield f-24u8n-hi) 8)
566		    (ifield f-24u8n-lo))))
567  )
568
569(df f-24u4n-hi "24u4n hi  8u4"  (all-mep-core-isas)  4  8 UINT #f #f)
570(df f-24u4n-lo "24u4n lo 16u16" (all-mep-core-isas) 16 16 UINT #f #f)
571(define-multi-ifield
572  (name f-24u4n)
573  (comment "coprocessor code")
574  (attrs all-mep-core-isas)
575  (mode UINT)
576  (subfields f-24u4n-hi f-24u4n-lo)
577  (insert (sequence ()
578		    (set (ifield f-24u4n-hi) (srl (ifield f-24u4n) 16))
579		    (set (ifield f-24u4n-lo) (and (ifield f-24u4n) #xffff))))
580  (extract (set (ifield f-24u4n)
581		(or (sll (ifield f-24u4n-hi) 16)
582		    (ifield f-24u4n-lo))))
583  )
584
585(define-multi-ifield
586  (name f-callnum)
587  (comment "system call number field")
588  (attrs all-mep-core-isas)
589  (mode UINT)
590  (subfields f-5 f-6 f-7 f-11)
591  (insert (sequence ()
592		    (set (ifield f-5)  (and (srl (ifield f-callnum) 3) 1))
593		    (set (ifield f-6)  (and (srl (ifield f-callnum) 2) 1))
594		    (set (ifield f-7)  (and (srl (ifield f-callnum) 1) 1))
595		    (set (ifield f-11) (and (ifield f-callnum) 1))))
596  (extract (set (ifield f-callnum)
597		(or (sll (ifield f-5) 3)
598		    (or (sll (ifield f-6) 2)
599			(or (sll (ifield f-7) 1)
600			    (ifield f-11))))))
601  )
602
603(df f-ccrn-hi "ccrn hi  2u28" (all-mep-core-isas) 28 2 UINT #f #f)
604(df f-ccrn-lo "ccrn lo  4u4"  (all-mep-core-isas)  4 4 UINT #f #f)
605(define-multi-ifield
606  (name f-ccrn)
607  (comment "Coprocessor register number field")
608  (attrs all-mep-core-isas)
609  (mode UINT)
610  (subfields f-ccrn-hi f-ccrn-lo)
611  (insert (sequence ()
612		    (set (ifield f-ccrn-hi)  (and (srl (ifield f-ccrn) 4) #x3))
613		    (set (ifield f-ccrn-lo)  (and (ifield f-ccrn) #xf))))
614  (extract (set (ifield f-ccrn)
615		(or (sll (ifield f-ccrn-hi) 4)
616		    (ifield f-ccrn-lo))))
617  )
618
619; Operands.
620
621;; Only LABEL, REGNUM, FMAX_FLOAT and FMAX_INT are now relevant for correct
622;; operation.  The others are mostly kept for backwards compatibility,
623;; although they do affect the dummy prototypes in
624;; gcc/config/mep/intrinsics.h.
625(define-attr
626  (type enum)
627  (for operand)
628  (name CDATA)
629  (comment "datatype to use for C intrinsics mapping")
630  (values LABEL REGNUM FMAX_FLOAT FMAX_INT
631	  POINTER LONG ULONG SHORT USHORT CHAR UCHAR CP_DATA_BUS_INT)
632  (default LONG))
633
634(define-attr
635  (type enum)
636  (for insn)
637  (name CPTYPE)
638  (comment "datatype to use for coprocessor values")
639  (values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI)
640  (default CP_DATA_BUS_INT))
641
642(define-attr
643  (type enum)
644  (for insn)
645  (name CRET)
646  ;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed.
647  ;; FIRST - the first argument is the return value.
648  ;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter.
649  (values VOID FIRST FIRSTCOPY)
650  (default VOID)
651  (comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it."))
652
653(define-attr
654  (type integer)
655  (for operand)
656  (name ALIGN)
657  (comment "alignment of immediate operands")
658  (default 1))
659
660(define-attr
661  (for operand)
662  (type boolean)
663  (name RELOC_IMPLIES_OVERFLOW)
664  (comment "Operand should not be considered as a candidate for relocs"))
665
666(define-attr
667  (for hardware)
668  (type boolean)
669  (name IS_FLOAT)
670  (comment "Register contains a floating point value"))
671
672(define-pmacro (dpop name commment attrib hwr field func)
673  (define-full-operand name comment attrib
674    hwr DFLT field ((parse func)) () ()))
675(define-pmacro (dprp name commment attrib hwr field pafunc prfunc)
676  (define-full-operand name comment attrib
677    hwr DFLT field ((parse pafunc) (print prfunc)) () ()))
678
679(dnop r0        "register 0"              (all-mep-core-isas) h-gpr   0)
680(dnop rn        "register Rn"             (all-mep-core-isas) h-gpr   f-rn)
681(dnop rm        "register Rm"             (all-mep-core-isas) h-gpr   f-rm)
682(dnop rl        "register Rl"             (all-mep-core-isas) h-gpr   f-rl)
683(dnop rn3       "register 0-7"            (all-mep-core-isas) h-gpr   f-rn3)
684
685;; Variants of RM/RN with different CDATA attributes.  See comment above
686;; CDATA for more details.
687
688(dnop rma       "register Rm holding pointer"          (all-mep-core-isas (CDATA POINTER)) h-gpr   f-rm)
689
690(dnop rnc       "register Rn holding char"             (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
691(dnop rnuc      "register Rn holding unsigned char"    (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
692(dnop rns       "register Rn holding short"            (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
693(dnop rnus      "register Rn holding unsigned short"   (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
694(dnop rnl       "register Rn holding long"             (all-mep-core-isas (CDATA LONG))    h-gpr   f-rn)
695(dnop rnul      "register Rn holding unsigned  long"   (all-mep-core-isas (CDATA ULONG))   h-gpr   f-rn)
696
697(dnop rn3c       "register 0-7 holding unsigned char"    (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
698(dnop rn3uc      "register 0-7 holding byte"             (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
699(dnop rn3s       "register 0-7 holding unsigned short"   (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
700(dnop rn3us      "register 0-7 holding short"            (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
701(dnop rn3l       "register 0-7 holding unsigned long"    (all-mep-core-isas (CDATA LONG))  h-gpr   f-rn3)
702(dnop rn3ul      "register 0-7 holding long"             (all-mep-core-isas (CDATA ULONG)) h-gpr   f-rn3)
703
704
705(dnop lp        "link pointer"            (all-mep-core-isas) h-csr   1)
706(dnop sar       "shift amount register"   (all-mep-core-isas) h-csr   2)
707(dnop hi        "high result"             (all-mep-core-isas) h-csr   7)
708(dnop lo        "low result"              (all-mep-core-isas) h-csr   8)
709(dnop mb0       "modulo begin register 0" (all-mep-core-isas) h-csr  12)
710(dnop me0       "modulo end register 0"   (all-mep-core-isas) h-csr  13)
711(dnop mb1       "modulo begin register 1" (all-mep-core-isas) h-csr  14)
712(dnop me1       "modulo end register 1"   (all-mep-core-isas) h-csr  15)
713(dnop psw       "program status word"     (all-mep-core-isas) h-csr  16)
714(dnop epc	"exception prog counter"  (all-mep-core-isas) h-csr  19)
715(dnop exc       "exception cause"         (all-mep-core-isas) h-csr  20)
716(dnop npc       "nmi program counter"     (all-mep-core-isas) h-csr  23)
717(dnop dbg       "debug register"          (all-mep-core-isas) h-csr  24)
718(dnop depc      "debug exception pc"      (all-mep-core-isas) h-csr  25)
719(dnop opt       "option register"         (all-mep-core-isas) h-csr  26)
720(dnop r1        "register 1"              (all-mep-core-isas) h-gpr   1)
721(dnop tp        "tiny data area pointer"  (all-mep-core-isas) h-gpr  13)
722(dnop sp        "stack pointer"           (all-mep-core-isas) h-gpr  15)
723(dprp tpr       "TP register"             (all-mep-core-isas) h-gpr  13       "tpreg" "tpreg")
724(dprp spr       "SP register"             (all-mep-core-isas) h-gpr  15       "spreg" "spreg")
725
726(define-full-operand
727  csrn "control/special register" (all-mep-core-isas (CDATA REGNUM)) h-csr
728  DFLT f-csrn ((parse "csrn")) () ()
729)
730
731(dnop csrn-idx  "control/special reg idx" (all-mep-core-isas) h-uint  f-csrn)
732(dnop crn64     "copro Rn (64-bit)"       (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64  f-crn)
733(dnop crn       "copro Rn (32-bit)"       (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr    f-crn)
734(dnop crnx64    "copro Rn (0-31, 64-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr64  f-crnx)
735(dnop crnx      "copro Rn (0-31, 32-bit)" (all-mep-core-isas (CDATA CP_DATA_BUS_INT)) h-cr    f-crnx)
736(dnop ccrn      "copro control reg CCRn"  (all-mep-core-isas (CDATA REGNUM)) h-ccr   f-ccrn)
737(dnop cccc      "copro flags"             (all-mep-core-isas) h-uint  f-rm)
738
739(dprp pcrel8a2  "pc-rel addr (8 bits)"    (all-mep-core-isas (CDATA LABEL) RELAX) h-sint  f-8s8a2   "mep_align" "address")
740(dprp pcrel12a2 "pc-rel addr (12 bits)"   (all-mep-core-isas (CDATA LABEL) RELAX) h-sint  f-12s4a2  "mep_align" "address")
741(dprp pcrel17a2 "pc-rel addr (17 bits)"   (all-mep-core-isas (CDATA LABEL) RELAX) h-sint  f-17s16a2 "mep_align" "address")
742(dprp pcrel24a2 "pc-rel addr (24 bits)"   (all-mep-core-isas (CDATA LABEL))       h-sint  f-24s5a2n "mep_align" "address")
743(dprp pcabs24a2 "pc-abs addr (24 bits)"   (all-mep-core-isas (CDATA LABEL))       h-uint  f-24u5a2n "mep_alignu" "address")
744
745(dpop sdisp16   "displacement (16 bits)"  (all-mep-core-isas) h-sint  f-16s16    "signed16")
746(dpop simm16    "signed imm (16 bits)"    (all-mep-core-isas) h-sint  f-16s16    "signed16")
747(dpop uimm16    "unsigned imm (16 bits)"  (all-mep-core-isas) h-uint  f-16u16    "unsigned16")
748(dnop code16    "uci/dsp code (16 bits)"  (all-mep-core-isas) h-uint  f-16u16)
749
750(dnop udisp2    "SSARB addend (2 bits)"   (all-mep-core-isas) h-sint  f-2u6)
751(dnop uimm2     "interrupt (2 bits)"      (all-mep-core-isas) h-uint  f-2u10)
752
753(dnop simm6     "add const (6 bits)"      (all-mep-core-isas) h-sint  f-6s8)
754(dnop simm8     "mov const (8 bits)"      (all-mep-core-isas RELOC_IMPLIES_OVERFLOW)
755                                             h-sint  f-8s8)
756
757(dpop addr24a4  "sw/lw addr (24 bits)"    (all-mep-core-isas (ALIGN 4)) h-uint  f-24u8a4n  "mep_alignu")
758(dnop code24    "coprocessor code"        (all-mep-core-isas) h-uint  f-24u4n)
759
760(dnop callnum   "system call number"      (all-mep-core-isas) h-uint  f-callnum)
761(dnop uimm3     "bit immediate (3 bits)"  (all-mep-core-isas) h-uint  f-3u5)
762(dnop uimm4     "bCC const (4 bits)"      (all-mep-core-isas) h-uint  f-4u8)
763(dnop uimm5     "bit/shift val (5 bits)"  (all-mep-core-isas) h-uint  f-5u8)
764
765(dpop udisp7    "tp-rel b (7 bits)"       (all-mep-core-isas)           h-uint  f-7u9      "unsigned7")
766(dpop udisp7a2  "tp-rel h (7 bits)"       (all-mep-core-isas (ALIGN 2)) h-uint  f-7u9a2    "unsigned7")
767(dpop udisp7a4  "tp/sp-rel w (7 bits)"    (all-mep-core-isas (ALIGN 4)) h-uint  f-7u9a4    "unsigned7")
768(dpop uimm7a4   "sp w-addend (7 bits)"    (all-mep-core-isas (ALIGN 4)) h-uint  f-7u9a4    "mep_alignu")
769
770(dnop uimm24    "immediate (24 bits)"     (all-mep-core-isas) h-uint  f-24u8n)
771
772(dnop cimm4     "cache immed'te (4 bits)" (all-mep-core-isas) h-uint  f-rn)
773(dnop cimm5     "clip immediate (5 bits)" (all-mep-core-isas) h-uint  f-5u24)
774
775(dpop cdisp10   "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
776(dpop cdisp10a2 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
777(dpop cdisp10a4 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
778(dpop cdisp10a8 "copro addend (8/10 bits)" (all-mep-core-isas) h-sint  f-cdisp10  "cdisp10")
779
780; Special operand representing the various ways that the literal zero can be
781; specified.
782(define-full-operand
783  zero "Zero operand" (all-mep-core-isas) h-sint DFLT f-nil
784  ((parse "zero")) () ()
785)
786
787; Attributes.
788
789(define-attr
790  (for insn)
791  (type boolean)
792  (name OPTIONAL_BIT_INSN)
793  (comment "optional bit manipulation instruction"))
794
795(define-attr
796  (for insn)
797  (type boolean)
798  (name OPTIONAL_MUL_INSN)
799  (comment "optional 32-bit multiply instruction"))
800
801(define-attr
802  (for insn)
803  (type boolean)
804  (name OPTIONAL_DIV_INSN)
805  (comment "optional 32-bit divide instruction"))
806
807(define-attr
808  (for insn)
809  (type boolean)
810  (name OPTIONAL_DEBUG_INSN)
811  (comment "optional debug instruction"))
812
813(define-attr
814  (for insn)
815  (type boolean)
816  (name OPTIONAL_LDZ_INSN)
817  (comment "optional leading zeroes instruction"))
818
819(define-attr
820  (for insn)
821  (type boolean)
822  (name OPTIONAL_ABS_INSN)
823  (comment "optional absolute difference instruction"))
824
825(define-attr
826  (for insn)
827  (type boolean)
828  (name OPTIONAL_AVE_INSN)
829  (comment "optional average instruction"))
830
831(define-attr
832  (for insn)
833  (type boolean)
834  (name OPTIONAL_MINMAX_INSN)
835  (comment "optional min/max instruction"))
836
837(define-attr
838  (for insn)
839  (type boolean)
840  (name OPTIONAL_CLIP_INSN)
841  (comment "optional clipping instruction"))
842
843(define-attr
844  (for insn)
845  (type boolean)
846  (name OPTIONAL_SAT_INSN)
847  (comment "optional saturation instruction"))
848
849(define-attr
850  (for insn)
851  (type boolean)
852  (name OPTIONAL_UCI_INSN)
853  (comment "optional UCI instruction"))
854
855(define-attr
856  (for insn)
857  (type boolean)
858  (name OPTIONAL_DSP_INSN)
859  (comment "optional DSP instruction"))
860
861(define-attr
862  (for insn)
863  (type boolean)
864  (name OPTIONAL_CP_INSN)
865  (comment "optional coprocessor-related instruction"))
866
867(define-attr
868  (for insn)
869  (type boolean)
870  (name OPTIONAL_CP64_INSN)
871  (comment "optional coprocessor-related 64 data bit instruction"))
872
873(define-attr
874  (for insn)
875  (type boolean)
876  (name OPTIONAL_VLIW64)
877  (comment "optional vliw64 mode (vliw32 is default)"))
878
879(define-attr
880  (for insn)
881  (type enum)
882  (name STALL)
883  (attrs META)
884  (values NONE SHIFTI INT2 LOAD STORE LDC STC LDCB STCB SSARB FSFT RET
885	  ADVCK MUL MULR DIV)
886  (default NONE)
887  (comment "gcc stall attribute"))
888
889(define-attr
890  (for insn)
891  (type string)
892  (name INTRINSIC)
893  (attrs META)
894  (comment "gcc intrinsic name"))
895
896(define-attr
897  (for insn)
898  (type enum)
899  (name SLOT)
900  (attrs META)
901  (values NONE C3 V1 V3 P0S P0 P1)
902  (default NONE)
903  (comment "coprocessor slot type"))
904
905(define-attr
906  (for insn)
907  (type boolean)
908  (name MAY_TRAP)
909  (comment "instruction may generate an exception"))
910
911; Attributes for scheduling restrictions in vliw mode
912
913(define-attr
914  (for insn)
915  (type boolean)
916  (name VLIW_ALONE)
917  (comment "instruction can be scheduled alone in vliw mode"))
918
919(define-attr
920  (for insn)
921  (type boolean)
922  (name VLIW_NO_CORE_NOP)
923  (comment "there is no corresponding nop core instruction"))
924
925(define-attr
926  (for insn)
927  (type boolean)
928  (name VLIW_NO_COP_NOP)
929  (comment "there is no corresponding nop coprocessor instruction"))
930
931(define-attr
932  (for insn)
933  (type boolean)
934  (name VLIW64_NO_MATCHING_NOP)
935  (comment "there is no corresponding nop coprocessor instruction"))
936(define-attr
937  (for insn)
938  (type boolean)
939  (name VLIW32_NO_MATCHING_NOP)
940  (comment "there is no corresponding nop coprocessor instruction"))
941
942(define-attr
943  (for insn)
944  (type boolean)
945  (name VOLATILE)
946  (comment "Insn is volatile."))
947
948(define-attr
949  (for insn)
950  (type integer)
951  (name LATENCY)
952  (comment "The latency of this insn, used for scheduling as an intrinsic in gcc")
953  (default 0))
954
955; The MeP config tool will edit this.
956(define-attr
957  (type enum)
958  (for insn)
959  (name CONFIG)
960  (values NONE ; config-attr-start
961	default
962	  ) ; config-attr-end
963)
964
965
966; Enumerations.
967
968(define-normal-insn-enum major "major opcodes" (all-mep-core-isas) MAJ_
969  f-major
970  (.map .str (.iota 16))
971)
972
973
974(define-pmacro (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming isa)
975  (define-insn
976    (name xname)
977    (comment xcomment)
978    (.splice attrs (.unsplice xattrs) (ISA isa))
979    (syntax xsyntax)
980    (format xformat)
981    (semantics xsemantics)
982    (.splice timing (.unsplice xtiming))
983    )
984)
985
986(define-pmacro (dnmi-isa xname xcomment xattrs xsyntax xemit isa)
987  (dnmi xname xcomment (.splice (.unsplice xattrs) (ISA isa)) xsyntax xemit)
988)
989
990; For making profiling calls and dynamic configuration
991(define-pmacro (cg-profile caller callee)
992  (c-call "cg_profile" caller callee)
993)
994; For dynamic configuration only
995(define-pmacro (cg-profile-jump caller callee)
996  (c-call "cg_profile_jump" caller callee)
997)
998
999; For defining Core Instructions
1000(define-pmacro (dnci xname xcomment xattrs xsyntax xformat xsemantics xtiming)
1001  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming all-core-isa-list)
1002)
1003(define-pmacro (dncmi xname xcomment xattrs xsyntax xemit)
1004  (dnmi-isa xname xcomment xattrs xsyntax xemit all-core-isa-list)
1005)
1006
1007; For defining Coprocessor Instructions
1008;(define-pmacro (dncpi xname xcomment xattrs xsyntax xformat xsemantics xtiming)  (dni-isa xname xcomment xattrs xsyntax xformat xsemantics xtiming cop)
1009;)
1010
1011;; flag setting macro
1012(define-pmacro (set-bit xop xbitnum xval)
1013  (set xop (or
1014	    (and xop (inv (sll 1 xbitnum)))
1015	    (and (sll 1 xbitnum) (sll xval xbitnum)))))
1016
1017;; some flags we commonly use in vliw reasoning / mode-switching etc.
1018(define-pmacro (get-opt.vliw64) (and (srl opt 6) 1))
1019(define-pmacro (get-opt.vliw32) (and (srl opt 5) 1))
1020(define-pmacro (get-rm.lsb) (and rm 1))
1021(define-pmacro (get-psw.om) (and (srl psw 12) 1))
1022(define-pmacro (get-psw.nmi) (and (srl psw 9) 1))
1023(define-pmacro (get-psw.iep) (and (srl psw 1) 1))
1024(define-pmacro (get-psw.ump) (and (srl psw 3) 1))
1025(define-pmacro (get-epc.etom) (and epc 1))
1026(define-pmacro (get-npc.ntom) (and npc 1))
1027(define-pmacro (get-lp.ltom) (and lp 1))
1028
1029(define-pmacro (set-psw.om zval) (set-bit (raw-reg h-csr 16) 12 zval))
1030(define-pmacro (set-psw.nmi zval) (set-bit (raw-reg h-csr 16) 9 zval))
1031(define-pmacro (set-psw.umc zval) (set-bit (raw-reg h-csr 16) 2 zval))
1032(define-pmacro (set-psw.iec zval) (set-bit (raw-reg h-csr 16) 0 zval))
1033(define-pmacro (set-rpe.elr zval) (set-bit (raw-reg h-csr 5) 0 zval))
1034
1035
1036;; the "3 way switch" depending on our current operating mode and vliw status flags
1037(define-pmacro (core-vliw-switch core-rtl vliw32-rtl vliw64-rtl)
1038  (cond
1039   ((andif (get-psw.om) (get-opt.vliw64)) vliw64-rtl)
1040   ((andif (get-psw.om) (get-opt.vliw32)) vliw32-rtl)
1041   (else core-rtl)))
1042
1043;; the varying-pcrel idiom
1044(define-pmacro (set-vliw-modified-pcrel-offset xtarg xa xb xc)
1045  (core-vliw-switch (set xtarg (add pc xa))
1046		    (set xtarg (add pc xb))
1047		    (set xtarg (add pc xc))))
1048
1049;; the increasing-alignment idiom in branch displacements
1050(define-pmacro (set-vliw-alignment-modified xtarg zaddr)
1051  (core-vliw-switch (set xtarg (and zaddr (inv 1)))
1052		    (set xtarg (and zaddr (inv 3)))
1053		    (set xtarg (and zaddr (inv 7)))))
1054
1055;; the increasing-alignment idiom in option-only form
1056(define-pmacro (set-vliw-aliignment-modified-by-option xtarg zaddr)
1057  (if (get-opt.vliw32)
1058      (set xtarg (and zaddr (inv 3)))
1059      (set xtarg (and zaddr (inv 7)))))
1060
1061
1062
1063; pmacros needed for coprocessor modulo addressing.
1064
1065; Taken from supplement ``The operation of the modulo addressing'' in
1066; Toshiba documentation rev 2.2, p. 34.
1067
1068(define-pmacro (compute-mask0)
1069  (sequence SI ((SI temp))
1070    (set temp (or mb0 me0))
1071    (srl (const SI -1) (c-call SI "do_ldz" temp))))
1072
1073(define-pmacro (mod0 immed)
1074  (sequence SI ((SI modulo-mask))
1075	    (set modulo-mask (compute-mask0))
1076	    (if SI (eq (and rma modulo-mask) me0)
1077		(or (and rma (inv modulo-mask)) mb0)
1078		(add rma (ext SI immed)))))
1079
1080(define-pmacro (compute-mask1)
1081  (sequence SI ((SI temp))
1082    (set temp (or mb1 me1))
1083    (srl (const SI -1) (c-call SI "do_ldz" temp))))
1084
1085(define-pmacro (mod1 immed)
1086  (sequence SI ((SI modulo-mask))
1087	    (set modulo-mask (compute-mask1))
1088	    (if SI (eq (and rma modulo-mask) me1)
1089		(or (and rma (inv modulo-mask)) mb1)
1090		(add rma (ext SI immed)))))
1091
1092
1093; Instructions.
1094
1095; A pmacro for use in semantic bodies of unimplemented insns.
1096(define-pmacro (unimp mnemonic) (nop))
1097
1098; Core specific instructions
1099; (include "mep-h1.cpu") ; -- exposed by MeP-Integrator
1100(include "mep-c5.cpu") ; -- exposed by MeP-Integrator
1101
1102; Load/store instructions.
1103
1104(dnci sb "store byte (register indirect)" ((STALL STORE))
1105     "sb $rnc,($rma)"
1106     (+ MAJ_0 rnc rma (f-sub4 8))
1107     (sequence ()
1108	       (c-call VOID "check_write_to_text" rma)
1109	       (set (mem UQI rma) (and rnc #xff)))
1110     ((mep (unit u-use-gpr (in usereg rnc))
1111	   (unit u-use-gpr (in usereg rma))
1112	   (unit u-exec))))
1113
1114(dnci sh "store half-word (register indirect)" ((STALL STORE))
1115     "sh $rns,($rma)"
1116     (+ MAJ_0 rns rma (f-sub4 9))
1117     (sequence ()
1118	       (c-call VOID "check_write_to_text" (and rma (inv 1)))
1119	       (set (mem UHI (and rma (inv 1))) (and rns #xffff)))
1120     ((mep (unit u-use-gpr (in usereg rns))
1121	   (unit u-use-gpr (in usereg rma))
1122	   (unit u-exec))))
1123
1124(dnci sw "store word (register indirect)" ((STALL STORE))
1125     "sw $rnl,($rma)"
1126     (+ MAJ_0 rnl rma (f-sub4 10))
1127     (sequence ()
1128	       (c-call VOID "check_write_to_text" (and rma (inv 3)))
1129	       (set (mem USI (and rma (inv 3))) rnl))
1130     ((mep (unit u-use-gpr (in usereg rnl))
1131	   (unit u-use-gpr (in usereg rma))
1132	   (unit u-exec))))
1133
1134(dnci lb "load byte (register indirect)" ((STALL LOAD) (LATENCY 2))
1135     "lb $rnc,($rma)"
1136     (+ MAJ_0 rnc rma (f-sub4 12))
1137     (set rnc (ext SI (mem QI rma)))
1138     ((mep (unit u-use-gpr (in usereg rma))
1139	   (unit u-exec)
1140	   (unit u-load-gpr (out loadreg rnc)))))
1141
1142(dnci lh "load half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
1143     "lh $rns,($rma)"
1144     (+ MAJ_0 rns rma (f-sub4 13))
1145     (set rns (ext SI (mem HI (and rma (inv 1)))))
1146     ((mep (unit u-use-gpr (in usereg rma))
1147	   (unit u-exec)
1148	   (unit u-load-gpr (out loadreg rns)))))
1149
1150(dnci lw "load word (register indirect)" ((STALL LOAD) (LATENCY 2))
1151     "lw $rnl,($rma)"
1152     (+ MAJ_0 rnl rma (f-sub4 14))
1153     (set rnl (mem SI (and rma (inv 3))))
1154     ((mep (unit u-use-gpr (in usereg rma))
1155	   (unit u-exec)
1156	   (unit u-load-gpr (out loadreg rnl)))))
1157
1158(dnci lbu "load unsigned byte (register indirect)" ((STALL LOAD) (LATENCY 2))
1159     "lbu $rnuc,($rma)"
1160     (+ MAJ_0 rnuc rma (f-sub4 11))
1161     (set rnuc (zext SI (mem UQI rma)))
1162     ((mep (unit u-use-gpr (in usereg rma))
1163	   (unit u-exec)
1164	   (unit u-load-gpr (out loadreg rnuc)))))
1165
1166(dnci lhu "load unsigned half-word (register indirect)" ((STALL LOAD) (LATENCY 2))
1167     "lhu $rnus,($rma)"
1168     (+ MAJ_0 rnus rma (f-sub4 15))
1169     (set rnus (zext SI (mem UHI (and rma (inv 1)))))
1170     ((mep (unit u-use-gpr (in usereg rma))
1171	   (unit u-exec)
1172	   (unit u-load-gpr (out loadreg rnus)))))
1173
1174(dnci sw-sp "store word (sp relative)" ((STALL STORE))
1175     "sw $rnl,$udisp7a4($spr)"
1176     (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 2))
1177     (sequence ()
1178	       (c-call VOID "check_write_to_text" (and (add udisp7a4 sp) (inv 3)))
1179	       (set (mem SI (and (add udisp7a4 sp) (inv 3))) rnl))
1180     ((mep (unit u-use-gpr (in usereg rnl))
1181	   (unit u-use-gpr (in usereg sp))
1182	   (unit u-exec))))
1183
1184
1185(dnci lw-sp "load word (sp relative)" ((STALL LOAD) (LATENCY 2))
1186     "lw $rnl,$udisp7a4($spr)"
1187     (+ MAJ_4 rnl (f-8 0) udisp7a4 (f-sub2 3))
1188     (set rnl (mem SI (and (add udisp7a4 sp) (inv 3))))
1189     ((mep (unit u-use-gpr (in usereg sp))
1190	   (unit u-exec)
1191	   (unit u-load-gpr (out loadreg rnl)))))
1192
1193(dnci sb-tp "store byte (tp relative)" ((STALL STORE))
1194     "sb $rn3c,$udisp7($tpr)"
1195     (+ MAJ_8 (f-4 0) rn3c (f-8 0) udisp7)
1196     (sequence ()
1197	       (c-call VOID "check_write_to_text" (add (zext SI udisp7) tp))
1198	       (set (mem QI (add (zext SI udisp7) tp)) (and rn3c #xff)))
1199     ((mep (unit u-use-gpr (in usereg rn3c))
1200	   (unit u-use-gpr (in usereg tp))
1201	   (unit u-exec))))
1202
1203(dnci sh-tp "store half-word (tp relative)" ((STALL STORE))
1204     "sh $rn3s,$udisp7a2($tpr)"
1205     (+ MAJ_8 (f-4 0) rn3s (f-8 1) udisp7a2 (f-15 0))
1206     (sequence ()
1207	       (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a2) tp) (inv 1)))
1208	       (set (mem HI (and (add (zext SI udisp7a2) tp) (inv 1))) (and rn3s #xffff)))
1209     ((mep (unit u-use-gpr (in usereg rn3s))
1210	   (unit u-use-gpr (in usereg tp))
1211	   (unit u-exec))))
1212
1213(dnci sw-tp "store word (tp relative)" ((STALL STORE))
1214     "sw $rn3l,$udisp7a4($tpr)"
1215     (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 2))
1216     (sequence ()
1217	       (c-call VOID "check_write_to_text" (and (add (zext SI udisp7a4) tp) (inv 3)))
1218	       (set (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))) rn3l))
1219     ((mep (unit u-use-gpr (in usereg rn3l))
1220	   (unit u-use-gpr (in usereg tp))
1221	   (unit u-exec))))
1222
1223(dnci lb-tp "load byte (tp relative)" ((STALL LOAD) (LATENCY 2))
1224     "lb $rn3c,$udisp7($tpr)"
1225     (+ MAJ_8 (f-4 1) rn3c (f-8 0) udisp7)
1226     (set rn3c (ext SI (mem QI (add (zext SI udisp7) tp))))
1227     ((mep (unit u-use-gpr (in usereg tp))
1228	   (unit u-exec)
1229	   (unit u-load-gpr (out loadreg rn3c)))))
1230
1231(dnci lh-tp "load half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
1232     "lh $rn3s,$udisp7a2($tpr)"
1233     (+ MAJ_8 (f-4 1) rn3s (f-8 1) udisp7a2 (f-15 0))
1234     (set rn3s (ext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
1235     ((mep (unit u-use-gpr (in usereg tp))
1236	   (unit u-exec)
1237	   (unit u-load-gpr (out loadreg rn3s)))))
1238
1239(dnci lw-tp "load word (tp relative)" ((STALL LOAD) (LATENCY 2))
1240     "lw $rn3l,$udisp7a4($tpr)"
1241     (+ MAJ_4 (f-4 0) rn3l (f-8 1) udisp7a4 (f-sub2 3))
1242     (set rn3l (mem SI (and (add (zext SI udisp7a4) tp) (inv 3))))
1243     ((mep (unit u-use-gpr (in usereg tp))
1244	   (unit u-exec)
1245	   (unit u-load-gpr (out loadreg rn3l)))))
1246
1247(dnci lbu-tp "load unsigned byte (tp relative)" ((STALL LOAD) (LATENCY 2))
1248     "lbu $rn3uc,$udisp7($tpr)"
1249     (+ MAJ_4 (f-4 1) rn3uc (f-8 1) udisp7)
1250     (set rn3uc (zext SI (mem QI (add (zext SI udisp7) tp))))
1251     ((mep (unit u-use-gpr (in usereg tp))
1252	   (unit u-exec)
1253	   (unit u-load-gpr (out loadreg rn3uc)))))
1254
1255(dnci lhu-tp "load unsigned half-word (tp relative)" ((STALL LOAD) (LATENCY 2))
1256     "lhu $rn3us,$udisp7a2($tpr)"
1257     (+ MAJ_8 (f-4 1) rn3us (f-8 1) udisp7a2 (f-15 1))
1258     (set rn3us (zext SI (mem HI (and (add (zext SI udisp7a2) tp) (inv 1)))))
1259     ((mep (unit u-use-gpr (in usereg tp))
1260	   (unit u-exec)
1261	   (unit u-load-gpr (out loadreg rn3us)))))
1262
1263(dnci sb16 "store byte (16 bit displacement)" ((STALL STORE))
1264     "sb $rnc,$sdisp16($rma)"
1265     (+ MAJ_12 rnc rma (f-sub4 8) sdisp16)
1266     (sequence ()
1267	       (c-call VOID "check_write_to_text" (add rma (ext SI sdisp16)))
1268	       (set (mem QI (add rma (ext SI sdisp16))) (and rnc #xff)))
1269     ((mep (unit u-use-gpr (in usereg rnc))
1270	   (unit u-use-gpr (in usereg rma))
1271	   (unit u-exec))))
1272
1273(dnci sh16 "store half-word (16 bit displacement)" ((STALL STORE))
1274     "sh $rns,$sdisp16($rma)"
1275     (+ MAJ_12 rns rma (f-sub4 9) sdisp16)
1276     (sequence ()
1277	       (c-call VOID "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 1)))
1278	       (set (mem HI (and (add rma (ext SI sdisp16)) (inv 1))) (and rns #xffff)))
1279     ((mep (unit u-use-gpr (in usereg rns))
1280	   (unit u-use-gpr (in usereg rma))
1281	   (unit u-exec))))
1282
1283(dnci sw16 "store word (16 bit displacement)" ((STALL STORE))
1284     "sw $rnl,$sdisp16($rma)"
1285     (+ MAJ_12 rnl rma (f-sub4 10) sdisp16)
1286     (sequence ()
1287	       (c-call "check_write_to_text" (and (add rma (ext SI sdisp16)) (inv 3)))
1288	       (set (mem SI (and (add rma (ext SI sdisp16)) (inv 3))) rnl))
1289     ((mep (unit u-use-gpr (in usereg rnl))
1290	   (unit u-use-gpr (in usereg rma))
1291	   (unit u-exec))))
1292
1293(dnci lb16 "load byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1294     "lb $rnc,$sdisp16($rma)"
1295     (+ MAJ_12 rnc rma (f-sub4 12) sdisp16)
1296     (set rnc (ext SI (mem QI (add rma (ext SI sdisp16)))))
1297     ((mep (unit u-use-gpr (in usereg rma))
1298	   (unit u-exec)
1299	   (unit u-load-gpr (out loadreg rnc)))))
1300
1301(dnci lh16 "load half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1302     "lh $rns,$sdisp16($rma)"
1303     (+ MAJ_12 rns rma (f-sub4 13) sdisp16)
1304     (set rns (ext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
1305     ((mep (unit u-use-gpr (in usereg rma))
1306	   (unit u-exec)
1307	   (unit u-load-gpr (out loadreg rns)))))
1308
1309(dnci lw16 "load word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1310     "lw $rnl,$sdisp16($rma)"
1311     (+ MAJ_12 rnl rma (f-sub4 14) sdisp16)
1312     (set rnl (mem SI (and (add rma (ext SI sdisp16)) (inv 3))))
1313     ((mep (unit u-use-gpr (in usereg rma))
1314	   (unit u-exec)
1315	   (unit u-load-gpr (out loadreg rnl)))))
1316
1317(dnci lbu16 "load unsigned byte (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1318     "lbu $rnuc,$sdisp16($rma)"
1319     (+ MAJ_12 rnuc rma (f-sub4 11) sdisp16)
1320     (set rnuc (zext SI (mem QI (add rma (ext SI sdisp16)))))
1321     ((mep (unit u-use-gpr (in usereg rma))
1322	   (unit u-exec)
1323	   (unit u-load-gpr (out loadreg rnuc)))))
1324
1325(dnci lhu16 "load unsigned half-word (16 bit displacement)" ((STALL LOAD) (LATENCY 2))
1326     "lhu $rnus,$sdisp16($rma)"
1327     (+ MAJ_12 rnus rma (f-sub4 15) sdisp16)
1328     (set rnus (zext SI (mem HI (and (add rma (ext SI sdisp16)) (inv 1)))))
1329     ((mep (unit u-use-gpr (in usereg rma))
1330	   (unit u-exec)
1331	   (unit u-load-gpr (out loadreg rnus)))))
1332
1333(dnci sw24 "store word (24 bit absolute addressing)" ((STALL STORE))
1334     "sw $rnl,($addr24a4)"
1335     (+ MAJ_14 rnl addr24a4 (f-sub2 2))
1336     (sequence ()
1337	       (c-call VOID "check_write_to_text" (zext SI addr24a4))
1338	       (set (mem SI (zext SI addr24a4)) rnl))
1339     ((mep (unit u-use-gpr (in usereg rnl))
1340	   (unit u-exec))))
1341
1342(dnci lw24 "load word (24 bit absolute addressing)" ((STALL LOAD) (LATENCY 2))
1343     "lw $rnl,($addr24a4)"
1344     (+ MAJ_14 rnl addr24a4 (f-sub2 3))
1345     (set rnl (mem SI (zext SI addr24a4)))
1346     ((mep (unit u-exec)
1347	   (unit u-load-gpr (out loadreg rnl)))))
1348
1349
1350; Extension instructions.
1351
1352(dnci extb "sign extend byte" ()
1353     "extb $rn"
1354     (+ MAJ_1 rn (f-rm 0) (f-sub4 13))
1355     (set rn (ext SI (and QI rn #xff)))
1356     ((mep (unit u-use-gpr (in usereg rn))
1357	   (unit u-exec))))
1358
1359(dnci exth "sign extend half-word" ()
1360     "exth $rn"
1361     (+ MAJ_1 rn (f-rm 2) (f-sub4 13))
1362     (set rn (ext SI (and HI rn #xffff)))
1363     ((mep (unit u-use-gpr (in usereg rn))
1364	   (unit u-exec))))
1365
1366(dnci extub "zero extend byte" ()
1367     "extub $rn"
1368     (+ MAJ_1 rn (f-rm 8) (f-sub4 13))
1369     (set rn (zext SI (and rn #xff)))
1370     ((mep (unit u-use-gpr (in usereg rn))
1371	   (unit u-exec))))
1372
1373(dnci extuh "zero extend half-word" ()
1374     "extuh $rn"
1375     (+ MAJ_1 rn (f-rm 10) (f-sub4 13))
1376     (set rn (zext SI (and rn #xffff)))
1377     ((mep (unit u-use-gpr (in usereg rn))
1378	   (unit u-exec))))
1379
1380
1381; Shift amount manipulation instructions.
1382
1383(dnci ssarb "set sar to bytes" ((STALL SSARB) VOLATILE)
1384     "ssarb $udisp2($rm)"
1385     (+ MAJ_1 (f-4 0) (f-5 0) udisp2 rm (f-sub4 12))
1386     (if (c-call BI "big_endian_p")
1387         (set sar (zext SI (mul (and (add udisp2 rm) 3) 8)))
1388         (set sar (sub 32 (zext SI (mul (and (add udisp2 rm) 3) 8)))))
1389     ((mep (unit u-use-gpr (in usereg rm))
1390	   (unit u-exec))))
1391
1392
1393; Move instructions.
1394
1395(dnci mov "move" ()
1396     "mov $rn,$rm"
1397     (+ MAJ_0 rn rm (f-sub4 0))
1398     (set rn rm)
1399     ((mep (unit u-use-gpr (in usereg rm))
1400	   (unit u-exec))))
1401
1402(dnci movi8 "move 8-bit immediate" ()
1403     "mov $rn,$simm8"
1404     (+ MAJ_5 rn simm8)
1405     (set rn (ext SI simm8))
1406     ())
1407
1408(dnci movi16 "move 16-bit immediate" ()
1409     "mov $rn,$simm16"
1410     (+ MAJ_12 rn (f-rm 0) (f-sub4 1) simm16)
1411     (set rn (ext SI simm16))
1412     ())
1413
1414(dnci movu24 "move 24-bit unsigned immediate" ()
1415     "movu $rn3,$uimm24"
1416     (+ MAJ_13 (f-4 0) rn3 uimm24)
1417     (set rn3 (zext SI uimm24))
1418     ())
1419
1420(dnci movu16 "move 16-bit unsigned immediate" ()
1421     "movu $rn,$uimm16"
1422     (+ MAJ_12 rn (f-rm 1) (f-sub4 1) uimm16)
1423     (set rn (zext SI uimm16))
1424     ())
1425
1426(dnci movh "move high 16-bit immediate" ()
1427     "movh $rn,$uimm16"
1428     (+ MAJ_12 rn (f-rm 2) (f-sub4 1) uimm16)
1429     (set rn (sll uimm16 16))
1430     ())
1431
1432
1433; Arithmetic instructions.
1434
1435(dnci add3 "add three registers" ()
1436     "add3 $rl,$rn,$rm"
1437     (+ MAJ_9 rn rm rl)
1438     (set rl (add rn rm))
1439     ((mep (unit u-use-gpr (in usereg rn))
1440           (unit u-use-gpr (in usereg rm))
1441	   (unit u-exec))))
1442
1443(dnci add "add" ()
1444     "add $rn,$simm6"
1445     (+ MAJ_6 rn simm6 (f-sub2 0))
1446     (set rn (add rn (ext SI simm6)))
1447     ((mep (unit u-use-gpr (in usereg rn))
1448	   (unit u-exec))))
1449
1450(dnci add3i "add two registers and immediate" ()
1451     "add3 $rn,$spr,$uimm7a4"
1452     (+ MAJ_4 rn (f-8 0) uimm7a4 (f-sub2 0))
1453     (set rn (add sp (zext SI uimm7a4)))
1454     ((mep (unit u-use-gpr (in usereg sp))
1455	   (unit u-exec))))
1456
1457(dnci advck3 "add overflow check" ((STALL ADVCK))
1458     "advck3 \\$0,$rn,$rm"
1459     (+ MAJ_0 rn rm (f-sub4 7))
1460     (if (add-oflag rn rm 0)
1461	 (set r0 1)
1462	 (set r0 0))
1463     ((mep (unit u-use-gpr (in usereg rn))
1464           (unit u-use-gpr (in usereg rm))
1465	   (unit u-exec))))
1466
1467(dnci sub "subtract" ()
1468     "sub $rn,$rm"
1469     (+ MAJ_0 rn rm (f-sub4 4))
1470     (set rn (sub rn rm))
1471     ((mep (unit u-use-gpr (in usereg rn))
1472           (unit u-use-gpr (in usereg rm)))))
1473
1474(dnci sbvck3 "subtraction overflow check" ((STALL ADVCK))
1475     "sbvck3 \\$0,$rn,$rm"
1476     (+ MAJ_0 rn rm (f-sub4 5))
1477     (if (sub-oflag rn rm 0)
1478	 (set r0 1)
1479	 (set r0 0))
1480     ((mep (unit u-use-gpr (in usereg rn))
1481           (unit u-use-gpr (in usereg rm))
1482	   (unit u-exec))))
1483
1484(dnci neg "negate" ()
1485     "neg $rn,$rm"
1486     (+ MAJ_0 rn rm (f-sub4 1))
1487     (set rn (neg rm))
1488     ((mep (unit u-use-gpr (in usereg rm))
1489	   (unit u-exec))))
1490
1491(dnci slt3 "set if less than" ()
1492     "slt3 \\$0,$rn,$rm"
1493     (+ MAJ_0 rn rm (f-sub4 2))
1494     (if (lt rn rm)
1495	 (set r0 1)
1496	 (set r0 0))
1497     ((mep (unit u-use-gpr (in usereg rn))
1498           (unit u-use-gpr (in usereg rm))
1499	   (unit u-exec))))
1500
1501(dnci sltu3 "set less than unsigned" ()
1502     "sltu3 \\$0,$rn,$rm"
1503     (+ MAJ_0 rn rm (f-sub4 3))
1504     (if (ltu rn rm)
1505	 (set r0 1)
1506	 (set r0 0))
1507     ((mep (unit u-use-gpr (in usereg rn))
1508           (unit u-use-gpr (in usereg rm))
1509	   (unit u-exec))))
1510
1511(dnci slt3i "set if less than immediate" ()
1512     "slt3 \\$0,$rn,$uimm5"
1513     (+ MAJ_6 rn uimm5 (f-sub3 1))
1514     (if (lt rn (zext SI uimm5))
1515	 (set r0 1)
1516	 (set r0 0))
1517     ((mep (unit u-use-gpr (in usereg rn))
1518	   (unit u-exec))))
1519
1520(dnci sltu3i "set if less than unsigned immediate" ()
1521     "sltu3 \\$0,$rn,$uimm5"
1522     (+ MAJ_6 rn uimm5 (f-sub3 5))
1523     (if (ltu rn (zext SI uimm5))
1524	 (set r0 1)
1525	 (set r0 0))
1526     ())
1527
1528(dnci sl1ad3 "shift left one and add" ((STALL INT2))
1529     "sl1ad3 \\$0,$rn,$rm"
1530     (+ MAJ_2 rn rm (f-sub4 6))
1531     (set r0 (add (sll rn 1) rm))
1532     ((mep (unit u-use-gpr (in usereg rn))
1533           (unit u-use-gpr (in usereg rm))
1534	   (unit u-exec))))
1535
1536(dnci sl2ad3 "shift left two and add" ((STALL INT2))
1537     "sl2ad3 \\$0,$rn,$rm"
1538     (+ MAJ_2 rn rm (f-sub4 7))
1539     (set r0 (add (sll rn 2) rm))
1540     ((mep (unit u-use-gpr (in usereg rn))
1541           (unit u-use-gpr (in usereg rm))
1542	   (unit u-exec))))
1543
1544(dnci add3x "three operand add (extended)" ()
1545     "add3 $rn,$rm,$simm16"
1546     (+ MAJ_12 rn rm (f-sub4 0) simm16)
1547     (set rn (add rm (ext SI simm16)))
1548     ((mep (unit u-use-gpr (in usereg rm))
1549	   (unit u-exec))))
1550
1551(dnci slt3x "set if less than (extended)" ()
1552     "slt3 $rn,$rm,$simm16"
1553     (+ MAJ_12 rn rm (f-sub4 2) simm16)
1554     (if (lt rm (ext SI simm16))
1555	 (set rn 1)
1556	 (set rn 0))
1557     ((mep (unit u-use-gpr (in usereg rm))
1558	   (unit u-exec))))
1559
1560(dnci sltu3x "set if less than unsigned (extended)" ()
1561     "sltu3 $rn,$rm,$uimm16"
1562     (+ MAJ_12 rn rm (f-sub4 3) uimm16)
1563     (if (ltu rm (zext SI uimm16))
1564	 (set rn 1)
1565	 (set rn 0))
1566     ((mep (unit u-use-gpr (in usereg rm))
1567	   (unit u-exec))))
1568
1569
1570; Logical instructions.
1571
1572(dnci or "bitwise or" ()
1573     "or $rn,$rm"
1574     (+ MAJ_1 rn rm (f-sub4 0))
1575     (set rn (or rn rm))
1576     ((mep (unit u-use-gpr (in usereg rn))
1577           (unit u-use-gpr (in usereg rm))
1578	   (unit u-exec))))
1579
1580(dnci and "bitwise and" ()
1581     "and $rn,$rm"
1582     (+ MAJ_1 rn rm (f-sub4 1))
1583     (set rn (and rn rm))
1584     ((mep (unit u-use-gpr (in usereg rn))
1585           (unit u-use-gpr (in usereg rm))
1586	   (unit u-exec))))
1587
1588(dnci xor "bitwise exclusive or" ()
1589     "xor $rn,$rm"
1590     (+ MAJ_1 rn rm (f-sub4 2))
1591     (set rn (xor rn rm))
1592     ((mep (unit u-use-gpr (in usereg rn))
1593           (unit u-use-gpr (in usereg rm))
1594	   (unit u-exec))))
1595
1596(dnci nor "bitwise negated or" ()
1597     "nor $rn,$rm"
1598     (+ MAJ_1 rn rm (f-sub4 3))
1599     (set rn (inv (or rn rm)))
1600     ((mep (unit u-use-gpr (in usereg rn))
1601           (unit u-use-gpr (in usereg rm))
1602	   (unit u-exec))))
1603
1604(dnci or3 "or three operand" ()
1605     "or3 $rn,$rm,$uimm16"
1606     (+ MAJ_12 rn rm (f-sub4 4) uimm16)
1607     (set rn (or rm (zext SI uimm16)))
1608     ((mep (unit u-use-gpr (in usereg rm))
1609	   (unit u-exec))))
1610
1611(dnci and3 "and three operand" ()
1612     "and3 $rn,$rm,$uimm16"
1613     (+ MAJ_12 rn rm (f-sub4 5) uimm16)
1614     (set rn (and rm (zext SI uimm16)))
1615     ((mep (unit u-use-gpr (in usereg rm))
1616	   (unit u-exec))))
1617
1618(dnci xor3 "exclusive or three operand" ()
1619     "xor3 $rn,$rm,$uimm16"
1620     (+ MAJ_12 rn rm (f-sub4 6) uimm16)
1621     (set rn (xor rm (zext SI uimm16)))
1622     ((mep (unit u-use-gpr (in usereg rm))
1623	   (unit u-exec))))
1624
1625
1626; Shift instructions.
1627
1628(dnci sra "shift right arithmetic" ((STALL INT2))
1629     "sra $rn,$rm"
1630     (+ MAJ_2 rn rm (f-sub4 13))
1631     (set rn (sra rn (and rm #x1f)))
1632     ((mep (unit u-use-gpr (in usereg rn))
1633           (unit u-use-gpr (in usereg rm))
1634	   (unit u-exec))))
1635
1636(dnci srl "shift right logical" ((STALL INT2))
1637     "srl $rn,$rm"
1638     (+ MAJ_2 rn rm (f-sub4 12))
1639     (set rn (srl rn (and rm #x1f)))
1640     ((mep (unit u-use-gpr (in usereg rn))
1641           (unit u-use-gpr (in usereg rm))
1642	   (unit u-exec))))
1643
1644(dnci sll "shift left logical" ((STALL INT2))
1645     "sll $rn,$rm"
1646     (+ MAJ_2 rn rm (f-sub4 14))
1647     (set rn (sll rn (and rm #x1f)))
1648     ((mep (unit u-use-gpr (in usereg rn))
1649           (unit u-use-gpr (in usereg rm))
1650	   (unit u-exec))))
1651
1652(dnci srai "shift right arithmetic (immediate)" ((STALL SHIFTI))
1653     "sra $rn,$uimm5"
1654     (+ MAJ_6 rn uimm5 (f-sub3 3))
1655     (set rn (sra rn uimm5))
1656     ((mep (unit u-use-gpr (in usereg rn))
1657	   (unit u-exec))))
1658
1659(dnci srli "shift right logical (immediate)" ((STALL SHIFTI))
1660     "srl $rn,$uimm5"
1661     (+ MAJ_6 rn uimm5 (f-sub3 2))
1662     (set rn (srl rn uimm5))
1663     ((mep (unit u-use-gpr (in usereg rn))
1664	   (unit u-exec))))
1665
1666(dnci slli "shift left logical (immediate)" ((STALL SHIFTI))
1667     "sll $rn,$uimm5"
1668     (+ MAJ_6 rn uimm5 (f-sub3 6))
1669     (set rn (sll rn uimm5))
1670     ((mep (unit u-use-gpr (in usereg rn))
1671	   (unit u-exec))))
1672
1673(dnci sll3 "three-register shift left logical" ((STALL INT2))
1674     "sll3 \\$0,$rn,$uimm5"
1675     (+ MAJ_6 rn uimm5 (f-sub3 7))
1676     (set r0 (sll rn uimm5))
1677     ((mep (unit u-use-gpr (in usereg rn))
1678	   (unit u-exec))))
1679
1680(dnci fsft "field shift" ((STALL FSFT) VOLATILE)
1681     "fsft $rn,$rm"
1682     (+ MAJ_2 rn rm (f-sub4 15))
1683     (sequence ((DI temp) (QI shamt))
1684	       (set shamt (and sar #x3f))
1685	       (set temp (sll (or (sll (zext DI rn) 32) (zext DI rm)) shamt))
1686	       (set rn (subword SI (srl temp 32) 1)))
1687     ((mep (unit u-use-gpr (in usereg rn))
1688           (unit u-use-gpr (in usereg rm))
1689	   (unit u-exec))))
1690
1691
1692; Branch/jump instructions.
1693
1694(dnci bra "branch" (RELAXABLE)
1695     "bra $pcrel12a2"
1696     (+ MAJ_11 pcrel12a2 (f-15 0))
1697     (set-vliw-alignment-modified pc pcrel12a2)
1698     ((mep (unit u-branch)
1699	   (unit u-exec))))
1700
1701(dnci beqz "branch if equal zero" (RELAXABLE)
1702     "beqz $rn,$pcrel8a2"
1703     (+ MAJ_10 rn pcrel8a2 (f-15 0))
1704     (if (eq rn 0)
1705	 (set-vliw-alignment-modified pc pcrel8a2))
1706     ((mep (unit u-use-gpr (in usereg rn))
1707	   (unit u-exec)
1708	   (unit u-branch))))
1709
1710(dnci bnez "branch if not equal zero" (RELAXABLE)
1711     "bnez $rn,$pcrel8a2"
1712     (+ MAJ_10 rn pcrel8a2 (f-15 1))
1713     (if (ne rn 0)
1714	 (set-vliw-alignment-modified pc pcrel8a2))
1715     ((mep (unit u-use-gpr (in usereg rn))
1716	   (unit u-exec)
1717	   (unit u-branch))))
1718
1719(dnci beqi "branch equal immediate" (RELAXABLE)
1720     "beqi $rn,$uimm4,$pcrel17a2"
1721     (+ MAJ_14 rn uimm4 (f-sub4 0) pcrel17a2)
1722     (if (eq rn (zext SI uimm4))
1723	 (set-vliw-alignment-modified pc pcrel17a2))
1724     ((mep (unit u-use-gpr (in usereg rn))
1725	   (unit u-exec)
1726	   (unit u-branch))))
1727
1728(dnci bnei "branch not equal immediate" (RELAXABLE)
1729     "bnei $rn,$uimm4,$pcrel17a2"
1730     (+ MAJ_14 rn uimm4 (f-sub4 4) pcrel17a2)
1731     (if (ne rn (zext SI uimm4))
1732	 (set-vliw-alignment-modified pc pcrel17a2))
1733     ((mep (unit u-use-gpr (in usereg rn))
1734	   (unit u-exec)
1735	   (unit u-branch))))
1736
1737(dnci blti "branch less than immediate" (RELAXABLE)
1738     "blti $rn,$uimm4,$pcrel17a2"
1739     (+ MAJ_14 rn uimm4 (f-sub4 12) pcrel17a2)
1740     (if (lt rn (zext SI uimm4))
1741	 (set-vliw-alignment-modified pc pcrel17a2))
1742     ((mep (unit u-use-gpr (in usereg rn))
1743	   (unit u-exec)
1744	   (unit u-branch))))
1745
1746(dnci bgei "branch greater than immediate" (RELAXABLE)
1747     "bgei $rn,$uimm4,$pcrel17a2"
1748     (+ MAJ_14 rn uimm4 (f-sub4 8) pcrel17a2)
1749     (if (ge rn (zext SI uimm4))
1750	 (set-vliw-alignment-modified pc pcrel17a2))
1751     ((mep (unit u-use-gpr (in usereg rn))
1752	   (unit u-exec)
1753	   (unit u-branch))))
1754
1755(dnci beq "branch equal" ()
1756     "beq $rn,$rm,$pcrel17a2"
1757     (+ MAJ_14 rn rm (f-sub4 1) pcrel17a2)
1758     (if (eq rn rm)
1759	 (set-vliw-alignment-modified pc pcrel17a2))
1760     ((mep (unit u-use-gpr (in usereg rn))
1761           (unit u-use-gpr (in usereg rm))
1762	   (unit u-exec)
1763	   (unit u-branch))))
1764
1765(dnci bne "branch not equal" ()
1766     "bne $rn,$rm,$pcrel17a2"
1767     (+ MAJ_14 rn rm (f-sub4 5) pcrel17a2)
1768     (if (ne rn rm)
1769	 (set-vliw-alignment-modified pc pcrel17a2))
1770     ((mep (unit u-use-gpr (in usereg rn))
1771           (unit u-use-gpr (in usereg rm))
1772	   (unit u-exec)
1773	   (unit u-branch))))
1774
1775(dnci bsr12 "branch to subroutine (12 bit displacement)" (RELAXABLE)
1776     "bsr $pcrel12a2"
1777     (+ MAJ_11 pcrel12a2 (f-15 1))
1778     (sequence ()
1779	       (cg-profile pc pcrel12a2)
1780	       (set-vliw-modified-pcrel-offset lp 2 4 8)
1781	       (set-vliw-alignment-modified pc pcrel12a2))
1782     ((mep (unit u-exec)
1783	   (unit u-branch))))
1784
1785(dnci bsr24 "branch to subroutine (24 bit displacement)" ()
1786     "bsr $pcrel24a2"
1787     (+ MAJ_13 (f-4 1) (f-sub4 9) pcrel24a2)
1788     (sequence ()
1789	       (cg-profile pc pcrel24a2)
1790	       (set-vliw-modified-pcrel-offset lp 4 4 8)
1791	       (set-vliw-alignment-modified pc pcrel24a2))
1792     ((mep (unit u-exec)
1793	   (unit u-branch))))
1794
1795(dnci jmp "jump" ()
1796     "jmp $rm"
1797     (+ MAJ_1 (f-rn 0) rm (f-sub4 14))
1798     (sequence ()
1799	       (if (eq (get-psw.om) 0)
1800		   ;; core mode
1801		   (if (get-rm.lsb)
1802		       (sequence ()
1803				 (set-psw.om 1) ;; enter VLIW mode
1804				 (set-vliw-aliignment-modified-by-option pc rm))
1805		       (set pc (and rm (inv 1))))
1806		   ;; VLIW mode
1807		   (if (get-rm.lsb)
1808		       (sequence ()
1809				 (set-psw.om 0) ;; enter core mode
1810				 (set pc (and rm (inv 1))))
1811		       (set-vliw-aliignment-modified-by-option pc rm)))
1812	       (cg-profile-jump pc rm))
1813     ((mep (unit u-use-gpr (in usereg rm))
1814	   (unit u-exec)
1815	   (unit u-branch))))
1816
1817(dnci jmp24 "jump (24 bit target)" ()
1818     "jmp $pcabs24a2"
1819     (+ MAJ_13 (f-4 1) (f-sub4 8) pcabs24a2)
1820     (sequence ()
1821	       (set-vliw-alignment-modified pc (or (and pc #xf0000000) pcabs24a2))
1822	       (cg-profile-jump pc pcabs24a2))
1823     ((mep (unit u-exec)
1824	   (unit u-branch))))
1825
1826(dnci jsr "jump to subroutine" ()
1827     "jsr $rm"
1828     (+ MAJ_1 (f-rn 0) rm (f-sub4 15))
1829     (sequence ()
1830	       (cg-profile pc rm)
1831	       (set-vliw-modified-pcrel-offset lp 2 4 8)
1832	       (set-vliw-alignment-modified pc rm))
1833     ((mep (unit u-use-gpr (in usereg rm))
1834	   (unit u-exec)
1835	   (unit u-branch))))
1836
1837(dnci ret "return from subroutine" ((STALL RET))
1838     "ret"
1839     (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 2))
1840     (sequence ()
1841	       (if (eq (get-psw.om) 0)
1842		   ;; core mode
1843		   (if (get-lp.ltom) ;; link-pointer "toggle mode" bit
1844		       (sequence ()
1845				 (set-psw.om 1) ;; enter VLIW mode
1846				 (set-vliw-aliignment-modified-by-option pc lp))
1847		       (set pc (and lp (inv 1))))
1848		   ;; VLIW mode
1849		   (if (get-lp.ltom) ;; link-pointer "toggle mode" bit
1850		       (sequence ()
1851				 (set-psw.om 0) ;; enter VLIW mode
1852				 (set pc (and lp (inv 1))))
1853		       (set-vliw-aliignment-modified-by-option pc lp)))
1854	       (c-call VOID "notify_ret" pc))
1855     ((mep (unit u-exec)
1856	   (unit u-branch))))
1857
1858
1859; Repeat instructions.
1860
1861(dnci repeat "repeat specified repeat block" ()
1862     "repeat $rn,$pcrel17a2"
1863     (+ MAJ_14 rn (f-rm 0) (f-sub4 9) pcrel17a2)
1864     (sequence ()
1865	       (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
1866	       (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
1867	       (set (reg h-csr 6) rn))
1868     ((mep (unit u-use-gpr (in usereg rn))
1869	   (unit u-exec))))
1870
1871(dnci erepeat "endless repeat" ()
1872     "erepeat $pcrel17a2"
1873     (+ MAJ_14 (f-rn 0) (f-rm 1) (f-sub4 9) pcrel17a2)
1874     (sequence ()
1875	       (set-vliw-modified-pcrel-offset (reg h-csr 4) 4 4 8)
1876	       (set-vliw-alignment-modified (reg h-csr 5) pcrel17a2)
1877	       (set-rpe.elr 1)
1878	       ; rpc may be undefined for erepeat
1879	       ; use 1 to trigger repeat logic in the sim's main loop
1880	       (set (reg h-csr 6) 1))
1881     ())
1882
1883
1884; Control instructions.
1885
1886;; special store variants
1887
1888(dnci stc_lp "store to control register lp" ((STALL STC))
1889      "stc $rn,\\$lp"
1890      (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
1891      (set lp rn)
1892      ((mep (unit u-use-gpr (in usereg rn))
1893	    (unit u-store-ctrl-reg (out storereg lp))
1894	    (unit u-exec))))
1895
1896(dnci stc_hi "store to control register hi" ((STALL STC))
1897      "stc $rn,\\$hi"
1898      (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
1899      (set hi rn)
1900      ((mep (unit u-use-gpr (in usereg rn))
1901	    (unit u-store-ctrl-reg (out storereg hi))
1902	    (unit u-exec))))
1903
1904(dnci stc_lo "store to control register lo" ((STALL STC))
1905      "stc $rn,\\$lo"
1906      (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 0))
1907      (set lo rn)
1908      ((mep (unit u-use-gpr (in usereg rn))
1909	    (unit u-store-ctrl-reg (out storereg lo))
1910	    (unit u-exec))))
1911
1912;; general store
1913
1914(dnci stc "store to control register" (VOLATILE (STALL STC))
1915     "stc $rn,$csrn"
1916     (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 0))
1917     (set csrn rn)
1918     ((mep (unit u-use-gpr (in usereg rn))
1919	   (unit u-store-ctrl-reg (out storereg csrn))
1920	   (unit u-exec))))
1921
1922;; special load variants
1923
1924(dnci ldc_lp "load from control register lp" ((STALL LDC))
1925      "ldc $rn,\\$lp"
1926      (+ MAJ_7 rn (f-csrn-lo 1) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
1927      (set rn lp)
1928      ((mep (unit u-use-ctrl-reg (in usereg lp))
1929	    (unit u-exec)
1930	    (unit u-load-gpr (out loadreg rn)))))
1931
1932
1933(dnci ldc_hi "load from control register hi" ((STALL LDC))
1934      "ldc $rn,\\$hi"
1935      (+ MAJ_7 rn (f-csrn-lo 7) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
1936      (set rn hi)
1937      ((mep (unit u-use-ctrl-reg (in usereg hi))
1938	    (unit u-exec)
1939	    (unit u-load-gpr (out loadreg rn)))))
1940
1941(dnci ldc_lo "load from control register lo" ((STALL LDC))
1942      "ldc $rn,\\$lo"
1943      (+ MAJ_7 rn (f-csrn-lo 8) (f-csrn-hi 0) (f-12 1) (f-13 0) (f-14 1))
1944      (set rn lo)
1945      ((mep (unit u-use-ctrl-reg (in usereg lo))
1946	    (unit u-exec)
1947	    (unit u-load-gpr (out loadreg rn)))))
1948
1949;; general load
1950
1951(dnci ldc "load from control register" (VOLATILE (STALL LDC) (LATENCY 2))
1952     "ldc $rn,$csrn"
1953     (+ MAJ_7 rn csrn (f-12 1) (f-13 0) (f-14 1))
1954     (if (eq (ifield f-csrn) 0)
1955	 ;; loading from the pc
1956	 (set-vliw-modified-pcrel-offset rn 2 4 8)
1957	 ;; loading from something else
1958	 (set rn csrn))
1959      ((mep (unit u-use-ctrl-reg (in usereg csrn))
1960	    (unit u-exec)
1961	    (unit u-load-gpr (out loadreg rn)))))
1962
1963(dnci di "disable interrupt" (VOLATILE)
1964     "di"
1965     (+ MAJ_7 (f-rn 0) (f-rm 0) (f-sub4 0))
1966     ; clear psw.iec
1967     (set psw (sll (srl psw 1) 1))
1968     ())
1969
1970(dnci ei "enable interrupt" (VOLATILE)
1971     "ei"
1972     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 0))
1973     ; set psw.iec
1974     (set psw (or psw 1))
1975     ())
1976
1977(dnci reti "return from interrupt" ((STALL RET))
1978     "reti"
1979     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 2))
1980     (if (eq (get-psw.om) 0)
1981	 ;; core operation mode
1982	 (if (get-psw.nmi)
1983	     ;; return from NMI
1984	     (if (get-npc.ntom)
1985		 ;; return in VLIW operation mode
1986		 (sequence ()
1987			   (set-psw.om 1)
1988			   (set-vliw-aliignment-modified-by-option pc npc)
1989			   (set-psw.nmi 0))
1990		 ;; return in core mode
1991		 (sequence ()
1992			   (set pc (and npc (inv 1)))
1993			   (set-psw.nmi 0)))
1994	     ;; return from non-NMI
1995	     (if (get-epc.etom)
1996		 ;; return in VLIW mode
1997		 (sequence ()
1998			   (set-psw.om 1)
1999			   (set-vliw-aliignment-modified-by-option pc epc)
2000			   (set-psw.umc (get-psw.ump))
2001			   (set-psw.iec (get-psw.iep)))
2002		 ;; return in core mode
2003		 (sequence ()
2004			   (set pc (and epc (inv 1)))
2005			   (set-psw.umc (get-psw.ump))
2006			   (set-psw.iec (get-psw.iep)))))
2007	 ;; VLIW operation mode
2008	 ;; xxx undefined
2009	 (nop))
2010     ((mep (unit u-exec)
2011	   (unit u-branch))))
2012
2013(dnci halt "halt pipeline" (VOLATILE)
2014     "halt"
2015     (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 2))
2016     ; set psw.halt
2017     (set (raw-reg h-csr 16) (or psw (sll 1 11)))
2018     ())
2019
2020(dnci sleep "sleep pipeline" (VOLATILE)
2021     "sleep"
2022     (+ MAJ_7 (f-rn 0) (f-rm 6) (f-sub4 2))
2023     (c-call VOID "do_sleep")
2024     ())
2025
2026(dnci swi "software interrupt" (MAY_TRAP VOLATILE)
2027     "swi $uimm2"
2028     (+ MAJ_7 (f-rn 0) (f-8 0) (f-9 0) uimm2 (f-sub4 6))
2029     (cond
2030      ((eq uimm2 0) (set exc (or exc (sll 1 4))))
2031      ((eq uimm2 1) (set exc (or exc (sll 1 5))))
2032      ((eq uimm2 2) (set exc (or exc (sll 1 6))))
2033      ((eq uimm2 3) (set exc (or exc (sll 1 7)))))
2034     ())
2035
2036(dnci break "break exception" (MAY_TRAP VOLATILE)
2037     "break"
2038     (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 2))
2039     (set pc (c-call USI "break_exception" pc))
2040     ((mep (unit u-exec)
2041	   (unit u-branch))))
2042
2043(dnci syncm "synchronise with memory" (VOLATILE)
2044     "syncm"
2045     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 1))
2046     (unimp "syncm")
2047     ())
2048
2049(dnci stcb "store in control bus space" (VOLATILE (STALL STCB))
2050     "stcb $rn,$uimm16"
2051     (+ MAJ_15 rn (f-rm 0) (f-sub4 4) uimm16)
2052     (c-call VOID "do_stcb" rn uimm16)
2053     ((mep (unit u-use-gpr (in usereg rn))
2054	   (unit u-exec)
2055	   (unit u-stcb))))
2056
2057(dnci ldcb "load from control bus space" (VOLATILE (STALL LDCB) (LATENCY 3))
2058     "ldcb $rn,$uimm16"
2059     (+ MAJ_15 rn (f-rm 1) (f-sub4 4) uimm16)
2060     (set rn (c-call SI "do_ldcb" uimm16))
2061      ((mep (unit u-ldcb)
2062	    (unit u-exec)
2063	    (unit u-ldcb-gpr (out loadreg rn)))))
2064
2065
2066; Bit manipulation instructions.
2067; The following instructions become the reserved instruction when the
2068; bit manipulation option is off.
2069
2070(dnci bsetm "set bit in memory" (OPTIONAL_BIT_INSN)
2071     "bsetm ($rma),$uimm3"
2072     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 0))
2073     (sequence ()
2074	       (c-call "check_option_bit" pc)
2075	       (set (mem UQI rma) (or (mem UQI rma) (sll 1 uimm3))))
2076     ((mep (unit u-use-gpr (in usereg rma))
2077	   (unit u-exec))))
2078
2079(dnci bclrm "clear bit in memory" (OPTIONAL_BIT_INSN)
2080     "bclrm ($rma),$uimm3"
2081     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 1))
2082     (sequence ()
2083	       (c-call "check_option_bit" pc)
2084	       (set (mem UQI rma) (and (mem UQI rma) (inv (sll 1 uimm3)))))
2085     ((mep (unit u-use-gpr (in usereg rma))
2086	   (unit u-exec))))
2087
2088(dnci bnotm "toggle bit in memory" (OPTIONAL_BIT_INSN)
2089     "bnotm ($rma),$uimm3"
2090     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 2))
2091     (sequence ()
2092	       (c-call "check_option_bit" pc)
2093	       (set (mem UQI rma) (xor (mem UQI rma) (sll 1 uimm3))))
2094     ((mep (unit u-use-gpr (in usereg rma))
2095	   (unit u-exec))))
2096
2097(dnci btstm "test bit in memory" (OPTIONAL_BIT_INSN)
2098     "btstm \\$0,($rma),$uimm3"
2099     (+ MAJ_2 (f-4 0) uimm3 rma (f-sub4 3))
2100     (sequence ()
2101	       (c-call "check_option_bit" pc)
2102	       (set r0 (zext SI (and UQI (mem UQI rma) (sll 1 uimm3)))))
2103     ((mep (unit u-use-gpr (in usereg rma))
2104	   (unit u-exec))))
2105
2106(dnci tas "test and set" (OPTIONAL_BIT_INSN)
2107     "tas $rn,($rma)"
2108     (+ MAJ_2 rn rma (f-sub4 4))
2109     (sequence ((SI result))
2110	       (c-call "check_option_bit" pc)
2111	       (set result (zext SI (mem UQI rma)))
2112	       (set (mem UQI rma) 1)
2113	       (set rn result))
2114     ((mep (unit u-use-gpr (in usereg rma))
2115	   (unit u-exec))))
2116
2117
2118; Data cache instruction.
2119
2120(dnci cache "cache operations" (VOLATILE)
2121     "cache $cimm4,($rma)"
2122     (+ MAJ_7 cimm4 rma (f-sub4 4))
2123     (c-call VOID "do_cache" cimm4 rma pc)
2124     ((mep (unit u-use-gpr (in usereg rma))
2125	   (unit u-exec))))
2126
2127
2128; Multiply instructions.
2129; These instructions become the RI when the 32-bit multiply
2130; instruction option is off.
2131
2132(dnci mul "multiply" (OPTIONAL_MUL_INSN (STALL MUL))
2133     "mul $rn,$rm"
2134     (+ MAJ_1 rn rm (f-sub4 4))
2135     (sequence ((DI result))
2136	       (c-call "check_option_mul" pc)
2137	       (set result (mul (ext DI rn) (ext DI rm)))
2138	       (set hi (subword SI result 0))
2139	       (set lo (subword SI result 1)))
2140     ((mep (unit u-use-gpr (in usereg rn))
2141	   (unit u-use-gpr (in usereg rm))
2142	   (unit u-exec)
2143	   (unit u-multiply))))
2144
2145(dnci mulu "multiply unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
2146     "mulu $rn,$rm"
2147     (+ MAJ_1 rn rm (f-sub4 5))
2148     (sequence ((DI result))
2149	       (c-call "check_option_mul" pc)
2150	       (set result (mul (zext UDI rn) (zext UDI rm)))
2151	       (set hi (subword SI result 0))
2152	       (set lo (subword SI result 1)))
2153     ((mep (unit u-use-gpr (in usereg rn))
2154	   (unit u-use-gpr (in usereg rm))
2155	   (unit u-exec)
2156	   (unit u-multiply))))
2157
2158(dnci mulr "multiply, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2159     "mulr $rn,$rm"
2160     (+ MAJ_1 rn rm (f-sub4 6))
2161     (sequence ((DI result))
2162	       (c-call "check_option_mul" pc)
2163	       (set result (mul (ext DI rn) (ext DI rm)))
2164	       (set hi (subword SI result 0))
2165	       (set lo (subword SI result 1))
2166	       (set rn (subword SI result 1)))
2167     ((mep (unit u-use-gpr (in usereg rn))
2168	   (unit u-use-gpr (in usereg rm))
2169	   (unit u-exec)
2170	   (unit u-multiply)
2171	   (unit u-mul-gpr (out resultreg rn)))))
2172
2173(dnci mulru "multiply unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2174     "mulru $rn,$rm"
2175     (+ MAJ_1 rn rm (f-sub4 7))
2176     (sequence ((DI result))
2177	       (c-call "check_option_mul" pc)
2178	       (set result (mul (zext UDI rn) (zext UDI rm)))
2179	       (set hi (subword SI result 0))
2180	       (set lo (subword SI result 1))
2181	       (set rn (subword SI result 1)))
2182     ((mep (unit u-use-gpr (in usereg rn))
2183	   (unit u-use-gpr (in usereg rm))
2184	   (unit u-exec)
2185	   (unit u-multiply)
2186	   (unit u-mul-gpr (out resultreg rn)))))
2187
2188(dnci madd "multiply accumulate" (OPTIONAL_MUL_INSN (STALL MUL))
2189     "madd $rn,$rm"
2190     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3004))
2191     (sequence ((DI result))
2192	       (c-call "check_option_mul" pc)
2193	       (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2194	       (set result (add result (mul (ext DI rn) (ext DI rm))))
2195	       (set hi (subword SI result 0))
2196	       (set lo (subword SI result 1)))
2197     ((mep (unit u-use-gpr (in usereg rn))
2198	   (unit u-use-gpr (in usereg rm))
2199	   (unit u-exec)
2200	   (unit u-multiply))))
2201
2202(dnci maddu "multiply accumulate unsigned" (OPTIONAL_MUL_INSN (STALL MUL))
2203     "maddu $rn,$rm"
2204     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3005))
2205     (sequence ((DI result))
2206	       (c-call "check_option_mul" pc)
2207	       (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2208	       (set result (add result (mul (zext UDI rn) (zext UDI rm))))
2209	       (set hi (subword SI result 0))
2210	       (set lo (subword SI result 1)))
2211     ((mep (unit u-use-gpr (in usereg rn))
2212	   (unit u-use-gpr (in usereg rm))
2213	   (unit u-exec)
2214	   (unit u-multiply))))
2215
2216
2217(dnci maddr "multiply accumulate, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2218     "maddr $rn,$rm"
2219     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3006))
2220     (sequence ((DI result))
2221	       (c-call "check_option_mul" pc)
2222	       (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2223	       (set result (add result (mul (ext DI rn) (ext DI rm))))
2224	       (set hi (subword SI result 0))
2225	       (set lo (subword SI result 1))
2226	       (set rn (subword SI result 1)))
2227     ((mep (unit u-use-gpr (in usereg rn))
2228	   (unit u-use-gpr (in usereg rm))
2229	   (unit u-exec)
2230	   (unit u-multiply)
2231	   (unit u-mul-gpr (out resultreg rn)))))
2232
2233(dnci maddru "multiple accumulate unsigned, lo -> reg" (OPTIONAL_MUL_INSN (STALL MULR) (LATENCY 3))
2234     "maddru $rn,$rm"
2235     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 #x3007))
2236     (sequence ((DI result))
2237	       (c-call "check_option_mul" pc)
2238	       (set result (or (sll (zext DI hi) 32) (zext DI lo)))
2239	       (set result (add result (mul (zext UDI rn) (zext UDI rm))))
2240	       (set hi (subword SI result 0))
2241	       (set lo (subword SI result 1))
2242	       (set rn (subword SI result 1)))
2243     ((mep (unit u-use-gpr (in usereg rn))
2244	   (unit u-use-gpr (in usereg rm))
2245	   (unit u-exec)
2246	   (unit u-multiply)
2247	   (unit u-mul-gpr (out resultreg rn)))))
2248
2249
2250; Divide instructions.
2251; These instructions become the RI when the 32-bit divide instruction
2252; option is off.
2253
2254(dnci div "divide" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
2255     "div $rn,$rm"
2256     (+ MAJ_1 rn rm (f-sub4 8))
2257     (sequence ()
2258	       (c-call "check_option_div" pc)
2259	       (if (eq rm 0)
2260		   (set pc (c-call USI "zdiv_exception" pc))
2261		   ; Special case described on p. 76.
2262		   (if (and (eq rn #x80000000)
2263			    (eq rm #xffffffff))
2264		       (sequence ()
2265				 (set lo #x80000000)
2266				 (set hi 0))
2267		       (sequence ()
2268				 (set lo (div rn rm))
2269				 (set hi (mod rn rm))))))
2270     ((mep (unit u-use-gpr (in usereg rn))
2271	   (unit u-use-gpr (in usereg rm))
2272	   (unit u-exec)
2273	   (unit u-divide)
2274           (unit u-branch))))
2275
2276(dnci divu "divide unsigned" (OPTIONAL_DIV_INSN (STALL DIV) (LATENCY 34) MAY_TRAP)
2277     "divu $rn,$rm"
2278     (+ MAJ_1 rn rm (f-sub4 9))
2279     (sequence ()
2280	       (c-call "check_option_div" pc)
2281	       (if (eq rm 0)
2282		   (set pc (c-call USI "zdiv_exception" pc))
2283		   (sequence ()
2284			     (set lo (udiv rn rm))
2285			     (set hi (umod rn rm)))))
2286     ((mep (unit u-use-gpr (in usereg rn))
2287	   (unit u-use-gpr (in usereg rm))
2288	   (unit u-exec)
2289	   (unit u-divide)
2290           (unit u-branch))))
2291
2292
2293; Debug functions.
2294; These instructions become the RI when the debug function option is
2295; off.
2296
2297(dnci dret "return from debug exception" (OPTIONAL_DEBUG_INSN)
2298     "dret"
2299     (+ MAJ_7 (f-rn 0) (f-rm 1) (f-sub4 3))
2300     (sequence ()
2301	       (c-call "check_option_debug" pc)
2302	       ; set DBG.DM.
2303	       (set dbg (and dbg (inv (sll SI 1 15))))
2304	       (set pc depc))
2305     ((mep (unit u-exec)
2306	   (unit u-branch))))
2307
2308(dnci dbreak "generate debug exception" (OPTIONAL_DEBUG_INSN MAY_TRAP VOLATILE)
2309     "dbreak"
2310     (+ MAJ_7 (f-rn 0) (f-rm 3) (f-sub4 3))
2311     (sequence ()
2312	       (c-call "check_option_debug" pc)
2313	       ; set DBG.DPB.
2314	       (set dbg (or dbg 1)))
2315     ())
2316
2317
2318; Leading zero instruction.
2319
2320(dnci ldz "leading zeroes" (OPTIONAL_LDZ_INSN (STALL INT2))
2321     "ldz $rn,$rm"
2322     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 0))
2323     (sequence ()
2324	       (c-call "check_option_ldz" pc)
2325	       (set rn (c-call SI "do_ldz" rm)))
2326     ((mep (unit u-use-gpr (in usereg rm))
2327	   (unit u-exec))))
2328
2329
2330; Absolute difference instruction.
2331
2332(dnci abs "absolute difference" (OPTIONAL_ABS_INSN (STALL INT2))
2333     "abs $rn,$rm"
2334     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 3))
2335     (sequence ()
2336	       (c-call "check_option_abs" pc)
2337	       (set rn (abs (sub rn rm))))
2338     ((mep (unit u-use-gpr (in usereg rm))
2339	   (unit u-use-gpr (in usereg rn))
2340	   (unit u-exec))))
2341
2342
2343; Average instruction.
2344
2345(dnci ave "average" (OPTIONAL_AVE_INSN (STALL INT2))
2346     "ave $rn,$rm"
2347     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 2))
2348     (sequence ()
2349	       (c-call "check_option_ave" pc)
2350	       (set rn (sra (add (add rn rm) 1) 1)))
2351     ((mep (unit u-use-gpr (in usereg rm))
2352	   (unit u-use-gpr (in usereg rn))
2353	   (unit u-exec))))
2354
2355
2356; MIN/MAX instructions.
2357
2358(dnci min "minimum" (OPTIONAL_MINMAX_INSN (STALL INT2))
2359     "min $rn,$rm"
2360     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 4))
2361     (sequence ()
2362	       (c-call "check_option_minmax" pc)
2363	       (if (gt rn rm)
2364		   (set rn rm)))
2365     ((mep (unit u-use-gpr (in usereg rm))
2366	   (unit u-use-gpr (in usereg rn))
2367	   (unit u-exec))))
2368
2369(dnci max "maximum" (OPTIONAL_MINMAX_INSN (STALL INT2))
2370     "max $rn,$rm"
2371     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 5))
2372     (sequence ()
2373	       (c-call "check_option_minmax" pc)
2374	       (if (lt rn rm)
2375		   (set rn rm)))
2376     ((mep (unit u-use-gpr (in usereg rm))
2377	   (unit u-use-gpr (in usereg rn))
2378	   (unit u-exec))))
2379
2380(dnci minu "minimum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
2381     "minu $rn,$rm"
2382     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 6))
2383     (sequence ()
2384	       (c-call "check_option_minmax" pc)
2385	       (if (gtu rn rm)
2386		   (set rn rm)))
2387     ((mep (unit u-use-gpr (in usereg rm))
2388	   (unit u-use-gpr (in usereg rn))
2389	   (unit u-exec))))
2390
2391(dnci maxu "maximum unsigned" (OPTIONAL_MINMAX_INSN (STALL INT2))
2392     "maxu $rn,$rm"
2393     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 7))
2394     (sequence ()
2395	       (c-call "check_option_minmax" pc)
2396	       (if (ltu rn rm)
2397		   (set rn rm)))
2398     ((mep (unit u-use-gpr (in usereg rm))
2399	   (unit u-use-gpr (in usereg rn))
2400	   (unit u-exec))))
2401
2402
2403; Clipping instruction.
2404
2405(dnci clip "clip" (OPTIONAL_CLIP_INSN (STALL INT2))
2406     "clip $rn,$cimm5"
2407     (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 0))
2408     (sequence ((SI min) (SI max))
2409	       (c-call "check_option_clip" pc)
2410	       (set max (sub (sll 1 (sub cimm5 1)) 1))
2411	       (set min (neg (sll 1 (sub cimm5 1))))
2412	       (cond
2413		((eq cimm5 0) (set rn 0))
2414		((gt rn max) (set rn max))
2415		((lt rn min) (set rn min))))
2416     ((mep (unit u-use-gpr (in usereg rn))
2417	   (unit u-exec))))
2418
2419(dnci clipu "clip unsigned" (OPTIONAL_CLIP_INSN (STALL INT2))
2420     "clipu $rn,$cimm5"
2421     (+ MAJ_15 rn (f-rm 0) (f-sub4 1) (f-ext #x10) cimm5 (f-29 0) (f-30 0) (f-31 1))
2422     (sequence ((SI max))
2423	       (c-call "check_option_clip" pc)
2424	       (set max (sub (sll 1 cimm5) 1))
2425	       (cond
2426		((eq cimm5 0) (set rn 0))
2427		((gt rn max) (set rn max))
2428		((lt rn 0) (set rn 0))))
2429     ((mep (unit u-use-gpr (in usereg rn))
2430	   (unit u-exec))))
2431
2432
2433; Saturation instructions.
2434
2435(dnci sadd "saturating addition" (OPTIONAL_SAT_INSN (STALL INT2))
2436     "sadd $rn,$rm"
2437     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 8))
2438     (sequence ()
2439	       (c-call "check_option_sat" pc)
2440	       (if (add-oflag rn rm 0)
2441		   (if (nflag rn)
2442		       ; underflow
2443		       (set rn (neg (sll 1 31)))
2444		       ; overflow
2445		       (set rn (sub (sll 1 31) 1)))
2446		   (set rn (add rn rm))))
2447     ((mep (unit u-use-gpr (in usereg rm))
2448	   (unit u-use-gpr (in usereg rn))
2449	   (unit u-exec))))
2450
2451(dnci ssub "saturating subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
2452     "ssub $rn,$rm"
2453     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 10))
2454     (sequence ()
2455	       (c-call "check_option_sat" pc)
2456	       (if (sub-oflag rn rm 0)
2457		   (if (nflag rn)
2458		       ; underflow
2459		       (set rn (neg (sll 1 31)))
2460		       ; overflow
2461		       (set rn (sub (sll 1 31) 1)))
2462		   (set rn (sub rn rm))))
2463     ((mep (unit u-use-gpr (in usereg rm))
2464	   (unit u-use-gpr (in usereg rn))
2465	   (unit u-exec))))
2466
2467(dnci saddu "saturating unsigned addition" (OPTIONAL_SAT_INSN (STALL INT2))
2468     "saddu $rn,$rm"
2469     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 9))
2470     (sequence ()
2471	       (c-call "check_option_sat" pc)
2472	       (if (add-cflag rn rm 0)
2473		   (set rn (inv 0))
2474		   (set rn (add rn rm))))
2475     ((mep (unit u-use-gpr (in usereg rm))
2476	   (unit u-use-gpr (in usereg rn))
2477	   (unit u-exec))))
2478
2479(dnci ssubu "saturating unsigned subtraction" (OPTIONAL_SAT_INSN (STALL INT2))
2480     "ssubu $rn,$rm"
2481     (+ MAJ_15 rn rm (f-sub4 1) (f-16u16 11))
2482     (sequence ()
2483	       (c-call "check_option_sat" pc)
2484	       (if (sub-cflag rn rm 0)
2485		   (set rn 0)
2486		   (set rn (sub rn rm))))
2487     ((mep (unit u-use-gpr (in usereg rm))
2488	   (unit u-use-gpr (in usereg rn))
2489	   (unit u-exec))))
2490
2491
2492; UCI and DSP options are defined in an external file.
2493; See `mep-sample-ucidsp.cpu' for a sample.
2494
2495
2496; Coprocessor instructions.
2497
2498(dnci swcp "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2499     "swcp $crn,($rma)"
2500     (+ MAJ_3 crn rma (f-sub4 8))
2501     (sequence ()
2502	       (c-call "check_option_cp" pc)
2503	       (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2504	       (set (mem SI (and rma (inv SI 3))) crn))
2505     ((mep (unit u-use-gpr (in usereg rma))
2506	   (unit u-exec))))
2507
2508(dnci lwcp "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2509     "lwcp $crn,($rma)"
2510     (+ MAJ_3 crn rma (f-sub4 9))
2511     (sequence ()
2512	       (c-call "check_option_cp" pc)
2513	       (set crn (mem SI (and rma (inv SI 3)))))
2514     ((mep (unit u-use-gpr (in usereg rma))
2515	   (unit u-exec))))
2516
2517(dnci smcp "smcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2518     "smcp $crn64,($rma)"
2519     (+ MAJ_3 crn64 rma (f-sub4 10))
2520     (sequence ()
2521	       (c-call "check_option_cp" pc)
2522	       (c-call "check_option_cp64" pc)
2523	       (c-call VOID "check_write_to_text" rma)
2524	       (c-call "do_smcp" rma crn64 pc))
2525     ((mep (unit u-use-gpr (in usereg rma))
2526	   (unit u-exec))))
2527
2528(dnci lmcp "lmcp" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2529     "lmcp $crn64,($rma)"
2530     (+ MAJ_3 crn64 rma (f-sub4 11))
2531     (sequence ()
2532	       (c-call "check_option_cp" pc)
2533	       (c-call "check_option_cp64" pc)
2534	       (set crn64 (c-call DI "do_lmcp" rma pc)))
2535     ((mep (unit u-use-gpr (in usereg rma))
2536	   (unit u-exec))))
2537
2538(dnci swcpi "swcp (post-increment)" (OPTIONAL_CP_INSN (STALL STORE))
2539     "swcpi $crn,($rma+)"
2540     (+ MAJ_3 crn rma (f-sub4 0))
2541     (sequence ()
2542	       (c-call "check_option_cp" pc)
2543	       (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2544	       (set (mem SI (and rma (inv SI 3))) crn)
2545	       (set rma (add rma 4)))
2546     ((mep (unit u-use-gpr (in usereg rma))
2547	   (unit u-exec))))
2548
2549(dnci lwcpi "lwcp (post-increment)" (OPTIONAL_CP_INSN (STALL LOAD))
2550     "lwcpi $crn,($rma+)"
2551     (+ MAJ_3 crn rma (f-sub4 1))
2552     (sequence ()
2553	       (c-call "check_option_cp" pc)
2554	       (set crn (mem SI (and rma (inv SI 3))))
2555	       (set rma (add rma 4)))
2556     ((mep (unit u-use-gpr (in usereg rma))
2557	   (unit u-exec))))
2558
2559(dnci smcpi "smcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2560     "smcpi $crn64,($rma+)"
2561     (+ MAJ_3 crn64 rma (f-sub4 2))
2562     (sequence ()
2563	       (c-call "check_option_cp" pc)
2564	       (c-call "check_option_cp64" pc)
2565	       (c-call VOID "check_write_to_text" rma)
2566	       (c-call "do_smcpi" (index-of rma) crn64 pc)
2567	       (set rma rma)) ; reference as output for intrinsic generation
2568     ((mep (unit u-use-gpr (in usereg rma))
2569	   (unit u-exec))))
2570
2571(dnci lmcpi "lmcp (post-increment)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2572     "lmcpi $crn64,($rma+)"
2573     (+ MAJ_3 crn64 rma (f-sub4 3))
2574     (sequence ()
2575	       (c-call "check_option_cp" pc)
2576	       (c-call "check_option_cp64" pc)
2577	       (set crn64 (c-call DI "do_lmcpi" (index-of rma) pc))
2578	       (set rma rma)) ; reference as output for intrinsic generation
2579     ((mep (unit u-use-gpr (in usereg rma))
2580	   (unit u-exec))))
2581
2582(dnci swcp16 "swcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL STORE))
2583     "swcp $crn,$sdisp16($rma)"
2584     (+ MAJ_15 crn rma (f-sub4 12) sdisp16)
2585     (sequence ()
2586	       (c-call "check_option_cp" pc)
2587	       (set (mem SI (and (add rma sdisp16) (inv SI 3))) crn))
2588     ((mep (unit u-use-gpr (in usereg rma))
2589	   (unit u-exec))))
2590
2591(dnci lwcp16 "lwcp (16-bit displacement)" (OPTIONAL_CP_INSN (STALL LOAD))
2592     "lwcp $crn,$sdisp16($rma)"
2593     (+ MAJ_15 crn rma (f-sub4 13) sdisp16)
2594     (sequence ()
2595	       (c-call "check_option_cp" pc)
2596	       (set crn (mem SI (and (add rma sdisp16) (inv SI 3)))))
2597     ((mep (unit u-use-gpr (in usereg rma))
2598	   (unit u-exec))))
2599
2600(dnci smcp16 "smcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2601     "smcp $crn64,$sdisp16($rma)"
2602     (+ MAJ_15 crn64 rma (f-sub4 14) sdisp16)
2603     (sequence ()
2604	       (c-call "check_option_cp" pc)
2605	       (c-call "check_option_cp64" pc)
2606	       (c-call "do_smcp16" rma sdisp16 crn64 pc))
2607     ((mep (unit u-use-gpr (in usereg rma))
2608	   (unit u-exec))))
2609
2610(dnci lmcp16 "lmcp (16-bit displacement)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2611     "lmcp $crn64,$sdisp16($rma)"
2612     (+ MAJ_15 crn64 rma (f-sub4 15) sdisp16)
2613     (sequence ()
2614	       (c-call "check_option_cp" pc)
2615	       (c-call "check_option_cp64" pc)
2616	       (set crn64 (c-call DI "do_lmcp16" rma sdisp16 pc)))
2617     ((mep (unit u-use-gpr (in usereg rma))
2618	   (unit u-exec))))
2619
2620(dnci sbcpa "store byte coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2621     "sbcpa $crn,($rma+),$cdisp10"
2622     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 0) (f-ext62 0) cdisp10)
2623     (sequence ()
2624	       (c-call "check_option_cp" pc)
2625	       (c-call VOID "check_write_to_text" rma)
2626	       (set (mem QI rma) (and crn #xff))
2627	       (set rma (add rma (ext SI cdisp10))))
2628     ((mep (unit u-use-gpr (in usereg rma))
2629	   (unit u-exec))))
2630
2631(dnci lbcpa "load byte coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2632     "lbcpa $crn,($rma+),$cdisp10"
2633     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x0) cdisp10)
2634     (sequence ()
2635	       (c-call "check_option_cp" pc)
2636	       (set crn (ext SI (mem QI rma)))
2637	       (set rma (add rma (ext SI cdisp10))))
2638     ((mep (unit u-use-gpr (in usereg rma))
2639	   (unit u-exec))))
2640
2641(dnci shcpa "store half-word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2642     "shcpa $crn,($rma+),$cdisp10a2"
2643     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x0) cdisp10a2)
2644     (sequence ()
2645	       (c-call "check_option_cp" pc)
2646	       (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
2647	       (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
2648	       (set rma (add rma (ext SI cdisp10a2))))
2649     ((mep (unit u-use-gpr (in usereg rma))
2650	   (unit u-exec))))
2651
2652(dnci lhcpa "load half-word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2653     "lhcpa $crn,($rma+),$cdisp10a2"
2654     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x0) cdisp10a2)
2655     (sequence ()
2656	       (c-call "check_option_cp" pc)
2657	       (set crn (ext SI (mem HI (and rma (inv SI 1)))))
2658	       (set rma (add rma (ext SI cdisp10a2))))
2659     ((mep (unit u-use-gpr (in usereg rma))
2660	   (unit u-exec))))
2661
2662(dnci swcpa "store word coprocessor" (OPTIONAL_CP_INSN (STALL STORE))
2663     "swcpa $crn,($rma+),$cdisp10a4"
2664     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x0) cdisp10a4)
2665     (sequence ()
2666	       (c-call "check_option_cp" pc)
2667	       (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2668	       (set (mem SI (and rma (inv SI 3))) crn)
2669	       (set rma (add rma (ext SI cdisp10a4))))
2670     ((mep (unit u-use-gpr (in usereg rma))
2671	   (unit u-exec))))
2672
2673(dnci lwcpa "load word coprocessor" (OPTIONAL_CP_INSN (STALL LOAD))
2674     "lwcpa $crn,($rma+),$cdisp10a4"
2675     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x0) cdisp10a4)
2676     (sequence ()
2677	       (c-call "check_option_cp" pc)
2678	       (set crn (mem SI (and rma (inv SI 3))))
2679	       (set rma (add rma (ext SI cdisp10a4))))
2680     ((mep (unit u-use-gpr (in usereg rma))
2681	   (unit u-exec))))
2682
2683(dnci smcpa "smcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL STORE))
2684     "smcpa $crn64,($rma+),$cdisp10a8"
2685     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x0) cdisp10a8)
2686     (sequence ()
2687	       (c-call "check_option_cp" pc)
2688	       (c-call "check_option_cp64" pc)
2689	       (c-call VOID "check_write_to_text" rma)
2690	       (c-call "do_smcpa" (index-of rma) cdisp10a8 crn64 pc)
2691	       (set rma rma)) ; reference as output for intrinsic generation
2692     ((mep (unit u-use-gpr (in usereg rma))
2693	   (unit u-exec))))
2694
2695(dnci lmcpa "lmcpa" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN (STALL LOAD))
2696     "lmcpa $crn64,($rma+),$cdisp10a8"
2697     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x0) cdisp10a8)
2698     (sequence ()
2699	       (c-call "check_option_cp" pc)
2700	       (c-call "check_option_cp64" pc)
2701	       (set crn64 (c-call DI "do_lmcpa" (index-of rma) cdisp10a8 pc))
2702	       (set rma rma)) ; reference as output for intrinsic generation
2703     ((mep (unit u-use-gpr (in usereg rma))
2704	   (unit u-exec))))
2705
2706
2707(dnci sbcpm0 "sbcpm0" (OPTIONAL_CP_INSN)
2708     "sbcpm0 $crn,($rma+),$cdisp10"
2709     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x2) cdisp10)
2710     (sequence ()
2711	       (c-call "check_option_cp" pc)
2712	       (c-call VOID "check_write_to_text" rma)
2713	       (set (mem QI rma) (and crn #xff))
2714	       (set rma (mod0 cdisp10)))
2715     ((mep (unit u-use-gpr (in usereg rma))
2716	   (unit u-exec))))
2717
2718(dnci lbcpm0 "lbcpm0" (OPTIONAL_CP_INSN)
2719     "lbcpm0 $crn,($rma+),$cdisp10"
2720     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x2) cdisp10)
2721     (sequence ()
2722	       (c-call "check_option_cp" pc)
2723	       (set crn (ext SI (mem QI rma)))
2724	       (set rma (mod0 cdisp10)))
2725     ((mep (unit u-use-gpr (in usereg rma))
2726	   (unit u-exec))))
2727
2728(dnci shcpm0 "shcpm0" (OPTIONAL_CP_INSN)
2729     "shcpm0 $crn,($rma+),$cdisp10a2"
2730     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x2) cdisp10a2)
2731     (sequence ()
2732	       (c-call "check_option_cp" pc)
2733	       (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
2734	       (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
2735	       (set rma (mod0 cdisp10a2)))
2736     ((mep (unit u-use-gpr (in usereg rma))
2737	   (unit u-exec))))
2738
2739(dnci lhcpm0 "lhcpm0" (OPTIONAL_CP_INSN)
2740     "lhcpm0 $crn,($rma+),$cdisp10a2"
2741     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x2) cdisp10a2)
2742     (sequence ()
2743	       (c-call "check_option_cp" pc)
2744	       (set crn (ext SI (mem HI (and rma (inv SI 1)))))
2745	       (set rma (mod0 cdisp10a2)))
2746     ((mep (unit u-use-gpr (in usereg rma))
2747	   (unit u-exec))))
2748
2749(dnci swcpm0 "swcpm0" (OPTIONAL_CP_INSN)
2750     "swcpm0 $crn,($rma+),$cdisp10a4"
2751     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x2) cdisp10a4)
2752     (sequence ()
2753	       (c-call "check_option_cp" pc)
2754	       (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2755	       (set (mem SI (and rma (inv SI 3))) crn)
2756	       (set rma (mod0 cdisp10a4)))
2757     ((mep (unit u-use-gpr (in usereg rma))
2758	   (unit u-exec))))
2759
2760(dnci lwcpm0 "lwcpm0" (OPTIONAL_CP_INSN)
2761     "lwcpm0 $crn,($rma+),$cdisp10a4"
2762     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x2) cdisp10a4)
2763     (sequence ()
2764	       (c-call "check_option_cp" pc)
2765	       (set crn (mem SI (and rma (inv SI 3))))
2766	       (set rma (mod0 cdisp10a4)))
2767     ((mep (unit u-use-gpr (in usereg rma))
2768	   (unit u-exec))))
2769
2770(dnci smcpm0 "smcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2771     "smcpm0 $crn64,($rma+),$cdisp10a8"
2772     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x2) cdisp10a8)
2773     (sequence ()
2774	       (c-call "check_option_cp" pc)
2775	       (c-call "check_option_cp64" pc)
2776	       (c-call VOID "check_write_to_text" rma)
2777	       (c-call "do_smcp" rma crn64 pc)
2778	       (set rma (mod0 cdisp10a8)))
2779     ((mep (unit u-use-gpr (in usereg rma))
2780	   (unit u-exec))))
2781
2782(dnci lmcpm0 "lmcpm0" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2783     "lmcpm0 $crn64,($rma+),$cdisp10a8"
2784     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x2) cdisp10a8)
2785     (sequence ()
2786	       (c-call "check_option_cp" pc)
2787	       (c-call "check_option_cp64" pc)
2788	       (set crn64 (c-call DI "do_lmcp" rma pc))
2789	       (set rma (mod0 cdisp10a8)))
2790     ((mep (unit u-use-gpr (in usereg rma))
2791	   (unit u-exec))))
2792
2793(dnci sbcpm1 "sbcpm1" (OPTIONAL_CP_INSN)
2794     "sbcpm1 $crn,($rma+),$cdisp10"
2795     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x0) (f-ext62 #x3) cdisp10)
2796     (sequence ()
2797	       (c-call "check_option_cp" pc)
2798	       (c-call VOID "check_write_to_text" rma)
2799	       (set (mem QI rma) (and crn #xff))
2800	       (set rma (mod1 cdisp10)))
2801     ((mep (unit u-use-gpr (in usereg rma))
2802	   (unit u-exec))))
2803
2804(dnci lbcpm1 "lbcpm1" (OPTIONAL_CP_INSN)
2805     "lbcpm1 $crn,($rma+),$cdisp10"
2806     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x4) (f-ext62 #x3) cdisp10)
2807     (sequence ()
2808	       (c-call "check_option_cp" pc)
2809	       (set crn (ext SI (mem QI rma)))
2810	       (set rma (mod1 cdisp10)))
2811     ((mep (unit u-use-gpr (in usereg rma))
2812	   (unit u-exec))))
2813
2814(dnci shcpm1 "shcpm1" (OPTIONAL_CP_INSN)
2815     "shcpm1 $crn,($rma+),$cdisp10a2"
2816     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x1) (f-ext62 #x3) cdisp10a2)
2817     (sequence ()
2818	       (c-call "check_option_cp" pc)
2819	       (c-call VOID "check_write_to_text" (and rma (inv SI 1)))
2820	       (set (mem HI (and rma (inv SI 1))) (and crn #xffff))
2821	       (set rma (mod1 cdisp10a2)))
2822     ((mep (unit u-use-gpr (in usereg rma))
2823	   (unit u-exec))))
2824
2825(dnci lhcpm1 "lhcpm1" (OPTIONAL_CP_INSN)
2826     "lhcpm1 $crn,($rma+),$cdisp10a2"
2827     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x5) (f-ext62 #x3) cdisp10a2)
2828     (sequence ()
2829	       (c-call "check_option_cp" pc)
2830	       (set crn (ext SI (mem HI (and rma (inv SI 1)))))
2831	       (set rma (mod1 cdisp10a2)))
2832     ((mep (unit u-use-gpr (in usereg rma))
2833	   (unit u-exec))))
2834
2835(dnci swcpm1 "swcpm1" (OPTIONAL_CP_INSN)
2836     "swcpm1 $crn,($rma+),$cdisp10a4"
2837     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x2) (f-ext62 #x3) cdisp10a4)
2838     (sequence ()
2839	       (c-call "check_option_cp" pc)
2840	       (c-call VOID "check_write_to_text" (and rma (inv SI 3)))
2841	       (set (mem SI (and rma (inv SI 3))) crn)
2842	       (set rma (mod1 cdisp10a4)))
2843     ((mep (unit u-use-gpr (in usereg rma))
2844	   (unit u-exec))))
2845
2846(dnci lwcpm1 "lwcpm1" (OPTIONAL_CP_INSN)
2847     "lwcpm1 $crn,($rma+),$cdisp10a4"
2848     (+ MAJ_15 crn rma (f-sub4 5) (f-ext4 #x6) (f-ext62 #x3) cdisp10a4)
2849     (sequence ()
2850	       (c-call "check_option_cp" pc)
2851	       (set crn (ext SI (mem SI (and rma (inv SI 3)))))
2852	       (set rma (mod1 cdisp10a4)))
2853     ((mep (unit u-use-gpr (in usereg rma))
2854	   (unit u-exec))))
2855
2856(dnci smcpm1 "smcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2857     "smcpm1 $crn64,($rma+),$cdisp10a8"
2858     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x3) (f-ext62 #x3) cdisp10a8)
2859     (sequence ()
2860	       (c-call "check_option_cp" pc)
2861	       (c-call "check_option_cp64" pc)
2862	       (c-call "do_smcp" rma crn64 pc)
2863	       (c-call VOID "check_write_to_text" rma)
2864	       (set rma (mod1 cdisp10a8)))
2865     ((mep (unit u-use-gpr (in usereg rma))
2866	   (unit u-exec))))
2867
2868(dnci lmcpm1 "lmcpm1" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN)
2869     "lmcpm1 $crn64,($rma+),$cdisp10a8"
2870     (+ MAJ_15 crn64 rma (f-sub4 5) (f-ext4 #x7) (f-ext62 #x3) cdisp10a8)
2871     (sequence ()
2872	       (c-call "check_option_cp" pc)
2873	       (c-call "check_option_cp64" pc)
2874	       (set crn64 (c-call DI "do_lmcp" rma pc))
2875	       (set rma (mod1 cdisp10a8)))
2876     ((mep (unit u-use-gpr (in usereg rma))
2877	   (unit u-exec))))
2878
2879(dnop cp_flag       "branch condition register"  (all-mep-isas) h-ccr   1)
2880
2881(dnci bcpeq "branch coprocessor equal" (OPTIONAL_CP_INSN RELAXABLE)
2882     "bcpeq $cccc,$pcrel17a2"
2883     (+ MAJ_13 (f-rn 8) cccc (f-sub4 4) pcrel17a2)
2884     (sequence ()
2885	       (c-call "check_option_cp" pc)
2886	       (if (eq (xor cccc cp_flag) 0)
2887	       (set-vliw-alignment-modified pc pcrel17a2)))
2888     ())
2889
2890(dnci bcpne "branch coprocessor not equal" (OPTIONAL_CP_INSN RELAXABLE)
2891     "bcpne $cccc,$pcrel17a2"
2892     (+ MAJ_13 (f-rn 8) cccc (f-sub4 5) pcrel17a2)
2893     (sequence ()
2894	       (c-call "check_option_cp" pc)
2895	       (if (ne (xor cccc cp_flag) 0)
2896	       (set-vliw-alignment-modified pc pcrel17a2)))
2897     ())
2898
2899(dnci bcpat "branch coprocessor and true" (OPTIONAL_CP_INSN RELAXABLE)
2900     "bcpat $cccc,$pcrel17a2"
2901     (+ MAJ_13 (f-rn 8) cccc (f-sub4 6) pcrel17a2)
2902     (sequence ()
2903	       (c-call "check_option_cp" pc)
2904	       (if (ne (and cccc cp_flag) 0)
2905	       (set-vliw-alignment-modified pc pcrel17a2)))
2906     ())
2907
2908(dnci bcpaf "branch coprocessor and false" (OPTIONAL_CP_INSN RELAXABLE)
2909     "bcpaf $cccc,$pcrel17a2"
2910     (+ MAJ_13 (f-rn 8) cccc (f-sub4 7) pcrel17a2)
2911     (sequence ()
2912	       (c-call "check_option_cp" pc)
2913	       (if (eq (and cccc cp_flag) 0)
2914	       (set-vliw-alignment-modified pc pcrel17a2)))
2915     ())
2916
2917(dnci synccp "synchronise with coprocessor" (OPTIONAL_CP_INSN)
2918     "synccp"
2919     (+ MAJ_7 (f-rn 0) (f-rm 2) (f-sub4 1))
2920     (sequence ()
2921	       (c-call "check_option_cp" pc)
2922	       (unimp "synccp"))
2923     ())
2924
2925(dnci jsrv "jump to vliw subroutine " (OPTIONAL_CP_INSN)
2926     "jsrv $rm"
2927     (+ MAJ_1 (f-rn 8) rm (f-sub4 15))
2928     (sequence ()
2929	       (cg-profile pc rm)
2930	       (c-call "check_option_cp" pc)
2931	       (core-vliw-switch
2932
2933		;; in core operating mode
2934		(sequence ()
2935			  (set lp (or (add pc 2) 1))
2936			  (set-vliw-aliignment-modified-by-option pc rm)
2937			  (set-psw.om 1)) ;; to VLIW operation mode
2938
2939		;; in VLIW32 operating mode
2940		(sequence ()
2941			  (set lp (or (add pc 4) 1))
2942			  (set pc (and rm (inv 1)))
2943			  (set-psw.om 0)) ;; to core operation mode
2944
2945		;; in VLIW64 operating mode
2946		(sequence ()
2947			  (set lp (or (add pc 8) 1))
2948			  (set pc (and rm (inv 1)))
2949			  (set-psw.om 0)))) ;; to core operation mode
2950     ((mep (unit u-use-gpr (in usereg rm))
2951	   (unit u-exec)
2952	   (unit u-branch))))
2953
2954(dnci bsrv "branch to vliw subroutine" (OPTIONAL_CP_INSN)
2955     "bsrv $pcrel24a2"
2956     (+ MAJ_13 (f-4 1) (f-sub4 11) pcrel24a2)
2957     (sequence ()
2958	       (cg-profile pc pcrel24a2)
2959	       (c-call "check_option_cp" pc)
2960	       (core-vliw-switch
2961
2962		;; in core operating mode
2963		(sequence ()
2964			  (set lp (or (add pc 4) 1))
2965			  (set-vliw-aliignment-modified-by-option pc pcrel24a2)
2966			  (set-psw.om 1)) ;; to VLIW operation mode
2967
2968		;; in VLIW32 operating mode
2969		(sequence ()
2970			  (set lp (or (add pc 4) 1))
2971			  (set pc (and pcrel24a2 (inv 1)))
2972			  (set-psw.om 0)) ;; to core operation mode
2973
2974		;; in VLIW64 operating mode
2975		(sequence ()
2976			  (set lp (or (add pc 8) 1))
2977			  (set pc (and pcrel24a2 (inv 1)))
2978			  (set-psw.om 0)))) ;; to core operation mode
2979     ((mep (unit u-exec)
2980	   (unit u-branch))))
2981
2982
2983; An instruction for test instrumentation.
2984; Using a reserved opcode.
2985
2986(dnci sim-syscall "simulator system call" ()
2987     "--syscall--"
2988     (+ MAJ_7 (f-4 1) callnum (f-8 0) (f-9 0) (f-10 0) (f-sub4 0))
2989     (c-call "do_syscall" pc callnum)
2990     ())
2991
2992(define-pmacro (dnri n major minor)
2993  (dnci (.sym ri- n) "reserved instruction" ()
2994	"--reserved--"
2995	(+ major rn rm (f-sub4 minor))
2996	(set pc (c-call USI "ri_exception" pc))
2997	((mep (unit u-exec)
2998	      (unit u-branch)))))
2999
3000(dnri 0  MAJ_0   6)
3001(dnri 1  MAJ_1  10)
3002(dnri 2  MAJ_1  11)
3003(dnri 3  MAJ_2   5)
3004(dnri 4  MAJ_2   8)
3005(dnri 5  MAJ_2   9)
3006(dnri 6  MAJ_2  10)
3007(dnri 7  MAJ_2  11)
3008(dnri 8  MAJ_3   4)
3009(dnri 9  MAJ_3   5)
3010(dnri 10 MAJ_3   6)
3011(dnri 11 MAJ_3   7)
3012(dnri 12 MAJ_3  12)
3013(dnri 13 MAJ_3  13)
3014(dnri 14 MAJ_3  14)
3015(dnri 15 MAJ_3  15)
3016(dnri 17 MAJ_7   7)
3017(dnri 20 MAJ_7  14)
3018(dnri 21 MAJ_7  15)
3019(dnri 22 MAJ_12  7)
3020(dnri 23 MAJ_14 13)
3021;(dnri 24 MAJ_15  3)
3022(dnri 26 MAJ_15  8)
3023; begin core-specific reserved insns
3024; end core-specific reserved insns
3025
3026
3027; Macro instructions.
3028
3029(dnmi nop "nop"
3030      ()
3031      "nop"
3032      (emit mov (rn 0) (rm 0)))
3033
3034; Emit the 16 bit form of these 32 bit insns when the displacement is zero.
3035;
3036(dncmi sb16-0 "store byte (explicit 16 bit displacement of zero)" (NO-DIS)
3037     "sb $rnc,$zero($rma)"
3038     (emit sb rnc rma))
3039
3040(dncmi sh16-0 "store half (explicit 16 bit displacement of zero)" (NO-DIS)
3041     "sh $rns,$zero($rma)"
3042     (emit sh rns rma))
3043
3044(dncmi sw16-0 "store word (explicit 16 bit displacement of zero)" (NO-DIS)
3045     "sw $rnl,$zero($rma)"
3046     (emit sw rnl rma))
3047
3048(dncmi lb16-0 "load byte (explicit 16 bit displacement of zero)" (NO-DIS)
3049     "lb $rnc,$zero($rma)"
3050     (emit lb rnc rma))
3051
3052(dncmi lh16-0 "load half (explicit 16 bit displacement of zero)" (NO-DIS)
3053     "lh $rns,$zero($rma)"
3054     (emit lh rns rma))
3055
3056(dncmi lw16-0 "load word (explicit 16 bit displacement of zero)" (NO-DIS)
3057     "lw $rnl,$zero($rma)"
3058     (emit lw rnl rma))
3059
3060(dncmi lbu16-0 "load unsigned byte (explicit 16 bit displacement of zero)" (NO-DIS)
3061     "lbu $rnuc,$zero($rma)"
3062     (emit lbu rnuc rma))
3063
3064(dncmi lhu16-0 "load unsigned half (explicit 16 bit displacement of zero)" (NO-DIS)
3065     "lhu $rnus,$zero($rma)"
3066     (emit lhu rnus rma))
3067
3068(dncmi swcp16-0 "swcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
3069     "swcp $crn,$zero($rma)"
3070     (emit swcp crn rma))
3071
3072(dncmi lwcp16-0 "lwcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN NO-DIS)
3073     "lwcp $crn,$zero($rma)"
3074     (emit lwcp crn rma))
3075
3076(dncmi smcp16-0 "smcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
3077     "smcp $crn64,$zero($rma)"
3078     (emit smcp crn64 rma))
3079
3080(dncmi lmcp16-0 "lmcp (explicit 16-bit displacement of zero)" (OPTIONAL_CP_INSN OPTIONAL_CP64_INSN NO-DIS)
3081     "lmcp $crn64,$zero($rma)"
3082     (emit lmcp crn64 rma))
3083