1.syntax unified
2
3VLD1.8 {d0}, 1f
41:
5VLD1.8 {D0}, R0
6VLD1.8 {Q1}, R0
7VLD1.8 {D0}, [PC]
8VLD1.8 {D0}, [PC, #0]
9VST1.8 {D0}, R0
10VST1.8 {Q1}, R0
11VST1.8 {D0}, [PC]
12VST1.8 {D0}, [PC, #0]
13VST1.8 {D0[]}, [R0]
14VST2.8 {D0[], D2[]}, [R0]
15VST3.16 {D0[], D1[], D2[]}, [R0]
16VST4.32 {D0[], D1[], D2[], D3[]}, [R0]
17VLD1.8 {Q0}, [R0, #8]
18VLD1.8 {Q0}, [R0, #8]!
19VLD1.8 {Q0}, [R0, R1]
20VLD1.8 {Q0}, [R0, R1]!
21.thumb
22VLD1.8 {d0}, 2f
232:
24VLD1.8 {D0}, R0
25VLD1.8 {Q1}, R0
26VLD1.8 {D0}, [PC]
27VLD1.8 {D0}, [PC, #0]
28VST1.8 {D0}, R0
29VST1.8 {Q1}, R0
30VST1.8 {D0}, [PC]
31VST1.8 {D0}, [PC, #0]
32
33VSHL.I8		d0, d0, #7
34VSHL.I8		d0, d0, #8
35VSHL.I16	d0, d0, #15
36VSHL.I16	d0, d0, #16
37VSHL.I32	d0, d0, #31
38VSHL.I32	d0, d0, #32
39VSHL.I64	d0, d0, #63
40VSHL.I64	d0, d0, #64
41
42VQSHL.S8	d0, d0, #7
43VQSHL.S8	d0, d0, #8
44VQSHL.S16	d0, d0, #15
45VQSHL.S16	d0, d0, #16
46VQSHL.S32	d0, d0, #31
47VQSHL.S32	d0, d0, #32
48VQSHL.S64	d0, d0, #63
49VQSHL.S64	d0, d0, #64
50
51VQSHLU.S8	d0, d0, #7
52VQSHLU.S8	d0, d0, #8
53VQSHLU.S16	d0, d0, #15
54VQSHLU.S16	d0, d0, #16
55VQSHLU.S32	d0, d0, #31
56VQSHLU.S32	d0, d0, #32
57VQSHLU.S64	d0, d0, #63
58VQSHLU.S64	d0, d0, #64
59