1// Copyright 2019 The Go Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style 3// license that can be found in the LICENSE file. 4 5#include "../../../../../runtime/textflag.h" 6 7TEXT asmtest(SB),DUPOK|NOSPLIT,$0 8start: 9 // Unprivileged ISA 10 11 // 2.4: Integer Computational Instructions 12 13 ADDI $2047, X5 // 9382f27f 14 ADDI $-2048, X5 // 93820280 15 ADDI $2048, X5 // 9382024093820240 16 ADDI $-2049, X5 // 938202c09382f2bf 17 ADDI $4094, X5 // 9382f27f9382f27f 18 ADDI $-4096, X5 // 9382028093820280 19 ADDI $4095, X5 // b71f00009b8fffffb382f201 20 ADDI $-4097, X5 // b7ffffff9b8fffffb382f201 21 ADDI $2047, X5, X6 // 1383f27f 22 ADDI $-2048, X5, X6 // 13830280 23 ADDI $2048, X5, X6 // 1383024013030340 24 ADDI $-2049, X5, X6 // 138302c01303f3bf 25 ADDI $4094, X5, X6 // 1383f27f1303f37f 26 ADDI $-4096, X5, X6 // 1383028013030380 27 ADDI $4095, X5, X6 // b71f00009b8fffff3383f201 28 ADDI $-4097, X5, X6 // b7ffffff9b8fffff3383f201 29 30 SLTI $55, X5, X7 // 93a37203 31 SLTIU $55, X5, X7 // 93b37203 32 33 ANDI $1, X5, X6 // 13f31200 34 ANDI $1, X5 // 93f21200 35 ANDI $2048, X5 // b71f00009b8f0f80b3f2f201 36 ORI $1, X5, X6 // 13e31200 37 ORI $1, X5 // 93e21200 38 ORI $2048, X5 // b71f00009b8f0f80b3e2f201 39 XORI $1, X5, X6 // 13c31200 40 XORI $1, X5 // 93c21200 41 XORI $2048, X5 // b71f00009b8f0f80b3c2f201 42 43 SLLI $1, X5, X6 // 13931200 44 SLLI $1, X5 // 93921200 45 SRLI $1, X5, X6 // 13d31200 46 SRLI $1, X5 // 93d21200 47 SRAI $1, X5, X6 // 13d31240 48 SRAI $1, X5 // 93d21240 49 50 ADD X6, X5, X7 // b3836200 51 ADD X5, X6 // 33035300 52 ADD $2047, X5, X6 // 1383f27f 53 ADD $-2048, X5, X6 // 13830280 54 ADD $2047, X5 // 9382f27f 55 ADD $-2048, X5 // 93820280 56 57 SLT X6, X5, X7 // b3a36200 58 SLT $55, X5, X7 // 93a37203 59 SLTU X6, X5, X7 // b3b36200 60 SLTU $55, X5, X7 // 93b37203 61 62 AND X6, X5, X7 // b3f36200 63 AND X5, X6 // 33735300 64 AND $1, X5, X6 // 13f31200 65 AND $1, X5 // 93f21200 66 OR X6, X5, X7 // b3e36200 67 OR X5, X6 // 33635300 68 OR $1, X5, X6 // 13e31200 69 OR $1, X5 // 93e21200 70 XOR X6, X5, X7 // b3c36200 71 XOR X5, X6 // 33435300 72 XOR $1, X5, X6 // 13c31200 73 XOR $1, X5 // 93c21200 74 75 AUIPC $0, X10 // 17050000 76 AUIPC $0, X11 // 97050000 77 AUIPC $1, X10 // 17150000 78 AUIPC $-524288, X15 // 97070080 79 AUIPC $524287, X10 // 17f5ff7f 80 81 LUI $0, X15 // b7070000 82 LUI $167, X15 // b7770a00 83 LUI $-524288, X15 // b7070080 84 LUI $524287, X15 // b7f7ff7f 85 86 SLL X6, X5, X7 // b3936200 87 SLL X5, X6 // 33135300 88 SLL $1, X5, X6 // 13931200 89 SLL $1, X5 // 93921200 90 SRL X6, X5, X7 // b3d36200 91 SRL X5, X6 // 33535300 92 SRL $1, X5, X6 // 13d31200 93 SRL $1, X5 // 93d21200 94 95 SUB X6, X5, X7 // b3836240 96 SUB X5, X6 // 33035340 97 98 SRA X6, X5, X7 // b3d36240 99 SRA X5, X6 // 33535340 100 SRA $1, X5, X6 // 13d31240 101 SRA $1, X5 // 93d21240 102 103 // 2.5: Control Transfer Instructions 104 JAL X5, 2(PC) // ef028000 105 JALR X6, (X5) // 67830200 106 JALR X6, 4(X5) // 67834200 107 BEQ X5, X6, 2(PC) // 63846200 108 BNE X5, X6, 2(PC) // 63946200 109 BLT X5, X6, 2(PC) // 63c46200 110 BLTU X5, X6, 2(PC) // 63e46200 111 BGE X5, X6, 2(PC) // 63d46200 112 BGEU X5, X6, 2(PC) // 63f46200 113 114 // 2.6: Load and Store Instructions 115 LW (X5), X6 // 03a30200 116 LW 4(X5), X6 // 03a34200 117 LWU (X5), X6 // 03e30200 118 LWU 4(X5), X6 // 03e34200 119 LH (X5), X6 // 03930200 120 LH 4(X5), X6 // 03934200 121 LHU (X5), X6 // 03d30200 122 LHU 4(X5), X6 // 03d34200 123 LB (X5), X6 // 03830200 124 LB 4(X5), X6 // 03834200 125 LBU (X5), X6 // 03c30200 126 LBU 4(X5), X6 // 03c34200 127 128 SW X5, (X6) // 23205300 129 SW X5, 4(X6) // 23225300 130 SH X5, (X6) // 23105300 131 SH X5, 4(X6) // 23125300 132 SB X5, (X6) // 23005300 133 SB X5, 4(X6) // 23025300 134 135 // 2.7: Memory Ordering Instructions 136 FENCE // 0f00f00f 137 138 // 5.2: Integer Computational Instructions (RV64I) 139 ADDIW $1, X5, X6 // 1b831200 140 SLLIW $1, X5, X6 // 1b931200 141 SRLIW $1, X5, X6 // 1bd31200 142 SRAIW $1, X5, X6 // 1bd31240 143 ADDW X5, X6, X7 // bb035300 144 SLLW X5, X6, X7 // bb135300 145 SRLW X5, X6, X7 // bb535300 146 SUBW X5, X6, X7 // bb035340 147 SRAW X5, X6, X7 // bb535340 148 149 // 5.3: Load and Store Instructions (RV64I) 150 LD (X5), X6 // 03b30200 151 LD 4(X5), X6 // 03b34200 152 SD X5, (X6) // 23305300 153 SD X5, 4(X6) // 23325300 154 155 // 7.1: Multiplication Operations 156 MUL X5, X6, X7 // b3035302 157 MULH X5, X6, X7 // b3135302 158 MULHU X5, X6, X7 // b3335302 159 MULHSU X5, X6, X7 // b3235302 160 MULW X5, X6, X7 // bb035302 161 DIV X5, X6, X7 // b3435302 162 DIVU X5, X6, X7 // b3535302 163 REM X5, X6, X7 // b3635302 164 REMU X5, X6, X7 // b3735302 165 DIVW X5, X6, X7 // bb435302 166 DIVUW X5, X6, X7 // bb535302 167 REMW X5, X6, X7 // bb635302 168 REMUW X5, X6, X7 // bb735302 169 170 // 8.2: Load-Reserved/Store-Conditional 171 LRW (X5), X6 // 2fa30214 172 LRD (X5), X6 // 2fb30214 173 SCW X5, (X6), X7 // af23531c 174 SCD X5, (X6), X7 // af33531c 175 176 // 8.3: Atomic Memory Operations 177 AMOSWAPW X5, (X6), X7 // af23530c 178 AMOSWAPD X5, (X6), X7 // af33530c 179 AMOADDW X5, (X6), X7 // af235304 180 AMOADDD X5, (X6), X7 // af335304 181 AMOANDW X5, (X6), X7 // af235364 182 AMOANDD X5, (X6), X7 // af335364 183 AMOORW X5, (X6), X7 // af235344 184 AMOORD X5, (X6), X7 // af335344 185 AMOXORW X5, (X6), X7 // af235324 186 AMOXORD X5, (X6), X7 // af335324 187 AMOMAXW X5, (X6), X7 // af2353a4 188 AMOMAXD X5, (X6), X7 // af3353a4 189 AMOMAXUW X5, (X6), X7 // af2353e4 190 AMOMAXUD X5, (X6), X7 // af3353e4 191 AMOMINW X5, (X6), X7 // af235384 192 AMOMIND X5, (X6), X7 // af335384 193 AMOMINUW X5, (X6), X7 // af2353c4 194 AMOMINUD X5, (X6), X7 // af3353c4 195 196 // 10.1: Base Counters and Timers 197 RDCYCLE X5 // f32200c0 198 RDTIME X5 // f32210c0 199 RDINSTRET X5 // f32220c0 200 201 // 11.5: Single-Precision Load and Store Instructions 202 FLW (X5), F0 // 07a00200 203 FLW 4(X5), F0 // 07a04200 204 FSW F0, (X5) // 27a00200 205 FSW F0, 4(X5) // 27a20200 206 207 // 11.6: Single-Precision Floating-Point Computational Instructions 208 FADDS F1, F0, F2 // 53011000 209 FSUBS F1, F0, F2 // 53011008 210 FMULS F1, F0, F2 // 53011010 211 FDIVS F1, F0, F2 // 53011018 212 FMINS F1, F0, F2 // 53011028 213 FMAXS F1, F0, F2 // 53111028 214 FSQRTS F0, F1 // d3000058 215 216 // 11.7: Single-Precision Floating-Point Conversion and Move Instructions 217 FCVTWS F0, X5 // d31200c0 218 FCVTLS F0, X5 // d31220c0 219 FCVTSW X5, F0 // 538002d0 220 FCVTSL X5, F0 // 538022d0 221 FCVTWUS F0, X5 // d31210c0 222 FCVTLUS F0, X5 // d31230c0 223 FCVTSWU X5, F0 // 538012d0 224 FCVTSLU X5, F0 // 538032d0 225 FSGNJS F1, F0, F2 // 53011020 226 FSGNJNS F1, F0, F2 // 53111020 227 FSGNJXS F1, F0, F2 // 53211020 228 FMVXS F0, X5 // d30200e0 229 FMVSX X5, F0 // 538002f0 230 FMVXW F0, X5 // d30200e0 231 FMVWX X5, F0 // 538002f0 232 FMADDS F1, F2, F3, F4 // 43822018 233 FMSUBS F1, F2, F3, F4 // 47822018 234 FNMSUBS F1, F2, F3, F4 // 4b822018 235 FNMADDS F1, F2, F3, F4 // 4f822018 236 237 // 11.8: Single-Precision Floating-Point Compare Instructions 238 FEQS F0, F1, X7 // d3a300a0 239 FLTS F0, F1, X7 // d39300a0 240 FLES F0, F1, X7 // d38300a0 241 242 // 11.9: Single-Precision Floating-Point Classify Instruction 243 FCLASSS F0, X5 // d31200e0 244 245 // 12.3: Double-Precision Load and Store Instructions 246 FLD (X5), F0 // 07b00200 247 FLD 4(X5), F0 // 07b04200 248 FSD F0, (X5) // 27b00200 249 FSD F0, 4(X5) // 27b20200 250 251 // 12.4: Double-Precision Floating-Point Computational Instructions 252 FADDD F1, F0, F2 // 53011002 253 FSUBD F1, F0, F2 // 5301100a 254 FMULD F1, F0, F2 // 53011012 255 FDIVD F1, F0, F2 // 5301101a 256 FMIND F1, F0, F2 // 5301102a 257 FMAXD F1, F0, F2 // 5311102a 258 FSQRTD F0, F1 // d300005a 259 260 // 12.5: Double-Precision Floating-Point Conversion and Move Instructions 261 FCVTWD F0, X5 // d31200c2 262 FCVTLD F0, X5 // d31220c2 263 FCVTDW X5, F0 // 538002d2 264 FCVTDL X5, F0 // 538022d2 265 FCVTWUD F0, X5 // d31210c2 266 FCVTLUD F0, X5 // d31230c2 267 FCVTDWU X5, F0 // 538012d2 268 FCVTDLU X5, F0 // 538032d2 269 FCVTSD F0, F1 // d3001040 270 FCVTDS F0, F1 // d3000042 271 FSGNJD F1, F0, F2 // 53011022 272 FSGNJND F1, F0, F2 // 53111022 273 FSGNJXD F1, F0, F2 // 53211022 274 FMVXD F0, X5 // d30200e2 275 FMVDX X5, F0 // 538002f2 276 FMADDD F1, F2, F3, F4 // 4382201a 277 FMSUBD F1, F2, F3, F4 // 4782201a 278 FNMSUBD F1, F2, F3, F4 // 4b82201a 279 FNMADDD F1, F2, F3, F4 // 4f82201a 280 281 // 12.6: Double-Precision Floating-Point Classify Instruction 282 FCLASSD F0, X5 // d31200e2 283 284 // Privileged ISA 285 286 // 3.2.1: Environment Call and Breakpoint 287 ECALL // 73000000 288 SCALL // 73000000 289 EBREAK // 73001000 290 SBREAK // 73001000 291 292 // Arbitrary bytes (entered in little-endian mode) 293 WORD $0x12345678 // WORD $305419896 // 78563412 294 WORD $0x9abcdef0 // WORD $2596069104 // f0debc9a 295 296 // MOV pseudo-instructions 297 MOV X5, X6 // 13830200 298 MOV $2047, X5 // 9302f07f 299 MOV $-2048, X5 // 93020080 300 MOV $2048, X5 // b71200009b820280 301 MOV $-2049, X5 // b7f2ffff9b82f27f 302 MOV $4096, X5 // b7120000 303 MOV $2147479552, X5 // b7f2ff7f 304 MOV $2147483647, X5 // b70200809b82f2ff 305 MOV $-2147483647, X5 // b70200809b821200 306 307 // Converted to load of symbol (AUIPC + LD) 308 MOV $4294967296, X5 // 9702000083b20200 309 310 MOV (X5), X6 // 03b30200 311 MOV 4(X5), X6 // 03b34200 312 MOVB (X5), X6 // 03830200 313 MOVB 4(X5), X6 // 03834200 314 MOVH (X5), X6 // 03930200 315 MOVH 4(X5), X6 // 03934200 316 MOVW (X5), X6 // 03a30200 317 MOVW 4(X5), X6 // 03a34200 318 MOV X5, (X6) // 23305300 319 MOV X5, 4(X6) // 23325300 320 MOVB X5, (X6) // 23005300 321 MOVB X5, 4(X6) // 23025300 322 MOVH X5, (X6) // 23105300 323 MOVH X5, 4(X6) // 23125300 324 MOVW X5, (X6) // 23205300 325 MOVW X5, 4(X6) // 23225300 326 327 MOVB X5, X6 // 1393820313538343 328 MOVH X5, X6 // 1393020313530343 329 MOVW X5, X6 // 1b830200 330 MOVBU X5, X6 // 13f3f20f 331 MOVHU X5, X6 // 1393020313530303 332 MOVWU X5, X6 // 1393020213530302 333 334 MOVF 4(X5), F0 // 07a04200 335 MOVF F0, 4(X5) // 27a20200 336 MOVF F0, F1 // d3000020 337 338 MOVD 4(X5), F0 // 07b04200 339 MOVD F0, 4(X5) // 27b20200 340 MOVD F0, F1 // d3000022 341 342 // NOT pseudo-instruction 343 NOT X5 // 93c2f2ff 344 NOT X5, X6 // 13c3f2ff 345 346 // NEG/NEGW pseudo-instructions 347 NEG X5 // b3025040 348 NEG X5, X6 // 33035040 349 NEGW X5 // bb025040 350 NEGW X5, X6 // 3b035040 351 352 // This jumps to the second instruction in the function (the 353 // first instruction is an invisible stack pointer adjustment). 354 JMP start // JMP 2 355 356 JMP 2(PC) // 6f008000 357 JMP (X5) // 67800200 358 JMP 4(X5) // 67804200 359 360 // CALL and JMP to symbol are encoded as JAL (using LR or ZERO 361 // respectively), with a R_RISCV_CALL relocation. The linker resolves 362 // the real address and updates the immediate, using a trampoline in 363 // the case where the address is not directly reachable. 364 CALL asmtest(SB) // ef000000 365 JMP asmtest(SB) // 6f000000 366 367 // Branch pseudo-instructions 368 BEQZ X5, 2(PC) // 63840200 369 BGEZ X5, 2(PC) // 63d40200 370 BGT X5, X6, 2(PC) // 63445300 371 BGTU X5, X6, 2(PC) // 63645300 372 BGTZ X5, 2(PC) // 63445000 373 BLE X5, X6, 2(PC) // 63545300 374 BLEU X5, X6, 2(PC) // 63745300 375 BLEZ X5, 2(PC) // 63545000 376 BLTZ X5, 2(PC) // 63c40200 377 BNEZ X5, 2(PC) // 63940200 378 379 // Set pseudo-instructions 380 SEQZ X15, X15 // 93b71700 381 SNEZ X15, X15 // b337f000 382 383 // F extension 384 FABSS F0, F1 // d3200020 385 FNEGS F0, F1 // d3100020 386 FNES F0, F1, X7 // d3a300a093c31300 387 388 // D extension 389 FABSD F0, F1 // d3200022 390 FNEGD F0, F1 // d3100022 391 FNED F0, F1, X5 // d3a200a293c21200 392 FLTD F0, F1, X5 // d39200a2 393 FLED F0, F1, X5 // d38200a2 394 FEQD F0, F1, X5 // d3a200a2 395