1// Copyright 2016 The Go Authors. All rights reserved. 2// Use of this source code is governed by a BSD-style 3// license that can be found in the LICENSE file. 4 5(Add(Ptr|32|16|8) ...) => (ADD ...) 6(Add(32|64)F ...) => (ADD(F|D) ...) 7 8(Select0 (Add32carry <t> x y)) => (ADD <t.FieldType(0)> x y) 9(Select1 (Add32carry <t> x y)) => (SGTU <typ.Bool> x (ADD <t.FieldType(0)> x y)) 10(Add32withcarry <t> x y c) => (ADD c (ADD <t> x y)) 11 12(Sub(Ptr|32|16|8) ...) => (SUB ...) 13(Sub(32|64)F ...) => (SUB(F|D) ...) 14 15(Select0 (Sub32carry <t> x y)) => (SUB <t.FieldType(0)> x y) 16(Select1 (Sub32carry <t> x y)) => (SGTU <typ.Bool> (SUB <t.FieldType(0)> x y) x) 17(Sub32withcarry <t> x y c) => (SUB (SUB <t> x y) c) 18 19(Mul(32|16|8) ...) => (MUL ...) 20(Mul(32|64)F ...) => (MUL(F|D) ...) 21 22(Hmul(32|32u) x y) => (Select0 (MUL(T|TU) x y)) 23(Mul32uhilo ...) => (MULTU ...) 24 25(Div32 x y) => (Select1 (DIV x y)) 26(Div32u x y) => (Select1 (DIVU x y)) 27(Div16 x y) => (Select1 (DIV (SignExt16to32 x) (SignExt16to32 y))) 28(Div16u x y) => (Select1 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y))) 29(Div8 x y) => (Select1 (DIV (SignExt8to32 x) (SignExt8to32 y))) 30(Div8u x y) => (Select1 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y))) 31(Div(32|64)F ...) => (DIV(F|D) ...) 32 33(Mod32 x y) => (Select0 (DIV x y)) 34(Mod32u x y) => (Select0 (DIVU x y)) 35(Mod16 x y) => (Select0 (DIV (SignExt16to32 x) (SignExt16to32 y))) 36(Mod16u x y) => (Select0 (DIVU (ZeroExt16to32 x) (ZeroExt16to32 y))) 37(Mod8 x y) => (Select0 (DIV (SignExt8to32 x) (SignExt8to32 y))) 38(Mod8u x y) => (Select0 (DIVU (ZeroExt8to32 x) (ZeroExt8to32 y))) 39 40// (x + y) / 2 with x>=y becomes (x - y) / 2 + y 41(Avg32u <t> x y) => (ADD (SRLconst <t> (SUB <t> x y) [1]) y) 42 43(And(32|16|8) ...) => (AND ...) 44(Or(32|16|8) ...) => (OR ...) 45(Xor(32|16|8) ...) => (XOR ...) 46 47// constant shifts 48// generic opt rewrites all constant shifts to shift by Const64 49(Lsh32x64 x (Const64 [c])) && uint32(c) < 32 => (SLLconst x [int32(c)]) 50(Rsh32x64 x (Const64 [c])) && uint32(c) < 32 => (SRAconst x [int32(c)]) 51(Rsh32Ux64 x (Const64 [c])) && uint32(c) < 32 => (SRLconst x [int32(c)]) 52(Lsh16x64 x (Const64 [c])) && uint32(c) < 16 => (SLLconst x [int32(c)]) 53(Rsh16x64 x (Const64 [c])) && uint32(c) < 16 => (SRAconst (SLLconst <typ.UInt32> x [16]) [int32(c+16)]) 54(Rsh16Ux64 x (Const64 [c])) && uint32(c) < 16 => (SRLconst (SLLconst <typ.UInt32> x [16]) [int32(c+16)]) 55(Lsh8x64 x (Const64 [c])) && uint32(c) < 8 => (SLLconst x [int32(c)]) 56(Rsh8x64 x (Const64 [c])) && uint32(c) < 8 => (SRAconst (SLLconst <typ.UInt32> x [24]) [int32(c+24)]) 57(Rsh8Ux64 x (Const64 [c])) && uint32(c) < 8 => (SRLconst (SLLconst <typ.UInt32> x [24]) [int32(c+24)]) 58 59// large constant shifts 60(Lsh32x64 _ (Const64 [c])) && uint32(c) >= 32 => (MOVWconst [0]) 61(Rsh32Ux64 _ (Const64 [c])) && uint32(c) >= 32 => (MOVWconst [0]) 62(Lsh16x64 _ (Const64 [c])) && uint32(c) >= 16 => (MOVWconst [0]) 63(Rsh16Ux64 _ (Const64 [c])) && uint32(c) >= 16 => (MOVWconst [0]) 64(Lsh8x64 _ (Const64 [c])) && uint32(c) >= 8 => (MOVWconst [0]) 65(Rsh8Ux64 _ (Const64 [c])) && uint32(c) >= 8 => (MOVWconst [0]) 66 67// large constant signed right shift, we leave the sign bit 68(Rsh32x64 x (Const64 [c])) && uint32(c) >= 32 => (SRAconst x [31]) 69(Rsh16x64 x (Const64 [c])) && uint32(c) >= 16 => (SRAconst (SLLconst <typ.UInt32> x [16]) [31]) 70(Rsh8x64 x (Const64 [c])) && uint32(c) >= 8 => (SRAconst (SLLconst <typ.UInt32> x [24]) [31]) 71 72// shifts 73// hardware instruction uses only the low 5 bits of the shift 74// we compare to 32 to ensure Go semantics for large shifts 75(Lsh32x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y)) 76(Lsh32x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y))) 77(Lsh32x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y))) 78 79(Lsh16x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y)) 80(Lsh16x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y))) 81(Lsh16x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y))) 82 83(Lsh8x32 <t> x y) => (CMOVZ (SLL <t> x y) (MOVWconst [0]) (SGTUconst [32] y)) 84(Lsh8x16 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y))) 85(Lsh8x8 <t> x y) => (CMOVZ (SLL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y))) 86 87(Rsh32Ux32 <t> x y) => (CMOVZ (SRL <t> x y) (MOVWconst [0]) (SGTUconst [32] y)) 88(Rsh32Ux16 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y))) 89(Rsh32Ux8 <t> x y) => (CMOVZ (SRL <t> x (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y))) 90 91(Rsh16Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) y) (MOVWconst [0]) (SGTUconst [32] y)) 92(Rsh16Ux16 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y))) 93(Rsh16Ux8 <t> x y) => (CMOVZ (SRL <t> (ZeroExt16to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y))) 94 95(Rsh8Ux32 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) y) (MOVWconst [0]) (SGTUconst [32] y)) 96(Rsh8Ux16 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt16to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt16to32 y))) 97(Rsh8Ux8 <t> x y) => (CMOVZ (SRL <t> (ZeroExt8to32 x) (ZeroExt8to32 y) ) (MOVWconst [0]) (SGTUconst [32] (ZeroExt8to32 y))) 98 99(Rsh32x32 x y) => (SRA x ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y))) 100(Rsh32x16 x y) => (SRA x ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y)))) 101(Rsh32x8 x y) => (SRA x ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y)))) 102 103(Rsh16x32 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y))) 104(Rsh16x16 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y)))) 105(Rsh16x8 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y)))) 106 107(Rsh8x32 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> y (MOVWconst [31]) (SGTUconst [32] y))) 108(Rsh8x16 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt16to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt16to32 y)))) 109(Rsh8x8 x y) => (SRA (SignExt16to32 x) ( CMOVZ <typ.UInt32> (ZeroExt8to32 y) (MOVWconst [31]) (SGTUconst [32] (ZeroExt8to32 y)))) 110 111// rotates 112(RotateLeft8 <t> x (MOVWconst [c])) => (Or8 (Lsh8x32 <t> x (MOVWconst [c&7])) (Rsh8Ux32 <t> x (MOVWconst [-c&7]))) 113(RotateLeft16 <t> x (MOVWconst [c])) => (Or16 (Lsh16x32 <t> x (MOVWconst [c&15])) (Rsh16Ux32 <t> x (MOVWconst [-c&15]))) 114(RotateLeft32 <t> x (MOVWconst [c])) => (Or32 (Lsh32x32 <t> x (MOVWconst [c&31])) (Rsh32Ux32 <t> x (MOVWconst [-c&31]))) 115(RotateLeft64 <t> x (MOVWconst [c])) => (Or64 (Lsh64x32 <t> x (MOVWconst [c&63])) (Rsh64Ux32 <t> x (MOVWconst [-c&63]))) 116 117// unary ops 118(Neg(32|16|8) ...) => (NEG ...) 119(Neg(32|64)F ...) => (NEG(F|D) ...) 120 121(Com(32|16|8) x) => (NORconst [0] x) 122 123(Sqrt ...) => (SQRTD ...) 124(Sqrt32 ...) => (SQRTF ...) 125 126// TODO: optimize this case? 127(Ctz32NonZero ...) => (Ctz32 ...) 128 129// count trailing zero 130// 32 - CLZ(x&-x - 1) 131(Ctz32 <t> x) => (SUB (MOVWconst [32]) (CLZ <t> (SUBconst <t> [1] (AND <t> x (NEG <t> x))))) 132 133// bit length 134(BitLen32 <t> x) => (SUB (MOVWconst [32]) (CLZ <t> x)) 135 136// boolean ops -- booleans are represented with 0=false, 1=true 137(AndB ...) => (AND ...) 138(OrB ...) => (OR ...) 139(EqB x y) => (XORconst [1] (XOR <typ.Bool> x y)) 140(NeqB ...) => (XOR ...) 141(Not x) => (XORconst [1] x) 142 143// constants 144(Const(32|16|8) [val]) => (MOVWconst [int32(val)]) 145(Const(32|64)F ...) => (MOV(F|D)const ...) 146(ConstNil) => (MOVWconst [0]) 147(ConstBool [t]) => (MOVWconst [b2i32(t)]) 148 149// truncations 150// Because we ignore high parts of registers, truncates are just copies. 151(Trunc16to8 ...) => (Copy ...) 152(Trunc32to8 ...) => (Copy ...) 153(Trunc32to16 ...) => (Copy ...) 154 155// Zero-/Sign-extensions 156(ZeroExt8to16 ...) => (MOVBUreg ...) 157(ZeroExt8to32 ...) => (MOVBUreg ...) 158(ZeroExt16to32 ...) => (MOVHUreg ...) 159 160(SignExt8to16 ...) => (MOVBreg ...) 161(SignExt8to32 ...) => (MOVBreg ...) 162(SignExt16to32 ...) => (MOVHreg ...) 163 164(Signmask x) => (SRAconst x [31]) 165(Zeromask x) => (NEG (SGTU x (MOVWconst [0]))) 166(Slicemask <t> x) => (SRAconst (NEG <t> x) [31]) 167 168// float-int conversion 169(Cvt32to(32|64)F ...) => (MOVW(F|D) ...) 170(Cvt(32|64)Fto32 ...) => (TRUNC(F|D)W ...) 171(Cvt32Fto64F ...) => (MOVFD ...) 172(Cvt64Fto32F ...) => (MOVDF ...) 173 174(CvtBoolToUint8 ...) => (Copy ...) 175 176(Round(32|64)F ...) => (Copy ...) 177 178// comparisons 179(Eq8 x y) => (SGTUconst [1] (XOR (ZeroExt8to32 x) (ZeroExt8to32 y))) 180(Eq16 x y) => (SGTUconst [1] (XOR (ZeroExt16to32 x) (ZeroExt16to32 y))) 181(Eq32 x y) => (SGTUconst [1] (XOR x y)) 182(EqPtr x y) => (SGTUconst [1] (XOR x y)) 183(Eq(32|64)F x y) => (FPFlagTrue (CMPEQ(F|D) x y)) 184 185(Neq8 x y) => (SGTU (XOR (ZeroExt8to32 x) (ZeroExt8to32 y)) (MOVWconst [0])) 186(Neq16 x y) => (SGTU (XOR (ZeroExt16to32 x) (ZeroExt16to32 y)) (MOVWconst [0])) 187(Neq32 x y) => (SGTU (XOR x y) (MOVWconst [0])) 188(NeqPtr x y) => (SGTU (XOR x y) (MOVWconst [0])) 189(Neq(32|64)F x y) => (FPFlagFalse (CMPEQ(F|D) x y)) 190 191(Less8 x y) => (SGT (SignExt8to32 y) (SignExt8to32 x)) 192(Less16 x y) => (SGT (SignExt16to32 y) (SignExt16to32 x)) 193(Less32 x y) => (SGT y x) 194(Less(32|64)F x y) => (FPFlagTrue (CMPGT(F|D) y x)) // reverse operands to work around NaN 195 196(Less8U x y) => (SGTU (ZeroExt8to32 y) (ZeroExt8to32 x)) 197(Less16U x y) => (SGTU (ZeroExt16to32 y) (ZeroExt16to32 x)) 198(Less32U x y) => (SGTU y x) 199 200(Leq8 x y) => (XORconst [1] (SGT (SignExt8to32 x) (SignExt8to32 y))) 201(Leq16 x y) => (XORconst [1] (SGT (SignExt16to32 x) (SignExt16to32 y))) 202(Leq32 x y) => (XORconst [1] (SGT x y)) 203(Leq(32|64)F x y) => (FPFlagTrue (CMPGE(F|D) y x)) // reverse operands to work around NaN 204 205(Leq8U x y) => (XORconst [1] (SGTU (ZeroExt8to32 x) (ZeroExt8to32 y))) 206(Leq16U x y) => (XORconst [1] (SGTU (ZeroExt16to32 x) (ZeroExt16to32 y))) 207(Leq32U x y) => (XORconst [1] (SGTU x y)) 208 209(OffPtr [off] ptr:(SP)) => (MOVWaddr [int32(off)] ptr) 210(OffPtr [off] ptr) => (ADDconst [int32(off)] ptr) 211 212(Addr {sym} base) => (MOVWaddr {sym} base) 213(LocalAddr {sym} base _) => (MOVWaddr {sym} base) 214 215// loads 216(Load <t> ptr mem) && t.IsBoolean() => (MOVBUload ptr mem) 217(Load <t> ptr mem) && (is8BitInt(t) && isSigned(t)) => (MOVBload ptr mem) 218(Load <t> ptr mem) && (is8BitInt(t) && !isSigned(t)) => (MOVBUload ptr mem) 219(Load <t> ptr mem) && (is16BitInt(t) && isSigned(t)) => (MOVHload ptr mem) 220(Load <t> ptr mem) && (is16BitInt(t) && !isSigned(t)) => (MOVHUload ptr mem) 221(Load <t> ptr mem) && (is32BitInt(t) || isPtr(t)) => (MOVWload ptr mem) 222(Load <t> ptr mem) && is32BitFloat(t) => (MOVFload ptr mem) 223(Load <t> ptr mem) && is64BitFloat(t) => (MOVDload ptr mem) 224 225// stores 226(Store {t} ptr val mem) && t.Size() == 1 => (MOVBstore ptr val mem) 227(Store {t} ptr val mem) && t.Size() == 2 => (MOVHstore ptr val mem) 228(Store {t} ptr val mem) && t.Size() == 4 && !is32BitFloat(val.Type) => (MOVWstore ptr val mem) 229(Store {t} ptr val mem) && t.Size() == 4 && is32BitFloat(val.Type) => (MOVFstore ptr val mem) 230(Store {t} ptr val mem) && t.Size() == 8 && is64BitFloat(val.Type) => (MOVDstore ptr val mem) 231 232// zero instructions 233(Zero [0] _ mem) => mem 234(Zero [1] ptr mem) => (MOVBstore ptr (MOVWconst [0]) mem) 235(Zero [2] {t} ptr mem) && t.Alignment()%2 == 0 => 236 (MOVHstore ptr (MOVWconst [0]) mem) 237(Zero [2] ptr mem) => 238 (MOVBstore [1] ptr (MOVWconst [0]) 239 (MOVBstore [0] ptr (MOVWconst [0]) mem)) 240(Zero [4] {t} ptr mem) && t.Alignment()%4 == 0 => 241 (MOVWstore ptr (MOVWconst [0]) mem) 242(Zero [4] {t} ptr mem) && t.Alignment()%2 == 0 => 243 (MOVHstore [2] ptr (MOVWconst [0]) 244 (MOVHstore [0] ptr (MOVWconst [0]) mem)) 245(Zero [4] ptr mem) => 246 (MOVBstore [3] ptr (MOVWconst [0]) 247 (MOVBstore [2] ptr (MOVWconst [0]) 248 (MOVBstore [1] ptr (MOVWconst [0]) 249 (MOVBstore [0] ptr (MOVWconst [0]) mem)))) 250(Zero [3] ptr mem) => 251 (MOVBstore [2] ptr (MOVWconst [0]) 252 (MOVBstore [1] ptr (MOVWconst [0]) 253 (MOVBstore [0] ptr (MOVWconst [0]) mem))) 254(Zero [6] {t} ptr mem) && t.Alignment()%2 == 0 => 255 (MOVHstore [4] ptr (MOVWconst [0]) 256 (MOVHstore [2] ptr (MOVWconst [0]) 257 (MOVHstore [0] ptr (MOVWconst [0]) mem))) 258(Zero [8] {t} ptr mem) && t.Alignment()%4 == 0 => 259 (MOVWstore [4] ptr (MOVWconst [0]) 260 (MOVWstore [0] ptr (MOVWconst [0]) mem)) 261(Zero [12] {t} ptr mem) && t.Alignment()%4 == 0 => 262 (MOVWstore [8] ptr (MOVWconst [0]) 263 (MOVWstore [4] ptr (MOVWconst [0]) 264 (MOVWstore [0] ptr (MOVWconst [0]) mem))) 265(Zero [16] {t} ptr mem) && t.Alignment()%4 == 0 => 266 (MOVWstore [12] ptr (MOVWconst [0]) 267 (MOVWstore [8] ptr (MOVWconst [0]) 268 (MOVWstore [4] ptr (MOVWconst [0]) 269 (MOVWstore [0] ptr (MOVWconst [0]) mem)))) 270 271// large or unaligned zeroing uses a loop 272(Zero [s] {t} ptr mem) 273 && (s > 16 || t.Alignment()%4 != 0) => 274 (LoweredZero [int32(t.Alignment())] 275 ptr 276 (ADDconst <ptr.Type> ptr [int32(s-moveSize(t.Alignment(), config))]) 277 mem) 278 279// moves 280(Move [0] _ _ mem) => mem 281(Move [1] dst src mem) => (MOVBstore dst (MOVBUload src mem) mem) 282(Move [2] {t} dst src mem) && t.Alignment()%2 == 0 => 283 (MOVHstore dst (MOVHUload src mem) mem) 284(Move [2] dst src mem) => 285 (MOVBstore [1] dst (MOVBUload [1] src mem) 286 (MOVBstore dst (MOVBUload src mem) mem)) 287(Move [4] {t} dst src mem) && t.Alignment()%4 == 0 => 288 (MOVWstore dst (MOVWload src mem) mem) 289(Move [4] {t} dst src mem) && t.Alignment()%2 == 0 => 290 (MOVHstore [2] dst (MOVHUload [2] src mem) 291 (MOVHstore dst (MOVHUload src mem) mem)) 292(Move [4] dst src mem) => 293 (MOVBstore [3] dst (MOVBUload [3] src mem) 294 (MOVBstore [2] dst (MOVBUload [2] src mem) 295 (MOVBstore [1] dst (MOVBUload [1] src mem) 296 (MOVBstore dst (MOVBUload src mem) mem)))) 297(Move [3] dst src mem) => 298 (MOVBstore [2] dst (MOVBUload [2] src mem) 299 (MOVBstore [1] dst (MOVBUload [1] src mem) 300 (MOVBstore dst (MOVBUload src mem) mem))) 301(Move [8] {t} dst src mem) && t.Alignment()%4 == 0 => 302 (MOVWstore [4] dst (MOVWload [4] src mem) 303 (MOVWstore dst (MOVWload src mem) mem)) 304(Move [8] {t} dst src mem) && t.Alignment()%2 == 0 => 305 (MOVHstore [6] dst (MOVHload [6] src mem) 306 (MOVHstore [4] dst (MOVHload [4] src mem) 307 (MOVHstore [2] dst (MOVHload [2] src mem) 308 (MOVHstore dst (MOVHload src mem) mem)))) 309(Move [6] {t} dst src mem) && t.Alignment()%2 == 0 => 310 (MOVHstore [4] dst (MOVHload [4] src mem) 311 (MOVHstore [2] dst (MOVHload [2] src mem) 312 (MOVHstore dst (MOVHload src mem) mem))) 313(Move [12] {t} dst src mem) && t.Alignment()%4 == 0 => 314 (MOVWstore [8] dst (MOVWload [8] src mem) 315 (MOVWstore [4] dst (MOVWload [4] src mem) 316 (MOVWstore dst (MOVWload src mem) mem))) 317(Move [16] {t} dst src mem) && t.Alignment()%4 == 0 => 318 (MOVWstore [12] dst (MOVWload [12] src mem) 319 (MOVWstore [8] dst (MOVWload [8] src mem) 320 (MOVWstore [4] dst (MOVWload [4] src mem) 321 (MOVWstore dst (MOVWload src mem) mem)))) 322 323 324// large or unaligned move uses a loop 325(Move [s] {t} dst src mem) 326 && (s > 16 && logLargeCopy(v, s) || t.Alignment()%4 != 0) => 327 (LoweredMove [int32(t.Alignment())] 328 dst 329 src 330 (ADDconst <src.Type> src [int32(s-moveSize(t.Alignment(), config))]) 331 mem) 332 333// calls 334(StaticCall ...) => (CALLstatic ...) 335(ClosureCall ...) => (CALLclosure ...) 336(InterCall ...) => (CALLinter ...) 337(TailCall ...) => (CALLtail ...) 338 339// atomic intrinsics 340(AtomicLoad(8|32) ...) => (LoweredAtomicLoad(8|32) ...) 341(AtomicLoadPtr ...) => (LoweredAtomicLoad32 ...) 342 343(AtomicStore(8|32) ...) => (LoweredAtomicStore(8|32) ...) 344(AtomicStorePtrNoWB ...) => (LoweredAtomicStore32 ...) 345 346(AtomicExchange32 ...) => (LoweredAtomicExchange ...) 347(AtomicAdd32 ...) => (LoweredAtomicAdd ...) 348 349(AtomicCompareAndSwap32 ...) => (LoweredAtomicCas ...) 350 351// AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << ((ptr & 3) * 8)) 352(AtomicOr8 ptr val mem) && !config.BigEndian => 353 (LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr) 354 (SLL <typ.UInt32> (ZeroExt8to32 val) 355 (SLLconst <typ.UInt32> [3] 356 (ANDconst <typ.UInt32> [3] ptr))) mem) 357 358// AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << ((ptr & 3) * 8)) | ^(uint32(0xFF) << ((ptr & 3) * 8)))) 359(AtomicAnd8 ptr val mem) && !config.BigEndian => 360 (LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr) 361 (OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val) 362 (SLLconst <typ.UInt32> [3] 363 (ANDconst <typ.UInt32> [3] ptr))) 364 (NORconst [0] <typ.UInt32> (SLL <typ.UInt32> 365 (MOVWconst [0xff]) (SLLconst <typ.UInt32> [3] 366 (ANDconst <typ.UInt32> [3] ptr))))) mem) 367 368// AtomicOr8(ptr,val) => LoweredAtomicOr(ptr&^3,uint32(val) << (((ptr^3) & 3) * 8)) 369(AtomicOr8 ptr val mem) && config.BigEndian => 370 (LoweredAtomicOr (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr) 371 (SLL <typ.UInt32> (ZeroExt8to32 val) 372 (SLLconst <typ.UInt32> [3] 373 (ANDconst <typ.UInt32> [3] 374 (XORconst <typ.UInt32> [3] ptr)))) mem) 375 376// AtomicAnd8(ptr,val) => LoweredAtomicAnd(ptr&^3,(uint32(val) << (((ptr^3) & 3) * 8)) | ^(uint32(0xFF) << (((ptr^3) & 3) * 8)))) 377(AtomicAnd8 ptr val mem) && config.BigEndian => 378 (LoweredAtomicAnd (AND <typ.UInt32Ptr> (MOVWconst [^3]) ptr) 379 (OR <typ.UInt32> (SLL <typ.UInt32> (ZeroExt8to32 val) 380 (SLLconst <typ.UInt32> [3] 381 (ANDconst <typ.UInt32> [3] 382 (XORconst <typ.UInt32> [3] ptr)))) 383 (NORconst [0] <typ.UInt32> (SLL <typ.UInt32> 384 (MOVWconst [0xff]) (SLLconst <typ.UInt32> [3] 385 (ANDconst <typ.UInt32> [3] 386 (XORconst <typ.UInt32> [3] ptr)))))) mem) 387 388(AtomicAnd32 ...) => (LoweredAtomicAnd ...) 389(AtomicOr32 ...) => (LoweredAtomicOr ...) 390 391 392// checks 393(NilCheck ...) => (LoweredNilCheck ...) 394(IsNonNil ptr) => (SGTU ptr (MOVWconst [0])) 395(IsInBounds idx len) => (SGTU len idx) 396(IsSliceInBounds idx len) => (XORconst [1] (SGTU idx len)) 397 398// pseudo-ops 399(GetClosurePtr ...) => (LoweredGetClosurePtr ...) 400(GetCallerSP ...) => (LoweredGetCallerSP ...) 401(GetCallerPC ...) => (LoweredGetCallerPC ...) 402 403(If cond yes no) => (NE cond yes no) 404 405// Write barrier. 406(WB ...) => (LoweredWB ...) 407 408(PanicBounds [kind] x y mem) && boundsABI(kind) == 0 => (LoweredPanicBoundsA [kind] x y mem) 409(PanicBounds [kind] x y mem) && boundsABI(kind) == 1 => (LoweredPanicBoundsB [kind] x y mem) 410(PanicBounds [kind] x y mem) && boundsABI(kind) == 2 => (LoweredPanicBoundsC [kind] x y mem) 411 412(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 0 => (LoweredPanicExtendA [kind] hi lo y mem) 413(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 1 => (LoweredPanicExtendB [kind] hi lo y mem) 414(PanicExtend [kind] hi lo y mem) && boundsABI(kind) == 2 => (LoweredPanicExtendC [kind] hi lo y mem) 415 416// Optimizations 417 418// Absorb boolean tests into block 419(NE (FPFlagTrue cmp) yes no) => (FPT cmp yes no) 420(NE (FPFlagFalse cmp) yes no) => (FPF cmp yes no) 421(EQ (FPFlagTrue cmp) yes no) => (FPF cmp yes no) 422(EQ (FPFlagFalse cmp) yes no) => (FPT cmp yes no) 423(NE (XORconst [1] cmp:(SGT _ _)) yes no) => (EQ cmp yes no) 424(NE (XORconst [1] cmp:(SGTU _ _)) yes no) => (EQ cmp yes no) 425(NE (XORconst [1] cmp:(SGTconst _)) yes no) => (EQ cmp yes no) 426(NE (XORconst [1] cmp:(SGTUconst _)) yes no) => (EQ cmp yes no) 427(NE (XORconst [1] cmp:(SGTzero _)) yes no) => (EQ cmp yes no) 428(NE (XORconst [1] cmp:(SGTUzero _)) yes no) => (EQ cmp yes no) 429(EQ (XORconst [1] cmp:(SGT _ _)) yes no) => (NE cmp yes no) 430(EQ (XORconst [1] cmp:(SGTU _ _)) yes no) => (NE cmp yes no) 431(EQ (XORconst [1] cmp:(SGTconst _)) yes no) => (NE cmp yes no) 432(EQ (XORconst [1] cmp:(SGTUconst _)) yes no) => (NE cmp yes no) 433(EQ (XORconst [1] cmp:(SGTzero _)) yes no) => (NE cmp yes no) 434(EQ (XORconst [1] cmp:(SGTUzero _)) yes no) => (NE cmp yes no) 435(NE (SGTUconst [1] x) yes no) => (EQ x yes no) 436(EQ (SGTUconst [1] x) yes no) => (NE x yes no) 437(NE (SGTUzero x) yes no) => (NE x yes no) 438(EQ (SGTUzero x) yes no) => (EQ x yes no) 439(NE (SGTconst [0] x) yes no) => (LTZ x yes no) 440(EQ (SGTconst [0] x) yes no) => (GEZ x yes no) 441(NE (SGTzero x) yes no) => (GTZ x yes no) 442(EQ (SGTzero x) yes no) => (LEZ x yes no) 443 444// fold offset into address 445(ADDconst [off1] (MOVWaddr [off2] {sym} ptr)) => (MOVWaddr [off1+off2] {sym} ptr) 446 447// fold address into load/store 448(MOVBload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBload [off1+off2] {sym} ptr mem) 449(MOVBUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBUload [off1+off2] {sym} ptr mem) 450(MOVHload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHload [off1+off2] {sym} ptr mem) 451(MOVHUload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHUload [off1+off2] {sym} ptr mem) 452(MOVWload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWload [off1+off2] {sym} ptr mem) 453(MOVFload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFload [off1+off2] {sym} ptr mem) 454(MOVDload [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDload [off1+off2] {sym} ptr mem) 455 456(MOVBstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstore [off1+off2] {sym} ptr val mem) 457(MOVHstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstore [off1+off2] {sym} ptr val mem) 458(MOVWstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstore [off1+off2] {sym} ptr val mem) 459(MOVFstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVFstore [off1+off2] {sym} ptr val mem) 460(MOVDstore [off1] {sym} x:(ADDconst [off2] ptr) val mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVDstore [off1+off2] {sym} ptr val mem) 461 462(MOVBstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVBstorezero [off1+off2] {sym} ptr mem) 463(MOVHstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVHstorezero [off1+off2] {sym} ptr mem) 464(MOVWstorezero [off1] {sym} x:(ADDconst [off2] ptr) mem) && (is16Bit(int64(off1+off2)) || x.Uses == 1) => (MOVWstorezero [off1+off2] {sym} ptr mem) 465 466(MOVBload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 467 (MOVBload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 468(MOVBUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 469 (MOVBUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 470(MOVHload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 471 (MOVHload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 472(MOVHUload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 473 (MOVHUload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 474(MOVWload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 475 (MOVWload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 476(MOVFload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 477 (MOVFload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 478(MOVDload [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 479 (MOVDload [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 480 481(MOVBstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => 482 (MOVBstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 483(MOVHstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => 484 (MOVHstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 485(MOVWstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => 486 (MOVWstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 487(MOVFstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => 488 (MOVFstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 489(MOVDstore [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) val mem) && canMergeSym(sym1,sym2) => 490 (MOVDstore [off1+off2] {mergeSym(sym1,sym2)} ptr val mem) 491(MOVBstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 492 (MOVBstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 493(MOVHstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 494 (MOVHstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 495(MOVWstorezero [off1] {sym1} (MOVWaddr [off2] {sym2} ptr) mem) && canMergeSym(sym1,sym2) => 496 (MOVWstorezero [off1+off2] {mergeSym(sym1,sym2)} ptr mem) 497 498// replace load from same location as preceding store with zero/sign extension (or copy in case of full width) 499(MOVBload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBreg x) 500(MOVBUload [off] {sym} ptr (MOVBstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVBUreg x) 501(MOVHload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHreg x) 502(MOVHUload [off] {sym} ptr (MOVHstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => (MOVHUreg x) 503(MOVWload [off] {sym} ptr (MOVWstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x 504(MOVFload [off] {sym} ptr (MOVFstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x 505(MOVDload [off] {sym} ptr (MOVDstore [off2] {sym2} ptr2 x _)) && sym == sym2 && off == off2 && isSamePtr(ptr, ptr2) => x 506 507// store zero 508(MOVBstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVBstorezero [off] {sym} ptr mem) 509(MOVHstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVHstorezero [off] {sym} ptr mem) 510(MOVWstore [off] {sym} ptr (MOVWconst [0]) mem) => (MOVWstorezero [off] {sym} ptr mem) 511 512// don't extend after proper load 513(MOVBreg x:(MOVBload _ _)) => (MOVWreg x) 514(MOVBUreg x:(MOVBUload _ _)) => (MOVWreg x) 515(MOVHreg x:(MOVBload _ _)) => (MOVWreg x) 516(MOVHreg x:(MOVBUload _ _)) => (MOVWreg x) 517(MOVHreg x:(MOVHload _ _)) => (MOVWreg x) 518(MOVHUreg x:(MOVBUload _ _)) => (MOVWreg x) 519(MOVHUreg x:(MOVHUload _ _)) => (MOVWreg x) 520 521// fold double extensions 522(MOVBreg x:(MOVBreg _)) => (MOVWreg x) 523(MOVBUreg x:(MOVBUreg _)) => (MOVWreg x) 524(MOVHreg x:(MOVBreg _)) => (MOVWreg x) 525(MOVHreg x:(MOVBUreg _)) => (MOVWreg x) 526(MOVHreg x:(MOVHreg _)) => (MOVWreg x) 527(MOVHUreg x:(MOVBUreg _)) => (MOVWreg x) 528(MOVHUreg x:(MOVHUreg _)) => (MOVWreg x) 529 530// sign extended loads 531// Note: The combined instruction must end up in the same block 532// as the original load. If not, we end up making a value with 533// memory type live in two different blocks, which can lead to 534// multiple memory values alive simultaneously. 535// Make sure we don't combine these ops if the load has another use. 536// This prevents a single load from being split into multiple loads 537// which then might return different values. See test/atomicload.go. 538(MOVBreg <t> x:(MOVBUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBload <t> [off] {sym} ptr mem) 539(MOVBUreg <t> x:(MOVBload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVBUload <t> [off] {sym} ptr mem) 540(MOVHreg <t> x:(MOVHUload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHload <t> [off] {sym} ptr mem) 541(MOVHUreg <t> x:(MOVHload [off] {sym} ptr mem)) && x.Uses == 1 && clobber(x) => @x.Block (MOVHUload <t> [off] {sym} ptr mem) 542 543// fold extensions and ANDs together 544(MOVBUreg (ANDconst [c] x)) => (ANDconst [c&0xff] x) 545(MOVHUreg (ANDconst [c] x)) => (ANDconst [c&0xffff] x) 546(MOVBreg (ANDconst [c] x)) && c & 0x80 == 0 => (ANDconst [c&0x7f] x) 547(MOVHreg (ANDconst [c] x)) && c & 0x8000 == 0 => (ANDconst [c&0x7fff] x) 548 549// don't extend before store 550(MOVBstore [off] {sym} ptr (MOVBreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 551(MOVBstore [off] {sym} ptr (MOVBUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 552(MOVBstore [off] {sym} ptr (MOVHreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 553(MOVBstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 554(MOVBstore [off] {sym} ptr (MOVWreg x) mem) => (MOVBstore [off] {sym} ptr x mem) 555(MOVHstore [off] {sym} ptr (MOVHreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 556(MOVHstore [off] {sym} ptr (MOVHUreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 557(MOVHstore [off] {sym} ptr (MOVWreg x) mem) => (MOVHstore [off] {sym} ptr x mem) 558(MOVWstore [off] {sym} ptr (MOVWreg x) mem) => (MOVWstore [off] {sym} ptr x mem) 559 560// if a register move has only 1 use, just use the same register without emitting instruction 561// MOVWnop doesn't emit instruction, only for ensuring the type. 562(MOVWreg x) && x.Uses == 1 => (MOVWnop x) 563 564// TODO: we should be able to get rid of MOVWnop all together. 565// But for now, this is enough to get rid of lots of them. 566(MOVWnop (MOVWconst [c])) => (MOVWconst [c]) 567 568// fold constant into arithmatic ops 569(ADD x (MOVWconst [c])) => (ADDconst [c] x) 570(SUB x (MOVWconst [c])) => (SUBconst [c] x) 571(AND x (MOVWconst [c])) => (ANDconst [c] x) 572(OR x (MOVWconst [c])) => (ORconst [c] x) 573(XOR x (MOVWconst [c])) => (XORconst [c] x) 574(NOR x (MOVWconst [c])) => (NORconst [c] x) 575 576(SLL x (MOVWconst [c])) => (SLLconst x [c&31]) 577(SRL x (MOVWconst [c])) => (SRLconst x [c&31]) 578(SRA x (MOVWconst [c])) => (SRAconst x [c&31]) 579 580(SGT (MOVWconst [c]) x) => (SGTconst [c] x) 581(SGTU (MOVWconst [c]) x) => (SGTUconst [c] x) 582(SGT x (MOVWconst [0])) => (SGTzero x) 583(SGTU x (MOVWconst [0])) => (SGTUzero x) 584 585// mul with constant 586(Select1 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0]) 587(Select0 (MULTU (MOVWconst [0]) _ )) => (MOVWconst [0]) 588(Select1 (MULTU (MOVWconst [1]) x )) => x 589(Select0 (MULTU (MOVWconst [1]) _ )) => (MOVWconst [0]) 590(Select1 (MULTU (MOVWconst [-1]) x )) => (NEG <x.Type> x) 591(Select0 (MULTU (MOVWconst [-1]) x )) => (CMOVZ (ADDconst <x.Type> [-1] x) (MOVWconst [0]) x) 592(Select1 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo64(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x) 593(Select0 (MULTU (MOVWconst [c]) x )) && isPowerOfTwo64(int64(uint32(c))) => (SRLconst [int32(32-log2uint32(int64(c)))] x) 594 595(MUL (MOVWconst [0]) _ ) => (MOVWconst [0]) 596(MUL (MOVWconst [1]) x ) => x 597(MUL (MOVWconst [-1]) x ) => (NEG x) 598(MUL (MOVWconst [c]) x ) && isPowerOfTwo64(int64(uint32(c))) => (SLLconst [int32(log2uint32(int64(c)))] x) 599 600// generic simplifications 601(ADD x (NEG y)) => (SUB x y) 602(SUB x x) => (MOVWconst [0]) 603(SUB (MOVWconst [0]) x) => (NEG x) 604(AND x x) => x 605(OR x x) => x 606(XOR x x) => (MOVWconst [0]) 607 608// miscellaneous patterns generated by dec64 609(AND (SGTUconst [1] x) (SGTUconst [1] y)) => (SGTUconst [1] (OR <x.Type> x y)) 610(OR (SGTUzero x) (SGTUzero y)) => (SGTUzero (OR <x.Type> x y)) 611 612// remove redundant *const ops 613(ADDconst [0] x) => x 614(SUBconst [0] x) => x 615(ANDconst [0] _) => (MOVWconst [0]) 616(ANDconst [-1] x) => x 617(ORconst [0] x) => x 618(ORconst [-1] _) => (MOVWconst [-1]) 619(XORconst [0] x) => x 620(XORconst [-1] x) => (NORconst [0] x) 621 622// generic constant folding 623(ADDconst [c] (MOVWconst [d])) => (MOVWconst [int32(c+d)]) 624(ADDconst [c] (ADDconst [d] x)) => (ADDconst [c+d] x) 625(ADDconst [c] (SUBconst [d] x)) => (ADDconst [c-d] x) 626(SUBconst [c] (MOVWconst [d])) => (MOVWconst [d-c]) 627(SUBconst [c] (SUBconst [d] x)) => (ADDconst [-c-d] x) 628(SUBconst [c] (ADDconst [d] x)) => (ADDconst [-c+d] x) 629(SLLconst [c] (MOVWconst [d])) => (MOVWconst [d<<uint32(c)]) 630(SRLconst [c] (MOVWconst [d])) => (MOVWconst [int32(uint32(d)>>uint32(c))]) 631(SRAconst [c] (MOVWconst [d])) => (MOVWconst [d>>uint32(c)]) 632(MUL (MOVWconst [c]) (MOVWconst [d])) => (MOVWconst [c*d]) 633(Select1 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32(uint32(c)*uint32(d))]) 634(Select0 (MULTU (MOVWconst [c]) (MOVWconst [d]))) => (MOVWconst [int32((int64(uint32(c))*int64(uint32(d)))>>32)]) 635(Select1 (DIV (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [c/d]) 636(Select1 (DIVU (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [int32(uint32(c)/uint32(d))]) 637(Select0 (DIV (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [c%d]) 638(Select0 (DIVU (MOVWconst [c]) (MOVWconst [d]))) && d != 0 => (MOVWconst [int32(uint32(c)%uint32(d))]) 639(ANDconst [c] (MOVWconst [d])) => (MOVWconst [c&d]) 640(ANDconst [c] (ANDconst [d] x)) => (ANDconst [c&d] x) 641(ORconst [c] (MOVWconst [d])) => (MOVWconst [c|d]) 642(ORconst [c] (ORconst [d] x)) => (ORconst [c|d] x) 643(XORconst [c] (MOVWconst [d])) => (MOVWconst [c^d]) 644(XORconst [c] (XORconst [d] x)) => (XORconst [c^d] x) 645(NORconst [c] (MOVWconst [d])) => (MOVWconst [^(c|d)]) 646(NEG (MOVWconst [c])) => (MOVWconst [-c]) 647(MOVBreg (MOVWconst [c])) => (MOVWconst [int32(int8(c))]) 648(MOVBUreg (MOVWconst [c])) => (MOVWconst [int32(uint8(c))]) 649(MOVHreg (MOVWconst [c])) => (MOVWconst [int32(int16(c))]) 650(MOVHUreg (MOVWconst [c])) => (MOVWconst [int32(uint16(c))]) 651(MOVWreg (MOVWconst [c])) => (MOVWconst [c]) 652 653// constant comparisons 654(SGTconst [c] (MOVWconst [d])) && c > d => (MOVWconst [1]) 655(SGTconst [c] (MOVWconst [d])) && c <= d => (MOVWconst [0]) 656(SGTUconst [c] (MOVWconst [d])) && uint32(c) > uint32(d) => (MOVWconst [1]) 657(SGTUconst [c] (MOVWconst [d])) && uint32(c) <= uint32(d) => (MOVWconst [0]) 658(SGTzero (MOVWconst [d])) && d > 0 => (MOVWconst [1]) 659(SGTzero (MOVWconst [d])) && d <= 0 => (MOVWconst [0]) 660(SGTUzero (MOVWconst [d])) && d != 0 => (MOVWconst [1]) 661(SGTUzero (MOVWconst [d])) && d == 0 => (MOVWconst [0]) 662 663// other known comparisons 664(SGTconst [c] (MOVBreg _)) && 0x7f < c => (MOVWconst [1]) 665(SGTconst [c] (MOVBreg _)) && c <= -0x80 => (MOVWconst [0]) 666(SGTconst [c] (MOVBUreg _)) && 0xff < c => (MOVWconst [1]) 667(SGTconst [c] (MOVBUreg _)) && c < 0 => (MOVWconst [0]) 668(SGTUconst [c] (MOVBUreg _)) && 0xff < uint32(c) => (MOVWconst [1]) 669(SGTconst [c] (MOVHreg _)) && 0x7fff < c => (MOVWconst [1]) 670(SGTconst [c] (MOVHreg _)) && c <= -0x8000 => (MOVWconst [0]) 671(SGTconst [c] (MOVHUreg _)) && 0xffff < c => (MOVWconst [1]) 672(SGTconst [c] (MOVHUreg _)) && c < 0 => (MOVWconst [0]) 673(SGTUconst [c] (MOVHUreg _)) && 0xffff < uint32(c) => (MOVWconst [1]) 674(SGTconst [c] (ANDconst [m] _)) && 0 <= m && m < c => (MOVWconst [1]) 675(SGTUconst [c] (ANDconst [m] _)) && uint32(m) < uint32(c) => (MOVWconst [1]) 676(SGTconst [c] (SRLconst _ [d])) && 0 <= c && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1]) 677(SGTUconst [c] (SRLconst _ [d])) && uint32(d) <= 31 && 0xffffffff>>uint32(d) < uint32(c) => (MOVWconst [1]) 678 679// absorb constants into branches 680(EQ (MOVWconst [0]) yes no) => (First yes no) 681(EQ (MOVWconst [c]) yes no) && c != 0 => (First no yes) 682(NE (MOVWconst [0]) yes no) => (First no yes) 683(NE (MOVWconst [c]) yes no) && c != 0 => (First yes no) 684(LTZ (MOVWconst [c]) yes no) && c < 0 => (First yes no) 685(LTZ (MOVWconst [c]) yes no) && c >= 0 => (First no yes) 686(LEZ (MOVWconst [c]) yes no) && c <= 0 => (First yes no) 687(LEZ (MOVWconst [c]) yes no) && c > 0 => (First no yes) 688(GTZ (MOVWconst [c]) yes no) && c > 0 => (First yes no) 689(GTZ (MOVWconst [c]) yes no) && c <= 0 => (First no yes) 690(GEZ (MOVWconst [c]) yes no) && c >= 0 => (First yes no) 691(GEZ (MOVWconst [c]) yes no) && c < 0 => (First no yes) 692 693// conditional move 694(CMOVZ _ f (MOVWconst [0])) => f 695(CMOVZ a _ (MOVWconst [c])) && c!=0 => a 696(CMOVZzero _ (MOVWconst [0])) => (MOVWconst [0]) 697(CMOVZzero a (MOVWconst [c])) && c!=0 => a 698(CMOVZ a (MOVWconst [0]) c) => (CMOVZzero a c) 699 700// atomic 701(LoweredAtomicStore32 ptr (MOVWconst [0]) mem) => (LoweredAtomicStorezero ptr mem) 702(LoweredAtomicAdd ptr (MOVWconst [c]) mem) && is16Bit(int64(c)) => (LoweredAtomicAddconst [c] ptr mem) 703 704