1// Code generated from gen/*Ops.go; DO NOT EDIT.
2
3package ssa
4
5import (
6	"cmd/internal/obj"
7	"cmd/internal/obj/arm"
8	"cmd/internal/obj/arm64"
9	"cmd/internal/obj/mips"
10	"cmd/internal/obj/ppc64"
11	"cmd/internal/obj/riscv"
12	"cmd/internal/obj/s390x"
13	"cmd/internal/obj/wasm"
14	"cmd/internal/obj/x86"
15)
16
17const (
18	BlockInvalid BlockKind = iota
19
20	Block386EQ
21	Block386NE
22	Block386LT
23	Block386LE
24	Block386GT
25	Block386GE
26	Block386OS
27	Block386OC
28	Block386ULT
29	Block386ULE
30	Block386UGT
31	Block386UGE
32	Block386EQF
33	Block386NEF
34	Block386ORD
35	Block386NAN
36
37	BlockAMD64EQ
38	BlockAMD64NE
39	BlockAMD64LT
40	BlockAMD64LE
41	BlockAMD64GT
42	BlockAMD64GE
43	BlockAMD64OS
44	BlockAMD64OC
45	BlockAMD64ULT
46	BlockAMD64ULE
47	BlockAMD64UGT
48	BlockAMD64UGE
49	BlockAMD64EQF
50	BlockAMD64NEF
51	BlockAMD64ORD
52	BlockAMD64NAN
53
54	BlockARMEQ
55	BlockARMNE
56	BlockARMLT
57	BlockARMLE
58	BlockARMGT
59	BlockARMGE
60	BlockARMULT
61	BlockARMULE
62	BlockARMUGT
63	BlockARMUGE
64	BlockARMLTnoov
65	BlockARMLEnoov
66	BlockARMGTnoov
67	BlockARMGEnoov
68
69	BlockARM64EQ
70	BlockARM64NE
71	BlockARM64LT
72	BlockARM64LE
73	BlockARM64GT
74	BlockARM64GE
75	BlockARM64ULT
76	BlockARM64ULE
77	BlockARM64UGT
78	BlockARM64UGE
79	BlockARM64Z
80	BlockARM64NZ
81	BlockARM64ZW
82	BlockARM64NZW
83	BlockARM64TBZ
84	BlockARM64TBNZ
85	BlockARM64FLT
86	BlockARM64FLE
87	BlockARM64FGT
88	BlockARM64FGE
89	BlockARM64LTnoov
90	BlockARM64LEnoov
91	BlockARM64GTnoov
92	BlockARM64GEnoov
93
94	BlockMIPSEQ
95	BlockMIPSNE
96	BlockMIPSLTZ
97	BlockMIPSLEZ
98	BlockMIPSGTZ
99	BlockMIPSGEZ
100	BlockMIPSFPT
101	BlockMIPSFPF
102
103	BlockMIPS64EQ
104	BlockMIPS64NE
105	BlockMIPS64LTZ
106	BlockMIPS64LEZ
107	BlockMIPS64GTZ
108	BlockMIPS64GEZ
109	BlockMIPS64FPT
110	BlockMIPS64FPF
111
112	BlockPPC64EQ
113	BlockPPC64NE
114	BlockPPC64LT
115	BlockPPC64LE
116	BlockPPC64GT
117	BlockPPC64GE
118	BlockPPC64FLT
119	BlockPPC64FLE
120	BlockPPC64FGT
121	BlockPPC64FGE
122
123	BlockRISCV64BEQ
124	BlockRISCV64BNE
125	BlockRISCV64BLT
126	BlockRISCV64BGE
127	BlockRISCV64BLTU
128	BlockRISCV64BGEU
129	BlockRISCV64BEQZ
130	BlockRISCV64BNEZ
131	BlockRISCV64BLEZ
132	BlockRISCV64BGEZ
133	BlockRISCV64BLTZ
134	BlockRISCV64BGTZ
135
136	BlockS390XBRC
137	BlockS390XCRJ
138	BlockS390XCGRJ
139	BlockS390XCLRJ
140	BlockS390XCLGRJ
141	BlockS390XCIJ
142	BlockS390XCGIJ
143	BlockS390XCLIJ
144	BlockS390XCLGIJ
145
146	BlockPlain
147	BlockIf
148	BlockDefer
149	BlockRet
150	BlockRetJmp
151	BlockExit
152	BlockFirst
153)
154
155var blockString = [...]string{
156	BlockInvalid: "BlockInvalid",
157
158	Block386EQ:  "EQ",
159	Block386NE:  "NE",
160	Block386LT:  "LT",
161	Block386LE:  "LE",
162	Block386GT:  "GT",
163	Block386GE:  "GE",
164	Block386OS:  "OS",
165	Block386OC:  "OC",
166	Block386ULT: "ULT",
167	Block386ULE: "ULE",
168	Block386UGT: "UGT",
169	Block386UGE: "UGE",
170	Block386EQF: "EQF",
171	Block386NEF: "NEF",
172	Block386ORD: "ORD",
173	Block386NAN: "NAN",
174
175	BlockAMD64EQ:  "EQ",
176	BlockAMD64NE:  "NE",
177	BlockAMD64LT:  "LT",
178	BlockAMD64LE:  "LE",
179	BlockAMD64GT:  "GT",
180	BlockAMD64GE:  "GE",
181	BlockAMD64OS:  "OS",
182	BlockAMD64OC:  "OC",
183	BlockAMD64ULT: "ULT",
184	BlockAMD64ULE: "ULE",
185	BlockAMD64UGT: "UGT",
186	BlockAMD64UGE: "UGE",
187	BlockAMD64EQF: "EQF",
188	BlockAMD64NEF: "NEF",
189	BlockAMD64ORD: "ORD",
190	BlockAMD64NAN: "NAN",
191
192	BlockARMEQ:     "EQ",
193	BlockARMNE:     "NE",
194	BlockARMLT:     "LT",
195	BlockARMLE:     "LE",
196	BlockARMGT:     "GT",
197	BlockARMGE:     "GE",
198	BlockARMULT:    "ULT",
199	BlockARMULE:    "ULE",
200	BlockARMUGT:    "UGT",
201	BlockARMUGE:    "UGE",
202	BlockARMLTnoov: "LTnoov",
203	BlockARMLEnoov: "LEnoov",
204	BlockARMGTnoov: "GTnoov",
205	BlockARMGEnoov: "GEnoov",
206
207	BlockARM64EQ:     "EQ",
208	BlockARM64NE:     "NE",
209	BlockARM64LT:     "LT",
210	BlockARM64LE:     "LE",
211	BlockARM64GT:     "GT",
212	BlockARM64GE:     "GE",
213	BlockARM64ULT:    "ULT",
214	BlockARM64ULE:    "ULE",
215	BlockARM64UGT:    "UGT",
216	BlockARM64UGE:    "UGE",
217	BlockARM64Z:      "Z",
218	BlockARM64NZ:     "NZ",
219	BlockARM64ZW:     "ZW",
220	BlockARM64NZW:    "NZW",
221	BlockARM64TBZ:    "TBZ",
222	BlockARM64TBNZ:   "TBNZ",
223	BlockARM64FLT:    "FLT",
224	BlockARM64FLE:    "FLE",
225	BlockARM64FGT:    "FGT",
226	BlockARM64FGE:    "FGE",
227	BlockARM64LTnoov: "LTnoov",
228	BlockARM64LEnoov: "LEnoov",
229	BlockARM64GTnoov: "GTnoov",
230	BlockARM64GEnoov: "GEnoov",
231
232	BlockMIPSEQ:  "EQ",
233	BlockMIPSNE:  "NE",
234	BlockMIPSLTZ: "LTZ",
235	BlockMIPSLEZ: "LEZ",
236	BlockMIPSGTZ: "GTZ",
237	BlockMIPSGEZ: "GEZ",
238	BlockMIPSFPT: "FPT",
239	BlockMIPSFPF: "FPF",
240
241	BlockMIPS64EQ:  "EQ",
242	BlockMIPS64NE:  "NE",
243	BlockMIPS64LTZ: "LTZ",
244	BlockMIPS64LEZ: "LEZ",
245	BlockMIPS64GTZ: "GTZ",
246	BlockMIPS64GEZ: "GEZ",
247	BlockMIPS64FPT: "FPT",
248	BlockMIPS64FPF: "FPF",
249
250	BlockPPC64EQ:  "EQ",
251	BlockPPC64NE:  "NE",
252	BlockPPC64LT:  "LT",
253	BlockPPC64LE:  "LE",
254	BlockPPC64GT:  "GT",
255	BlockPPC64GE:  "GE",
256	BlockPPC64FLT: "FLT",
257	BlockPPC64FLE: "FLE",
258	BlockPPC64FGT: "FGT",
259	BlockPPC64FGE: "FGE",
260
261	BlockRISCV64BEQ:  "BEQ",
262	BlockRISCV64BNE:  "BNE",
263	BlockRISCV64BLT:  "BLT",
264	BlockRISCV64BGE:  "BGE",
265	BlockRISCV64BLTU: "BLTU",
266	BlockRISCV64BGEU: "BGEU",
267	BlockRISCV64BEQZ: "BEQZ",
268	BlockRISCV64BNEZ: "BNEZ",
269	BlockRISCV64BLEZ: "BLEZ",
270	BlockRISCV64BGEZ: "BGEZ",
271	BlockRISCV64BLTZ: "BLTZ",
272	BlockRISCV64BGTZ: "BGTZ",
273
274	BlockS390XBRC:   "BRC",
275	BlockS390XCRJ:   "CRJ",
276	BlockS390XCGRJ:  "CGRJ",
277	BlockS390XCLRJ:  "CLRJ",
278	BlockS390XCLGRJ: "CLGRJ",
279	BlockS390XCIJ:   "CIJ",
280	BlockS390XCGIJ:  "CGIJ",
281	BlockS390XCLIJ:  "CLIJ",
282	BlockS390XCLGIJ: "CLGIJ",
283
284	BlockPlain:  "Plain",
285	BlockIf:     "If",
286	BlockDefer:  "Defer",
287	BlockRet:    "Ret",
288	BlockRetJmp: "RetJmp",
289	BlockExit:   "Exit",
290	BlockFirst:  "First",
291}
292
293func (k BlockKind) String() string { return blockString[k] }
294func (k BlockKind) AuxIntType() string {
295	switch k {
296	case BlockARM64TBZ:
297		return "int64"
298	case BlockARM64TBNZ:
299		return "int64"
300	case BlockS390XCIJ:
301		return "int8"
302	case BlockS390XCGIJ:
303		return "int8"
304	case BlockS390XCLIJ:
305		return "uint8"
306	case BlockS390XCLGIJ:
307		return "uint8"
308	}
309	return ""
310}
311
312const (
313	OpInvalid Op = iota
314
315	Op386ADDSS
316	Op386ADDSD
317	Op386SUBSS
318	Op386SUBSD
319	Op386MULSS
320	Op386MULSD
321	Op386DIVSS
322	Op386DIVSD
323	Op386MOVSSload
324	Op386MOVSDload
325	Op386MOVSSconst
326	Op386MOVSDconst
327	Op386MOVSSloadidx1
328	Op386MOVSSloadidx4
329	Op386MOVSDloadidx1
330	Op386MOVSDloadidx8
331	Op386MOVSSstore
332	Op386MOVSDstore
333	Op386MOVSSstoreidx1
334	Op386MOVSSstoreidx4
335	Op386MOVSDstoreidx1
336	Op386MOVSDstoreidx8
337	Op386ADDSSload
338	Op386ADDSDload
339	Op386SUBSSload
340	Op386SUBSDload
341	Op386MULSSload
342	Op386MULSDload
343	Op386DIVSSload
344	Op386DIVSDload
345	Op386ADDL
346	Op386ADDLconst
347	Op386ADDLcarry
348	Op386ADDLconstcarry
349	Op386ADCL
350	Op386ADCLconst
351	Op386SUBL
352	Op386SUBLconst
353	Op386SUBLcarry
354	Op386SUBLconstcarry
355	Op386SBBL
356	Op386SBBLconst
357	Op386MULL
358	Op386MULLconst
359	Op386MULLU
360	Op386HMULL
361	Op386HMULLU
362	Op386MULLQU
363	Op386AVGLU
364	Op386DIVL
365	Op386DIVW
366	Op386DIVLU
367	Op386DIVWU
368	Op386MODL
369	Op386MODW
370	Op386MODLU
371	Op386MODWU
372	Op386ANDL
373	Op386ANDLconst
374	Op386ORL
375	Op386ORLconst
376	Op386XORL
377	Op386XORLconst
378	Op386CMPL
379	Op386CMPW
380	Op386CMPB
381	Op386CMPLconst
382	Op386CMPWconst
383	Op386CMPBconst
384	Op386CMPLload
385	Op386CMPWload
386	Op386CMPBload
387	Op386CMPLconstload
388	Op386CMPWconstload
389	Op386CMPBconstload
390	Op386UCOMISS
391	Op386UCOMISD
392	Op386TESTL
393	Op386TESTW
394	Op386TESTB
395	Op386TESTLconst
396	Op386TESTWconst
397	Op386TESTBconst
398	Op386SHLL
399	Op386SHLLconst
400	Op386SHRL
401	Op386SHRW
402	Op386SHRB
403	Op386SHRLconst
404	Op386SHRWconst
405	Op386SHRBconst
406	Op386SARL
407	Op386SARW
408	Op386SARB
409	Op386SARLconst
410	Op386SARWconst
411	Op386SARBconst
412	Op386ROLLconst
413	Op386ROLWconst
414	Op386ROLBconst
415	Op386ADDLload
416	Op386SUBLload
417	Op386MULLload
418	Op386ANDLload
419	Op386ORLload
420	Op386XORLload
421	Op386ADDLloadidx4
422	Op386SUBLloadidx4
423	Op386MULLloadidx4
424	Op386ANDLloadidx4
425	Op386ORLloadidx4
426	Op386XORLloadidx4
427	Op386NEGL
428	Op386NOTL
429	Op386BSFL
430	Op386BSFW
431	Op386BSRL
432	Op386BSRW
433	Op386BSWAPL
434	Op386SQRTSD
435	Op386SQRTSS
436	Op386SBBLcarrymask
437	Op386SETEQ
438	Op386SETNE
439	Op386SETL
440	Op386SETLE
441	Op386SETG
442	Op386SETGE
443	Op386SETB
444	Op386SETBE
445	Op386SETA
446	Op386SETAE
447	Op386SETO
448	Op386SETEQF
449	Op386SETNEF
450	Op386SETORD
451	Op386SETNAN
452	Op386SETGF
453	Op386SETGEF
454	Op386MOVBLSX
455	Op386MOVBLZX
456	Op386MOVWLSX
457	Op386MOVWLZX
458	Op386MOVLconst
459	Op386CVTTSD2SL
460	Op386CVTTSS2SL
461	Op386CVTSL2SS
462	Op386CVTSL2SD
463	Op386CVTSD2SS
464	Op386CVTSS2SD
465	Op386PXOR
466	Op386LEAL
467	Op386LEAL1
468	Op386LEAL2
469	Op386LEAL4
470	Op386LEAL8
471	Op386MOVBload
472	Op386MOVBLSXload
473	Op386MOVWload
474	Op386MOVWLSXload
475	Op386MOVLload
476	Op386MOVBstore
477	Op386MOVWstore
478	Op386MOVLstore
479	Op386ADDLmodify
480	Op386SUBLmodify
481	Op386ANDLmodify
482	Op386ORLmodify
483	Op386XORLmodify
484	Op386ADDLmodifyidx4
485	Op386SUBLmodifyidx4
486	Op386ANDLmodifyidx4
487	Op386ORLmodifyidx4
488	Op386XORLmodifyidx4
489	Op386ADDLconstmodify
490	Op386ANDLconstmodify
491	Op386ORLconstmodify
492	Op386XORLconstmodify
493	Op386ADDLconstmodifyidx4
494	Op386ANDLconstmodifyidx4
495	Op386ORLconstmodifyidx4
496	Op386XORLconstmodifyidx4
497	Op386MOVBloadidx1
498	Op386MOVWloadidx1
499	Op386MOVWloadidx2
500	Op386MOVLloadidx1
501	Op386MOVLloadidx4
502	Op386MOVBstoreidx1
503	Op386MOVWstoreidx1
504	Op386MOVWstoreidx2
505	Op386MOVLstoreidx1
506	Op386MOVLstoreidx4
507	Op386MOVBstoreconst
508	Op386MOVWstoreconst
509	Op386MOVLstoreconst
510	Op386MOVBstoreconstidx1
511	Op386MOVWstoreconstidx1
512	Op386MOVWstoreconstidx2
513	Op386MOVLstoreconstidx1
514	Op386MOVLstoreconstidx4
515	Op386DUFFZERO
516	Op386REPSTOSL
517	Op386CALLstatic
518	Op386CALLtail
519	Op386CALLclosure
520	Op386CALLinter
521	Op386DUFFCOPY
522	Op386REPMOVSL
523	Op386InvertFlags
524	Op386LoweredGetG
525	Op386LoweredGetClosurePtr
526	Op386LoweredGetCallerPC
527	Op386LoweredGetCallerSP
528	Op386LoweredNilCheck
529	Op386LoweredWB
530	Op386LoweredPanicBoundsA
531	Op386LoweredPanicBoundsB
532	Op386LoweredPanicBoundsC
533	Op386LoweredPanicExtendA
534	Op386LoweredPanicExtendB
535	Op386LoweredPanicExtendC
536	Op386FlagEQ
537	Op386FlagLT_ULT
538	Op386FlagLT_UGT
539	Op386FlagGT_UGT
540	Op386FlagGT_ULT
541	Op386MOVSSconst1
542	Op386MOVSDconst1
543	Op386MOVSSconst2
544	Op386MOVSDconst2
545
546	OpAMD64ADDSS
547	OpAMD64ADDSD
548	OpAMD64SUBSS
549	OpAMD64SUBSD
550	OpAMD64MULSS
551	OpAMD64MULSD
552	OpAMD64DIVSS
553	OpAMD64DIVSD
554	OpAMD64MOVSSload
555	OpAMD64MOVSDload
556	OpAMD64MOVSSconst
557	OpAMD64MOVSDconst
558	OpAMD64MOVSSloadidx1
559	OpAMD64MOVSSloadidx4
560	OpAMD64MOVSDloadidx1
561	OpAMD64MOVSDloadidx8
562	OpAMD64MOVSSstore
563	OpAMD64MOVSDstore
564	OpAMD64MOVSSstoreidx1
565	OpAMD64MOVSSstoreidx4
566	OpAMD64MOVSDstoreidx1
567	OpAMD64MOVSDstoreidx8
568	OpAMD64ADDSSload
569	OpAMD64ADDSDload
570	OpAMD64SUBSSload
571	OpAMD64SUBSDload
572	OpAMD64MULSSload
573	OpAMD64MULSDload
574	OpAMD64DIVSSload
575	OpAMD64DIVSDload
576	OpAMD64ADDSSloadidx1
577	OpAMD64ADDSSloadidx4
578	OpAMD64ADDSDloadidx1
579	OpAMD64ADDSDloadidx8
580	OpAMD64SUBSSloadidx1
581	OpAMD64SUBSSloadidx4
582	OpAMD64SUBSDloadidx1
583	OpAMD64SUBSDloadidx8
584	OpAMD64MULSSloadidx1
585	OpAMD64MULSSloadidx4
586	OpAMD64MULSDloadidx1
587	OpAMD64MULSDloadidx8
588	OpAMD64DIVSSloadidx1
589	OpAMD64DIVSSloadidx4
590	OpAMD64DIVSDloadidx1
591	OpAMD64DIVSDloadidx8
592	OpAMD64ADDQ
593	OpAMD64ADDL
594	OpAMD64ADDQconst
595	OpAMD64ADDLconst
596	OpAMD64ADDQconstmodify
597	OpAMD64ADDLconstmodify
598	OpAMD64SUBQ
599	OpAMD64SUBL
600	OpAMD64SUBQconst
601	OpAMD64SUBLconst
602	OpAMD64MULQ
603	OpAMD64MULL
604	OpAMD64MULQconst
605	OpAMD64MULLconst
606	OpAMD64MULLU
607	OpAMD64MULQU
608	OpAMD64HMULQ
609	OpAMD64HMULL
610	OpAMD64HMULQU
611	OpAMD64HMULLU
612	OpAMD64AVGQU
613	OpAMD64DIVQ
614	OpAMD64DIVL
615	OpAMD64DIVW
616	OpAMD64DIVQU
617	OpAMD64DIVLU
618	OpAMD64DIVWU
619	OpAMD64NEGLflags
620	OpAMD64ADDQcarry
621	OpAMD64ADCQ
622	OpAMD64ADDQconstcarry
623	OpAMD64ADCQconst
624	OpAMD64SUBQborrow
625	OpAMD64SBBQ
626	OpAMD64SUBQconstborrow
627	OpAMD64SBBQconst
628	OpAMD64MULQU2
629	OpAMD64DIVQU2
630	OpAMD64ANDQ
631	OpAMD64ANDL
632	OpAMD64ANDQconst
633	OpAMD64ANDLconst
634	OpAMD64ANDQconstmodify
635	OpAMD64ANDLconstmodify
636	OpAMD64ORQ
637	OpAMD64ORL
638	OpAMD64ORQconst
639	OpAMD64ORLconst
640	OpAMD64ORQconstmodify
641	OpAMD64ORLconstmodify
642	OpAMD64XORQ
643	OpAMD64XORL
644	OpAMD64XORQconst
645	OpAMD64XORLconst
646	OpAMD64XORQconstmodify
647	OpAMD64XORLconstmodify
648	OpAMD64CMPQ
649	OpAMD64CMPL
650	OpAMD64CMPW
651	OpAMD64CMPB
652	OpAMD64CMPQconst
653	OpAMD64CMPLconst
654	OpAMD64CMPWconst
655	OpAMD64CMPBconst
656	OpAMD64CMPQload
657	OpAMD64CMPLload
658	OpAMD64CMPWload
659	OpAMD64CMPBload
660	OpAMD64CMPQconstload
661	OpAMD64CMPLconstload
662	OpAMD64CMPWconstload
663	OpAMD64CMPBconstload
664	OpAMD64CMPQloadidx8
665	OpAMD64CMPQloadidx1
666	OpAMD64CMPLloadidx4
667	OpAMD64CMPLloadidx1
668	OpAMD64CMPWloadidx2
669	OpAMD64CMPWloadidx1
670	OpAMD64CMPBloadidx1
671	OpAMD64CMPQconstloadidx8
672	OpAMD64CMPQconstloadidx1
673	OpAMD64CMPLconstloadidx4
674	OpAMD64CMPLconstloadidx1
675	OpAMD64CMPWconstloadidx2
676	OpAMD64CMPWconstloadidx1
677	OpAMD64CMPBconstloadidx1
678	OpAMD64UCOMISS
679	OpAMD64UCOMISD
680	OpAMD64BTL
681	OpAMD64BTQ
682	OpAMD64BTCL
683	OpAMD64BTCQ
684	OpAMD64BTRL
685	OpAMD64BTRQ
686	OpAMD64BTSL
687	OpAMD64BTSQ
688	OpAMD64BTLconst
689	OpAMD64BTQconst
690	OpAMD64BTCLconst
691	OpAMD64BTCQconst
692	OpAMD64BTRLconst
693	OpAMD64BTRQconst
694	OpAMD64BTSLconst
695	OpAMD64BTSQconst
696	OpAMD64TESTQ
697	OpAMD64TESTL
698	OpAMD64TESTW
699	OpAMD64TESTB
700	OpAMD64TESTQconst
701	OpAMD64TESTLconst
702	OpAMD64TESTWconst
703	OpAMD64TESTBconst
704	OpAMD64SHLQ
705	OpAMD64SHLL
706	OpAMD64SHLQconst
707	OpAMD64SHLLconst
708	OpAMD64SHRQ
709	OpAMD64SHRL
710	OpAMD64SHRW
711	OpAMD64SHRB
712	OpAMD64SHRQconst
713	OpAMD64SHRLconst
714	OpAMD64SHRWconst
715	OpAMD64SHRBconst
716	OpAMD64SARQ
717	OpAMD64SARL
718	OpAMD64SARW
719	OpAMD64SARB
720	OpAMD64SARQconst
721	OpAMD64SARLconst
722	OpAMD64SARWconst
723	OpAMD64SARBconst
724	OpAMD64SHRDQ
725	OpAMD64SHLDQ
726	OpAMD64ROLQ
727	OpAMD64ROLL
728	OpAMD64ROLW
729	OpAMD64ROLB
730	OpAMD64RORQ
731	OpAMD64RORL
732	OpAMD64RORW
733	OpAMD64RORB
734	OpAMD64ROLQconst
735	OpAMD64ROLLconst
736	OpAMD64ROLWconst
737	OpAMD64ROLBconst
738	OpAMD64ADDLload
739	OpAMD64ADDQload
740	OpAMD64SUBQload
741	OpAMD64SUBLload
742	OpAMD64ANDLload
743	OpAMD64ANDQload
744	OpAMD64ORQload
745	OpAMD64ORLload
746	OpAMD64XORQload
747	OpAMD64XORLload
748	OpAMD64ADDLloadidx1
749	OpAMD64ADDLloadidx4
750	OpAMD64ADDLloadidx8
751	OpAMD64ADDQloadidx1
752	OpAMD64ADDQloadidx8
753	OpAMD64SUBLloadidx1
754	OpAMD64SUBLloadidx4
755	OpAMD64SUBLloadidx8
756	OpAMD64SUBQloadidx1
757	OpAMD64SUBQloadidx8
758	OpAMD64ANDLloadidx1
759	OpAMD64ANDLloadidx4
760	OpAMD64ANDLloadidx8
761	OpAMD64ANDQloadidx1
762	OpAMD64ANDQloadidx8
763	OpAMD64ORLloadidx1
764	OpAMD64ORLloadidx4
765	OpAMD64ORLloadidx8
766	OpAMD64ORQloadidx1
767	OpAMD64ORQloadidx8
768	OpAMD64XORLloadidx1
769	OpAMD64XORLloadidx4
770	OpAMD64XORLloadidx8
771	OpAMD64XORQloadidx1
772	OpAMD64XORQloadidx8
773	OpAMD64ADDQmodify
774	OpAMD64SUBQmodify
775	OpAMD64ANDQmodify
776	OpAMD64ORQmodify
777	OpAMD64XORQmodify
778	OpAMD64ADDLmodify
779	OpAMD64SUBLmodify
780	OpAMD64ANDLmodify
781	OpAMD64ORLmodify
782	OpAMD64XORLmodify
783	OpAMD64ADDQmodifyidx1
784	OpAMD64ADDQmodifyidx8
785	OpAMD64SUBQmodifyidx1
786	OpAMD64SUBQmodifyidx8
787	OpAMD64ANDQmodifyidx1
788	OpAMD64ANDQmodifyidx8
789	OpAMD64ORQmodifyidx1
790	OpAMD64ORQmodifyidx8
791	OpAMD64XORQmodifyidx1
792	OpAMD64XORQmodifyidx8
793	OpAMD64ADDLmodifyidx1
794	OpAMD64ADDLmodifyidx4
795	OpAMD64ADDLmodifyidx8
796	OpAMD64SUBLmodifyidx1
797	OpAMD64SUBLmodifyidx4
798	OpAMD64SUBLmodifyidx8
799	OpAMD64ANDLmodifyidx1
800	OpAMD64ANDLmodifyidx4
801	OpAMD64ANDLmodifyidx8
802	OpAMD64ORLmodifyidx1
803	OpAMD64ORLmodifyidx4
804	OpAMD64ORLmodifyidx8
805	OpAMD64XORLmodifyidx1
806	OpAMD64XORLmodifyidx4
807	OpAMD64XORLmodifyidx8
808	OpAMD64ADDQconstmodifyidx1
809	OpAMD64ADDQconstmodifyidx8
810	OpAMD64ANDQconstmodifyidx1
811	OpAMD64ANDQconstmodifyidx8
812	OpAMD64ORQconstmodifyidx1
813	OpAMD64ORQconstmodifyidx8
814	OpAMD64XORQconstmodifyidx1
815	OpAMD64XORQconstmodifyidx8
816	OpAMD64ADDLconstmodifyidx1
817	OpAMD64ADDLconstmodifyidx4
818	OpAMD64ADDLconstmodifyidx8
819	OpAMD64ANDLconstmodifyidx1
820	OpAMD64ANDLconstmodifyidx4
821	OpAMD64ANDLconstmodifyidx8
822	OpAMD64ORLconstmodifyidx1
823	OpAMD64ORLconstmodifyidx4
824	OpAMD64ORLconstmodifyidx8
825	OpAMD64XORLconstmodifyidx1
826	OpAMD64XORLconstmodifyidx4
827	OpAMD64XORLconstmodifyidx8
828	OpAMD64NEGQ
829	OpAMD64NEGL
830	OpAMD64NOTQ
831	OpAMD64NOTL
832	OpAMD64BSFQ
833	OpAMD64BSFL
834	OpAMD64BSRQ
835	OpAMD64BSRL
836	OpAMD64CMOVQEQ
837	OpAMD64CMOVQNE
838	OpAMD64CMOVQLT
839	OpAMD64CMOVQGT
840	OpAMD64CMOVQLE
841	OpAMD64CMOVQGE
842	OpAMD64CMOVQLS
843	OpAMD64CMOVQHI
844	OpAMD64CMOVQCC
845	OpAMD64CMOVQCS
846	OpAMD64CMOVLEQ
847	OpAMD64CMOVLNE
848	OpAMD64CMOVLLT
849	OpAMD64CMOVLGT
850	OpAMD64CMOVLLE
851	OpAMD64CMOVLGE
852	OpAMD64CMOVLLS
853	OpAMD64CMOVLHI
854	OpAMD64CMOVLCC
855	OpAMD64CMOVLCS
856	OpAMD64CMOVWEQ
857	OpAMD64CMOVWNE
858	OpAMD64CMOVWLT
859	OpAMD64CMOVWGT
860	OpAMD64CMOVWLE
861	OpAMD64CMOVWGE
862	OpAMD64CMOVWLS
863	OpAMD64CMOVWHI
864	OpAMD64CMOVWCC
865	OpAMD64CMOVWCS
866	OpAMD64CMOVQEQF
867	OpAMD64CMOVQNEF
868	OpAMD64CMOVQGTF
869	OpAMD64CMOVQGEF
870	OpAMD64CMOVLEQF
871	OpAMD64CMOVLNEF
872	OpAMD64CMOVLGTF
873	OpAMD64CMOVLGEF
874	OpAMD64CMOVWEQF
875	OpAMD64CMOVWNEF
876	OpAMD64CMOVWGTF
877	OpAMD64CMOVWGEF
878	OpAMD64BSWAPQ
879	OpAMD64BSWAPL
880	OpAMD64POPCNTQ
881	OpAMD64POPCNTL
882	OpAMD64SQRTSD
883	OpAMD64SQRTSS
884	OpAMD64ROUNDSD
885	OpAMD64VFMADD231SD
886	OpAMD64SBBQcarrymask
887	OpAMD64SBBLcarrymask
888	OpAMD64SETEQ
889	OpAMD64SETNE
890	OpAMD64SETL
891	OpAMD64SETLE
892	OpAMD64SETG
893	OpAMD64SETGE
894	OpAMD64SETB
895	OpAMD64SETBE
896	OpAMD64SETA
897	OpAMD64SETAE
898	OpAMD64SETO
899	OpAMD64SETEQstore
900	OpAMD64SETNEstore
901	OpAMD64SETLstore
902	OpAMD64SETLEstore
903	OpAMD64SETGstore
904	OpAMD64SETGEstore
905	OpAMD64SETBstore
906	OpAMD64SETBEstore
907	OpAMD64SETAstore
908	OpAMD64SETAEstore
909	OpAMD64SETEQF
910	OpAMD64SETNEF
911	OpAMD64SETORD
912	OpAMD64SETNAN
913	OpAMD64SETGF
914	OpAMD64SETGEF
915	OpAMD64MOVBQSX
916	OpAMD64MOVBQZX
917	OpAMD64MOVWQSX
918	OpAMD64MOVWQZX
919	OpAMD64MOVLQSX
920	OpAMD64MOVLQZX
921	OpAMD64MOVLconst
922	OpAMD64MOVQconst
923	OpAMD64CVTTSD2SL
924	OpAMD64CVTTSD2SQ
925	OpAMD64CVTTSS2SL
926	OpAMD64CVTTSS2SQ
927	OpAMD64CVTSL2SS
928	OpAMD64CVTSL2SD
929	OpAMD64CVTSQ2SS
930	OpAMD64CVTSQ2SD
931	OpAMD64CVTSD2SS
932	OpAMD64CVTSS2SD
933	OpAMD64MOVQi2f
934	OpAMD64MOVQf2i
935	OpAMD64MOVLi2f
936	OpAMD64MOVLf2i
937	OpAMD64PXOR
938	OpAMD64LEAQ
939	OpAMD64LEAL
940	OpAMD64LEAW
941	OpAMD64LEAQ1
942	OpAMD64LEAL1
943	OpAMD64LEAW1
944	OpAMD64LEAQ2
945	OpAMD64LEAL2
946	OpAMD64LEAW2
947	OpAMD64LEAQ4
948	OpAMD64LEAL4
949	OpAMD64LEAW4
950	OpAMD64LEAQ8
951	OpAMD64LEAL8
952	OpAMD64LEAW8
953	OpAMD64MOVBload
954	OpAMD64MOVBQSXload
955	OpAMD64MOVWload
956	OpAMD64MOVWQSXload
957	OpAMD64MOVLload
958	OpAMD64MOVLQSXload
959	OpAMD64MOVQload
960	OpAMD64MOVBstore
961	OpAMD64MOVWstore
962	OpAMD64MOVLstore
963	OpAMD64MOVQstore
964	OpAMD64MOVOload
965	OpAMD64MOVOstore
966	OpAMD64MOVBloadidx1
967	OpAMD64MOVWloadidx1
968	OpAMD64MOVWloadidx2
969	OpAMD64MOVLloadidx1
970	OpAMD64MOVLloadidx4
971	OpAMD64MOVLloadidx8
972	OpAMD64MOVQloadidx1
973	OpAMD64MOVQloadidx8
974	OpAMD64MOVBstoreidx1
975	OpAMD64MOVWstoreidx1
976	OpAMD64MOVWstoreidx2
977	OpAMD64MOVLstoreidx1
978	OpAMD64MOVLstoreidx4
979	OpAMD64MOVLstoreidx8
980	OpAMD64MOVQstoreidx1
981	OpAMD64MOVQstoreidx8
982	OpAMD64MOVBstoreconst
983	OpAMD64MOVWstoreconst
984	OpAMD64MOVLstoreconst
985	OpAMD64MOVQstoreconst
986	OpAMD64MOVOstoreconst
987	OpAMD64MOVBstoreconstidx1
988	OpAMD64MOVWstoreconstidx1
989	OpAMD64MOVWstoreconstidx2
990	OpAMD64MOVLstoreconstidx1
991	OpAMD64MOVLstoreconstidx4
992	OpAMD64MOVQstoreconstidx1
993	OpAMD64MOVQstoreconstidx8
994	OpAMD64DUFFZERO
995	OpAMD64REPSTOSQ
996	OpAMD64CALLstatic
997	OpAMD64CALLtail
998	OpAMD64CALLclosure
999	OpAMD64CALLinter
1000	OpAMD64DUFFCOPY
1001	OpAMD64REPMOVSQ
1002	OpAMD64InvertFlags
1003	OpAMD64LoweredGetG
1004	OpAMD64LoweredGetClosurePtr
1005	OpAMD64LoweredGetCallerPC
1006	OpAMD64LoweredGetCallerSP
1007	OpAMD64LoweredNilCheck
1008	OpAMD64LoweredWB
1009	OpAMD64LoweredHasCPUFeature
1010	OpAMD64LoweredPanicBoundsA
1011	OpAMD64LoweredPanicBoundsB
1012	OpAMD64LoweredPanicBoundsC
1013	OpAMD64FlagEQ
1014	OpAMD64FlagLT_ULT
1015	OpAMD64FlagLT_UGT
1016	OpAMD64FlagGT_UGT
1017	OpAMD64FlagGT_ULT
1018	OpAMD64MOVBatomicload
1019	OpAMD64MOVLatomicload
1020	OpAMD64MOVQatomicload
1021	OpAMD64XCHGB
1022	OpAMD64XCHGL
1023	OpAMD64XCHGQ
1024	OpAMD64XADDLlock
1025	OpAMD64XADDQlock
1026	OpAMD64AddTupleFirst32
1027	OpAMD64AddTupleFirst64
1028	OpAMD64CMPXCHGLlock
1029	OpAMD64CMPXCHGQlock
1030	OpAMD64ANDBlock
1031	OpAMD64ANDLlock
1032	OpAMD64ORBlock
1033	OpAMD64ORLlock
1034	OpAMD64PrefetchT0
1035	OpAMD64PrefetchNTA
1036	OpAMD64ANDNQ
1037	OpAMD64ANDNL
1038	OpAMD64BLSIQ
1039	OpAMD64BLSIL
1040	OpAMD64BLSMSKQ
1041	OpAMD64BLSMSKL
1042	OpAMD64BLSRQ
1043	OpAMD64BLSRL
1044	OpAMD64TZCNTQ
1045	OpAMD64TZCNTL
1046	OpAMD64MOVBELload
1047	OpAMD64MOVBELstore
1048	OpAMD64MOVBEQload
1049	OpAMD64MOVBEQstore
1050
1051	OpARMADD
1052	OpARMADDconst
1053	OpARMSUB
1054	OpARMSUBconst
1055	OpARMRSB
1056	OpARMRSBconst
1057	OpARMMUL
1058	OpARMHMUL
1059	OpARMHMULU
1060	OpARMCALLudiv
1061	OpARMADDS
1062	OpARMADDSconst
1063	OpARMADC
1064	OpARMADCconst
1065	OpARMSUBS
1066	OpARMSUBSconst
1067	OpARMRSBSconst
1068	OpARMSBC
1069	OpARMSBCconst
1070	OpARMRSCconst
1071	OpARMMULLU
1072	OpARMMULA
1073	OpARMMULS
1074	OpARMADDF
1075	OpARMADDD
1076	OpARMSUBF
1077	OpARMSUBD
1078	OpARMMULF
1079	OpARMMULD
1080	OpARMNMULF
1081	OpARMNMULD
1082	OpARMDIVF
1083	OpARMDIVD
1084	OpARMMULAF
1085	OpARMMULAD
1086	OpARMMULSF
1087	OpARMMULSD
1088	OpARMFMULAD
1089	OpARMAND
1090	OpARMANDconst
1091	OpARMOR
1092	OpARMORconst
1093	OpARMXOR
1094	OpARMXORconst
1095	OpARMBIC
1096	OpARMBICconst
1097	OpARMBFX
1098	OpARMBFXU
1099	OpARMMVN
1100	OpARMNEGF
1101	OpARMNEGD
1102	OpARMSQRTD
1103	OpARMSQRTF
1104	OpARMABSD
1105	OpARMCLZ
1106	OpARMREV
1107	OpARMREV16
1108	OpARMRBIT
1109	OpARMSLL
1110	OpARMSLLconst
1111	OpARMSRL
1112	OpARMSRLconst
1113	OpARMSRA
1114	OpARMSRAconst
1115	OpARMSRR
1116	OpARMSRRconst
1117	OpARMADDshiftLL
1118	OpARMADDshiftRL
1119	OpARMADDshiftRA
1120	OpARMSUBshiftLL
1121	OpARMSUBshiftRL
1122	OpARMSUBshiftRA
1123	OpARMRSBshiftLL
1124	OpARMRSBshiftRL
1125	OpARMRSBshiftRA
1126	OpARMANDshiftLL
1127	OpARMANDshiftRL
1128	OpARMANDshiftRA
1129	OpARMORshiftLL
1130	OpARMORshiftRL
1131	OpARMORshiftRA
1132	OpARMXORshiftLL
1133	OpARMXORshiftRL
1134	OpARMXORshiftRA
1135	OpARMXORshiftRR
1136	OpARMBICshiftLL
1137	OpARMBICshiftRL
1138	OpARMBICshiftRA
1139	OpARMMVNshiftLL
1140	OpARMMVNshiftRL
1141	OpARMMVNshiftRA
1142	OpARMADCshiftLL
1143	OpARMADCshiftRL
1144	OpARMADCshiftRA
1145	OpARMSBCshiftLL
1146	OpARMSBCshiftRL
1147	OpARMSBCshiftRA
1148	OpARMRSCshiftLL
1149	OpARMRSCshiftRL
1150	OpARMRSCshiftRA
1151	OpARMADDSshiftLL
1152	OpARMADDSshiftRL
1153	OpARMADDSshiftRA
1154	OpARMSUBSshiftLL
1155	OpARMSUBSshiftRL
1156	OpARMSUBSshiftRA
1157	OpARMRSBSshiftLL
1158	OpARMRSBSshiftRL
1159	OpARMRSBSshiftRA
1160	OpARMADDshiftLLreg
1161	OpARMADDshiftRLreg
1162	OpARMADDshiftRAreg
1163	OpARMSUBshiftLLreg
1164	OpARMSUBshiftRLreg
1165	OpARMSUBshiftRAreg
1166	OpARMRSBshiftLLreg
1167	OpARMRSBshiftRLreg
1168	OpARMRSBshiftRAreg
1169	OpARMANDshiftLLreg
1170	OpARMANDshiftRLreg
1171	OpARMANDshiftRAreg
1172	OpARMORshiftLLreg
1173	OpARMORshiftRLreg
1174	OpARMORshiftRAreg
1175	OpARMXORshiftLLreg
1176	OpARMXORshiftRLreg
1177	OpARMXORshiftRAreg
1178	OpARMBICshiftLLreg
1179	OpARMBICshiftRLreg
1180	OpARMBICshiftRAreg
1181	OpARMMVNshiftLLreg
1182	OpARMMVNshiftRLreg
1183	OpARMMVNshiftRAreg
1184	OpARMADCshiftLLreg
1185	OpARMADCshiftRLreg
1186	OpARMADCshiftRAreg
1187	OpARMSBCshiftLLreg
1188	OpARMSBCshiftRLreg
1189	OpARMSBCshiftRAreg
1190	OpARMRSCshiftLLreg
1191	OpARMRSCshiftRLreg
1192	OpARMRSCshiftRAreg
1193	OpARMADDSshiftLLreg
1194	OpARMADDSshiftRLreg
1195	OpARMADDSshiftRAreg
1196	OpARMSUBSshiftLLreg
1197	OpARMSUBSshiftRLreg
1198	OpARMSUBSshiftRAreg
1199	OpARMRSBSshiftLLreg
1200	OpARMRSBSshiftRLreg
1201	OpARMRSBSshiftRAreg
1202	OpARMCMP
1203	OpARMCMPconst
1204	OpARMCMN
1205	OpARMCMNconst
1206	OpARMTST
1207	OpARMTSTconst
1208	OpARMTEQ
1209	OpARMTEQconst
1210	OpARMCMPF
1211	OpARMCMPD
1212	OpARMCMPshiftLL
1213	OpARMCMPshiftRL
1214	OpARMCMPshiftRA
1215	OpARMCMNshiftLL
1216	OpARMCMNshiftRL
1217	OpARMCMNshiftRA
1218	OpARMTSTshiftLL
1219	OpARMTSTshiftRL
1220	OpARMTSTshiftRA
1221	OpARMTEQshiftLL
1222	OpARMTEQshiftRL
1223	OpARMTEQshiftRA
1224	OpARMCMPshiftLLreg
1225	OpARMCMPshiftRLreg
1226	OpARMCMPshiftRAreg
1227	OpARMCMNshiftLLreg
1228	OpARMCMNshiftRLreg
1229	OpARMCMNshiftRAreg
1230	OpARMTSTshiftLLreg
1231	OpARMTSTshiftRLreg
1232	OpARMTSTshiftRAreg
1233	OpARMTEQshiftLLreg
1234	OpARMTEQshiftRLreg
1235	OpARMTEQshiftRAreg
1236	OpARMCMPF0
1237	OpARMCMPD0
1238	OpARMMOVWconst
1239	OpARMMOVFconst
1240	OpARMMOVDconst
1241	OpARMMOVWaddr
1242	OpARMMOVBload
1243	OpARMMOVBUload
1244	OpARMMOVHload
1245	OpARMMOVHUload
1246	OpARMMOVWload
1247	OpARMMOVFload
1248	OpARMMOVDload
1249	OpARMMOVBstore
1250	OpARMMOVHstore
1251	OpARMMOVWstore
1252	OpARMMOVFstore
1253	OpARMMOVDstore
1254	OpARMMOVWloadidx
1255	OpARMMOVWloadshiftLL
1256	OpARMMOVWloadshiftRL
1257	OpARMMOVWloadshiftRA
1258	OpARMMOVBUloadidx
1259	OpARMMOVBloadidx
1260	OpARMMOVHUloadidx
1261	OpARMMOVHloadidx
1262	OpARMMOVWstoreidx
1263	OpARMMOVWstoreshiftLL
1264	OpARMMOVWstoreshiftRL
1265	OpARMMOVWstoreshiftRA
1266	OpARMMOVBstoreidx
1267	OpARMMOVHstoreidx
1268	OpARMMOVBreg
1269	OpARMMOVBUreg
1270	OpARMMOVHreg
1271	OpARMMOVHUreg
1272	OpARMMOVWreg
1273	OpARMMOVWnop
1274	OpARMMOVWF
1275	OpARMMOVWD
1276	OpARMMOVWUF
1277	OpARMMOVWUD
1278	OpARMMOVFW
1279	OpARMMOVDW
1280	OpARMMOVFWU
1281	OpARMMOVDWU
1282	OpARMMOVFD
1283	OpARMMOVDF
1284	OpARMCMOVWHSconst
1285	OpARMCMOVWLSconst
1286	OpARMSRAcond
1287	OpARMCALLstatic
1288	OpARMCALLtail
1289	OpARMCALLclosure
1290	OpARMCALLinter
1291	OpARMLoweredNilCheck
1292	OpARMEqual
1293	OpARMNotEqual
1294	OpARMLessThan
1295	OpARMLessEqual
1296	OpARMGreaterThan
1297	OpARMGreaterEqual
1298	OpARMLessThanU
1299	OpARMLessEqualU
1300	OpARMGreaterThanU
1301	OpARMGreaterEqualU
1302	OpARMDUFFZERO
1303	OpARMDUFFCOPY
1304	OpARMLoweredZero
1305	OpARMLoweredMove
1306	OpARMLoweredGetClosurePtr
1307	OpARMLoweredGetCallerSP
1308	OpARMLoweredGetCallerPC
1309	OpARMLoweredPanicBoundsA
1310	OpARMLoweredPanicBoundsB
1311	OpARMLoweredPanicBoundsC
1312	OpARMLoweredPanicExtendA
1313	OpARMLoweredPanicExtendB
1314	OpARMLoweredPanicExtendC
1315	OpARMFlagConstant
1316	OpARMInvertFlags
1317	OpARMLoweredWB
1318
1319	OpARM64ADCSflags
1320	OpARM64ADCzerocarry
1321	OpARM64ADD
1322	OpARM64ADDconst
1323	OpARM64ADDSconstflags
1324	OpARM64ADDSflags
1325	OpARM64SUB
1326	OpARM64SUBconst
1327	OpARM64SBCSflags
1328	OpARM64SUBSflags
1329	OpARM64MUL
1330	OpARM64MULW
1331	OpARM64MNEG
1332	OpARM64MNEGW
1333	OpARM64MULH
1334	OpARM64UMULH
1335	OpARM64MULL
1336	OpARM64UMULL
1337	OpARM64DIV
1338	OpARM64UDIV
1339	OpARM64DIVW
1340	OpARM64UDIVW
1341	OpARM64MOD
1342	OpARM64UMOD
1343	OpARM64MODW
1344	OpARM64UMODW
1345	OpARM64FADDS
1346	OpARM64FADDD
1347	OpARM64FSUBS
1348	OpARM64FSUBD
1349	OpARM64FMULS
1350	OpARM64FMULD
1351	OpARM64FNMULS
1352	OpARM64FNMULD
1353	OpARM64FDIVS
1354	OpARM64FDIVD
1355	OpARM64AND
1356	OpARM64ANDconst
1357	OpARM64OR
1358	OpARM64ORconst
1359	OpARM64XOR
1360	OpARM64XORconst
1361	OpARM64BIC
1362	OpARM64EON
1363	OpARM64ORN
1364	OpARM64LoweredMuluhilo
1365	OpARM64MVN
1366	OpARM64NEG
1367	OpARM64NEGSflags
1368	OpARM64NGCzerocarry
1369	OpARM64FABSD
1370	OpARM64FNEGS
1371	OpARM64FNEGD
1372	OpARM64FSQRTD
1373	OpARM64FSQRTS
1374	OpARM64REV
1375	OpARM64REVW
1376	OpARM64REV16
1377	OpARM64REV16W
1378	OpARM64RBIT
1379	OpARM64RBITW
1380	OpARM64CLZ
1381	OpARM64CLZW
1382	OpARM64VCNT
1383	OpARM64VUADDLV
1384	OpARM64LoweredRound32F
1385	OpARM64LoweredRound64F
1386	OpARM64FMADDS
1387	OpARM64FMADDD
1388	OpARM64FNMADDS
1389	OpARM64FNMADDD
1390	OpARM64FMSUBS
1391	OpARM64FMSUBD
1392	OpARM64FNMSUBS
1393	OpARM64FNMSUBD
1394	OpARM64MADD
1395	OpARM64MADDW
1396	OpARM64MSUB
1397	OpARM64MSUBW
1398	OpARM64SLL
1399	OpARM64SLLconst
1400	OpARM64SRL
1401	OpARM64SRLconst
1402	OpARM64SRA
1403	OpARM64SRAconst
1404	OpARM64ROR
1405	OpARM64RORW
1406	OpARM64RORconst
1407	OpARM64RORWconst
1408	OpARM64EXTRconst
1409	OpARM64EXTRWconst
1410	OpARM64CMP
1411	OpARM64CMPconst
1412	OpARM64CMPW
1413	OpARM64CMPWconst
1414	OpARM64CMN
1415	OpARM64CMNconst
1416	OpARM64CMNW
1417	OpARM64CMNWconst
1418	OpARM64TST
1419	OpARM64TSTconst
1420	OpARM64TSTW
1421	OpARM64TSTWconst
1422	OpARM64FCMPS
1423	OpARM64FCMPD
1424	OpARM64FCMPS0
1425	OpARM64FCMPD0
1426	OpARM64MVNshiftLL
1427	OpARM64MVNshiftRL
1428	OpARM64MVNshiftRA
1429	OpARM64MVNshiftRO
1430	OpARM64NEGshiftLL
1431	OpARM64NEGshiftRL
1432	OpARM64NEGshiftRA
1433	OpARM64ADDshiftLL
1434	OpARM64ADDshiftRL
1435	OpARM64ADDshiftRA
1436	OpARM64SUBshiftLL
1437	OpARM64SUBshiftRL
1438	OpARM64SUBshiftRA
1439	OpARM64ANDshiftLL
1440	OpARM64ANDshiftRL
1441	OpARM64ANDshiftRA
1442	OpARM64ANDshiftRO
1443	OpARM64ORshiftLL
1444	OpARM64ORshiftRL
1445	OpARM64ORshiftRA
1446	OpARM64ORshiftRO
1447	OpARM64XORshiftLL
1448	OpARM64XORshiftRL
1449	OpARM64XORshiftRA
1450	OpARM64XORshiftRO
1451	OpARM64BICshiftLL
1452	OpARM64BICshiftRL
1453	OpARM64BICshiftRA
1454	OpARM64BICshiftRO
1455	OpARM64EONshiftLL
1456	OpARM64EONshiftRL
1457	OpARM64EONshiftRA
1458	OpARM64EONshiftRO
1459	OpARM64ORNshiftLL
1460	OpARM64ORNshiftRL
1461	OpARM64ORNshiftRA
1462	OpARM64ORNshiftRO
1463	OpARM64CMPshiftLL
1464	OpARM64CMPshiftRL
1465	OpARM64CMPshiftRA
1466	OpARM64CMNshiftLL
1467	OpARM64CMNshiftRL
1468	OpARM64CMNshiftRA
1469	OpARM64TSTshiftLL
1470	OpARM64TSTshiftRL
1471	OpARM64TSTshiftRA
1472	OpARM64TSTshiftRO
1473	OpARM64BFI
1474	OpARM64BFXIL
1475	OpARM64SBFIZ
1476	OpARM64SBFX
1477	OpARM64UBFIZ
1478	OpARM64UBFX
1479	OpARM64MOVDconst
1480	OpARM64FMOVSconst
1481	OpARM64FMOVDconst
1482	OpARM64MOVDaddr
1483	OpARM64MOVBload
1484	OpARM64MOVBUload
1485	OpARM64MOVHload
1486	OpARM64MOVHUload
1487	OpARM64MOVWload
1488	OpARM64MOVWUload
1489	OpARM64MOVDload
1490	OpARM64FMOVSload
1491	OpARM64FMOVDload
1492	OpARM64MOVDloadidx
1493	OpARM64MOVWloadidx
1494	OpARM64MOVWUloadidx
1495	OpARM64MOVHloadidx
1496	OpARM64MOVHUloadidx
1497	OpARM64MOVBloadidx
1498	OpARM64MOVBUloadidx
1499	OpARM64FMOVSloadidx
1500	OpARM64FMOVDloadidx
1501	OpARM64MOVHloadidx2
1502	OpARM64MOVHUloadidx2
1503	OpARM64MOVWloadidx4
1504	OpARM64MOVWUloadidx4
1505	OpARM64MOVDloadidx8
1506	OpARM64FMOVSloadidx4
1507	OpARM64FMOVDloadidx8
1508	OpARM64MOVBstore
1509	OpARM64MOVHstore
1510	OpARM64MOVWstore
1511	OpARM64MOVDstore
1512	OpARM64STP
1513	OpARM64FMOVSstore
1514	OpARM64FMOVDstore
1515	OpARM64MOVBstoreidx
1516	OpARM64MOVHstoreidx
1517	OpARM64MOVWstoreidx
1518	OpARM64MOVDstoreidx
1519	OpARM64FMOVSstoreidx
1520	OpARM64FMOVDstoreidx
1521	OpARM64MOVHstoreidx2
1522	OpARM64MOVWstoreidx4
1523	OpARM64MOVDstoreidx8
1524	OpARM64FMOVSstoreidx4
1525	OpARM64FMOVDstoreidx8
1526	OpARM64MOVBstorezero
1527	OpARM64MOVHstorezero
1528	OpARM64MOVWstorezero
1529	OpARM64MOVDstorezero
1530	OpARM64MOVQstorezero
1531	OpARM64MOVBstorezeroidx
1532	OpARM64MOVHstorezeroidx
1533	OpARM64MOVWstorezeroidx
1534	OpARM64MOVDstorezeroidx
1535	OpARM64MOVHstorezeroidx2
1536	OpARM64MOVWstorezeroidx4
1537	OpARM64MOVDstorezeroidx8
1538	OpARM64FMOVDgpfp
1539	OpARM64FMOVDfpgp
1540	OpARM64FMOVSgpfp
1541	OpARM64FMOVSfpgp
1542	OpARM64MOVBreg
1543	OpARM64MOVBUreg
1544	OpARM64MOVHreg
1545	OpARM64MOVHUreg
1546	OpARM64MOVWreg
1547	OpARM64MOVWUreg
1548	OpARM64MOVDreg
1549	OpARM64MOVDnop
1550	OpARM64SCVTFWS
1551	OpARM64SCVTFWD
1552	OpARM64UCVTFWS
1553	OpARM64UCVTFWD
1554	OpARM64SCVTFS
1555	OpARM64SCVTFD
1556	OpARM64UCVTFS
1557	OpARM64UCVTFD
1558	OpARM64FCVTZSSW
1559	OpARM64FCVTZSDW
1560	OpARM64FCVTZUSW
1561	OpARM64FCVTZUDW
1562	OpARM64FCVTZSS
1563	OpARM64FCVTZSD
1564	OpARM64FCVTZUS
1565	OpARM64FCVTZUD
1566	OpARM64FCVTSD
1567	OpARM64FCVTDS
1568	OpARM64FRINTAD
1569	OpARM64FRINTMD
1570	OpARM64FRINTND
1571	OpARM64FRINTPD
1572	OpARM64FRINTZD
1573	OpARM64CSEL
1574	OpARM64CSEL0
1575	OpARM64CSINC
1576	OpARM64CSINV
1577	OpARM64CSNEG
1578	OpARM64CSETM
1579	OpARM64CALLstatic
1580	OpARM64CALLtail
1581	OpARM64CALLclosure
1582	OpARM64CALLinter
1583	OpARM64LoweredNilCheck
1584	OpARM64Equal
1585	OpARM64NotEqual
1586	OpARM64LessThan
1587	OpARM64LessEqual
1588	OpARM64GreaterThan
1589	OpARM64GreaterEqual
1590	OpARM64LessThanU
1591	OpARM64LessEqualU
1592	OpARM64GreaterThanU
1593	OpARM64GreaterEqualU
1594	OpARM64LessThanF
1595	OpARM64LessEqualF
1596	OpARM64GreaterThanF
1597	OpARM64GreaterEqualF
1598	OpARM64NotLessThanF
1599	OpARM64NotLessEqualF
1600	OpARM64NotGreaterThanF
1601	OpARM64NotGreaterEqualF
1602	OpARM64DUFFZERO
1603	OpARM64LoweredZero
1604	OpARM64DUFFCOPY
1605	OpARM64LoweredMove
1606	OpARM64LoweredGetClosurePtr
1607	OpARM64LoweredGetCallerSP
1608	OpARM64LoweredGetCallerPC
1609	OpARM64FlagConstant
1610	OpARM64InvertFlags
1611	OpARM64LDAR
1612	OpARM64LDARB
1613	OpARM64LDARW
1614	OpARM64STLRB
1615	OpARM64STLR
1616	OpARM64STLRW
1617	OpARM64LoweredAtomicExchange64
1618	OpARM64LoweredAtomicExchange32
1619	OpARM64LoweredAtomicExchange64Variant
1620	OpARM64LoweredAtomicExchange32Variant
1621	OpARM64LoweredAtomicAdd64
1622	OpARM64LoweredAtomicAdd32
1623	OpARM64LoweredAtomicAdd64Variant
1624	OpARM64LoweredAtomicAdd32Variant
1625	OpARM64LoweredAtomicCas64
1626	OpARM64LoweredAtomicCas32
1627	OpARM64LoweredAtomicCas64Variant
1628	OpARM64LoweredAtomicCas32Variant
1629	OpARM64LoweredAtomicAnd8
1630	OpARM64LoweredAtomicAnd32
1631	OpARM64LoweredAtomicOr8
1632	OpARM64LoweredAtomicOr32
1633	OpARM64LoweredAtomicAnd8Variant
1634	OpARM64LoweredAtomicAnd32Variant
1635	OpARM64LoweredAtomicOr8Variant
1636	OpARM64LoweredAtomicOr32Variant
1637	OpARM64LoweredWB
1638	OpARM64LoweredPanicBoundsA
1639	OpARM64LoweredPanicBoundsB
1640	OpARM64LoweredPanicBoundsC
1641	OpARM64PRFM
1642	OpARM64DMB
1643
1644	OpMIPSADD
1645	OpMIPSADDconst
1646	OpMIPSSUB
1647	OpMIPSSUBconst
1648	OpMIPSMUL
1649	OpMIPSMULT
1650	OpMIPSMULTU
1651	OpMIPSDIV
1652	OpMIPSDIVU
1653	OpMIPSADDF
1654	OpMIPSADDD
1655	OpMIPSSUBF
1656	OpMIPSSUBD
1657	OpMIPSMULF
1658	OpMIPSMULD
1659	OpMIPSDIVF
1660	OpMIPSDIVD
1661	OpMIPSAND
1662	OpMIPSANDconst
1663	OpMIPSOR
1664	OpMIPSORconst
1665	OpMIPSXOR
1666	OpMIPSXORconst
1667	OpMIPSNOR
1668	OpMIPSNORconst
1669	OpMIPSNEG
1670	OpMIPSNEGF
1671	OpMIPSNEGD
1672	OpMIPSSQRTD
1673	OpMIPSSQRTF
1674	OpMIPSSLL
1675	OpMIPSSLLconst
1676	OpMIPSSRL
1677	OpMIPSSRLconst
1678	OpMIPSSRA
1679	OpMIPSSRAconst
1680	OpMIPSCLZ
1681	OpMIPSSGT
1682	OpMIPSSGTconst
1683	OpMIPSSGTzero
1684	OpMIPSSGTU
1685	OpMIPSSGTUconst
1686	OpMIPSSGTUzero
1687	OpMIPSCMPEQF
1688	OpMIPSCMPEQD
1689	OpMIPSCMPGEF
1690	OpMIPSCMPGED
1691	OpMIPSCMPGTF
1692	OpMIPSCMPGTD
1693	OpMIPSMOVWconst
1694	OpMIPSMOVFconst
1695	OpMIPSMOVDconst
1696	OpMIPSMOVWaddr
1697	OpMIPSMOVBload
1698	OpMIPSMOVBUload
1699	OpMIPSMOVHload
1700	OpMIPSMOVHUload
1701	OpMIPSMOVWload
1702	OpMIPSMOVFload
1703	OpMIPSMOVDload
1704	OpMIPSMOVBstore
1705	OpMIPSMOVHstore
1706	OpMIPSMOVWstore
1707	OpMIPSMOVFstore
1708	OpMIPSMOVDstore
1709	OpMIPSMOVBstorezero
1710	OpMIPSMOVHstorezero
1711	OpMIPSMOVWstorezero
1712	OpMIPSMOVBreg
1713	OpMIPSMOVBUreg
1714	OpMIPSMOVHreg
1715	OpMIPSMOVHUreg
1716	OpMIPSMOVWreg
1717	OpMIPSMOVWnop
1718	OpMIPSCMOVZ
1719	OpMIPSCMOVZzero
1720	OpMIPSMOVWF
1721	OpMIPSMOVWD
1722	OpMIPSTRUNCFW
1723	OpMIPSTRUNCDW
1724	OpMIPSMOVFD
1725	OpMIPSMOVDF
1726	OpMIPSCALLstatic
1727	OpMIPSCALLtail
1728	OpMIPSCALLclosure
1729	OpMIPSCALLinter
1730	OpMIPSLoweredAtomicLoad8
1731	OpMIPSLoweredAtomicLoad32
1732	OpMIPSLoweredAtomicStore8
1733	OpMIPSLoweredAtomicStore32
1734	OpMIPSLoweredAtomicStorezero
1735	OpMIPSLoweredAtomicExchange
1736	OpMIPSLoweredAtomicAdd
1737	OpMIPSLoweredAtomicAddconst
1738	OpMIPSLoweredAtomicCas
1739	OpMIPSLoweredAtomicAnd
1740	OpMIPSLoweredAtomicOr
1741	OpMIPSLoweredZero
1742	OpMIPSLoweredMove
1743	OpMIPSLoweredNilCheck
1744	OpMIPSFPFlagTrue
1745	OpMIPSFPFlagFalse
1746	OpMIPSLoweredGetClosurePtr
1747	OpMIPSLoweredGetCallerSP
1748	OpMIPSLoweredGetCallerPC
1749	OpMIPSLoweredWB
1750	OpMIPSLoweredPanicBoundsA
1751	OpMIPSLoweredPanicBoundsB
1752	OpMIPSLoweredPanicBoundsC
1753	OpMIPSLoweredPanicExtendA
1754	OpMIPSLoweredPanicExtendB
1755	OpMIPSLoweredPanicExtendC
1756
1757	OpMIPS64ADDV
1758	OpMIPS64ADDVconst
1759	OpMIPS64SUBV
1760	OpMIPS64SUBVconst
1761	OpMIPS64MULV
1762	OpMIPS64MULVU
1763	OpMIPS64DIVV
1764	OpMIPS64DIVVU
1765	OpMIPS64ADDF
1766	OpMIPS64ADDD
1767	OpMIPS64SUBF
1768	OpMIPS64SUBD
1769	OpMIPS64MULF
1770	OpMIPS64MULD
1771	OpMIPS64DIVF
1772	OpMIPS64DIVD
1773	OpMIPS64AND
1774	OpMIPS64ANDconst
1775	OpMIPS64OR
1776	OpMIPS64ORconst
1777	OpMIPS64XOR
1778	OpMIPS64XORconst
1779	OpMIPS64NOR
1780	OpMIPS64NORconst
1781	OpMIPS64NEGV
1782	OpMIPS64NEGF
1783	OpMIPS64NEGD
1784	OpMIPS64SQRTD
1785	OpMIPS64SQRTF
1786	OpMIPS64SLLV
1787	OpMIPS64SLLVconst
1788	OpMIPS64SRLV
1789	OpMIPS64SRLVconst
1790	OpMIPS64SRAV
1791	OpMIPS64SRAVconst
1792	OpMIPS64SGT
1793	OpMIPS64SGTconst
1794	OpMIPS64SGTU
1795	OpMIPS64SGTUconst
1796	OpMIPS64CMPEQF
1797	OpMIPS64CMPEQD
1798	OpMIPS64CMPGEF
1799	OpMIPS64CMPGED
1800	OpMIPS64CMPGTF
1801	OpMIPS64CMPGTD
1802	OpMIPS64MOVVconst
1803	OpMIPS64MOVFconst
1804	OpMIPS64MOVDconst
1805	OpMIPS64MOVVaddr
1806	OpMIPS64MOVBload
1807	OpMIPS64MOVBUload
1808	OpMIPS64MOVHload
1809	OpMIPS64MOVHUload
1810	OpMIPS64MOVWload
1811	OpMIPS64MOVWUload
1812	OpMIPS64MOVVload
1813	OpMIPS64MOVFload
1814	OpMIPS64MOVDload
1815	OpMIPS64MOVBstore
1816	OpMIPS64MOVHstore
1817	OpMIPS64MOVWstore
1818	OpMIPS64MOVVstore
1819	OpMIPS64MOVFstore
1820	OpMIPS64MOVDstore
1821	OpMIPS64MOVBstorezero
1822	OpMIPS64MOVHstorezero
1823	OpMIPS64MOVWstorezero
1824	OpMIPS64MOVVstorezero
1825	OpMIPS64MOVBreg
1826	OpMIPS64MOVBUreg
1827	OpMIPS64MOVHreg
1828	OpMIPS64MOVHUreg
1829	OpMIPS64MOVWreg
1830	OpMIPS64MOVWUreg
1831	OpMIPS64MOVVreg
1832	OpMIPS64MOVVnop
1833	OpMIPS64MOVWF
1834	OpMIPS64MOVWD
1835	OpMIPS64MOVVF
1836	OpMIPS64MOVVD
1837	OpMIPS64TRUNCFW
1838	OpMIPS64TRUNCDW
1839	OpMIPS64TRUNCFV
1840	OpMIPS64TRUNCDV
1841	OpMIPS64MOVFD
1842	OpMIPS64MOVDF
1843	OpMIPS64CALLstatic
1844	OpMIPS64CALLtail
1845	OpMIPS64CALLclosure
1846	OpMIPS64CALLinter
1847	OpMIPS64DUFFZERO
1848	OpMIPS64DUFFCOPY
1849	OpMIPS64LoweredZero
1850	OpMIPS64LoweredMove
1851	OpMIPS64LoweredAtomicLoad8
1852	OpMIPS64LoweredAtomicLoad32
1853	OpMIPS64LoweredAtomicLoad64
1854	OpMIPS64LoweredAtomicStore8
1855	OpMIPS64LoweredAtomicStore32
1856	OpMIPS64LoweredAtomicStore64
1857	OpMIPS64LoweredAtomicStorezero32
1858	OpMIPS64LoweredAtomicStorezero64
1859	OpMIPS64LoweredAtomicExchange32
1860	OpMIPS64LoweredAtomicExchange64
1861	OpMIPS64LoweredAtomicAdd32
1862	OpMIPS64LoweredAtomicAdd64
1863	OpMIPS64LoweredAtomicAddconst32
1864	OpMIPS64LoweredAtomicAddconst64
1865	OpMIPS64LoweredAtomicCas32
1866	OpMIPS64LoweredAtomicCas64
1867	OpMIPS64LoweredNilCheck
1868	OpMIPS64FPFlagTrue
1869	OpMIPS64FPFlagFalse
1870	OpMIPS64LoweredGetClosurePtr
1871	OpMIPS64LoweredGetCallerSP
1872	OpMIPS64LoweredGetCallerPC
1873	OpMIPS64LoweredWB
1874	OpMIPS64LoweredPanicBoundsA
1875	OpMIPS64LoweredPanicBoundsB
1876	OpMIPS64LoweredPanicBoundsC
1877
1878	OpPPC64ADD
1879	OpPPC64ADDconst
1880	OpPPC64FADD
1881	OpPPC64FADDS
1882	OpPPC64SUB
1883	OpPPC64SUBFCconst
1884	OpPPC64FSUB
1885	OpPPC64FSUBS
1886	OpPPC64MULLD
1887	OpPPC64MULLW
1888	OpPPC64MULLDconst
1889	OpPPC64MULLWconst
1890	OpPPC64MADDLD
1891	OpPPC64MULHD
1892	OpPPC64MULHW
1893	OpPPC64MULHDU
1894	OpPPC64MULHWU
1895	OpPPC64LoweredMuluhilo
1896	OpPPC64FMUL
1897	OpPPC64FMULS
1898	OpPPC64FMADD
1899	OpPPC64FMADDS
1900	OpPPC64FMSUB
1901	OpPPC64FMSUBS
1902	OpPPC64SRAD
1903	OpPPC64SRAW
1904	OpPPC64SRD
1905	OpPPC64SRW
1906	OpPPC64SLD
1907	OpPPC64SLW
1908	OpPPC64ROTL
1909	OpPPC64ROTLW
1910	OpPPC64RLDICL
1911	OpPPC64CLRLSLWI
1912	OpPPC64CLRLSLDI
1913	OpPPC64LoweredAdd64Carry
1914	OpPPC64SRADconst
1915	OpPPC64SRAWconst
1916	OpPPC64SRDconst
1917	OpPPC64SRWconst
1918	OpPPC64SLDconst
1919	OpPPC64SLWconst
1920	OpPPC64ROTLconst
1921	OpPPC64ROTLWconst
1922	OpPPC64EXTSWSLconst
1923	OpPPC64RLWINM
1924	OpPPC64RLWNM
1925	OpPPC64RLWMI
1926	OpPPC64CNTLZD
1927	OpPPC64CNTLZW
1928	OpPPC64CNTTZD
1929	OpPPC64CNTTZW
1930	OpPPC64POPCNTD
1931	OpPPC64POPCNTW
1932	OpPPC64POPCNTB
1933	OpPPC64FDIV
1934	OpPPC64FDIVS
1935	OpPPC64DIVD
1936	OpPPC64DIVW
1937	OpPPC64DIVDU
1938	OpPPC64DIVWU
1939	OpPPC64MODUD
1940	OpPPC64MODSD
1941	OpPPC64MODUW
1942	OpPPC64MODSW
1943	OpPPC64FCTIDZ
1944	OpPPC64FCTIWZ
1945	OpPPC64FCFID
1946	OpPPC64FCFIDS
1947	OpPPC64FRSP
1948	OpPPC64MFVSRD
1949	OpPPC64MTVSRD
1950	OpPPC64AND
1951	OpPPC64ANDN
1952	OpPPC64ANDCC
1953	OpPPC64OR
1954	OpPPC64ORN
1955	OpPPC64ORCC
1956	OpPPC64NOR
1957	OpPPC64XOR
1958	OpPPC64XORCC
1959	OpPPC64EQV
1960	OpPPC64NEG
1961	OpPPC64FNEG
1962	OpPPC64FSQRT
1963	OpPPC64FSQRTS
1964	OpPPC64FFLOOR
1965	OpPPC64FCEIL
1966	OpPPC64FTRUNC
1967	OpPPC64FROUND
1968	OpPPC64FABS
1969	OpPPC64FNABS
1970	OpPPC64FCPSGN
1971	OpPPC64ORconst
1972	OpPPC64XORconst
1973	OpPPC64ANDconst
1974	OpPPC64ANDCCconst
1975	OpPPC64MOVBreg
1976	OpPPC64MOVBZreg
1977	OpPPC64MOVHreg
1978	OpPPC64MOVHZreg
1979	OpPPC64MOVWreg
1980	OpPPC64MOVWZreg
1981	OpPPC64MOVBZload
1982	OpPPC64MOVHload
1983	OpPPC64MOVHZload
1984	OpPPC64MOVWload
1985	OpPPC64MOVWZload
1986	OpPPC64MOVDload
1987	OpPPC64MOVDBRload
1988	OpPPC64MOVWBRload
1989	OpPPC64MOVHBRload
1990	OpPPC64MOVBZloadidx
1991	OpPPC64MOVHloadidx
1992	OpPPC64MOVHZloadidx
1993	OpPPC64MOVWloadidx
1994	OpPPC64MOVWZloadidx
1995	OpPPC64MOVDloadidx
1996	OpPPC64MOVHBRloadidx
1997	OpPPC64MOVWBRloadidx
1998	OpPPC64MOVDBRloadidx
1999	OpPPC64FMOVDloadidx
2000	OpPPC64FMOVSloadidx
2001	OpPPC64DCBT
2002	OpPPC64MOVDBRstore
2003	OpPPC64MOVWBRstore
2004	OpPPC64MOVHBRstore
2005	OpPPC64FMOVDload
2006	OpPPC64FMOVSload
2007	OpPPC64MOVBstore
2008	OpPPC64MOVHstore
2009	OpPPC64MOVWstore
2010	OpPPC64MOVDstore
2011	OpPPC64FMOVDstore
2012	OpPPC64FMOVSstore
2013	OpPPC64MOVBstoreidx
2014	OpPPC64MOVHstoreidx
2015	OpPPC64MOVWstoreidx
2016	OpPPC64MOVDstoreidx
2017	OpPPC64FMOVDstoreidx
2018	OpPPC64FMOVSstoreidx
2019	OpPPC64MOVHBRstoreidx
2020	OpPPC64MOVWBRstoreidx
2021	OpPPC64MOVDBRstoreidx
2022	OpPPC64MOVBstorezero
2023	OpPPC64MOVHstorezero
2024	OpPPC64MOVWstorezero
2025	OpPPC64MOVDstorezero
2026	OpPPC64MOVDaddr
2027	OpPPC64MOVDconst
2028	OpPPC64FMOVDconst
2029	OpPPC64FMOVSconst
2030	OpPPC64FCMPU
2031	OpPPC64CMP
2032	OpPPC64CMPU
2033	OpPPC64CMPW
2034	OpPPC64CMPWU
2035	OpPPC64CMPconst
2036	OpPPC64CMPUconst
2037	OpPPC64CMPWconst
2038	OpPPC64CMPWUconst
2039	OpPPC64ISEL
2040	OpPPC64ISELB
2041	OpPPC64Equal
2042	OpPPC64NotEqual
2043	OpPPC64LessThan
2044	OpPPC64FLessThan
2045	OpPPC64LessEqual
2046	OpPPC64FLessEqual
2047	OpPPC64GreaterThan
2048	OpPPC64FGreaterThan
2049	OpPPC64GreaterEqual
2050	OpPPC64FGreaterEqual
2051	OpPPC64LoweredGetClosurePtr
2052	OpPPC64LoweredGetCallerSP
2053	OpPPC64LoweredGetCallerPC
2054	OpPPC64LoweredNilCheck
2055	OpPPC64LoweredRound32F
2056	OpPPC64LoweredRound64F
2057	OpPPC64CALLstatic
2058	OpPPC64CALLtail
2059	OpPPC64CALLclosure
2060	OpPPC64CALLinter
2061	OpPPC64LoweredZero
2062	OpPPC64LoweredZeroShort
2063	OpPPC64LoweredQuadZeroShort
2064	OpPPC64LoweredQuadZero
2065	OpPPC64LoweredMove
2066	OpPPC64LoweredMoveShort
2067	OpPPC64LoweredQuadMove
2068	OpPPC64LoweredQuadMoveShort
2069	OpPPC64LoweredAtomicStore8
2070	OpPPC64LoweredAtomicStore32
2071	OpPPC64LoweredAtomicStore64
2072	OpPPC64LoweredAtomicLoad8
2073	OpPPC64LoweredAtomicLoad32
2074	OpPPC64LoweredAtomicLoad64
2075	OpPPC64LoweredAtomicLoadPtr
2076	OpPPC64LoweredAtomicAdd32
2077	OpPPC64LoweredAtomicAdd64
2078	OpPPC64LoweredAtomicExchange32
2079	OpPPC64LoweredAtomicExchange64
2080	OpPPC64LoweredAtomicCas64
2081	OpPPC64LoweredAtomicCas32
2082	OpPPC64LoweredAtomicAnd8
2083	OpPPC64LoweredAtomicAnd32
2084	OpPPC64LoweredAtomicOr8
2085	OpPPC64LoweredAtomicOr32
2086	OpPPC64LoweredWB
2087	OpPPC64LoweredPanicBoundsA
2088	OpPPC64LoweredPanicBoundsB
2089	OpPPC64LoweredPanicBoundsC
2090	OpPPC64InvertFlags
2091	OpPPC64FlagEQ
2092	OpPPC64FlagLT
2093	OpPPC64FlagGT
2094
2095	OpRISCV64ADD
2096	OpRISCV64ADDI
2097	OpRISCV64ADDIW
2098	OpRISCV64NEG
2099	OpRISCV64NEGW
2100	OpRISCV64SUB
2101	OpRISCV64SUBW
2102	OpRISCV64MUL
2103	OpRISCV64MULW
2104	OpRISCV64MULH
2105	OpRISCV64MULHU
2106	OpRISCV64LoweredMuluhilo
2107	OpRISCV64LoweredMuluover
2108	OpRISCV64DIV
2109	OpRISCV64DIVU
2110	OpRISCV64DIVW
2111	OpRISCV64DIVUW
2112	OpRISCV64REM
2113	OpRISCV64REMU
2114	OpRISCV64REMW
2115	OpRISCV64REMUW
2116	OpRISCV64MOVaddr
2117	OpRISCV64MOVDconst
2118	OpRISCV64MOVBload
2119	OpRISCV64MOVHload
2120	OpRISCV64MOVWload
2121	OpRISCV64MOVDload
2122	OpRISCV64MOVBUload
2123	OpRISCV64MOVHUload
2124	OpRISCV64MOVWUload
2125	OpRISCV64MOVBstore
2126	OpRISCV64MOVHstore
2127	OpRISCV64MOVWstore
2128	OpRISCV64MOVDstore
2129	OpRISCV64MOVBstorezero
2130	OpRISCV64MOVHstorezero
2131	OpRISCV64MOVWstorezero
2132	OpRISCV64MOVDstorezero
2133	OpRISCV64MOVBreg
2134	OpRISCV64MOVHreg
2135	OpRISCV64MOVWreg
2136	OpRISCV64MOVDreg
2137	OpRISCV64MOVBUreg
2138	OpRISCV64MOVHUreg
2139	OpRISCV64MOVWUreg
2140	OpRISCV64MOVDnop
2141	OpRISCV64SLL
2142	OpRISCV64SRA
2143	OpRISCV64SRL
2144	OpRISCV64SLLI
2145	OpRISCV64SRAI
2146	OpRISCV64SRLI
2147	OpRISCV64XOR
2148	OpRISCV64XORI
2149	OpRISCV64OR
2150	OpRISCV64ORI
2151	OpRISCV64AND
2152	OpRISCV64ANDI
2153	OpRISCV64NOT
2154	OpRISCV64SEQZ
2155	OpRISCV64SNEZ
2156	OpRISCV64SLT
2157	OpRISCV64SLTI
2158	OpRISCV64SLTU
2159	OpRISCV64SLTIU
2160	OpRISCV64MOVconvert
2161	OpRISCV64CALLstatic
2162	OpRISCV64CALLtail
2163	OpRISCV64CALLclosure
2164	OpRISCV64CALLinter
2165	OpRISCV64DUFFZERO
2166	OpRISCV64DUFFCOPY
2167	OpRISCV64LoweredZero
2168	OpRISCV64LoweredMove
2169	OpRISCV64LoweredAtomicLoad8
2170	OpRISCV64LoweredAtomicLoad32
2171	OpRISCV64LoweredAtomicLoad64
2172	OpRISCV64LoweredAtomicStore8
2173	OpRISCV64LoweredAtomicStore32
2174	OpRISCV64LoweredAtomicStore64
2175	OpRISCV64LoweredAtomicExchange32
2176	OpRISCV64LoweredAtomicExchange64
2177	OpRISCV64LoweredAtomicAdd32
2178	OpRISCV64LoweredAtomicAdd64
2179	OpRISCV64LoweredAtomicCas32
2180	OpRISCV64LoweredAtomicCas64
2181	OpRISCV64LoweredAtomicAnd32
2182	OpRISCV64LoweredAtomicOr32
2183	OpRISCV64LoweredNilCheck
2184	OpRISCV64LoweredGetClosurePtr
2185	OpRISCV64LoweredGetCallerSP
2186	OpRISCV64LoweredGetCallerPC
2187	OpRISCV64LoweredWB
2188	OpRISCV64LoweredPanicBoundsA
2189	OpRISCV64LoweredPanicBoundsB
2190	OpRISCV64LoweredPanicBoundsC
2191	OpRISCV64FADDS
2192	OpRISCV64FSUBS
2193	OpRISCV64FMULS
2194	OpRISCV64FDIVS
2195	OpRISCV64FSQRTS
2196	OpRISCV64FNEGS
2197	OpRISCV64FMVSX
2198	OpRISCV64FCVTSW
2199	OpRISCV64FCVTSL
2200	OpRISCV64FCVTWS
2201	OpRISCV64FCVTLS
2202	OpRISCV64FMOVWload
2203	OpRISCV64FMOVWstore
2204	OpRISCV64FEQS
2205	OpRISCV64FNES
2206	OpRISCV64FLTS
2207	OpRISCV64FLES
2208	OpRISCV64FADDD
2209	OpRISCV64FSUBD
2210	OpRISCV64FMULD
2211	OpRISCV64FDIVD
2212	OpRISCV64FMADDD
2213	OpRISCV64FMSUBD
2214	OpRISCV64FNMADDD
2215	OpRISCV64FNMSUBD
2216	OpRISCV64FSQRTD
2217	OpRISCV64FNEGD
2218	OpRISCV64FABSD
2219	OpRISCV64FSGNJD
2220	OpRISCV64FMVDX
2221	OpRISCV64FCVTDW
2222	OpRISCV64FCVTDL
2223	OpRISCV64FCVTWD
2224	OpRISCV64FCVTLD
2225	OpRISCV64FCVTDS
2226	OpRISCV64FCVTSD
2227	OpRISCV64FMOVDload
2228	OpRISCV64FMOVDstore
2229	OpRISCV64FEQD
2230	OpRISCV64FNED
2231	OpRISCV64FLTD
2232	OpRISCV64FLED
2233
2234	OpS390XFADDS
2235	OpS390XFADD
2236	OpS390XFSUBS
2237	OpS390XFSUB
2238	OpS390XFMULS
2239	OpS390XFMUL
2240	OpS390XFDIVS
2241	OpS390XFDIV
2242	OpS390XFNEGS
2243	OpS390XFNEG
2244	OpS390XFMADDS
2245	OpS390XFMADD
2246	OpS390XFMSUBS
2247	OpS390XFMSUB
2248	OpS390XLPDFR
2249	OpS390XLNDFR
2250	OpS390XCPSDR
2251	OpS390XFIDBR
2252	OpS390XFMOVSload
2253	OpS390XFMOVDload
2254	OpS390XFMOVSconst
2255	OpS390XFMOVDconst
2256	OpS390XFMOVSloadidx
2257	OpS390XFMOVDloadidx
2258	OpS390XFMOVSstore
2259	OpS390XFMOVDstore
2260	OpS390XFMOVSstoreidx
2261	OpS390XFMOVDstoreidx
2262	OpS390XADD
2263	OpS390XADDW
2264	OpS390XADDconst
2265	OpS390XADDWconst
2266	OpS390XADDload
2267	OpS390XADDWload
2268	OpS390XSUB
2269	OpS390XSUBW
2270	OpS390XSUBconst
2271	OpS390XSUBWconst
2272	OpS390XSUBload
2273	OpS390XSUBWload
2274	OpS390XMULLD
2275	OpS390XMULLW
2276	OpS390XMULLDconst
2277	OpS390XMULLWconst
2278	OpS390XMULLDload
2279	OpS390XMULLWload
2280	OpS390XMULHD
2281	OpS390XMULHDU
2282	OpS390XDIVD
2283	OpS390XDIVW
2284	OpS390XDIVDU
2285	OpS390XDIVWU
2286	OpS390XMODD
2287	OpS390XMODW
2288	OpS390XMODDU
2289	OpS390XMODWU
2290	OpS390XAND
2291	OpS390XANDW
2292	OpS390XANDconst
2293	OpS390XANDWconst
2294	OpS390XANDload
2295	OpS390XANDWload
2296	OpS390XOR
2297	OpS390XORW
2298	OpS390XORconst
2299	OpS390XORWconst
2300	OpS390XORload
2301	OpS390XORWload
2302	OpS390XXOR
2303	OpS390XXORW
2304	OpS390XXORconst
2305	OpS390XXORWconst
2306	OpS390XXORload
2307	OpS390XXORWload
2308	OpS390XADDC
2309	OpS390XADDCconst
2310	OpS390XADDE
2311	OpS390XSUBC
2312	OpS390XSUBE
2313	OpS390XCMP
2314	OpS390XCMPW
2315	OpS390XCMPU
2316	OpS390XCMPWU
2317	OpS390XCMPconst
2318	OpS390XCMPWconst
2319	OpS390XCMPUconst
2320	OpS390XCMPWUconst
2321	OpS390XFCMPS
2322	OpS390XFCMP
2323	OpS390XLTDBR
2324	OpS390XLTEBR
2325	OpS390XSLD
2326	OpS390XSLW
2327	OpS390XSLDconst
2328	OpS390XSLWconst
2329	OpS390XSRD
2330	OpS390XSRW
2331	OpS390XSRDconst
2332	OpS390XSRWconst
2333	OpS390XSRAD
2334	OpS390XSRAW
2335	OpS390XSRADconst
2336	OpS390XSRAWconst
2337	OpS390XRLLG
2338	OpS390XRLL
2339	OpS390XRLLconst
2340	OpS390XRXSBG
2341	OpS390XRISBGZ
2342	OpS390XNEG
2343	OpS390XNEGW
2344	OpS390XNOT
2345	OpS390XNOTW
2346	OpS390XFSQRT
2347	OpS390XFSQRTS
2348	OpS390XLOCGR
2349	OpS390XMOVBreg
2350	OpS390XMOVBZreg
2351	OpS390XMOVHreg
2352	OpS390XMOVHZreg
2353	OpS390XMOVWreg
2354	OpS390XMOVWZreg
2355	OpS390XMOVDconst
2356	OpS390XLDGR
2357	OpS390XLGDR
2358	OpS390XCFDBRA
2359	OpS390XCGDBRA
2360	OpS390XCFEBRA
2361	OpS390XCGEBRA
2362	OpS390XCEFBRA
2363	OpS390XCDFBRA
2364	OpS390XCEGBRA
2365	OpS390XCDGBRA
2366	OpS390XCLFEBR
2367	OpS390XCLFDBR
2368	OpS390XCLGEBR
2369	OpS390XCLGDBR
2370	OpS390XCELFBR
2371	OpS390XCDLFBR
2372	OpS390XCELGBR
2373	OpS390XCDLGBR
2374	OpS390XLEDBR
2375	OpS390XLDEBR
2376	OpS390XMOVDaddr
2377	OpS390XMOVDaddridx
2378	OpS390XMOVBZload
2379	OpS390XMOVBload
2380	OpS390XMOVHZload
2381	OpS390XMOVHload
2382	OpS390XMOVWZload
2383	OpS390XMOVWload
2384	OpS390XMOVDload
2385	OpS390XMOVWBR
2386	OpS390XMOVDBR
2387	OpS390XMOVHBRload
2388	OpS390XMOVWBRload
2389	OpS390XMOVDBRload
2390	OpS390XMOVBstore
2391	OpS390XMOVHstore
2392	OpS390XMOVWstore
2393	OpS390XMOVDstore
2394	OpS390XMOVHBRstore
2395	OpS390XMOVWBRstore
2396	OpS390XMOVDBRstore
2397	OpS390XMVC
2398	OpS390XMOVBZloadidx
2399	OpS390XMOVBloadidx
2400	OpS390XMOVHZloadidx
2401	OpS390XMOVHloadidx
2402	OpS390XMOVWZloadidx
2403	OpS390XMOVWloadidx
2404	OpS390XMOVDloadidx
2405	OpS390XMOVHBRloadidx
2406	OpS390XMOVWBRloadidx
2407	OpS390XMOVDBRloadidx
2408	OpS390XMOVBstoreidx
2409	OpS390XMOVHstoreidx
2410	OpS390XMOVWstoreidx
2411	OpS390XMOVDstoreidx
2412	OpS390XMOVHBRstoreidx
2413	OpS390XMOVWBRstoreidx
2414	OpS390XMOVDBRstoreidx
2415	OpS390XMOVBstoreconst
2416	OpS390XMOVHstoreconst
2417	OpS390XMOVWstoreconst
2418	OpS390XMOVDstoreconst
2419	OpS390XCLEAR
2420	OpS390XCALLstatic
2421	OpS390XCALLtail
2422	OpS390XCALLclosure
2423	OpS390XCALLinter
2424	OpS390XInvertFlags
2425	OpS390XLoweredGetG
2426	OpS390XLoweredGetClosurePtr
2427	OpS390XLoweredGetCallerSP
2428	OpS390XLoweredGetCallerPC
2429	OpS390XLoweredNilCheck
2430	OpS390XLoweredRound32F
2431	OpS390XLoweredRound64F
2432	OpS390XLoweredWB
2433	OpS390XLoweredPanicBoundsA
2434	OpS390XLoweredPanicBoundsB
2435	OpS390XLoweredPanicBoundsC
2436	OpS390XFlagEQ
2437	OpS390XFlagLT
2438	OpS390XFlagGT
2439	OpS390XFlagOV
2440	OpS390XSYNC
2441	OpS390XMOVBZatomicload
2442	OpS390XMOVWZatomicload
2443	OpS390XMOVDatomicload
2444	OpS390XMOVBatomicstore
2445	OpS390XMOVWatomicstore
2446	OpS390XMOVDatomicstore
2447	OpS390XLAA
2448	OpS390XLAAG
2449	OpS390XAddTupleFirst32
2450	OpS390XAddTupleFirst64
2451	OpS390XLAN
2452	OpS390XLANfloor
2453	OpS390XLAO
2454	OpS390XLAOfloor
2455	OpS390XLoweredAtomicCas32
2456	OpS390XLoweredAtomicCas64
2457	OpS390XLoweredAtomicExchange32
2458	OpS390XLoweredAtomicExchange64
2459	OpS390XFLOGR
2460	OpS390XPOPCNT
2461	OpS390XMLGR
2462	OpS390XSumBytes2
2463	OpS390XSumBytes4
2464	OpS390XSumBytes8
2465	OpS390XSTMG2
2466	OpS390XSTMG3
2467	OpS390XSTMG4
2468	OpS390XSTM2
2469	OpS390XSTM3
2470	OpS390XSTM4
2471	OpS390XLoweredMove
2472	OpS390XLoweredZero
2473
2474	OpWasmLoweredStaticCall
2475	OpWasmLoweredTailCall
2476	OpWasmLoweredClosureCall
2477	OpWasmLoweredInterCall
2478	OpWasmLoweredAddr
2479	OpWasmLoweredMove
2480	OpWasmLoweredZero
2481	OpWasmLoweredGetClosurePtr
2482	OpWasmLoweredGetCallerPC
2483	OpWasmLoweredGetCallerSP
2484	OpWasmLoweredNilCheck
2485	OpWasmLoweredWB
2486	OpWasmLoweredConvert
2487	OpWasmSelect
2488	OpWasmI64Load8U
2489	OpWasmI64Load8S
2490	OpWasmI64Load16U
2491	OpWasmI64Load16S
2492	OpWasmI64Load32U
2493	OpWasmI64Load32S
2494	OpWasmI64Load
2495	OpWasmI64Store8
2496	OpWasmI64Store16
2497	OpWasmI64Store32
2498	OpWasmI64Store
2499	OpWasmF32Load
2500	OpWasmF64Load
2501	OpWasmF32Store
2502	OpWasmF64Store
2503	OpWasmI64Const
2504	OpWasmF32Const
2505	OpWasmF64Const
2506	OpWasmI64Eqz
2507	OpWasmI64Eq
2508	OpWasmI64Ne
2509	OpWasmI64LtS
2510	OpWasmI64LtU
2511	OpWasmI64GtS
2512	OpWasmI64GtU
2513	OpWasmI64LeS
2514	OpWasmI64LeU
2515	OpWasmI64GeS
2516	OpWasmI64GeU
2517	OpWasmF32Eq
2518	OpWasmF32Ne
2519	OpWasmF32Lt
2520	OpWasmF32Gt
2521	OpWasmF32Le
2522	OpWasmF32Ge
2523	OpWasmF64Eq
2524	OpWasmF64Ne
2525	OpWasmF64Lt
2526	OpWasmF64Gt
2527	OpWasmF64Le
2528	OpWasmF64Ge
2529	OpWasmI64Add
2530	OpWasmI64AddConst
2531	OpWasmI64Sub
2532	OpWasmI64Mul
2533	OpWasmI64DivS
2534	OpWasmI64DivU
2535	OpWasmI64RemS
2536	OpWasmI64RemU
2537	OpWasmI64And
2538	OpWasmI64Or
2539	OpWasmI64Xor
2540	OpWasmI64Shl
2541	OpWasmI64ShrS
2542	OpWasmI64ShrU
2543	OpWasmF32Neg
2544	OpWasmF32Add
2545	OpWasmF32Sub
2546	OpWasmF32Mul
2547	OpWasmF32Div
2548	OpWasmF64Neg
2549	OpWasmF64Add
2550	OpWasmF64Sub
2551	OpWasmF64Mul
2552	OpWasmF64Div
2553	OpWasmI64TruncSatF64S
2554	OpWasmI64TruncSatF64U
2555	OpWasmI64TruncSatF32S
2556	OpWasmI64TruncSatF32U
2557	OpWasmF32ConvertI64S
2558	OpWasmF32ConvertI64U
2559	OpWasmF64ConvertI64S
2560	OpWasmF64ConvertI64U
2561	OpWasmF32DemoteF64
2562	OpWasmF64PromoteF32
2563	OpWasmI64Extend8S
2564	OpWasmI64Extend16S
2565	OpWasmI64Extend32S
2566	OpWasmF32Sqrt
2567	OpWasmF32Trunc
2568	OpWasmF32Ceil
2569	OpWasmF32Floor
2570	OpWasmF32Nearest
2571	OpWasmF32Abs
2572	OpWasmF32Copysign
2573	OpWasmF64Sqrt
2574	OpWasmF64Trunc
2575	OpWasmF64Ceil
2576	OpWasmF64Floor
2577	OpWasmF64Nearest
2578	OpWasmF64Abs
2579	OpWasmF64Copysign
2580	OpWasmI64Ctz
2581	OpWasmI64Clz
2582	OpWasmI32Rotl
2583	OpWasmI64Rotl
2584	OpWasmI64Popcnt
2585
2586	OpAdd8
2587	OpAdd16
2588	OpAdd32
2589	OpAdd64
2590	OpAddPtr
2591	OpAdd32F
2592	OpAdd64F
2593	OpSub8
2594	OpSub16
2595	OpSub32
2596	OpSub64
2597	OpSubPtr
2598	OpSub32F
2599	OpSub64F
2600	OpMul8
2601	OpMul16
2602	OpMul32
2603	OpMul64
2604	OpMul32F
2605	OpMul64F
2606	OpDiv32F
2607	OpDiv64F
2608	OpHmul32
2609	OpHmul32u
2610	OpHmul64
2611	OpHmul64u
2612	OpMul32uhilo
2613	OpMul64uhilo
2614	OpMul32uover
2615	OpMul64uover
2616	OpAvg32u
2617	OpAvg64u
2618	OpDiv8
2619	OpDiv8u
2620	OpDiv16
2621	OpDiv16u
2622	OpDiv32
2623	OpDiv32u
2624	OpDiv64
2625	OpDiv64u
2626	OpDiv128u
2627	OpMod8
2628	OpMod8u
2629	OpMod16
2630	OpMod16u
2631	OpMod32
2632	OpMod32u
2633	OpMod64
2634	OpMod64u
2635	OpAnd8
2636	OpAnd16
2637	OpAnd32
2638	OpAnd64
2639	OpOr8
2640	OpOr16
2641	OpOr32
2642	OpOr64
2643	OpXor8
2644	OpXor16
2645	OpXor32
2646	OpXor64
2647	OpLsh8x8
2648	OpLsh8x16
2649	OpLsh8x32
2650	OpLsh8x64
2651	OpLsh16x8
2652	OpLsh16x16
2653	OpLsh16x32
2654	OpLsh16x64
2655	OpLsh32x8
2656	OpLsh32x16
2657	OpLsh32x32
2658	OpLsh32x64
2659	OpLsh64x8
2660	OpLsh64x16
2661	OpLsh64x32
2662	OpLsh64x64
2663	OpRsh8x8
2664	OpRsh8x16
2665	OpRsh8x32
2666	OpRsh8x64
2667	OpRsh16x8
2668	OpRsh16x16
2669	OpRsh16x32
2670	OpRsh16x64
2671	OpRsh32x8
2672	OpRsh32x16
2673	OpRsh32x32
2674	OpRsh32x64
2675	OpRsh64x8
2676	OpRsh64x16
2677	OpRsh64x32
2678	OpRsh64x64
2679	OpRsh8Ux8
2680	OpRsh8Ux16
2681	OpRsh8Ux32
2682	OpRsh8Ux64
2683	OpRsh16Ux8
2684	OpRsh16Ux16
2685	OpRsh16Ux32
2686	OpRsh16Ux64
2687	OpRsh32Ux8
2688	OpRsh32Ux16
2689	OpRsh32Ux32
2690	OpRsh32Ux64
2691	OpRsh64Ux8
2692	OpRsh64Ux16
2693	OpRsh64Ux32
2694	OpRsh64Ux64
2695	OpEq8
2696	OpEq16
2697	OpEq32
2698	OpEq64
2699	OpEqPtr
2700	OpEqInter
2701	OpEqSlice
2702	OpEq32F
2703	OpEq64F
2704	OpNeq8
2705	OpNeq16
2706	OpNeq32
2707	OpNeq64
2708	OpNeqPtr
2709	OpNeqInter
2710	OpNeqSlice
2711	OpNeq32F
2712	OpNeq64F
2713	OpLess8
2714	OpLess8U
2715	OpLess16
2716	OpLess16U
2717	OpLess32
2718	OpLess32U
2719	OpLess64
2720	OpLess64U
2721	OpLess32F
2722	OpLess64F
2723	OpLeq8
2724	OpLeq8U
2725	OpLeq16
2726	OpLeq16U
2727	OpLeq32
2728	OpLeq32U
2729	OpLeq64
2730	OpLeq64U
2731	OpLeq32F
2732	OpLeq64F
2733	OpCondSelect
2734	OpAndB
2735	OpOrB
2736	OpEqB
2737	OpNeqB
2738	OpNot
2739	OpNeg8
2740	OpNeg16
2741	OpNeg32
2742	OpNeg64
2743	OpNeg32F
2744	OpNeg64F
2745	OpCom8
2746	OpCom16
2747	OpCom32
2748	OpCom64
2749	OpCtz8
2750	OpCtz16
2751	OpCtz32
2752	OpCtz64
2753	OpCtz8NonZero
2754	OpCtz16NonZero
2755	OpCtz32NonZero
2756	OpCtz64NonZero
2757	OpBitLen8
2758	OpBitLen16
2759	OpBitLen32
2760	OpBitLen64
2761	OpBswap32
2762	OpBswap64
2763	OpBitRev8
2764	OpBitRev16
2765	OpBitRev32
2766	OpBitRev64
2767	OpPopCount8
2768	OpPopCount16
2769	OpPopCount32
2770	OpPopCount64
2771	OpRotateLeft8
2772	OpRotateLeft16
2773	OpRotateLeft32
2774	OpRotateLeft64
2775	OpSqrt
2776	OpSqrt32
2777	OpFloor
2778	OpCeil
2779	OpTrunc
2780	OpRound
2781	OpRoundToEven
2782	OpAbs
2783	OpCopysign
2784	OpFMA
2785	OpPhi
2786	OpCopy
2787	OpConvert
2788	OpConstBool
2789	OpConstString
2790	OpConstNil
2791	OpConst8
2792	OpConst16
2793	OpConst32
2794	OpConst64
2795	OpConst32F
2796	OpConst64F
2797	OpConstInterface
2798	OpConstSlice
2799	OpInitMem
2800	OpArg
2801	OpArgIntReg
2802	OpArgFloatReg
2803	OpAddr
2804	OpLocalAddr
2805	OpSP
2806	OpSB
2807	OpLoad
2808	OpDereference
2809	OpStore
2810	OpMove
2811	OpZero
2812	OpStoreWB
2813	OpMoveWB
2814	OpZeroWB
2815	OpWB
2816	OpHasCPUFeature
2817	OpPanicBounds
2818	OpPanicExtend
2819	OpClosureCall
2820	OpStaticCall
2821	OpInterCall
2822	OpTailCall
2823	OpClosureLECall
2824	OpStaticLECall
2825	OpInterLECall
2826	OpTailLECall
2827	OpSignExt8to16
2828	OpSignExt8to32
2829	OpSignExt8to64
2830	OpSignExt16to32
2831	OpSignExt16to64
2832	OpSignExt32to64
2833	OpZeroExt8to16
2834	OpZeroExt8to32
2835	OpZeroExt8to64
2836	OpZeroExt16to32
2837	OpZeroExt16to64
2838	OpZeroExt32to64
2839	OpTrunc16to8
2840	OpTrunc32to8
2841	OpTrunc32to16
2842	OpTrunc64to8
2843	OpTrunc64to16
2844	OpTrunc64to32
2845	OpCvt32to32F
2846	OpCvt32to64F
2847	OpCvt64to32F
2848	OpCvt64to64F
2849	OpCvt32Fto32
2850	OpCvt32Fto64
2851	OpCvt64Fto32
2852	OpCvt64Fto64
2853	OpCvt32Fto64F
2854	OpCvt64Fto32F
2855	OpCvtBoolToUint8
2856	OpRound32F
2857	OpRound64F
2858	OpIsNonNil
2859	OpIsInBounds
2860	OpIsSliceInBounds
2861	OpNilCheck
2862	OpGetG
2863	OpGetClosurePtr
2864	OpGetCallerPC
2865	OpGetCallerSP
2866	OpPtrIndex
2867	OpOffPtr
2868	OpSliceMake
2869	OpSlicePtr
2870	OpSliceLen
2871	OpSliceCap
2872	OpSlicePtrUnchecked
2873	OpComplexMake
2874	OpComplexReal
2875	OpComplexImag
2876	OpStringMake
2877	OpStringPtr
2878	OpStringLen
2879	OpIMake
2880	OpITab
2881	OpIData
2882	OpStructMake0
2883	OpStructMake1
2884	OpStructMake2
2885	OpStructMake3
2886	OpStructMake4
2887	OpStructSelect
2888	OpArrayMake0
2889	OpArrayMake1
2890	OpArraySelect
2891	OpStoreReg
2892	OpLoadReg
2893	OpFwdRef
2894	OpUnknown
2895	OpVarDef
2896	OpVarKill
2897	OpVarLive
2898	OpKeepAlive
2899	OpInlMark
2900	OpInt64Make
2901	OpInt64Hi
2902	OpInt64Lo
2903	OpAdd32carry
2904	OpAdd32withcarry
2905	OpSub32carry
2906	OpSub32withcarry
2907	OpAdd64carry
2908	OpSub64borrow
2909	OpSignmask
2910	OpZeromask
2911	OpSlicemask
2912	OpSpectreIndex
2913	OpSpectreSliceIndex
2914	OpCvt32Uto32F
2915	OpCvt32Uto64F
2916	OpCvt32Fto32U
2917	OpCvt64Fto32U
2918	OpCvt64Uto32F
2919	OpCvt64Uto64F
2920	OpCvt32Fto64U
2921	OpCvt64Fto64U
2922	OpSelect0
2923	OpSelect1
2924	OpSelectN
2925	OpSelectNAddr
2926	OpMakeResult
2927	OpAtomicLoad8
2928	OpAtomicLoad32
2929	OpAtomicLoad64
2930	OpAtomicLoadPtr
2931	OpAtomicLoadAcq32
2932	OpAtomicLoadAcq64
2933	OpAtomicStore8
2934	OpAtomicStore32
2935	OpAtomicStore64
2936	OpAtomicStorePtrNoWB
2937	OpAtomicStoreRel32
2938	OpAtomicStoreRel64
2939	OpAtomicExchange32
2940	OpAtomicExchange64
2941	OpAtomicAdd32
2942	OpAtomicAdd64
2943	OpAtomicCompareAndSwap32
2944	OpAtomicCompareAndSwap64
2945	OpAtomicCompareAndSwapRel32
2946	OpAtomicAnd8
2947	OpAtomicAnd32
2948	OpAtomicOr8
2949	OpAtomicOr32
2950	OpAtomicAdd32Variant
2951	OpAtomicAdd64Variant
2952	OpAtomicExchange32Variant
2953	OpAtomicExchange64Variant
2954	OpAtomicCompareAndSwap32Variant
2955	OpAtomicCompareAndSwap64Variant
2956	OpAtomicAnd8Variant
2957	OpAtomicAnd32Variant
2958	OpAtomicOr8Variant
2959	OpAtomicOr32Variant
2960	OpPubBarrier
2961	OpClobber
2962	OpClobberReg
2963	OpPrefetchCache
2964	OpPrefetchCacheStreamed
2965)
2966
2967var opcodeTable = [...]opInfo{
2968	{name: "OpInvalid"},
2969
2970	{
2971		name:         "ADDSS",
2972		argLen:       2,
2973		commutative:  true,
2974		resultInArg0: true,
2975		asm:          x86.AADDSS,
2976		reg: regInfo{
2977			inputs: []inputInfo{
2978				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2979				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2980			},
2981			outputs: []outputInfo{
2982				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2983			},
2984		},
2985	},
2986	{
2987		name:         "ADDSD",
2988		argLen:       2,
2989		commutative:  true,
2990		resultInArg0: true,
2991		asm:          x86.AADDSD,
2992		reg: regInfo{
2993			inputs: []inputInfo{
2994				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2995				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2996			},
2997			outputs: []outputInfo{
2998				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
2999			},
3000		},
3001	},
3002	{
3003		name:         "SUBSS",
3004		argLen:       2,
3005		resultInArg0: true,
3006		asm:          x86.ASUBSS,
3007		reg: regInfo{
3008			inputs: []inputInfo{
3009				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3010				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3011			},
3012			outputs: []outputInfo{
3013				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3014			},
3015		},
3016	},
3017	{
3018		name:         "SUBSD",
3019		argLen:       2,
3020		resultInArg0: true,
3021		asm:          x86.ASUBSD,
3022		reg: regInfo{
3023			inputs: []inputInfo{
3024				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3025				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3026			},
3027			outputs: []outputInfo{
3028				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3029			},
3030		},
3031	},
3032	{
3033		name:         "MULSS",
3034		argLen:       2,
3035		commutative:  true,
3036		resultInArg0: true,
3037		asm:          x86.AMULSS,
3038		reg: regInfo{
3039			inputs: []inputInfo{
3040				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3041				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3042			},
3043			outputs: []outputInfo{
3044				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3045			},
3046		},
3047	},
3048	{
3049		name:         "MULSD",
3050		argLen:       2,
3051		commutative:  true,
3052		resultInArg0: true,
3053		asm:          x86.AMULSD,
3054		reg: regInfo{
3055			inputs: []inputInfo{
3056				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3057				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3058			},
3059			outputs: []outputInfo{
3060				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3061			},
3062		},
3063	},
3064	{
3065		name:         "DIVSS",
3066		argLen:       2,
3067		resultInArg0: true,
3068		asm:          x86.ADIVSS,
3069		reg: regInfo{
3070			inputs: []inputInfo{
3071				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3072				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3073			},
3074			outputs: []outputInfo{
3075				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3076			},
3077		},
3078	},
3079	{
3080		name:         "DIVSD",
3081		argLen:       2,
3082		resultInArg0: true,
3083		asm:          x86.ADIVSD,
3084		reg: regInfo{
3085			inputs: []inputInfo{
3086				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3087				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3088			},
3089			outputs: []outputInfo{
3090				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3091			},
3092		},
3093	},
3094	{
3095		name:           "MOVSSload",
3096		auxType:        auxSymOff,
3097		argLen:         2,
3098		faultOnNilArg0: true,
3099		symEffect:      SymRead,
3100		asm:            x86.AMOVSS,
3101		reg: regInfo{
3102			inputs: []inputInfo{
3103				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3104			},
3105			outputs: []outputInfo{
3106				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3107			},
3108		},
3109	},
3110	{
3111		name:           "MOVSDload",
3112		auxType:        auxSymOff,
3113		argLen:         2,
3114		faultOnNilArg0: true,
3115		symEffect:      SymRead,
3116		asm:            x86.AMOVSD,
3117		reg: regInfo{
3118			inputs: []inputInfo{
3119				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3120			},
3121			outputs: []outputInfo{
3122				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3123			},
3124		},
3125	},
3126	{
3127		name:              "MOVSSconst",
3128		auxType:           auxFloat32,
3129		argLen:            0,
3130		rematerializeable: true,
3131		asm:               x86.AMOVSS,
3132		reg: regInfo{
3133			outputs: []outputInfo{
3134				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3135			},
3136		},
3137	},
3138	{
3139		name:              "MOVSDconst",
3140		auxType:           auxFloat64,
3141		argLen:            0,
3142		rematerializeable: true,
3143		asm:               x86.AMOVSD,
3144		reg: regInfo{
3145			outputs: []outputInfo{
3146				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3147			},
3148		},
3149	},
3150	{
3151		name:      "MOVSSloadidx1",
3152		auxType:   auxSymOff,
3153		argLen:    3,
3154		symEffect: SymRead,
3155		asm:       x86.AMOVSS,
3156		reg: regInfo{
3157			inputs: []inputInfo{
3158				{1, 255},   // AX CX DX BX SP BP SI DI
3159				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3160			},
3161			outputs: []outputInfo{
3162				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3163			},
3164		},
3165	},
3166	{
3167		name:      "MOVSSloadidx4",
3168		auxType:   auxSymOff,
3169		argLen:    3,
3170		symEffect: SymRead,
3171		asm:       x86.AMOVSS,
3172		reg: regInfo{
3173			inputs: []inputInfo{
3174				{1, 255},   // AX CX DX BX SP BP SI DI
3175				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3176			},
3177			outputs: []outputInfo{
3178				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3179			},
3180		},
3181	},
3182	{
3183		name:      "MOVSDloadidx1",
3184		auxType:   auxSymOff,
3185		argLen:    3,
3186		symEffect: SymRead,
3187		asm:       x86.AMOVSD,
3188		reg: regInfo{
3189			inputs: []inputInfo{
3190				{1, 255},   // AX CX DX BX SP BP SI DI
3191				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3192			},
3193			outputs: []outputInfo{
3194				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3195			},
3196		},
3197	},
3198	{
3199		name:      "MOVSDloadidx8",
3200		auxType:   auxSymOff,
3201		argLen:    3,
3202		symEffect: SymRead,
3203		asm:       x86.AMOVSD,
3204		reg: regInfo{
3205			inputs: []inputInfo{
3206				{1, 255},   // AX CX DX BX SP BP SI DI
3207				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3208			},
3209			outputs: []outputInfo{
3210				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3211			},
3212		},
3213	},
3214	{
3215		name:           "MOVSSstore",
3216		auxType:        auxSymOff,
3217		argLen:         3,
3218		faultOnNilArg0: true,
3219		symEffect:      SymWrite,
3220		asm:            x86.AMOVSS,
3221		reg: regInfo{
3222			inputs: []inputInfo{
3223				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3224				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3225			},
3226		},
3227	},
3228	{
3229		name:           "MOVSDstore",
3230		auxType:        auxSymOff,
3231		argLen:         3,
3232		faultOnNilArg0: true,
3233		symEffect:      SymWrite,
3234		asm:            x86.AMOVSD,
3235		reg: regInfo{
3236			inputs: []inputInfo{
3237				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3238				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3239			},
3240		},
3241	},
3242	{
3243		name:      "MOVSSstoreidx1",
3244		auxType:   auxSymOff,
3245		argLen:    4,
3246		symEffect: SymWrite,
3247		asm:       x86.AMOVSS,
3248		reg: regInfo{
3249			inputs: []inputInfo{
3250				{1, 255},   // AX CX DX BX SP BP SI DI
3251				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3252				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3253			},
3254		},
3255	},
3256	{
3257		name:      "MOVSSstoreidx4",
3258		auxType:   auxSymOff,
3259		argLen:    4,
3260		symEffect: SymWrite,
3261		asm:       x86.AMOVSS,
3262		reg: regInfo{
3263			inputs: []inputInfo{
3264				{1, 255},   // AX CX DX BX SP BP SI DI
3265				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3266				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3267			},
3268		},
3269	},
3270	{
3271		name:      "MOVSDstoreidx1",
3272		auxType:   auxSymOff,
3273		argLen:    4,
3274		symEffect: SymWrite,
3275		asm:       x86.AMOVSD,
3276		reg: regInfo{
3277			inputs: []inputInfo{
3278				{1, 255},   // AX CX DX BX SP BP SI DI
3279				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3280				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3281			},
3282		},
3283	},
3284	{
3285		name:      "MOVSDstoreidx8",
3286		auxType:   auxSymOff,
3287		argLen:    4,
3288		symEffect: SymWrite,
3289		asm:       x86.AMOVSD,
3290		reg: regInfo{
3291			inputs: []inputInfo{
3292				{1, 255},   // AX CX DX BX SP BP SI DI
3293				{2, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3294				{0, 65791}, // AX CX DX BX SP BP SI DI SB
3295			},
3296		},
3297	},
3298	{
3299		name:           "ADDSSload",
3300		auxType:        auxSymOff,
3301		argLen:         3,
3302		resultInArg0:   true,
3303		faultOnNilArg1: true,
3304		symEffect:      SymRead,
3305		asm:            x86.AADDSS,
3306		reg: regInfo{
3307			inputs: []inputInfo{
3308				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3309				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3310			},
3311			outputs: []outputInfo{
3312				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3313			},
3314		},
3315	},
3316	{
3317		name:           "ADDSDload",
3318		auxType:        auxSymOff,
3319		argLen:         3,
3320		resultInArg0:   true,
3321		faultOnNilArg1: true,
3322		symEffect:      SymRead,
3323		asm:            x86.AADDSD,
3324		reg: regInfo{
3325			inputs: []inputInfo{
3326				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3327				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3328			},
3329			outputs: []outputInfo{
3330				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3331			},
3332		},
3333	},
3334	{
3335		name:           "SUBSSload",
3336		auxType:        auxSymOff,
3337		argLen:         3,
3338		resultInArg0:   true,
3339		faultOnNilArg1: true,
3340		symEffect:      SymRead,
3341		asm:            x86.ASUBSS,
3342		reg: regInfo{
3343			inputs: []inputInfo{
3344				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3345				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3346			},
3347			outputs: []outputInfo{
3348				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3349			},
3350		},
3351	},
3352	{
3353		name:           "SUBSDload",
3354		auxType:        auxSymOff,
3355		argLen:         3,
3356		resultInArg0:   true,
3357		faultOnNilArg1: true,
3358		symEffect:      SymRead,
3359		asm:            x86.ASUBSD,
3360		reg: regInfo{
3361			inputs: []inputInfo{
3362				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3363				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3364			},
3365			outputs: []outputInfo{
3366				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3367			},
3368		},
3369	},
3370	{
3371		name:           "MULSSload",
3372		auxType:        auxSymOff,
3373		argLen:         3,
3374		resultInArg0:   true,
3375		faultOnNilArg1: true,
3376		symEffect:      SymRead,
3377		asm:            x86.AMULSS,
3378		reg: regInfo{
3379			inputs: []inputInfo{
3380				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3381				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3382			},
3383			outputs: []outputInfo{
3384				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3385			},
3386		},
3387	},
3388	{
3389		name:           "MULSDload",
3390		auxType:        auxSymOff,
3391		argLen:         3,
3392		resultInArg0:   true,
3393		faultOnNilArg1: true,
3394		symEffect:      SymRead,
3395		asm:            x86.AMULSD,
3396		reg: regInfo{
3397			inputs: []inputInfo{
3398				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3399				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3400			},
3401			outputs: []outputInfo{
3402				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3403			},
3404		},
3405	},
3406	{
3407		name:           "DIVSSload",
3408		auxType:        auxSymOff,
3409		argLen:         3,
3410		resultInArg0:   true,
3411		faultOnNilArg1: true,
3412		symEffect:      SymRead,
3413		asm:            x86.ADIVSS,
3414		reg: regInfo{
3415			inputs: []inputInfo{
3416				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3417				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3418			},
3419			outputs: []outputInfo{
3420				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3421			},
3422		},
3423	},
3424	{
3425		name:           "DIVSDload",
3426		auxType:        auxSymOff,
3427		argLen:         3,
3428		resultInArg0:   true,
3429		faultOnNilArg1: true,
3430		symEffect:      SymRead,
3431		asm:            x86.ADIVSD,
3432		reg: regInfo{
3433			inputs: []inputInfo{
3434				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3435				{1, 65791}, // AX CX DX BX SP BP SI DI SB
3436			},
3437			outputs: []outputInfo{
3438				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
3439			},
3440		},
3441	},
3442	{
3443		name:         "ADDL",
3444		argLen:       2,
3445		commutative:  true,
3446		clobberFlags: true,
3447		asm:          x86.AADDL,
3448		reg: regInfo{
3449			inputs: []inputInfo{
3450				{1, 239}, // AX CX DX BX BP SI DI
3451				{0, 255}, // AX CX DX BX SP BP SI DI
3452			},
3453			outputs: []outputInfo{
3454				{0, 239}, // AX CX DX BX BP SI DI
3455			},
3456		},
3457	},
3458	{
3459		name:         "ADDLconst",
3460		auxType:      auxInt32,
3461		argLen:       1,
3462		clobberFlags: true,
3463		asm:          x86.AADDL,
3464		reg: regInfo{
3465			inputs: []inputInfo{
3466				{0, 255}, // AX CX DX BX SP BP SI DI
3467			},
3468			outputs: []outputInfo{
3469				{0, 239}, // AX CX DX BX BP SI DI
3470			},
3471		},
3472	},
3473	{
3474		name:         "ADDLcarry",
3475		argLen:       2,
3476		commutative:  true,
3477		resultInArg0: true,
3478		asm:          x86.AADDL,
3479		reg: regInfo{
3480			inputs: []inputInfo{
3481				{0, 239}, // AX CX DX BX BP SI DI
3482				{1, 239}, // AX CX DX BX BP SI DI
3483			},
3484			outputs: []outputInfo{
3485				{1, 0},
3486				{0, 239}, // AX CX DX BX BP SI DI
3487			},
3488		},
3489	},
3490	{
3491		name:         "ADDLconstcarry",
3492		auxType:      auxInt32,
3493		argLen:       1,
3494		resultInArg0: true,
3495		asm:          x86.AADDL,
3496		reg: regInfo{
3497			inputs: []inputInfo{
3498				{0, 239}, // AX CX DX BX BP SI DI
3499			},
3500			outputs: []outputInfo{
3501				{1, 0},
3502				{0, 239}, // AX CX DX BX BP SI DI
3503			},
3504		},
3505	},
3506	{
3507		name:         "ADCL",
3508		argLen:       3,
3509		commutative:  true,
3510		resultInArg0: true,
3511		clobberFlags: true,
3512		asm:          x86.AADCL,
3513		reg: regInfo{
3514			inputs: []inputInfo{
3515				{0, 239}, // AX CX DX BX BP SI DI
3516				{1, 239}, // AX CX DX BX BP SI DI
3517			},
3518			outputs: []outputInfo{
3519				{0, 239}, // AX CX DX BX BP SI DI
3520			},
3521		},
3522	},
3523	{
3524		name:         "ADCLconst",
3525		auxType:      auxInt32,
3526		argLen:       2,
3527		resultInArg0: true,
3528		clobberFlags: true,
3529		asm:          x86.AADCL,
3530		reg: regInfo{
3531			inputs: []inputInfo{
3532				{0, 239}, // AX CX DX BX BP SI DI
3533			},
3534			outputs: []outputInfo{
3535				{0, 239}, // AX CX DX BX BP SI DI
3536			},
3537		},
3538	},
3539	{
3540		name:         "SUBL",
3541		argLen:       2,
3542		resultInArg0: true,
3543		clobberFlags: true,
3544		asm:          x86.ASUBL,
3545		reg: regInfo{
3546			inputs: []inputInfo{
3547				{0, 239}, // AX CX DX BX BP SI DI
3548				{1, 239}, // AX CX DX BX BP SI DI
3549			},
3550			outputs: []outputInfo{
3551				{0, 239}, // AX CX DX BX BP SI DI
3552			},
3553		},
3554	},
3555	{
3556		name:         "SUBLconst",
3557		auxType:      auxInt32,
3558		argLen:       1,
3559		resultInArg0: true,
3560		clobberFlags: true,
3561		asm:          x86.ASUBL,
3562		reg: regInfo{
3563			inputs: []inputInfo{
3564				{0, 239}, // AX CX DX BX BP SI DI
3565			},
3566			outputs: []outputInfo{
3567				{0, 239}, // AX CX DX BX BP SI DI
3568			},
3569		},
3570	},
3571	{
3572		name:         "SUBLcarry",
3573		argLen:       2,
3574		resultInArg0: true,
3575		asm:          x86.ASUBL,
3576		reg: regInfo{
3577			inputs: []inputInfo{
3578				{0, 239}, // AX CX DX BX BP SI DI
3579				{1, 239}, // AX CX DX BX BP SI DI
3580			},
3581			outputs: []outputInfo{
3582				{1, 0},
3583				{0, 239}, // AX CX DX BX BP SI DI
3584			},
3585		},
3586	},
3587	{
3588		name:         "SUBLconstcarry",
3589		auxType:      auxInt32,
3590		argLen:       1,
3591		resultInArg0: true,
3592		asm:          x86.ASUBL,
3593		reg: regInfo{
3594			inputs: []inputInfo{
3595				{0, 239}, // AX CX DX BX BP SI DI
3596			},
3597			outputs: []outputInfo{
3598				{1, 0},
3599				{0, 239}, // AX CX DX BX BP SI DI
3600			},
3601		},
3602	},
3603	{
3604		name:         "SBBL",
3605		argLen:       3,
3606		resultInArg0: true,
3607		clobberFlags: true,
3608		asm:          x86.ASBBL,
3609		reg: regInfo{
3610			inputs: []inputInfo{
3611				{0, 239}, // AX CX DX BX BP SI DI
3612				{1, 239}, // AX CX DX BX BP SI DI
3613			},
3614			outputs: []outputInfo{
3615				{0, 239}, // AX CX DX BX BP SI DI
3616			},
3617		},
3618	},
3619	{
3620		name:         "SBBLconst",
3621		auxType:      auxInt32,
3622		argLen:       2,
3623		resultInArg0: true,
3624		clobberFlags: true,
3625		asm:          x86.ASBBL,
3626		reg: regInfo{
3627			inputs: []inputInfo{
3628				{0, 239}, // AX CX DX BX BP SI DI
3629			},
3630			outputs: []outputInfo{
3631				{0, 239}, // AX CX DX BX BP SI DI
3632			},
3633		},
3634	},
3635	{
3636		name:         "MULL",
3637		argLen:       2,
3638		commutative:  true,
3639		resultInArg0: true,
3640		clobberFlags: true,
3641		asm:          x86.AIMULL,
3642		reg: regInfo{
3643			inputs: []inputInfo{
3644				{0, 239}, // AX CX DX BX BP SI DI
3645				{1, 239}, // AX CX DX BX BP SI DI
3646			},
3647			outputs: []outputInfo{
3648				{0, 239}, // AX CX DX BX BP SI DI
3649			},
3650		},
3651	},
3652	{
3653		name:         "MULLconst",
3654		auxType:      auxInt32,
3655		argLen:       1,
3656		clobberFlags: true,
3657		asm:          x86.AIMUL3L,
3658		reg: regInfo{
3659			inputs: []inputInfo{
3660				{0, 239}, // AX CX DX BX BP SI DI
3661			},
3662			outputs: []outputInfo{
3663				{0, 239}, // AX CX DX BX BP SI DI
3664			},
3665		},
3666	},
3667	{
3668		name:         "MULLU",
3669		argLen:       2,
3670		commutative:  true,
3671		clobberFlags: true,
3672		asm:          x86.AMULL,
3673		reg: regInfo{
3674			inputs: []inputInfo{
3675				{0, 1},   // AX
3676				{1, 255}, // AX CX DX BX SP BP SI DI
3677			},
3678			clobbers: 4, // DX
3679			outputs: []outputInfo{
3680				{1, 0},
3681				{0, 1}, // AX
3682			},
3683		},
3684	},
3685	{
3686		name:         "HMULL",
3687		argLen:       2,
3688		commutative:  true,
3689		clobberFlags: true,
3690		asm:          x86.AIMULL,
3691		reg: regInfo{
3692			inputs: []inputInfo{
3693				{0, 1},   // AX
3694				{1, 255}, // AX CX DX BX SP BP SI DI
3695			},
3696			clobbers: 1, // AX
3697			outputs: []outputInfo{
3698				{0, 4}, // DX
3699			},
3700		},
3701	},
3702	{
3703		name:         "HMULLU",
3704		argLen:       2,
3705		commutative:  true,
3706		clobberFlags: true,
3707		asm:          x86.AMULL,
3708		reg: regInfo{
3709			inputs: []inputInfo{
3710				{0, 1},   // AX
3711				{1, 255}, // AX CX DX BX SP BP SI DI
3712			},
3713			clobbers: 1, // AX
3714			outputs: []outputInfo{
3715				{0, 4}, // DX
3716			},
3717		},
3718	},
3719	{
3720		name:         "MULLQU",
3721		argLen:       2,
3722		commutative:  true,
3723		clobberFlags: true,
3724		asm:          x86.AMULL,
3725		reg: regInfo{
3726			inputs: []inputInfo{
3727				{0, 1},   // AX
3728				{1, 255}, // AX CX DX BX SP BP SI DI
3729			},
3730			outputs: []outputInfo{
3731				{0, 4}, // DX
3732				{1, 1}, // AX
3733			},
3734		},
3735	},
3736	{
3737		name:         "AVGLU",
3738		argLen:       2,
3739		commutative:  true,
3740		resultInArg0: true,
3741		clobberFlags: true,
3742		reg: regInfo{
3743			inputs: []inputInfo{
3744				{0, 239}, // AX CX DX BX BP SI DI
3745				{1, 239}, // AX CX DX BX BP SI DI
3746			},
3747			outputs: []outputInfo{
3748				{0, 239}, // AX CX DX BX BP SI DI
3749			},
3750		},
3751	},
3752	{
3753		name:         "DIVL",
3754		auxType:      auxBool,
3755		argLen:       2,
3756		clobberFlags: true,
3757		asm:          x86.AIDIVL,
3758		reg: regInfo{
3759			inputs: []inputInfo{
3760				{0, 1},   // AX
3761				{1, 251}, // AX CX BX SP BP SI DI
3762			},
3763			clobbers: 4, // DX
3764			outputs: []outputInfo{
3765				{0, 1}, // AX
3766			},
3767		},
3768	},
3769	{
3770		name:         "DIVW",
3771		auxType:      auxBool,
3772		argLen:       2,
3773		clobberFlags: true,
3774		asm:          x86.AIDIVW,
3775		reg: regInfo{
3776			inputs: []inputInfo{
3777				{0, 1},   // AX
3778				{1, 251}, // AX CX BX SP BP SI DI
3779			},
3780			clobbers: 4, // DX
3781			outputs: []outputInfo{
3782				{0, 1}, // AX
3783			},
3784		},
3785	},
3786	{
3787		name:         "DIVLU",
3788		argLen:       2,
3789		clobberFlags: true,
3790		asm:          x86.ADIVL,
3791		reg: regInfo{
3792			inputs: []inputInfo{
3793				{0, 1},   // AX
3794				{1, 251}, // AX CX BX SP BP SI DI
3795			},
3796			clobbers: 4, // DX
3797			outputs: []outputInfo{
3798				{0, 1}, // AX
3799			},
3800		},
3801	},
3802	{
3803		name:         "DIVWU",
3804		argLen:       2,
3805		clobberFlags: true,
3806		asm:          x86.ADIVW,
3807		reg: regInfo{
3808			inputs: []inputInfo{
3809				{0, 1},   // AX
3810				{1, 251}, // AX CX BX SP BP SI DI
3811			},
3812			clobbers: 4, // DX
3813			outputs: []outputInfo{
3814				{0, 1}, // AX
3815			},
3816		},
3817	},
3818	{
3819		name:         "MODL",
3820		auxType:      auxBool,
3821		argLen:       2,
3822		clobberFlags: true,
3823		asm:          x86.AIDIVL,
3824		reg: regInfo{
3825			inputs: []inputInfo{
3826				{0, 1},   // AX
3827				{1, 251}, // AX CX BX SP BP SI DI
3828			},
3829			clobbers: 1, // AX
3830			outputs: []outputInfo{
3831				{0, 4}, // DX
3832			},
3833		},
3834	},
3835	{
3836		name:         "MODW",
3837		auxType:      auxBool,
3838		argLen:       2,
3839		clobberFlags: true,
3840		asm:          x86.AIDIVW,
3841		reg: regInfo{
3842			inputs: []inputInfo{
3843				{0, 1},   // AX
3844				{1, 251}, // AX CX BX SP BP SI DI
3845			},
3846			clobbers: 1, // AX
3847			outputs: []outputInfo{
3848				{0, 4}, // DX
3849			},
3850		},
3851	},
3852	{
3853		name:         "MODLU",
3854		argLen:       2,
3855		clobberFlags: true,
3856		asm:          x86.ADIVL,
3857		reg: regInfo{
3858			inputs: []inputInfo{
3859				{0, 1},   // AX
3860				{1, 251}, // AX CX BX SP BP SI DI
3861			},
3862			clobbers: 1, // AX
3863			outputs: []outputInfo{
3864				{0, 4}, // DX
3865			},
3866		},
3867	},
3868	{
3869		name:         "MODWU",
3870		argLen:       2,
3871		clobberFlags: true,
3872		asm:          x86.ADIVW,
3873		reg: regInfo{
3874			inputs: []inputInfo{
3875				{0, 1},   // AX
3876				{1, 251}, // AX CX BX SP BP SI DI
3877			},
3878			clobbers: 1, // AX
3879			outputs: []outputInfo{
3880				{0, 4}, // DX
3881			},
3882		},
3883	},
3884	{
3885		name:         "ANDL",
3886		argLen:       2,
3887		commutative:  true,
3888		resultInArg0: true,
3889		clobberFlags: true,
3890		asm:          x86.AANDL,
3891		reg: regInfo{
3892			inputs: []inputInfo{
3893				{0, 239}, // AX CX DX BX BP SI DI
3894				{1, 239}, // AX CX DX BX BP SI DI
3895			},
3896			outputs: []outputInfo{
3897				{0, 239}, // AX CX DX BX BP SI DI
3898			},
3899		},
3900	},
3901	{
3902		name:         "ANDLconst",
3903		auxType:      auxInt32,
3904		argLen:       1,
3905		resultInArg0: true,
3906		clobberFlags: true,
3907		asm:          x86.AANDL,
3908		reg: regInfo{
3909			inputs: []inputInfo{
3910				{0, 239}, // AX CX DX BX BP SI DI
3911			},
3912			outputs: []outputInfo{
3913				{0, 239}, // AX CX DX BX BP SI DI
3914			},
3915		},
3916	},
3917	{
3918		name:         "ORL",
3919		argLen:       2,
3920		commutative:  true,
3921		resultInArg0: true,
3922		clobberFlags: true,
3923		asm:          x86.AORL,
3924		reg: regInfo{
3925			inputs: []inputInfo{
3926				{0, 239}, // AX CX DX BX BP SI DI
3927				{1, 239}, // AX CX DX BX BP SI DI
3928			},
3929			outputs: []outputInfo{
3930				{0, 239}, // AX CX DX BX BP SI DI
3931			},
3932		},
3933	},
3934	{
3935		name:         "ORLconst",
3936		auxType:      auxInt32,
3937		argLen:       1,
3938		resultInArg0: true,
3939		clobberFlags: true,
3940		asm:          x86.AORL,
3941		reg: regInfo{
3942			inputs: []inputInfo{
3943				{0, 239}, // AX CX DX BX BP SI DI
3944			},
3945			outputs: []outputInfo{
3946				{0, 239}, // AX CX DX BX BP SI DI
3947			},
3948		},
3949	},
3950	{
3951		name:         "XORL",
3952		argLen:       2,
3953		commutative:  true,
3954		resultInArg0: true,
3955		clobberFlags: true,
3956		asm:          x86.AXORL,
3957		reg: regInfo{
3958			inputs: []inputInfo{
3959				{0, 239}, // AX CX DX BX BP SI DI
3960				{1, 239}, // AX CX DX BX BP SI DI
3961			},
3962			outputs: []outputInfo{
3963				{0, 239}, // AX CX DX BX BP SI DI
3964			},
3965		},
3966	},
3967	{
3968		name:         "XORLconst",
3969		auxType:      auxInt32,
3970		argLen:       1,
3971		resultInArg0: true,
3972		clobberFlags: true,
3973		asm:          x86.AXORL,
3974		reg: regInfo{
3975			inputs: []inputInfo{
3976				{0, 239}, // AX CX DX BX BP SI DI
3977			},
3978			outputs: []outputInfo{
3979				{0, 239}, // AX CX DX BX BP SI DI
3980			},
3981		},
3982	},
3983	{
3984		name:   "CMPL",
3985		argLen: 2,
3986		asm:    x86.ACMPL,
3987		reg: regInfo{
3988			inputs: []inputInfo{
3989				{0, 255}, // AX CX DX BX SP BP SI DI
3990				{1, 255}, // AX CX DX BX SP BP SI DI
3991			},
3992		},
3993	},
3994	{
3995		name:   "CMPW",
3996		argLen: 2,
3997		asm:    x86.ACMPW,
3998		reg: regInfo{
3999			inputs: []inputInfo{
4000				{0, 255}, // AX CX DX BX SP BP SI DI
4001				{1, 255}, // AX CX DX BX SP BP SI DI
4002			},
4003		},
4004	},
4005	{
4006		name:   "CMPB",
4007		argLen: 2,
4008		asm:    x86.ACMPB,
4009		reg: regInfo{
4010			inputs: []inputInfo{
4011				{0, 255}, // AX CX DX BX SP BP SI DI
4012				{1, 255}, // AX CX DX BX SP BP SI DI
4013			},
4014		},
4015	},
4016	{
4017		name:    "CMPLconst",
4018		auxType: auxInt32,
4019		argLen:  1,
4020		asm:     x86.ACMPL,
4021		reg: regInfo{
4022			inputs: []inputInfo{
4023				{0, 255}, // AX CX DX BX SP BP SI DI
4024			},
4025		},
4026	},
4027	{
4028		name:    "CMPWconst",
4029		auxType: auxInt16,
4030		argLen:  1,
4031		asm:     x86.ACMPW,
4032		reg: regInfo{
4033			inputs: []inputInfo{
4034				{0, 255}, // AX CX DX BX SP BP SI DI
4035			},
4036		},
4037	},
4038	{
4039		name:    "CMPBconst",
4040		auxType: auxInt8,
4041		argLen:  1,
4042		asm:     x86.ACMPB,
4043		reg: regInfo{
4044			inputs: []inputInfo{
4045				{0, 255}, // AX CX DX BX SP BP SI DI
4046			},
4047		},
4048	},
4049	{
4050		name:           "CMPLload",
4051		auxType:        auxSymOff,
4052		argLen:         3,
4053		faultOnNilArg0: true,
4054		symEffect:      SymRead,
4055		asm:            x86.ACMPL,
4056		reg: regInfo{
4057			inputs: []inputInfo{
4058				{1, 255},   // AX CX DX BX SP BP SI DI
4059				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4060			},
4061		},
4062	},
4063	{
4064		name:           "CMPWload",
4065		auxType:        auxSymOff,
4066		argLen:         3,
4067		faultOnNilArg0: true,
4068		symEffect:      SymRead,
4069		asm:            x86.ACMPW,
4070		reg: regInfo{
4071			inputs: []inputInfo{
4072				{1, 255},   // AX CX DX BX SP BP SI DI
4073				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4074			},
4075		},
4076	},
4077	{
4078		name:           "CMPBload",
4079		auxType:        auxSymOff,
4080		argLen:         3,
4081		faultOnNilArg0: true,
4082		symEffect:      SymRead,
4083		asm:            x86.ACMPB,
4084		reg: regInfo{
4085			inputs: []inputInfo{
4086				{1, 255},   // AX CX DX BX SP BP SI DI
4087				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4088			},
4089		},
4090	},
4091	{
4092		name:           "CMPLconstload",
4093		auxType:        auxSymValAndOff,
4094		argLen:         2,
4095		faultOnNilArg0: true,
4096		symEffect:      SymRead,
4097		asm:            x86.ACMPL,
4098		reg: regInfo{
4099			inputs: []inputInfo{
4100				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4101			},
4102		},
4103	},
4104	{
4105		name:           "CMPWconstload",
4106		auxType:        auxSymValAndOff,
4107		argLen:         2,
4108		faultOnNilArg0: true,
4109		symEffect:      SymRead,
4110		asm:            x86.ACMPW,
4111		reg: regInfo{
4112			inputs: []inputInfo{
4113				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4114			},
4115		},
4116	},
4117	{
4118		name:           "CMPBconstload",
4119		auxType:        auxSymValAndOff,
4120		argLen:         2,
4121		faultOnNilArg0: true,
4122		symEffect:      SymRead,
4123		asm:            x86.ACMPB,
4124		reg: regInfo{
4125			inputs: []inputInfo{
4126				{0, 65791}, // AX CX DX BX SP BP SI DI SB
4127			},
4128		},
4129	},
4130	{
4131		name:   "UCOMISS",
4132		argLen: 2,
4133		asm:    x86.AUCOMISS,
4134		reg: regInfo{
4135			inputs: []inputInfo{
4136				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4137				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4138			},
4139		},
4140	},
4141	{
4142		name:   "UCOMISD",
4143		argLen: 2,
4144		asm:    x86.AUCOMISD,
4145		reg: regInfo{
4146			inputs: []inputInfo{
4147				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4148				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4149			},
4150		},
4151	},
4152	{
4153		name:        "TESTL",
4154		argLen:      2,
4155		commutative: true,
4156		asm:         x86.ATESTL,
4157		reg: regInfo{
4158			inputs: []inputInfo{
4159				{0, 255}, // AX CX DX BX SP BP SI DI
4160				{1, 255}, // AX CX DX BX SP BP SI DI
4161			},
4162		},
4163	},
4164	{
4165		name:        "TESTW",
4166		argLen:      2,
4167		commutative: true,
4168		asm:         x86.ATESTW,
4169		reg: regInfo{
4170			inputs: []inputInfo{
4171				{0, 255}, // AX CX DX BX SP BP SI DI
4172				{1, 255}, // AX CX DX BX SP BP SI DI
4173			},
4174		},
4175	},
4176	{
4177		name:        "TESTB",
4178		argLen:      2,
4179		commutative: true,
4180		asm:         x86.ATESTB,
4181		reg: regInfo{
4182			inputs: []inputInfo{
4183				{0, 255}, // AX CX DX BX SP BP SI DI
4184				{1, 255}, // AX CX DX BX SP BP SI DI
4185			},
4186		},
4187	},
4188	{
4189		name:    "TESTLconst",
4190		auxType: auxInt32,
4191		argLen:  1,
4192		asm:     x86.ATESTL,
4193		reg: regInfo{
4194			inputs: []inputInfo{
4195				{0, 255}, // AX CX DX BX SP BP SI DI
4196			},
4197		},
4198	},
4199	{
4200		name:    "TESTWconst",
4201		auxType: auxInt16,
4202		argLen:  1,
4203		asm:     x86.ATESTW,
4204		reg: regInfo{
4205			inputs: []inputInfo{
4206				{0, 255}, // AX CX DX BX SP BP SI DI
4207			},
4208		},
4209	},
4210	{
4211		name:    "TESTBconst",
4212		auxType: auxInt8,
4213		argLen:  1,
4214		asm:     x86.ATESTB,
4215		reg: regInfo{
4216			inputs: []inputInfo{
4217				{0, 255}, // AX CX DX BX SP BP SI DI
4218			},
4219		},
4220	},
4221	{
4222		name:         "SHLL",
4223		argLen:       2,
4224		resultInArg0: true,
4225		clobberFlags: true,
4226		asm:          x86.ASHLL,
4227		reg: regInfo{
4228			inputs: []inputInfo{
4229				{1, 2},   // CX
4230				{0, 239}, // AX CX DX BX BP SI DI
4231			},
4232			outputs: []outputInfo{
4233				{0, 239}, // AX CX DX BX BP SI DI
4234			},
4235		},
4236	},
4237	{
4238		name:         "SHLLconst",
4239		auxType:      auxInt32,
4240		argLen:       1,
4241		resultInArg0: true,
4242		clobberFlags: true,
4243		asm:          x86.ASHLL,
4244		reg: regInfo{
4245			inputs: []inputInfo{
4246				{0, 239}, // AX CX DX BX BP SI DI
4247			},
4248			outputs: []outputInfo{
4249				{0, 239}, // AX CX DX BX BP SI DI
4250			},
4251		},
4252	},
4253	{
4254		name:         "SHRL",
4255		argLen:       2,
4256		resultInArg0: true,
4257		clobberFlags: true,
4258		asm:          x86.ASHRL,
4259		reg: regInfo{
4260			inputs: []inputInfo{
4261				{1, 2},   // CX
4262				{0, 239}, // AX CX DX BX BP SI DI
4263			},
4264			outputs: []outputInfo{
4265				{0, 239}, // AX CX DX BX BP SI DI
4266			},
4267		},
4268	},
4269	{
4270		name:         "SHRW",
4271		argLen:       2,
4272		resultInArg0: true,
4273		clobberFlags: true,
4274		asm:          x86.ASHRW,
4275		reg: regInfo{
4276			inputs: []inputInfo{
4277				{1, 2},   // CX
4278				{0, 239}, // AX CX DX BX BP SI DI
4279			},
4280			outputs: []outputInfo{
4281				{0, 239}, // AX CX DX BX BP SI DI
4282			},
4283		},
4284	},
4285	{
4286		name:         "SHRB",
4287		argLen:       2,
4288		resultInArg0: true,
4289		clobberFlags: true,
4290		asm:          x86.ASHRB,
4291		reg: regInfo{
4292			inputs: []inputInfo{
4293				{1, 2},   // CX
4294				{0, 239}, // AX CX DX BX BP SI DI
4295			},
4296			outputs: []outputInfo{
4297				{0, 239}, // AX CX DX BX BP SI DI
4298			},
4299		},
4300	},
4301	{
4302		name:         "SHRLconst",
4303		auxType:      auxInt32,
4304		argLen:       1,
4305		resultInArg0: true,
4306		clobberFlags: true,
4307		asm:          x86.ASHRL,
4308		reg: regInfo{
4309			inputs: []inputInfo{
4310				{0, 239}, // AX CX DX BX BP SI DI
4311			},
4312			outputs: []outputInfo{
4313				{0, 239}, // AX CX DX BX BP SI DI
4314			},
4315		},
4316	},
4317	{
4318		name:         "SHRWconst",
4319		auxType:      auxInt16,
4320		argLen:       1,
4321		resultInArg0: true,
4322		clobberFlags: true,
4323		asm:          x86.ASHRW,
4324		reg: regInfo{
4325			inputs: []inputInfo{
4326				{0, 239}, // AX CX DX BX BP SI DI
4327			},
4328			outputs: []outputInfo{
4329				{0, 239}, // AX CX DX BX BP SI DI
4330			},
4331		},
4332	},
4333	{
4334		name:         "SHRBconst",
4335		auxType:      auxInt8,
4336		argLen:       1,
4337		resultInArg0: true,
4338		clobberFlags: true,
4339		asm:          x86.ASHRB,
4340		reg: regInfo{
4341			inputs: []inputInfo{
4342				{0, 239}, // AX CX DX BX BP SI DI
4343			},
4344			outputs: []outputInfo{
4345				{0, 239}, // AX CX DX BX BP SI DI
4346			},
4347		},
4348	},
4349	{
4350		name:         "SARL",
4351		argLen:       2,
4352		resultInArg0: true,
4353		clobberFlags: true,
4354		asm:          x86.ASARL,
4355		reg: regInfo{
4356			inputs: []inputInfo{
4357				{1, 2},   // CX
4358				{0, 239}, // AX CX DX BX BP SI DI
4359			},
4360			outputs: []outputInfo{
4361				{0, 239}, // AX CX DX BX BP SI DI
4362			},
4363		},
4364	},
4365	{
4366		name:         "SARW",
4367		argLen:       2,
4368		resultInArg0: true,
4369		clobberFlags: true,
4370		asm:          x86.ASARW,
4371		reg: regInfo{
4372			inputs: []inputInfo{
4373				{1, 2},   // CX
4374				{0, 239}, // AX CX DX BX BP SI DI
4375			},
4376			outputs: []outputInfo{
4377				{0, 239}, // AX CX DX BX BP SI DI
4378			},
4379		},
4380	},
4381	{
4382		name:         "SARB",
4383		argLen:       2,
4384		resultInArg0: true,
4385		clobberFlags: true,
4386		asm:          x86.ASARB,
4387		reg: regInfo{
4388			inputs: []inputInfo{
4389				{1, 2},   // CX
4390				{0, 239}, // AX CX DX BX BP SI DI
4391			},
4392			outputs: []outputInfo{
4393				{0, 239}, // AX CX DX BX BP SI DI
4394			},
4395		},
4396	},
4397	{
4398		name:         "SARLconst",
4399		auxType:      auxInt32,
4400		argLen:       1,
4401		resultInArg0: true,
4402		clobberFlags: true,
4403		asm:          x86.ASARL,
4404		reg: regInfo{
4405			inputs: []inputInfo{
4406				{0, 239}, // AX CX DX BX BP SI DI
4407			},
4408			outputs: []outputInfo{
4409				{0, 239}, // AX CX DX BX BP SI DI
4410			},
4411		},
4412	},
4413	{
4414		name:         "SARWconst",
4415		auxType:      auxInt16,
4416		argLen:       1,
4417		resultInArg0: true,
4418		clobberFlags: true,
4419		asm:          x86.ASARW,
4420		reg: regInfo{
4421			inputs: []inputInfo{
4422				{0, 239}, // AX CX DX BX BP SI DI
4423			},
4424			outputs: []outputInfo{
4425				{0, 239}, // AX CX DX BX BP SI DI
4426			},
4427		},
4428	},
4429	{
4430		name:         "SARBconst",
4431		auxType:      auxInt8,
4432		argLen:       1,
4433		resultInArg0: true,
4434		clobberFlags: true,
4435		asm:          x86.ASARB,
4436		reg: regInfo{
4437			inputs: []inputInfo{
4438				{0, 239}, // AX CX DX BX BP SI DI
4439			},
4440			outputs: []outputInfo{
4441				{0, 239}, // AX CX DX BX BP SI DI
4442			},
4443		},
4444	},
4445	{
4446		name:         "ROLLconst",
4447		auxType:      auxInt32,
4448		argLen:       1,
4449		resultInArg0: true,
4450		clobberFlags: true,
4451		asm:          x86.AROLL,
4452		reg: regInfo{
4453			inputs: []inputInfo{
4454				{0, 239}, // AX CX DX BX BP SI DI
4455			},
4456			outputs: []outputInfo{
4457				{0, 239}, // AX CX DX BX BP SI DI
4458			},
4459		},
4460	},
4461	{
4462		name:         "ROLWconst",
4463		auxType:      auxInt16,
4464		argLen:       1,
4465		resultInArg0: true,
4466		clobberFlags: true,
4467		asm:          x86.AROLW,
4468		reg: regInfo{
4469			inputs: []inputInfo{
4470				{0, 239}, // AX CX DX BX BP SI DI
4471			},
4472			outputs: []outputInfo{
4473				{0, 239}, // AX CX DX BX BP SI DI
4474			},
4475		},
4476	},
4477	{
4478		name:         "ROLBconst",
4479		auxType:      auxInt8,
4480		argLen:       1,
4481		resultInArg0: true,
4482		clobberFlags: true,
4483		asm:          x86.AROLB,
4484		reg: regInfo{
4485			inputs: []inputInfo{
4486				{0, 239}, // AX CX DX BX BP SI DI
4487			},
4488			outputs: []outputInfo{
4489				{0, 239}, // AX CX DX BX BP SI DI
4490			},
4491		},
4492	},
4493	{
4494		name:           "ADDLload",
4495		auxType:        auxSymOff,
4496		argLen:         3,
4497		resultInArg0:   true,
4498		clobberFlags:   true,
4499		faultOnNilArg1: true,
4500		symEffect:      SymRead,
4501		asm:            x86.AADDL,
4502		reg: regInfo{
4503			inputs: []inputInfo{
4504				{0, 239},   // AX CX DX BX BP SI DI
4505				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4506			},
4507			outputs: []outputInfo{
4508				{0, 239}, // AX CX DX BX BP SI DI
4509			},
4510		},
4511	},
4512	{
4513		name:           "SUBLload",
4514		auxType:        auxSymOff,
4515		argLen:         3,
4516		resultInArg0:   true,
4517		clobberFlags:   true,
4518		faultOnNilArg1: true,
4519		symEffect:      SymRead,
4520		asm:            x86.ASUBL,
4521		reg: regInfo{
4522			inputs: []inputInfo{
4523				{0, 239},   // AX CX DX BX BP SI DI
4524				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4525			},
4526			outputs: []outputInfo{
4527				{0, 239}, // AX CX DX BX BP SI DI
4528			},
4529		},
4530	},
4531	{
4532		name:           "MULLload",
4533		auxType:        auxSymOff,
4534		argLen:         3,
4535		resultInArg0:   true,
4536		clobberFlags:   true,
4537		faultOnNilArg1: true,
4538		symEffect:      SymRead,
4539		asm:            x86.AIMULL,
4540		reg: regInfo{
4541			inputs: []inputInfo{
4542				{0, 239},   // AX CX DX BX BP SI DI
4543				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4544			},
4545			outputs: []outputInfo{
4546				{0, 239}, // AX CX DX BX BP SI DI
4547			},
4548		},
4549	},
4550	{
4551		name:           "ANDLload",
4552		auxType:        auxSymOff,
4553		argLen:         3,
4554		resultInArg0:   true,
4555		clobberFlags:   true,
4556		faultOnNilArg1: true,
4557		symEffect:      SymRead,
4558		asm:            x86.AANDL,
4559		reg: regInfo{
4560			inputs: []inputInfo{
4561				{0, 239},   // AX CX DX BX BP SI DI
4562				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4563			},
4564			outputs: []outputInfo{
4565				{0, 239}, // AX CX DX BX BP SI DI
4566			},
4567		},
4568	},
4569	{
4570		name:           "ORLload",
4571		auxType:        auxSymOff,
4572		argLen:         3,
4573		resultInArg0:   true,
4574		clobberFlags:   true,
4575		faultOnNilArg1: true,
4576		symEffect:      SymRead,
4577		asm:            x86.AORL,
4578		reg: regInfo{
4579			inputs: []inputInfo{
4580				{0, 239},   // AX CX DX BX BP SI DI
4581				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4582			},
4583			outputs: []outputInfo{
4584				{0, 239}, // AX CX DX BX BP SI DI
4585			},
4586		},
4587	},
4588	{
4589		name:           "XORLload",
4590		auxType:        auxSymOff,
4591		argLen:         3,
4592		resultInArg0:   true,
4593		clobberFlags:   true,
4594		faultOnNilArg1: true,
4595		symEffect:      SymRead,
4596		asm:            x86.AXORL,
4597		reg: regInfo{
4598			inputs: []inputInfo{
4599				{0, 239},   // AX CX DX BX BP SI DI
4600				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4601			},
4602			outputs: []outputInfo{
4603				{0, 239}, // AX CX DX BX BP SI DI
4604			},
4605		},
4606	},
4607	{
4608		name:         "ADDLloadidx4",
4609		auxType:      auxSymOff,
4610		argLen:       4,
4611		resultInArg0: true,
4612		clobberFlags: true,
4613		symEffect:    SymRead,
4614		asm:          x86.AADDL,
4615		reg: regInfo{
4616			inputs: []inputInfo{
4617				{0, 239},   // AX CX DX BX BP SI DI
4618				{2, 255},   // AX CX DX BX SP BP SI DI
4619				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4620			},
4621			outputs: []outputInfo{
4622				{0, 239}, // AX CX DX BX BP SI DI
4623			},
4624		},
4625	},
4626	{
4627		name:         "SUBLloadidx4",
4628		auxType:      auxSymOff,
4629		argLen:       4,
4630		resultInArg0: true,
4631		clobberFlags: true,
4632		symEffect:    SymRead,
4633		asm:          x86.ASUBL,
4634		reg: regInfo{
4635			inputs: []inputInfo{
4636				{0, 239},   // AX CX DX BX BP SI DI
4637				{2, 255},   // AX CX DX BX SP BP SI DI
4638				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4639			},
4640			outputs: []outputInfo{
4641				{0, 239}, // AX CX DX BX BP SI DI
4642			},
4643		},
4644	},
4645	{
4646		name:         "MULLloadidx4",
4647		auxType:      auxSymOff,
4648		argLen:       4,
4649		resultInArg0: true,
4650		clobberFlags: true,
4651		symEffect:    SymRead,
4652		asm:          x86.AIMULL,
4653		reg: regInfo{
4654			inputs: []inputInfo{
4655				{0, 239},   // AX CX DX BX BP SI DI
4656				{2, 255},   // AX CX DX BX SP BP SI DI
4657				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4658			},
4659			outputs: []outputInfo{
4660				{0, 239}, // AX CX DX BX BP SI DI
4661			},
4662		},
4663	},
4664	{
4665		name:         "ANDLloadidx4",
4666		auxType:      auxSymOff,
4667		argLen:       4,
4668		resultInArg0: true,
4669		clobberFlags: true,
4670		symEffect:    SymRead,
4671		asm:          x86.AANDL,
4672		reg: regInfo{
4673			inputs: []inputInfo{
4674				{0, 239},   // AX CX DX BX BP SI DI
4675				{2, 255},   // AX CX DX BX SP BP SI DI
4676				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4677			},
4678			outputs: []outputInfo{
4679				{0, 239}, // AX CX DX BX BP SI DI
4680			},
4681		},
4682	},
4683	{
4684		name:         "ORLloadidx4",
4685		auxType:      auxSymOff,
4686		argLen:       4,
4687		resultInArg0: true,
4688		clobberFlags: true,
4689		symEffect:    SymRead,
4690		asm:          x86.AORL,
4691		reg: regInfo{
4692			inputs: []inputInfo{
4693				{0, 239},   // AX CX DX BX BP SI DI
4694				{2, 255},   // AX CX DX BX SP BP SI DI
4695				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4696			},
4697			outputs: []outputInfo{
4698				{0, 239}, // AX CX DX BX BP SI DI
4699			},
4700		},
4701	},
4702	{
4703		name:         "XORLloadidx4",
4704		auxType:      auxSymOff,
4705		argLen:       4,
4706		resultInArg0: true,
4707		clobberFlags: true,
4708		symEffect:    SymRead,
4709		asm:          x86.AXORL,
4710		reg: regInfo{
4711			inputs: []inputInfo{
4712				{0, 239},   // AX CX DX BX BP SI DI
4713				{2, 255},   // AX CX DX BX SP BP SI DI
4714				{1, 65791}, // AX CX DX BX SP BP SI DI SB
4715			},
4716			outputs: []outputInfo{
4717				{0, 239}, // AX CX DX BX BP SI DI
4718			},
4719		},
4720	},
4721	{
4722		name:         "NEGL",
4723		argLen:       1,
4724		resultInArg0: true,
4725		clobberFlags: true,
4726		asm:          x86.ANEGL,
4727		reg: regInfo{
4728			inputs: []inputInfo{
4729				{0, 239}, // AX CX DX BX BP SI DI
4730			},
4731			outputs: []outputInfo{
4732				{0, 239}, // AX CX DX BX BP SI DI
4733			},
4734		},
4735	},
4736	{
4737		name:         "NOTL",
4738		argLen:       1,
4739		resultInArg0: true,
4740		asm:          x86.ANOTL,
4741		reg: regInfo{
4742			inputs: []inputInfo{
4743				{0, 239}, // AX CX DX BX BP SI DI
4744			},
4745			outputs: []outputInfo{
4746				{0, 239}, // AX CX DX BX BP SI DI
4747			},
4748		},
4749	},
4750	{
4751		name:         "BSFL",
4752		argLen:       1,
4753		clobberFlags: true,
4754		asm:          x86.ABSFL,
4755		reg: regInfo{
4756			inputs: []inputInfo{
4757				{0, 239}, // AX CX DX BX BP SI DI
4758			},
4759			outputs: []outputInfo{
4760				{0, 239}, // AX CX DX BX BP SI DI
4761			},
4762		},
4763	},
4764	{
4765		name:         "BSFW",
4766		argLen:       1,
4767		clobberFlags: true,
4768		asm:          x86.ABSFW,
4769		reg: regInfo{
4770			inputs: []inputInfo{
4771				{0, 239}, // AX CX DX BX BP SI DI
4772			},
4773			outputs: []outputInfo{
4774				{0, 239}, // AX CX DX BX BP SI DI
4775			},
4776		},
4777	},
4778	{
4779		name:         "BSRL",
4780		argLen:       1,
4781		clobberFlags: true,
4782		asm:          x86.ABSRL,
4783		reg: regInfo{
4784			inputs: []inputInfo{
4785				{0, 239}, // AX CX DX BX BP SI DI
4786			},
4787			outputs: []outputInfo{
4788				{0, 239}, // AX CX DX BX BP SI DI
4789			},
4790		},
4791	},
4792	{
4793		name:         "BSRW",
4794		argLen:       1,
4795		clobberFlags: true,
4796		asm:          x86.ABSRW,
4797		reg: regInfo{
4798			inputs: []inputInfo{
4799				{0, 239}, // AX CX DX BX BP SI DI
4800			},
4801			outputs: []outputInfo{
4802				{0, 239}, // AX CX DX BX BP SI DI
4803			},
4804		},
4805	},
4806	{
4807		name:         "BSWAPL",
4808		argLen:       1,
4809		resultInArg0: true,
4810		clobberFlags: true,
4811		asm:          x86.ABSWAPL,
4812		reg: regInfo{
4813			inputs: []inputInfo{
4814				{0, 239}, // AX CX DX BX BP SI DI
4815			},
4816			outputs: []outputInfo{
4817				{0, 239}, // AX CX DX BX BP SI DI
4818			},
4819		},
4820	},
4821	{
4822		name:   "SQRTSD",
4823		argLen: 1,
4824		asm:    x86.ASQRTSD,
4825		reg: regInfo{
4826			inputs: []inputInfo{
4827				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4828			},
4829			outputs: []outputInfo{
4830				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4831			},
4832		},
4833	},
4834	{
4835		name:   "SQRTSS",
4836		argLen: 1,
4837		asm:    x86.ASQRTSS,
4838		reg: regInfo{
4839			inputs: []inputInfo{
4840				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4841			},
4842			outputs: []outputInfo{
4843				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
4844			},
4845		},
4846	},
4847	{
4848		name:   "SBBLcarrymask",
4849		argLen: 1,
4850		asm:    x86.ASBBL,
4851		reg: regInfo{
4852			outputs: []outputInfo{
4853				{0, 239}, // AX CX DX BX BP SI DI
4854			},
4855		},
4856	},
4857	{
4858		name:   "SETEQ",
4859		argLen: 1,
4860		asm:    x86.ASETEQ,
4861		reg: regInfo{
4862			outputs: []outputInfo{
4863				{0, 239}, // AX CX DX BX BP SI DI
4864			},
4865		},
4866	},
4867	{
4868		name:   "SETNE",
4869		argLen: 1,
4870		asm:    x86.ASETNE,
4871		reg: regInfo{
4872			outputs: []outputInfo{
4873				{0, 239}, // AX CX DX BX BP SI DI
4874			},
4875		},
4876	},
4877	{
4878		name:   "SETL",
4879		argLen: 1,
4880		asm:    x86.ASETLT,
4881		reg: regInfo{
4882			outputs: []outputInfo{
4883				{0, 239}, // AX CX DX BX BP SI DI
4884			},
4885		},
4886	},
4887	{
4888		name:   "SETLE",
4889		argLen: 1,
4890		asm:    x86.ASETLE,
4891		reg: regInfo{
4892			outputs: []outputInfo{
4893				{0, 239}, // AX CX DX BX BP SI DI
4894			},
4895		},
4896	},
4897	{
4898		name:   "SETG",
4899		argLen: 1,
4900		asm:    x86.ASETGT,
4901		reg: regInfo{
4902			outputs: []outputInfo{
4903				{0, 239}, // AX CX DX BX BP SI DI
4904			},
4905		},
4906	},
4907	{
4908		name:   "SETGE",
4909		argLen: 1,
4910		asm:    x86.ASETGE,
4911		reg: regInfo{
4912			outputs: []outputInfo{
4913				{0, 239}, // AX CX DX BX BP SI DI
4914			},
4915		},
4916	},
4917	{
4918		name:   "SETB",
4919		argLen: 1,
4920		asm:    x86.ASETCS,
4921		reg: regInfo{
4922			outputs: []outputInfo{
4923				{0, 239}, // AX CX DX BX BP SI DI
4924			},
4925		},
4926	},
4927	{
4928		name:   "SETBE",
4929		argLen: 1,
4930		asm:    x86.ASETLS,
4931		reg: regInfo{
4932			outputs: []outputInfo{
4933				{0, 239}, // AX CX DX BX BP SI DI
4934			},
4935		},
4936	},
4937	{
4938		name:   "SETA",
4939		argLen: 1,
4940		asm:    x86.ASETHI,
4941		reg: regInfo{
4942			outputs: []outputInfo{
4943				{0, 239}, // AX CX DX BX BP SI DI
4944			},
4945		},
4946	},
4947	{
4948		name:   "SETAE",
4949		argLen: 1,
4950		asm:    x86.ASETCC,
4951		reg: regInfo{
4952			outputs: []outputInfo{
4953				{0, 239}, // AX CX DX BX BP SI DI
4954			},
4955		},
4956	},
4957	{
4958		name:   "SETO",
4959		argLen: 1,
4960		asm:    x86.ASETOS,
4961		reg: regInfo{
4962			outputs: []outputInfo{
4963				{0, 239}, // AX CX DX BX BP SI DI
4964			},
4965		},
4966	},
4967	{
4968		name:         "SETEQF",
4969		argLen:       1,
4970		clobberFlags: true,
4971		asm:          x86.ASETEQ,
4972		reg: regInfo{
4973			clobbers: 1, // AX
4974			outputs: []outputInfo{
4975				{0, 238}, // CX DX BX BP SI DI
4976			},
4977		},
4978	},
4979	{
4980		name:         "SETNEF",
4981		argLen:       1,
4982		clobberFlags: true,
4983		asm:          x86.ASETNE,
4984		reg: regInfo{
4985			clobbers: 1, // AX
4986			outputs: []outputInfo{
4987				{0, 238}, // CX DX BX BP SI DI
4988			},
4989		},
4990	},
4991	{
4992		name:   "SETORD",
4993		argLen: 1,
4994		asm:    x86.ASETPC,
4995		reg: regInfo{
4996			outputs: []outputInfo{
4997				{0, 239}, // AX CX DX BX BP SI DI
4998			},
4999		},
5000	},
5001	{
5002		name:   "SETNAN",
5003		argLen: 1,
5004		asm:    x86.ASETPS,
5005		reg: regInfo{
5006			outputs: []outputInfo{
5007				{0, 239}, // AX CX DX BX BP SI DI
5008			},
5009		},
5010	},
5011	{
5012		name:   "SETGF",
5013		argLen: 1,
5014		asm:    x86.ASETHI,
5015		reg: regInfo{
5016			outputs: []outputInfo{
5017				{0, 239}, // AX CX DX BX BP SI DI
5018			},
5019		},
5020	},
5021	{
5022		name:   "SETGEF",
5023		argLen: 1,
5024		asm:    x86.ASETCC,
5025		reg: regInfo{
5026			outputs: []outputInfo{
5027				{0, 239}, // AX CX DX BX BP SI DI
5028			},
5029		},
5030	},
5031	{
5032		name:   "MOVBLSX",
5033		argLen: 1,
5034		asm:    x86.AMOVBLSX,
5035		reg: regInfo{
5036			inputs: []inputInfo{
5037				{0, 239}, // AX CX DX BX BP SI DI
5038			},
5039			outputs: []outputInfo{
5040				{0, 239}, // AX CX DX BX BP SI DI
5041			},
5042		},
5043	},
5044	{
5045		name:   "MOVBLZX",
5046		argLen: 1,
5047		asm:    x86.AMOVBLZX,
5048		reg: regInfo{
5049			inputs: []inputInfo{
5050				{0, 239}, // AX CX DX BX BP SI DI
5051			},
5052			outputs: []outputInfo{
5053				{0, 239}, // AX CX DX BX BP SI DI
5054			},
5055		},
5056	},
5057	{
5058		name:   "MOVWLSX",
5059		argLen: 1,
5060		asm:    x86.AMOVWLSX,
5061		reg: regInfo{
5062			inputs: []inputInfo{
5063				{0, 239}, // AX CX DX BX BP SI DI
5064			},
5065			outputs: []outputInfo{
5066				{0, 239}, // AX CX DX BX BP SI DI
5067			},
5068		},
5069	},
5070	{
5071		name:   "MOVWLZX",
5072		argLen: 1,
5073		asm:    x86.AMOVWLZX,
5074		reg: regInfo{
5075			inputs: []inputInfo{
5076				{0, 239}, // AX CX DX BX BP SI DI
5077			},
5078			outputs: []outputInfo{
5079				{0, 239}, // AX CX DX BX BP SI DI
5080			},
5081		},
5082	},
5083	{
5084		name:              "MOVLconst",
5085		auxType:           auxInt32,
5086		argLen:            0,
5087		rematerializeable: true,
5088		asm:               x86.AMOVL,
5089		reg: regInfo{
5090			outputs: []outputInfo{
5091				{0, 239}, // AX CX DX BX BP SI DI
5092			},
5093		},
5094	},
5095	{
5096		name:   "CVTTSD2SL",
5097		argLen: 1,
5098		asm:    x86.ACVTTSD2SL,
5099		reg: regInfo{
5100			inputs: []inputInfo{
5101				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5102			},
5103			outputs: []outputInfo{
5104				{0, 239}, // AX CX DX BX BP SI DI
5105			},
5106		},
5107	},
5108	{
5109		name:   "CVTTSS2SL",
5110		argLen: 1,
5111		asm:    x86.ACVTTSS2SL,
5112		reg: regInfo{
5113			inputs: []inputInfo{
5114				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5115			},
5116			outputs: []outputInfo{
5117				{0, 239}, // AX CX DX BX BP SI DI
5118			},
5119		},
5120	},
5121	{
5122		name:   "CVTSL2SS",
5123		argLen: 1,
5124		asm:    x86.ACVTSL2SS,
5125		reg: regInfo{
5126			inputs: []inputInfo{
5127				{0, 239}, // AX CX DX BX BP SI DI
5128			},
5129			outputs: []outputInfo{
5130				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5131			},
5132		},
5133	},
5134	{
5135		name:   "CVTSL2SD",
5136		argLen: 1,
5137		asm:    x86.ACVTSL2SD,
5138		reg: regInfo{
5139			inputs: []inputInfo{
5140				{0, 239}, // AX CX DX BX BP SI DI
5141			},
5142			outputs: []outputInfo{
5143				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5144			},
5145		},
5146	},
5147	{
5148		name:   "CVTSD2SS",
5149		argLen: 1,
5150		asm:    x86.ACVTSD2SS,
5151		reg: regInfo{
5152			inputs: []inputInfo{
5153				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5154			},
5155			outputs: []outputInfo{
5156				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5157			},
5158		},
5159	},
5160	{
5161		name:   "CVTSS2SD",
5162		argLen: 1,
5163		asm:    x86.ACVTSS2SD,
5164		reg: regInfo{
5165			inputs: []inputInfo{
5166				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5167			},
5168			outputs: []outputInfo{
5169				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5170			},
5171		},
5172	},
5173	{
5174		name:         "PXOR",
5175		argLen:       2,
5176		commutative:  true,
5177		resultInArg0: true,
5178		asm:          x86.APXOR,
5179		reg: regInfo{
5180			inputs: []inputInfo{
5181				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5182				{1, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5183			},
5184			outputs: []outputInfo{
5185				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
5186			},
5187		},
5188	},
5189	{
5190		name:              "LEAL",
5191		auxType:           auxSymOff,
5192		argLen:            1,
5193		rematerializeable: true,
5194		symEffect:         SymAddr,
5195		reg: regInfo{
5196			inputs: []inputInfo{
5197				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5198			},
5199			outputs: []outputInfo{
5200				{0, 239}, // AX CX DX BX BP SI DI
5201			},
5202		},
5203	},
5204	{
5205		name:        "LEAL1",
5206		auxType:     auxSymOff,
5207		argLen:      2,
5208		commutative: true,
5209		symEffect:   SymAddr,
5210		reg: regInfo{
5211			inputs: []inputInfo{
5212				{1, 255},   // AX CX DX BX SP BP SI DI
5213				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5214			},
5215			outputs: []outputInfo{
5216				{0, 239}, // AX CX DX BX BP SI DI
5217			},
5218		},
5219	},
5220	{
5221		name:      "LEAL2",
5222		auxType:   auxSymOff,
5223		argLen:    2,
5224		symEffect: SymAddr,
5225		reg: regInfo{
5226			inputs: []inputInfo{
5227				{1, 255},   // AX CX DX BX SP BP SI DI
5228				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5229			},
5230			outputs: []outputInfo{
5231				{0, 239}, // AX CX DX BX BP SI DI
5232			},
5233		},
5234	},
5235	{
5236		name:      "LEAL4",
5237		auxType:   auxSymOff,
5238		argLen:    2,
5239		symEffect: SymAddr,
5240		reg: regInfo{
5241			inputs: []inputInfo{
5242				{1, 255},   // AX CX DX BX SP BP SI DI
5243				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5244			},
5245			outputs: []outputInfo{
5246				{0, 239}, // AX CX DX BX BP SI DI
5247			},
5248		},
5249	},
5250	{
5251		name:      "LEAL8",
5252		auxType:   auxSymOff,
5253		argLen:    2,
5254		symEffect: SymAddr,
5255		reg: regInfo{
5256			inputs: []inputInfo{
5257				{1, 255},   // AX CX DX BX SP BP SI DI
5258				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5259			},
5260			outputs: []outputInfo{
5261				{0, 239}, // AX CX DX BX BP SI DI
5262			},
5263		},
5264	},
5265	{
5266		name:           "MOVBload",
5267		auxType:        auxSymOff,
5268		argLen:         2,
5269		faultOnNilArg0: true,
5270		symEffect:      SymRead,
5271		asm:            x86.AMOVBLZX,
5272		reg: regInfo{
5273			inputs: []inputInfo{
5274				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5275			},
5276			outputs: []outputInfo{
5277				{0, 239}, // AX CX DX BX BP SI DI
5278			},
5279		},
5280	},
5281	{
5282		name:           "MOVBLSXload",
5283		auxType:        auxSymOff,
5284		argLen:         2,
5285		faultOnNilArg0: true,
5286		symEffect:      SymRead,
5287		asm:            x86.AMOVBLSX,
5288		reg: regInfo{
5289			inputs: []inputInfo{
5290				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5291			},
5292			outputs: []outputInfo{
5293				{0, 239}, // AX CX DX BX BP SI DI
5294			},
5295		},
5296	},
5297	{
5298		name:           "MOVWload",
5299		auxType:        auxSymOff,
5300		argLen:         2,
5301		faultOnNilArg0: true,
5302		symEffect:      SymRead,
5303		asm:            x86.AMOVWLZX,
5304		reg: regInfo{
5305			inputs: []inputInfo{
5306				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5307			},
5308			outputs: []outputInfo{
5309				{0, 239}, // AX CX DX BX BP SI DI
5310			},
5311		},
5312	},
5313	{
5314		name:           "MOVWLSXload",
5315		auxType:        auxSymOff,
5316		argLen:         2,
5317		faultOnNilArg0: true,
5318		symEffect:      SymRead,
5319		asm:            x86.AMOVWLSX,
5320		reg: regInfo{
5321			inputs: []inputInfo{
5322				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5323			},
5324			outputs: []outputInfo{
5325				{0, 239}, // AX CX DX BX BP SI DI
5326			},
5327		},
5328	},
5329	{
5330		name:           "MOVLload",
5331		auxType:        auxSymOff,
5332		argLen:         2,
5333		faultOnNilArg0: true,
5334		symEffect:      SymRead,
5335		asm:            x86.AMOVL,
5336		reg: regInfo{
5337			inputs: []inputInfo{
5338				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5339			},
5340			outputs: []outputInfo{
5341				{0, 239}, // AX CX DX BX BP SI DI
5342			},
5343		},
5344	},
5345	{
5346		name:           "MOVBstore",
5347		auxType:        auxSymOff,
5348		argLen:         3,
5349		faultOnNilArg0: true,
5350		symEffect:      SymWrite,
5351		asm:            x86.AMOVB,
5352		reg: regInfo{
5353			inputs: []inputInfo{
5354				{1, 255},   // AX CX DX BX SP BP SI DI
5355				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5356			},
5357		},
5358	},
5359	{
5360		name:           "MOVWstore",
5361		auxType:        auxSymOff,
5362		argLen:         3,
5363		faultOnNilArg0: true,
5364		symEffect:      SymWrite,
5365		asm:            x86.AMOVW,
5366		reg: regInfo{
5367			inputs: []inputInfo{
5368				{1, 255},   // AX CX DX BX SP BP SI DI
5369				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5370			},
5371		},
5372	},
5373	{
5374		name:           "MOVLstore",
5375		auxType:        auxSymOff,
5376		argLen:         3,
5377		faultOnNilArg0: true,
5378		symEffect:      SymWrite,
5379		asm:            x86.AMOVL,
5380		reg: regInfo{
5381			inputs: []inputInfo{
5382				{1, 255},   // AX CX DX BX SP BP SI DI
5383				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5384			},
5385		},
5386	},
5387	{
5388		name:           "ADDLmodify",
5389		auxType:        auxSymOff,
5390		argLen:         3,
5391		clobberFlags:   true,
5392		faultOnNilArg0: true,
5393		symEffect:      SymRead | SymWrite,
5394		asm:            x86.AADDL,
5395		reg: regInfo{
5396			inputs: []inputInfo{
5397				{1, 255},   // AX CX DX BX SP BP SI DI
5398				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5399			},
5400		},
5401	},
5402	{
5403		name:           "SUBLmodify",
5404		auxType:        auxSymOff,
5405		argLen:         3,
5406		clobberFlags:   true,
5407		faultOnNilArg0: true,
5408		symEffect:      SymRead | SymWrite,
5409		asm:            x86.ASUBL,
5410		reg: regInfo{
5411			inputs: []inputInfo{
5412				{1, 255},   // AX CX DX BX SP BP SI DI
5413				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5414			},
5415		},
5416	},
5417	{
5418		name:           "ANDLmodify",
5419		auxType:        auxSymOff,
5420		argLen:         3,
5421		clobberFlags:   true,
5422		faultOnNilArg0: true,
5423		symEffect:      SymRead | SymWrite,
5424		asm:            x86.AANDL,
5425		reg: regInfo{
5426			inputs: []inputInfo{
5427				{1, 255},   // AX CX DX BX SP BP SI DI
5428				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5429			},
5430		},
5431	},
5432	{
5433		name:           "ORLmodify",
5434		auxType:        auxSymOff,
5435		argLen:         3,
5436		clobberFlags:   true,
5437		faultOnNilArg0: true,
5438		symEffect:      SymRead | SymWrite,
5439		asm:            x86.AORL,
5440		reg: regInfo{
5441			inputs: []inputInfo{
5442				{1, 255},   // AX CX DX BX SP BP SI DI
5443				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5444			},
5445		},
5446	},
5447	{
5448		name:           "XORLmodify",
5449		auxType:        auxSymOff,
5450		argLen:         3,
5451		clobberFlags:   true,
5452		faultOnNilArg0: true,
5453		symEffect:      SymRead | SymWrite,
5454		asm:            x86.AXORL,
5455		reg: regInfo{
5456			inputs: []inputInfo{
5457				{1, 255},   // AX CX DX BX SP BP SI DI
5458				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5459			},
5460		},
5461	},
5462	{
5463		name:         "ADDLmodifyidx4",
5464		auxType:      auxSymOff,
5465		argLen:       4,
5466		clobberFlags: true,
5467		symEffect:    SymRead | SymWrite,
5468		asm:          x86.AADDL,
5469		reg: regInfo{
5470			inputs: []inputInfo{
5471				{1, 255},   // AX CX DX BX SP BP SI DI
5472				{2, 255},   // AX CX DX BX SP BP SI DI
5473				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5474			},
5475		},
5476	},
5477	{
5478		name:         "SUBLmodifyidx4",
5479		auxType:      auxSymOff,
5480		argLen:       4,
5481		clobberFlags: true,
5482		symEffect:    SymRead | SymWrite,
5483		asm:          x86.ASUBL,
5484		reg: regInfo{
5485			inputs: []inputInfo{
5486				{1, 255},   // AX CX DX BX SP BP SI DI
5487				{2, 255},   // AX CX DX BX SP BP SI DI
5488				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5489			},
5490		},
5491	},
5492	{
5493		name:         "ANDLmodifyidx4",
5494		auxType:      auxSymOff,
5495		argLen:       4,
5496		clobberFlags: true,
5497		symEffect:    SymRead | SymWrite,
5498		asm:          x86.AANDL,
5499		reg: regInfo{
5500			inputs: []inputInfo{
5501				{1, 255},   // AX CX DX BX SP BP SI DI
5502				{2, 255},   // AX CX DX BX SP BP SI DI
5503				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5504			},
5505		},
5506	},
5507	{
5508		name:         "ORLmodifyidx4",
5509		auxType:      auxSymOff,
5510		argLen:       4,
5511		clobberFlags: true,
5512		symEffect:    SymRead | SymWrite,
5513		asm:          x86.AORL,
5514		reg: regInfo{
5515			inputs: []inputInfo{
5516				{1, 255},   // AX CX DX BX SP BP SI DI
5517				{2, 255},   // AX CX DX BX SP BP SI DI
5518				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5519			},
5520		},
5521	},
5522	{
5523		name:         "XORLmodifyidx4",
5524		auxType:      auxSymOff,
5525		argLen:       4,
5526		clobberFlags: true,
5527		symEffect:    SymRead | SymWrite,
5528		asm:          x86.AXORL,
5529		reg: regInfo{
5530			inputs: []inputInfo{
5531				{1, 255},   // AX CX DX BX SP BP SI DI
5532				{2, 255},   // AX CX DX BX SP BP SI DI
5533				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5534			},
5535		},
5536	},
5537	{
5538		name:           "ADDLconstmodify",
5539		auxType:        auxSymValAndOff,
5540		argLen:         2,
5541		clobberFlags:   true,
5542		faultOnNilArg0: true,
5543		symEffect:      SymRead | SymWrite,
5544		asm:            x86.AADDL,
5545		reg: regInfo{
5546			inputs: []inputInfo{
5547				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5548			},
5549		},
5550	},
5551	{
5552		name:           "ANDLconstmodify",
5553		auxType:        auxSymValAndOff,
5554		argLen:         2,
5555		clobberFlags:   true,
5556		faultOnNilArg0: true,
5557		symEffect:      SymRead | SymWrite,
5558		asm:            x86.AANDL,
5559		reg: regInfo{
5560			inputs: []inputInfo{
5561				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5562			},
5563		},
5564	},
5565	{
5566		name:           "ORLconstmodify",
5567		auxType:        auxSymValAndOff,
5568		argLen:         2,
5569		clobberFlags:   true,
5570		faultOnNilArg0: true,
5571		symEffect:      SymRead | SymWrite,
5572		asm:            x86.AORL,
5573		reg: regInfo{
5574			inputs: []inputInfo{
5575				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5576			},
5577		},
5578	},
5579	{
5580		name:           "XORLconstmodify",
5581		auxType:        auxSymValAndOff,
5582		argLen:         2,
5583		clobberFlags:   true,
5584		faultOnNilArg0: true,
5585		symEffect:      SymRead | SymWrite,
5586		asm:            x86.AXORL,
5587		reg: regInfo{
5588			inputs: []inputInfo{
5589				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5590			},
5591		},
5592	},
5593	{
5594		name:         "ADDLconstmodifyidx4",
5595		auxType:      auxSymValAndOff,
5596		argLen:       3,
5597		clobberFlags: true,
5598		symEffect:    SymRead | SymWrite,
5599		asm:          x86.AADDL,
5600		reg: regInfo{
5601			inputs: []inputInfo{
5602				{1, 255},   // AX CX DX BX SP BP SI DI
5603				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5604			},
5605		},
5606	},
5607	{
5608		name:         "ANDLconstmodifyidx4",
5609		auxType:      auxSymValAndOff,
5610		argLen:       3,
5611		clobberFlags: true,
5612		symEffect:    SymRead | SymWrite,
5613		asm:          x86.AANDL,
5614		reg: regInfo{
5615			inputs: []inputInfo{
5616				{1, 255},   // AX CX DX BX SP BP SI DI
5617				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5618			},
5619		},
5620	},
5621	{
5622		name:         "ORLconstmodifyidx4",
5623		auxType:      auxSymValAndOff,
5624		argLen:       3,
5625		clobberFlags: true,
5626		symEffect:    SymRead | SymWrite,
5627		asm:          x86.AORL,
5628		reg: regInfo{
5629			inputs: []inputInfo{
5630				{1, 255},   // AX CX DX BX SP BP SI DI
5631				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5632			},
5633		},
5634	},
5635	{
5636		name:         "XORLconstmodifyidx4",
5637		auxType:      auxSymValAndOff,
5638		argLen:       3,
5639		clobberFlags: true,
5640		symEffect:    SymRead | SymWrite,
5641		asm:          x86.AXORL,
5642		reg: regInfo{
5643			inputs: []inputInfo{
5644				{1, 255},   // AX CX DX BX SP BP SI DI
5645				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5646			},
5647		},
5648	},
5649	{
5650		name:        "MOVBloadidx1",
5651		auxType:     auxSymOff,
5652		argLen:      3,
5653		commutative: true,
5654		symEffect:   SymRead,
5655		asm:         x86.AMOVBLZX,
5656		reg: regInfo{
5657			inputs: []inputInfo{
5658				{1, 255},   // AX CX DX BX SP BP SI DI
5659				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5660			},
5661			outputs: []outputInfo{
5662				{0, 239}, // AX CX DX BX BP SI DI
5663			},
5664		},
5665	},
5666	{
5667		name:        "MOVWloadidx1",
5668		auxType:     auxSymOff,
5669		argLen:      3,
5670		commutative: true,
5671		symEffect:   SymRead,
5672		asm:         x86.AMOVWLZX,
5673		reg: regInfo{
5674			inputs: []inputInfo{
5675				{1, 255},   // AX CX DX BX SP BP SI DI
5676				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5677			},
5678			outputs: []outputInfo{
5679				{0, 239}, // AX CX DX BX BP SI DI
5680			},
5681		},
5682	},
5683	{
5684		name:      "MOVWloadidx2",
5685		auxType:   auxSymOff,
5686		argLen:    3,
5687		symEffect: SymRead,
5688		asm:       x86.AMOVWLZX,
5689		reg: regInfo{
5690			inputs: []inputInfo{
5691				{1, 255},   // AX CX DX BX SP BP SI DI
5692				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5693			},
5694			outputs: []outputInfo{
5695				{0, 239}, // AX CX DX BX BP SI DI
5696			},
5697		},
5698	},
5699	{
5700		name:        "MOVLloadidx1",
5701		auxType:     auxSymOff,
5702		argLen:      3,
5703		commutative: true,
5704		symEffect:   SymRead,
5705		asm:         x86.AMOVL,
5706		reg: regInfo{
5707			inputs: []inputInfo{
5708				{1, 255},   // AX CX DX BX SP BP SI DI
5709				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5710			},
5711			outputs: []outputInfo{
5712				{0, 239}, // AX CX DX BX BP SI DI
5713			},
5714		},
5715	},
5716	{
5717		name:      "MOVLloadidx4",
5718		auxType:   auxSymOff,
5719		argLen:    3,
5720		symEffect: SymRead,
5721		asm:       x86.AMOVL,
5722		reg: regInfo{
5723			inputs: []inputInfo{
5724				{1, 255},   // AX CX DX BX SP BP SI DI
5725				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5726			},
5727			outputs: []outputInfo{
5728				{0, 239}, // AX CX DX BX BP SI DI
5729			},
5730		},
5731	},
5732	{
5733		name:        "MOVBstoreidx1",
5734		auxType:     auxSymOff,
5735		argLen:      4,
5736		commutative: true,
5737		symEffect:   SymWrite,
5738		asm:         x86.AMOVB,
5739		reg: regInfo{
5740			inputs: []inputInfo{
5741				{1, 255},   // AX CX DX BX SP BP SI DI
5742				{2, 255},   // AX CX DX BX SP BP SI DI
5743				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5744			},
5745		},
5746	},
5747	{
5748		name:        "MOVWstoreidx1",
5749		auxType:     auxSymOff,
5750		argLen:      4,
5751		commutative: true,
5752		symEffect:   SymWrite,
5753		asm:         x86.AMOVW,
5754		reg: regInfo{
5755			inputs: []inputInfo{
5756				{1, 255},   // AX CX DX BX SP BP SI DI
5757				{2, 255},   // AX CX DX BX SP BP SI DI
5758				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5759			},
5760		},
5761	},
5762	{
5763		name:      "MOVWstoreidx2",
5764		auxType:   auxSymOff,
5765		argLen:    4,
5766		symEffect: SymWrite,
5767		asm:       x86.AMOVW,
5768		reg: regInfo{
5769			inputs: []inputInfo{
5770				{1, 255},   // AX CX DX BX SP BP SI DI
5771				{2, 255},   // AX CX DX BX SP BP SI DI
5772				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5773			},
5774		},
5775	},
5776	{
5777		name:        "MOVLstoreidx1",
5778		auxType:     auxSymOff,
5779		argLen:      4,
5780		commutative: true,
5781		symEffect:   SymWrite,
5782		asm:         x86.AMOVL,
5783		reg: regInfo{
5784			inputs: []inputInfo{
5785				{1, 255},   // AX CX DX BX SP BP SI DI
5786				{2, 255},   // AX CX DX BX SP BP SI DI
5787				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5788			},
5789		},
5790	},
5791	{
5792		name:      "MOVLstoreidx4",
5793		auxType:   auxSymOff,
5794		argLen:    4,
5795		symEffect: SymWrite,
5796		asm:       x86.AMOVL,
5797		reg: regInfo{
5798			inputs: []inputInfo{
5799				{1, 255},   // AX CX DX BX SP BP SI DI
5800				{2, 255},   // AX CX DX BX SP BP SI DI
5801				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5802			},
5803		},
5804	},
5805	{
5806		name:           "MOVBstoreconst",
5807		auxType:        auxSymValAndOff,
5808		argLen:         2,
5809		faultOnNilArg0: true,
5810		symEffect:      SymWrite,
5811		asm:            x86.AMOVB,
5812		reg: regInfo{
5813			inputs: []inputInfo{
5814				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5815			},
5816		},
5817	},
5818	{
5819		name:           "MOVWstoreconst",
5820		auxType:        auxSymValAndOff,
5821		argLen:         2,
5822		faultOnNilArg0: true,
5823		symEffect:      SymWrite,
5824		asm:            x86.AMOVW,
5825		reg: regInfo{
5826			inputs: []inputInfo{
5827				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5828			},
5829		},
5830	},
5831	{
5832		name:           "MOVLstoreconst",
5833		auxType:        auxSymValAndOff,
5834		argLen:         2,
5835		faultOnNilArg0: true,
5836		symEffect:      SymWrite,
5837		asm:            x86.AMOVL,
5838		reg: regInfo{
5839			inputs: []inputInfo{
5840				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5841			},
5842		},
5843	},
5844	{
5845		name:      "MOVBstoreconstidx1",
5846		auxType:   auxSymValAndOff,
5847		argLen:    3,
5848		symEffect: SymWrite,
5849		asm:       x86.AMOVB,
5850		reg: regInfo{
5851			inputs: []inputInfo{
5852				{1, 255},   // AX CX DX BX SP BP SI DI
5853				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5854			},
5855		},
5856	},
5857	{
5858		name:      "MOVWstoreconstidx1",
5859		auxType:   auxSymValAndOff,
5860		argLen:    3,
5861		symEffect: SymWrite,
5862		asm:       x86.AMOVW,
5863		reg: regInfo{
5864			inputs: []inputInfo{
5865				{1, 255},   // AX CX DX BX SP BP SI DI
5866				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5867			},
5868		},
5869	},
5870	{
5871		name:      "MOVWstoreconstidx2",
5872		auxType:   auxSymValAndOff,
5873		argLen:    3,
5874		symEffect: SymWrite,
5875		asm:       x86.AMOVW,
5876		reg: regInfo{
5877			inputs: []inputInfo{
5878				{1, 255},   // AX CX DX BX SP BP SI DI
5879				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5880			},
5881		},
5882	},
5883	{
5884		name:      "MOVLstoreconstidx1",
5885		auxType:   auxSymValAndOff,
5886		argLen:    3,
5887		symEffect: SymWrite,
5888		asm:       x86.AMOVL,
5889		reg: regInfo{
5890			inputs: []inputInfo{
5891				{1, 255},   // AX CX DX BX SP BP SI DI
5892				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5893			},
5894		},
5895	},
5896	{
5897		name:      "MOVLstoreconstidx4",
5898		auxType:   auxSymValAndOff,
5899		argLen:    3,
5900		symEffect: SymWrite,
5901		asm:       x86.AMOVL,
5902		reg: regInfo{
5903			inputs: []inputInfo{
5904				{1, 255},   // AX CX DX BX SP BP SI DI
5905				{0, 65791}, // AX CX DX BX SP BP SI DI SB
5906			},
5907		},
5908	},
5909	{
5910		name:           "DUFFZERO",
5911		auxType:        auxInt64,
5912		argLen:         3,
5913		faultOnNilArg0: true,
5914		reg: regInfo{
5915			inputs: []inputInfo{
5916				{0, 128}, // DI
5917				{1, 1},   // AX
5918			},
5919			clobbers: 130, // CX DI
5920		},
5921	},
5922	{
5923		name:           "REPSTOSL",
5924		argLen:         4,
5925		faultOnNilArg0: true,
5926		reg: regInfo{
5927			inputs: []inputInfo{
5928				{0, 128}, // DI
5929				{1, 2},   // CX
5930				{2, 1},   // AX
5931			},
5932			clobbers: 130, // CX DI
5933		},
5934	},
5935	{
5936		name:         "CALLstatic",
5937		auxType:      auxCallOff,
5938		argLen:       1,
5939		clobberFlags: true,
5940		call:         true,
5941		reg: regInfo{
5942			clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
5943		},
5944	},
5945	{
5946		name:         "CALLtail",
5947		auxType:      auxCallOff,
5948		argLen:       1,
5949		clobberFlags: true,
5950		call:         true,
5951		tailCall:     true,
5952		reg: regInfo{
5953			clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
5954		},
5955	},
5956	{
5957		name:         "CALLclosure",
5958		auxType:      auxCallOff,
5959		argLen:       3,
5960		clobberFlags: true,
5961		call:         true,
5962		reg: regInfo{
5963			inputs: []inputInfo{
5964				{1, 4},   // DX
5965				{0, 255}, // AX CX DX BX SP BP SI DI
5966			},
5967			clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
5968		},
5969	},
5970	{
5971		name:         "CALLinter",
5972		auxType:      auxCallOff,
5973		argLen:       2,
5974		clobberFlags: true,
5975		call:         true,
5976		reg: regInfo{
5977			inputs: []inputInfo{
5978				{0, 239}, // AX CX DX BX BP SI DI
5979			},
5980			clobbers: 65519, // AX CX DX BX BP SI DI X0 X1 X2 X3 X4 X5 X6 X7
5981		},
5982	},
5983	{
5984		name:           "DUFFCOPY",
5985		auxType:        auxInt64,
5986		argLen:         3,
5987		clobberFlags:   true,
5988		faultOnNilArg0: true,
5989		faultOnNilArg1: true,
5990		reg: regInfo{
5991			inputs: []inputInfo{
5992				{0, 128}, // DI
5993				{1, 64},  // SI
5994			},
5995			clobbers: 194, // CX SI DI
5996		},
5997	},
5998	{
5999		name:           "REPMOVSL",
6000		argLen:         4,
6001		faultOnNilArg0: true,
6002		faultOnNilArg1: true,
6003		reg: regInfo{
6004			inputs: []inputInfo{
6005				{0, 128}, // DI
6006				{1, 64},  // SI
6007				{2, 2},   // CX
6008			},
6009			clobbers: 194, // CX SI DI
6010		},
6011	},
6012	{
6013		name:   "InvertFlags",
6014		argLen: 1,
6015		reg:    regInfo{},
6016	},
6017	{
6018		name:   "LoweredGetG",
6019		argLen: 1,
6020		reg: regInfo{
6021			outputs: []outputInfo{
6022				{0, 239}, // AX CX DX BX BP SI DI
6023			},
6024		},
6025	},
6026	{
6027		name:      "LoweredGetClosurePtr",
6028		argLen:    0,
6029		zeroWidth: true,
6030		reg: regInfo{
6031			outputs: []outputInfo{
6032				{0, 4}, // DX
6033			},
6034		},
6035	},
6036	{
6037		name:              "LoweredGetCallerPC",
6038		argLen:            0,
6039		rematerializeable: true,
6040		reg: regInfo{
6041			outputs: []outputInfo{
6042				{0, 239}, // AX CX DX BX BP SI DI
6043			},
6044		},
6045	},
6046	{
6047		name:              "LoweredGetCallerSP",
6048		argLen:            0,
6049		rematerializeable: true,
6050		reg: regInfo{
6051			outputs: []outputInfo{
6052				{0, 239}, // AX CX DX BX BP SI DI
6053			},
6054		},
6055	},
6056	{
6057		name:           "LoweredNilCheck",
6058		argLen:         2,
6059		clobberFlags:   true,
6060		nilCheck:       true,
6061		faultOnNilArg0: true,
6062		reg: regInfo{
6063			inputs: []inputInfo{
6064				{0, 255}, // AX CX DX BX SP BP SI DI
6065			},
6066		},
6067	},
6068	{
6069		name:         "LoweredWB",
6070		auxType:      auxSym,
6071		argLen:       3,
6072		clobberFlags: true,
6073		symEffect:    SymNone,
6074		reg: regInfo{
6075			inputs: []inputInfo{
6076				{0, 128}, // DI
6077				{1, 1},   // AX
6078			},
6079			clobbers: 65280, // X0 X1 X2 X3 X4 X5 X6 X7
6080		},
6081	},
6082	{
6083		name:    "LoweredPanicBoundsA",
6084		auxType: auxInt64,
6085		argLen:  3,
6086		call:    true,
6087		reg: regInfo{
6088			inputs: []inputInfo{
6089				{0, 4}, // DX
6090				{1, 8}, // BX
6091			},
6092		},
6093	},
6094	{
6095		name:    "LoweredPanicBoundsB",
6096		auxType: auxInt64,
6097		argLen:  3,
6098		call:    true,
6099		reg: regInfo{
6100			inputs: []inputInfo{
6101				{0, 2}, // CX
6102				{1, 4}, // DX
6103			},
6104		},
6105	},
6106	{
6107		name:    "LoweredPanicBoundsC",
6108		auxType: auxInt64,
6109		argLen:  3,
6110		call:    true,
6111		reg: regInfo{
6112			inputs: []inputInfo{
6113				{0, 1}, // AX
6114				{1, 2}, // CX
6115			},
6116		},
6117	},
6118	{
6119		name:    "LoweredPanicExtendA",
6120		auxType: auxInt64,
6121		argLen:  4,
6122		call:    true,
6123		reg: regInfo{
6124			inputs: []inputInfo{
6125				{0, 64}, // SI
6126				{1, 4},  // DX
6127				{2, 8},  // BX
6128			},
6129		},
6130	},
6131	{
6132		name:    "LoweredPanicExtendB",
6133		auxType: auxInt64,
6134		argLen:  4,
6135		call:    true,
6136		reg: regInfo{
6137			inputs: []inputInfo{
6138				{0, 64}, // SI
6139				{1, 2},  // CX
6140				{2, 4},  // DX
6141			},
6142		},
6143	},
6144	{
6145		name:    "LoweredPanicExtendC",
6146		auxType: auxInt64,
6147		argLen:  4,
6148		call:    true,
6149		reg: regInfo{
6150			inputs: []inputInfo{
6151				{0, 64}, // SI
6152				{1, 1},  // AX
6153				{2, 2},  // CX
6154			},
6155		},
6156	},
6157	{
6158		name:   "FlagEQ",
6159		argLen: 0,
6160		reg:    regInfo{},
6161	},
6162	{
6163		name:   "FlagLT_ULT",
6164		argLen: 0,
6165		reg:    regInfo{},
6166	},
6167	{
6168		name:   "FlagLT_UGT",
6169		argLen: 0,
6170		reg:    regInfo{},
6171	},
6172	{
6173		name:   "FlagGT_UGT",
6174		argLen: 0,
6175		reg:    regInfo{},
6176	},
6177	{
6178		name:   "FlagGT_ULT",
6179		argLen: 0,
6180		reg:    regInfo{},
6181	},
6182	{
6183		name:    "MOVSSconst1",
6184		auxType: auxFloat32,
6185		argLen:  0,
6186		reg: regInfo{
6187			outputs: []outputInfo{
6188				{0, 239}, // AX CX DX BX BP SI DI
6189			},
6190		},
6191	},
6192	{
6193		name:    "MOVSDconst1",
6194		auxType: auxFloat64,
6195		argLen:  0,
6196		reg: regInfo{
6197			outputs: []outputInfo{
6198				{0, 239}, // AX CX DX BX BP SI DI
6199			},
6200		},
6201	},
6202	{
6203		name:   "MOVSSconst2",
6204		argLen: 1,
6205		asm:    x86.AMOVSS,
6206		reg: regInfo{
6207			inputs: []inputInfo{
6208				{0, 239}, // AX CX DX BX BP SI DI
6209			},
6210			outputs: []outputInfo{
6211				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
6212			},
6213		},
6214	},
6215	{
6216		name:   "MOVSDconst2",
6217		argLen: 1,
6218		asm:    x86.AMOVSD,
6219		reg: regInfo{
6220			inputs: []inputInfo{
6221				{0, 239}, // AX CX DX BX BP SI DI
6222			},
6223			outputs: []outputInfo{
6224				{0, 65280}, // X0 X1 X2 X3 X4 X5 X6 X7
6225			},
6226		},
6227	},
6228
6229	{
6230		name:         "ADDSS",
6231		argLen:       2,
6232		commutative:  true,
6233		resultInArg0: true,
6234		asm:          x86.AADDSS,
6235		reg: regInfo{
6236			inputs: []inputInfo{
6237				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6238				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6239			},
6240			outputs: []outputInfo{
6241				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6242			},
6243		},
6244	},
6245	{
6246		name:         "ADDSD",
6247		argLen:       2,
6248		commutative:  true,
6249		resultInArg0: true,
6250		asm:          x86.AADDSD,
6251		reg: regInfo{
6252			inputs: []inputInfo{
6253				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6254				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6255			},
6256			outputs: []outputInfo{
6257				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6258			},
6259		},
6260	},
6261	{
6262		name:         "SUBSS",
6263		argLen:       2,
6264		resultInArg0: true,
6265		asm:          x86.ASUBSS,
6266		reg: regInfo{
6267			inputs: []inputInfo{
6268				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6269				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6270			},
6271			outputs: []outputInfo{
6272				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6273			},
6274		},
6275	},
6276	{
6277		name:         "SUBSD",
6278		argLen:       2,
6279		resultInArg0: true,
6280		asm:          x86.ASUBSD,
6281		reg: regInfo{
6282			inputs: []inputInfo{
6283				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6284				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6285			},
6286			outputs: []outputInfo{
6287				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6288			},
6289		},
6290	},
6291	{
6292		name:         "MULSS",
6293		argLen:       2,
6294		commutative:  true,
6295		resultInArg0: true,
6296		asm:          x86.AMULSS,
6297		reg: regInfo{
6298			inputs: []inputInfo{
6299				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6300				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6301			},
6302			outputs: []outputInfo{
6303				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6304			},
6305		},
6306	},
6307	{
6308		name:         "MULSD",
6309		argLen:       2,
6310		commutative:  true,
6311		resultInArg0: true,
6312		asm:          x86.AMULSD,
6313		reg: regInfo{
6314			inputs: []inputInfo{
6315				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6316				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6317			},
6318			outputs: []outputInfo{
6319				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6320			},
6321		},
6322	},
6323	{
6324		name:         "DIVSS",
6325		argLen:       2,
6326		resultInArg0: true,
6327		asm:          x86.ADIVSS,
6328		reg: regInfo{
6329			inputs: []inputInfo{
6330				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6331				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6332			},
6333			outputs: []outputInfo{
6334				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6335			},
6336		},
6337	},
6338	{
6339		name:         "DIVSD",
6340		argLen:       2,
6341		resultInArg0: true,
6342		asm:          x86.ADIVSD,
6343		reg: regInfo{
6344			inputs: []inputInfo{
6345				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6346				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6347			},
6348			outputs: []outputInfo{
6349				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6350			},
6351		},
6352	},
6353	{
6354		name:           "MOVSSload",
6355		auxType:        auxSymOff,
6356		argLen:         2,
6357		faultOnNilArg0: true,
6358		symEffect:      SymRead,
6359		asm:            x86.AMOVSS,
6360		reg: regInfo{
6361			inputs: []inputInfo{
6362				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6363			},
6364			outputs: []outputInfo{
6365				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6366			},
6367		},
6368	},
6369	{
6370		name:           "MOVSDload",
6371		auxType:        auxSymOff,
6372		argLen:         2,
6373		faultOnNilArg0: true,
6374		symEffect:      SymRead,
6375		asm:            x86.AMOVSD,
6376		reg: regInfo{
6377			inputs: []inputInfo{
6378				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6379			},
6380			outputs: []outputInfo{
6381				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6382			},
6383		},
6384	},
6385	{
6386		name:              "MOVSSconst",
6387		auxType:           auxFloat32,
6388		argLen:            0,
6389		rematerializeable: true,
6390		asm:               x86.AMOVSS,
6391		reg: regInfo{
6392			outputs: []outputInfo{
6393				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6394			},
6395		},
6396	},
6397	{
6398		name:              "MOVSDconst",
6399		auxType:           auxFloat64,
6400		argLen:            0,
6401		rematerializeable: true,
6402		asm:               x86.AMOVSD,
6403		reg: regInfo{
6404			outputs: []outputInfo{
6405				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6406			},
6407		},
6408	},
6409	{
6410		name:      "MOVSSloadidx1",
6411		auxType:   auxSymOff,
6412		argLen:    3,
6413		symEffect: SymRead,
6414		asm:       x86.AMOVSS,
6415		scale:     1,
6416		reg: regInfo{
6417			inputs: []inputInfo{
6418				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6419				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6420			},
6421			outputs: []outputInfo{
6422				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6423			},
6424		},
6425	},
6426	{
6427		name:      "MOVSSloadidx4",
6428		auxType:   auxSymOff,
6429		argLen:    3,
6430		symEffect: SymRead,
6431		asm:       x86.AMOVSS,
6432		scale:     4,
6433		reg: regInfo{
6434			inputs: []inputInfo{
6435				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6436				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6437			},
6438			outputs: []outputInfo{
6439				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6440			},
6441		},
6442	},
6443	{
6444		name:      "MOVSDloadidx1",
6445		auxType:   auxSymOff,
6446		argLen:    3,
6447		symEffect: SymRead,
6448		asm:       x86.AMOVSD,
6449		scale:     1,
6450		reg: regInfo{
6451			inputs: []inputInfo{
6452				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6453				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6454			},
6455			outputs: []outputInfo{
6456				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6457			},
6458		},
6459	},
6460	{
6461		name:      "MOVSDloadidx8",
6462		auxType:   auxSymOff,
6463		argLen:    3,
6464		symEffect: SymRead,
6465		asm:       x86.AMOVSD,
6466		scale:     8,
6467		reg: regInfo{
6468			inputs: []inputInfo{
6469				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6470				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6471			},
6472			outputs: []outputInfo{
6473				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6474			},
6475		},
6476	},
6477	{
6478		name:           "MOVSSstore",
6479		auxType:        auxSymOff,
6480		argLen:         3,
6481		faultOnNilArg0: true,
6482		symEffect:      SymWrite,
6483		asm:            x86.AMOVSS,
6484		reg: regInfo{
6485			inputs: []inputInfo{
6486				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6487				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6488			},
6489		},
6490	},
6491	{
6492		name:           "MOVSDstore",
6493		auxType:        auxSymOff,
6494		argLen:         3,
6495		faultOnNilArg0: true,
6496		symEffect:      SymWrite,
6497		asm:            x86.AMOVSD,
6498		reg: regInfo{
6499			inputs: []inputInfo{
6500				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6501				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6502			},
6503		},
6504	},
6505	{
6506		name:      "MOVSSstoreidx1",
6507		auxType:   auxSymOff,
6508		argLen:    4,
6509		symEffect: SymWrite,
6510		asm:       x86.AMOVSS,
6511		scale:     1,
6512		reg: regInfo{
6513			inputs: []inputInfo{
6514				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6515				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6516				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6517			},
6518		},
6519	},
6520	{
6521		name:      "MOVSSstoreidx4",
6522		auxType:   auxSymOff,
6523		argLen:    4,
6524		symEffect: SymWrite,
6525		asm:       x86.AMOVSS,
6526		scale:     4,
6527		reg: regInfo{
6528			inputs: []inputInfo{
6529				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6530				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6531				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6532			},
6533		},
6534	},
6535	{
6536		name:      "MOVSDstoreidx1",
6537		auxType:   auxSymOff,
6538		argLen:    4,
6539		symEffect: SymWrite,
6540		asm:       x86.AMOVSD,
6541		scale:     1,
6542		reg: regInfo{
6543			inputs: []inputInfo{
6544				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6545				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6546				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6547			},
6548		},
6549	},
6550	{
6551		name:      "MOVSDstoreidx8",
6552		auxType:   auxSymOff,
6553		argLen:    4,
6554		symEffect: SymWrite,
6555		asm:       x86.AMOVSD,
6556		scale:     8,
6557		reg: regInfo{
6558			inputs: []inputInfo{
6559				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
6560				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6561				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6562			},
6563		},
6564	},
6565	{
6566		name:           "ADDSSload",
6567		auxType:        auxSymOff,
6568		argLen:         3,
6569		resultInArg0:   true,
6570		faultOnNilArg1: true,
6571		symEffect:      SymRead,
6572		asm:            x86.AADDSS,
6573		reg: regInfo{
6574			inputs: []inputInfo{
6575				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6576				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6577			},
6578			outputs: []outputInfo{
6579				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6580			},
6581		},
6582	},
6583	{
6584		name:           "ADDSDload",
6585		auxType:        auxSymOff,
6586		argLen:         3,
6587		resultInArg0:   true,
6588		faultOnNilArg1: true,
6589		symEffect:      SymRead,
6590		asm:            x86.AADDSD,
6591		reg: regInfo{
6592			inputs: []inputInfo{
6593				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6594				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6595			},
6596			outputs: []outputInfo{
6597				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6598			},
6599		},
6600	},
6601	{
6602		name:           "SUBSSload",
6603		auxType:        auxSymOff,
6604		argLen:         3,
6605		resultInArg0:   true,
6606		faultOnNilArg1: true,
6607		symEffect:      SymRead,
6608		asm:            x86.ASUBSS,
6609		reg: regInfo{
6610			inputs: []inputInfo{
6611				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6612				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6613			},
6614			outputs: []outputInfo{
6615				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6616			},
6617		},
6618	},
6619	{
6620		name:           "SUBSDload",
6621		auxType:        auxSymOff,
6622		argLen:         3,
6623		resultInArg0:   true,
6624		faultOnNilArg1: true,
6625		symEffect:      SymRead,
6626		asm:            x86.ASUBSD,
6627		reg: regInfo{
6628			inputs: []inputInfo{
6629				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6630				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6631			},
6632			outputs: []outputInfo{
6633				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6634			},
6635		},
6636	},
6637	{
6638		name:           "MULSSload",
6639		auxType:        auxSymOff,
6640		argLen:         3,
6641		resultInArg0:   true,
6642		faultOnNilArg1: true,
6643		symEffect:      SymRead,
6644		asm:            x86.AMULSS,
6645		reg: regInfo{
6646			inputs: []inputInfo{
6647				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6648				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6649			},
6650			outputs: []outputInfo{
6651				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6652			},
6653		},
6654	},
6655	{
6656		name:           "MULSDload",
6657		auxType:        auxSymOff,
6658		argLen:         3,
6659		resultInArg0:   true,
6660		faultOnNilArg1: true,
6661		symEffect:      SymRead,
6662		asm:            x86.AMULSD,
6663		reg: regInfo{
6664			inputs: []inputInfo{
6665				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6666				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6667			},
6668			outputs: []outputInfo{
6669				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6670			},
6671		},
6672	},
6673	{
6674		name:           "DIVSSload",
6675		auxType:        auxSymOff,
6676		argLen:         3,
6677		resultInArg0:   true,
6678		faultOnNilArg1: true,
6679		symEffect:      SymRead,
6680		asm:            x86.ADIVSS,
6681		reg: regInfo{
6682			inputs: []inputInfo{
6683				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6684				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6685			},
6686			outputs: []outputInfo{
6687				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6688			},
6689		},
6690	},
6691	{
6692		name:           "DIVSDload",
6693		auxType:        auxSymOff,
6694		argLen:         3,
6695		resultInArg0:   true,
6696		faultOnNilArg1: true,
6697		symEffect:      SymRead,
6698		asm:            x86.ADIVSD,
6699		reg: regInfo{
6700			inputs: []inputInfo{
6701				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6702				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6703			},
6704			outputs: []outputInfo{
6705				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6706			},
6707		},
6708	},
6709	{
6710		name:         "ADDSSloadidx1",
6711		auxType:      auxSymOff,
6712		argLen:       4,
6713		resultInArg0: true,
6714		symEffect:    SymRead,
6715		asm:          x86.AADDSS,
6716		scale:        1,
6717		reg: regInfo{
6718			inputs: []inputInfo{
6719				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6720				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6721				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6722			},
6723			outputs: []outputInfo{
6724				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6725			},
6726		},
6727	},
6728	{
6729		name:         "ADDSSloadidx4",
6730		auxType:      auxSymOff,
6731		argLen:       4,
6732		resultInArg0: true,
6733		symEffect:    SymRead,
6734		asm:          x86.AADDSS,
6735		scale:        4,
6736		reg: regInfo{
6737			inputs: []inputInfo{
6738				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6739				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6740				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6741			},
6742			outputs: []outputInfo{
6743				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6744			},
6745		},
6746	},
6747	{
6748		name:         "ADDSDloadidx1",
6749		auxType:      auxSymOff,
6750		argLen:       4,
6751		resultInArg0: true,
6752		symEffect:    SymRead,
6753		asm:          x86.AADDSD,
6754		scale:        1,
6755		reg: regInfo{
6756			inputs: []inputInfo{
6757				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6758				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6759				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6760			},
6761			outputs: []outputInfo{
6762				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6763			},
6764		},
6765	},
6766	{
6767		name:         "ADDSDloadidx8",
6768		auxType:      auxSymOff,
6769		argLen:       4,
6770		resultInArg0: true,
6771		symEffect:    SymRead,
6772		asm:          x86.AADDSD,
6773		scale:        8,
6774		reg: regInfo{
6775			inputs: []inputInfo{
6776				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6777				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6778				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6779			},
6780			outputs: []outputInfo{
6781				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6782			},
6783		},
6784	},
6785	{
6786		name:         "SUBSSloadidx1",
6787		auxType:      auxSymOff,
6788		argLen:       4,
6789		resultInArg0: true,
6790		symEffect:    SymRead,
6791		asm:          x86.ASUBSS,
6792		scale:        1,
6793		reg: regInfo{
6794			inputs: []inputInfo{
6795				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6796				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6797				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6798			},
6799			outputs: []outputInfo{
6800				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6801			},
6802		},
6803	},
6804	{
6805		name:         "SUBSSloadidx4",
6806		auxType:      auxSymOff,
6807		argLen:       4,
6808		resultInArg0: true,
6809		symEffect:    SymRead,
6810		asm:          x86.ASUBSS,
6811		scale:        4,
6812		reg: regInfo{
6813			inputs: []inputInfo{
6814				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6815				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6816				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6817			},
6818			outputs: []outputInfo{
6819				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6820			},
6821		},
6822	},
6823	{
6824		name:         "SUBSDloadidx1",
6825		auxType:      auxSymOff,
6826		argLen:       4,
6827		resultInArg0: true,
6828		symEffect:    SymRead,
6829		asm:          x86.ASUBSD,
6830		scale:        1,
6831		reg: regInfo{
6832			inputs: []inputInfo{
6833				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6834				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6835				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6836			},
6837			outputs: []outputInfo{
6838				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6839			},
6840		},
6841	},
6842	{
6843		name:         "SUBSDloadidx8",
6844		auxType:      auxSymOff,
6845		argLen:       4,
6846		resultInArg0: true,
6847		symEffect:    SymRead,
6848		asm:          x86.ASUBSD,
6849		scale:        8,
6850		reg: regInfo{
6851			inputs: []inputInfo{
6852				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6853				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6854				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6855			},
6856			outputs: []outputInfo{
6857				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6858			},
6859		},
6860	},
6861	{
6862		name:         "MULSSloadidx1",
6863		auxType:      auxSymOff,
6864		argLen:       4,
6865		resultInArg0: true,
6866		symEffect:    SymRead,
6867		asm:          x86.AMULSS,
6868		scale:        1,
6869		reg: regInfo{
6870			inputs: []inputInfo{
6871				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6872				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6873				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6874			},
6875			outputs: []outputInfo{
6876				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6877			},
6878		},
6879	},
6880	{
6881		name:         "MULSSloadidx4",
6882		auxType:      auxSymOff,
6883		argLen:       4,
6884		resultInArg0: true,
6885		symEffect:    SymRead,
6886		asm:          x86.AMULSS,
6887		scale:        4,
6888		reg: regInfo{
6889			inputs: []inputInfo{
6890				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6891				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6892				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6893			},
6894			outputs: []outputInfo{
6895				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6896			},
6897		},
6898	},
6899	{
6900		name:         "MULSDloadidx1",
6901		auxType:      auxSymOff,
6902		argLen:       4,
6903		resultInArg0: true,
6904		symEffect:    SymRead,
6905		asm:          x86.AMULSD,
6906		scale:        1,
6907		reg: regInfo{
6908			inputs: []inputInfo{
6909				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6910				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6911				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6912			},
6913			outputs: []outputInfo{
6914				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6915			},
6916		},
6917	},
6918	{
6919		name:         "MULSDloadidx8",
6920		auxType:      auxSymOff,
6921		argLen:       4,
6922		resultInArg0: true,
6923		symEffect:    SymRead,
6924		asm:          x86.AMULSD,
6925		scale:        8,
6926		reg: regInfo{
6927			inputs: []inputInfo{
6928				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6929				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6930				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6931			},
6932			outputs: []outputInfo{
6933				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6934			},
6935		},
6936	},
6937	{
6938		name:         "DIVSSloadidx1",
6939		auxType:      auxSymOff,
6940		argLen:       4,
6941		resultInArg0: true,
6942		symEffect:    SymRead,
6943		asm:          x86.ADIVSS,
6944		scale:        1,
6945		reg: regInfo{
6946			inputs: []inputInfo{
6947				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6948				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6949				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6950			},
6951			outputs: []outputInfo{
6952				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6953			},
6954		},
6955	},
6956	{
6957		name:         "DIVSSloadidx4",
6958		auxType:      auxSymOff,
6959		argLen:       4,
6960		resultInArg0: true,
6961		symEffect:    SymRead,
6962		asm:          x86.ADIVSS,
6963		scale:        4,
6964		reg: regInfo{
6965			inputs: []inputInfo{
6966				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6967				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6968				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6969			},
6970			outputs: []outputInfo{
6971				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6972			},
6973		},
6974	},
6975	{
6976		name:         "DIVSDloadidx1",
6977		auxType:      auxSymOff,
6978		argLen:       4,
6979		resultInArg0: true,
6980		symEffect:    SymRead,
6981		asm:          x86.ADIVSD,
6982		scale:        1,
6983		reg: regInfo{
6984			inputs: []inputInfo{
6985				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6986				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
6987				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
6988			},
6989			outputs: []outputInfo{
6990				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
6991			},
6992		},
6993	},
6994	{
6995		name:         "DIVSDloadidx8",
6996		auxType:      auxSymOff,
6997		argLen:       4,
6998		resultInArg0: true,
6999		symEffect:    SymRead,
7000		asm:          x86.ADIVSD,
7001		scale:        8,
7002		reg: regInfo{
7003			inputs: []inputInfo{
7004				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7005				{2, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
7006				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7007			},
7008			outputs: []outputInfo{
7009				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
7010			},
7011		},
7012	},
7013	{
7014		name:         "ADDQ",
7015		argLen:       2,
7016		commutative:  true,
7017		clobberFlags: true,
7018		asm:          x86.AADDQ,
7019		reg: regInfo{
7020			inputs: []inputInfo{
7021				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7022				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7023			},
7024			outputs: []outputInfo{
7025				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7026			},
7027		},
7028	},
7029	{
7030		name:         "ADDL",
7031		argLen:       2,
7032		commutative:  true,
7033		clobberFlags: true,
7034		asm:          x86.AADDL,
7035		reg: regInfo{
7036			inputs: []inputInfo{
7037				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7038				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7039			},
7040			outputs: []outputInfo{
7041				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7042			},
7043		},
7044	},
7045	{
7046		name:         "ADDQconst",
7047		auxType:      auxInt32,
7048		argLen:       1,
7049		clobberFlags: true,
7050		asm:          x86.AADDQ,
7051		reg: regInfo{
7052			inputs: []inputInfo{
7053				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7054			},
7055			outputs: []outputInfo{
7056				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7057			},
7058		},
7059	},
7060	{
7061		name:         "ADDLconst",
7062		auxType:      auxInt32,
7063		argLen:       1,
7064		clobberFlags: true,
7065		asm:          x86.AADDL,
7066		reg: regInfo{
7067			inputs: []inputInfo{
7068				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7069			},
7070			outputs: []outputInfo{
7071				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7072			},
7073		},
7074	},
7075	{
7076		name:           "ADDQconstmodify",
7077		auxType:        auxSymValAndOff,
7078		argLen:         2,
7079		clobberFlags:   true,
7080		faultOnNilArg0: true,
7081		symEffect:      SymRead | SymWrite,
7082		asm:            x86.AADDQ,
7083		reg: regInfo{
7084			inputs: []inputInfo{
7085				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7086			},
7087		},
7088	},
7089	{
7090		name:           "ADDLconstmodify",
7091		auxType:        auxSymValAndOff,
7092		argLen:         2,
7093		clobberFlags:   true,
7094		faultOnNilArg0: true,
7095		symEffect:      SymRead | SymWrite,
7096		asm:            x86.AADDL,
7097		reg: regInfo{
7098			inputs: []inputInfo{
7099				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7100			},
7101		},
7102	},
7103	{
7104		name:         "SUBQ",
7105		argLen:       2,
7106		resultInArg0: true,
7107		clobberFlags: true,
7108		asm:          x86.ASUBQ,
7109		reg: regInfo{
7110			inputs: []inputInfo{
7111				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7112				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7113			},
7114			outputs: []outputInfo{
7115				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7116			},
7117		},
7118	},
7119	{
7120		name:         "SUBL",
7121		argLen:       2,
7122		resultInArg0: true,
7123		clobberFlags: true,
7124		asm:          x86.ASUBL,
7125		reg: regInfo{
7126			inputs: []inputInfo{
7127				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7128				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7129			},
7130			outputs: []outputInfo{
7131				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7132			},
7133		},
7134	},
7135	{
7136		name:         "SUBQconst",
7137		auxType:      auxInt32,
7138		argLen:       1,
7139		resultInArg0: true,
7140		clobberFlags: true,
7141		asm:          x86.ASUBQ,
7142		reg: regInfo{
7143			inputs: []inputInfo{
7144				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7145			},
7146			outputs: []outputInfo{
7147				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7148			},
7149		},
7150	},
7151	{
7152		name:         "SUBLconst",
7153		auxType:      auxInt32,
7154		argLen:       1,
7155		resultInArg0: true,
7156		clobberFlags: true,
7157		asm:          x86.ASUBL,
7158		reg: regInfo{
7159			inputs: []inputInfo{
7160				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7161			},
7162			outputs: []outputInfo{
7163				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7164			},
7165		},
7166	},
7167	{
7168		name:         "MULQ",
7169		argLen:       2,
7170		commutative:  true,
7171		resultInArg0: true,
7172		clobberFlags: true,
7173		asm:          x86.AIMULQ,
7174		reg: regInfo{
7175			inputs: []inputInfo{
7176				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7177				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7178			},
7179			outputs: []outputInfo{
7180				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7181			},
7182		},
7183	},
7184	{
7185		name:         "MULL",
7186		argLen:       2,
7187		commutative:  true,
7188		resultInArg0: true,
7189		clobberFlags: true,
7190		asm:          x86.AIMULL,
7191		reg: regInfo{
7192			inputs: []inputInfo{
7193				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7194				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7195			},
7196			outputs: []outputInfo{
7197				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7198			},
7199		},
7200	},
7201	{
7202		name:         "MULQconst",
7203		auxType:      auxInt32,
7204		argLen:       1,
7205		clobberFlags: true,
7206		asm:          x86.AIMUL3Q,
7207		reg: regInfo{
7208			inputs: []inputInfo{
7209				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7210			},
7211			outputs: []outputInfo{
7212				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7213			},
7214		},
7215	},
7216	{
7217		name:         "MULLconst",
7218		auxType:      auxInt32,
7219		argLen:       1,
7220		clobberFlags: true,
7221		asm:          x86.AIMUL3L,
7222		reg: regInfo{
7223			inputs: []inputInfo{
7224				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7225			},
7226			outputs: []outputInfo{
7227				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7228			},
7229		},
7230	},
7231	{
7232		name:         "MULLU",
7233		argLen:       2,
7234		commutative:  true,
7235		clobberFlags: true,
7236		asm:          x86.AMULL,
7237		reg: regInfo{
7238			inputs: []inputInfo{
7239				{0, 1},     // AX
7240				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7241			},
7242			clobbers: 4, // DX
7243			outputs: []outputInfo{
7244				{1, 0},
7245				{0, 1}, // AX
7246			},
7247		},
7248	},
7249	{
7250		name:         "MULQU",
7251		argLen:       2,
7252		commutative:  true,
7253		clobberFlags: true,
7254		asm:          x86.AMULQ,
7255		reg: regInfo{
7256			inputs: []inputInfo{
7257				{0, 1},     // AX
7258				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7259			},
7260			clobbers: 4, // DX
7261			outputs: []outputInfo{
7262				{1, 0},
7263				{0, 1}, // AX
7264			},
7265		},
7266	},
7267	{
7268		name:         "HMULQ",
7269		argLen:       2,
7270		clobberFlags: true,
7271		asm:          x86.AIMULQ,
7272		reg: regInfo{
7273			inputs: []inputInfo{
7274				{0, 1},     // AX
7275				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7276			},
7277			clobbers: 1, // AX
7278			outputs: []outputInfo{
7279				{0, 4}, // DX
7280			},
7281		},
7282	},
7283	{
7284		name:         "HMULL",
7285		argLen:       2,
7286		clobberFlags: true,
7287		asm:          x86.AIMULL,
7288		reg: regInfo{
7289			inputs: []inputInfo{
7290				{0, 1},     // AX
7291				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7292			},
7293			clobbers: 1, // AX
7294			outputs: []outputInfo{
7295				{0, 4}, // DX
7296			},
7297		},
7298	},
7299	{
7300		name:         "HMULQU",
7301		argLen:       2,
7302		clobberFlags: true,
7303		asm:          x86.AMULQ,
7304		reg: regInfo{
7305			inputs: []inputInfo{
7306				{0, 1},     // AX
7307				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7308			},
7309			clobbers: 1, // AX
7310			outputs: []outputInfo{
7311				{0, 4}, // DX
7312			},
7313		},
7314	},
7315	{
7316		name:         "HMULLU",
7317		argLen:       2,
7318		clobberFlags: true,
7319		asm:          x86.AMULL,
7320		reg: regInfo{
7321			inputs: []inputInfo{
7322				{0, 1},     // AX
7323				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7324			},
7325			clobbers: 1, // AX
7326			outputs: []outputInfo{
7327				{0, 4}, // DX
7328			},
7329		},
7330	},
7331	{
7332		name:         "AVGQU",
7333		argLen:       2,
7334		commutative:  true,
7335		resultInArg0: true,
7336		clobberFlags: true,
7337		reg: regInfo{
7338			inputs: []inputInfo{
7339				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7340				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7341			},
7342			outputs: []outputInfo{
7343				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7344			},
7345		},
7346	},
7347	{
7348		name:         "DIVQ",
7349		auxType:      auxBool,
7350		argLen:       2,
7351		clobberFlags: true,
7352		asm:          x86.AIDIVQ,
7353		reg: regInfo{
7354			inputs: []inputInfo{
7355				{0, 1},     // AX
7356				{1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7357			},
7358			outputs: []outputInfo{
7359				{0, 1}, // AX
7360				{1, 4}, // DX
7361			},
7362		},
7363	},
7364	{
7365		name:         "DIVL",
7366		auxType:      auxBool,
7367		argLen:       2,
7368		clobberFlags: true,
7369		asm:          x86.AIDIVL,
7370		reg: regInfo{
7371			inputs: []inputInfo{
7372				{0, 1},     // AX
7373				{1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7374			},
7375			outputs: []outputInfo{
7376				{0, 1}, // AX
7377				{1, 4}, // DX
7378			},
7379		},
7380	},
7381	{
7382		name:         "DIVW",
7383		auxType:      auxBool,
7384		argLen:       2,
7385		clobberFlags: true,
7386		asm:          x86.AIDIVW,
7387		reg: regInfo{
7388			inputs: []inputInfo{
7389				{0, 1},     // AX
7390				{1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7391			},
7392			outputs: []outputInfo{
7393				{0, 1}, // AX
7394				{1, 4}, // DX
7395			},
7396		},
7397	},
7398	{
7399		name:         "DIVQU",
7400		argLen:       2,
7401		clobberFlags: true,
7402		asm:          x86.ADIVQ,
7403		reg: regInfo{
7404			inputs: []inputInfo{
7405				{0, 1},     // AX
7406				{1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7407			},
7408			outputs: []outputInfo{
7409				{0, 1}, // AX
7410				{1, 4}, // DX
7411			},
7412		},
7413	},
7414	{
7415		name:         "DIVLU",
7416		argLen:       2,
7417		clobberFlags: true,
7418		asm:          x86.ADIVL,
7419		reg: regInfo{
7420			inputs: []inputInfo{
7421				{0, 1},     // AX
7422				{1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7423			},
7424			outputs: []outputInfo{
7425				{0, 1}, // AX
7426				{1, 4}, // DX
7427			},
7428		},
7429	},
7430	{
7431		name:         "DIVWU",
7432		argLen:       2,
7433		clobberFlags: true,
7434		asm:          x86.ADIVW,
7435		reg: regInfo{
7436			inputs: []inputInfo{
7437				{0, 1},     // AX
7438				{1, 49147}, // AX CX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7439			},
7440			outputs: []outputInfo{
7441				{0, 1}, // AX
7442				{1, 4}, // DX
7443			},
7444		},
7445	},
7446	{
7447		name:         "NEGLflags",
7448		argLen:       1,
7449		resultInArg0: true,
7450		asm:          x86.ANEGL,
7451		reg: regInfo{
7452			inputs: []inputInfo{
7453				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7454			},
7455			outputs: []outputInfo{
7456				{1, 0},
7457				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7458			},
7459		},
7460	},
7461	{
7462		name:         "ADDQcarry",
7463		argLen:       2,
7464		commutative:  true,
7465		resultInArg0: true,
7466		asm:          x86.AADDQ,
7467		reg: regInfo{
7468			inputs: []inputInfo{
7469				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7470				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7471			},
7472			outputs: []outputInfo{
7473				{1, 0},
7474				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7475			},
7476		},
7477	},
7478	{
7479		name:         "ADCQ",
7480		argLen:       3,
7481		commutative:  true,
7482		resultInArg0: true,
7483		asm:          x86.AADCQ,
7484		reg: regInfo{
7485			inputs: []inputInfo{
7486				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7487				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7488			},
7489			outputs: []outputInfo{
7490				{1, 0},
7491				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7492			},
7493		},
7494	},
7495	{
7496		name:         "ADDQconstcarry",
7497		auxType:      auxInt32,
7498		argLen:       1,
7499		resultInArg0: true,
7500		asm:          x86.AADDQ,
7501		reg: regInfo{
7502			inputs: []inputInfo{
7503				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7504			},
7505			outputs: []outputInfo{
7506				{1, 0},
7507				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7508			},
7509		},
7510	},
7511	{
7512		name:         "ADCQconst",
7513		auxType:      auxInt32,
7514		argLen:       2,
7515		resultInArg0: true,
7516		asm:          x86.AADCQ,
7517		reg: regInfo{
7518			inputs: []inputInfo{
7519				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7520			},
7521			outputs: []outputInfo{
7522				{1, 0},
7523				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7524			},
7525		},
7526	},
7527	{
7528		name:         "SUBQborrow",
7529		argLen:       2,
7530		resultInArg0: true,
7531		asm:          x86.ASUBQ,
7532		reg: regInfo{
7533			inputs: []inputInfo{
7534				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7535				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7536			},
7537			outputs: []outputInfo{
7538				{1, 0},
7539				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7540			},
7541		},
7542	},
7543	{
7544		name:         "SBBQ",
7545		argLen:       3,
7546		resultInArg0: true,
7547		asm:          x86.ASBBQ,
7548		reg: regInfo{
7549			inputs: []inputInfo{
7550				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7551				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7552			},
7553			outputs: []outputInfo{
7554				{1, 0},
7555				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7556			},
7557		},
7558	},
7559	{
7560		name:         "SUBQconstborrow",
7561		auxType:      auxInt32,
7562		argLen:       1,
7563		resultInArg0: true,
7564		asm:          x86.ASUBQ,
7565		reg: regInfo{
7566			inputs: []inputInfo{
7567				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7568			},
7569			outputs: []outputInfo{
7570				{1, 0},
7571				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7572			},
7573		},
7574	},
7575	{
7576		name:         "SBBQconst",
7577		auxType:      auxInt32,
7578		argLen:       2,
7579		resultInArg0: true,
7580		asm:          x86.ASBBQ,
7581		reg: regInfo{
7582			inputs: []inputInfo{
7583				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7584			},
7585			outputs: []outputInfo{
7586				{1, 0},
7587				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7588			},
7589		},
7590	},
7591	{
7592		name:         "MULQU2",
7593		argLen:       2,
7594		commutative:  true,
7595		clobberFlags: true,
7596		asm:          x86.AMULQ,
7597		reg: regInfo{
7598			inputs: []inputInfo{
7599				{0, 1},     // AX
7600				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7601			},
7602			outputs: []outputInfo{
7603				{0, 4}, // DX
7604				{1, 1}, // AX
7605			},
7606		},
7607	},
7608	{
7609		name:         "DIVQU2",
7610		argLen:       3,
7611		clobberFlags: true,
7612		asm:          x86.ADIVQ,
7613		reg: regInfo{
7614			inputs: []inputInfo{
7615				{0, 4},     // DX
7616				{1, 1},     // AX
7617				{2, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7618			},
7619			outputs: []outputInfo{
7620				{0, 1}, // AX
7621				{1, 4}, // DX
7622			},
7623		},
7624	},
7625	{
7626		name:         "ANDQ",
7627		argLen:       2,
7628		commutative:  true,
7629		resultInArg0: true,
7630		clobberFlags: true,
7631		asm:          x86.AANDQ,
7632		reg: regInfo{
7633			inputs: []inputInfo{
7634				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7635				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7636			},
7637			outputs: []outputInfo{
7638				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7639			},
7640		},
7641	},
7642	{
7643		name:         "ANDL",
7644		argLen:       2,
7645		commutative:  true,
7646		resultInArg0: true,
7647		clobberFlags: true,
7648		asm:          x86.AANDL,
7649		reg: regInfo{
7650			inputs: []inputInfo{
7651				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7652				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7653			},
7654			outputs: []outputInfo{
7655				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7656			},
7657		},
7658	},
7659	{
7660		name:         "ANDQconst",
7661		auxType:      auxInt32,
7662		argLen:       1,
7663		resultInArg0: true,
7664		clobberFlags: true,
7665		asm:          x86.AANDQ,
7666		reg: regInfo{
7667			inputs: []inputInfo{
7668				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7669			},
7670			outputs: []outputInfo{
7671				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7672			},
7673		},
7674	},
7675	{
7676		name:         "ANDLconst",
7677		auxType:      auxInt32,
7678		argLen:       1,
7679		resultInArg0: true,
7680		clobberFlags: true,
7681		asm:          x86.AANDL,
7682		reg: regInfo{
7683			inputs: []inputInfo{
7684				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7685			},
7686			outputs: []outputInfo{
7687				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7688			},
7689		},
7690	},
7691	{
7692		name:           "ANDQconstmodify",
7693		auxType:        auxSymValAndOff,
7694		argLen:         2,
7695		clobberFlags:   true,
7696		faultOnNilArg0: true,
7697		symEffect:      SymRead | SymWrite,
7698		asm:            x86.AANDQ,
7699		reg: regInfo{
7700			inputs: []inputInfo{
7701				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7702			},
7703		},
7704	},
7705	{
7706		name:           "ANDLconstmodify",
7707		auxType:        auxSymValAndOff,
7708		argLen:         2,
7709		clobberFlags:   true,
7710		faultOnNilArg0: true,
7711		symEffect:      SymRead | SymWrite,
7712		asm:            x86.AANDL,
7713		reg: regInfo{
7714			inputs: []inputInfo{
7715				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7716			},
7717		},
7718	},
7719	{
7720		name:         "ORQ",
7721		argLen:       2,
7722		commutative:  true,
7723		resultInArg0: true,
7724		clobberFlags: true,
7725		asm:          x86.AORQ,
7726		reg: regInfo{
7727			inputs: []inputInfo{
7728				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7729				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7730			},
7731			outputs: []outputInfo{
7732				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7733			},
7734		},
7735	},
7736	{
7737		name:         "ORL",
7738		argLen:       2,
7739		commutative:  true,
7740		resultInArg0: true,
7741		clobberFlags: true,
7742		asm:          x86.AORL,
7743		reg: regInfo{
7744			inputs: []inputInfo{
7745				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7746				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7747			},
7748			outputs: []outputInfo{
7749				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7750			},
7751		},
7752	},
7753	{
7754		name:         "ORQconst",
7755		auxType:      auxInt32,
7756		argLen:       1,
7757		resultInArg0: true,
7758		clobberFlags: true,
7759		asm:          x86.AORQ,
7760		reg: regInfo{
7761			inputs: []inputInfo{
7762				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7763			},
7764			outputs: []outputInfo{
7765				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7766			},
7767		},
7768	},
7769	{
7770		name:         "ORLconst",
7771		auxType:      auxInt32,
7772		argLen:       1,
7773		resultInArg0: true,
7774		clobberFlags: true,
7775		asm:          x86.AORL,
7776		reg: regInfo{
7777			inputs: []inputInfo{
7778				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7779			},
7780			outputs: []outputInfo{
7781				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7782			},
7783		},
7784	},
7785	{
7786		name:           "ORQconstmodify",
7787		auxType:        auxSymValAndOff,
7788		argLen:         2,
7789		clobberFlags:   true,
7790		faultOnNilArg0: true,
7791		symEffect:      SymRead | SymWrite,
7792		asm:            x86.AORQ,
7793		reg: regInfo{
7794			inputs: []inputInfo{
7795				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7796			},
7797		},
7798	},
7799	{
7800		name:           "ORLconstmodify",
7801		auxType:        auxSymValAndOff,
7802		argLen:         2,
7803		clobberFlags:   true,
7804		faultOnNilArg0: true,
7805		symEffect:      SymRead | SymWrite,
7806		asm:            x86.AORL,
7807		reg: regInfo{
7808			inputs: []inputInfo{
7809				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7810			},
7811		},
7812	},
7813	{
7814		name:         "XORQ",
7815		argLen:       2,
7816		commutative:  true,
7817		resultInArg0: true,
7818		clobberFlags: true,
7819		asm:          x86.AXORQ,
7820		reg: regInfo{
7821			inputs: []inputInfo{
7822				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7823				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7824			},
7825			outputs: []outputInfo{
7826				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7827			},
7828		},
7829	},
7830	{
7831		name:         "XORL",
7832		argLen:       2,
7833		commutative:  true,
7834		resultInArg0: true,
7835		clobberFlags: true,
7836		asm:          x86.AXORL,
7837		reg: regInfo{
7838			inputs: []inputInfo{
7839				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7840				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7841			},
7842			outputs: []outputInfo{
7843				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7844			},
7845		},
7846	},
7847	{
7848		name:         "XORQconst",
7849		auxType:      auxInt32,
7850		argLen:       1,
7851		resultInArg0: true,
7852		clobberFlags: true,
7853		asm:          x86.AXORQ,
7854		reg: regInfo{
7855			inputs: []inputInfo{
7856				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7857			},
7858			outputs: []outputInfo{
7859				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7860			},
7861		},
7862	},
7863	{
7864		name:         "XORLconst",
7865		auxType:      auxInt32,
7866		argLen:       1,
7867		resultInArg0: true,
7868		clobberFlags: true,
7869		asm:          x86.AXORL,
7870		reg: regInfo{
7871			inputs: []inputInfo{
7872				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7873			},
7874			outputs: []outputInfo{
7875				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
7876			},
7877		},
7878	},
7879	{
7880		name:           "XORQconstmodify",
7881		auxType:        auxSymValAndOff,
7882		argLen:         2,
7883		clobberFlags:   true,
7884		faultOnNilArg0: true,
7885		symEffect:      SymRead | SymWrite,
7886		asm:            x86.AXORQ,
7887		reg: regInfo{
7888			inputs: []inputInfo{
7889				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7890			},
7891		},
7892	},
7893	{
7894		name:           "XORLconstmodify",
7895		auxType:        auxSymValAndOff,
7896		argLen:         2,
7897		clobberFlags:   true,
7898		faultOnNilArg0: true,
7899		symEffect:      SymRead | SymWrite,
7900		asm:            x86.AXORL,
7901		reg: regInfo{
7902			inputs: []inputInfo{
7903				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
7904			},
7905		},
7906	},
7907	{
7908		name:   "CMPQ",
7909		argLen: 2,
7910		asm:    x86.ACMPQ,
7911		reg: regInfo{
7912			inputs: []inputInfo{
7913				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7914				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7915			},
7916		},
7917	},
7918	{
7919		name:   "CMPL",
7920		argLen: 2,
7921		asm:    x86.ACMPL,
7922		reg: regInfo{
7923			inputs: []inputInfo{
7924				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7925				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7926			},
7927		},
7928	},
7929	{
7930		name:   "CMPW",
7931		argLen: 2,
7932		asm:    x86.ACMPW,
7933		reg: regInfo{
7934			inputs: []inputInfo{
7935				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7936				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7937			},
7938		},
7939	},
7940	{
7941		name:   "CMPB",
7942		argLen: 2,
7943		asm:    x86.ACMPB,
7944		reg: regInfo{
7945			inputs: []inputInfo{
7946				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7947				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7948			},
7949		},
7950	},
7951	{
7952		name:    "CMPQconst",
7953		auxType: auxInt32,
7954		argLen:  1,
7955		asm:     x86.ACMPQ,
7956		reg: regInfo{
7957			inputs: []inputInfo{
7958				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7959			},
7960		},
7961	},
7962	{
7963		name:    "CMPLconst",
7964		auxType: auxInt32,
7965		argLen:  1,
7966		asm:     x86.ACMPL,
7967		reg: regInfo{
7968			inputs: []inputInfo{
7969				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7970			},
7971		},
7972	},
7973	{
7974		name:    "CMPWconst",
7975		auxType: auxInt16,
7976		argLen:  1,
7977		asm:     x86.ACMPW,
7978		reg: regInfo{
7979			inputs: []inputInfo{
7980				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7981			},
7982		},
7983	},
7984	{
7985		name:    "CMPBconst",
7986		auxType: auxInt8,
7987		argLen:  1,
7988		asm:     x86.ACMPB,
7989		reg: regInfo{
7990			inputs: []inputInfo{
7991				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
7992			},
7993		},
7994	},
7995	{
7996		name:           "CMPQload",
7997		auxType:        auxSymOff,
7998		argLen:         3,
7999		faultOnNilArg0: true,
8000		symEffect:      SymRead,
8001		asm:            x86.ACMPQ,
8002		reg: regInfo{
8003			inputs: []inputInfo{
8004				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8005				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8006			},
8007		},
8008	},
8009	{
8010		name:           "CMPLload",
8011		auxType:        auxSymOff,
8012		argLen:         3,
8013		faultOnNilArg0: true,
8014		symEffect:      SymRead,
8015		asm:            x86.ACMPL,
8016		reg: regInfo{
8017			inputs: []inputInfo{
8018				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8019				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8020			},
8021		},
8022	},
8023	{
8024		name:           "CMPWload",
8025		auxType:        auxSymOff,
8026		argLen:         3,
8027		faultOnNilArg0: true,
8028		symEffect:      SymRead,
8029		asm:            x86.ACMPW,
8030		reg: regInfo{
8031			inputs: []inputInfo{
8032				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8033				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8034			},
8035		},
8036	},
8037	{
8038		name:           "CMPBload",
8039		auxType:        auxSymOff,
8040		argLen:         3,
8041		faultOnNilArg0: true,
8042		symEffect:      SymRead,
8043		asm:            x86.ACMPB,
8044		reg: regInfo{
8045			inputs: []inputInfo{
8046				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8047				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8048			},
8049		},
8050	},
8051	{
8052		name:           "CMPQconstload",
8053		auxType:        auxSymValAndOff,
8054		argLen:         2,
8055		faultOnNilArg0: true,
8056		symEffect:      SymRead,
8057		asm:            x86.ACMPQ,
8058		reg: regInfo{
8059			inputs: []inputInfo{
8060				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8061			},
8062		},
8063	},
8064	{
8065		name:           "CMPLconstload",
8066		auxType:        auxSymValAndOff,
8067		argLen:         2,
8068		faultOnNilArg0: true,
8069		symEffect:      SymRead,
8070		asm:            x86.ACMPL,
8071		reg: regInfo{
8072			inputs: []inputInfo{
8073				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8074			},
8075		},
8076	},
8077	{
8078		name:           "CMPWconstload",
8079		auxType:        auxSymValAndOff,
8080		argLen:         2,
8081		faultOnNilArg0: true,
8082		symEffect:      SymRead,
8083		asm:            x86.ACMPW,
8084		reg: regInfo{
8085			inputs: []inputInfo{
8086				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8087			},
8088		},
8089	},
8090	{
8091		name:           "CMPBconstload",
8092		auxType:        auxSymValAndOff,
8093		argLen:         2,
8094		faultOnNilArg0: true,
8095		symEffect:      SymRead,
8096		asm:            x86.ACMPB,
8097		reg: regInfo{
8098			inputs: []inputInfo{
8099				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8100			},
8101		},
8102	},
8103	{
8104		name:      "CMPQloadidx8",
8105		auxType:   auxSymOff,
8106		argLen:    4,
8107		symEffect: SymRead,
8108		asm:       x86.ACMPQ,
8109		scale:     8,
8110		reg: regInfo{
8111			inputs: []inputInfo{
8112				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8113				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8114				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8115			},
8116		},
8117	},
8118	{
8119		name:        "CMPQloadidx1",
8120		auxType:     auxSymOff,
8121		argLen:      4,
8122		commutative: true,
8123		symEffect:   SymRead,
8124		asm:         x86.ACMPQ,
8125		scale:       1,
8126		reg: regInfo{
8127			inputs: []inputInfo{
8128				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8129				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8130				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8131			},
8132		},
8133	},
8134	{
8135		name:      "CMPLloadidx4",
8136		auxType:   auxSymOff,
8137		argLen:    4,
8138		symEffect: SymRead,
8139		asm:       x86.ACMPL,
8140		scale:     4,
8141		reg: regInfo{
8142			inputs: []inputInfo{
8143				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8144				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8145				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8146			},
8147		},
8148	},
8149	{
8150		name:        "CMPLloadidx1",
8151		auxType:     auxSymOff,
8152		argLen:      4,
8153		commutative: true,
8154		symEffect:   SymRead,
8155		asm:         x86.ACMPL,
8156		scale:       1,
8157		reg: regInfo{
8158			inputs: []inputInfo{
8159				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8160				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8161				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8162			},
8163		},
8164	},
8165	{
8166		name:      "CMPWloadidx2",
8167		auxType:   auxSymOff,
8168		argLen:    4,
8169		symEffect: SymRead,
8170		asm:       x86.ACMPW,
8171		scale:     2,
8172		reg: regInfo{
8173			inputs: []inputInfo{
8174				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8175				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8176				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8177			},
8178		},
8179	},
8180	{
8181		name:        "CMPWloadidx1",
8182		auxType:     auxSymOff,
8183		argLen:      4,
8184		commutative: true,
8185		symEffect:   SymRead,
8186		asm:         x86.ACMPW,
8187		scale:       1,
8188		reg: regInfo{
8189			inputs: []inputInfo{
8190				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8191				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8192				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8193			},
8194		},
8195	},
8196	{
8197		name:        "CMPBloadidx1",
8198		auxType:     auxSymOff,
8199		argLen:      4,
8200		commutative: true,
8201		symEffect:   SymRead,
8202		asm:         x86.ACMPB,
8203		scale:       1,
8204		reg: regInfo{
8205			inputs: []inputInfo{
8206				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8207				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8208				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8209			},
8210		},
8211	},
8212	{
8213		name:      "CMPQconstloadidx8",
8214		auxType:   auxSymValAndOff,
8215		argLen:    3,
8216		symEffect: SymRead,
8217		asm:       x86.ACMPQ,
8218		scale:     8,
8219		reg: regInfo{
8220			inputs: []inputInfo{
8221				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8222				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8223			},
8224		},
8225	},
8226	{
8227		name:        "CMPQconstloadidx1",
8228		auxType:     auxSymValAndOff,
8229		argLen:      3,
8230		commutative: true,
8231		symEffect:   SymRead,
8232		asm:         x86.ACMPQ,
8233		scale:       1,
8234		reg: regInfo{
8235			inputs: []inputInfo{
8236				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8237				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8238			},
8239		},
8240	},
8241	{
8242		name:      "CMPLconstloadidx4",
8243		auxType:   auxSymValAndOff,
8244		argLen:    3,
8245		symEffect: SymRead,
8246		asm:       x86.ACMPL,
8247		scale:     4,
8248		reg: regInfo{
8249			inputs: []inputInfo{
8250				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8251				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8252			},
8253		},
8254	},
8255	{
8256		name:        "CMPLconstloadidx1",
8257		auxType:     auxSymValAndOff,
8258		argLen:      3,
8259		commutative: true,
8260		symEffect:   SymRead,
8261		asm:         x86.ACMPL,
8262		scale:       1,
8263		reg: regInfo{
8264			inputs: []inputInfo{
8265				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8266				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8267			},
8268		},
8269	},
8270	{
8271		name:      "CMPWconstloadidx2",
8272		auxType:   auxSymValAndOff,
8273		argLen:    3,
8274		symEffect: SymRead,
8275		asm:       x86.ACMPW,
8276		scale:     2,
8277		reg: regInfo{
8278			inputs: []inputInfo{
8279				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8280				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8281			},
8282		},
8283	},
8284	{
8285		name:        "CMPWconstloadidx1",
8286		auxType:     auxSymValAndOff,
8287		argLen:      3,
8288		commutative: true,
8289		symEffect:   SymRead,
8290		asm:         x86.ACMPW,
8291		scale:       1,
8292		reg: regInfo{
8293			inputs: []inputInfo{
8294				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8295				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8296			},
8297		},
8298	},
8299	{
8300		name:        "CMPBconstloadidx1",
8301		auxType:     auxSymValAndOff,
8302		argLen:      3,
8303		commutative: true,
8304		symEffect:   SymRead,
8305		asm:         x86.ACMPB,
8306		scale:       1,
8307		reg: regInfo{
8308			inputs: []inputInfo{
8309				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8310				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
8311			},
8312		},
8313	},
8314	{
8315		name:   "UCOMISS",
8316		argLen: 2,
8317		asm:    x86.AUCOMISS,
8318		reg: regInfo{
8319			inputs: []inputInfo{
8320				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8321				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8322			},
8323		},
8324	},
8325	{
8326		name:   "UCOMISD",
8327		argLen: 2,
8328		asm:    x86.AUCOMISD,
8329		reg: regInfo{
8330			inputs: []inputInfo{
8331				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8332				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
8333			},
8334		},
8335	},
8336	{
8337		name:   "BTL",
8338		argLen: 2,
8339		asm:    x86.ABTL,
8340		reg: regInfo{
8341			inputs: []inputInfo{
8342				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8343				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8344			},
8345		},
8346	},
8347	{
8348		name:   "BTQ",
8349		argLen: 2,
8350		asm:    x86.ABTQ,
8351		reg: regInfo{
8352			inputs: []inputInfo{
8353				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8354				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8355			},
8356		},
8357	},
8358	{
8359		name:         "BTCL",
8360		argLen:       2,
8361		resultInArg0: true,
8362		clobberFlags: true,
8363		asm:          x86.ABTCL,
8364		reg: regInfo{
8365			inputs: []inputInfo{
8366				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8367				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8368			},
8369			outputs: []outputInfo{
8370				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8371			},
8372		},
8373	},
8374	{
8375		name:         "BTCQ",
8376		argLen:       2,
8377		resultInArg0: true,
8378		clobberFlags: true,
8379		asm:          x86.ABTCQ,
8380		reg: regInfo{
8381			inputs: []inputInfo{
8382				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8383				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8384			},
8385			outputs: []outputInfo{
8386				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8387			},
8388		},
8389	},
8390	{
8391		name:         "BTRL",
8392		argLen:       2,
8393		resultInArg0: true,
8394		clobberFlags: true,
8395		asm:          x86.ABTRL,
8396		reg: regInfo{
8397			inputs: []inputInfo{
8398				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8399				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8400			},
8401			outputs: []outputInfo{
8402				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8403			},
8404		},
8405	},
8406	{
8407		name:         "BTRQ",
8408		argLen:       2,
8409		resultInArg0: true,
8410		clobberFlags: true,
8411		asm:          x86.ABTRQ,
8412		reg: regInfo{
8413			inputs: []inputInfo{
8414				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8415				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8416			},
8417			outputs: []outputInfo{
8418				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8419			},
8420		},
8421	},
8422	{
8423		name:         "BTSL",
8424		argLen:       2,
8425		resultInArg0: true,
8426		clobberFlags: true,
8427		asm:          x86.ABTSL,
8428		reg: regInfo{
8429			inputs: []inputInfo{
8430				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8431				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8432			},
8433			outputs: []outputInfo{
8434				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8435			},
8436		},
8437	},
8438	{
8439		name:         "BTSQ",
8440		argLen:       2,
8441		resultInArg0: true,
8442		clobberFlags: true,
8443		asm:          x86.ABTSQ,
8444		reg: regInfo{
8445			inputs: []inputInfo{
8446				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8447				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8448			},
8449			outputs: []outputInfo{
8450				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8451			},
8452		},
8453	},
8454	{
8455		name:    "BTLconst",
8456		auxType: auxInt8,
8457		argLen:  1,
8458		asm:     x86.ABTL,
8459		reg: regInfo{
8460			inputs: []inputInfo{
8461				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8462			},
8463		},
8464	},
8465	{
8466		name:    "BTQconst",
8467		auxType: auxInt8,
8468		argLen:  1,
8469		asm:     x86.ABTQ,
8470		reg: regInfo{
8471			inputs: []inputInfo{
8472				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8473			},
8474		},
8475	},
8476	{
8477		name:         "BTCLconst",
8478		auxType:      auxInt8,
8479		argLen:       1,
8480		resultInArg0: true,
8481		clobberFlags: true,
8482		asm:          x86.ABTCL,
8483		reg: regInfo{
8484			inputs: []inputInfo{
8485				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8486			},
8487			outputs: []outputInfo{
8488				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8489			},
8490		},
8491	},
8492	{
8493		name:         "BTCQconst",
8494		auxType:      auxInt8,
8495		argLen:       1,
8496		resultInArg0: true,
8497		clobberFlags: true,
8498		asm:          x86.ABTCQ,
8499		reg: regInfo{
8500			inputs: []inputInfo{
8501				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8502			},
8503			outputs: []outputInfo{
8504				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8505			},
8506		},
8507	},
8508	{
8509		name:         "BTRLconst",
8510		auxType:      auxInt8,
8511		argLen:       1,
8512		resultInArg0: true,
8513		clobberFlags: true,
8514		asm:          x86.ABTRL,
8515		reg: regInfo{
8516			inputs: []inputInfo{
8517				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8518			},
8519			outputs: []outputInfo{
8520				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8521			},
8522		},
8523	},
8524	{
8525		name:         "BTRQconst",
8526		auxType:      auxInt8,
8527		argLen:       1,
8528		resultInArg0: true,
8529		clobberFlags: true,
8530		asm:          x86.ABTRQ,
8531		reg: regInfo{
8532			inputs: []inputInfo{
8533				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8534			},
8535			outputs: []outputInfo{
8536				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8537			},
8538		},
8539	},
8540	{
8541		name:         "BTSLconst",
8542		auxType:      auxInt8,
8543		argLen:       1,
8544		resultInArg0: true,
8545		clobberFlags: true,
8546		asm:          x86.ABTSL,
8547		reg: regInfo{
8548			inputs: []inputInfo{
8549				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8550			},
8551			outputs: []outputInfo{
8552				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8553			},
8554		},
8555	},
8556	{
8557		name:         "BTSQconst",
8558		auxType:      auxInt8,
8559		argLen:       1,
8560		resultInArg0: true,
8561		clobberFlags: true,
8562		asm:          x86.ABTSQ,
8563		reg: regInfo{
8564			inputs: []inputInfo{
8565				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8566			},
8567			outputs: []outputInfo{
8568				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8569			},
8570		},
8571	},
8572	{
8573		name:        "TESTQ",
8574		argLen:      2,
8575		commutative: true,
8576		asm:         x86.ATESTQ,
8577		reg: regInfo{
8578			inputs: []inputInfo{
8579				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8580				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8581			},
8582		},
8583	},
8584	{
8585		name:        "TESTL",
8586		argLen:      2,
8587		commutative: true,
8588		asm:         x86.ATESTL,
8589		reg: regInfo{
8590			inputs: []inputInfo{
8591				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8592				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8593			},
8594		},
8595	},
8596	{
8597		name:        "TESTW",
8598		argLen:      2,
8599		commutative: true,
8600		asm:         x86.ATESTW,
8601		reg: regInfo{
8602			inputs: []inputInfo{
8603				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8604				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8605			},
8606		},
8607	},
8608	{
8609		name:        "TESTB",
8610		argLen:      2,
8611		commutative: true,
8612		asm:         x86.ATESTB,
8613		reg: regInfo{
8614			inputs: []inputInfo{
8615				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8616				{1, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8617			},
8618		},
8619	},
8620	{
8621		name:    "TESTQconst",
8622		auxType: auxInt32,
8623		argLen:  1,
8624		asm:     x86.ATESTQ,
8625		reg: regInfo{
8626			inputs: []inputInfo{
8627				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8628			},
8629		},
8630	},
8631	{
8632		name:    "TESTLconst",
8633		auxType: auxInt32,
8634		argLen:  1,
8635		asm:     x86.ATESTL,
8636		reg: regInfo{
8637			inputs: []inputInfo{
8638				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8639			},
8640		},
8641	},
8642	{
8643		name:    "TESTWconst",
8644		auxType: auxInt16,
8645		argLen:  1,
8646		asm:     x86.ATESTW,
8647		reg: regInfo{
8648			inputs: []inputInfo{
8649				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8650			},
8651		},
8652	},
8653	{
8654		name:    "TESTBconst",
8655		auxType: auxInt8,
8656		argLen:  1,
8657		asm:     x86.ATESTB,
8658		reg: regInfo{
8659			inputs: []inputInfo{
8660				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
8661			},
8662		},
8663	},
8664	{
8665		name:         "SHLQ",
8666		argLen:       2,
8667		resultInArg0: true,
8668		clobberFlags: true,
8669		asm:          x86.ASHLQ,
8670		reg: regInfo{
8671			inputs: []inputInfo{
8672				{1, 2},     // CX
8673				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8674			},
8675			outputs: []outputInfo{
8676				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8677			},
8678		},
8679	},
8680	{
8681		name:         "SHLL",
8682		argLen:       2,
8683		resultInArg0: true,
8684		clobberFlags: true,
8685		asm:          x86.ASHLL,
8686		reg: regInfo{
8687			inputs: []inputInfo{
8688				{1, 2},     // CX
8689				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8690			},
8691			outputs: []outputInfo{
8692				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8693			},
8694		},
8695	},
8696	{
8697		name:         "SHLQconst",
8698		auxType:      auxInt8,
8699		argLen:       1,
8700		resultInArg0: true,
8701		clobberFlags: true,
8702		asm:          x86.ASHLQ,
8703		reg: regInfo{
8704			inputs: []inputInfo{
8705				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8706			},
8707			outputs: []outputInfo{
8708				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8709			},
8710		},
8711	},
8712	{
8713		name:         "SHLLconst",
8714		auxType:      auxInt8,
8715		argLen:       1,
8716		resultInArg0: true,
8717		clobberFlags: true,
8718		asm:          x86.ASHLL,
8719		reg: regInfo{
8720			inputs: []inputInfo{
8721				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8722			},
8723			outputs: []outputInfo{
8724				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8725			},
8726		},
8727	},
8728	{
8729		name:         "SHRQ",
8730		argLen:       2,
8731		resultInArg0: true,
8732		clobberFlags: true,
8733		asm:          x86.ASHRQ,
8734		reg: regInfo{
8735			inputs: []inputInfo{
8736				{1, 2},     // CX
8737				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8738			},
8739			outputs: []outputInfo{
8740				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8741			},
8742		},
8743	},
8744	{
8745		name:         "SHRL",
8746		argLen:       2,
8747		resultInArg0: true,
8748		clobberFlags: true,
8749		asm:          x86.ASHRL,
8750		reg: regInfo{
8751			inputs: []inputInfo{
8752				{1, 2},     // CX
8753				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8754			},
8755			outputs: []outputInfo{
8756				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8757			},
8758		},
8759	},
8760	{
8761		name:         "SHRW",
8762		argLen:       2,
8763		resultInArg0: true,
8764		clobberFlags: true,
8765		asm:          x86.ASHRW,
8766		reg: regInfo{
8767			inputs: []inputInfo{
8768				{1, 2},     // CX
8769				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8770			},
8771			outputs: []outputInfo{
8772				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8773			},
8774		},
8775	},
8776	{
8777		name:         "SHRB",
8778		argLen:       2,
8779		resultInArg0: true,
8780		clobberFlags: true,
8781		asm:          x86.ASHRB,
8782		reg: regInfo{
8783			inputs: []inputInfo{
8784				{1, 2},     // CX
8785				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8786			},
8787			outputs: []outputInfo{
8788				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8789			},
8790		},
8791	},
8792	{
8793		name:         "SHRQconst",
8794		auxType:      auxInt8,
8795		argLen:       1,
8796		resultInArg0: true,
8797		clobberFlags: true,
8798		asm:          x86.ASHRQ,
8799		reg: regInfo{
8800			inputs: []inputInfo{
8801				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8802			},
8803			outputs: []outputInfo{
8804				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8805			},
8806		},
8807	},
8808	{
8809		name:         "SHRLconst",
8810		auxType:      auxInt8,
8811		argLen:       1,
8812		resultInArg0: true,
8813		clobberFlags: true,
8814		asm:          x86.ASHRL,
8815		reg: regInfo{
8816			inputs: []inputInfo{
8817				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8818			},
8819			outputs: []outputInfo{
8820				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8821			},
8822		},
8823	},
8824	{
8825		name:         "SHRWconst",
8826		auxType:      auxInt8,
8827		argLen:       1,
8828		resultInArg0: true,
8829		clobberFlags: true,
8830		asm:          x86.ASHRW,
8831		reg: regInfo{
8832			inputs: []inputInfo{
8833				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8834			},
8835			outputs: []outputInfo{
8836				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8837			},
8838		},
8839	},
8840	{
8841		name:         "SHRBconst",
8842		auxType:      auxInt8,
8843		argLen:       1,
8844		resultInArg0: true,
8845		clobberFlags: true,
8846		asm:          x86.ASHRB,
8847		reg: regInfo{
8848			inputs: []inputInfo{
8849				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8850			},
8851			outputs: []outputInfo{
8852				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8853			},
8854		},
8855	},
8856	{
8857		name:         "SARQ",
8858		argLen:       2,
8859		resultInArg0: true,
8860		clobberFlags: true,
8861		asm:          x86.ASARQ,
8862		reg: regInfo{
8863			inputs: []inputInfo{
8864				{1, 2},     // CX
8865				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8866			},
8867			outputs: []outputInfo{
8868				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8869			},
8870		},
8871	},
8872	{
8873		name:         "SARL",
8874		argLen:       2,
8875		resultInArg0: true,
8876		clobberFlags: true,
8877		asm:          x86.ASARL,
8878		reg: regInfo{
8879			inputs: []inputInfo{
8880				{1, 2},     // CX
8881				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8882			},
8883			outputs: []outputInfo{
8884				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8885			},
8886		},
8887	},
8888	{
8889		name:         "SARW",
8890		argLen:       2,
8891		resultInArg0: true,
8892		clobberFlags: true,
8893		asm:          x86.ASARW,
8894		reg: regInfo{
8895			inputs: []inputInfo{
8896				{1, 2},     // CX
8897				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8898			},
8899			outputs: []outputInfo{
8900				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8901			},
8902		},
8903	},
8904	{
8905		name:         "SARB",
8906		argLen:       2,
8907		resultInArg0: true,
8908		clobberFlags: true,
8909		asm:          x86.ASARB,
8910		reg: regInfo{
8911			inputs: []inputInfo{
8912				{1, 2},     // CX
8913				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8914			},
8915			outputs: []outputInfo{
8916				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8917			},
8918		},
8919	},
8920	{
8921		name:         "SARQconst",
8922		auxType:      auxInt8,
8923		argLen:       1,
8924		resultInArg0: true,
8925		clobberFlags: true,
8926		asm:          x86.ASARQ,
8927		reg: regInfo{
8928			inputs: []inputInfo{
8929				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8930			},
8931			outputs: []outputInfo{
8932				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8933			},
8934		},
8935	},
8936	{
8937		name:         "SARLconst",
8938		auxType:      auxInt8,
8939		argLen:       1,
8940		resultInArg0: true,
8941		clobberFlags: true,
8942		asm:          x86.ASARL,
8943		reg: regInfo{
8944			inputs: []inputInfo{
8945				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8946			},
8947			outputs: []outputInfo{
8948				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8949			},
8950		},
8951	},
8952	{
8953		name:         "SARWconst",
8954		auxType:      auxInt8,
8955		argLen:       1,
8956		resultInArg0: true,
8957		clobberFlags: true,
8958		asm:          x86.ASARW,
8959		reg: regInfo{
8960			inputs: []inputInfo{
8961				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8962			},
8963			outputs: []outputInfo{
8964				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8965			},
8966		},
8967	},
8968	{
8969		name:         "SARBconst",
8970		auxType:      auxInt8,
8971		argLen:       1,
8972		resultInArg0: true,
8973		clobberFlags: true,
8974		asm:          x86.ASARB,
8975		reg: regInfo{
8976			inputs: []inputInfo{
8977				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8978			},
8979			outputs: []outputInfo{
8980				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8981			},
8982		},
8983	},
8984	{
8985		name:         "SHRDQ",
8986		argLen:       3,
8987		resultInArg0: true,
8988		clobberFlags: true,
8989		asm:          x86.ASHRQ,
8990		reg: regInfo{
8991			inputs: []inputInfo{
8992				{2, 2},     // CX
8993				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8994				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8995			},
8996			outputs: []outputInfo{
8997				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
8998			},
8999		},
9000	},
9001	{
9002		name:         "SHLDQ",
9003		argLen:       3,
9004		resultInArg0: true,
9005		clobberFlags: true,
9006		asm:          x86.ASHLQ,
9007		reg: regInfo{
9008			inputs: []inputInfo{
9009				{2, 2},     // CX
9010				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9011				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9012			},
9013			outputs: []outputInfo{
9014				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9015			},
9016		},
9017	},
9018	{
9019		name:         "ROLQ",
9020		argLen:       2,
9021		resultInArg0: true,
9022		clobberFlags: true,
9023		asm:          x86.AROLQ,
9024		reg: regInfo{
9025			inputs: []inputInfo{
9026				{1, 2},     // CX
9027				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9028			},
9029			outputs: []outputInfo{
9030				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9031			},
9032		},
9033	},
9034	{
9035		name:         "ROLL",
9036		argLen:       2,
9037		resultInArg0: true,
9038		clobberFlags: true,
9039		asm:          x86.AROLL,
9040		reg: regInfo{
9041			inputs: []inputInfo{
9042				{1, 2},     // CX
9043				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9044			},
9045			outputs: []outputInfo{
9046				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9047			},
9048		},
9049	},
9050	{
9051		name:         "ROLW",
9052		argLen:       2,
9053		resultInArg0: true,
9054		clobberFlags: true,
9055		asm:          x86.AROLW,
9056		reg: regInfo{
9057			inputs: []inputInfo{
9058				{1, 2},     // CX
9059				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9060			},
9061			outputs: []outputInfo{
9062				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9063			},
9064		},
9065	},
9066	{
9067		name:         "ROLB",
9068		argLen:       2,
9069		resultInArg0: true,
9070		clobberFlags: true,
9071		asm:          x86.AROLB,
9072		reg: regInfo{
9073			inputs: []inputInfo{
9074				{1, 2},     // CX
9075				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9076			},
9077			outputs: []outputInfo{
9078				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9079			},
9080		},
9081	},
9082	{
9083		name:         "RORQ",
9084		argLen:       2,
9085		resultInArg0: true,
9086		clobberFlags: true,
9087		asm:          x86.ARORQ,
9088		reg: regInfo{
9089			inputs: []inputInfo{
9090				{1, 2},     // CX
9091				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9092			},
9093			outputs: []outputInfo{
9094				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9095			},
9096		},
9097	},
9098	{
9099		name:         "RORL",
9100		argLen:       2,
9101		resultInArg0: true,
9102		clobberFlags: true,
9103		asm:          x86.ARORL,
9104		reg: regInfo{
9105			inputs: []inputInfo{
9106				{1, 2},     // CX
9107				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9108			},
9109			outputs: []outputInfo{
9110				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9111			},
9112		},
9113	},
9114	{
9115		name:         "RORW",
9116		argLen:       2,
9117		resultInArg0: true,
9118		clobberFlags: true,
9119		asm:          x86.ARORW,
9120		reg: regInfo{
9121			inputs: []inputInfo{
9122				{1, 2},     // CX
9123				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9124			},
9125			outputs: []outputInfo{
9126				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9127			},
9128		},
9129	},
9130	{
9131		name:         "RORB",
9132		argLen:       2,
9133		resultInArg0: true,
9134		clobberFlags: true,
9135		asm:          x86.ARORB,
9136		reg: regInfo{
9137			inputs: []inputInfo{
9138				{1, 2},     // CX
9139				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9140			},
9141			outputs: []outputInfo{
9142				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9143			},
9144		},
9145	},
9146	{
9147		name:         "ROLQconst",
9148		auxType:      auxInt8,
9149		argLen:       1,
9150		resultInArg0: true,
9151		clobberFlags: true,
9152		asm:          x86.AROLQ,
9153		reg: regInfo{
9154			inputs: []inputInfo{
9155				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9156			},
9157			outputs: []outputInfo{
9158				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9159			},
9160		},
9161	},
9162	{
9163		name:         "ROLLconst",
9164		auxType:      auxInt8,
9165		argLen:       1,
9166		resultInArg0: true,
9167		clobberFlags: true,
9168		asm:          x86.AROLL,
9169		reg: regInfo{
9170			inputs: []inputInfo{
9171				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9172			},
9173			outputs: []outputInfo{
9174				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9175			},
9176		},
9177	},
9178	{
9179		name:         "ROLWconst",
9180		auxType:      auxInt8,
9181		argLen:       1,
9182		resultInArg0: true,
9183		clobberFlags: true,
9184		asm:          x86.AROLW,
9185		reg: regInfo{
9186			inputs: []inputInfo{
9187				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9188			},
9189			outputs: []outputInfo{
9190				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9191			},
9192		},
9193	},
9194	{
9195		name:         "ROLBconst",
9196		auxType:      auxInt8,
9197		argLen:       1,
9198		resultInArg0: true,
9199		clobberFlags: true,
9200		asm:          x86.AROLB,
9201		reg: regInfo{
9202			inputs: []inputInfo{
9203				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9204			},
9205			outputs: []outputInfo{
9206				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9207			},
9208		},
9209	},
9210	{
9211		name:           "ADDLload",
9212		auxType:        auxSymOff,
9213		argLen:         3,
9214		resultInArg0:   true,
9215		clobberFlags:   true,
9216		faultOnNilArg1: true,
9217		symEffect:      SymRead,
9218		asm:            x86.AADDL,
9219		reg: regInfo{
9220			inputs: []inputInfo{
9221				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9222				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9223			},
9224			outputs: []outputInfo{
9225				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9226			},
9227		},
9228	},
9229	{
9230		name:           "ADDQload",
9231		auxType:        auxSymOff,
9232		argLen:         3,
9233		resultInArg0:   true,
9234		clobberFlags:   true,
9235		faultOnNilArg1: true,
9236		symEffect:      SymRead,
9237		asm:            x86.AADDQ,
9238		reg: regInfo{
9239			inputs: []inputInfo{
9240				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9241				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9242			},
9243			outputs: []outputInfo{
9244				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9245			},
9246		},
9247	},
9248	{
9249		name:           "SUBQload",
9250		auxType:        auxSymOff,
9251		argLen:         3,
9252		resultInArg0:   true,
9253		clobberFlags:   true,
9254		faultOnNilArg1: true,
9255		symEffect:      SymRead,
9256		asm:            x86.ASUBQ,
9257		reg: regInfo{
9258			inputs: []inputInfo{
9259				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9260				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9261			},
9262			outputs: []outputInfo{
9263				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9264			},
9265		},
9266	},
9267	{
9268		name:           "SUBLload",
9269		auxType:        auxSymOff,
9270		argLen:         3,
9271		resultInArg0:   true,
9272		clobberFlags:   true,
9273		faultOnNilArg1: true,
9274		symEffect:      SymRead,
9275		asm:            x86.ASUBL,
9276		reg: regInfo{
9277			inputs: []inputInfo{
9278				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9279				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9280			},
9281			outputs: []outputInfo{
9282				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9283			},
9284		},
9285	},
9286	{
9287		name:           "ANDLload",
9288		auxType:        auxSymOff,
9289		argLen:         3,
9290		resultInArg0:   true,
9291		clobberFlags:   true,
9292		faultOnNilArg1: true,
9293		symEffect:      SymRead,
9294		asm:            x86.AANDL,
9295		reg: regInfo{
9296			inputs: []inputInfo{
9297				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9298				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9299			},
9300			outputs: []outputInfo{
9301				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9302			},
9303		},
9304	},
9305	{
9306		name:           "ANDQload",
9307		auxType:        auxSymOff,
9308		argLen:         3,
9309		resultInArg0:   true,
9310		clobberFlags:   true,
9311		faultOnNilArg1: true,
9312		symEffect:      SymRead,
9313		asm:            x86.AANDQ,
9314		reg: regInfo{
9315			inputs: []inputInfo{
9316				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9317				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9318			},
9319			outputs: []outputInfo{
9320				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9321			},
9322		},
9323	},
9324	{
9325		name:           "ORQload",
9326		auxType:        auxSymOff,
9327		argLen:         3,
9328		resultInArg0:   true,
9329		clobberFlags:   true,
9330		faultOnNilArg1: true,
9331		symEffect:      SymRead,
9332		asm:            x86.AORQ,
9333		reg: regInfo{
9334			inputs: []inputInfo{
9335				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9336				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9337			},
9338			outputs: []outputInfo{
9339				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9340			},
9341		},
9342	},
9343	{
9344		name:           "ORLload",
9345		auxType:        auxSymOff,
9346		argLen:         3,
9347		resultInArg0:   true,
9348		clobberFlags:   true,
9349		faultOnNilArg1: true,
9350		symEffect:      SymRead,
9351		asm:            x86.AORL,
9352		reg: regInfo{
9353			inputs: []inputInfo{
9354				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9355				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9356			},
9357			outputs: []outputInfo{
9358				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9359			},
9360		},
9361	},
9362	{
9363		name:           "XORQload",
9364		auxType:        auxSymOff,
9365		argLen:         3,
9366		resultInArg0:   true,
9367		clobberFlags:   true,
9368		faultOnNilArg1: true,
9369		symEffect:      SymRead,
9370		asm:            x86.AXORQ,
9371		reg: regInfo{
9372			inputs: []inputInfo{
9373				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9374				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9375			},
9376			outputs: []outputInfo{
9377				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9378			},
9379		},
9380	},
9381	{
9382		name:           "XORLload",
9383		auxType:        auxSymOff,
9384		argLen:         3,
9385		resultInArg0:   true,
9386		clobberFlags:   true,
9387		faultOnNilArg1: true,
9388		symEffect:      SymRead,
9389		asm:            x86.AXORL,
9390		reg: regInfo{
9391			inputs: []inputInfo{
9392				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9393				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9394			},
9395			outputs: []outputInfo{
9396				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9397			},
9398		},
9399	},
9400	{
9401		name:         "ADDLloadidx1",
9402		auxType:      auxSymOff,
9403		argLen:       4,
9404		resultInArg0: true,
9405		clobberFlags: true,
9406		symEffect:    SymRead,
9407		asm:          x86.AADDL,
9408		scale:        1,
9409		reg: regInfo{
9410			inputs: []inputInfo{
9411				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9412				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9413				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9414			},
9415			outputs: []outputInfo{
9416				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9417			},
9418		},
9419	},
9420	{
9421		name:         "ADDLloadidx4",
9422		auxType:      auxSymOff,
9423		argLen:       4,
9424		resultInArg0: true,
9425		clobberFlags: true,
9426		symEffect:    SymRead,
9427		asm:          x86.AADDL,
9428		scale:        4,
9429		reg: regInfo{
9430			inputs: []inputInfo{
9431				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9432				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9433				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9434			},
9435			outputs: []outputInfo{
9436				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9437			},
9438		},
9439	},
9440	{
9441		name:         "ADDLloadidx8",
9442		auxType:      auxSymOff,
9443		argLen:       4,
9444		resultInArg0: true,
9445		clobberFlags: true,
9446		symEffect:    SymRead,
9447		asm:          x86.AADDL,
9448		scale:        8,
9449		reg: regInfo{
9450			inputs: []inputInfo{
9451				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9452				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9453				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9454			},
9455			outputs: []outputInfo{
9456				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9457			},
9458		},
9459	},
9460	{
9461		name:         "ADDQloadidx1",
9462		auxType:      auxSymOff,
9463		argLen:       4,
9464		resultInArg0: true,
9465		clobberFlags: true,
9466		symEffect:    SymRead,
9467		asm:          x86.AADDQ,
9468		scale:        1,
9469		reg: regInfo{
9470			inputs: []inputInfo{
9471				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9472				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9473				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9474			},
9475			outputs: []outputInfo{
9476				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9477			},
9478		},
9479	},
9480	{
9481		name:         "ADDQloadidx8",
9482		auxType:      auxSymOff,
9483		argLen:       4,
9484		resultInArg0: true,
9485		clobberFlags: true,
9486		symEffect:    SymRead,
9487		asm:          x86.AADDQ,
9488		scale:        8,
9489		reg: regInfo{
9490			inputs: []inputInfo{
9491				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9492				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9493				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9494			},
9495			outputs: []outputInfo{
9496				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9497			},
9498		},
9499	},
9500	{
9501		name:         "SUBLloadidx1",
9502		auxType:      auxSymOff,
9503		argLen:       4,
9504		resultInArg0: true,
9505		clobberFlags: true,
9506		symEffect:    SymRead,
9507		asm:          x86.ASUBL,
9508		scale:        1,
9509		reg: regInfo{
9510			inputs: []inputInfo{
9511				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9512				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9513				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9514			},
9515			outputs: []outputInfo{
9516				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9517			},
9518		},
9519	},
9520	{
9521		name:         "SUBLloadidx4",
9522		auxType:      auxSymOff,
9523		argLen:       4,
9524		resultInArg0: true,
9525		clobberFlags: true,
9526		symEffect:    SymRead,
9527		asm:          x86.ASUBL,
9528		scale:        4,
9529		reg: regInfo{
9530			inputs: []inputInfo{
9531				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9532				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9533				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9534			},
9535			outputs: []outputInfo{
9536				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9537			},
9538		},
9539	},
9540	{
9541		name:         "SUBLloadidx8",
9542		auxType:      auxSymOff,
9543		argLen:       4,
9544		resultInArg0: true,
9545		clobberFlags: true,
9546		symEffect:    SymRead,
9547		asm:          x86.ASUBL,
9548		scale:        8,
9549		reg: regInfo{
9550			inputs: []inputInfo{
9551				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9552				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9553				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9554			},
9555			outputs: []outputInfo{
9556				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9557			},
9558		},
9559	},
9560	{
9561		name:         "SUBQloadidx1",
9562		auxType:      auxSymOff,
9563		argLen:       4,
9564		resultInArg0: true,
9565		clobberFlags: true,
9566		symEffect:    SymRead,
9567		asm:          x86.ASUBQ,
9568		scale:        1,
9569		reg: regInfo{
9570			inputs: []inputInfo{
9571				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9572				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9573				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9574			},
9575			outputs: []outputInfo{
9576				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9577			},
9578		},
9579	},
9580	{
9581		name:         "SUBQloadidx8",
9582		auxType:      auxSymOff,
9583		argLen:       4,
9584		resultInArg0: true,
9585		clobberFlags: true,
9586		symEffect:    SymRead,
9587		asm:          x86.ASUBQ,
9588		scale:        8,
9589		reg: regInfo{
9590			inputs: []inputInfo{
9591				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9592				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9593				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9594			},
9595			outputs: []outputInfo{
9596				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9597			},
9598		},
9599	},
9600	{
9601		name:         "ANDLloadidx1",
9602		auxType:      auxSymOff,
9603		argLen:       4,
9604		resultInArg0: true,
9605		clobberFlags: true,
9606		symEffect:    SymRead,
9607		asm:          x86.AANDL,
9608		scale:        1,
9609		reg: regInfo{
9610			inputs: []inputInfo{
9611				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9612				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9613				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9614			},
9615			outputs: []outputInfo{
9616				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9617			},
9618		},
9619	},
9620	{
9621		name:         "ANDLloadidx4",
9622		auxType:      auxSymOff,
9623		argLen:       4,
9624		resultInArg0: true,
9625		clobberFlags: true,
9626		symEffect:    SymRead,
9627		asm:          x86.AANDL,
9628		scale:        4,
9629		reg: regInfo{
9630			inputs: []inputInfo{
9631				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9632				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9633				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9634			},
9635			outputs: []outputInfo{
9636				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9637			},
9638		},
9639	},
9640	{
9641		name:         "ANDLloadidx8",
9642		auxType:      auxSymOff,
9643		argLen:       4,
9644		resultInArg0: true,
9645		clobberFlags: true,
9646		symEffect:    SymRead,
9647		asm:          x86.AANDL,
9648		scale:        8,
9649		reg: regInfo{
9650			inputs: []inputInfo{
9651				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9652				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9653				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9654			},
9655			outputs: []outputInfo{
9656				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9657			},
9658		},
9659	},
9660	{
9661		name:         "ANDQloadidx1",
9662		auxType:      auxSymOff,
9663		argLen:       4,
9664		resultInArg0: true,
9665		clobberFlags: true,
9666		symEffect:    SymRead,
9667		asm:          x86.AANDQ,
9668		scale:        1,
9669		reg: regInfo{
9670			inputs: []inputInfo{
9671				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9672				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9673				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9674			},
9675			outputs: []outputInfo{
9676				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9677			},
9678		},
9679	},
9680	{
9681		name:         "ANDQloadidx8",
9682		auxType:      auxSymOff,
9683		argLen:       4,
9684		resultInArg0: true,
9685		clobberFlags: true,
9686		symEffect:    SymRead,
9687		asm:          x86.AANDQ,
9688		scale:        8,
9689		reg: regInfo{
9690			inputs: []inputInfo{
9691				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9692				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9693				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9694			},
9695			outputs: []outputInfo{
9696				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9697			},
9698		},
9699	},
9700	{
9701		name:         "ORLloadidx1",
9702		auxType:      auxSymOff,
9703		argLen:       4,
9704		resultInArg0: true,
9705		clobberFlags: true,
9706		symEffect:    SymRead,
9707		asm:          x86.AORL,
9708		scale:        1,
9709		reg: regInfo{
9710			inputs: []inputInfo{
9711				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9712				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9713				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9714			},
9715			outputs: []outputInfo{
9716				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9717			},
9718		},
9719	},
9720	{
9721		name:         "ORLloadidx4",
9722		auxType:      auxSymOff,
9723		argLen:       4,
9724		resultInArg0: true,
9725		clobberFlags: true,
9726		symEffect:    SymRead,
9727		asm:          x86.AORL,
9728		scale:        4,
9729		reg: regInfo{
9730			inputs: []inputInfo{
9731				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9732				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9733				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9734			},
9735			outputs: []outputInfo{
9736				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9737			},
9738		},
9739	},
9740	{
9741		name:         "ORLloadidx8",
9742		auxType:      auxSymOff,
9743		argLen:       4,
9744		resultInArg0: true,
9745		clobberFlags: true,
9746		symEffect:    SymRead,
9747		asm:          x86.AORL,
9748		scale:        8,
9749		reg: regInfo{
9750			inputs: []inputInfo{
9751				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9752				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9753				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9754			},
9755			outputs: []outputInfo{
9756				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9757			},
9758		},
9759	},
9760	{
9761		name:         "ORQloadidx1",
9762		auxType:      auxSymOff,
9763		argLen:       4,
9764		resultInArg0: true,
9765		clobberFlags: true,
9766		symEffect:    SymRead,
9767		asm:          x86.AORQ,
9768		scale:        1,
9769		reg: regInfo{
9770			inputs: []inputInfo{
9771				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9772				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9773				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9774			},
9775			outputs: []outputInfo{
9776				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9777			},
9778		},
9779	},
9780	{
9781		name:         "ORQloadidx8",
9782		auxType:      auxSymOff,
9783		argLen:       4,
9784		resultInArg0: true,
9785		clobberFlags: true,
9786		symEffect:    SymRead,
9787		asm:          x86.AORQ,
9788		scale:        8,
9789		reg: regInfo{
9790			inputs: []inputInfo{
9791				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9792				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9793				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9794			},
9795			outputs: []outputInfo{
9796				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9797			},
9798		},
9799	},
9800	{
9801		name:         "XORLloadidx1",
9802		auxType:      auxSymOff,
9803		argLen:       4,
9804		resultInArg0: true,
9805		clobberFlags: true,
9806		symEffect:    SymRead,
9807		asm:          x86.AXORL,
9808		scale:        1,
9809		reg: regInfo{
9810			inputs: []inputInfo{
9811				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9812				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9813				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9814			},
9815			outputs: []outputInfo{
9816				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9817			},
9818		},
9819	},
9820	{
9821		name:         "XORLloadidx4",
9822		auxType:      auxSymOff,
9823		argLen:       4,
9824		resultInArg0: true,
9825		clobberFlags: true,
9826		symEffect:    SymRead,
9827		asm:          x86.AXORL,
9828		scale:        4,
9829		reg: regInfo{
9830			inputs: []inputInfo{
9831				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9832				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9833				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9834			},
9835			outputs: []outputInfo{
9836				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9837			},
9838		},
9839	},
9840	{
9841		name:         "XORLloadidx8",
9842		auxType:      auxSymOff,
9843		argLen:       4,
9844		resultInArg0: true,
9845		clobberFlags: true,
9846		symEffect:    SymRead,
9847		asm:          x86.AXORL,
9848		scale:        8,
9849		reg: regInfo{
9850			inputs: []inputInfo{
9851				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9852				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9853				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9854			},
9855			outputs: []outputInfo{
9856				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9857			},
9858		},
9859	},
9860	{
9861		name:         "XORQloadidx1",
9862		auxType:      auxSymOff,
9863		argLen:       4,
9864		resultInArg0: true,
9865		clobberFlags: true,
9866		symEffect:    SymRead,
9867		asm:          x86.AXORQ,
9868		scale:        1,
9869		reg: regInfo{
9870			inputs: []inputInfo{
9871				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9872				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9873				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9874			},
9875			outputs: []outputInfo{
9876				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9877			},
9878		},
9879	},
9880	{
9881		name:         "XORQloadidx8",
9882		auxType:      auxSymOff,
9883		argLen:       4,
9884		resultInArg0: true,
9885		clobberFlags: true,
9886		symEffect:    SymRead,
9887		asm:          x86.AXORQ,
9888		scale:        8,
9889		reg: regInfo{
9890			inputs: []inputInfo{
9891				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9892				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9893				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9894			},
9895			outputs: []outputInfo{
9896				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
9897			},
9898		},
9899	},
9900	{
9901		name:           "ADDQmodify",
9902		auxType:        auxSymOff,
9903		argLen:         3,
9904		clobberFlags:   true,
9905		faultOnNilArg0: true,
9906		symEffect:      SymRead | SymWrite,
9907		asm:            x86.AADDQ,
9908		reg: regInfo{
9909			inputs: []inputInfo{
9910				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9911				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9912			},
9913		},
9914	},
9915	{
9916		name:           "SUBQmodify",
9917		auxType:        auxSymOff,
9918		argLen:         3,
9919		clobberFlags:   true,
9920		faultOnNilArg0: true,
9921		symEffect:      SymRead | SymWrite,
9922		asm:            x86.ASUBQ,
9923		reg: regInfo{
9924			inputs: []inputInfo{
9925				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9926				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9927			},
9928		},
9929	},
9930	{
9931		name:           "ANDQmodify",
9932		auxType:        auxSymOff,
9933		argLen:         3,
9934		clobberFlags:   true,
9935		faultOnNilArg0: true,
9936		symEffect:      SymRead | SymWrite,
9937		asm:            x86.AANDQ,
9938		reg: regInfo{
9939			inputs: []inputInfo{
9940				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9941				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9942			},
9943		},
9944	},
9945	{
9946		name:           "ORQmodify",
9947		auxType:        auxSymOff,
9948		argLen:         3,
9949		clobberFlags:   true,
9950		faultOnNilArg0: true,
9951		symEffect:      SymRead | SymWrite,
9952		asm:            x86.AORQ,
9953		reg: regInfo{
9954			inputs: []inputInfo{
9955				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9956				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9957			},
9958		},
9959	},
9960	{
9961		name:           "XORQmodify",
9962		auxType:        auxSymOff,
9963		argLen:         3,
9964		clobberFlags:   true,
9965		faultOnNilArg0: true,
9966		symEffect:      SymRead | SymWrite,
9967		asm:            x86.AXORQ,
9968		reg: regInfo{
9969			inputs: []inputInfo{
9970				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9971				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9972			},
9973		},
9974	},
9975	{
9976		name:           "ADDLmodify",
9977		auxType:        auxSymOff,
9978		argLen:         3,
9979		clobberFlags:   true,
9980		faultOnNilArg0: true,
9981		symEffect:      SymRead | SymWrite,
9982		asm:            x86.AADDL,
9983		reg: regInfo{
9984			inputs: []inputInfo{
9985				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
9986				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
9987			},
9988		},
9989	},
9990	{
9991		name:           "SUBLmodify",
9992		auxType:        auxSymOff,
9993		argLen:         3,
9994		clobberFlags:   true,
9995		faultOnNilArg0: true,
9996		symEffect:      SymRead | SymWrite,
9997		asm:            x86.ASUBL,
9998		reg: regInfo{
9999			inputs: []inputInfo{
10000				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10001				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10002			},
10003		},
10004	},
10005	{
10006		name:           "ANDLmodify",
10007		auxType:        auxSymOff,
10008		argLen:         3,
10009		clobberFlags:   true,
10010		faultOnNilArg0: true,
10011		symEffect:      SymRead | SymWrite,
10012		asm:            x86.AANDL,
10013		reg: regInfo{
10014			inputs: []inputInfo{
10015				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10016				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10017			},
10018		},
10019	},
10020	{
10021		name:           "ORLmodify",
10022		auxType:        auxSymOff,
10023		argLen:         3,
10024		clobberFlags:   true,
10025		faultOnNilArg0: true,
10026		symEffect:      SymRead | SymWrite,
10027		asm:            x86.AORL,
10028		reg: regInfo{
10029			inputs: []inputInfo{
10030				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10031				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10032			},
10033		},
10034	},
10035	{
10036		name:           "XORLmodify",
10037		auxType:        auxSymOff,
10038		argLen:         3,
10039		clobberFlags:   true,
10040		faultOnNilArg0: true,
10041		symEffect:      SymRead | SymWrite,
10042		asm:            x86.AXORL,
10043		reg: regInfo{
10044			inputs: []inputInfo{
10045				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10046				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10047			},
10048		},
10049	},
10050	{
10051		name:         "ADDQmodifyidx1",
10052		auxType:      auxSymOff,
10053		argLen:       4,
10054		clobberFlags: true,
10055		symEffect:    SymRead | SymWrite,
10056		asm:          x86.AADDQ,
10057		scale:        1,
10058		reg: regInfo{
10059			inputs: []inputInfo{
10060				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10061				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10062				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10063			},
10064		},
10065	},
10066	{
10067		name:         "ADDQmodifyidx8",
10068		auxType:      auxSymOff,
10069		argLen:       4,
10070		clobberFlags: true,
10071		symEffect:    SymRead | SymWrite,
10072		asm:          x86.AADDQ,
10073		scale:        8,
10074		reg: regInfo{
10075			inputs: []inputInfo{
10076				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10077				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10078				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10079			},
10080		},
10081	},
10082	{
10083		name:         "SUBQmodifyidx1",
10084		auxType:      auxSymOff,
10085		argLen:       4,
10086		clobberFlags: true,
10087		symEffect:    SymRead | SymWrite,
10088		asm:          x86.ASUBQ,
10089		scale:        1,
10090		reg: regInfo{
10091			inputs: []inputInfo{
10092				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10093				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10094				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10095			},
10096		},
10097	},
10098	{
10099		name:         "SUBQmodifyidx8",
10100		auxType:      auxSymOff,
10101		argLen:       4,
10102		clobberFlags: true,
10103		symEffect:    SymRead | SymWrite,
10104		asm:          x86.ASUBQ,
10105		scale:        8,
10106		reg: regInfo{
10107			inputs: []inputInfo{
10108				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10109				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10110				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10111			},
10112		},
10113	},
10114	{
10115		name:         "ANDQmodifyidx1",
10116		auxType:      auxSymOff,
10117		argLen:       4,
10118		clobberFlags: true,
10119		symEffect:    SymRead | SymWrite,
10120		asm:          x86.AANDQ,
10121		scale:        1,
10122		reg: regInfo{
10123			inputs: []inputInfo{
10124				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10125				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10126				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10127			},
10128		},
10129	},
10130	{
10131		name:         "ANDQmodifyidx8",
10132		auxType:      auxSymOff,
10133		argLen:       4,
10134		clobberFlags: true,
10135		symEffect:    SymRead | SymWrite,
10136		asm:          x86.AANDQ,
10137		scale:        8,
10138		reg: regInfo{
10139			inputs: []inputInfo{
10140				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10141				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10142				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10143			},
10144		},
10145	},
10146	{
10147		name:         "ORQmodifyidx1",
10148		auxType:      auxSymOff,
10149		argLen:       4,
10150		clobberFlags: true,
10151		symEffect:    SymRead | SymWrite,
10152		asm:          x86.AORQ,
10153		scale:        1,
10154		reg: regInfo{
10155			inputs: []inputInfo{
10156				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10157				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10158				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10159			},
10160		},
10161	},
10162	{
10163		name:         "ORQmodifyidx8",
10164		auxType:      auxSymOff,
10165		argLen:       4,
10166		clobberFlags: true,
10167		symEffect:    SymRead | SymWrite,
10168		asm:          x86.AORQ,
10169		scale:        8,
10170		reg: regInfo{
10171			inputs: []inputInfo{
10172				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10173				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10174				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10175			},
10176		},
10177	},
10178	{
10179		name:         "XORQmodifyidx1",
10180		auxType:      auxSymOff,
10181		argLen:       4,
10182		clobberFlags: true,
10183		symEffect:    SymRead | SymWrite,
10184		asm:          x86.AXORQ,
10185		scale:        1,
10186		reg: regInfo{
10187			inputs: []inputInfo{
10188				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10189				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10190				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10191			},
10192		},
10193	},
10194	{
10195		name:         "XORQmodifyidx8",
10196		auxType:      auxSymOff,
10197		argLen:       4,
10198		clobberFlags: true,
10199		symEffect:    SymRead | SymWrite,
10200		asm:          x86.AXORQ,
10201		scale:        8,
10202		reg: regInfo{
10203			inputs: []inputInfo{
10204				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10205				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10206				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10207			},
10208		},
10209	},
10210	{
10211		name:         "ADDLmodifyidx1",
10212		auxType:      auxSymOff,
10213		argLen:       4,
10214		clobberFlags: true,
10215		symEffect:    SymRead | SymWrite,
10216		asm:          x86.AADDL,
10217		scale:        1,
10218		reg: regInfo{
10219			inputs: []inputInfo{
10220				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10221				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10222				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10223			},
10224		},
10225	},
10226	{
10227		name:         "ADDLmodifyidx4",
10228		auxType:      auxSymOff,
10229		argLen:       4,
10230		clobberFlags: true,
10231		symEffect:    SymRead | SymWrite,
10232		asm:          x86.AADDL,
10233		scale:        4,
10234		reg: regInfo{
10235			inputs: []inputInfo{
10236				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10237				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10238				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10239			},
10240		},
10241	},
10242	{
10243		name:         "ADDLmodifyidx8",
10244		auxType:      auxSymOff,
10245		argLen:       4,
10246		clobberFlags: true,
10247		symEffect:    SymRead | SymWrite,
10248		asm:          x86.AADDL,
10249		scale:        8,
10250		reg: regInfo{
10251			inputs: []inputInfo{
10252				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10253				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10254				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10255			},
10256		},
10257	},
10258	{
10259		name:         "SUBLmodifyidx1",
10260		auxType:      auxSymOff,
10261		argLen:       4,
10262		clobberFlags: true,
10263		symEffect:    SymRead | SymWrite,
10264		asm:          x86.ASUBL,
10265		scale:        1,
10266		reg: regInfo{
10267			inputs: []inputInfo{
10268				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10269				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10270				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10271			},
10272		},
10273	},
10274	{
10275		name:         "SUBLmodifyidx4",
10276		auxType:      auxSymOff,
10277		argLen:       4,
10278		clobberFlags: true,
10279		symEffect:    SymRead | SymWrite,
10280		asm:          x86.ASUBL,
10281		scale:        4,
10282		reg: regInfo{
10283			inputs: []inputInfo{
10284				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10285				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10286				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10287			},
10288		},
10289	},
10290	{
10291		name:         "SUBLmodifyidx8",
10292		auxType:      auxSymOff,
10293		argLen:       4,
10294		clobberFlags: true,
10295		symEffect:    SymRead | SymWrite,
10296		asm:          x86.ASUBL,
10297		scale:        8,
10298		reg: regInfo{
10299			inputs: []inputInfo{
10300				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10301				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10302				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10303			},
10304		},
10305	},
10306	{
10307		name:         "ANDLmodifyidx1",
10308		auxType:      auxSymOff,
10309		argLen:       4,
10310		clobberFlags: true,
10311		symEffect:    SymRead | SymWrite,
10312		asm:          x86.AANDL,
10313		scale:        1,
10314		reg: regInfo{
10315			inputs: []inputInfo{
10316				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10317				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10318				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10319			},
10320		},
10321	},
10322	{
10323		name:         "ANDLmodifyidx4",
10324		auxType:      auxSymOff,
10325		argLen:       4,
10326		clobberFlags: true,
10327		symEffect:    SymRead | SymWrite,
10328		asm:          x86.AANDL,
10329		scale:        4,
10330		reg: regInfo{
10331			inputs: []inputInfo{
10332				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10333				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10334				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10335			},
10336		},
10337	},
10338	{
10339		name:         "ANDLmodifyidx8",
10340		auxType:      auxSymOff,
10341		argLen:       4,
10342		clobberFlags: true,
10343		symEffect:    SymRead | SymWrite,
10344		asm:          x86.AANDL,
10345		scale:        8,
10346		reg: regInfo{
10347			inputs: []inputInfo{
10348				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10349				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10350				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10351			},
10352		},
10353	},
10354	{
10355		name:         "ORLmodifyidx1",
10356		auxType:      auxSymOff,
10357		argLen:       4,
10358		clobberFlags: true,
10359		symEffect:    SymRead | SymWrite,
10360		asm:          x86.AORL,
10361		scale:        1,
10362		reg: regInfo{
10363			inputs: []inputInfo{
10364				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10365				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10366				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10367			},
10368		},
10369	},
10370	{
10371		name:         "ORLmodifyidx4",
10372		auxType:      auxSymOff,
10373		argLen:       4,
10374		clobberFlags: true,
10375		symEffect:    SymRead | SymWrite,
10376		asm:          x86.AORL,
10377		scale:        4,
10378		reg: regInfo{
10379			inputs: []inputInfo{
10380				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10381				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10382				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10383			},
10384		},
10385	},
10386	{
10387		name:         "ORLmodifyidx8",
10388		auxType:      auxSymOff,
10389		argLen:       4,
10390		clobberFlags: true,
10391		symEffect:    SymRead | SymWrite,
10392		asm:          x86.AORL,
10393		scale:        8,
10394		reg: regInfo{
10395			inputs: []inputInfo{
10396				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10397				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10398				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10399			},
10400		},
10401	},
10402	{
10403		name:         "XORLmodifyidx1",
10404		auxType:      auxSymOff,
10405		argLen:       4,
10406		clobberFlags: true,
10407		symEffect:    SymRead | SymWrite,
10408		asm:          x86.AXORL,
10409		scale:        1,
10410		reg: regInfo{
10411			inputs: []inputInfo{
10412				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10413				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10414				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10415			},
10416		},
10417	},
10418	{
10419		name:         "XORLmodifyidx4",
10420		auxType:      auxSymOff,
10421		argLen:       4,
10422		clobberFlags: true,
10423		symEffect:    SymRead | SymWrite,
10424		asm:          x86.AXORL,
10425		scale:        4,
10426		reg: regInfo{
10427			inputs: []inputInfo{
10428				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10429				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10430				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10431			},
10432		},
10433	},
10434	{
10435		name:         "XORLmodifyidx8",
10436		auxType:      auxSymOff,
10437		argLen:       4,
10438		clobberFlags: true,
10439		symEffect:    SymRead | SymWrite,
10440		asm:          x86.AXORL,
10441		scale:        8,
10442		reg: regInfo{
10443			inputs: []inputInfo{
10444				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10445				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10446				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10447			},
10448		},
10449	},
10450	{
10451		name:         "ADDQconstmodifyidx1",
10452		auxType:      auxSymValAndOff,
10453		argLen:       3,
10454		clobberFlags: true,
10455		symEffect:    SymRead | SymWrite,
10456		asm:          x86.AADDQ,
10457		scale:        1,
10458		reg: regInfo{
10459			inputs: []inputInfo{
10460				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10461				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10462			},
10463		},
10464	},
10465	{
10466		name:         "ADDQconstmodifyidx8",
10467		auxType:      auxSymValAndOff,
10468		argLen:       3,
10469		clobberFlags: true,
10470		symEffect:    SymRead | SymWrite,
10471		asm:          x86.AADDQ,
10472		scale:        8,
10473		reg: regInfo{
10474			inputs: []inputInfo{
10475				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10476				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10477			},
10478		},
10479	},
10480	{
10481		name:         "ANDQconstmodifyidx1",
10482		auxType:      auxSymValAndOff,
10483		argLen:       3,
10484		clobberFlags: true,
10485		symEffect:    SymRead | SymWrite,
10486		asm:          x86.AANDQ,
10487		scale:        1,
10488		reg: regInfo{
10489			inputs: []inputInfo{
10490				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10491				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10492			},
10493		},
10494	},
10495	{
10496		name:         "ANDQconstmodifyidx8",
10497		auxType:      auxSymValAndOff,
10498		argLen:       3,
10499		clobberFlags: true,
10500		symEffect:    SymRead | SymWrite,
10501		asm:          x86.AANDQ,
10502		scale:        8,
10503		reg: regInfo{
10504			inputs: []inputInfo{
10505				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10506				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10507			},
10508		},
10509	},
10510	{
10511		name:         "ORQconstmodifyidx1",
10512		auxType:      auxSymValAndOff,
10513		argLen:       3,
10514		clobberFlags: true,
10515		symEffect:    SymRead | SymWrite,
10516		asm:          x86.AORQ,
10517		scale:        1,
10518		reg: regInfo{
10519			inputs: []inputInfo{
10520				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10521				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10522			},
10523		},
10524	},
10525	{
10526		name:         "ORQconstmodifyidx8",
10527		auxType:      auxSymValAndOff,
10528		argLen:       3,
10529		clobberFlags: true,
10530		symEffect:    SymRead | SymWrite,
10531		asm:          x86.AORQ,
10532		scale:        8,
10533		reg: regInfo{
10534			inputs: []inputInfo{
10535				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10536				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10537			},
10538		},
10539	},
10540	{
10541		name:         "XORQconstmodifyidx1",
10542		auxType:      auxSymValAndOff,
10543		argLen:       3,
10544		clobberFlags: true,
10545		symEffect:    SymRead | SymWrite,
10546		asm:          x86.AXORQ,
10547		scale:        1,
10548		reg: regInfo{
10549			inputs: []inputInfo{
10550				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10551				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10552			},
10553		},
10554	},
10555	{
10556		name:         "XORQconstmodifyidx8",
10557		auxType:      auxSymValAndOff,
10558		argLen:       3,
10559		clobberFlags: true,
10560		symEffect:    SymRead | SymWrite,
10561		asm:          x86.AXORQ,
10562		scale:        8,
10563		reg: regInfo{
10564			inputs: []inputInfo{
10565				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10566				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10567			},
10568		},
10569	},
10570	{
10571		name:         "ADDLconstmodifyidx1",
10572		auxType:      auxSymValAndOff,
10573		argLen:       3,
10574		clobberFlags: true,
10575		symEffect:    SymRead | SymWrite,
10576		asm:          x86.AADDL,
10577		scale:        1,
10578		reg: regInfo{
10579			inputs: []inputInfo{
10580				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10581				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10582			},
10583		},
10584	},
10585	{
10586		name:         "ADDLconstmodifyidx4",
10587		auxType:      auxSymValAndOff,
10588		argLen:       3,
10589		clobberFlags: true,
10590		symEffect:    SymRead | SymWrite,
10591		asm:          x86.AADDL,
10592		scale:        4,
10593		reg: regInfo{
10594			inputs: []inputInfo{
10595				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10596				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10597			},
10598		},
10599	},
10600	{
10601		name:         "ADDLconstmodifyidx8",
10602		auxType:      auxSymValAndOff,
10603		argLen:       3,
10604		clobberFlags: true,
10605		symEffect:    SymRead | SymWrite,
10606		asm:          x86.AADDL,
10607		scale:        8,
10608		reg: regInfo{
10609			inputs: []inputInfo{
10610				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10611				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10612			},
10613		},
10614	},
10615	{
10616		name:         "ANDLconstmodifyidx1",
10617		auxType:      auxSymValAndOff,
10618		argLen:       3,
10619		clobberFlags: true,
10620		symEffect:    SymRead | SymWrite,
10621		asm:          x86.AANDL,
10622		scale:        1,
10623		reg: regInfo{
10624			inputs: []inputInfo{
10625				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10626				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10627			},
10628		},
10629	},
10630	{
10631		name:         "ANDLconstmodifyidx4",
10632		auxType:      auxSymValAndOff,
10633		argLen:       3,
10634		clobberFlags: true,
10635		symEffect:    SymRead | SymWrite,
10636		asm:          x86.AANDL,
10637		scale:        4,
10638		reg: regInfo{
10639			inputs: []inputInfo{
10640				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10641				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10642			},
10643		},
10644	},
10645	{
10646		name:         "ANDLconstmodifyidx8",
10647		auxType:      auxSymValAndOff,
10648		argLen:       3,
10649		clobberFlags: true,
10650		symEffect:    SymRead | SymWrite,
10651		asm:          x86.AANDL,
10652		scale:        8,
10653		reg: regInfo{
10654			inputs: []inputInfo{
10655				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10656				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10657			},
10658		},
10659	},
10660	{
10661		name:         "ORLconstmodifyidx1",
10662		auxType:      auxSymValAndOff,
10663		argLen:       3,
10664		clobberFlags: true,
10665		symEffect:    SymRead | SymWrite,
10666		asm:          x86.AORL,
10667		scale:        1,
10668		reg: regInfo{
10669			inputs: []inputInfo{
10670				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10671				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10672			},
10673		},
10674	},
10675	{
10676		name:         "ORLconstmodifyidx4",
10677		auxType:      auxSymValAndOff,
10678		argLen:       3,
10679		clobberFlags: true,
10680		symEffect:    SymRead | SymWrite,
10681		asm:          x86.AORL,
10682		scale:        4,
10683		reg: regInfo{
10684			inputs: []inputInfo{
10685				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10686				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10687			},
10688		},
10689	},
10690	{
10691		name:         "ORLconstmodifyidx8",
10692		auxType:      auxSymValAndOff,
10693		argLen:       3,
10694		clobberFlags: true,
10695		symEffect:    SymRead | SymWrite,
10696		asm:          x86.AORL,
10697		scale:        8,
10698		reg: regInfo{
10699			inputs: []inputInfo{
10700				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10701				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10702			},
10703		},
10704	},
10705	{
10706		name:         "XORLconstmodifyidx1",
10707		auxType:      auxSymValAndOff,
10708		argLen:       3,
10709		clobberFlags: true,
10710		symEffect:    SymRead | SymWrite,
10711		asm:          x86.AXORL,
10712		scale:        1,
10713		reg: regInfo{
10714			inputs: []inputInfo{
10715				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10716				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10717			},
10718		},
10719	},
10720	{
10721		name:         "XORLconstmodifyidx4",
10722		auxType:      auxSymValAndOff,
10723		argLen:       3,
10724		clobberFlags: true,
10725		symEffect:    SymRead | SymWrite,
10726		asm:          x86.AXORL,
10727		scale:        4,
10728		reg: regInfo{
10729			inputs: []inputInfo{
10730				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10731				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10732			},
10733		},
10734	},
10735	{
10736		name:         "XORLconstmodifyidx8",
10737		auxType:      auxSymValAndOff,
10738		argLen:       3,
10739		clobberFlags: true,
10740		symEffect:    SymRead | SymWrite,
10741		asm:          x86.AXORL,
10742		scale:        8,
10743		reg: regInfo{
10744			inputs: []inputInfo{
10745				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
10746				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
10747			},
10748		},
10749	},
10750	{
10751		name:         "NEGQ",
10752		argLen:       1,
10753		resultInArg0: true,
10754		clobberFlags: true,
10755		asm:          x86.ANEGQ,
10756		reg: regInfo{
10757			inputs: []inputInfo{
10758				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10759			},
10760			outputs: []outputInfo{
10761				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10762			},
10763		},
10764	},
10765	{
10766		name:         "NEGL",
10767		argLen:       1,
10768		resultInArg0: true,
10769		clobberFlags: true,
10770		asm:          x86.ANEGL,
10771		reg: regInfo{
10772			inputs: []inputInfo{
10773				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10774			},
10775			outputs: []outputInfo{
10776				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10777			},
10778		},
10779	},
10780	{
10781		name:         "NOTQ",
10782		argLen:       1,
10783		resultInArg0: true,
10784		asm:          x86.ANOTQ,
10785		reg: regInfo{
10786			inputs: []inputInfo{
10787				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10788			},
10789			outputs: []outputInfo{
10790				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10791			},
10792		},
10793	},
10794	{
10795		name:         "NOTL",
10796		argLen:       1,
10797		resultInArg0: true,
10798		asm:          x86.ANOTL,
10799		reg: regInfo{
10800			inputs: []inputInfo{
10801				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10802			},
10803			outputs: []outputInfo{
10804				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10805			},
10806		},
10807	},
10808	{
10809		name:   "BSFQ",
10810		argLen: 1,
10811		asm:    x86.ABSFQ,
10812		reg: regInfo{
10813			inputs: []inputInfo{
10814				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10815			},
10816			outputs: []outputInfo{
10817				{1, 0},
10818				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10819			},
10820		},
10821	},
10822	{
10823		name:         "BSFL",
10824		argLen:       1,
10825		clobberFlags: true,
10826		asm:          x86.ABSFL,
10827		reg: regInfo{
10828			inputs: []inputInfo{
10829				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10830			},
10831			outputs: []outputInfo{
10832				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10833			},
10834		},
10835	},
10836	{
10837		name:   "BSRQ",
10838		argLen: 1,
10839		asm:    x86.ABSRQ,
10840		reg: regInfo{
10841			inputs: []inputInfo{
10842				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10843			},
10844			outputs: []outputInfo{
10845				{1, 0},
10846				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10847			},
10848		},
10849	},
10850	{
10851		name:         "BSRL",
10852		argLen:       1,
10853		clobberFlags: true,
10854		asm:          x86.ABSRL,
10855		reg: regInfo{
10856			inputs: []inputInfo{
10857				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10858			},
10859			outputs: []outputInfo{
10860				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10861			},
10862		},
10863	},
10864	{
10865		name:         "CMOVQEQ",
10866		argLen:       3,
10867		resultInArg0: true,
10868		asm:          x86.ACMOVQEQ,
10869		reg: regInfo{
10870			inputs: []inputInfo{
10871				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10872				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10873			},
10874			outputs: []outputInfo{
10875				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10876			},
10877		},
10878	},
10879	{
10880		name:         "CMOVQNE",
10881		argLen:       3,
10882		resultInArg0: true,
10883		asm:          x86.ACMOVQNE,
10884		reg: regInfo{
10885			inputs: []inputInfo{
10886				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10887				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10888			},
10889			outputs: []outputInfo{
10890				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10891			},
10892		},
10893	},
10894	{
10895		name:         "CMOVQLT",
10896		argLen:       3,
10897		resultInArg0: true,
10898		asm:          x86.ACMOVQLT,
10899		reg: regInfo{
10900			inputs: []inputInfo{
10901				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10902				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10903			},
10904			outputs: []outputInfo{
10905				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10906			},
10907		},
10908	},
10909	{
10910		name:         "CMOVQGT",
10911		argLen:       3,
10912		resultInArg0: true,
10913		asm:          x86.ACMOVQGT,
10914		reg: regInfo{
10915			inputs: []inputInfo{
10916				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10917				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10918			},
10919			outputs: []outputInfo{
10920				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10921			},
10922		},
10923	},
10924	{
10925		name:         "CMOVQLE",
10926		argLen:       3,
10927		resultInArg0: true,
10928		asm:          x86.ACMOVQLE,
10929		reg: regInfo{
10930			inputs: []inputInfo{
10931				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10932				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10933			},
10934			outputs: []outputInfo{
10935				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10936			},
10937		},
10938	},
10939	{
10940		name:         "CMOVQGE",
10941		argLen:       3,
10942		resultInArg0: true,
10943		asm:          x86.ACMOVQGE,
10944		reg: regInfo{
10945			inputs: []inputInfo{
10946				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10947				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10948			},
10949			outputs: []outputInfo{
10950				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10951			},
10952		},
10953	},
10954	{
10955		name:         "CMOVQLS",
10956		argLen:       3,
10957		resultInArg0: true,
10958		asm:          x86.ACMOVQLS,
10959		reg: regInfo{
10960			inputs: []inputInfo{
10961				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10962				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10963			},
10964			outputs: []outputInfo{
10965				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10966			},
10967		},
10968	},
10969	{
10970		name:         "CMOVQHI",
10971		argLen:       3,
10972		resultInArg0: true,
10973		asm:          x86.ACMOVQHI,
10974		reg: regInfo{
10975			inputs: []inputInfo{
10976				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10977				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10978			},
10979			outputs: []outputInfo{
10980				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10981			},
10982		},
10983	},
10984	{
10985		name:         "CMOVQCC",
10986		argLen:       3,
10987		resultInArg0: true,
10988		asm:          x86.ACMOVQCC,
10989		reg: regInfo{
10990			inputs: []inputInfo{
10991				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10992				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10993			},
10994			outputs: []outputInfo{
10995				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
10996			},
10997		},
10998	},
10999	{
11000		name:         "CMOVQCS",
11001		argLen:       3,
11002		resultInArg0: true,
11003		asm:          x86.ACMOVQCS,
11004		reg: regInfo{
11005			inputs: []inputInfo{
11006				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11007				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11008			},
11009			outputs: []outputInfo{
11010				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11011			},
11012		},
11013	},
11014	{
11015		name:         "CMOVLEQ",
11016		argLen:       3,
11017		resultInArg0: true,
11018		asm:          x86.ACMOVLEQ,
11019		reg: regInfo{
11020			inputs: []inputInfo{
11021				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11022				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11023			},
11024			outputs: []outputInfo{
11025				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11026			},
11027		},
11028	},
11029	{
11030		name:         "CMOVLNE",
11031		argLen:       3,
11032		resultInArg0: true,
11033		asm:          x86.ACMOVLNE,
11034		reg: regInfo{
11035			inputs: []inputInfo{
11036				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11037				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11038			},
11039			outputs: []outputInfo{
11040				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11041			},
11042		},
11043	},
11044	{
11045		name:         "CMOVLLT",
11046		argLen:       3,
11047		resultInArg0: true,
11048		asm:          x86.ACMOVLLT,
11049		reg: regInfo{
11050			inputs: []inputInfo{
11051				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11052				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11053			},
11054			outputs: []outputInfo{
11055				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11056			},
11057		},
11058	},
11059	{
11060		name:         "CMOVLGT",
11061		argLen:       3,
11062		resultInArg0: true,
11063		asm:          x86.ACMOVLGT,
11064		reg: regInfo{
11065			inputs: []inputInfo{
11066				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11067				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11068			},
11069			outputs: []outputInfo{
11070				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11071			},
11072		},
11073	},
11074	{
11075		name:         "CMOVLLE",
11076		argLen:       3,
11077		resultInArg0: true,
11078		asm:          x86.ACMOVLLE,
11079		reg: regInfo{
11080			inputs: []inputInfo{
11081				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11082				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11083			},
11084			outputs: []outputInfo{
11085				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11086			},
11087		},
11088	},
11089	{
11090		name:         "CMOVLGE",
11091		argLen:       3,
11092		resultInArg0: true,
11093		asm:          x86.ACMOVLGE,
11094		reg: regInfo{
11095			inputs: []inputInfo{
11096				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11097				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11098			},
11099			outputs: []outputInfo{
11100				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11101			},
11102		},
11103	},
11104	{
11105		name:         "CMOVLLS",
11106		argLen:       3,
11107		resultInArg0: true,
11108		asm:          x86.ACMOVLLS,
11109		reg: regInfo{
11110			inputs: []inputInfo{
11111				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11112				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11113			},
11114			outputs: []outputInfo{
11115				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11116			},
11117		},
11118	},
11119	{
11120		name:         "CMOVLHI",
11121		argLen:       3,
11122		resultInArg0: true,
11123		asm:          x86.ACMOVLHI,
11124		reg: regInfo{
11125			inputs: []inputInfo{
11126				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11127				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11128			},
11129			outputs: []outputInfo{
11130				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11131			},
11132		},
11133	},
11134	{
11135		name:         "CMOVLCC",
11136		argLen:       3,
11137		resultInArg0: true,
11138		asm:          x86.ACMOVLCC,
11139		reg: regInfo{
11140			inputs: []inputInfo{
11141				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11142				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11143			},
11144			outputs: []outputInfo{
11145				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11146			},
11147		},
11148	},
11149	{
11150		name:         "CMOVLCS",
11151		argLen:       3,
11152		resultInArg0: true,
11153		asm:          x86.ACMOVLCS,
11154		reg: regInfo{
11155			inputs: []inputInfo{
11156				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11157				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11158			},
11159			outputs: []outputInfo{
11160				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11161			},
11162		},
11163	},
11164	{
11165		name:         "CMOVWEQ",
11166		argLen:       3,
11167		resultInArg0: true,
11168		asm:          x86.ACMOVWEQ,
11169		reg: regInfo{
11170			inputs: []inputInfo{
11171				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11172				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11173			},
11174			outputs: []outputInfo{
11175				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11176			},
11177		},
11178	},
11179	{
11180		name:         "CMOVWNE",
11181		argLen:       3,
11182		resultInArg0: true,
11183		asm:          x86.ACMOVWNE,
11184		reg: regInfo{
11185			inputs: []inputInfo{
11186				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11187				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11188			},
11189			outputs: []outputInfo{
11190				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11191			},
11192		},
11193	},
11194	{
11195		name:         "CMOVWLT",
11196		argLen:       3,
11197		resultInArg0: true,
11198		asm:          x86.ACMOVWLT,
11199		reg: regInfo{
11200			inputs: []inputInfo{
11201				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11202				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11203			},
11204			outputs: []outputInfo{
11205				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11206			},
11207		},
11208	},
11209	{
11210		name:         "CMOVWGT",
11211		argLen:       3,
11212		resultInArg0: true,
11213		asm:          x86.ACMOVWGT,
11214		reg: regInfo{
11215			inputs: []inputInfo{
11216				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11217				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11218			},
11219			outputs: []outputInfo{
11220				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11221			},
11222		},
11223	},
11224	{
11225		name:         "CMOVWLE",
11226		argLen:       3,
11227		resultInArg0: true,
11228		asm:          x86.ACMOVWLE,
11229		reg: regInfo{
11230			inputs: []inputInfo{
11231				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11232				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11233			},
11234			outputs: []outputInfo{
11235				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11236			},
11237		},
11238	},
11239	{
11240		name:         "CMOVWGE",
11241		argLen:       3,
11242		resultInArg0: true,
11243		asm:          x86.ACMOVWGE,
11244		reg: regInfo{
11245			inputs: []inputInfo{
11246				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11247				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11248			},
11249			outputs: []outputInfo{
11250				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11251			},
11252		},
11253	},
11254	{
11255		name:         "CMOVWLS",
11256		argLen:       3,
11257		resultInArg0: true,
11258		asm:          x86.ACMOVWLS,
11259		reg: regInfo{
11260			inputs: []inputInfo{
11261				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11262				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11263			},
11264			outputs: []outputInfo{
11265				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11266			},
11267		},
11268	},
11269	{
11270		name:         "CMOVWHI",
11271		argLen:       3,
11272		resultInArg0: true,
11273		asm:          x86.ACMOVWHI,
11274		reg: regInfo{
11275			inputs: []inputInfo{
11276				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11277				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11278			},
11279			outputs: []outputInfo{
11280				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11281			},
11282		},
11283	},
11284	{
11285		name:         "CMOVWCC",
11286		argLen:       3,
11287		resultInArg0: true,
11288		asm:          x86.ACMOVWCC,
11289		reg: regInfo{
11290			inputs: []inputInfo{
11291				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11292				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11293			},
11294			outputs: []outputInfo{
11295				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11296			},
11297		},
11298	},
11299	{
11300		name:         "CMOVWCS",
11301		argLen:       3,
11302		resultInArg0: true,
11303		asm:          x86.ACMOVWCS,
11304		reg: regInfo{
11305			inputs: []inputInfo{
11306				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11307				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11308			},
11309			outputs: []outputInfo{
11310				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11311			},
11312		},
11313	},
11314	{
11315		name:         "CMOVQEQF",
11316		argLen:       3,
11317		resultInArg0: true,
11318		asm:          x86.ACMOVQNE,
11319		reg: regInfo{
11320			inputs: []inputInfo{
11321				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11322				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11323			},
11324			clobbers: 1, // AX
11325			outputs: []outputInfo{
11326				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11327			},
11328		},
11329	},
11330	{
11331		name:         "CMOVQNEF",
11332		argLen:       3,
11333		resultInArg0: true,
11334		asm:          x86.ACMOVQNE,
11335		reg: regInfo{
11336			inputs: []inputInfo{
11337				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11338				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11339			},
11340			outputs: []outputInfo{
11341				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11342			},
11343		},
11344	},
11345	{
11346		name:         "CMOVQGTF",
11347		argLen:       3,
11348		resultInArg0: true,
11349		asm:          x86.ACMOVQHI,
11350		reg: regInfo{
11351			inputs: []inputInfo{
11352				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11353				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11354			},
11355			outputs: []outputInfo{
11356				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11357			},
11358		},
11359	},
11360	{
11361		name:         "CMOVQGEF",
11362		argLen:       3,
11363		resultInArg0: true,
11364		asm:          x86.ACMOVQCC,
11365		reg: regInfo{
11366			inputs: []inputInfo{
11367				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11368				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11369			},
11370			outputs: []outputInfo{
11371				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11372			},
11373		},
11374	},
11375	{
11376		name:         "CMOVLEQF",
11377		argLen:       3,
11378		resultInArg0: true,
11379		asm:          x86.ACMOVLNE,
11380		reg: regInfo{
11381			inputs: []inputInfo{
11382				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11383				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11384			},
11385			clobbers: 1, // AX
11386			outputs: []outputInfo{
11387				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11388			},
11389		},
11390	},
11391	{
11392		name:         "CMOVLNEF",
11393		argLen:       3,
11394		resultInArg0: true,
11395		asm:          x86.ACMOVLNE,
11396		reg: regInfo{
11397			inputs: []inputInfo{
11398				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11399				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11400			},
11401			outputs: []outputInfo{
11402				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11403			},
11404		},
11405	},
11406	{
11407		name:         "CMOVLGTF",
11408		argLen:       3,
11409		resultInArg0: true,
11410		asm:          x86.ACMOVLHI,
11411		reg: regInfo{
11412			inputs: []inputInfo{
11413				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11414				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11415			},
11416			outputs: []outputInfo{
11417				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11418			},
11419		},
11420	},
11421	{
11422		name:         "CMOVLGEF",
11423		argLen:       3,
11424		resultInArg0: true,
11425		asm:          x86.ACMOVLCC,
11426		reg: regInfo{
11427			inputs: []inputInfo{
11428				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11429				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11430			},
11431			outputs: []outputInfo{
11432				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11433			},
11434		},
11435	},
11436	{
11437		name:         "CMOVWEQF",
11438		argLen:       3,
11439		resultInArg0: true,
11440		asm:          x86.ACMOVWNE,
11441		reg: regInfo{
11442			inputs: []inputInfo{
11443				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11444				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11445			},
11446			clobbers: 1, // AX
11447			outputs: []outputInfo{
11448				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11449			},
11450		},
11451	},
11452	{
11453		name:         "CMOVWNEF",
11454		argLen:       3,
11455		resultInArg0: true,
11456		asm:          x86.ACMOVWNE,
11457		reg: regInfo{
11458			inputs: []inputInfo{
11459				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11460				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11461			},
11462			outputs: []outputInfo{
11463				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11464			},
11465		},
11466	},
11467	{
11468		name:         "CMOVWGTF",
11469		argLen:       3,
11470		resultInArg0: true,
11471		asm:          x86.ACMOVWHI,
11472		reg: regInfo{
11473			inputs: []inputInfo{
11474				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11475				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11476			},
11477			outputs: []outputInfo{
11478				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11479			},
11480		},
11481	},
11482	{
11483		name:         "CMOVWGEF",
11484		argLen:       3,
11485		resultInArg0: true,
11486		asm:          x86.ACMOVWCC,
11487		reg: regInfo{
11488			inputs: []inputInfo{
11489				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11490				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11491			},
11492			outputs: []outputInfo{
11493				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11494			},
11495		},
11496	},
11497	{
11498		name:         "BSWAPQ",
11499		argLen:       1,
11500		resultInArg0: true,
11501		clobberFlags: true,
11502		asm:          x86.ABSWAPQ,
11503		reg: regInfo{
11504			inputs: []inputInfo{
11505				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11506			},
11507			outputs: []outputInfo{
11508				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11509			},
11510		},
11511	},
11512	{
11513		name:         "BSWAPL",
11514		argLen:       1,
11515		resultInArg0: true,
11516		clobberFlags: true,
11517		asm:          x86.ABSWAPL,
11518		reg: regInfo{
11519			inputs: []inputInfo{
11520				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11521			},
11522			outputs: []outputInfo{
11523				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11524			},
11525		},
11526	},
11527	{
11528		name:         "POPCNTQ",
11529		argLen:       1,
11530		clobberFlags: true,
11531		asm:          x86.APOPCNTQ,
11532		reg: regInfo{
11533			inputs: []inputInfo{
11534				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11535			},
11536			outputs: []outputInfo{
11537				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11538			},
11539		},
11540	},
11541	{
11542		name:         "POPCNTL",
11543		argLen:       1,
11544		clobberFlags: true,
11545		asm:          x86.APOPCNTL,
11546		reg: regInfo{
11547			inputs: []inputInfo{
11548				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11549			},
11550			outputs: []outputInfo{
11551				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11552			},
11553		},
11554	},
11555	{
11556		name:   "SQRTSD",
11557		argLen: 1,
11558		asm:    x86.ASQRTSD,
11559		reg: regInfo{
11560			inputs: []inputInfo{
11561				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11562			},
11563			outputs: []outputInfo{
11564				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11565			},
11566		},
11567	},
11568	{
11569		name:   "SQRTSS",
11570		argLen: 1,
11571		asm:    x86.ASQRTSS,
11572		reg: regInfo{
11573			inputs: []inputInfo{
11574				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11575			},
11576			outputs: []outputInfo{
11577				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11578			},
11579		},
11580	},
11581	{
11582		name:    "ROUNDSD",
11583		auxType: auxInt8,
11584		argLen:  1,
11585		asm:     x86.AROUNDSD,
11586		reg: regInfo{
11587			inputs: []inputInfo{
11588				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11589			},
11590			outputs: []outputInfo{
11591				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11592			},
11593		},
11594	},
11595	{
11596		name:         "VFMADD231SD",
11597		argLen:       3,
11598		resultInArg0: true,
11599		asm:          x86.AVFMADD231SD,
11600		reg: regInfo{
11601			inputs: []inputInfo{
11602				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11603				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11604				{2, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11605			},
11606			outputs: []outputInfo{
11607				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
11608			},
11609		},
11610	},
11611	{
11612		name:   "SBBQcarrymask",
11613		argLen: 1,
11614		asm:    x86.ASBBQ,
11615		reg: regInfo{
11616			outputs: []outputInfo{
11617				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11618			},
11619		},
11620	},
11621	{
11622		name:   "SBBLcarrymask",
11623		argLen: 1,
11624		asm:    x86.ASBBL,
11625		reg: regInfo{
11626			outputs: []outputInfo{
11627				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11628			},
11629		},
11630	},
11631	{
11632		name:   "SETEQ",
11633		argLen: 1,
11634		asm:    x86.ASETEQ,
11635		reg: regInfo{
11636			outputs: []outputInfo{
11637				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11638			},
11639		},
11640	},
11641	{
11642		name:   "SETNE",
11643		argLen: 1,
11644		asm:    x86.ASETNE,
11645		reg: regInfo{
11646			outputs: []outputInfo{
11647				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11648			},
11649		},
11650	},
11651	{
11652		name:   "SETL",
11653		argLen: 1,
11654		asm:    x86.ASETLT,
11655		reg: regInfo{
11656			outputs: []outputInfo{
11657				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11658			},
11659		},
11660	},
11661	{
11662		name:   "SETLE",
11663		argLen: 1,
11664		asm:    x86.ASETLE,
11665		reg: regInfo{
11666			outputs: []outputInfo{
11667				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11668			},
11669		},
11670	},
11671	{
11672		name:   "SETG",
11673		argLen: 1,
11674		asm:    x86.ASETGT,
11675		reg: regInfo{
11676			outputs: []outputInfo{
11677				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11678			},
11679		},
11680	},
11681	{
11682		name:   "SETGE",
11683		argLen: 1,
11684		asm:    x86.ASETGE,
11685		reg: regInfo{
11686			outputs: []outputInfo{
11687				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11688			},
11689		},
11690	},
11691	{
11692		name:   "SETB",
11693		argLen: 1,
11694		asm:    x86.ASETCS,
11695		reg: regInfo{
11696			outputs: []outputInfo{
11697				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11698			},
11699		},
11700	},
11701	{
11702		name:   "SETBE",
11703		argLen: 1,
11704		asm:    x86.ASETLS,
11705		reg: regInfo{
11706			outputs: []outputInfo{
11707				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11708			},
11709		},
11710	},
11711	{
11712		name:   "SETA",
11713		argLen: 1,
11714		asm:    x86.ASETHI,
11715		reg: regInfo{
11716			outputs: []outputInfo{
11717				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11718			},
11719		},
11720	},
11721	{
11722		name:   "SETAE",
11723		argLen: 1,
11724		asm:    x86.ASETCC,
11725		reg: regInfo{
11726			outputs: []outputInfo{
11727				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11728			},
11729		},
11730	},
11731	{
11732		name:   "SETO",
11733		argLen: 1,
11734		asm:    x86.ASETOS,
11735		reg: regInfo{
11736			outputs: []outputInfo{
11737				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11738			},
11739		},
11740	},
11741	{
11742		name:           "SETEQstore",
11743		auxType:        auxSymOff,
11744		argLen:         3,
11745		faultOnNilArg0: true,
11746		symEffect:      SymWrite,
11747		asm:            x86.ASETEQ,
11748		reg: regInfo{
11749			inputs: []inputInfo{
11750				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11751			},
11752		},
11753	},
11754	{
11755		name:           "SETNEstore",
11756		auxType:        auxSymOff,
11757		argLen:         3,
11758		faultOnNilArg0: true,
11759		symEffect:      SymWrite,
11760		asm:            x86.ASETNE,
11761		reg: regInfo{
11762			inputs: []inputInfo{
11763				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11764			},
11765		},
11766	},
11767	{
11768		name:           "SETLstore",
11769		auxType:        auxSymOff,
11770		argLen:         3,
11771		faultOnNilArg0: true,
11772		symEffect:      SymWrite,
11773		asm:            x86.ASETLT,
11774		reg: regInfo{
11775			inputs: []inputInfo{
11776				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11777			},
11778		},
11779	},
11780	{
11781		name:           "SETLEstore",
11782		auxType:        auxSymOff,
11783		argLen:         3,
11784		faultOnNilArg0: true,
11785		symEffect:      SymWrite,
11786		asm:            x86.ASETLE,
11787		reg: regInfo{
11788			inputs: []inputInfo{
11789				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11790			},
11791		},
11792	},
11793	{
11794		name:           "SETGstore",
11795		auxType:        auxSymOff,
11796		argLen:         3,
11797		faultOnNilArg0: true,
11798		symEffect:      SymWrite,
11799		asm:            x86.ASETGT,
11800		reg: regInfo{
11801			inputs: []inputInfo{
11802				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11803			},
11804		},
11805	},
11806	{
11807		name:           "SETGEstore",
11808		auxType:        auxSymOff,
11809		argLen:         3,
11810		faultOnNilArg0: true,
11811		symEffect:      SymWrite,
11812		asm:            x86.ASETGE,
11813		reg: regInfo{
11814			inputs: []inputInfo{
11815				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11816			},
11817		},
11818	},
11819	{
11820		name:           "SETBstore",
11821		auxType:        auxSymOff,
11822		argLen:         3,
11823		faultOnNilArg0: true,
11824		symEffect:      SymWrite,
11825		asm:            x86.ASETCS,
11826		reg: regInfo{
11827			inputs: []inputInfo{
11828				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11829			},
11830		},
11831	},
11832	{
11833		name:           "SETBEstore",
11834		auxType:        auxSymOff,
11835		argLen:         3,
11836		faultOnNilArg0: true,
11837		symEffect:      SymWrite,
11838		asm:            x86.ASETLS,
11839		reg: regInfo{
11840			inputs: []inputInfo{
11841				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11842			},
11843		},
11844	},
11845	{
11846		name:           "SETAstore",
11847		auxType:        auxSymOff,
11848		argLen:         3,
11849		faultOnNilArg0: true,
11850		symEffect:      SymWrite,
11851		asm:            x86.ASETHI,
11852		reg: regInfo{
11853			inputs: []inputInfo{
11854				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11855			},
11856		},
11857	},
11858	{
11859		name:           "SETAEstore",
11860		auxType:        auxSymOff,
11861		argLen:         3,
11862		faultOnNilArg0: true,
11863		symEffect:      SymWrite,
11864		asm:            x86.ASETCC,
11865		reg: regInfo{
11866			inputs: []inputInfo{
11867				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
11868			},
11869		},
11870	},
11871	{
11872		name:         "SETEQF",
11873		argLen:       1,
11874		clobberFlags: true,
11875		asm:          x86.ASETEQ,
11876		reg: regInfo{
11877			clobbers: 1, // AX
11878			outputs: []outputInfo{
11879				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11880			},
11881		},
11882	},
11883	{
11884		name:         "SETNEF",
11885		argLen:       1,
11886		clobberFlags: true,
11887		asm:          x86.ASETNE,
11888		reg: regInfo{
11889			clobbers: 1, // AX
11890			outputs: []outputInfo{
11891				{0, 49134}, // CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11892			},
11893		},
11894	},
11895	{
11896		name:   "SETORD",
11897		argLen: 1,
11898		asm:    x86.ASETPC,
11899		reg: regInfo{
11900			outputs: []outputInfo{
11901				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11902			},
11903		},
11904	},
11905	{
11906		name:   "SETNAN",
11907		argLen: 1,
11908		asm:    x86.ASETPS,
11909		reg: regInfo{
11910			outputs: []outputInfo{
11911				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11912			},
11913		},
11914	},
11915	{
11916		name:   "SETGF",
11917		argLen: 1,
11918		asm:    x86.ASETHI,
11919		reg: regInfo{
11920			outputs: []outputInfo{
11921				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11922			},
11923		},
11924	},
11925	{
11926		name:   "SETGEF",
11927		argLen: 1,
11928		asm:    x86.ASETCC,
11929		reg: regInfo{
11930			outputs: []outputInfo{
11931				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11932			},
11933		},
11934	},
11935	{
11936		name:   "MOVBQSX",
11937		argLen: 1,
11938		asm:    x86.AMOVBQSX,
11939		reg: regInfo{
11940			inputs: []inputInfo{
11941				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11942			},
11943			outputs: []outputInfo{
11944				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11945			},
11946		},
11947	},
11948	{
11949		name:   "MOVBQZX",
11950		argLen: 1,
11951		asm:    x86.AMOVBLZX,
11952		reg: regInfo{
11953			inputs: []inputInfo{
11954				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11955			},
11956			outputs: []outputInfo{
11957				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11958			},
11959		},
11960	},
11961	{
11962		name:   "MOVWQSX",
11963		argLen: 1,
11964		asm:    x86.AMOVWQSX,
11965		reg: regInfo{
11966			inputs: []inputInfo{
11967				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11968			},
11969			outputs: []outputInfo{
11970				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11971			},
11972		},
11973	},
11974	{
11975		name:   "MOVWQZX",
11976		argLen: 1,
11977		asm:    x86.AMOVWLZX,
11978		reg: regInfo{
11979			inputs: []inputInfo{
11980				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11981			},
11982			outputs: []outputInfo{
11983				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11984			},
11985		},
11986	},
11987	{
11988		name:   "MOVLQSX",
11989		argLen: 1,
11990		asm:    x86.AMOVLQSX,
11991		reg: regInfo{
11992			inputs: []inputInfo{
11993				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11994			},
11995			outputs: []outputInfo{
11996				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
11997			},
11998		},
11999	},
12000	{
12001		name:   "MOVLQZX",
12002		argLen: 1,
12003		asm:    x86.AMOVL,
12004		reg: regInfo{
12005			inputs: []inputInfo{
12006				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12007			},
12008			outputs: []outputInfo{
12009				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12010			},
12011		},
12012	},
12013	{
12014		name:              "MOVLconst",
12015		auxType:           auxInt32,
12016		argLen:            0,
12017		rematerializeable: true,
12018		asm:               x86.AMOVL,
12019		reg: regInfo{
12020			outputs: []outputInfo{
12021				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12022			},
12023		},
12024	},
12025	{
12026		name:              "MOVQconst",
12027		auxType:           auxInt64,
12028		argLen:            0,
12029		rematerializeable: true,
12030		asm:               x86.AMOVQ,
12031		reg: regInfo{
12032			outputs: []outputInfo{
12033				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12034			},
12035		},
12036	},
12037	{
12038		name:   "CVTTSD2SL",
12039		argLen: 1,
12040		asm:    x86.ACVTTSD2SL,
12041		reg: regInfo{
12042			inputs: []inputInfo{
12043				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12044			},
12045			outputs: []outputInfo{
12046				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12047			},
12048		},
12049	},
12050	{
12051		name:   "CVTTSD2SQ",
12052		argLen: 1,
12053		asm:    x86.ACVTTSD2SQ,
12054		reg: regInfo{
12055			inputs: []inputInfo{
12056				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12057			},
12058			outputs: []outputInfo{
12059				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12060			},
12061		},
12062	},
12063	{
12064		name:   "CVTTSS2SL",
12065		argLen: 1,
12066		asm:    x86.ACVTTSS2SL,
12067		reg: regInfo{
12068			inputs: []inputInfo{
12069				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12070			},
12071			outputs: []outputInfo{
12072				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12073			},
12074		},
12075	},
12076	{
12077		name:   "CVTTSS2SQ",
12078		argLen: 1,
12079		asm:    x86.ACVTTSS2SQ,
12080		reg: regInfo{
12081			inputs: []inputInfo{
12082				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12083			},
12084			outputs: []outputInfo{
12085				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12086			},
12087		},
12088	},
12089	{
12090		name:   "CVTSL2SS",
12091		argLen: 1,
12092		asm:    x86.ACVTSL2SS,
12093		reg: regInfo{
12094			inputs: []inputInfo{
12095				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12096			},
12097			outputs: []outputInfo{
12098				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12099			},
12100		},
12101	},
12102	{
12103		name:   "CVTSL2SD",
12104		argLen: 1,
12105		asm:    x86.ACVTSL2SD,
12106		reg: regInfo{
12107			inputs: []inputInfo{
12108				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12109			},
12110			outputs: []outputInfo{
12111				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12112			},
12113		},
12114	},
12115	{
12116		name:   "CVTSQ2SS",
12117		argLen: 1,
12118		asm:    x86.ACVTSQ2SS,
12119		reg: regInfo{
12120			inputs: []inputInfo{
12121				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12122			},
12123			outputs: []outputInfo{
12124				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12125			},
12126		},
12127	},
12128	{
12129		name:   "CVTSQ2SD",
12130		argLen: 1,
12131		asm:    x86.ACVTSQ2SD,
12132		reg: regInfo{
12133			inputs: []inputInfo{
12134				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12135			},
12136			outputs: []outputInfo{
12137				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12138			},
12139		},
12140	},
12141	{
12142		name:   "CVTSD2SS",
12143		argLen: 1,
12144		asm:    x86.ACVTSD2SS,
12145		reg: regInfo{
12146			inputs: []inputInfo{
12147				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12148			},
12149			outputs: []outputInfo{
12150				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12151			},
12152		},
12153	},
12154	{
12155		name:   "CVTSS2SD",
12156		argLen: 1,
12157		asm:    x86.ACVTSS2SD,
12158		reg: regInfo{
12159			inputs: []inputInfo{
12160				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12161			},
12162			outputs: []outputInfo{
12163				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12164			},
12165		},
12166	},
12167	{
12168		name:   "MOVQi2f",
12169		argLen: 1,
12170		reg: regInfo{
12171			inputs: []inputInfo{
12172				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12173			},
12174			outputs: []outputInfo{
12175				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12176			},
12177		},
12178	},
12179	{
12180		name:   "MOVQf2i",
12181		argLen: 1,
12182		reg: regInfo{
12183			inputs: []inputInfo{
12184				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12185			},
12186			outputs: []outputInfo{
12187				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12188			},
12189		},
12190	},
12191	{
12192		name:   "MOVLi2f",
12193		argLen: 1,
12194		reg: regInfo{
12195			inputs: []inputInfo{
12196				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12197			},
12198			outputs: []outputInfo{
12199				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12200			},
12201		},
12202	},
12203	{
12204		name:   "MOVLf2i",
12205		argLen: 1,
12206		reg: regInfo{
12207			inputs: []inputInfo{
12208				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12209			},
12210			outputs: []outputInfo{
12211				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12212			},
12213		},
12214	},
12215	{
12216		name:         "PXOR",
12217		argLen:       2,
12218		commutative:  true,
12219		resultInArg0: true,
12220		asm:          x86.APXOR,
12221		reg: regInfo{
12222			inputs: []inputInfo{
12223				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12224				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12225			},
12226			outputs: []outputInfo{
12227				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12228			},
12229		},
12230	},
12231	{
12232		name:              "LEAQ",
12233		auxType:           auxSymOff,
12234		argLen:            1,
12235		rematerializeable: true,
12236		symEffect:         SymAddr,
12237		asm:               x86.ALEAQ,
12238		reg: regInfo{
12239			inputs: []inputInfo{
12240				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12241			},
12242			outputs: []outputInfo{
12243				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12244			},
12245		},
12246	},
12247	{
12248		name:              "LEAL",
12249		auxType:           auxSymOff,
12250		argLen:            1,
12251		rematerializeable: true,
12252		symEffect:         SymAddr,
12253		asm:               x86.ALEAL,
12254		reg: regInfo{
12255			inputs: []inputInfo{
12256				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12257			},
12258			outputs: []outputInfo{
12259				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12260			},
12261		},
12262	},
12263	{
12264		name:              "LEAW",
12265		auxType:           auxSymOff,
12266		argLen:            1,
12267		rematerializeable: true,
12268		symEffect:         SymAddr,
12269		asm:               x86.ALEAW,
12270		reg: regInfo{
12271			inputs: []inputInfo{
12272				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12273			},
12274			outputs: []outputInfo{
12275				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12276			},
12277		},
12278	},
12279	{
12280		name:        "LEAQ1",
12281		auxType:     auxSymOff,
12282		argLen:      2,
12283		commutative: true,
12284		symEffect:   SymAddr,
12285		asm:         x86.ALEAQ,
12286		scale:       1,
12287		reg: regInfo{
12288			inputs: []inputInfo{
12289				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12290				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12291			},
12292			outputs: []outputInfo{
12293				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12294			},
12295		},
12296	},
12297	{
12298		name:        "LEAL1",
12299		auxType:     auxSymOff,
12300		argLen:      2,
12301		commutative: true,
12302		symEffect:   SymAddr,
12303		asm:         x86.ALEAL,
12304		scale:       1,
12305		reg: regInfo{
12306			inputs: []inputInfo{
12307				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12308				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12309			},
12310			outputs: []outputInfo{
12311				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12312			},
12313		},
12314	},
12315	{
12316		name:        "LEAW1",
12317		auxType:     auxSymOff,
12318		argLen:      2,
12319		commutative: true,
12320		symEffect:   SymAddr,
12321		asm:         x86.ALEAW,
12322		scale:       1,
12323		reg: regInfo{
12324			inputs: []inputInfo{
12325				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12326				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12327			},
12328			outputs: []outputInfo{
12329				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12330			},
12331		},
12332	},
12333	{
12334		name:      "LEAQ2",
12335		auxType:   auxSymOff,
12336		argLen:    2,
12337		symEffect: SymAddr,
12338		asm:       x86.ALEAQ,
12339		scale:     2,
12340		reg: regInfo{
12341			inputs: []inputInfo{
12342				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12343				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12344			},
12345			outputs: []outputInfo{
12346				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12347			},
12348		},
12349	},
12350	{
12351		name:      "LEAL2",
12352		auxType:   auxSymOff,
12353		argLen:    2,
12354		symEffect: SymAddr,
12355		asm:       x86.ALEAL,
12356		scale:     2,
12357		reg: regInfo{
12358			inputs: []inputInfo{
12359				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12360				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12361			},
12362			outputs: []outputInfo{
12363				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12364			},
12365		},
12366	},
12367	{
12368		name:      "LEAW2",
12369		auxType:   auxSymOff,
12370		argLen:    2,
12371		symEffect: SymAddr,
12372		asm:       x86.ALEAW,
12373		scale:     2,
12374		reg: regInfo{
12375			inputs: []inputInfo{
12376				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12377				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12378			},
12379			outputs: []outputInfo{
12380				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12381			},
12382		},
12383	},
12384	{
12385		name:      "LEAQ4",
12386		auxType:   auxSymOff,
12387		argLen:    2,
12388		symEffect: SymAddr,
12389		asm:       x86.ALEAQ,
12390		scale:     4,
12391		reg: regInfo{
12392			inputs: []inputInfo{
12393				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12394				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12395			},
12396			outputs: []outputInfo{
12397				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12398			},
12399		},
12400	},
12401	{
12402		name:      "LEAL4",
12403		auxType:   auxSymOff,
12404		argLen:    2,
12405		symEffect: SymAddr,
12406		asm:       x86.ALEAL,
12407		scale:     4,
12408		reg: regInfo{
12409			inputs: []inputInfo{
12410				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12411				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12412			},
12413			outputs: []outputInfo{
12414				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12415			},
12416		},
12417	},
12418	{
12419		name:      "LEAW4",
12420		auxType:   auxSymOff,
12421		argLen:    2,
12422		symEffect: SymAddr,
12423		asm:       x86.ALEAW,
12424		scale:     4,
12425		reg: regInfo{
12426			inputs: []inputInfo{
12427				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12428				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12429			},
12430			outputs: []outputInfo{
12431				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12432			},
12433		},
12434	},
12435	{
12436		name:      "LEAQ8",
12437		auxType:   auxSymOff,
12438		argLen:    2,
12439		symEffect: SymAddr,
12440		asm:       x86.ALEAQ,
12441		scale:     8,
12442		reg: regInfo{
12443			inputs: []inputInfo{
12444				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12445				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12446			},
12447			outputs: []outputInfo{
12448				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12449			},
12450		},
12451	},
12452	{
12453		name:      "LEAL8",
12454		auxType:   auxSymOff,
12455		argLen:    2,
12456		symEffect: SymAddr,
12457		asm:       x86.ALEAL,
12458		scale:     8,
12459		reg: regInfo{
12460			inputs: []inputInfo{
12461				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12462				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12463			},
12464			outputs: []outputInfo{
12465				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12466			},
12467		},
12468	},
12469	{
12470		name:      "LEAW8",
12471		auxType:   auxSymOff,
12472		argLen:    2,
12473		symEffect: SymAddr,
12474		asm:       x86.ALEAW,
12475		scale:     8,
12476		reg: regInfo{
12477			inputs: []inputInfo{
12478				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12479				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12480			},
12481			outputs: []outputInfo{
12482				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12483			},
12484		},
12485	},
12486	{
12487		name:           "MOVBload",
12488		auxType:        auxSymOff,
12489		argLen:         2,
12490		faultOnNilArg0: true,
12491		symEffect:      SymRead,
12492		asm:            x86.AMOVBLZX,
12493		reg: regInfo{
12494			inputs: []inputInfo{
12495				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12496			},
12497			outputs: []outputInfo{
12498				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12499			},
12500		},
12501	},
12502	{
12503		name:           "MOVBQSXload",
12504		auxType:        auxSymOff,
12505		argLen:         2,
12506		faultOnNilArg0: true,
12507		symEffect:      SymRead,
12508		asm:            x86.AMOVBQSX,
12509		reg: regInfo{
12510			inputs: []inputInfo{
12511				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12512			},
12513			outputs: []outputInfo{
12514				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12515			},
12516		},
12517	},
12518	{
12519		name:           "MOVWload",
12520		auxType:        auxSymOff,
12521		argLen:         2,
12522		faultOnNilArg0: true,
12523		symEffect:      SymRead,
12524		asm:            x86.AMOVWLZX,
12525		reg: regInfo{
12526			inputs: []inputInfo{
12527				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12528			},
12529			outputs: []outputInfo{
12530				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12531			},
12532		},
12533	},
12534	{
12535		name:           "MOVWQSXload",
12536		auxType:        auxSymOff,
12537		argLen:         2,
12538		faultOnNilArg0: true,
12539		symEffect:      SymRead,
12540		asm:            x86.AMOVWQSX,
12541		reg: regInfo{
12542			inputs: []inputInfo{
12543				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12544			},
12545			outputs: []outputInfo{
12546				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12547			},
12548		},
12549	},
12550	{
12551		name:           "MOVLload",
12552		auxType:        auxSymOff,
12553		argLen:         2,
12554		faultOnNilArg0: true,
12555		symEffect:      SymRead,
12556		asm:            x86.AMOVL,
12557		reg: regInfo{
12558			inputs: []inputInfo{
12559				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12560			},
12561			outputs: []outputInfo{
12562				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12563			},
12564		},
12565	},
12566	{
12567		name:           "MOVLQSXload",
12568		auxType:        auxSymOff,
12569		argLen:         2,
12570		faultOnNilArg0: true,
12571		symEffect:      SymRead,
12572		asm:            x86.AMOVLQSX,
12573		reg: regInfo{
12574			inputs: []inputInfo{
12575				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12576			},
12577			outputs: []outputInfo{
12578				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12579			},
12580		},
12581	},
12582	{
12583		name:           "MOVQload",
12584		auxType:        auxSymOff,
12585		argLen:         2,
12586		faultOnNilArg0: true,
12587		symEffect:      SymRead,
12588		asm:            x86.AMOVQ,
12589		reg: regInfo{
12590			inputs: []inputInfo{
12591				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12592			},
12593			outputs: []outputInfo{
12594				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12595			},
12596		},
12597	},
12598	{
12599		name:           "MOVBstore",
12600		auxType:        auxSymOff,
12601		argLen:         3,
12602		faultOnNilArg0: true,
12603		symEffect:      SymWrite,
12604		asm:            x86.AMOVB,
12605		reg: regInfo{
12606			inputs: []inputInfo{
12607				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12608				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12609			},
12610		},
12611	},
12612	{
12613		name:           "MOVWstore",
12614		auxType:        auxSymOff,
12615		argLen:         3,
12616		faultOnNilArg0: true,
12617		symEffect:      SymWrite,
12618		asm:            x86.AMOVW,
12619		reg: regInfo{
12620			inputs: []inputInfo{
12621				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12622				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12623			},
12624		},
12625	},
12626	{
12627		name:           "MOVLstore",
12628		auxType:        auxSymOff,
12629		argLen:         3,
12630		faultOnNilArg0: true,
12631		symEffect:      SymWrite,
12632		asm:            x86.AMOVL,
12633		reg: regInfo{
12634			inputs: []inputInfo{
12635				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12636				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12637			},
12638		},
12639	},
12640	{
12641		name:           "MOVQstore",
12642		auxType:        auxSymOff,
12643		argLen:         3,
12644		faultOnNilArg0: true,
12645		symEffect:      SymWrite,
12646		asm:            x86.AMOVQ,
12647		reg: regInfo{
12648			inputs: []inputInfo{
12649				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12650				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12651			},
12652		},
12653	},
12654	{
12655		name:           "MOVOload",
12656		auxType:        auxSymOff,
12657		argLen:         2,
12658		faultOnNilArg0: true,
12659		symEffect:      SymRead,
12660		asm:            x86.AMOVUPS,
12661		reg: regInfo{
12662			inputs: []inputInfo{
12663				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
12664			},
12665			outputs: []outputInfo{
12666				{0, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12667			},
12668		},
12669	},
12670	{
12671		name:           "MOVOstore",
12672		auxType:        auxSymOff,
12673		argLen:         3,
12674		faultOnNilArg0: true,
12675		symEffect:      SymWrite,
12676		asm:            x86.AMOVUPS,
12677		reg: regInfo{
12678			inputs: []inputInfo{
12679				{1, 2147418112}, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
12680				{0, 4295016447}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15 SB
12681			},
12682		},
12683	},
12684	{
12685		name:        "MOVBloadidx1",
12686		auxType:     auxSymOff,
12687		argLen:      3,
12688		commutative: true,
12689		symEffect:   SymRead,
12690		asm:         x86.AMOVBLZX,
12691		scale:       1,
12692		reg: regInfo{
12693			inputs: []inputInfo{
12694				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12695				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12696			},
12697			outputs: []outputInfo{
12698				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12699			},
12700		},
12701	},
12702	{
12703		name:        "MOVWloadidx1",
12704		auxType:     auxSymOff,
12705		argLen:      3,
12706		commutative: true,
12707		symEffect:   SymRead,
12708		asm:         x86.AMOVWLZX,
12709		scale:       1,
12710		reg: regInfo{
12711			inputs: []inputInfo{
12712				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12713				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12714			},
12715			outputs: []outputInfo{
12716				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12717			},
12718		},
12719	},
12720	{
12721		name:      "MOVWloadidx2",
12722		auxType:   auxSymOff,
12723		argLen:    3,
12724		symEffect: SymRead,
12725		asm:       x86.AMOVWLZX,
12726		scale:     2,
12727		reg: regInfo{
12728			inputs: []inputInfo{
12729				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12730				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12731			},
12732			outputs: []outputInfo{
12733				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12734			},
12735		},
12736	},
12737	{
12738		name:        "MOVLloadidx1",
12739		auxType:     auxSymOff,
12740		argLen:      3,
12741		commutative: true,
12742		symEffect:   SymRead,
12743		asm:         x86.AMOVL,
12744		scale:       1,
12745		reg: regInfo{
12746			inputs: []inputInfo{
12747				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12748				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12749			},
12750			outputs: []outputInfo{
12751				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12752			},
12753		},
12754	},
12755	{
12756		name:      "MOVLloadidx4",
12757		auxType:   auxSymOff,
12758		argLen:    3,
12759		symEffect: SymRead,
12760		asm:       x86.AMOVL,
12761		scale:     4,
12762		reg: regInfo{
12763			inputs: []inputInfo{
12764				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12765				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12766			},
12767			outputs: []outputInfo{
12768				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12769			},
12770		},
12771	},
12772	{
12773		name:      "MOVLloadidx8",
12774		auxType:   auxSymOff,
12775		argLen:    3,
12776		symEffect: SymRead,
12777		asm:       x86.AMOVL,
12778		scale:     8,
12779		reg: regInfo{
12780			inputs: []inputInfo{
12781				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12782				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12783			},
12784			outputs: []outputInfo{
12785				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12786			},
12787		},
12788	},
12789	{
12790		name:        "MOVQloadidx1",
12791		auxType:     auxSymOff,
12792		argLen:      3,
12793		commutative: true,
12794		symEffect:   SymRead,
12795		asm:         x86.AMOVQ,
12796		scale:       1,
12797		reg: regInfo{
12798			inputs: []inputInfo{
12799				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12800				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12801			},
12802			outputs: []outputInfo{
12803				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12804			},
12805		},
12806	},
12807	{
12808		name:      "MOVQloadidx8",
12809		auxType:   auxSymOff,
12810		argLen:    3,
12811		symEffect: SymRead,
12812		asm:       x86.AMOVQ,
12813		scale:     8,
12814		reg: regInfo{
12815			inputs: []inputInfo{
12816				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12817				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12818			},
12819			outputs: []outputInfo{
12820				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
12821			},
12822		},
12823	},
12824	{
12825		name:        "MOVBstoreidx1",
12826		auxType:     auxSymOff,
12827		argLen:      4,
12828		commutative: true,
12829		symEffect:   SymWrite,
12830		asm:         x86.AMOVB,
12831		scale:       1,
12832		reg: regInfo{
12833			inputs: []inputInfo{
12834				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12835				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12836				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12837			},
12838		},
12839	},
12840	{
12841		name:        "MOVWstoreidx1",
12842		auxType:     auxSymOff,
12843		argLen:      4,
12844		commutative: true,
12845		symEffect:   SymWrite,
12846		asm:         x86.AMOVW,
12847		scale:       1,
12848		reg: regInfo{
12849			inputs: []inputInfo{
12850				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12851				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12852				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12853			},
12854		},
12855	},
12856	{
12857		name:      "MOVWstoreidx2",
12858		auxType:   auxSymOff,
12859		argLen:    4,
12860		symEffect: SymWrite,
12861		asm:       x86.AMOVW,
12862		scale:     2,
12863		reg: regInfo{
12864			inputs: []inputInfo{
12865				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12866				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12867				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12868			},
12869		},
12870	},
12871	{
12872		name:        "MOVLstoreidx1",
12873		auxType:     auxSymOff,
12874		argLen:      4,
12875		commutative: true,
12876		symEffect:   SymWrite,
12877		asm:         x86.AMOVL,
12878		scale:       1,
12879		reg: regInfo{
12880			inputs: []inputInfo{
12881				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12882				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12883				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12884			},
12885		},
12886	},
12887	{
12888		name:      "MOVLstoreidx4",
12889		auxType:   auxSymOff,
12890		argLen:    4,
12891		symEffect: SymWrite,
12892		asm:       x86.AMOVL,
12893		scale:     4,
12894		reg: regInfo{
12895			inputs: []inputInfo{
12896				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12897				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12898				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12899			},
12900		},
12901	},
12902	{
12903		name:      "MOVLstoreidx8",
12904		auxType:   auxSymOff,
12905		argLen:    4,
12906		symEffect: SymWrite,
12907		asm:       x86.AMOVL,
12908		scale:     8,
12909		reg: regInfo{
12910			inputs: []inputInfo{
12911				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12912				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12913				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12914			},
12915		},
12916	},
12917	{
12918		name:        "MOVQstoreidx1",
12919		auxType:     auxSymOff,
12920		argLen:      4,
12921		commutative: true,
12922		symEffect:   SymWrite,
12923		asm:         x86.AMOVQ,
12924		scale:       1,
12925		reg: regInfo{
12926			inputs: []inputInfo{
12927				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12928				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12929				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12930			},
12931		},
12932	},
12933	{
12934		name:      "MOVQstoreidx8",
12935		auxType:   auxSymOff,
12936		argLen:    4,
12937		symEffect: SymWrite,
12938		asm:       x86.AMOVQ,
12939		scale:     8,
12940		reg: regInfo{
12941			inputs: []inputInfo{
12942				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12943				{2, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
12944				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12945			},
12946		},
12947	},
12948	{
12949		name:           "MOVBstoreconst",
12950		auxType:        auxSymValAndOff,
12951		argLen:         2,
12952		faultOnNilArg0: true,
12953		symEffect:      SymWrite,
12954		asm:            x86.AMOVB,
12955		reg: regInfo{
12956			inputs: []inputInfo{
12957				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12958			},
12959		},
12960	},
12961	{
12962		name:           "MOVWstoreconst",
12963		auxType:        auxSymValAndOff,
12964		argLen:         2,
12965		faultOnNilArg0: true,
12966		symEffect:      SymWrite,
12967		asm:            x86.AMOVW,
12968		reg: regInfo{
12969			inputs: []inputInfo{
12970				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12971			},
12972		},
12973	},
12974	{
12975		name:           "MOVLstoreconst",
12976		auxType:        auxSymValAndOff,
12977		argLen:         2,
12978		faultOnNilArg0: true,
12979		symEffect:      SymWrite,
12980		asm:            x86.AMOVL,
12981		reg: regInfo{
12982			inputs: []inputInfo{
12983				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12984			},
12985		},
12986	},
12987	{
12988		name:           "MOVQstoreconst",
12989		auxType:        auxSymValAndOff,
12990		argLen:         2,
12991		faultOnNilArg0: true,
12992		symEffect:      SymWrite,
12993		asm:            x86.AMOVQ,
12994		reg: regInfo{
12995			inputs: []inputInfo{
12996				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
12997			},
12998		},
12999	},
13000	{
13001		name:           "MOVOstoreconst",
13002		auxType:        auxSymValAndOff,
13003		argLen:         2,
13004		faultOnNilArg0: true,
13005		symEffect:      SymWrite,
13006		asm:            x86.AMOVUPS,
13007		reg: regInfo{
13008			inputs: []inputInfo{
13009				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13010			},
13011		},
13012	},
13013	{
13014		name:        "MOVBstoreconstidx1",
13015		auxType:     auxSymValAndOff,
13016		argLen:      3,
13017		commutative: true,
13018		symEffect:   SymWrite,
13019		asm:         x86.AMOVB,
13020		scale:       1,
13021		reg: regInfo{
13022			inputs: []inputInfo{
13023				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13024				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13025			},
13026		},
13027	},
13028	{
13029		name:        "MOVWstoreconstidx1",
13030		auxType:     auxSymValAndOff,
13031		argLen:      3,
13032		commutative: true,
13033		symEffect:   SymWrite,
13034		asm:         x86.AMOVW,
13035		scale:       1,
13036		reg: regInfo{
13037			inputs: []inputInfo{
13038				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13039				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13040			},
13041		},
13042	},
13043	{
13044		name:      "MOVWstoreconstidx2",
13045		auxType:   auxSymValAndOff,
13046		argLen:    3,
13047		symEffect: SymWrite,
13048		asm:       x86.AMOVW,
13049		scale:     2,
13050		reg: regInfo{
13051			inputs: []inputInfo{
13052				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13053				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13054			},
13055		},
13056	},
13057	{
13058		name:        "MOVLstoreconstidx1",
13059		auxType:     auxSymValAndOff,
13060		argLen:      3,
13061		commutative: true,
13062		symEffect:   SymWrite,
13063		asm:         x86.AMOVL,
13064		scale:       1,
13065		reg: regInfo{
13066			inputs: []inputInfo{
13067				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13068				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13069			},
13070		},
13071	},
13072	{
13073		name:      "MOVLstoreconstidx4",
13074		auxType:   auxSymValAndOff,
13075		argLen:    3,
13076		symEffect: SymWrite,
13077		asm:       x86.AMOVL,
13078		scale:     4,
13079		reg: regInfo{
13080			inputs: []inputInfo{
13081				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13082				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13083			},
13084		},
13085	},
13086	{
13087		name:        "MOVQstoreconstidx1",
13088		auxType:     auxSymValAndOff,
13089		argLen:      3,
13090		commutative: true,
13091		symEffect:   SymWrite,
13092		asm:         x86.AMOVQ,
13093		scale:       1,
13094		reg: regInfo{
13095			inputs: []inputInfo{
13096				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13097				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13098			},
13099		},
13100	},
13101	{
13102		name:      "MOVQstoreconstidx8",
13103		auxType:   auxSymValAndOff,
13104		argLen:    3,
13105		symEffect: SymWrite,
13106		asm:       x86.AMOVQ,
13107		scale:     8,
13108		reg: regInfo{
13109			inputs: []inputInfo{
13110				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13111				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13112			},
13113		},
13114	},
13115	{
13116		name:           "DUFFZERO",
13117		auxType:        auxInt64,
13118		argLen:         2,
13119		faultOnNilArg0: true,
13120		unsafePoint:    true,
13121		reg: regInfo{
13122			inputs: []inputInfo{
13123				{0, 128}, // DI
13124			},
13125			clobbers: 128, // DI
13126		},
13127	},
13128	{
13129		name:           "REPSTOSQ",
13130		argLen:         4,
13131		faultOnNilArg0: true,
13132		reg: regInfo{
13133			inputs: []inputInfo{
13134				{0, 128}, // DI
13135				{1, 2},   // CX
13136				{2, 1},   // AX
13137			},
13138			clobbers: 130, // CX DI
13139		},
13140	},
13141	{
13142		name:         "CALLstatic",
13143		auxType:      auxCallOff,
13144		argLen:       -1,
13145		clobberFlags: true,
13146		call:         true,
13147		reg: regInfo{
13148			clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13149		},
13150	},
13151	{
13152		name:         "CALLtail",
13153		auxType:      auxCallOff,
13154		argLen:       -1,
13155		clobberFlags: true,
13156		call:         true,
13157		tailCall:     true,
13158		reg: regInfo{
13159			clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13160		},
13161	},
13162	{
13163		name:         "CALLclosure",
13164		auxType:      auxCallOff,
13165		argLen:       -1,
13166		clobberFlags: true,
13167		call:         true,
13168		reg: regInfo{
13169			inputs: []inputInfo{
13170				{1, 4},     // DX
13171				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13172			},
13173			clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13174		},
13175	},
13176	{
13177		name:         "CALLinter",
13178		auxType:      auxCallOff,
13179		argLen:       -1,
13180		clobberFlags: true,
13181		call:         true,
13182		reg: regInfo{
13183			inputs: []inputInfo{
13184				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13185			},
13186			clobbers: 2147483631, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 g R15 X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13187		},
13188	},
13189	{
13190		name:           "DUFFCOPY",
13191		auxType:        auxInt64,
13192		argLen:         3,
13193		clobberFlags:   true,
13194		faultOnNilArg0: true,
13195		faultOnNilArg1: true,
13196		unsafePoint:    true,
13197		reg: regInfo{
13198			inputs: []inputInfo{
13199				{0, 128}, // DI
13200				{1, 64},  // SI
13201			},
13202			clobbers: 65728, // SI DI X0
13203		},
13204	},
13205	{
13206		name:           "REPMOVSQ",
13207		argLen:         4,
13208		faultOnNilArg0: true,
13209		faultOnNilArg1: true,
13210		reg: regInfo{
13211			inputs: []inputInfo{
13212				{0, 128}, // DI
13213				{1, 64},  // SI
13214				{2, 2},   // CX
13215			},
13216			clobbers: 194, // CX SI DI
13217		},
13218	},
13219	{
13220		name:   "InvertFlags",
13221		argLen: 1,
13222		reg:    regInfo{},
13223	},
13224	{
13225		name:   "LoweredGetG",
13226		argLen: 1,
13227		reg: regInfo{
13228			outputs: []outputInfo{
13229				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13230			},
13231		},
13232	},
13233	{
13234		name:      "LoweredGetClosurePtr",
13235		argLen:    0,
13236		zeroWidth: true,
13237		reg: regInfo{
13238			outputs: []outputInfo{
13239				{0, 4}, // DX
13240			},
13241		},
13242	},
13243	{
13244		name:              "LoweredGetCallerPC",
13245		argLen:            0,
13246		rematerializeable: true,
13247		reg: regInfo{
13248			outputs: []outputInfo{
13249				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13250			},
13251		},
13252	},
13253	{
13254		name:              "LoweredGetCallerSP",
13255		argLen:            0,
13256		rematerializeable: true,
13257		reg: regInfo{
13258			outputs: []outputInfo{
13259				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13260			},
13261		},
13262	},
13263	{
13264		name:           "LoweredNilCheck",
13265		argLen:         2,
13266		clobberFlags:   true,
13267		nilCheck:       true,
13268		faultOnNilArg0: true,
13269		reg: regInfo{
13270			inputs: []inputInfo{
13271				{0, 49151}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13272			},
13273		},
13274	},
13275	{
13276		name:         "LoweredWB",
13277		auxType:      auxSym,
13278		argLen:       3,
13279		clobberFlags: true,
13280		symEffect:    SymNone,
13281		reg: regInfo{
13282			inputs: []inputInfo{
13283				{0, 128}, // DI
13284				{1, 879}, // AX CX DX BX BP SI R8 R9
13285			},
13286			clobbers: 2147418112, // X0 X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X11 X12 X13 X14
13287		},
13288	},
13289	{
13290		name:              "LoweredHasCPUFeature",
13291		auxType:           auxSym,
13292		argLen:            0,
13293		rematerializeable: true,
13294		symEffect:         SymNone,
13295		reg: regInfo{
13296			outputs: []outputInfo{
13297				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13298			},
13299		},
13300	},
13301	{
13302		name:    "LoweredPanicBoundsA",
13303		auxType: auxInt64,
13304		argLen:  3,
13305		call:    true,
13306		reg: regInfo{
13307			inputs: []inputInfo{
13308				{0, 4}, // DX
13309				{1, 8}, // BX
13310			},
13311		},
13312	},
13313	{
13314		name:    "LoweredPanicBoundsB",
13315		auxType: auxInt64,
13316		argLen:  3,
13317		call:    true,
13318		reg: regInfo{
13319			inputs: []inputInfo{
13320				{0, 2}, // CX
13321				{1, 4}, // DX
13322			},
13323		},
13324	},
13325	{
13326		name:    "LoweredPanicBoundsC",
13327		auxType: auxInt64,
13328		argLen:  3,
13329		call:    true,
13330		reg: regInfo{
13331			inputs: []inputInfo{
13332				{0, 1}, // AX
13333				{1, 2}, // CX
13334			},
13335		},
13336	},
13337	{
13338		name:   "FlagEQ",
13339		argLen: 0,
13340		reg:    regInfo{},
13341	},
13342	{
13343		name:   "FlagLT_ULT",
13344		argLen: 0,
13345		reg:    regInfo{},
13346	},
13347	{
13348		name:   "FlagLT_UGT",
13349		argLen: 0,
13350		reg:    regInfo{},
13351	},
13352	{
13353		name:   "FlagGT_UGT",
13354		argLen: 0,
13355		reg:    regInfo{},
13356	},
13357	{
13358		name:   "FlagGT_ULT",
13359		argLen: 0,
13360		reg:    regInfo{},
13361	},
13362	{
13363		name:           "MOVBatomicload",
13364		auxType:        auxSymOff,
13365		argLen:         2,
13366		faultOnNilArg0: true,
13367		symEffect:      SymRead,
13368		asm:            x86.AMOVB,
13369		reg: regInfo{
13370			inputs: []inputInfo{
13371				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13372			},
13373			outputs: []outputInfo{
13374				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13375			},
13376		},
13377	},
13378	{
13379		name:           "MOVLatomicload",
13380		auxType:        auxSymOff,
13381		argLen:         2,
13382		faultOnNilArg0: true,
13383		symEffect:      SymRead,
13384		asm:            x86.AMOVL,
13385		reg: regInfo{
13386			inputs: []inputInfo{
13387				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13388			},
13389			outputs: []outputInfo{
13390				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13391			},
13392		},
13393	},
13394	{
13395		name:           "MOVQatomicload",
13396		auxType:        auxSymOff,
13397		argLen:         2,
13398		faultOnNilArg0: true,
13399		symEffect:      SymRead,
13400		asm:            x86.AMOVQ,
13401		reg: regInfo{
13402			inputs: []inputInfo{
13403				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13404			},
13405			outputs: []outputInfo{
13406				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13407			},
13408		},
13409	},
13410	{
13411		name:           "XCHGB",
13412		auxType:        auxSymOff,
13413		argLen:         3,
13414		resultInArg0:   true,
13415		faultOnNilArg1: true,
13416		hasSideEffects: true,
13417		symEffect:      SymRdWr,
13418		asm:            x86.AXCHGB,
13419		reg: regInfo{
13420			inputs: []inputInfo{
13421				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13422				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13423			},
13424			outputs: []outputInfo{
13425				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13426			},
13427		},
13428	},
13429	{
13430		name:           "XCHGL",
13431		auxType:        auxSymOff,
13432		argLen:         3,
13433		resultInArg0:   true,
13434		faultOnNilArg1: true,
13435		hasSideEffects: true,
13436		symEffect:      SymRdWr,
13437		asm:            x86.AXCHGL,
13438		reg: regInfo{
13439			inputs: []inputInfo{
13440				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13441				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13442			},
13443			outputs: []outputInfo{
13444				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13445			},
13446		},
13447	},
13448	{
13449		name:           "XCHGQ",
13450		auxType:        auxSymOff,
13451		argLen:         3,
13452		resultInArg0:   true,
13453		faultOnNilArg1: true,
13454		hasSideEffects: true,
13455		symEffect:      SymRdWr,
13456		asm:            x86.AXCHGQ,
13457		reg: regInfo{
13458			inputs: []inputInfo{
13459				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13460				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13461			},
13462			outputs: []outputInfo{
13463				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13464			},
13465		},
13466	},
13467	{
13468		name:           "XADDLlock",
13469		auxType:        auxSymOff,
13470		argLen:         3,
13471		resultInArg0:   true,
13472		clobberFlags:   true,
13473		faultOnNilArg1: true,
13474		hasSideEffects: true,
13475		symEffect:      SymRdWr,
13476		asm:            x86.AXADDL,
13477		reg: regInfo{
13478			inputs: []inputInfo{
13479				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13480				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13481			},
13482			outputs: []outputInfo{
13483				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13484			},
13485		},
13486	},
13487	{
13488		name:           "XADDQlock",
13489		auxType:        auxSymOff,
13490		argLen:         3,
13491		resultInArg0:   true,
13492		clobberFlags:   true,
13493		faultOnNilArg1: true,
13494		hasSideEffects: true,
13495		symEffect:      SymRdWr,
13496		asm:            x86.AXADDQ,
13497		reg: regInfo{
13498			inputs: []inputInfo{
13499				{0, 49135},      // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13500				{1, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13501			},
13502			outputs: []outputInfo{
13503				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13504			},
13505		},
13506	},
13507	{
13508		name:   "AddTupleFirst32",
13509		argLen: 2,
13510		reg:    regInfo{},
13511	},
13512	{
13513		name:   "AddTupleFirst64",
13514		argLen: 2,
13515		reg:    regInfo{},
13516	},
13517	{
13518		name:           "CMPXCHGLlock",
13519		auxType:        auxSymOff,
13520		argLen:         4,
13521		clobberFlags:   true,
13522		faultOnNilArg0: true,
13523		hasSideEffects: true,
13524		symEffect:      SymRdWr,
13525		asm:            x86.ACMPXCHGL,
13526		reg: regInfo{
13527			inputs: []inputInfo{
13528				{1, 1},     // AX
13529				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13530				{2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13531			},
13532			clobbers: 1, // AX
13533			outputs: []outputInfo{
13534				{1, 0},
13535				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13536			},
13537		},
13538	},
13539	{
13540		name:           "CMPXCHGQlock",
13541		auxType:        auxSymOff,
13542		argLen:         4,
13543		clobberFlags:   true,
13544		faultOnNilArg0: true,
13545		hasSideEffects: true,
13546		symEffect:      SymRdWr,
13547		asm:            x86.ACMPXCHGQ,
13548		reg: regInfo{
13549			inputs: []inputInfo{
13550				{1, 1},     // AX
13551				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13552				{2, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13553			},
13554			clobbers: 1, // AX
13555			outputs: []outputInfo{
13556				{1, 0},
13557				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13558			},
13559		},
13560	},
13561	{
13562		name:           "ANDBlock",
13563		auxType:        auxSymOff,
13564		argLen:         3,
13565		clobberFlags:   true,
13566		faultOnNilArg0: true,
13567		hasSideEffects: true,
13568		symEffect:      SymRdWr,
13569		asm:            x86.AANDB,
13570		reg: regInfo{
13571			inputs: []inputInfo{
13572				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13573				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13574			},
13575		},
13576	},
13577	{
13578		name:           "ANDLlock",
13579		auxType:        auxSymOff,
13580		argLen:         3,
13581		clobberFlags:   true,
13582		faultOnNilArg0: true,
13583		hasSideEffects: true,
13584		symEffect:      SymRdWr,
13585		asm:            x86.AANDL,
13586		reg: regInfo{
13587			inputs: []inputInfo{
13588				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13589				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13590			},
13591		},
13592	},
13593	{
13594		name:           "ORBlock",
13595		auxType:        auxSymOff,
13596		argLen:         3,
13597		clobberFlags:   true,
13598		faultOnNilArg0: true,
13599		hasSideEffects: true,
13600		symEffect:      SymRdWr,
13601		asm:            x86.AORB,
13602		reg: regInfo{
13603			inputs: []inputInfo{
13604				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13605				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13606			},
13607		},
13608	},
13609	{
13610		name:           "ORLlock",
13611		auxType:        auxSymOff,
13612		argLen:         3,
13613		clobberFlags:   true,
13614		faultOnNilArg0: true,
13615		hasSideEffects: true,
13616		symEffect:      SymRdWr,
13617		asm:            x86.AORL,
13618		reg: regInfo{
13619			inputs: []inputInfo{
13620				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13621				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13622			},
13623		},
13624	},
13625	{
13626		name:           "PrefetchT0",
13627		argLen:         2,
13628		hasSideEffects: true,
13629		asm:            x86.APREFETCHT0,
13630		reg: regInfo{
13631			inputs: []inputInfo{
13632				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13633			},
13634		},
13635	},
13636	{
13637		name:           "PrefetchNTA",
13638		argLen:         2,
13639		hasSideEffects: true,
13640		asm:            x86.APREFETCHNTA,
13641		reg: regInfo{
13642			inputs: []inputInfo{
13643				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13644			},
13645		},
13646	},
13647	{
13648		name:         "ANDNQ",
13649		argLen:       2,
13650		clobberFlags: true,
13651		asm:          x86.AANDNQ,
13652		reg: regInfo{
13653			inputs: []inputInfo{
13654				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13655				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13656			},
13657			outputs: []outputInfo{
13658				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13659			},
13660		},
13661	},
13662	{
13663		name:         "ANDNL",
13664		argLen:       2,
13665		clobberFlags: true,
13666		asm:          x86.AANDNL,
13667		reg: regInfo{
13668			inputs: []inputInfo{
13669				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13670				{1, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13671			},
13672			outputs: []outputInfo{
13673				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13674			},
13675		},
13676	},
13677	{
13678		name:         "BLSIQ",
13679		argLen:       1,
13680		clobberFlags: true,
13681		asm:          x86.ABLSIQ,
13682		reg: regInfo{
13683			inputs: []inputInfo{
13684				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13685			},
13686			outputs: []outputInfo{
13687				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13688			},
13689		},
13690	},
13691	{
13692		name:         "BLSIL",
13693		argLen:       1,
13694		clobberFlags: true,
13695		asm:          x86.ABLSIL,
13696		reg: regInfo{
13697			inputs: []inputInfo{
13698				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13699			},
13700			outputs: []outputInfo{
13701				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13702			},
13703		},
13704	},
13705	{
13706		name:         "BLSMSKQ",
13707		argLen:       1,
13708		clobberFlags: true,
13709		asm:          x86.ABLSMSKQ,
13710		reg: regInfo{
13711			inputs: []inputInfo{
13712				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13713			},
13714			outputs: []outputInfo{
13715				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13716			},
13717		},
13718	},
13719	{
13720		name:         "BLSMSKL",
13721		argLen:       1,
13722		clobberFlags: true,
13723		asm:          x86.ABLSMSKL,
13724		reg: regInfo{
13725			inputs: []inputInfo{
13726				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13727			},
13728			outputs: []outputInfo{
13729				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13730			},
13731		},
13732	},
13733	{
13734		name:         "BLSRQ",
13735		argLen:       1,
13736		clobberFlags: true,
13737		asm:          x86.ABLSRQ,
13738		reg: regInfo{
13739			inputs: []inputInfo{
13740				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13741			},
13742			outputs: []outputInfo{
13743				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13744			},
13745		},
13746	},
13747	{
13748		name:         "BLSRL",
13749		argLen:       1,
13750		clobberFlags: true,
13751		asm:          x86.ABLSRL,
13752		reg: regInfo{
13753			inputs: []inputInfo{
13754				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13755			},
13756			outputs: []outputInfo{
13757				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13758			},
13759		},
13760	},
13761	{
13762		name:         "TZCNTQ",
13763		argLen:       1,
13764		clobberFlags: true,
13765		asm:          x86.ATZCNTQ,
13766		reg: regInfo{
13767			inputs: []inputInfo{
13768				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13769			},
13770			outputs: []outputInfo{
13771				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13772			},
13773		},
13774	},
13775	{
13776		name:         "TZCNTL",
13777		argLen:       1,
13778		clobberFlags: true,
13779		asm:          x86.ATZCNTL,
13780		reg: regInfo{
13781			inputs: []inputInfo{
13782				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13783			},
13784			outputs: []outputInfo{
13785				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13786			},
13787		},
13788	},
13789	{
13790		name:           "MOVBELload",
13791		auxType:        auxSymOff,
13792		argLen:         2,
13793		faultOnNilArg0: true,
13794		symEffect:      SymRead,
13795		asm:            x86.AMOVBEL,
13796		reg: regInfo{
13797			inputs: []inputInfo{
13798				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13799			},
13800			outputs: []outputInfo{
13801				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13802			},
13803		},
13804	},
13805	{
13806		name:           "MOVBELstore",
13807		auxType:        auxSymOff,
13808		argLen:         3,
13809		faultOnNilArg0: true,
13810		symEffect:      SymWrite,
13811		asm:            x86.AMOVBEL,
13812		reg: regInfo{
13813			inputs: []inputInfo{
13814				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13815				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13816			},
13817		},
13818	},
13819	{
13820		name:           "MOVBEQload",
13821		auxType:        auxSymOff,
13822		argLen:         2,
13823		faultOnNilArg0: true,
13824		symEffect:      SymRead,
13825		asm:            x86.AMOVBEQ,
13826		reg: regInfo{
13827			inputs: []inputInfo{
13828				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13829			},
13830			outputs: []outputInfo{
13831				{0, 49135}, // AX CX DX BX BP SI DI R8 R9 R10 R11 R12 R13 R15
13832			},
13833		},
13834	},
13835	{
13836		name:           "MOVBEQstore",
13837		auxType:        auxSymOff,
13838		argLen:         3,
13839		faultOnNilArg0: true,
13840		symEffect:      SymWrite,
13841		asm:            x86.AMOVBEQ,
13842		reg: regInfo{
13843			inputs: []inputInfo{
13844				{1, 49151},      // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 R15
13845				{0, 4295032831}, // AX CX DX BX SP BP SI DI R8 R9 R10 R11 R12 R13 g R15 SB
13846			},
13847		},
13848	},
13849
13850	{
13851		name:        "ADD",
13852		argLen:      2,
13853		commutative: true,
13854		asm:         arm.AADD,
13855		reg: regInfo{
13856			inputs: []inputInfo{
13857				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13858				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13859			},
13860			outputs: []outputInfo{
13861				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13862			},
13863		},
13864	},
13865	{
13866		name:    "ADDconst",
13867		auxType: auxInt32,
13868		argLen:  1,
13869		asm:     arm.AADD,
13870		reg: regInfo{
13871			inputs: []inputInfo{
13872				{0, 30719}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14
13873			},
13874			outputs: []outputInfo{
13875				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13876			},
13877		},
13878	},
13879	{
13880		name:   "SUB",
13881		argLen: 2,
13882		asm:    arm.ASUB,
13883		reg: regInfo{
13884			inputs: []inputInfo{
13885				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13886				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13887			},
13888			outputs: []outputInfo{
13889				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13890			},
13891		},
13892	},
13893	{
13894		name:    "SUBconst",
13895		auxType: auxInt32,
13896		argLen:  1,
13897		asm:     arm.ASUB,
13898		reg: regInfo{
13899			inputs: []inputInfo{
13900				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13901			},
13902			outputs: []outputInfo{
13903				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13904			},
13905		},
13906	},
13907	{
13908		name:   "RSB",
13909		argLen: 2,
13910		asm:    arm.ARSB,
13911		reg: regInfo{
13912			inputs: []inputInfo{
13913				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13914				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13915			},
13916			outputs: []outputInfo{
13917				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13918			},
13919		},
13920	},
13921	{
13922		name:    "RSBconst",
13923		auxType: auxInt32,
13924		argLen:  1,
13925		asm:     arm.ARSB,
13926		reg: regInfo{
13927			inputs: []inputInfo{
13928				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13929			},
13930			outputs: []outputInfo{
13931				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13932			},
13933		},
13934	},
13935	{
13936		name:        "MUL",
13937		argLen:      2,
13938		commutative: true,
13939		asm:         arm.AMUL,
13940		reg: regInfo{
13941			inputs: []inputInfo{
13942				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13943				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13944			},
13945			outputs: []outputInfo{
13946				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13947			},
13948		},
13949	},
13950	{
13951		name:        "HMUL",
13952		argLen:      2,
13953		commutative: true,
13954		asm:         arm.AMULL,
13955		reg: regInfo{
13956			inputs: []inputInfo{
13957				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13958				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13959			},
13960			outputs: []outputInfo{
13961				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13962			},
13963		},
13964	},
13965	{
13966		name:        "HMULU",
13967		argLen:      2,
13968		commutative: true,
13969		asm:         arm.AMULLU,
13970		reg: regInfo{
13971			inputs: []inputInfo{
13972				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13973				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
13974			},
13975			outputs: []outputInfo{
13976				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
13977			},
13978		},
13979	},
13980	{
13981		name:         "CALLudiv",
13982		argLen:       2,
13983		clobberFlags: true,
13984		reg: regInfo{
13985			inputs: []inputInfo{
13986				{0, 2}, // R1
13987				{1, 1}, // R0
13988			},
13989			clobbers: 20492, // R2 R3 R12 R14
13990			outputs: []outputInfo{
13991				{0, 1}, // R0
13992				{1, 2}, // R1
13993			},
13994		},
13995	},
13996	{
13997		name:        "ADDS",
13998		argLen:      2,
13999		commutative: true,
14000		asm:         arm.AADD,
14001		reg: regInfo{
14002			inputs: []inputInfo{
14003				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14004				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14005			},
14006			outputs: []outputInfo{
14007				{1, 0},
14008				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14009			},
14010		},
14011	},
14012	{
14013		name:    "ADDSconst",
14014		auxType: auxInt32,
14015		argLen:  1,
14016		asm:     arm.AADD,
14017		reg: regInfo{
14018			inputs: []inputInfo{
14019				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14020			},
14021			outputs: []outputInfo{
14022				{1, 0},
14023				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14024			},
14025		},
14026	},
14027	{
14028		name:        "ADC",
14029		argLen:      3,
14030		commutative: true,
14031		asm:         arm.AADC,
14032		reg: regInfo{
14033			inputs: []inputInfo{
14034				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14035				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14036			},
14037			outputs: []outputInfo{
14038				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14039			},
14040		},
14041	},
14042	{
14043		name:    "ADCconst",
14044		auxType: auxInt32,
14045		argLen:  2,
14046		asm:     arm.AADC,
14047		reg: regInfo{
14048			inputs: []inputInfo{
14049				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14050			},
14051			outputs: []outputInfo{
14052				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14053			},
14054		},
14055	},
14056	{
14057		name:   "SUBS",
14058		argLen: 2,
14059		asm:    arm.ASUB,
14060		reg: regInfo{
14061			inputs: []inputInfo{
14062				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14063				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14064			},
14065			outputs: []outputInfo{
14066				{1, 0},
14067				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14068			},
14069		},
14070	},
14071	{
14072		name:    "SUBSconst",
14073		auxType: auxInt32,
14074		argLen:  1,
14075		asm:     arm.ASUB,
14076		reg: regInfo{
14077			inputs: []inputInfo{
14078				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14079			},
14080			outputs: []outputInfo{
14081				{1, 0},
14082				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14083			},
14084		},
14085	},
14086	{
14087		name:    "RSBSconst",
14088		auxType: auxInt32,
14089		argLen:  1,
14090		asm:     arm.ARSB,
14091		reg: regInfo{
14092			inputs: []inputInfo{
14093				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14094			},
14095			outputs: []outputInfo{
14096				{1, 0},
14097				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14098			},
14099		},
14100	},
14101	{
14102		name:   "SBC",
14103		argLen: 3,
14104		asm:    arm.ASBC,
14105		reg: regInfo{
14106			inputs: []inputInfo{
14107				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14108				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14109			},
14110			outputs: []outputInfo{
14111				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14112			},
14113		},
14114	},
14115	{
14116		name:    "SBCconst",
14117		auxType: auxInt32,
14118		argLen:  2,
14119		asm:     arm.ASBC,
14120		reg: regInfo{
14121			inputs: []inputInfo{
14122				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14123			},
14124			outputs: []outputInfo{
14125				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14126			},
14127		},
14128	},
14129	{
14130		name:    "RSCconst",
14131		auxType: auxInt32,
14132		argLen:  2,
14133		asm:     arm.ARSC,
14134		reg: regInfo{
14135			inputs: []inputInfo{
14136				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14137			},
14138			outputs: []outputInfo{
14139				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14140			},
14141		},
14142	},
14143	{
14144		name:        "MULLU",
14145		argLen:      2,
14146		commutative: true,
14147		asm:         arm.AMULLU,
14148		reg: regInfo{
14149			inputs: []inputInfo{
14150				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14151				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14152			},
14153			outputs: []outputInfo{
14154				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14155				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14156			},
14157		},
14158	},
14159	{
14160		name:   "MULA",
14161		argLen: 3,
14162		asm:    arm.AMULA,
14163		reg: regInfo{
14164			inputs: []inputInfo{
14165				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14166				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14167				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14168			},
14169			outputs: []outputInfo{
14170				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14171			},
14172		},
14173	},
14174	{
14175		name:   "MULS",
14176		argLen: 3,
14177		asm:    arm.AMULS,
14178		reg: regInfo{
14179			inputs: []inputInfo{
14180				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14181				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14182				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14183			},
14184			outputs: []outputInfo{
14185				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14186			},
14187		},
14188	},
14189	{
14190		name:        "ADDF",
14191		argLen:      2,
14192		commutative: true,
14193		asm:         arm.AADDF,
14194		reg: regInfo{
14195			inputs: []inputInfo{
14196				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14197				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14198			},
14199			outputs: []outputInfo{
14200				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14201			},
14202		},
14203	},
14204	{
14205		name:        "ADDD",
14206		argLen:      2,
14207		commutative: true,
14208		asm:         arm.AADDD,
14209		reg: regInfo{
14210			inputs: []inputInfo{
14211				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14212				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14213			},
14214			outputs: []outputInfo{
14215				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14216			},
14217		},
14218	},
14219	{
14220		name:   "SUBF",
14221		argLen: 2,
14222		asm:    arm.ASUBF,
14223		reg: regInfo{
14224			inputs: []inputInfo{
14225				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14226				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14227			},
14228			outputs: []outputInfo{
14229				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14230			},
14231		},
14232	},
14233	{
14234		name:   "SUBD",
14235		argLen: 2,
14236		asm:    arm.ASUBD,
14237		reg: regInfo{
14238			inputs: []inputInfo{
14239				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14240				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14241			},
14242			outputs: []outputInfo{
14243				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14244			},
14245		},
14246	},
14247	{
14248		name:        "MULF",
14249		argLen:      2,
14250		commutative: true,
14251		asm:         arm.AMULF,
14252		reg: regInfo{
14253			inputs: []inputInfo{
14254				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14255				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14256			},
14257			outputs: []outputInfo{
14258				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14259			},
14260		},
14261	},
14262	{
14263		name:        "MULD",
14264		argLen:      2,
14265		commutative: true,
14266		asm:         arm.AMULD,
14267		reg: regInfo{
14268			inputs: []inputInfo{
14269				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14270				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14271			},
14272			outputs: []outputInfo{
14273				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14274			},
14275		},
14276	},
14277	{
14278		name:        "NMULF",
14279		argLen:      2,
14280		commutative: true,
14281		asm:         arm.ANMULF,
14282		reg: regInfo{
14283			inputs: []inputInfo{
14284				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14285				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14286			},
14287			outputs: []outputInfo{
14288				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14289			},
14290		},
14291	},
14292	{
14293		name:        "NMULD",
14294		argLen:      2,
14295		commutative: true,
14296		asm:         arm.ANMULD,
14297		reg: regInfo{
14298			inputs: []inputInfo{
14299				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14300				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14301			},
14302			outputs: []outputInfo{
14303				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14304			},
14305		},
14306	},
14307	{
14308		name:   "DIVF",
14309		argLen: 2,
14310		asm:    arm.ADIVF,
14311		reg: regInfo{
14312			inputs: []inputInfo{
14313				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14314				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14315			},
14316			outputs: []outputInfo{
14317				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14318			},
14319		},
14320	},
14321	{
14322		name:   "DIVD",
14323		argLen: 2,
14324		asm:    arm.ADIVD,
14325		reg: regInfo{
14326			inputs: []inputInfo{
14327				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14328				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14329			},
14330			outputs: []outputInfo{
14331				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14332			},
14333		},
14334	},
14335	{
14336		name:         "MULAF",
14337		argLen:       3,
14338		resultInArg0: true,
14339		asm:          arm.AMULAF,
14340		reg: regInfo{
14341			inputs: []inputInfo{
14342				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14343				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14344				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14345			},
14346			outputs: []outputInfo{
14347				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14348			},
14349		},
14350	},
14351	{
14352		name:         "MULAD",
14353		argLen:       3,
14354		resultInArg0: true,
14355		asm:          arm.AMULAD,
14356		reg: regInfo{
14357			inputs: []inputInfo{
14358				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14359				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14360				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14361			},
14362			outputs: []outputInfo{
14363				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14364			},
14365		},
14366	},
14367	{
14368		name:         "MULSF",
14369		argLen:       3,
14370		resultInArg0: true,
14371		asm:          arm.AMULSF,
14372		reg: regInfo{
14373			inputs: []inputInfo{
14374				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14375				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14376				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14377			},
14378			outputs: []outputInfo{
14379				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14380			},
14381		},
14382	},
14383	{
14384		name:         "MULSD",
14385		argLen:       3,
14386		resultInArg0: true,
14387		asm:          arm.AMULSD,
14388		reg: regInfo{
14389			inputs: []inputInfo{
14390				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14391				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14392				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14393			},
14394			outputs: []outputInfo{
14395				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14396			},
14397		},
14398	},
14399	{
14400		name:         "FMULAD",
14401		argLen:       3,
14402		resultInArg0: true,
14403		asm:          arm.AFMULAD,
14404		reg: regInfo{
14405			inputs: []inputInfo{
14406				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14407				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14408				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14409			},
14410			outputs: []outputInfo{
14411				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14412			},
14413		},
14414	},
14415	{
14416		name:        "AND",
14417		argLen:      2,
14418		commutative: true,
14419		asm:         arm.AAND,
14420		reg: regInfo{
14421			inputs: []inputInfo{
14422				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14423				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14424			},
14425			outputs: []outputInfo{
14426				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14427			},
14428		},
14429	},
14430	{
14431		name:    "ANDconst",
14432		auxType: auxInt32,
14433		argLen:  1,
14434		asm:     arm.AAND,
14435		reg: regInfo{
14436			inputs: []inputInfo{
14437				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14438			},
14439			outputs: []outputInfo{
14440				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14441			},
14442		},
14443	},
14444	{
14445		name:        "OR",
14446		argLen:      2,
14447		commutative: true,
14448		asm:         arm.AORR,
14449		reg: regInfo{
14450			inputs: []inputInfo{
14451				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14452				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14453			},
14454			outputs: []outputInfo{
14455				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14456			},
14457		},
14458	},
14459	{
14460		name:    "ORconst",
14461		auxType: auxInt32,
14462		argLen:  1,
14463		asm:     arm.AORR,
14464		reg: regInfo{
14465			inputs: []inputInfo{
14466				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14467			},
14468			outputs: []outputInfo{
14469				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14470			},
14471		},
14472	},
14473	{
14474		name:        "XOR",
14475		argLen:      2,
14476		commutative: true,
14477		asm:         arm.AEOR,
14478		reg: regInfo{
14479			inputs: []inputInfo{
14480				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14481				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14482			},
14483			outputs: []outputInfo{
14484				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14485			},
14486		},
14487	},
14488	{
14489		name:    "XORconst",
14490		auxType: auxInt32,
14491		argLen:  1,
14492		asm:     arm.AEOR,
14493		reg: regInfo{
14494			inputs: []inputInfo{
14495				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14496			},
14497			outputs: []outputInfo{
14498				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14499			},
14500		},
14501	},
14502	{
14503		name:   "BIC",
14504		argLen: 2,
14505		asm:    arm.ABIC,
14506		reg: regInfo{
14507			inputs: []inputInfo{
14508				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14509				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14510			},
14511			outputs: []outputInfo{
14512				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14513			},
14514		},
14515	},
14516	{
14517		name:    "BICconst",
14518		auxType: auxInt32,
14519		argLen:  1,
14520		asm:     arm.ABIC,
14521		reg: regInfo{
14522			inputs: []inputInfo{
14523				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14524			},
14525			outputs: []outputInfo{
14526				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14527			},
14528		},
14529	},
14530	{
14531		name:    "BFX",
14532		auxType: auxInt32,
14533		argLen:  1,
14534		asm:     arm.ABFX,
14535		reg: regInfo{
14536			inputs: []inputInfo{
14537				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14538			},
14539			outputs: []outputInfo{
14540				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14541			},
14542		},
14543	},
14544	{
14545		name:    "BFXU",
14546		auxType: auxInt32,
14547		argLen:  1,
14548		asm:     arm.ABFXU,
14549		reg: regInfo{
14550			inputs: []inputInfo{
14551				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14552			},
14553			outputs: []outputInfo{
14554				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14555			},
14556		},
14557	},
14558	{
14559		name:   "MVN",
14560		argLen: 1,
14561		asm:    arm.AMVN,
14562		reg: regInfo{
14563			inputs: []inputInfo{
14564				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14565			},
14566			outputs: []outputInfo{
14567				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14568			},
14569		},
14570	},
14571	{
14572		name:   "NEGF",
14573		argLen: 1,
14574		asm:    arm.ANEGF,
14575		reg: regInfo{
14576			inputs: []inputInfo{
14577				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14578			},
14579			outputs: []outputInfo{
14580				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14581			},
14582		},
14583	},
14584	{
14585		name:   "NEGD",
14586		argLen: 1,
14587		asm:    arm.ANEGD,
14588		reg: regInfo{
14589			inputs: []inputInfo{
14590				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14591			},
14592			outputs: []outputInfo{
14593				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14594			},
14595		},
14596	},
14597	{
14598		name:   "SQRTD",
14599		argLen: 1,
14600		asm:    arm.ASQRTD,
14601		reg: regInfo{
14602			inputs: []inputInfo{
14603				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14604			},
14605			outputs: []outputInfo{
14606				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14607			},
14608		},
14609	},
14610	{
14611		name:   "SQRTF",
14612		argLen: 1,
14613		asm:    arm.ASQRTF,
14614		reg: regInfo{
14615			inputs: []inputInfo{
14616				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14617			},
14618			outputs: []outputInfo{
14619				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14620			},
14621		},
14622	},
14623	{
14624		name:   "ABSD",
14625		argLen: 1,
14626		asm:    arm.AABSD,
14627		reg: regInfo{
14628			inputs: []inputInfo{
14629				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14630			},
14631			outputs: []outputInfo{
14632				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
14633			},
14634		},
14635	},
14636	{
14637		name:   "CLZ",
14638		argLen: 1,
14639		asm:    arm.ACLZ,
14640		reg: regInfo{
14641			inputs: []inputInfo{
14642				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14643			},
14644			outputs: []outputInfo{
14645				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14646			},
14647		},
14648	},
14649	{
14650		name:   "REV",
14651		argLen: 1,
14652		asm:    arm.AREV,
14653		reg: regInfo{
14654			inputs: []inputInfo{
14655				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14656			},
14657			outputs: []outputInfo{
14658				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14659			},
14660		},
14661	},
14662	{
14663		name:   "REV16",
14664		argLen: 1,
14665		asm:    arm.AREV16,
14666		reg: regInfo{
14667			inputs: []inputInfo{
14668				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14669			},
14670			outputs: []outputInfo{
14671				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14672			},
14673		},
14674	},
14675	{
14676		name:   "RBIT",
14677		argLen: 1,
14678		asm:    arm.ARBIT,
14679		reg: regInfo{
14680			inputs: []inputInfo{
14681				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14682			},
14683			outputs: []outputInfo{
14684				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14685			},
14686		},
14687	},
14688	{
14689		name:   "SLL",
14690		argLen: 2,
14691		asm:    arm.ASLL,
14692		reg: regInfo{
14693			inputs: []inputInfo{
14694				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14695				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14696			},
14697			outputs: []outputInfo{
14698				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14699			},
14700		},
14701	},
14702	{
14703		name:    "SLLconst",
14704		auxType: auxInt32,
14705		argLen:  1,
14706		asm:     arm.ASLL,
14707		reg: regInfo{
14708			inputs: []inputInfo{
14709				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14710			},
14711			outputs: []outputInfo{
14712				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14713			},
14714		},
14715	},
14716	{
14717		name:   "SRL",
14718		argLen: 2,
14719		asm:    arm.ASRL,
14720		reg: regInfo{
14721			inputs: []inputInfo{
14722				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14723				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14724			},
14725			outputs: []outputInfo{
14726				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14727			},
14728		},
14729	},
14730	{
14731		name:    "SRLconst",
14732		auxType: auxInt32,
14733		argLen:  1,
14734		asm:     arm.ASRL,
14735		reg: regInfo{
14736			inputs: []inputInfo{
14737				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14738			},
14739			outputs: []outputInfo{
14740				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14741			},
14742		},
14743	},
14744	{
14745		name:   "SRA",
14746		argLen: 2,
14747		asm:    arm.ASRA,
14748		reg: regInfo{
14749			inputs: []inputInfo{
14750				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14751				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14752			},
14753			outputs: []outputInfo{
14754				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14755			},
14756		},
14757	},
14758	{
14759		name:    "SRAconst",
14760		auxType: auxInt32,
14761		argLen:  1,
14762		asm:     arm.ASRA,
14763		reg: regInfo{
14764			inputs: []inputInfo{
14765				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14766			},
14767			outputs: []outputInfo{
14768				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14769			},
14770		},
14771	},
14772	{
14773		name:   "SRR",
14774		argLen: 2,
14775		reg: regInfo{
14776			inputs: []inputInfo{
14777				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14778				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14779			},
14780			outputs: []outputInfo{
14781				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14782			},
14783		},
14784	},
14785	{
14786		name:    "SRRconst",
14787		auxType: auxInt32,
14788		argLen:  1,
14789		reg: regInfo{
14790			inputs: []inputInfo{
14791				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14792			},
14793			outputs: []outputInfo{
14794				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14795			},
14796		},
14797	},
14798	{
14799		name:    "ADDshiftLL",
14800		auxType: auxInt32,
14801		argLen:  2,
14802		asm:     arm.AADD,
14803		reg: regInfo{
14804			inputs: []inputInfo{
14805				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14806				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14807			},
14808			outputs: []outputInfo{
14809				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14810			},
14811		},
14812	},
14813	{
14814		name:    "ADDshiftRL",
14815		auxType: auxInt32,
14816		argLen:  2,
14817		asm:     arm.AADD,
14818		reg: regInfo{
14819			inputs: []inputInfo{
14820				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14821				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14822			},
14823			outputs: []outputInfo{
14824				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14825			},
14826		},
14827	},
14828	{
14829		name:    "ADDshiftRA",
14830		auxType: auxInt32,
14831		argLen:  2,
14832		asm:     arm.AADD,
14833		reg: regInfo{
14834			inputs: []inputInfo{
14835				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14836				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14837			},
14838			outputs: []outputInfo{
14839				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14840			},
14841		},
14842	},
14843	{
14844		name:    "SUBshiftLL",
14845		auxType: auxInt32,
14846		argLen:  2,
14847		asm:     arm.ASUB,
14848		reg: regInfo{
14849			inputs: []inputInfo{
14850				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14851				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14852			},
14853			outputs: []outputInfo{
14854				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14855			},
14856		},
14857	},
14858	{
14859		name:    "SUBshiftRL",
14860		auxType: auxInt32,
14861		argLen:  2,
14862		asm:     arm.ASUB,
14863		reg: regInfo{
14864			inputs: []inputInfo{
14865				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14866				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14867			},
14868			outputs: []outputInfo{
14869				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14870			},
14871		},
14872	},
14873	{
14874		name:    "SUBshiftRA",
14875		auxType: auxInt32,
14876		argLen:  2,
14877		asm:     arm.ASUB,
14878		reg: regInfo{
14879			inputs: []inputInfo{
14880				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14881				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14882			},
14883			outputs: []outputInfo{
14884				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14885			},
14886		},
14887	},
14888	{
14889		name:    "RSBshiftLL",
14890		auxType: auxInt32,
14891		argLen:  2,
14892		asm:     arm.ARSB,
14893		reg: regInfo{
14894			inputs: []inputInfo{
14895				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14896				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14897			},
14898			outputs: []outputInfo{
14899				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14900			},
14901		},
14902	},
14903	{
14904		name:    "RSBshiftRL",
14905		auxType: auxInt32,
14906		argLen:  2,
14907		asm:     arm.ARSB,
14908		reg: regInfo{
14909			inputs: []inputInfo{
14910				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14911				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14912			},
14913			outputs: []outputInfo{
14914				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14915			},
14916		},
14917	},
14918	{
14919		name:    "RSBshiftRA",
14920		auxType: auxInt32,
14921		argLen:  2,
14922		asm:     arm.ARSB,
14923		reg: regInfo{
14924			inputs: []inputInfo{
14925				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14926				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14927			},
14928			outputs: []outputInfo{
14929				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14930			},
14931		},
14932	},
14933	{
14934		name:    "ANDshiftLL",
14935		auxType: auxInt32,
14936		argLen:  2,
14937		asm:     arm.AAND,
14938		reg: regInfo{
14939			inputs: []inputInfo{
14940				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14941				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14942			},
14943			outputs: []outputInfo{
14944				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14945			},
14946		},
14947	},
14948	{
14949		name:    "ANDshiftRL",
14950		auxType: auxInt32,
14951		argLen:  2,
14952		asm:     arm.AAND,
14953		reg: regInfo{
14954			inputs: []inputInfo{
14955				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14956				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14957			},
14958			outputs: []outputInfo{
14959				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14960			},
14961		},
14962	},
14963	{
14964		name:    "ANDshiftRA",
14965		auxType: auxInt32,
14966		argLen:  2,
14967		asm:     arm.AAND,
14968		reg: regInfo{
14969			inputs: []inputInfo{
14970				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14971				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14972			},
14973			outputs: []outputInfo{
14974				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14975			},
14976		},
14977	},
14978	{
14979		name:    "ORshiftLL",
14980		auxType: auxInt32,
14981		argLen:  2,
14982		asm:     arm.AORR,
14983		reg: regInfo{
14984			inputs: []inputInfo{
14985				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14986				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
14987			},
14988			outputs: []outputInfo{
14989				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
14990			},
14991		},
14992	},
14993	{
14994		name:    "ORshiftRL",
14995		auxType: auxInt32,
14996		argLen:  2,
14997		asm:     arm.AORR,
14998		reg: regInfo{
14999			inputs: []inputInfo{
15000				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15001				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15002			},
15003			outputs: []outputInfo{
15004				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15005			},
15006		},
15007	},
15008	{
15009		name:    "ORshiftRA",
15010		auxType: auxInt32,
15011		argLen:  2,
15012		asm:     arm.AORR,
15013		reg: regInfo{
15014			inputs: []inputInfo{
15015				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15016				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15017			},
15018			outputs: []outputInfo{
15019				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15020			},
15021		},
15022	},
15023	{
15024		name:    "XORshiftLL",
15025		auxType: auxInt32,
15026		argLen:  2,
15027		asm:     arm.AEOR,
15028		reg: regInfo{
15029			inputs: []inputInfo{
15030				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15031				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15032			},
15033			outputs: []outputInfo{
15034				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15035			},
15036		},
15037	},
15038	{
15039		name:    "XORshiftRL",
15040		auxType: auxInt32,
15041		argLen:  2,
15042		asm:     arm.AEOR,
15043		reg: regInfo{
15044			inputs: []inputInfo{
15045				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15046				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15047			},
15048			outputs: []outputInfo{
15049				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15050			},
15051		},
15052	},
15053	{
15054		name:    "XORshiftRA",
15055		auxType: auxInt32,
15056		argLen:  2,
15057		asm:     arm.AEOR,
15058		reg: regInfo{
15059			inputs: []inputInfo{
15060				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15061				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15062			},
15063			outputs: []outputInfo{
15064				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15065			},
15066		},
15067	},
15068	{
15069		name:    "XORshiftRR",
15070		auxType: auxInt32,
15071		argLen:  2,
15072		asm:     arm.AEOR,
15073		reg: regInfo{
15074			inputs: []inputInfo{
15075				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15076				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15077			},
15078			outputs: []outputInfo{
15079				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15080			},
15081		},
15082	},
15083	{
15084		name:    "BICshiftLL",
15085		auxType: auxInt32,
15086		argLen:  2,
15087		asm:     arm.ABIC,
15088		reg: regInfo{
15089			inputs: []inputInfo{
15090				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15091				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15092			},
15093			outputs: []outputInfo{
15094				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15095			},
15096		},
15097	},
15098	{
15099		name:    "BICshiftRL",
15100		auxType: auxInt32,
15101		argLen:  2,
15102		asm:     arm.ABIC,
15103		reg: regInfo{
15104			inputs: []inputInfo{
15105				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15106				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15107			},
15108			outputs: []outputInfo{
15109				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15110			},
15111		},
15112	},
15113	{
15114		name:    "BICshiftRA",
15115		auxType: auxInt32,
15116		argLen:  2,
15117		asm:     arm.ABIC,
15118		reg: regInfo{
15119			inputs: []inputInfo{
15120				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15121				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15122			},
15123			outputs: []outputInfo{
15124				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15125			},
15126		},
15127	},
15128	{
15129		name:    "MVNshiftLL",
15130		auxType: auxInt32,
15131		argLen:  1,
15132		asm:     arm.AMVN,
15133		reg: regInfo{
15134			inputs: []inputInfo{
15135				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15136			},
15137			outputs: []outputInfo{
15138				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15139			},
15140		},
15141	},
15142	{
15143		name:    "MVNshiftRL",
15144		auxType: auxInt32,
15145		argLen:  1,
15146		asm:     arm.AMVN,
15147		reg: regInfo{
15148			inputs: []inputInfo{
15149				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15150			},
15151			outputs: []outputInfo{
15152				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15153			},
15154		},
15155	},
15156	{
15157		name:    "MVNshiftRA",
15158		auxType: auxInt32,
15159		argLen:  1,
15160		asm:     arm.AMVN,
15161		reg: regInfo{
15162			inputs: []inputInfo{
15163				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15164			},
15165			outputs: []outputInfo{
15166				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15167			},
15168		},
15169	},
15170	{
15171		name:    "ADCshiftLL",
15172		auxType: auxInt32,
15173		argLen:  3,
15174		asm:     arm.AADC,
15175		reg: regInfo{
15176			inputs: []inputInfo{
15177				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15178				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15179			},
15180			outputs: []outputInfo{
15181				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15182			},
15183		},
15184	},
15185	{
15186		name:    "ADCshiftRL",
15187		auxType: auxInt32,
15188		argLen:  3,
15189		asm:     arm.AADC,
15190		reg: regInfo{
15191			inputs: []inputInfo{
15192				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15193				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15194			},
15195			outputs: []outputInfo{
15196				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15197			},
15198		},
15199	},
15200	{
15201		name:    "ADCshiftRA",
15202		auxType: auxInt32,
15203		argLen:  3,
15204		asm:     arm.AADC,
15205		reg: regInfo{
15206			inputs: []inputInfo{
15207				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15208				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15209			},
15210			outputs: []outputInfo{
15211				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15212			},
15213		},
15214	},
15215	{
15216		name:    "SBCshiftLL",
15217		auxType: auxInt32,
15218		argLen:  3,
15219		asm:     arm.ASBC,
15220		reg: regInfo{
15221			inputs: []inputInfo{
15222				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15223				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15224			},
15225			outputs: []outputInfo{
15226				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15227			},
15228		},
15229	},
15230	{
15231		name:    "SBCshiftRL",
15232		auxType: auxInt32,
15233		argLen:  3,
15234		asm:     arm.ASBC,
15235		reg: regInfo{
15236			inputs: []inputInfo{
15237				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15238				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15239			},
15240			outputs: []outputInfo{
15241				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15242			},
15243		},
15244	},
15245	{
15246		name:    "SBCshiftRA",
15247		auxType: auxInt32,
15248		argLen:  3,
15249		asm:     arm.ASBC,
15250		reg: regInfo{
15251			inputs: []inputInfo{
15252				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15253				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15254			},
15255			outputs: []outputInfo{
15256				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15257			},
15258		},
15259	},
15260	{
15261		name:    "RSCshiftLL",
15262		auxType: auxInt32,
15263		argLen:  3,
15264		asm:     arm.ARSC,
15265		reg: regInfo{
15266			inputs: []inputInfo{
15267				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15268				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15269			},
15270			outputs: []outputInfo{
15271				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15272			},
15273		},
15274	},
15275	{
15276		name:    "RSCshiftRL",
15277		auxType: auxInt32,
15278		argLen:  3,
15279		asm:     arm.ARSC,
15280		reg: regInfo{
15281			inputs: []inputInfo{
15282				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15283				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15284			},
15285			outputs: []outputInfo{
15286				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15287			},
15288		},
15289	},
15290	{
15291		name:    "RSCshiftRA",
15292		auxType: auxInt32,
15293		argLen:  3,
15294		asm:     arm.ARSC,
15295		reg: regInfo{
15296			inputs: []inputInfo{
15297				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15298				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15299			},
15300			outputs: []outputInfo{
15301				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15302			},
15303		},
15304	},
15305	{
15306		name:    "ADDSshiftLL",
15307		auxType: auxInt32,
15308		argLen:  2,
15309		asm:     arm.AADD,
15310		reg: regInfo{
15311			inputs: []inputInfo{
15312				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15313				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15314			},
15315			outputs: []outputInfo{
15316				{1, 0},
15317				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15318			},
15319		},
15320	},
15321	{
15322		name:    "ADDSshiftRL",
15323		auxType: auxInt32,
15324		argLen:  2,
15325		asm:     arm.AADD,
15326		reg: regInfo{
15327			inputs: []inputInfo{
15328				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15329				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15330			},
15331			outputs: []outputInfo{
15332				{1, 0},
15333				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15334			},
15335		},
15336	},
15337	{
15338		name:    "ADDSshiftRA",
15339		auxType: auxInt32,
15340		argLen:  2,
15341		asm:     arm.AADD,
15342		reg: regInfo{
15343			inputs: []inputInfo{
15344				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15345				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15346			},
15347			outputs: []outputInfo{
15348				{1, 0},
15349				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15350			},
15351		},
15352	},
15353	{
15354		name:    "SUBSshiftLL",
15355		auxType: auxInt32,
15356		argLen:  2,
15357		asm:     arm.ASUB,
15358		reg: regInfo{
15359			inputs: []inputInfo{
15360				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15361				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15362			},
15363			outputs: []outputInfo{
15364				{1, 0},
15365				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15366			},
15367		},
15368	},
15369	{
15370		name:    "SUBSshiftRL",
15371		auxType: auxInt32,
15372		argLen:  2,
15373		asm:     arm.ASUB,
15374		reg: regInfo{
15375			inputs: []inputInfo{
15376				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15377				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15378			},
15379			outputs: []outputInfo{
15380				{1, 0},
15381				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15382			},
15383		},
15384	},
15385	{
15386		name:    "SUBSshiftRA",
15387		auxType: auxInt32,
15388		argLen:  2,
15389		asm:     arm.ASUB,
15390		reg: regInfo{
15391			inputs: []inputInfo{
15392				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15393				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15394			},
15395			outputs: []outputInfo{
15396				{1, 0},
15397				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15398			},
15399		},
15400	},
15401	{
15402		name:    "RSBSshiftLL",
15403		auxType: auxInt32,
15404		argLen:  2,
15405		asm:     arm.ARSB,
15406		reg: regInfo{
15407			inputs: []inputInfo{
15408				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15409				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15410			},
15411			outputs: []outputInfo{
15412				{1, 0},
15413				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15414			},
15415		},
15416	},
15417	{
15418		name:    "RSBSshiftRL",
15419		auxType: auxInt32,
15420		argLen:  2,
15421		asm:     arm.ARSB,
15422		reg: regInfo{
15423			inputs: []inputInfo{
15424				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15425				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15426			},
15427			outputs: []outputInfo{
15428				{1, 0},
15429				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15430			},
15431		},
15432	},
15433	{
15434		name:    "RSBSshiftRA",
15435		auxType: auxInt32,
15436		argLen:  2,
15437		asm:     arm.ARSB,
15438		reg: regInfo{
15439			inputs: []inputInfo{
15440				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15441				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15442			},
15443			outputs: []outputInfo{
15444				{1, 0},
15445				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15446			},
15447		},
15448	},
15449	{
15450		name:   "ADDshiftLLreg",
15451		argLen: 3,
15452		asm:    arm.AADD,
15453		reg: regInfo{
15454			inputs: []inputInfo{
15455				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15456				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15457				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15458			},
15459			outputs: []outputInfo{
15460				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15461			},
15462		},
15463	},
15464	{
15465		name:   "ADDshiftRLreg",
15466		argLen: 3,
15467		asm:    arm.AADD,
15468		reg: regInfo{
15469			inputs: []inputInfo{
15470				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15471				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15472				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15473			},
15474			outputs: []outputInfo{
15475				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15476			},
15477		},
15478	},
15479	{
15480		name:   "ADDshiftRAreg",
15481		argLen: 3,
15482		asm:    arm.AADD,
15483		reg: regInfo{
15484			inputs: []inputInfo{
15485				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15486				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15487				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15488			},
15489			outputs: []outputInfo{
15490				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15491			},
15492		},
15493	},
15494	{
15495		name:   "SUBshiftLLreg",
15496		argLen: 3,
15497		asm:    arm.ASUB,
15498		reg: regInfo{
15499			inputs: []inputInfo{
15500				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15501				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15502				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15503			},
15504			outputs: []outputInfo{
15505				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15506			},
15507		},
15508	},
15509	{
15510		name:   "SUBshiftRLreg",
15511		argLen: 3,
15512		asm:    arm.ASUB,
15513		reg: regInfo{
15514			inputs: []inputInfo{
15515				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15516				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15517				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15518			},
15519			outputs: []outputInfo{
15520				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15521			},
15522		},
15523	},
15524	{
15525		name:   "SUBshiftRAreg",
15526		argLen: 3,
15527		asm:    arm.ASUB,
15528		reg: regInfo{
15529			inputs: []inputInfo{
15530				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15531				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15532				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15533			},
15534			outputs: []outputInfo{
15535				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15536			},
15537		},
15538	},
15539	{
15540		name:   "RSBshiftLLreg",
15541		argLen: 3,
15542		asm:    arm.ARSB,
15543		reg: regInfo{
15544			inputs: []inputInfo{
15545				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15546				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15547				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15548			},
15549			outputs: []outputInfo{
15550				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15551			},
15552		},
15553	},
15554	{
15555		name:   "RSBshiftRLreg",
15556		argLen: 3,
15557		asm:    arm.ARSB,
15558		reg: regInfo{
15559			inputs: []inputInfo{
15560				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15561				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15562				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15563			},
15564			outputs: []outputInfo{
15565				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15566			},
15567		},
15568	},
15569	{
15570		name:   "RSBshiftRAreg",
15571		argLen: 3,
15572		asm:    arm.ARSB,
15573		reg: regInfo{
15574			inputs: []inputInfo{
15575				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15576				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15577				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15578			},
15579			outputs: []outputInfo{
15580				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15581			},
15582		},
15583	},
15584	{
15585		name:   "ANDshiftLLreg",
15586		argLen: 3,
15587		asm:    arm.AAND,
15588		reg: regInfo{
15589			inputs: []inputInfo{
15590				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15591				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15592				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15593			},
15594			outputs: []outputInfo{
15595				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15596			},
15597		},
15598	},
15599	{
15600		name:   "ANDshiftRLreg",
15601		argLen: 3,
15602		asm:    arm.AAND,
15603		reg: regInfo{
15604			inputs: []inputInfo{
15605				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15606				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15607				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15608			},
15609			outputs: []outputInfo{
15610				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15611			},
15612		},
15613	},
15614	{
15615		name:   "ANDshiftRAreg",
15616		argLen: 3,
15617		asm:    arm.AAND,
15618		reg: regInfo{
15619			inputs: []inputInfo{
15620				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15621				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15622				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15623			},
15624			outputs: []outputInfo{
15625				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15626			},
15627		},
15628	},
15629	{
15630		name:   "ORshiftLLreg",
15631		argLen: 3,
15632		asm:    arm.AORR,
15633		reg: regInfo{
15634			inputs: []inputInfo{
15635				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15636				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15637				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15638			},
15639			outputs: []outputInfo{
15640				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15641			},
15642		},
15643	},
15644	{
15645		name:   "ORshiftRLreg",
15646		argLen: 3,
15647		asm:    arm.AORR,
15648		reg: regInfo{
15649			inputs: []inputInfo{
15650				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15651				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15652				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15653			},
15654			outputs: []outputInfo{
15655				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15656			},
15657		},
15658	},
15659	{
15660		name:   "ORshiftRAreg",
15661		argLen: 3,
15662		asm:    arm.AORR,
15663		reg: regInfo{
15664			inputs: []inputInfo{
15665				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15666				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15667				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15668			},
15669			outputs: []outputInfo{
15670				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15671			},
15672		},
15673	},
15674	{
15675		name:   "XORshiftLLreg",
15676		argLen: 3,
15677		asm:    arm.AEOR,
15678		reg: regInfo{
15679			inputs: []inputInfo{
15680				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15681				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15682				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15683			},
15684			outputs: []outputInfo{
15685				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15686			},
15687		},
15688	},
15689	{
15690		name:   "XORshiftRLreg",
15691		argLen: 3,
15692		asm:    arm.AEOR,
15693		reg: regInfo{
15694			inputs: []inputInfo{
15695				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15696				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15697				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15698			},
15699			outputs: []outputInfo{
15700				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15701			},
15702		},
15703	},
15704	{
15705		name:   "XORshiftRAreg",
15706		argLen: 3,
15707		asm:    arm.AEOR,
15708		reg: regInfo{
15709			inputs: []inputInfo{
15710				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15711				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15712				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15713			},
15714			outputs: []outputInfo{
15715				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15716			},
15717		},
15718	},
15719	{
15720		name:   "BICshiftLLreg",
15721		argLen: 3,
15722		asm:    arm.ABIC,
15723		reg: regInfo{
15724			inputs: []inputInfo{
15725				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15726				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15727				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15728			},
15729			outputs: []outputInfo{
15730				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15731			},
15732		},
15733	},
15734	{
15735		name:   "BICshiftRLreg",
15736		argLen: 3,
15737		asm:    arm.ABIC,
15738		reg: regInfo{
15739			inputs: []inputInfo{
15740				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15741				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15742				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15743			},
15744			outputs: []outputInfo{
15745				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15746			},
15747		},
15748	},
15749	{
15750		name:   "BICshiftRAreg",
15751		argLen: 3,
15752		asm:    arm.ABIC,
15753		reg: regInfo{
15754			inputs: []inputInfo{
15755				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15756				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15757				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15758			},
15759			outputs: []outputInfo{
15760				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15761			},
15762		},
15763	},
15764	{
15765		name:   "MVNshiftLLreg",
15766		argLen: 2,
15767		asm:    arm.AMVN,
15768		reg: regInfo{
15769			inputs: []inputInfo{
15770				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15771				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15772			},
15773			outputs: []outputInfo{
15774				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15775			},
15776		},
15777	},
15778	{
15779		name:   "MVNshiftRLreg",
15780		argLen: 2,
15781		asm:    arm.AMVN,
15782		reg: regInfo{
15783			inputs: []inputInfo{
15784				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15785				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15786			},
15787			outputs: []outputInfo{
15788				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15789			},
15790		},
15791	},
15792	{
15793		name:   "MVNshiftRAreg",
15794		argLen: 2,
15795		asm:    arm.AMVN,
15796		reg: regInfo{
15797			inputs: []inputInfo{
15798				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15799				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
15800			},
15801			outputs: []outputInfo{
15802				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15803			},
15804		},
15805	},
15806	{
15807		name:   "ADCshiftLLreg",
15808		argLen: 4,
15809		asm:    arm.AADC,
15810		reg: regInfo{
15811			inputs: []inputInfo{
15812				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15813				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15814				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15815			},
15816			outputs: []outputInfo{
15817				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15818			},
15819		},
15820	},
15821	{
15822		name:   "ADCshiftRLreg",
15823		argLen: 4,
15824		asm:    arm.AADC,
15825		reg: regInfo{
15826			inputs: []inputInfo{
15827				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15828				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15829				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15830			},
15831			outputs: []outputInfo{
15832				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15833			},
15834		},
15835	},
15836	{
15837		name:   "ADCshiftRAreg",
15838		argLen: 4,
15839		asm:    arm.AADC,
15840		reg: regInfo{
15841			inputs: []inputInfo{
15842				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15843				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15844				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15845			},
15846			outputs: []outputInfo{
15847				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15848			},
15849		},
15850	},
15851	{
15852		name:   "SBCshiftLLreg",
15853		argLen: 4,
15854		asm:    arm.ASBC,
15855		reg: regInfo{
15856			inputs: []inputInfo{
15857				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15858				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15859				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15860			},
15861			outputs: []outputInfo{
15862				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15863			},
15864		},
15865	},
15866	{
15867		name:   "SBCshiftRLreg",
15868		argLen: 4,
15869		asm:    arm.ASBC,
15870		reg: regInfo{
15871			inputs: []inputInfo{
15872				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15873				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15874				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15875			},
15876			outputs: []outputInfo{
15877				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15878			},
15879		},
15880	},
15881	{
15882		name:   "SBCshiftRAreg",
15883		argLen: 4,
15884		asm:    arm.ASBC,
15885		reg: regInfo{
15886			inputs: []inputInfo{
15887				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15888				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15889				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15890			},
15891			outputs: []outputInfo{
15892				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15893			},
15894		},
15895	},
15896	{
15897		name:   "RSCshiftLLreg",
15898		argLen: 4,
15899		asm:    arm.ARSC,
15900		reg: regInfo{
15901			inputs: []inputInfo{
15902				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15903				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15904				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15905			},
15906			outputs: []outputInfo{
15907				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15908			},
15909		},
15910	},
15911	{
15912		name:   "RSCshiftRLreg",
15913		argLen: 4,
15914		asm:    arm.ARSC,
15915		reg: regInfo{
15916			inputs: []inputInfo{
15917				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15918				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15919				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15920			},
15921			outputs: []outputInfo{
15922				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15923			},
15924		},
15925	},
15926	{
15927		name:   "RSCshiftRAreg",
15928		argLen: 4,
15929		asm:    arm.ARSC,
15930		reg: regInfo{
15931			inputs: []inputInfo{
15932				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15933				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15934				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15935			},
15936			outputs: []outputInfo{
15937				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15938			},
15939		},
15940	},
15941	{
15942		name:   "ADDSshiftLLreg",
15943		argLen: 3,
15944		asm:    arm.AADD,
15945		reg: regInfo{
15946			inputs: []inputInfo{
15947				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15948				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15949				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15950			},
15951			outputs: []outputInfo{
15952				{1, 0},
15953				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15954			},
15955		},
15956	},
15957	{
15958		name:   "ADDSshiftRLreg",
15959		argLen: 3,
15960		asm:    arm.AADD,
15961		reg: regInfo{
15962			inputs: []inputInfo{
15963				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15964				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15965				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15966			},
15967			outputs: []outputInfo{
15968				{1, 0},
15969				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15970			},
15971		},
15972	},
15973	{
15974		name:   "ADDSshiftRAreg",
15975		argLen: 3,
15976		asm:    arm.AADD,
15977		reg: regInfo{
15978			inputs: []inputInfo{
15979				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15980				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15981				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15982			},
15983			outputs: []outputInfo{
15984				{1, 0},
15985				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15986			},
15987		},
15988	},
15989	{
15990		name:   "SUBSshiftLLreg",
15991		argLen: 3,
15992		asm:    arm.ASUB,
15993		reg: regInfo{
15994			inputs: []inputInfo{
15995				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15996				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15997				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
15998			},
15999			outputs: []outputInfo{
16000				{1, 0},
16001				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16002			},
16003		},
16004	},
16005	{
16006		name:   "SUBSshiftRLreg",
16007		argLen: 3,
16008		asm:    arm.ASUB,
16009		reg: regInfo{
16010			inputs: []inputInfo{
16011				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16012				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16013				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16014			},
16015			outputs: []outputInfo{
16016				{1, 0},
16017				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16018			},
16019		},
16020	},
16021	{
16022		name:   "SUBSshiftRAreg",
16023		argLen: 3,
16024		asm:    arm.ASUB,
16025		reg: regInfo{
16026			inputs: []inputInfo{
16027				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16028				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16029				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16030			},
16031			outputs: []outputInfo{
16032				{1, 0},
16033				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16034			},
16035		},
16036	},
16037	{
16038		name:   "RSBSshiftLLreg",
16039		argLen: 3,
16040		asm:    arm.ARSB,
16041		reg: regInfo{
16042			inputs: []inputInfo{
16043				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16044				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16045				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16046			},
16047			outputs: []outputInfo{
16048				{1, 0},
16049				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16050			},
16051		},
16052	},
16053	{
16054		name:   "RSBSshiftRLreg",
16055		argLen: 3,
16056		asm:    arm.ARSB,
16057		reg: regInfo{
16058			inputs: []inputInfo{
16059				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16060				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16061				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16062			},
16063			outputs: []outputInfo{
16064				{1, 0},
16065				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16066			},
16067		},
16068	},
16069	{
16070		name:   "RSBSshiftRAreg",
16071		argLen: 3,
16072		asm:    arm.ARSB,
16073		reg: regInfo{
16074			inputs: []inputInfo{
16075				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16076				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16077				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16078			},
16079			outputs: []outputInfo{
16080				{1, 0},
16081				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16082			},
16083		},
16084	},
16085	{
16086		name:   "CMP",
16087		argLen: 2,
16088		asm:    arm.ACMP,
16089		reg: regInfo{
16090			inputs: []inputInfo{
16091				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16092				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16093			},
16094		},
16095	},
16096	{
16097		name:    "CMPconst",
16098		auxType: auxInt32,
16099		argLen:  1,
16100		asm:     arm.ACMP,
16101		reg: regInfo{
16102			inputs: []inputInfo{
16103				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16104			},
16105		},
16106	},
16107	{
16108		name:        "CMN",
16109		argLen:      2,
16110		commutative: true,
16111		asm:         arm.ACMN,
16112		reg: regInfo{
16113			inputs: []inputInfo{
16114				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16115				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16116			},
16117		},
16118	},
16119	{
16120		name:    "CMNconst",
16121		auxType: auxInt32,
16122		argLen:  1,
16123		asm:     arm.ACMN,
16124		reg: regInfo{
16125			inputs: []inputInfo{
16126				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16127			},
16128		},
16129	},
16130	{
16131		name:        "TST",
16132		argLen:      2,
16133		commutative: true,
16134		asm:         arm.ATST,
16135		reg: regInfo{
16136			inputs: []inputInfo{
16137				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16138				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16139			},
16140		},
16141	},
16142	{
16143		name:    "TSTconst",
16144		auxType: auxInt32,
16145		argLen:  1,
16146		asm:     arm.ATST,
16147		reg: regInfo{
16148			inputs: []inputInfo{
16149				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16150			},
16151		},
16152	},
16153	{
16154		name:        "TEQ",
16155		argLen:      2,
16156		commutative: true,
16157		asm:         arm.ATEQ,
16158		reg: regInfo{
16159			inputs: []inputInfo{
16160				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16161				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16162			},
16163		},
16164	},
16165	{
16166		name:    "TEQconst",
16167		auxType: auxInt32,
16168		argLen:  1,
16169		asm:     arm.ATEQ,
16170		reg: regInfo{
16171			inputs: []inputInfo{
16172				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16173			},
16174		},
16175	},
16176	{
16177		name:   "CMPF",
16178		argLen: 2,
16179		asm:    arm.ACMPF,
16180		reg: regInfo{
16181			inputs: []inputInfo{
16182				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16183				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16184			},
16185		},
16186	},
16187	{
16188		name:   "CMPD",
16189		argLen: 2,
16190		asm:    arm.ACMPD,
16191		reg: regInfo{
16192			inputs: []inputInfo{
16193				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16194				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16195			},
16196		},
16197	},
16198	{
16199		name:    "CMPshiftLL",
16200		auxType: auxInt32,
16201		argLen:  2,
16202		asm:     arm.ACMP,
16203		reg: regInfo{
16204			inputs: []inputInfo{
16205				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16206				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16207			},
16208		},
16209	},
16210	{
16211		name:    "CMPshiftRL",
16212		auxType: auxInt32,
16213		argLen:  2,
16214		asm:     arm.ACMP,
16215		reg: regInfo{
16216			inputs: []inputInfo{
16217				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16218				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16219			},
16220		},
16221	},
16222	{
16223		name:    "CMPshiftRA",
16224		auxType: auxInt32,
16225		argLen:  2,
16226		asm:     arm.ACMP,
16227		reg: regInfo{
16228			inputs: []inputInfo{
16229				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16230				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16231			},
16232		},
16233	},
16234	{
16235		name:    "CMNshiftLL",
16236		auxType: auxInt32,
16237		argLen:  2,
16238		asm:     arm.ACMN,
16239		reg: regInfo{
16240			inputs: []inputInfo{
16241				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16242				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16243			},
16244		},
16245	},
16246	{
16247		name:    "CMNshiftRL",
16248		auxType: auxInt32,
16249		argLen:  2,
16250		asm:     arm.ACMN,
16251		reg: regInfo{
16252			inputs: []inputInfo{
16253				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16254				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16255			},
16256		},
16257	},
16258	{
16259		name:    "CMNshiftRA",
16260		auxType: auxInt32,
16261		argLen:  2,
16262		asm:     arm.ACMN,
16263		reg: regInfo{
16264			inputs: []inputInfo{
16265				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16266				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16267			},
16268		},
16269	},
16270	{
16271		name:    "TSTshiftLL",
16272		auxType: auxInt32,
16273		argLen:  2,
16274		asm:     arm.ATST,
16275		reg: regInfo{
16276			inputs: []inputInfo{
16277				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16278				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16279			},
16280		},
16281	},
16282	{
16283		name:    "TSTshiftRL",
16284		auxType: auxInt32,
16285		argLen:  2,
16286		asm:     arm.ATST,
16287		reg: regInfo{
16288			inputs: []inputInfo{
16289				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16290				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16291			},
16292		},
16293	},
16294	{
16295		name:    "TSTshiftRA",
16296		auxType: auxInt32,
16297		argLen:  2,
16298		asm:     arm.ATST,
16299		reg: regInfo{
16300			inputs: []inputInfo{
16301				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16302				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16303			},
16304		},
16305	},
16306	{
16307		name:    "TEQshiftLL",
16308		auxType: auxInt32,
16309		argLen:  2,
16310		asm:     arm.ATEQ,
16311		reg: regInfo{
16312			inputs: []inputInfo{
16313				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16314				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16315			},
16316		},
16317	},
16318	{
16319		name:    "TEQshiftRL",
16320		auxType: auxInt32,
16321		argLen:  2,
16322		asm:     arm.ATEQ,
16323		reg: regInfo{
16324			inputs: []inputInfo{
16325				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16326				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16327			},
16328		},
16329	},
16330	{
16331		name:    "TEQshiftRA",
16332		auxType: auxInt32,
16333		argLen:  2,
16334		asm:     arm.ATEQ,
16335		reg: regInfo{
16336			inputs: []inputInfo{
16337				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16338				{1, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16339			},
16340		},
16341	},
16342	{
16343		name:   "CMPshiftLLreg",
16344		argLen: 3,
16345		asm:    arm.ACMP,
16346		reg: regInfo{
16347			inputs: []inputInfo{
16348				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16349				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16350				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16351			},
16352		},
16353	},
16354	{
16355		name:   "CMPshiftRLreg",
16356		argLen: 3,
16357		asm:    arm.ACMP,
16358		reg: regInfo{
16359			inputs: []inputInfo{
16360				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16361				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16362				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16363			},
16364		},
16365	},
16366	{
16367		name:   "CMPshiftRAreg",
16368		argLen: 3,
16369		asm:    arm.ACMP,
16370		reg: regInfo{
16371			inputs: []inputInfo{
16372				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16373				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16374				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16375			},
16376		},
16377	},
16378	{
16379		name:   "CMNshiftLLreg",
16380		argLen: 3,
16381		asm:    arm.ACMN,
16382		reg: regInfo{
16383			inputs: []inputInfo{
16384				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16385				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16386				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16387			},
16388		},
16389	},
16390	{
16391		name:   "CMNshiftRLreg",
16392		argLen: 3,
16393		asm:    arm.ACMN,
16394		reg: regInfo{
16395			inputs: []inputInfo{
16396				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16397				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16398				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16399			},
16400		},
16401	},
16402	{
16403		name:   "CMNshiftRAreg",
16404		argLen: 3,
16405		asm:    arm.ACMN,
16406		reg: regInfo{
16407			inputs: []inputInfo{
16408				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16409				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16410				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16411			},
16412		},
16413	},
16414	{
16415		name:   "TSTshiftLLreg",
16416		argLen: 3,
16417		asm:    arm.ATST,
16418		reg: regInfo{
16419			inputs: []inputInfo{
16420				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16421				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16422				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16423			},
16424		},
16425	},
16426	{
16427		name:   "TSTshiftRLreg",
16428		argLen: 3,
16429		asm:    arm.ATST,
16430		reg: regInfo{
16431			inputs: []inputInfo{
16432				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16433				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16434				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16435			},
16436		},
16437	},
16438	{
16439		name:   "TSTshiftRAreg",
16440		argLen: 3,
16441		asm:    arm.ATST,
16442		reg: regInfo{
16443			inputs: []inputInfo{
16444				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16445				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16446				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16447			},
16448		},
16449	},
16450	{
16451		name:   "TEQshiftLLreg",
16452		argLen: 3,
16453		asm:    arm.ATEQ,
16454		reg: regInfo{
16455			inputs: []inputInfo{
16456				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16457				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16458				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16459			},
16460		},
16461	},
16462	{
16463		name:   "TEQshiftRLreg",
16464		argLen: 3,
16465		asm:    arm.ATEQ,
16466		reg: regInfo{
16467			inputs: []inputInfo{
16468				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16469				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16470				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16471			},
16472		},
16473	},
16474	{
16475		name:   "TEQshiftRAreg",
16476		argLen: 3,
16477		asm:    arm.ATEQ,
16478		reg: regInfo{
16479			inputs: []inputInfo{
16480				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16481				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16482				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16483			},
16484		},
16485	},
16486	{
16487		name:   "CMPF0",
16488		argLen: 1,
16489		asm:    arm.ACMPF,
16490		reg: regInfo{
16491			inputs: []inputInfo{
16492				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16493			},
16494		},
16495	},
16496	{
16497		name:   "CMPD0",
16498		argLen: 1,
16499		asm:    arm.ACMPD,
16500		reg: regInfo{
16501			inputs: []inputInfo{
16502				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16503			},
16504		},
16505	},
16506	{
16507		name:              "MOVWconst",
16508		auxType:           auxInt32,
16509		argLen:            0,
16510		rematerializeable: true,
16511		asm:               arm.AMOVW,
16512		reg: regInfo{
16513			outputs: []outputInfo{
16514				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16515			},
16516		},
16517	},
16518	{
16519		name:              "MOVFconst",
16520		auxType:           auxFloat64,
16521		argLen:            0,
16522		rematerializeable: true,
16523		asm:               arm.AMOVF,
16524		reg: regInfo{
16525			outputs: []outputInfo{
16526				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16527			},
16528		},
16529	},
16530	{
16531		name:              "MOVDconst",
16532		auxType:           auxFloat64,
16533		argLen:            0,
16534		rematerializeable: true,
16535		asm:               arm.AMOVD,
16536		reg: regInfo{
16537			outputs: []outputInfo{
16538				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16539			},
16540		},
16541	},
16542	{
16543		name:              "MOVWaddr",
16544		auxType:           auxSymOff,
16545		argLen:            1,
16546		rematerializeable: true,
16547		symEffect:         SymAddr,
16548		asm:               arm.AMOVW,
16549		reg: regInfo{
16550			inputs: []inputInfo{
16551				{0, 4294975488}, // SP SB
16552			},
16553			outputs: []outputInfo{
16554				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16555			},
16556		},
16557	},
16558	{
16559		name:           "MOVBload",
16560		auxType:        auxSymOff,
16561		argLen:         2,
16562		faultOnNilArg0: true,
16563		symEffect:      SymRead,
16564		asm:            arm.AMOVB,
16565		reg: regInfo{
16566			inputs: []inputInfo{
16567				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16568			},
16569			outputs: []outputInfo{
16570				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16571			},
16572		},
16573	},
16574	{
16575		name:           "MOVBUload",
16576		auxType:        auxSymOff,
16577		argLen:         2,
16578		faultOnNilArg0: true,
16579		symEffect:      SymRead,
16580		asm:            arm.AMOVBU,
16581		reg: regInfo{
16582			inputs: []inputInfo{
16583				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16584			},
16585			outputs: []outputInfo{
16586				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16587			},
16588		},
16589	},
16590	{
16591		name:           "MOVHload",
16592		auxType:        auxSymOff,
16593		argLen:         2,
16594		faultOnNilArg0: true,
16595		symEffect:      SymRead,
16596		asm:            arm.AMOVH,
16597		reg: regInfo{
16598			inputs: []inputInfo{
16599				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16600			},
16601			outputs: []outputInfo{
16602				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16603			},
16604		},
16605	},
16606	{
16607		name:           "MOVHUload",
16608		auxType:        auxSymOff,
16609		argLen:         2,
16610		faultOnNilArg0: true,
16611		symEffect:      SymRead,
16612		asm:            arm.AMOVHU,
16613		reg: regInfo{
16614			inputs: []inputInfo{
16615				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16616			},
16617			outputs: []outputInfo{
16618				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16619			},
16620		},
16621	},
16622	{
16623		name:           "MOVWload",
16624		auxType:        auxSymOff,
16625		argLen:         2,
16626		faultOnNilArg0: true,
16627		symEffect:      SymRead,
16628		asm:            arm.AMOVW,
16629		reg: regInfo{
16630			inputs: []inputInfo{
16631				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16632			},
16633			outputs: []outputInfo{
16634				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16635			},
16636		},
16637	},
16638	{
16639		name:           "MOVFload",
16640		auxType:        auxSymOff,
16641		argLen:         2,
16642		faultOnNilArg0: true,
16643		symEffect:      SymRead,
16644		asm:            arm.AMOVF,
16645		reg: regInfo{
16646			inputs: []inputInfo{
16647				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16648			},
16649			outputs: []outputInfo{
16650				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16651			},
16652		},
16653	},
16654	{
16655		name:           "MOVDload",
16656		auxType:        auxSymOff,
16657		argLen:         2,
16658		faultOnNilArg0: true,
16659		symEffect:      SymRead,
16660		asm:            arm.AMOVD,
16661		reg: regInfo{
16662			inputs: []inputInfo{
16663				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16664			},
16665			outputs: []outputInfo{
16666				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16667			},
16668		},
16669	},
16670	{
16671		name:           "MOVBstore",
16672		auxType:        auxSymOff,
16673		argLen:         3,
16674		faultOnNilArg0: true,
16675		symEffect:      SymWrite,
16676		asm:            arm.AMOVB,
16677		reg: regInfo{
16678			inputs: []inputInfo{
16679				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16680				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16681			},
16682		},
16683	},
16684	{
16685		name:           "MOVHstore",
16686		auxType:        auxSymOff,
16687		argLen:         3,
16688		faultOnNilArg0: true,
16689		symEffect:      SymWrite,
16690		asm:            arm.AMOVH,
16691		reg: regInfo{
16692			inputs: []inputInfo{
16693				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16694				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16695			},
16696		},
16697	},
16698	{
16699		name:           "MOVWstore",
16700		auxType:        auxSymOff,
16701		argLen:         3,
16702		faultOnNilArg0: true,
16703		symEffect:      SymWrite,
16704		asm:            arm.AMOVW,
16705		reg: regInfo{
16706			inputs: []inputInfo{
16707				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16708				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16709			},
16710		},
16711	},
16712	{
16713		name:           "MOVFstore",
16714		auxType:        auxSymOff,
16715		argLen:         3,
16716		faultOnNilArg0: true,
16717		symEffect:      SymWrite,
16718		asm:            arm.AMOVF,
16719		reg: regInfo{
16720			inputs: []inputInfo{
16721				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16722				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16723			},
16724		},
16725	},
16726	{
16727		name:           "MOVDstore",
16728		auxType:        auxSymOff,
16729		argLen:         3,
16730		faultOnNilArg0: true,
16731		symEffect:      SymWrite,
16732		asm:            arm.AMOVD,
16733		reg: regInfo{
16734			inputs: []inputInfo{
16735				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16736				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
16737			},
16738		},
16739	},
16740	{
16741		name:   "MOVWloadidx",
16742		argLen: 3,
16743		asm:    arm.AMOVW,
16744		reg: regInfo{
16745			inputs: []inputInfo{
16746				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16747				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16748			},
16749			outputs: []outputInfo{
16750				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16751			},
16752		},
16753	},
16754	{
16755		name:    "MOVWloadshiftLL",
16756		auxType: auxInt32,
16757		argLen:  3,
16758		asm:     arm.AMOVW,
16759		reg: regInfo{
16760			inputs: []inputInfo{
16761				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16762				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16763			},
16764			outputs: []outputInfo{
16765				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16766			},
16767		},
16768	},
16769	{
16770		name:    "MOVWloadshiftRL",
16771		auxType: auxInt32,
16772		argLen:  3,
16773		asm:     arm.AMOVW,
16774		reg: regInfo{
16775			inputs: []inputInfo{
16776				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16777				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16778			},
16779			outputs: []outputInfo{
16780				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16781			},
16782		},
16783	},
16784	{
16785		name:    "MOVWloadshiftRA",
16786		auxType: auxInt32,
16787		argLen:  3,
16788		asm:     arm.AMOVW,
16789		reg: regInfo{
16790			inputs: []inputInfo{
16791				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16792				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16793			},
16794			outputs: []outputInfo{
16795				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16796			},
16797		},
16798	},
16799	{
16800		name:   "MOVBUloadidx",
16801		argLen: 3,
16802		asm:    arm.AMOVBU,
16803		reg: regInfo{
16804			inputs: []inputInfo{
16805				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16806				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16807			},
16808			outputs: []outputInfo{
16809				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16810			},
16811		},
16812	},
16813	{
16814		name:   "MOVBloadidx",
16815		argLen: 3,
16816		asm:    arm.AMOVB,
16817		reg: regInfo{
16818			inputs: []inputInfo{
16819				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16820				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16821			},
16822			outputs: []outputInfo{
16823				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16824			},
16825		},
16826	},
16827	{
16828		name:   "MOVHUloadidx",
16829		argLen: 3,
16830		asm:    arm.AMOVHU,
16831		reg: regInfo{
16832			inputs: []inputInfo{
16833				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16834				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16835			},
16836			outputs: []outputInfo{
16837				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16838			},
16839		},
16840	},
16841	{
16842		name:   "MOVHloadidx",
16843		argLen: 3,
16844		asm:    arm.AMOVH,
16845		reg: regInfo{
16846			inputs: []inputInfo{
16847				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16848				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16849			},
16850			outputs: []outputInfo{
16851				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16852			},
16853		},
16854	},
16855	{
16856		name:   "MOVWstoreidx",
16857		argLen: 4,
16858		asm:    arm.AMOVW,
16859		reg: regInfo{
16860			inputs: []inputInfo{
16861				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16862				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16863				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16864			},
16865		},
16866	},
16867	{
16868		name:    "MOVWstoreshiftLL",
16869		auxType: auxInt32,
16870		argLen:  4,
16871		asm:     arm.AMOVW,
16872		reg: regInfo{
16873			inputs: []inputInfo{
16874				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16875				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16876				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16877			},
16878		},
16879	},
16880	{
16881		name:    "MOVWstoreshiftRL",
16882		auxType: auxInt32,
16883		argLen:  4,
16884		asm:     arm.AMOVW,
16885		reg: regInfo{
16886			inputs: []inputInfo{
16887				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16888				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16889				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16890			},
16891		},
16892	},
16893	{
16894		name:    "MOVWstoreshiftRA",
16895		auxType: auxInt32,
16896		argLen:  4,
16897		asm:     arm.AMOVW,
16898		reg: regInfo{
16899			inputs: []inputInfo{
16900				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16901				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16902				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16903			},
16904		},
16905	},
16906	{
16907		name:   "MOVBstoreidx",
16908		argLen: 4,
16909		asm:    arm.AMOVB,
16910		reg: regInfo{
16911			inputs: []inputInfo{
16912				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16913				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16914				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16915			},
16916		},
16917	},
16918	{
16919		name:   "MOVHstoreidx",
16920		argLen: 4,
16921		asm:    arm.AMOVH,
16922		reg: regInfo{
16923			inputs: []inputInfo{
16924				{1, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16925				{2, 22527},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16926				{0, 4294998015}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 SP R14 SB
16927			},
16928		},
16929	},
16930	{
16931		name:   "MOVBreg",
16932		argLen: 1,
16933		asm:    arm.AMOVBS,
16934		reg: regInfo{
16935			inputs: []inputInfo{
16936				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16937			},
16938			outputs: []outputInfo{
16939				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16940			},
16941		},
16942	},
16943	{
16944		name:   "MOVBUreg",
16945		argLen: 1,
16946		asm:    arm.AMOVBU,
16947		reg: regInfo{
16948			inputs: []inputInfo{
16949				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16950			},
16951			outputs: []outputInfo{
16952				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16953			},
16954		},
16955	},
16956	{
16957		name:   "MOVHreg",
16958		argLen: 1,
16959		asm:    arm.AMOVHS,
16960		reg: regInfo{
16961			inputs: []inputInfo{
16962				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16963			},
16964			outputs: []outputInfo{
16965				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16966			},
16967		},
16968	},
16969	{
16970		name:   "MOVHUreg",
16971		argLen: 1,
16972		asm:    arm.AMOVHU,
16973		reg: regInfo{
16974			inputs: []inputInfo{
16975				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16976			},
16977			outputs: []outputInfo{
16978				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16979			},
16980		},
16981	},
16982	{
16983		name:   "MOVWreg",
16984		argLen: 1,
16985		asm:    arm.AMOVW,
16986		reg: regInfo{
16987			inputs: []inputInfo{
16988				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
16989			},
16990			outputs: []outputInfo{
16991				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
16992			},
16993		},
16994	},
16995	{
16996		name:         "MOVWnop",
16997		argLen:       1,
16998		resultInArg0: true,
16999		reg: regInfo{
17000			inputs: []inputInfo{
17001				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17002			},
17003			outputs: []outputInfo{
17004				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17005			},
17006		},
17007	},
17008	{
17009		name:   "MOVWF",
17010		argLen: 1,
17011		asm:    arm.AMOVWF,
17012		reg: regInfo{
17013			inputs: []inputInfo{
17014				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17015			},
17016			clobbers: 2147483648, // F15
17017			outputs: []outputInfo{
17018				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17019			},
17020		},
17021	},
17022	{
17023		name:   "MOVWD",
17024		argLen: 1,
17025		asm:    arm.AMOVWD,
17026		reg: regInfo{
17027			inputs: []inputInfo{
17028				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17029			},
17030			clobbers: 2147483648, // F15
17031			outputs: []outputInfo{
17032				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17033			},
17034		},
17035	},
17036	{
17037		name:   "MOVWUF",
17038		argLen: 1,
17039		asm:    arm.AMOVWF,
17040		reg: regInfo{
17041			inputs: []inputInfo{
17042				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17043			},
17044			clobbers: 2147483648, // F15
17045			outputs: []outputInfo{
17046				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17047			},
17048		},
17049	},
17050	{
17051		name:   "MOVWUD",
17052		argLen: 1,
17053		asm:    arm.AMOVWD,
17054		reg: regInfo{
17055			inputs: []inputInfo{
17056				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17057			},
17058			clobbers: 2147483648, // F15
17059			outputs: []outputInfo{
17060				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17061			},
17062		},
17063	},
17064	{
17065		name:   "MOVFW",
17066		argLen: 1,
17067		asm:    arm.AMOVFW,
17068		reg: regInfo{
17069			inputs: []inputInfo{
17070				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17071			},
17072			clobbers: 2147483648, // F15
17073			outputs: []outputInfo{
17074				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17075			},
17076		},
17077	},
17078	{
17079		name:   "MOVDW",
17080		argLen: 1,
17081		asm:    arm.AMOVDW,
17082		reg: regInfo{
17083			inputs: []inputInfo{
17084				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17085			},
17086			clobbers: 2147483648, // F15
17087			outputs: []outputInfo{
17088				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17089			},
17090		},
17091	},
17092	{
17093		name:   "MOVFWU",
17094		argLen: 1,
17095		asm:    arm.AMOVFW,
17096		reg: regInfo{
17097			inputs: []inputInfo{
17098				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17099			},
17100			clobbers: 2147483648, // F15
17101			outputs: []outputInfo{
17102				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17103			},
17104		},
17105	},
17106	{
17107		name:   "MOVDWU",
17108		argLen: 1,
17109		asm:    arm.AMOVDW,
17110		reg: regInfo{
17111			inputs: []inputInfo{
17112				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17113			},
17114			clobbers: 2147483648, // F15
17115			outputs: []outputInfo{
17116				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17117			},
17118		},
17119	},
17120	{
17121		name:   "MOVFD",
17122		argLen: 1,
17123		asm:    arm.AMOVFD,
17124		reg: regInfo{
17125			inputs: []inputInfo{
17126				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17127			},
17128			outputs: []outputInfo{
17129				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17130			},
17131		},
17132	},
17133	{
17134		name:   "MOVDF",
17135		argLen: 1,
17136		asm:    arm.AMOVDF,
17137		reg: regInfo{
17138			inputs: []inputInfo{
17139				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17140			},
17141			outputs: []outputInfo{
17142				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17143			},
17144		},
17145	},
17146	{
17147		name:         "CMOVWHSconst",
17148		auxType:      auxInt32,
17149		argLen:       2,
17150		resultInArg0: true,
17151		asm:          arm.AMOVW,
17152		reg: regInfo{
17153			inputs: []inputInfo{
17154				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17155			},
17156			outputs: []outputInfo{
17157				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17158			},
17159		},
17160	},
17161	{
17162		name:         "CMOVWLSconst",
17163		auxType:      auxInt32,
17164		argLen:       2,
17165		resultInArg0: true,
17166		asm:          arm.AMOVW,
17167		reg: regInfo{
17168			inputs: []inputInfo{
17169				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17170			},
17171			outputs: []outputInfo{
17172				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17173			},
17174		},
17175	},
17176	{
17177		name:   "SRAcond",
17178		argLen: 3,
17179		asm:    arm.ASRA,
17180		reg: regInfo{
17181			inputs: []inputInfo{
17182				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17183				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17184			},
17185			outputs: []outputInfo{
17186				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17187			},
17188		},
17189	},
17190	{
17191		name:         "CALLstatic",
17192		auxType:      auxCallOff,
17193		argLen:       1,
17194		clobberFlags: true,
17195		call:         true,
17196		reg: regInfo{
17197			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17198		},
17199	},
17200	{
17201		name:         "CALLtail",
17202		auxType:      auxCallOff,
17203		argLen:       1,
17204		clobberFlags: true,
17205		call:         true,
17206		tailCall:     true,
17207		reg: regInfo{
17208			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17209		},
17210	},
17211	{
17212		name:         "CALLclosure",
17213		auxType:      auxCallOff,
17214		argLen:       3,
17215		clobberFlags: true,
17216		call:         true,
17217		reg: regInfo{
17218			inputs: []inputInfo{
17219				{1, 128},   // R7
17220				{0, 29695}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 SP R14
17221			},
17222			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17223		},
17224	},
17225	{
17226		name:         "CALLinter",
17227		auxType:      auxCallOff,
17228		argLen:       2,
17229		clobberFlags: true,
17230		call:         true,
17231		reg: regInfo{
17232			inputs: []inputInfo{
17233				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17234			},
17235			clobbers: 4294924287, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17236		},
17237	},
17238	{
17239		name:           "LoweredNilCheck",
17240		argLen:         2,
17241		nilCheck:       true,
17242		faultOnNilArg0: true,
17243		reg: regInfo{
17244			inputs: []inputInfo{
17245				{0, 22527}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 g R12 R14
17246			},
17247		},
17248	},
17249	{
17250		name:   "Equal",
17251		argLen: 1,
17252		reg: regInfo{
17253			outputs: []outputInfo{
17254				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17255			},
17256		},
17257	},
17258	{
17259		name:   "NotEqual",
17260		argLen: 1,
17261		reg: regInfo{
17262			outputs: []outputInfo{
17263				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17264			},
17265		},
17266	},
17267	{
17268		name:   "LessThan",
17269		argLen: 1,
17270		reg: regInfo{
17271			outputs: []outputInfo{
17272				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17273			},
17274		},
17275	},
17276	{
17277		name:   "LessEqual",
17278		argLen: 1,
17279		reg: regInfo{
17280			outputs: []outputInfo{
17281				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17282			},
17283		},
17284	},
17285	{
17286		name:   "GreaterThan",
17287		argLen: 1,
17288		reg: regInfo{
17289			outputs: []outputInfo{
17290				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17291			},
17292		},
17293	},
17294	{
17295		name:   "GreaterEqual",
17296		argLen: 1,
17297		reg: regInfo{
17298			outputs: []outputInfo{
17299				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17300			},
17301		},
17302	},
17303	{
17304		name:   "LessThanU",
17305		argLen: 1,
17306		reg: regInfo{
17307			outputs: []outputInfo{
17308				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17309			},
17310		},
17311	},
17312	{
17313		name:   "LessEqualU",
17314		argLen: 1,
17315		reg: regInfo{
17316			outputs: []outputInfo{
17317				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17318			},
17319		},
17320	},
17321	{
17322		name:   "GreaterThanU",
17323		argLen: 1,
17324		reg: regInfo{
17325			outputs: []outputInfo{
17326				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17327			},
17328		},
17329	},
17330	{
17331		name:   "GreaterEqualU",
17332		argLen: 1,
17333		reg: regInfo{
17334			outputs: []outputInfo{
17335				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17336			},
17337		},
17338	},
17339	{
17340		name:           "DUFFZERO",
17341		auxType:        auxInt64,
17342		argLen:         3,
17343		faultOnNilArg0: true,
17344		reg: regInfo{
17345			inputs: []inputInfo{
17346				{0, 2}, // R1
17347				{1, 1}, // R0
17348			},
17349			clobbers: 20482, // R1 R12 R14
17350		},
17351	},
17352	{
17353		name:           "DUFFCOPY",
17354		auxType:        auxInt64,
17355		argLen:         3,
17356		faultOnNilArg0: true,
17357		faultOnNilArg1: true,
17358		reg: regInfo{
17359			inputs: []inputInfo{
17360				{0, 4}, // R2
17361				{1, 2}, // R1
17362			},
17363			clobbers: 20487, // R0 R1 R2 R12 R14
17364		},
17365	},
17366	{
17367		name:           "LoweredZero",
17368		auxType:        auxInt64,
17369		argLen:         4,
17370		clobberFlags:   true,
17371		faultOnNilArg0: true,
17372		reg: regInfo{
17373			inputs: []inputInfo{
17374				{0, 2},     // R1
17375				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17376				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17377			},
17378			clobbers: 2, // R1
17379		},
17380	},
17381	{
17382		name:           "LoweredMove",
17383		auxType:        auxInt64,
17384		argLen:         4,
17385		clobberFlags:   true,
17386		faultOnNilArg0: true,
17387		faultOnNilArg1: true,
17388		reg: regInfo{
17389			inputs: []inputInfo{
17390				{0, 4},     // R2
17391				{1, 2},     // R1
17392				{2, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17393			},
17394			clobbers: 6, // R1 R2
17395		},
17396	},
17397	{
17398		name:      "LoweredGetClosurePtr",
17399		argLen:    0,
17400		zeroWidth: true,
17401		reg: regInfo{
17402			outputs: []outputInfo{
17403				{0, 128}, // R7
17404			},
17405		},
17406	},
17407	{
17408		name:              "LoweredGetCallerSP",
17409		argLen:            0,
17410		rematerializeable: true,
17411		reg: regInfo{
17412			outputs: []outputInfo{
17413				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17414			},
17415		},
17416	},
17417	{
17418		name:              "LoweredGetCallerPC",
17419		argLen:            0,
17420		rematerializeable: true,
17421		reg: regInfo{
17422			outputs: []outputInfo{
17423				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
17424			},
17425		},
17426	},
17427	{
17428		name:    "LoweredPanicBoundsA",
17429		auxType: auxInt64,
17430		argLen:  3,
17431		call:    true,
17432		reg: regInfo{
17433			inputs: []inputInfo{
17434				{0, 4}, // R2
17435				{1, 8}, // R3
17436			},
17437		},
17438	},
17439	{
17440		name:    "LoweredPanicBoundsB",
17441		auxType: auxInt64,
17442		argLen:  3,
17443		call:    true,
17444		reg: regInfo{
17445			inputs: []inputInfo{
17446				{0, 2}, // R1
17447				{1, 4}, // R2
17448			},
17449		},
17450	},
17451	{
17452		name:    "LoweredPanicBoundsC",
17453		auxType: auxInt64,
17454		argLen:  3,
17455		call:    true,
17456		reg: regInfo{
17457			inputs: []inputInfo{
17458				{0, 1}, // R0
17459				{1, 2}, // R1
17460			},
17461		},
17462	},
17463	{
17464		name:    "LoweredPanicExtendA",
17465		auxType: auxInt64,
17466		argLen:  4,
17467		call:    true,
17468		reg: regInfo{
17469			inputs: []inputInfo{
17470				{0, 16}, // R4
17471				{1, 4},  // R2
17472				{2, 8},  // R3
17473			},
17474		},
17475	},
17476	{
17477		name:    "LoweredPanicExtendB",
17478		auxType: auxInt64,
17479		argLen:  4,
17480		call:    true,
17481		reg: regInfo{
17482			inputs: []inputInfo{
17483				{0, 16}, // R4
17484				{1, 2},  // R1
17485				{2, 4},  // R2
17486			},
17487		},
17488	},
17489	{
17490		name:    "LoweredPanicExtendC",
17491		auxType: auxInt64,
17492		argLen:  4,
17493		call:    true,
17494		reg: regInfo{
17495			inputs: []inputInfo{
17496				{0, 16}, // R4
17497				{1, 1},  // R0
17498				{2, 2},  // R1
17499			},
17500		},
17501	},
17502	{
17503		name:    "FlagConstant",
17504		auxType: auxFlagConstant,
17505		argLen:  0,
17506		reg:     regInfo{},
17507	},
17508	{
17509		name:   "InvertFlags",
17510		argLen: 1,
17511		reg:    regInfo{},
17512	},
17513	{
17514		name:         "LoweredWB",
17515		auxType:      auxSym,
17516		argLen:       3,
17517		clobberFlags: true,
17518		symEffect:    SymNone,
17519		reg: regInfo{
17520			inputs: []inputInfo{
17521				{0, 4}, // R2
17522				{1, 8}, // R3
17523			},
17524			clobbers: 4294922240, // R12 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
17525		},
17526	},
17527
17528	{
17529		name:        "ADCSflags",
17530		argLen:      3,
17531		commutative: true,
17532		asm:         arm64.AADCS,
17533		reg: regInfo{
17534			inputs: []inputInfo{
17535				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17536				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17537			},
17538			outputs: []outputInfo{
17539				{1, 0},
17540				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17541			},
17542		},
17543	},
17544	{
17545		name:   "ADCzerocarry",
17546		argLen: 1,
17547		asm:    arm64.AADC,
17548		reg: regInfo{
17549			outputs: []outputInfo{
17550				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17551			},
17552		},
17553	},
17554	{
17555		name:        "ADD",
17556		argLen:      2,
17557		commutative: true,
17558		asm:         arm64.AADD,
17559		reg: regInfo{
17560			inputs: []inputInfo{
17561				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17562				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17563			},
17564			outputs: []outputInfo{
17565				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17566			},
17567		},
17568	},
17569	{
17570		name:    "ADDconst",
17571		auxType: auxInt64,
17572		argLen:  1,
17573		asm:     arm64.AADD,
17574		reg: regInfo{
17575			inputs: []inputInfo{
17576				{0, 1878786047}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP
17577			},
17578			outputs: []outputInfo{
17579				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17580			},
17581		},
17582	},
17583	{
17584		name:    "ADDSconstflags",
17585		auxType: auxInt64,
17586		argLen:  1,
17587		asm:     arm64.AADDS,
17588		reg: regInfo{
17589			inputs: []inputInfo{
17590				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17591			},
17592			outputs: []outputInfo{
17593				{1, 0},
17594				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17595			},
17596		},
17597	},
17598	{
17599		name:        "ADDSflags",
17600		argLen:      2,
17601		commutative: true,
17602		asm:         arm64.AADDS,
17603		reg: regInfo{
17604			inputs: []inputInfo{
17605				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17606				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17607			},
17608			outputs: []outputInfo{
17609				{1, 0},
17610				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17611			},
17612		},
17613	},
17614	{
17615		name:   "SUB",
17616		argLen: 2,
17617		asm:    arm64.ASUB,
17618		reg: regInfo{
17619			inputs: []inputInfo{
17620				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17621				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17622			},
17623			outputs: []outputInfo{
17624				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17625			},
17626		},
17627	},
17628	{
17629		name:    "SUBconst",
17630		auxType: auxInt64,
17631		argLen:  1,
17632		asm:     arm64.ASUB,
17633		reg: regInfo{
17634			inputs: []inputInfo{
17635				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17636			},
17637			outputs: []outputInfo{
17638				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17639			},
17640		},
17641	},
17642	{
17643		name:   "SBCSflags",
17644		argLen: 3,
17645		asm:    arm64.ASBCS,
17646		reg: regInfo{
17647			inputs: []inputInfo{
17648				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17649				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17650			},
17651			outputs: []outputInfo{
17652				{1, 0},
17653				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17654			},
17655		},
17656	},
17657	{
17658		name:   "SUBSflags",
17659		argLen: 2,
17660		asm:    arm64.ASUBS,
17661		reg: regInfo{
17662			inputs: []inputInfo{
17663				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17664				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17665			},
17666			outputs: []outputInfo{
17667				{1, 0},
17668				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17669			},
17670		},
17671	},
17672	{
17673		name:        "MUL",
17674		argLen:      2,
17675		commutative: true,
17676		asm:         arm64.AMUL,
17677		reg: regInfo{
17678			inputs: []inputInfo{
17679				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17680				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17681			},
17682			outputs: []outputInfo{
17683				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17684			},
17685		},
17686	},
17687	{
17688		name:        "MULW",
17689		argLen:      2,
17690		commutative: true,
17691		asm:         arm64.AMULW,
17692		reg: regInfo{
17693			inputs: []inputInfo{
17694				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17695				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17696			},
17697			outputs: []outputInfo{
17698				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17699			},
17700		},
17701	},
17702	{
17703		name:        "MNEG",
17704		argLen:      2,
17705		commutative: true,
17706		asm:         arm64.AMNEG,
17707		reg: regInfo{
17708			inputs: []inputInfo{
17709				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17710				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17711			},
17712			outputs: []outputInfo{
17713				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17714			},
17715		},
17716	},
17717	{
17718		name:        "MNEGW",
17719		argLen:      2,
17720		commutative: true,
17721		asm:         arm64.AMNEGW,
17722		reg: regInfo{
17723			inputs: []inputInfo{
17724				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17725				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17726			},
17727			outputs: []outputInfo{
17728				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17729			},
17730		},
17731	},
17732	{
17733		name:        "MULH",
17734		argLen:      2,
17735		commutative: true,
17736		asm:         arm64.ASMULH,
17737		reg: regInfo{
17738			inputs: []inputInfo{
17739				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17740				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17741			},
17742			outputs: []outputInfo{
17743				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17744			},
17745		},
17746	},
17747	{
17748		name:        "UMULH",
17749		argLen:      2,
17750		commutative: true,
17751		asm:         arm64.AUMULH,
17752		reg: regInfo{
17753			inputs: []inputInfo{
17754				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17755				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17756			},
17757			outputs: []outputInfo{
17758				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17759			},
17760		},
17761	},
17762	{
17763		name:        "MULL",
17764		argLen:      2,
17765		commutative: true,
17766		asm:         arm64.ASMULL,
17767		reg: regInfo{
17768			inputs: []inputInfo{
17769				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17770				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17771			},
17772			outputs: []outputInfo{
17773				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17774			},
17775		},
17776	},
17777	{
17778		name:        "UMULL",
17779		argLen:      2,
17780		commutative: true,
17781		asm:         arm64.AUMULL,
17782		reg: regInfo{
17783			inputs: []inputInfo{
17784				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17785				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17786			},
17787			outputs: []outputInfo{
17788				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17789			},
17790		},
17791	},
17792	{
17793		name:   "DIV",
17794		argLen: 2,
17795		asm:    arm64.ASDIV,
17796		reg: regInfo{
17797			inputs: []inputInfo{
17798				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17799				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17800			},
17801			outputs: []outputInfo{
17802				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17803			},
17804		},
17805	},
17806	{
17807		name:   "UDIV",
17808		argLen: 2,
17809		asm:    arm64.AUDIV,
17810		reg: regInfo{
17811			inputs: []inputInfo{
17812				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17813				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17814			},
17815			outputs: []outputInfo{
17816				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17817			},
17818		},
17819	},
17820	{
17821		name:   "DIVW",
17822		argLen: 2,
17823		asm:    arm64.ASDIVW,
17824		reg: regInfo{
17825			inputs: []inputInfo{
17826				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17827				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17828			},
17829			outputs: []outputInfo{
17830				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17831			},
17832		},
17833	},
17834	{
17835		name:   "UDIVW",
17836		argLen: 2,
17837		asm:    arm64.AUDIVW,
17838		reg: regInfo{
17839			inputs: []inputInfo{
17840				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17841				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17842			},
17843			outputs: []outputInfo{
17844				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17845			},
17846		},
17847	},
17848	{
17849		name:   "MOD",
17850		argLen: 2,
17851		asm:    arm64.AREM,
17852		reg: regInfo{
17853			inputs: []inputInfo{
17854				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17855				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17856			},
17857			outputs: []outputInfo{
17858				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17859			},
17860		},
17861	},
17862	{
17863		name:   "UMOD",
17864		argLen: 2,
17865		asm:    arm64.AUREM,
17866		reg: regInfo{
17867			inputs: []inputInfo{
17868				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17869				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17870			},
17871			outputs: []outputInfo{
17872				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17873			},
17874		},
17875	},
17876	{
17877		name:   "MODW",
17878		argLen: 2,
17879		asm:    arm64.AREMW,
17880		reg: regInfo{
17881			inputs: []inputInfo{
17882				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17883				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17884			},
17885			outputs: []outputInfo{
17886				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17887			},
17888		},
17889	},
17890	{
17891		name:   "UMODW",
17892		argLen: 2,
17893		asm:    arm64.AUREMW,
17894		reg: regInfo{
17895			inputs: []inputInfo{
17896				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17897				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
17898			},
17899			outputs: []outputInfo{
17900				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
17901			},
17902		},
17903	},
17904	{
17905		name:        "FADDS",
17906		argLen:      2,
17907		commutative: true,
17908		asm:         arm64.AFADDS,
17909		reg: regInfo{
17910			inputs: []inputInfo{
17911				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17912				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17913			},
17914			outputs: []outputInfo{
17915				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17916			},
17917		},
17918	},
17919	{
17920		name:        "FADDD",
17921		argLen:      2,
17922		commutative: true,
17923		asm:         arm64.AFADDD,
17924		reg: regInfo{
17925			inputs: []inputInfo{
17926				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17927				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17928			},
17929			outputs: []outputInfo{
17930				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17931			},
17932		},
17933	},
17934	{
17935		name:   "FSUBS",
17936		argLen: 2,
17937		asm:    arm64.AFSUBS,
17938		reg: regInfo{
17939			inputs: []inputInfo{
17940				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17941				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17942			},
17943			outputs: []outputInfo{
17944				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17945			},
17946		},
17947	},
17948	{
17949		name:   "FSUBD",
17950		argLen: 2,
17951		asm:    arm64.AFSUBD,
17952		reg: regInfo{
17953			inputs: []inputInfo{
17954				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17955				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17956			},
17957			outputs: []outputInfo{
17958				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17959			},
17960		},
17961	},
17962	{
17963		name:        "FMULS",
17964		argLen:      2,
17965		commutative: true,
17966		asm:         arm64.AFMULS,
17967		reg: regInfo{
17968			inputs: []inputInfo{
17969				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17970				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17971			},
17972			outputs: []outputInfo{
17973				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17974			},
17975		},
17976	},
17977	{
17978		name:        "FMULD",
17979		argLen:      2,
17980		commutative: true,
17981		asm:         arm64.AFMULD,
17982		reg: regInfo{
17983			inputs: []inputInfo{
17984				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17985				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17986			},
17987			outputs: []outputInfo{
17988				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
17989			},
17990		},
17991	},
17992	{
17993		name:        "FNMULS",
17994		argLen:      2,
17995		commutative: true,
17996		asm:         arm64.AFNMULS,
17997		reg: regInfo{
17998			inputs: []inputInfo{
17999				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18000				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18001			},
18002			outputs: []outputInfo{
18003				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18004			},
18005		},
18006	},
18007	{
18008		name:        "FNMULD",
18009		argLen:      2,
18010		commutative: true,
18011		asm:         arm64.AFNMULD,
18012		reg: regInfo{
18013			inputs: []inputInfo{
18014				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18015				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18016			},
18017			outputs: []outputInfo{
18018				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18019			},
18020		},
18021	},
18022	{
18023		name:   "FDIVS",
18024		argLen: 2,
18025		asm:    arm64.AFDIVS,
18026		reg: regInfo{
18027			inputs: []inputInfo{
18028				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18029				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18030			},
18031			outputs: []outputInfo{
18032				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18033			},
18034		},
18035	},
18036	{
18037		name:   "FDIVD",
18038		argLen: 2,
18039		asm:    arm64.AFDIVD,
18040		reg: regInfo{
18041			inputs: []inputInfo{
18042				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18043				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18044			},
18045			outputs: []outputInfo{
18046				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18047			},
18048		},
18049	},
18050	{
18051		name:        "AND",
18052		argLen:      2,
18053		commutative: true,
18054		asm:         arm64.AAND,
18055		reg: regInfo{
18056			inputs: []inputInfo{
18057				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18058				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18059			},
18060			outputs: []outputInfo{
18061				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18062			},
18063		},
18064	},
18065	{
18066		name:    "ANDconst",
18067		auxType: auxInt64,
18068		argLen:  1,
18069		asm:     arm64.AAND,
18070		reg: regInfo{
18071			inputs: []inputInfo{
18072				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18073			},
18074			outputs: []outputInfo{
18075				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18076			},
18077		},
18078	},
18079	{
18080		name:        "OR",
18081		argLen:      2,
18082		commutative: true,
18083		asm:         arm64.AORR,
18084		reg: regInfo{
18085			inputs: []inputInfo{
18086				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18087				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18088			},
18089			outputs: []outputInfo{
18090				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18091			},
18092		},
18093	},
18094	{
18095		name:    "ORconst",
18096		auxType: auxInt64,
18097		argLen:  1,
18098		asm:     arm64.AORR,
18099		reg: regInfo{
18100			inputs: []inputInfo{
18101				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18102			},
18103			outputs: []outputInfo{
18104				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18105			},
18106		},
18107	},
18108	{
18109		name:        "XOR",
18110		argLen:      2,
18111		commutative: true,
18112		asm:         arm64.AEOR,
18113		reg: regInfo{
18114			inputs: []inputInfo{
18115				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18116				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18117			},
18118			outputs: []outputInfo{
18119				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18120			},
18121		},
18122	},
18123	{
18124		name:    "XORconst",
18125		auxType: auxInt64,
18126		argLen:  1,
18127		asm:     arm64.AEOR,
18128		reg: regInfo{
18129			inputs: []inputInfo{
18130				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18131			},
18132			outputs: []outputInfo{
18133				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18134			},
18135		},
18136	},
18137	{
18138		name:   "BIC",
18139		argLen: 2,
18140		asm:    arm64.ABIC,
18141		reg: regInfo{
18142			inputs: []inputInfo{
18143				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18144				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18145			},
18146			outputs: []outputInfo{
18147				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18148			},
18149		},
18150	},
18151	{
18152		name:   "EON",
18153		argLen: 2,
18154		asm:    arm64.AEON,
18155		reg: regInfo{
18156			inputs: []inputInfo{
18157				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18158				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18159			},
18160			outputs: []outputInfo{
18161				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18162			},
18163		},
18164	},
18165	{
18166		name:   "ORN",
18167		argLen: 2,
18168		asm:    arm64.AORN,
18169		reg: regInfo{
18170			inputs: []inputInfo{
18171				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18172				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18173			},
18174			outputs: []outputInfo{
18175				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18176			},
18177		},
18178	},
18179	{
18180		name:            "LoweredMuluhilo",
18181		argLen:          2,
18182		resultNotInArgs: true,
18183		reg: regInfo{
18184			inputs: []inputInfo{
18185				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18186				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18187			},
18188			outputs: []outputInfo{
18189				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18190				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18191			},
18192		},
18193	},
18194	{
18195		name:   "MVN",
18196		argLen: 1,
18197		asm:    arm64.AMVN,
18198		reg: regInfo{
18199			inputs: []inputInfo{
18200				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18201			},
18202			outputs: []outputInfo{
18203				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18204			},
18205		},
18206	},
18207	{
18208		name:   "NEG",
18209		argLen: 1,
18210		asm:    arm64.ANEG,
18211		reg: regInfo{
18212			inputs: []inputInfo{
18213				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18214			},
18215			outputs: []outputInfo{
18216				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18217			},
18218		},
18219	},
18220	{
18221		name:   "NEGSflags",
18222		argLen: 1,
18223		asm:    arm64.ANEGS,
18224		reg: regInfo{
18225			inputs: []inputInfo{
18226				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18227			},
18228			outputs: []outputInfo{
18229				{1, 0},
18230				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18231			},
18232		},
18233	},
18234	{
18235		name:   "NGCzerocarry",
18236		argLen: 1,
18237		asm:    arm64.ANGC,
18238		reg: regInfo{
18239			outputs: []outputInfo{
18240				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18241			},
18242		},
18243	},
18244	{
18245		name:   "FABSD",
18246		argLen: 1,
18247		asm:    arm64.AFABSD,
18248		reg: regInfo{
18249			inputs: []inputInfo{
18250				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18251			},
18252			outputs: []outputInfo{
18253				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18254			},
18255		},
18256	},
18257	{
18258		name:   "FNEGS",
18259		argLen: 1,
18260		asm:    arm64.AFNEGS,
18261		reg: regInfo{
18262			inputs: []inputInfo{
18263				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18264			},
18265			outputs: []outputInfo{
18266				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18267			},
18268		},
18269	},
18270	{
18271		name:   "FNEGD",
18272		argLen: 1,
18273		asm:    arm64.AFNEGD,
18274		reg: regInfo{
18275			inputs: []inputInfo{
18276				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18277			},
18278			outputs: []outputInfo{
18279				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18280			},
18281		},
18282	},
18283	{
18284		name:   "FSQRTD",
18285		argLen: 1,
18286		asm:    arm64.AFSQRTD,
18287		reg: regInfo{
18288			inputs: []inputInfo{
18289				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18290			},
18291			outputs: []outputInfo{
18292				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18293			},
18294		},
18295	},
18296	{
18297		name:   "FSQRTS",
18298		argLen: 1,
18299		asm:    arm64.AFSQRTS,
18300		reg: regInfo{
18301			inputs: []inputInfo{
18302				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18303			},
18304			outputs: []outputInfo{
18305				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18306			},
18307		},
18308	},
18309	{
18310		name:   "REV",
18311		argLen: 1,
18312		asm:    arm64.AREV,
18313		reg: regInfo{
18314			inputs: []inputInfo{
18315				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18316			},
18317			outputs: []outputInfo{
18318				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18319			},
18320		},
18321	},
18322	{
18323		name:   "REVW",
18324		argLen: 1,
18325		asm:    arm64.AREVW,
18326		reg: regInfo{
18327			inputs: []inputInfo{
18328				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18329			},
18330			outputs: []outputInfo{
18331				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18332			},
18333		},
18334	},
18335	{
18336		name:   "REV16",
18337		argLen: 1,
18338		asm:    arm64.AREV16,
18339		reg: regInfo{
18340			inputs: []inputInfo{
18341				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18342			},
18343			outputs: []outputInfo{
18344				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18345			},
18346		},
18347	},
18348	{
18349		name:   "REV16W",
18350		argLen: 1,
18351		asm:    arm64.AREV16W,
18352		reg: regInfo{
18353			inputs: []inputInfo{
18354				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18355			},
18356			outputs: []outputInfo{
18357				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18358			},
18359		},
18360	},
18361	{
18362		name:   "RBIT",
18363		argLen: 1,
18364		asm:    arm64.ARBIT,
18365		reg: regInfo{
18366			inputs: []inputInfo{
18367				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18368			},
18369			outputs: []outputInfo{
18370				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18371			},
18372		},
18373	},
18374	{
18375		name:   "RBITW",
18376		argLen: 1,
18377		asm:    arm64.ARBITW,
18378		reg: regInfo{
18379			inputs: []inputInfo{
18380				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18381			},
18382			outputs: []outputInfo{
18383				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18384			},
18385		},
18386	},
18387	{
18388		name:   "CLZ",
18389		argLen: 1,
18390		asm:    arm64.ACLZ,
18391		reg: regInfo{
18392			inputs: []inputInfo{
18393				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18394			},
18395			outputs: []outputInfo{
18396				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18397			},
18398		},
18399	},
18400	{
18401		name:   "CLZW",
18402		argLen: 1,
18403		asm:    arm64.ACLZW,
18404		reg: regInfo{
18405			inputs: []inputInfo{
18406				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18407			},
18408			outputs: []outputInfo{
18409				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18410			},
18411		},
18412	},
18413	{
18414		name:   "VCNT",
18415		argLen: 1,
18416		asm:    arm64.AVCNT,
18417		reg: regInfo{
18418			inputs: []inputInfo{
18419				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18420			},
18421			outputs: []outputInfo{
18422				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18423			},
18424		},
18425	},
18426	{
18427		name:   "VUADDLV",
18428		argLen: 1,
18429		asm:    arm64.AVUADDLV,
18430		reg: regInfo{
18431			inputs: []inputInfo{
18432				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18433			},
18434			outputs: []outputInfo{
18435				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18436			},
18437		},
18438	},
18439	{
18440		name:         "LoweredRound32F",
18441		argLen:       1,
18442		resultInArg0: true,
18443		zeroWidth:    true,
18444		reg: regInfo{
18445			inputs: []inputInfo{
18446				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18447			},
18448			outputs: []outputInfo{
18449				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18450			},
18451		},
18452	},
18453	{
18454		name:         "LoweredRound64F",
18455		argLen:       1,
18456		resultInArg0: true,
18457		zeroWidth:    true,
18458		reg: regInfo{
18459			inputs: []inputInfo{
18460				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18461			},
18462			outputs: []outputInfo{
18463				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18464			},
18465		},
18466	},
18467	{
18468		name:   "FMADDS",
18469		argLen: 3,
18470		asm:    arm64.AFMADDS,
18471		reg: regInfo{
18472			inputs: []inputInfo{
18473				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18474				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18475				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18476			},
18477			outputs: []outputInfo{
18478				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18479			},
18480		},
18481	},
18482	{
18483		name:   "FMADDD",
18484		argLen: 3,
18485		asm:    arm64.AFMADDD,
18486		reg: regInfo{
18487			inputs: []inputInfo{
18488				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18489				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18490				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18491			},
18492			outputs: []outputInfo{
18493				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18494			},
18495		},
18496	},
18497	{
18498		name:   "FNMADDS",
18499		argLen: 3,
18500		asm:    arm64.AFNMADDS,
18501		reg: regInfo{
18502			inputs: []inputInfo{
18503				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18504				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18505				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18506			},
18507			outputs: []outputInfo{
18508				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18509			},
18510		},
18511	},
18512	{
18513		name:   "FNMADDD",
18514		argLen: 3,
18515		asm:    arm64.AFNMADDD,
18516		reg: regInfo{
18517			inputs: []inputInfo{
18518				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18519				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18520				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18521			},
18522			outputs: []outputInfo{
18523				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18524			},
18525		},
18526	},
18527	{
18528		name:   "FMSUBS",
18529		argLen: 3,
18530		asm:    arm64.AFMSUBS,
18531		reg: regInfo{
18532			inputs: []inputInfo{
18533				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18534				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18535				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18536			},
18537			outputs: []outputInfo{
18538				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18539			},
18540		},
18541	},
18542	{
18543		name:   "FMSUBD",
18544		argLen: 3,
18545		asm:    arm64.AFMSUBD,
18546		reg: regInfo{
18547			inputs: []inputInfo{
18548				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18549				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18550				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18551			},
18552			outputs: []outputInfo{
18553				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18554			},
18555		},
18556	},
18557	{
18558		name:   "FNMSUBS",
18559		argLen: 3,
18560		asm:    arm64.AFNMSUBS,
18561		reg: regInfo{
18562			inputs: []inputInfo{
18563				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18564				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18565				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18566			},
18567			outputs: []outputInfo{
18568				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18569			},
18570		},
18571	},
18572	{
18573		name:   "FNMSUBD",
18574		argLen: 3,
18575		asm:    arm64.AFNMSUBD,
18576		reg: regInfo{
18577			inputs: []inputInfo{
18578				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18579				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18580				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18581			},
18582			outputs: []outputInfo{
18583				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18584			},
18585		},
18586	},
18587	{
18588		name:   "MADD",
18589		argLen: 3,
18590		asm:    arm64.AMADD,
18591		reg: regInfo{
18592			inputs: []inputInfo{
18593				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18594				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18595				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18596			},
18597			outputs: []outputInfo{
18598				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18599			},
18600		},
18601	},
18602	{
18603		name:   "MADDW",
18604		argLen: 3,
18605		asm:    arm64.AMADDW,
18606		reg: regInfo{
18607			inputs: []inputInfo{
18608				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18609				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18610				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18611			},
18612			outputs: []outputInfo{
18613				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18614			},
18615		},
18616	},
18617	{
18618		name:   "MSUB",
18619		argLen: 3,
18620		asm:    arm64.AMSUB,
18621		reg: regInfo{
18622			inputs: []inputInfo{
18623				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18624				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18625				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18626			},
18627			outputs: []outputInfo{
18628				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18629			},
18630		},
18631	},
18632	{
18633		name:   "MSUBW",
18634		argLen: 3,
18635		asm:    arm64.AMSUBW,
18636		reg: regInfo{
18637			inputs: []inputInfo{
18638				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18639				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18640				{2, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18641			},
18642			outputs: []outputInfo{
18643				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18644			},
18645		},
18646	},
18647	{
18648		name:   "SLL",
18649		argLen: 2,
18650		asm:    arm64.ALSL,
18651		reg: regInfo{
18652			inputs: []inputInfo{
18653				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18654				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18655			},
18656			outputs: []outputInfo{
18657				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18658			},
18659		},
18660	},
18661	{
18662		name:    "SLLconst",
18663		auxType: auxInt64,
18664		argLen:  1,
18665		asm:     arm64.ALSL,
18666		reg: regInfo{
18667			inputs: []inputInfo{
18668				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18669			},
18670			outputs: []outputInfo{
18671				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18672			},
18673		},
18674	},
18675	{
18676		name:   "SRL",
18677		argLen: 2,
18678		asm:    arm64.ALSR,
18679		reg: regInfo{
18680			inputs: []inputInfo{
18681				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18682				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18683			},
18684			outputs: []outputInfo{
18685				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18686			},
18687		},
18688	},
18689	{
18690		name:    "SRLconst",
18691		auxType: auxInt64,
18692		argLen:  1,
18693		asm:     arm64.ALSR,
18694		reg: regInfo{
18695			inputs: []inputInfo{
18696				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18697			},
18698			outputs: []outputInfo{
18699				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18700			},
18701		},
18702	},
18703	{
18704		name:   "SRA",
18705		argLen: 2,
18706		asm:    arm64.AASR,
18707		reg: regInfo{
18708			inputs: []inputInfo{
18709				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18710				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18711			},
18712			outputs: []outputInfo{
18713				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18714			},
18715		},
18716	},
18717	{
18718		name:    "SRAconst",
18719		auxType: auxInt64,
18720		argLen:  1,
18721		asm:     arm64.AASR,
18722		reg: regInfo{
18723			inputs: []inputInfo{
18724				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18725			},
18726			outputs: []outputInfo{
18727				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18728			},
18729		},
18730	},
18731	{
18732		name:   "ROR",
18733		argLen: 2,
18734		asm:    arm64.AROR,
18735		reg: regInfo{
18736			inputs: []inputInfo{
18737				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18738				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18739			},
18740			outputs: []outputInfo{
18741				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18742			},
18743		},
18744	},
18745	{
18746		name:   "RORW",
18747		argLen: 2,
18748		asm:    arm64.ARORW,
18749		reg: regInfo{
18750			inputs: []inputInfo{
18751				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18752				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18753			},
18754			outputs: []outputInfo{
18755				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18756			},
18757		},
18758	},
18759	{
18760		name:    "RORconst",
18761		auxType: auxInt64,
18762		argLen:  1,
18763		asm:     arm64.AROR,
18764		reg: regInfo{
18765			inputs: []inputInfo{
18766				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18767			},
18768			outputs: []outputInfo{
18769				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18770			},
18771		},
18772	},
18773	{
18774		name:    "RORWconst",
18775		auxType: auxInt64,
18776		argLen:  1,
18777		asm:     arm64.ARORW,
18778		reg: regInfo{
18779			inputs: []inputInfo{
18780				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18781			},
18782			outputs: []outputInfo{
18783				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18784			},
18785		},
18786	},
18787	{
18788		name:    "EXTRconst",
18789		auxType: auxInt64,
18790		argLen:  2,
18791		asm:     arm64.AEXTR,
18792		reg: regInfo{
18793			inputs: []inputInfo{
18794				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18795				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18796			},
18797			outputs: []outputInfo{
18798				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18799			},
18800		},
18801	},
18802	{
18803		name:    "EXTRWconst",
18804		auxType: auxInt64,
18805		argLen:  2,
18806		asm:     arm64.AEXTRW,
18807		reg: regInfo{
18808			inputs: []inputInfo{
18809				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18810				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18811			},
18812			outputs: []outputInfo{
18813				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
18814			},
18815		},
18816	},
18817	{
18818		name:   "CMP",
18819		argLen: 2,
18820		asm:    arm64.ACMP,
18821		reg: regInfo{
18822			inputs: []inputInfo{
18823				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18824				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18825			},
18826		},
18827	},
18828	{
18829		name:    "CMPconst",
18830		auxType: auxInt64,
18831		argLen:  1,
18832		asm:     arm64.ACMP,
18833		reg: regInfo{
18834			inputs: []inputInfo{
18835				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18836			},
18837		},
18838	},
18839	{
18840		name:   "CMPW",
18841		argLen: 2,
18842		asm:    arm64.ACMPW,
18843		reg: regInfo{
18844			inputs: []inputInfo{
18845				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18846				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18847			},
18848		},
18849	},
18850	{
18851		name:    "CMPWconst",
18852		auxType: auxInt32,
18853		argLen:  1,
18854		asm:     arm64.ACMPW,
18855		reg: regInfo{
18856			inputs: []inputInfo{
18857				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18858			},
18859		},
18860	},
18861	{
18862		name:        "CMN",
18863		argLen:      2,
18864		commutative: true,
18865		asm:         arm64.ACMN,
18866		reg: regInfo{
18867			inputs: []inputInfo{
18868				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18869				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18870			},
18871		},
18872	},
18873	{
18874		name:    "CMNconst",
18875		auxType: auxInt64,
18876		argLen:  1,
18877		asm:     arm64.ACMN,
18878		reg: regInfo{
18879			inputs: []inputInfo{
18880				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18881			},
18882		},
18883	},
18884	{
18885		name:        "CMNW",
18886		argLen:      2,
18887		commutative: true,
18888		asm:         arm64.ACMNW,
18889		reg: regInfo{
18890			inputs: []inputInfo{
18891				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18892				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18893			},
18894		},
18895	},
18896	{
18897		name:    "CMNWconst",
18898		auxType: auxInt32,
18899		argLen:  1,
18900		asm:     arm64.ACMNW,
18901		reg: regInfo{
18902			inputs: []inputInfo{
18903				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18904			},
18905		},
18906	},
18907	{
18908		name:        "TST",
18909		argLen:      2,
18910		commutative: true,
18911		asm:         arm64.ATST,
18912		reg: regInfo{
18913			inputs: []inputInfo{
18914				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18915				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18916			},
18917		},
18918	},
18919	{
18920		name:    "TSTconst",
18921		auxType: auxInt64,
18922		argLen:  1,
18923		asm:     arm64.ATST,
18924		reg: regInfo{
18925			inputs: []inputInfo{
18926				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18927			},
18928		},
18929	},
18930	{
18931		name:        "TSTW",
18932		argLen:      2,
18933		commutative: true,
18934		asm:         arm64.ATSTW,
18935		reg: regInfo{
18936			inputs: []inputInfo{
18937				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18938				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18939			},
18940		},
18941	},
18942	{
18943		name:    "TSTWconst",
18944		auxType: auxInt32,
18945		argLen:  1,
18946		asm:     arm64.ATSTW,
18947		reg: regInfo{
18948			inputs: []inputInfo{
18949				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
18950			},
18951		},
18952	},
18953	{
18954		name:   "FCMPS",
18955		argLen: 2,
18956		asm:    arm64.AFCMPS,
18957		reg: regInfo{
18958			inputs: []inputInfo{
18959				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18960				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18961			},
18962		},
18963	},
18964	{
18965		name:   "FCMPD",
18966		argLen: 2,
18967		asm:    arm64.AFCMPD,
18968		reg: regInfo{
18969			inputs: []inputInfo{
18970				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18971				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18972			},
18973		},
18974	},
18975	{
18976		name:   "FCMPS0",
18977		argLen: 1,
18978		asm:    arm64.AFCMPS,
18979		reg: regInfo{
18980			inputs: []inputInfo{
18981				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18982			},
18983		},
18984	},
18985	{
18986		name:   "FCMPD0",
18987		argLen: 1,
18988		asm:    arm64.AFCMPD,
18989		reg: regInfo{
18990			inputs: []inputInfo{
18991				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
18992			},
18993		},
18994	},
18995	{
18996		name:    "MVNshiftLL",
18997		auxType: auxInt64,
18998		argLen:  1,
18999		asm:     arm64.AMVN,
19000		reg: regInfo{
19001			inputs: []inputInfo{
19002				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19003			},
19004			outputs: []outputInfo{
19005				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19006			},
19007		},
19008	},
19009	{
19010		name:    "MVNshiftRL",
19011		auxType: auxInt64,
19012		argLen:  1,
19013		asm:     arm64.AMVN,
19014		reg: regInfo{
19015			inputs: []inputInfo{
19016				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19017			},
19018			outputs: []outputInfo{
19019				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19020			},
19021		},
19022	},
19023	{
19024		name:    "MVNshiftRA",
19025		auxType: auxInt64,
19026		argLen:  1,
19027		asm:     arm64.AMVN,
19028		reg: regInfo{
19029			inputs: []inputInfo{
19030				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19031			},
19032			outputs: []outputInfo{
19033				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19034			},
19035		},
19036	},
19037	{
19038		name:    "MVNshiftRO",
19039		auxType: auxInt64,
19040		argLen:  1,
19041		asm:     arm64.AMVN,
19042		reg: regInfo{
19043			inputs: []inputInfo{
19044				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19045			},
19046			outputs: []outputInfo{
19047				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19048			},
19049		},
19050	},
19051	{
19052		name:    "NEGshiftLL",
19053		auxType: auxInt64,
19054		argLen:  1,
19055		asm:     arm64.ANEG,
19056		reg: regInfo{
19057			inputs: []inputInfo{
19058				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19059			},
19060			outputs: []outputInfo{
19061				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19062			},
19063		},
19064	},
19065	{
19066		name:    "NEGshiftRL",
19067		auxType: auxInt64,
19068		argLen:  1,
19069		asm:     arm64.ANEG,
19070		reg: regInfo{
19071			inputs: []inputInfo{
19072				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19073			},
19074			outputs: []outputInfo{
19075				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19076			},
19077		},
19078	},
19079	{
19080		name:    "NEGshiftRA",
19081		auxType: auxInt64,
19082		argLen:  1,
19083		asm:     arm64.ANEG,
19084		reg: regInfo{
19085			inputs: []inputInfo{
19086				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19087			},
19088			outputs: []outputInfo{
19089				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19090			},
19091		},
19092	},
19093	{
19094		name:    "ADDshiftLL",
19095		auxType: auxInt64,
19096		argLen:  2,
19097		asm:     arm64.AADD,
19098		reg: regInfo{
19099			inputs: []inputInfo{
19100				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19101				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19102			},
19103			outputs: []outputInfo{
19104				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19105			},
19106		},
19107	},
19108	{
19109		name:    "ADDshiftRL",
19110		auxType: auxInt64,
19111		argLen:  2,
19112		asm:     arm64.AADD,
19113		reg: regInfo{
19114			inputs: []inputInfo{
19115				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19116				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19117			},
19118			outputs: []outputInfo{
19119				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19120			},
19121		},
19122	},
19123	{
19124		name:    "ADDshiftRA",
19125		auxType: auxInt64,
19126		argLen:  2,
19127		asm:     arm64.AADD,
19128		reg: regInfo{
19129			inputs: []inputInfo{
19130				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19131				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19132			},
19133			outputs: []outputInfo{
19134				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19135			},
19136		},
19137	},
19138	{
19139		name:    "SUBshiftLL",
19140		auxType: auxInt64,
19141		argLen:  2,
19142		asm:     arm64.ASUB,
19143		reg: regInfo{
19144			inputs: []inputInfo{
19145				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19146				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19147			},
19148			outputs: []outputInfo{
19149				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19150			},
19151		},
19152	},
19153	{
19154		name:    "SUBshiftRL",
19155		auxType: auxInt64,
19156		argLen:  2,
19157		asm:     arm64.ASUB,
19158		reg: regInfo{
19159			inputs: []inputInfo{
19160				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19161				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19162			},
19163			outputs: []outputInfo{
19164				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19165			},
19166		},
19167	},
19168	{
19169		name:    "SUBshiftRA",
19170		auxType: auxInt64,
19171		argLen:  2,
19172		asm:     arm64.ASUB,
19173		reg: regInfo{
19174			inputs: []inputInfo{
19175				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19176				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19177			},
19178			outputs: []outputInfo{
19179				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19180			},
19181		},
19182	},
19183	{
19184		name:    "ANDshiftLL",
19185		auxType: auxInt64,
19186		argLen:  2,
19187		asm:     arm64.AAND,
19188		reg: regInfo{
19189			inputs: []inputInfo{
19190				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19191				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19192			},
19193			outputs: []outputInfo{
19194				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19195			},
19196		},
19197	},
19198	{
19199		name:    "ANDshiftRL",
19200		auxType: auxInt64,
19201		argLen:  2,
19202		asm:     arm64.AAND,
19203		reg: regInfo{
19204			inputs: []inputInfo{
19205				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19206				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19207			},
19208			outputs: []outputInfo{
19209				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19210			},
19211		},
19212	},
19213	{
19214		name:    "ANDshiftRA",
19215		auxType: auxInt64,
19216		argLen:  2,
19217		asm:     arm64.AAND,
19218		reg: regInfo{
19219			inputs: []inputInfo{
19220				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19221				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19222			},
19223			outputs: []outputInfo{
19224				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19225			},
19226		},
19227	},
19228	{
19229		name:    "ANDshiftRO",
19230		auxType: auxInt64,
19231		argLen:  2,
19232		asm:     arm64.AAND,
19233		reg: regInfo{
19234			inputs: []inputInfo{
19235				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19236				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19237			},
19238			outputs: []outputInfo{
19239				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19240			},
19241		},
19242	},
19243	{
19244		name:    "ORshiftLL",
19245		auxType: auxInt64,
19246		argLen:  2,
19247		asm:     arm64.AORR,
19248		reg: regInfo{
19249			inputs: []inputInfo{
19250				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19251				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19252			},
19253			outputs: []outputInfo{
19254				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19255			},
19256		},
19257	},
19258	{
19259		name:    "ORshiftRL",
19260		auxType: auxInt64,
19261		argLen:  2,
19262		asm:     arm64.AORR,
19263		reg: regInfo{
19264			inputs: []inputInfo{
19265				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19266				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19267			},
19268			outputs: []outputInfo{
19269				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19270			},
19271		},
19272	},
19273	{
19274		name:    "ORshiftRA",
19275		auxType: auxInt64,
19276		argLen:  2,
19277		asm:     arm64.AORR,
19278		reg: regInfo{
19279			inputs: []inputInfo{
19280				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19281				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19282			},
19283			outputs: []outputInfo{
19284				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19285			},
19286		},
19287	},
19288	{
19289		name:    "ORshiftRO",
19290		auxType: auxInt64,
19291		argLen:  2,
19292		asm:     arm64.AORR,
19293		reg: regInfo{
19294			inputs: []inputInfo{
19295				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19296				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19297			},
19298			outputs: []outputInfo{
19299				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19300			},
19301		},
19302	},
19303	{
19304		name:    "XORshiftLL",
19305		auxType: auxInt64,
19306		argLen:  2,
19307		asm:     arm64.AEOR,
19308		reg: regInfo{
19309			inputs: []inputInfo{
19310				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19311				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19312			},
19313			outputs: []outputInfo{
19314				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19315			},
19316		},
19317	},
19318	{
19319		name:    "XORshiftRL",
19320		auxType: auxInt64,
19321		argLen:  2,
19322		asm:     arm64.AEOR,
19323		reg: regInfo{
19324			inputs: []inputInfo{
19325				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19326				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19327			},
19328			outputs: []outputInfo{
19329				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19330			},
19331		},
19332	},
19333	{
19334		name:    "XORshiftRA",
19335		auxType: auxInt64,
19336		argLen:  2,
19337		asm:     arm64.AEOR,
19338		reg: regInfo{
19339			inputs: []inputInfo{
19340				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19341				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19342			},
19343			outputs: []outputInfo{
19344				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19345			},
19346		},
19347	},
19348	{
19349		name:    "XORshiftRO",
19350		auxType: auxInt64,
19351		argLen:  2,
19352		asm:     arm64.AEOR,
19353		reg: regInfo{
19354			inputs: []inputInfo{
19355				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19356				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19357			},
19358			outputs: []outputInfo{
19359				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19360			},
19361		},
19362	},
19363	{
19364		name:    "BICshiftLL",
19365		auxType: auxInt64,
19366		argLen:  2,
19367		asm:     arm64.ABIC,
19368		reg: regInfo{
19369			inputs: []inputInfo{
19370				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19371				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19372			},
19373			outputs: []outputInfo{
19374				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19375			},
19376		},
19377	},
19378	{
19379		name:    "BICshiftRL",
19380		auxType: auxInt64,
19381		argLen:  2,
19382		asm:     arm64.ABIC,
19383		reg: regInfo{
19384			inputs: []inputInfo{
19385				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19386				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19387			},
19388			outputs: []outputInfo{
19389				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19390			},
19391		},
19392	},
19393	{
19394		name:    "BICshiftRA",
19395		auxType: auxInt64,
19396		argLen:  2,
19397		asm:     arm64.ABIC,
19398		reg: regInfo{
19399			inputs: []inputInfo{
19400				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19401				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19402			},
19403			outputs: []outputInfo{
19404				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19405			},
19406		},
19407	},
19408	{
19409		name:    "BICshiftRO",
19410		auxType: auxInt64,
19411		argLen:  2,
19412		asm:     arm64.ABIC,
19413		reg: regInfo{
19414			inputs: []inputInfo{
19415				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19416				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19417			},
19418			outputs: []outputInfo{
19419				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19420			},
19421		},
19422	},
19423	{
19424		name:    "EONshiftLL",
19425		auxType: auxInt64,
19426		argLen:  2,
19427		asm:     arm64.AEON,
19428		reg: regInfo{
19429			inputs: []inputInfo{
19430				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19431				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19432			},
19433			outputs: []outputInfo{
19434				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19435			},
19436		},
19437	},
19438	{
19439		name:    "EONshiftRL",
19440		auxType: auxInt64,
19441		argLen:  2,
19442		asm:     arm64.AEON,
19443		reg: regInfo{
19444			inputs: []inputInfo{
19445				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19446				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19447			},
19448			outputs: []outputInfo{
19449				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19450			},
19451		},
19452	},
19453	{
19454		name:    "EONshiftRA",
19455		auxType: auxInt64,
19456		argLen:  2,
19457		asm:     arm64.AEON,
19458		reg: regInfo{
19459			inputs: []inputInfo{
19460				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19461				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19462			},
19463			outputs: []outputInfo{
19464				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19465			},
19466		},
19467	},
19468	{
19469		name:    "EONshiftRO",
19470		auxType: auxInt64,
19471		argLen:  2,
19472		asm:     arm64.AEON,
19473		reg: regInfo{
19474			inputs: []inputInfo{
19475				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19476				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19477			},
19478			outputs: []outputInfo{
19479				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19480			},
19481		},
19482	},
19483	{
19484		name:    "ORNshiftLL",
19485		auxType: auxInt64,
19486		argLen:  2,
19487		asm:     arm64.AORN,
19488		reg: regInfo{
19489			inputs: []inputInfo{
19490				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19491				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19492			},
19493			outputs: []outputInfo{
19494				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19495			},
19496		},
19497	},
19498	{
19499		name:    "ORNshiftRL",
19500		auxType: auxInt64,
19501		argLen:  2,
19502		asm:     arm64.AORN,
19503		reg: regInfo{
19504			inputs: []inputInfo{
19505				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19506				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19507			},
19508			outputs: []outputInfo{
19509				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19510			},
19511		},
19512	},
19513	{
19514		name:    "ORNshiftRA",
19515		auxType: auxInt64,
19516		argLen:  2,
19517		asm:     arm64.AORN,
19518		reg: regInfo{
19519			inputs: []inputInfo{
19520				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19521				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19522			},
19523			outputs: []outputInfo{
19524				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19525			},
19526		},
19527	},
19528	{
19529		name:    "ORNshiftRO",
19530		auxType: auxInt64,
19531		argLen:  2,
19532		asm:     arm64.AORN,
19533		reg: regInfo{
19534			inputs: []inputInfo{
19535				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19536				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19537			},
19538			outputs: []outputInfo{
19539				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19540			},
19541		},
19542	},
19543	{
19544		name:    "CMPshiftLL",
19545		auxType: auxInt64,
19546		argLen:  2,
19547		asm:     arm64.ACMP,
19548		reg: regInfo{
19549			inputs: []inputInfo{
19550				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19551				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19552			},
19553		},
19554	},
19555	{
19556		name:    "CMPshiftRL",
19557		auxType: auxInt64,
19558		argLen:  2,
19559		asm:     arm64.ACMP,
19560		reg: regInfo{
19561			inputs: []inputInfo{
19562				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19563				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19564			},
19565		},
19566	},
19567	{
19568		name:    "CMPshiftRA",
19569		auxType: auxInt64,
19570		argLen:  2,
19571		asm:     arm64.ACMP,
19572		reg: regInfo{
19573			inputs: []inputInfo{
19574				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19575				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19576			},
19577		},
19578	},
19579	{
19580		name:    "CMNshiftLL",
19581		auxType: auxInt64,
19582		argLen:  2,
19583		asm:     arm64.ACMN,
19584		reg: regInfo{
19585			inputs: []inputInfo{
19586				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19587				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19588			},
19589		},
19590	},
19591	{
19592		name:    "CMNshiftRL",
19593		auxType: auxInt64,
19594		argLen:  2,
19595		asm:     arm64.ACMN,
19596		reg: regInfo{
19597			inputs: []inputInfo{
19598				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19599				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19600			},
19601		},
19602	},
19603	{
19604		name:    "CMNshiftRA",
19605		auxType: auxInt64,
19606		argLen:  2,
19607		asm:     arm64.ACMN,
19608		reg: regInfo{
19609			inputs: []inputInfo{
19610				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19611				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19612			},
19613		},
19614	},
19615	{
19616		name:    "TSTshiftLL",
19617		auxType: auxInt64,
19618		argLen:  2,
19619		asm:     arm64.ATST,
19620		reg: regInfo{
19621			inputs: []inputInfo{
19622				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19623				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19624			},
19625		},
19626	},
19627	{
19628		name:    "TSTshiftRL",
19629		auxType: auxInt64,
19630		argLen:  2,
19631		asm:     arm64.ATST,
19632		reg: regInfo{
19633			inputs: []inputInfo{
19634				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19635				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19636			},
19637		},
19638	},
19639	{
19640		name:    "TSTshiftRA",
19641		auxType: auxInt64,
19642		argLen:  2,
19643		asm:     arm64.ATST,
19644		reg: regInfo{
19645			inputs: []inputInfo{
19646				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19647				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19648			},
19649		},
19650	},
19651	{
19652		name:    "TSTshiftRO",
19653		auxType: auxInt64,
19654		argLen:  2,
19655		asm:     arm64.ATST,
19656		reg: regInfo{
19657			inputs: []inputInfo{
19658				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19659				{1, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19660			},
19661		},
19662	},
19663	{
19664		name:         "BFI",
19665		auxType:      auxARM64BitField,
19666		argLen:       2,
19667		resultInArg0: true,
19668		asm:          arm64.ABFI,
19669		reg: regInfo{
19670			inputs: []inputInfo{
19671				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19672				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19673			},
19674			outputs: []outputInfo{
19675				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19676			},
19677		},
19678	},
19679	{
19680		name:         "BFXIL",
19681		auxType:      auxARM64BitField,
19682		argLen:       2,
19683		resultInArg0: true,
19684		asm:          arm64.ABFXIL,
19685		reg: regInfo{
19686			inputs: []inputInfo{
19687				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19688				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19689			},
19690			outputs: []outputInfo{
19691				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19692			},
19693		},
19694	},
19695	{
19696		name:    "SBFIZ",
19697		auxType: auxARM64BitField,
19698		argLen:  1,
19699		asm:     arm64.ASBFIZ,
19700		reg: regInfo{
19701			inputs: []inputInfo{
19702				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19703			},
19704			outputs: []outputInfo{
19705				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19706			},
19707		},
19708	},
19709	{
19710		name:    "SBFX",
19711		auxType: auxARM64BitField,
19712		argLen:  1,
19713		asm:     arm64.ASBFX,
19714		reg: regInfo{
19715			inputs: []inputInfo{
19716				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19717			},
19718			outputs: []outputInfo{
19719				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19720			},
19721		},
19722	},
19723	{
19724		name:    "UBFIZ",
19725		auxType: auxARM64BitField,
19726		argLen:  1,
19727		asm:     arm64.AUBFIZ,
19728		reg: regInfo{
19729			inputs: []inputInfo{
19730				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19731			},
19732			outputs: []outputInfo{
19733				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19734			},
19735		},
19736	},
19737	{
19738		name:    "UBFX",
19739		auxType: auxARM64BitField,
19740		argLen:  1,
19741		asm:     arm64.AUBFX,
19742		reg: regInfo{
19743			inputs: []inputInfo{
19744				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19745			},
19746			outputs: []outputInfo{
19747				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19748			},
19749		},
19750	},
19751	{
19752		name:              "MOVDconst",
19753		auxType:           auxInt64,
19754		argLen:            0,
19755		rematerializeable: true,
19756		asm:               arm64.AMOVD,
19757		reg: regInfo{
19758			outputs: []outputInfo{
19759				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19760			},
19761		},
19762	},
19763	{
19764		name:              "FMOVSconst",
19765		auxType:           auxFloat64,
19766		argLen:            0,
19767		rematerializeable: true,
19768		asm:               arm64.AFMOVS,
19769		reg: regInfo{
19770			outputs: []outputInfo{
19771				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19772			},
19773		},
19774	},
19775	{
19776		name:              "FMOVDconst",
19777		auxType:           auxFloat64,
19778		argLen:            0,
19779		rematerializeable: true,
19780		asm:               arm64.AFMOVD,
19781		reg: regInfo{
19782			outputs: []outputInfo{
19783				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19784			},
19785		},
19786	},
19787	{
19788		name:              "MOVDaddr",
19789		auxType:           auxSymOff,
19790		argLen:            1,
19791		rematerializeable: true,
19792		symEffect:         SymAddr,
19793		asm:               arm64.AMOVD,
19794		reg: regInfo{
19795			inputs: []inputInfo{
19796				{0, 9223372037928517632}, // SP SB
19797			},
19798			outputs: []outputInfo{
19799				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19800			},
19801		},
19802	},
19803	{
19804		name:           "MOVBload",
19805		auxType:        auxSymOff,
19806		argLen:         2,
19807		faultOnNilArg0: true,
19808		symEffect:      SymRead,
19809		asm:            arm64.AMOVB,
19810		reg: regInfo{
19811			inputs: []inputInfo{
19812				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19813			},
19814			outputs: []outputInfo{
19815				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19816			},
19817		},
19818	},
19819	{
19820		name:           "MOVBUload",
19821		auxType:        auxSymOff,
19822		argLen:         2,
19823		faultOnNilArg0: true,
19824		symEffect:      SymRead,
19825		asm:            arm64.AMOVBU,
19826		reg: regInfo{
19827			inputs: []inputInfo{
19828				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19829			},
19830			outputs: []outputInfo{
19831				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19832			},
19833		},
19834	},
19835	{
19836		name:           "MOVHload",
19837		auxType:        auxSymOff,
19838		argLen:         2,
19839		faultOnNilArg0: true,
19840		symEffect:      SymRead,
19841		asm:            arm64.AMOVH,
19842		reg: regInfo{
19843			inputs: []inputInfo{
19844				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19845			},
19846			outputs: []outputInfo{
19847				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19848			},
19849		},
19850	},
19851	{
19852		name:           "MOVHUload",
19853		auxType:        auxSymOff,
19854		argLen:         2,
19855		faultOnNilArg0: true,
19856		symEffect:      SymRead,
19857		asm:            arm64.AMOVHU,
19858		reg: regInfo{
19859			inputs: []inputInfo{
19860				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19861			},
19862			outputs: []outputInfo{
19863				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19864			},
19865		},
19866	},
19867	{
19868		name:           "MOVWload",
19869		auxType:        auxSymOff,
19870		argLen:         2,
19871		faultOnNilArg0: true,
19872		symEffect:      SymRead,
19873		asm:            arm64.AMOVW,
19874		reg: regInfo{
19875			inputs: []inputInfo{
19876				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19877			},
19878			outputs: []outputInfo{
19879				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19880			},
19881		},
19882	},
19883	{
19884		name:           "MOVWUload",
19885		auxType:        auxSymOff,
19886		argLen:         2,
19887		faultOnNilArg0: true,
19888		symEffect:      SymRead,
19889		asm:            arm64.AMOVWU,
19890		reg: regInfo{
19891			inputs: []inputInfo{
19892				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19893			},
19894			outputs: []outputInfo{
19895				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19896			},
19897		},
19898	},
19899	{
19900		name:           "MOVDload",
19901		auxType:        auxSymOff,
19902		argLen:         2,
19903		faultOnNilArg0: true,
19904		symEffect:      SymRead,
19905		asm:            arm64.AMOVD,
19906		reg: regInfo{
19907			inputs: []inputInfo{
19908				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19909			},
19910			outputs: []outputInfo{
19911				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19912			},
19913		},
19914	},
19915	{
19916		name:           "FMOVSload",
19917		auxType:        auxSymOff,
19918		argLen:         2,
19919		faultOnNilArg0: true,
19920		symEffect:      SymRead,
19921		asm:            arm64.AFMOVS,
19922		reg: regInfo{
19923			inputs: []inputInfo{
19924				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19925			},
19926			outputs: []outputInfo{
19927				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19928			},
19929		},
19930	},
19931	{
19932		name:           "FMOVDload",
19933		auxType:        auxSymOff,
19934		argLen:         2,
19935		faultOnNilArg0: true,
19936		symEffect:      SymRead,
19937		asm:            arm64.AFMOVD,
19938		reg: regInfo{
19939			inputs: []inputInfo{
19940				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19941			},
19942			outputs: []outputInfo{
19943				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
19944			},
19945		},
19946	},
19947	{
19948		name:   "MOVDloadidx",
19949		argLen: 3,
19950		asm:    arm64.AMOVD,
19951		reg: regInfo{
19952			inputs: []inputInfo{
19953				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19954				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19955			},
19956			outputs: []outputInfo{
19957				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19958			},
19959		},
19960	},
19961	{
19962		name:   "MOVWloadidx",
19963		argLen: 3,
19964		asm:    arm64.AMOVW,
19965		reg: regInfo{
19966			inputs: []inputInfo{
19967				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19968				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19969			},
19970			outputs: []outputInfo{
19971				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19972			},
19973		},
19974	},
19975	{
19976		name:   "MOVWUloadidx",
19977		argLen: 3,
19978		asm:    arm64.AMOVWU,
19979		reg: regInfo{
19980			inputs: []inputInfo{
19981				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19982				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19983			},
19984			outputs: []outputInfo{
19985				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
19986			},
19987		},
19988	},
19989	{
19990		name:   "MOVHloadidx",
19991		argLen: 3,
19992		asm:    arm64.AMOVH,
19993		reg: regInfo{
19994			inputs: []inputInfo{
19995				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
19996				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
19997			},
19998			outputs: []outputInfo{
19999				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20000			},
20001		},
20002	},
20003	{
20004		name:   "MOVHUloadidx",
20005		argLen: 3,
20006		asm:    arm64.AMOVHU,
20007		reg: regInfo{
20008			inputs: []inputInfo{
20009				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20010				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20011			},
20012			outputs: []outputInfo{
20013				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20014			},
20015		},
20016	},
20017	{
20018		name:   "MOVBloadidx",
20019		argLen: 3,
20020		asm:    arm64.AMOVB,
20021		reg: regInfo{
20022			inputs: []inputInfo{
20023				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20024				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20025			},
20026			outputs: []outputInfo{
20027				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20028			},
20029		},
20030	},
20031	{
20032		name:   "MOVBUloadidx",
20033		argLen: 3,
20034		asm:    arm64.AMOVBU,
20035		reg: regInfo{
20036			inputs: []inputInfo{
20037				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20038				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20039			},
20040			outputs: []outputInfo{
20041				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20042			},
20043		},
20044	},
20045	{
20046		name:   "FMOVSloadidx",
20047		argLen: 3,
20048		asm:    arm64.AFMOVS,
20049		reg: regInfo{
20050			inputs: []inputInfo{
20051				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20052				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20053			},
20054			outputs: []outputInfo{
20055				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20056			},
20057		},
20058	},
20059	{
20060		name:   "FMOVDloadidx",
20061		argLen: 3,
20062		asm:    arm64.AFMOVD,
20063		reg: regInfo{
20064			inputs: []inputInfo{
20065				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20066				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20067			},
20068			outputs: []outputInfo{
20069				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20070			},
20071		},
20072	},
20073	{
20074		name:   "MOVHloadidx2",
20075		argLen: 3,
20076		asm:    arm64.AMOVH,
20077		reg: regInfo{
20078			inputs: []inputInfo{
20079				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20080				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20081			},
20082			outputs: []outputInfo{
20083				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20084			},
20085		},
20086	},
20087	{
20088		name:   "MOVHUloadidx2",
20089		argLen: 3,
20090		asm:    arm64.AMOVHU,
20091		reg: regInfo{
20092			inputs: []inputInfo{
20093				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20094				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20095			},
20096			outputs: []outputInfo{
20097				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20098			},
20099		},
20100	},
20101	{
20102		name:   "MOVWloadidx4",
20103		argLen: 3,
20104		asm:    arm64.AMOVW,
20105		reg: regInfo{
20106			inputs: []inputInfo{
20107				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20108				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20109			},
20110			outputs: []outputInfo{
20111				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20112			},
20113		},
20114	},
20115	{
20116		name:   "MOVWUloadidx4",
20117		argLen: 3,
20118		asm:    arm64.AMOVWU,
20119		reg: regInfo{
20120			inputs: []inputInfo{
20121				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20122				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20123			},
20124			outputs: []outputInfo{
20125				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20126			},
20127		},
20128	},
20129	{
20130		name:   "MOVDloadidx8",
20131		argLen: 3,
20132		asm:    arm64.AMOVD,
20133		reg: regInfo{
20134			inputs: []inputInfo{
20135				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20136				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20137			},
20138			outputs: []outputInfo{
20139				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20140			},
20141		},
20142	},
20143	{
20144		name:   "FMOVSloadidx4",
20145		argLen: 3,
20146		asm:    arm64.AFMOVS,
20147		reg: regInfo{
20148			inputs: []inputInfo{
20149				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20150				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20151			},
20152			outputs: []outputInfo{
20153				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20154			},
20155		},
20156	},
20157	{
20158		name:   "FMOVDloadidx8",
20159		argLen: 3,
20160		asm:    arm64.AFMOVD,
20161		reg: regInfo{
20162			inputs: []inputInfo{
20163				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20164				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20165			},
20166			outputs: []outputInfo{
20167				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20168			},
20169		},
20170	},
20171	{
20172		name:           "MOVBstore",
20173		auxType:        auxSymOff,
20174		argLen:         3,
20175		faultOnNilArg0: true,
20176		symEffect:      SymWrite,
20177		asm:            arm64.AMOVB,
20178		reg: regInfo{
20179			inputs: []inputInfo{
20180				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20181				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20182			},
20183		},
20184	},
20185	{
20186		name:           "MOVHstore",
20187		auxType:        auxSymOff,
20188		argLen:         3,
20189		faultOnNilArg0: true,
20190		symEffect:      SymWrite,
20191		asm:            arm64.AMOVH,
20192		reg: regInfo{
20193			inputs: []inputInfo{
20194				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20195				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20196			},
20197		},
20198	},
20199	{
20200		name:           "MOVWstore",
20201		auxType:        auxSymOff,
20202		argLen:         3,
20203		faultOnNilArg0: true,
20204		symEffect:      SymWrite,
20205		asm:            arm64.AMOVW,
20206		reg: regInfo{
20207			inputs: []inputInfo{
20208				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20209				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20210			},
20211		},
20212	},
20213	{
20214		name:           "MOVDstore",
20215		auxType:        auxSymOff,
20216		argLen:         3,
20217		faultOnNilArg0: true,
20218		symEffect:      SymWrite,
20219		asm:            arm64.AMOVD,
20220		reg: regInfo{
20221			inputs: []inputInfo{
20222				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20223				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20224			},
20225		},
20226	},
20227	{
20228		name:           "STP",
20229		auxType:        auxSymOff,
20230		argLen:         4,
20231		faultOnNilArg0: true,
20232		symEffect:      SymWrite,
20233		asm:            arm64.ASTP,
20234		reg: regInfo{
20235			inputs: []inputInfo{
20236				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20237				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20238				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20239			},
20240		},
20241	},
20242	{
20243		name:           "FMOVSstore",
20244		auxType:        auxSymOff,
20245		argLen:         3,
20246		faultOnNilArg0: true,
20247		symEffect:      SymWrite,
20248		asm:            arm64.AFMOVS,
20249		reg: regInfo{
20250			inputs: []inputInfo{
20251				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20252				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20253			},
20254		},
20255	},
20256	{
20257		name:           "FMOVDstore",
20258		auxType:        auxSymOff,
20259		argLen:         3,
20260		faultOnNilArg0: true,
20261		symEffect:      SymWrite,
20262		asm:            arm64.AFMOVD,
20263		reg: regInfo{
20264			inputs: []inputInfo{
20265				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20266				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20267			},
20268		},
20269	},
20270	{
20271		name:   "MOVBstoreidx",
20272		argLen: 4,
20273		asm:    arm64.AMOVB,
20274		reg: regInfo{
20275			inputs: []inputInfo{
20276				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20277				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20278				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20279			},
20280		},
20281	},
20282	{
20283		name:   "MOVHstoreidx",
20284		argLen: 4,
20285		asm:    arm64.AMOVH,
20286		reg: regInfo{
20287			inputs: []inputInfo{
20288				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20289				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20290				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20291			},
20292		},
20293	},
20294	{
20295		name:   "MOVWstoreidx",
20296		argLen: 4,
20297		asm:    arm64.AMOVW,
20298		reg: regInfo{
20299			inputs: []inputInfo{
20300				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20301				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20302				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20303			},
20304		},
20305	},
20306	{
20307		name:   "MOVDstoreidx",
20308		argLen: 4,
20309		asm:    arm64.AMOVD,
20310		reg: regInfo{
20311			inputs: []inputInfo{
20312				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20313				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20314				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20315			},
20316		},
20317	},
20318	{
20319		name:   "FMOVSstoreidx",
20320		argLen: 4,
20321		asm:    arm64.AFMOVS,
20322		reg: regInfo{
20323			inputs: []inputInfo{
20324				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20325				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20326				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20327			},
20328		},
20329	},
20330	{
20331		name:   "FMOVDstoreidx",
20332		argLen: 4,
20333		asm:    arm64.AFMOVD,
20334		reg: regInfo{
20335			inputs: []inputInfo{
20336				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20337				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20338				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20339			},
20340		},
20341	},
20342	{
20343		name:   "MOVHstoreidx2",
20344		argLen: 4,
20345		asm:    arm64.AMOVH,
20346		reg: regInfo{
20347			inputs: []inputInfo{
20348				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20349				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20350				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20351			},
20352		},
20353	},
20354	{
20355		name:   "MOVWstoreidx4",
20356		argLen: 4,
20357		asm:    arm64.AMOVW,
20358		reg: regInfo{
20359			inputs: []inputInfo{
20360				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20361				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20362				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20363			},
20364		},
20365	},
20366	{
20367		name:   "MOVDstoreidx8",
20368		argLen: 4,
20369		asm:    arm64.AMOVD,
20370		reg: regInfo{
20371			inputs: []inputInfo{
20372				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20373				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20374				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20375			},
20376		},
20377	},
20378	{
20379		name:   "FMOVSstoreidx4",
20380		argLen: 4,
20381		asm:    arm64.AFMOVS,
20382		reg: regInfo{
20383			inputs: []inputInfo{
20384				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20385				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20386				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20387			},
20388		},
20389	},
20390	{
20391		name:   "FMOVDstoreidx8",
20392		argLen: 4,
20393		asm:    arm64.AFMOVD,
20394		reg: regInfo{
20395			inputs: []inputInfo{
20396				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20397				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20398				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20399			},
20400		},
20401	},
20402	{
20403		name:           "MOVBstorezero",
20404		auxType:        auxSymOff,
20405		argLen:         2,
20406		faultOnNilArg0: true,
20407		symEffect:      SymWrite,
20408		asm:            arm64.AMOVB,
20409		reg: regInfo{
20410			inputs: []inputInfo{
20411				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20412			},
20413		},
20414	},
20415	{
20416		name:           "MOVHstorezero",
20417		auxType:        auxSymOff,
20418		argLen:         2,
20419		faultOnNilArg0: true,
20420		symEffect:      SymWrite,
20421		asm:            arm64.AMOVH,
20422		reg: regInfo{
20423			inputs: []inputInfo{
20424				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20425			},
20426		},
20427	},
20428	{
20429		name:           "MOVWstorezero",
20430		auxType:        auxSymOff,
20431		argLen:         2,
20432		faultOnNilArg0: true,
20433		symEffect:      SymWrite,
20434		asm:            arm64.AMOVW,
20435		reg: regInfo{
20436			inputs: []inputInfo{
20437				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20438			},
20439		},
20440	},
20441	{
20442		name:           "MOVDstorezero",
20443		auxType:        auxSymOff,
20444		argLen:         2,
20445		faultOnNilArg0: true,
20446		symEffect:      SymWrite,
20447		asm:            arm64.AMOVD,
20448		reg: regInfo{
20449			inputs: []inputInfo{
20450				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20451			},
20452		},
20453	},
20454	{
20455		name:           "MOVQstorezero",
20456		auxType:        auxSymOff,
20457		argLen:         2,
20458		faultOnNilArg0: true,
20459		symEffect:      SymWrite,
20460		asm:            arm64.ASTP,
20461		reg: regInfo{
20462			inputs: []inputInfo{
20463				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20464			},
20465		},
20466	},
20467	{
20468		name:   "MOVBstorezeroidx",
20469		argLen: 3,
20470		asm:    arm64.AMOVB,
20471		reg: regInfo{
20472			inputs: []inputInfo{
20473				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20474				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20475			},
20476		},
20477	},
20478	{
20479		name:   "MOVHstorezeroidx",
20480		argLen: 3,
20481		asm:    arm64.AMOVH,
20482		reg: regInfo{
20483			inputs: []inputInfo{
20484				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20485				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20486			},
20487		},
20488	},
20489	{
20490		name:   "MOVWstorezeroidx",
20491		argLen: 3,
20492		asm:    arm64.AMOVW,
20493		reg: regInfo{
20494			inputs: []inputInfo{
20495				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20496				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20497			},
20498		},
20499	},
20500	{
20501		name:   "MOVDstorezeroidx",
20502		argLen: 3,
20503		asm:    arm64.AMOVD,
20504		reg: regInfo{
20505			inputs: []inputInfo{
20506				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20507				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20508			},
20509		},
20510	},
20511	{
20512		name:   "MOVHstorezeroidx2",
20513		argLen: 3,
20514		asm:    arm64.AMOVH,
20515		reg: regInfo{
20516			inputs: []inputInfo{
20517				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20518				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20519			},
20520		},
20521	},
20522	{
20523		name:   "MOVWstorezeroidx4",
20524		argLen: 3,
20525		asm:    arm64.AMOVW,
20526		reg: regInfo{
20527			inputs: []inputInfo{
20528				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20529				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20530			},
20531		},
20532	},
20533	{
20534		name:   "MOVDstorezeroidx8",
20535		argLen: 3,
20536		asm:    arm64.AMOVD,
20537		reg: regInfo{
20538			inputs: []inputInfo{
20539				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20540				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
20541			},
20542		},
20543	},
20544	{
20545		name:   "FMOVDgpfp",
20546		argLen: 1,
20547		asm:    arm64.AFMOVD,
20548		reg: regInfo{
20549			inputs: []inputInfo{
20550				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20551			},
20552			outputs: []outputInfo{
20553				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20554			},
20555		},
20556	},
20557	{
20558		name:   "FMOVDfpgp",
20559		argLen: 1,
20560		asm:    arm64.AFMOVD,
20561		reg: regInfo{
20562			inputs: []inputInfo{
20563				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20564			},
20565			outputs: []outputInfo{
20566				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20567			},
20568		},
20569	},
20570	{
20571		name:   "FMOVSgpfp",
20572		argLen: 1,
20573		asm:    arm64.AFMOVS,
20574		reg: regInfo{
20575			inputs: []inputInfo{
20576				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20577			},
20578			outputs: []outputInfo{
20579				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20580			},
20581		},
20582	},
20583	{
20584		name:   "FMOVSfpgp",
20585		argLen: 1,
20586		asm:    arm64.AFMOVS,
20587		reg: regInfo{
20588			inputs: []inputInfo{
20589				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20590			},
20591			outputs: []outputInfo{
20592				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20593			},
20594		},
20595	},
20596	{
20597		name:   "MOVBreg",
20598		argLen: 1,
20599		asm:    arm64.AMOVB,
20600		reg: regInfo{
20601			inputs: []inputInfo{
20602				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20603			},
20604			outputs: []outputInfo{
20605				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20606			},
20607		},
20608	},
20609	{
20610		name:   "MOVBUreg",
20611		argLen: 1,
20612		asm:    arm64.AMOVBU,
20613		reg: regInfo{
20614			inputs: []inputInfo{
20615				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20616			},
20617			outputs: []outputInfo{
20618				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20619			},
20620		},
20621	},
20622	{
20623		name:   "MOVHreg",
20624		argLen: 1,
20625		asm:    arm64.AMOVH,
20626		reg: regInfo{
20627			inputs: []inputInfo{
20628				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20629			},
20630			outputs: []outputInfo{
20631				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20632			},
20633		},
20634	},
20635	{
20636		name:   "MOVHUreg",
20637		argLen: 1,
20638		asm:    arm64.AMOVHU,
20639		reg: regInfo{
20640			inputs: []inputInfo{
20641				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20642			},
20643			outputs: []outputInfo{
20644				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20645			},
20646		},
20647	},
20648	{
20649		name:   "MOVWreg",
20650		argLen: 1,
20651		asm:    arm64.AMOVW,
20652		reg: regInfo{
20653			inputs: []inputInfo{
20654				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20655			},
20656			outputs: []outputInfo{
20657				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20658			},
20659		},
20660	},
20661	{
20662		name:   "MOVWUreg",
20663		argLen: 1,
20664		asm:    arm64.AMOVWU,
20665		reg: regInfo{
20666			inputs: []inputInfo{
20667				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20668			},
20669			outputs: []outputInfo{
20670				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20671			},
20672		},
20673	},
20674	{
20675		name:   "MOVDreg",
20676		argLen: 1,
20677		asm:    arm64.AMOVD,
20678		reg: regInfo{
20679			inputs: []inputInfo{
20680				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
20681			},
20682			outputs: []outputInfo{
20683				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20684			},
20685		},
20686	},
20687	{
20688		name:         "MOVDnop",
20689		argLen:       1,
20690		resultInArg0: true,
20691		reg: regInfo{
20692			inputs: []inputInfo{
20693				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20694			},
20695			outputs: []outputInfo{
20696				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20697			},
20698		},
20699	},
20700	{
20701		name:   "SCVTFWS",
20702		argLen: 1,
20703		asm:    arm64.ASCVTFWS,
20704		reg: regInfo{
20705			inputs: []inputInfo{
20706				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20707			},
20708			outputs: []outputInfo{
20709				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20710			},
20711		},
20712	},
20713	{
20714		name:   "SCVTFWD",
20715		argLen: 1,
20716		asm:    arm64.ASCVTFWD,
20717		reg: regInfo{
20718			inputs: []inputInfo{
20719				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20720			},
20721			outputs: []outputInfo{
20722				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20723			},
20724		},
20725	},
20726	{
20727		name:   "UCVTFWS",
20728		argLen: 1,
20729		asm:    arm64.AUCVTFWS,
20730		reg: regInfo{
20731			inputs: []inputInfo{
20732				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20733			},
20734			outputs: []outputInfo{
20735				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20736			},
20737		},
20738	},
20739	{
20740		name:   "UCVTFWD",
20741		argLen: 1,
20742		asm:    arm64.AUCVTFWD,
20743		reg: regInfo{
20744			inputs: []inputInfo{
20745				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20746			},
20747			outputs: []outputInfo{
20748				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20749			},
20750		},
20751	},
20752	{
20753		name:   "SCVTFS",
20754		argLen: 1,
20755		asm:    arm64.ASCVTFS,
20756		reg: regInfo{
20757			inputs: []inputInfo{
20758				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20759			},
20760			outputs: []outputInfo{
20761				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20762			},
20763		},
20764	},
20765	{
20766		name:   "SCVTFD",
20767		argLen: 1,
20768		asm:    arm64.ASCVTFD,
20769		reg: regInfo{
20770			inputs: []inputInfo{
20771				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20772			},
20773			outputs: []outputInfo{
20774				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20775			},
20776		},
20777	},
20778	{
20779		name:   "UCVTFS",
20780		argLen: 1,
20781		asm:    arm64.AUCVTFS,
20782		reg: regInfo{
20783			inputs: []inputInfo{
20784				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20785			},
20786			outputs: []outputInfo{
20787				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20788			},
20789		},
20790	},
20791	{
20792		name:   "UCVTFD",
20793		argLen: 1,
20794		asm:    arm64.AUCVTFD,
20795		reg: regInfo{
20796			inputs: []inputInfo{
20797				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20798			},
20799			outputs: []outputInfo{
20800				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20801			},
20802		},
20803	},
20804	{
20805		name:   "FCVTZSSW",
20806		argLen: 1,
20807		asm:    arm64.AFCVTZSSW,
20808		reg: regInfo{
20809			inputs: []inputInfo{
20810				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20811			},
20812			outputs: []outputInfo{
20813				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20814			},
20815		},
20816	},
20817	{
20818		name:   "FCVTZSDW",
20819		argLen: 1,
20820		asm:    arm64.AFCVTZSDW,
20821		reg: regInfo{
20822			inputs: []inputInfo{
20823				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20824			},
20825			outputs: []outputInfo{
20826				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20827			},
20828		},
20829	},
20830	{
20831		name:   "FCVTZUSW",
20832		argLen: 1,
20833		asm:    arm64.AFCVTZUSW,
20834		reg: regInfo{
20835			inputs: []inputInfo{
20836				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20837			},
20838			outputs: []outputInfo{
20839				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20840			},
20841		},
20842	},
20843	{
20844		name:   "FCVTZUDW",
20845		argLen: 1,
20846		asm:    arm64.AFCVTZUDW,
20847		reg: regInfo{
20848			inputs: []inputInfo{
20849				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20850			},
20851			outputs: []outputInfo{
20852				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20853			},
20854		},
20855	},
20856	{
20857		name:   "FCVTZSS",
20858		argLen: 1,
20859		asm:    arm64.AFCVTZSS,
20860		reg: regInfo{
20861			inputs: []inputInfo{
20862				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20863			},
20864			outputs: []outputInfo{
20865				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20866			},
20867		},
20868	},
20869	{
20870		name:   "FCVTZSD",
20871		argLen: 1,
20872		asm:    arm64.AFCVTZSD,
20873		reg: regInfo{
20874			inputs: []inputInfo{
20875				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20876			},
20877			outputs: []outputInfo{
20878				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20879			},
20880		},
20881	},
20882	{
20883		name:   "FCVTZUS",
20884		argLen: 1,
20885		asm:    arm64.AFCVTZUS,
20886		reg: regInfo{
20887			inputs: []inputInfo{
20888				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20889			},
20890			outputs: []outputInfo{
20891				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20892			},
20893		},
20894	},
20895	{
20896		name:   "FCVTZUD",
20897		argLen: 1,
20898		asm:    arm64.AFCVTZUD,
20899		reg: regInfo{
20900			inputs: []inputInfo{
20901				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20902			},
20903			outputs: []outputInfo{
20904				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
20905			},
20906		},
20907	},
20908	{
20909		name:   "FCVTSD",
20910		argLen: 1,
20911		asm:    arm64.AFCVTSD,
20912		reg: regInfo{
20913			inputs: []inputInfo{
20914				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20915			},
20916			outputs: []outputInfo{
20917				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20918			},
20919		},
20920	},
20921	{
20922		name:   "FCVTDS",
20923		argLen: 1,
20924		asm:    arm64.AFCVTDS,
20925		reg: regInfo{
20926			inputs: []inputInfo{
20927				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20928			},
20929			outputs: []outputInfo{
20930				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20931			},
20932		},
20933	},
20934	{
20935		name:   "FRINTAD",
20936		argLen: 1,
20937		asm:    arm64.AFRINTAD,
20938		reg: regInfo{
20939			inputs: []inputInfo{
20940				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20941			},
20942			outputs: []outputInfo{
20943				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20944			},
20945		},
20946	},
20947	{
20948		name:   "FRINTMD",
20949		argLen: 1,
20950		asm:    arm64.AFRINTMD,
20951		reg: regInfo{
20952			inputs: []inputInfo{
20953				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20954			},
20955			outputs: []outputInfo{
20956				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20957			},
20958		},
20959	},
20960	{
20961		name:   "FRINTND",
20962		argLen: 1,
20963		asm:    arm64.AFRINTND,
20964		reg: regInfo{
20965			inputs: []inputInfo{
20966				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20967			},
20968			outputs: []outputInfo{
20969				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20970			},
20971		},
20972	},
20973	{
20974		name:   "FRINTPD",
20975		argLen: 1,
20976		asm:    arm64.AFRINTPD,
20977		reg: regInfo{
20978			inputs: []inputInfo{
20979				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20980			},
20981			outputs: []outputInfo{
20982				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20983			},
20984		},
20985	},
20986	{
20987		name:   "FRINTZD",
20988		argLen: 1,
20989		asm:    arm64.AFRINTZD,
20990		reg: regInfo{
20991			inputs: []inputInfo{
20992				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20993			},
20994			outputs: []outputInfo{
20995				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
20996			},
20997		},
20998	},
20999	{
21000		name:    "CSEL",
21001		auxType: auxCCop,
21002		argLen:  3,
21003		asm:     arm64.ACSEL,
21004		reg: regInfo{
21005			inputs: []inputInfo{
21006				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21007				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21008			},
21009			outputs: []outputInfo{
21010				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21011			},
21012		},
21013	},
21014	{
21015		name:    "CSEL0",
21016		auxType: auxCCop,
21017		argLen:  2,
21018		asm:     arm64.ACSEL,
21019		reg: regInfo{
21020			inputs: []inputInfo{
21021				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21022			},
21023			outputs: []outputInfo{
21024				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21025			},
21026		},
21027	},
21028	{
21029		name:    "CSINC",
21030		auxType: auxCCop,
21031		argLen:  3,
21032		asm:     arm64.ACSINC,
21033		reg: regInfo{
21034			inputs: []inputInfo{
21035				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21036				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21037			},
21038			outputs: []outputInfo{
21039				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21040			},
21041		},
21042	},
21043	{
21044		name:    "CSINV",
21045		auxType: auxCCop,
21046		argLen:  3,
21047		asm:     arm64.ACSINV,
21048		reg: regInfo{
21049			inputs: []inputInfo{
21050				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21051				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21052			},
21053			outputs: []outputInfo{
21054				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21055			},
21056		},
21057	},
21058	{
21059		name:    "CSNEG",
21060		auxType: auxCCop,
21061		argLen:  3,
21062		asm:     arm64.ACSNEG,
21063		reg: regInfo{
21064			inputs: []inputInfo{
21065				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21066				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21067			},
21068			outputs: []outputInfo{
21069				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21070			},
21071		},
21072	},
21073	{
21074		name:    "CSETM",
21075		auxType: auxCCop,
21076		argLen:  1,
21077		asm:     arm64.ACSETM,
21078		reg: regInfo{
21079			outputs: []outputInfo{
21080				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21081			},
21082		},
21083	},
21084	{
21085		name:         "CALLstatic",
21086		auxType:      auxCallOff,
21087		argLen:       -1,
21088		clobberFlags: true,
21089		call:         true,
21090		reg: regInfo{
21091			clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21092		},
21093	},
21094	{
21095		name:         "CALLtail",
21096		auxType:      auxCallOff,
21097		argLen:       -1,
21098		clobberFlags: true,
21099		call:         true,
21100		tailCall:     true,
21101		reg: regInfo{
21102			clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21103		},
21104	},
21105	{
21106		name:         "CALLclosure",
21107		auxType:      auxCallOff,
21108		argLen:       -1,
21109		clobberFlags: true,
21110		call:         true,
21111		reg: regInfo{
21112			inputs: []inputInfo{
21113				{1, 67108864},   // R26
21114				{0, 1744568319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30 SP
21115			},
21116			clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21117		},
21118	},
21119	{
21120		name:         "CALLinter",
21121		auxType:      auxCallOff,
21122		argLen:       -1,
21123		clobberFlags: true,
21124		call:         true,
21125		reg: regInfo{
21126			inputs: []inputInfo{
21127				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21128			},
21129			clobbers: 9223372035512336383, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21130		},
21131	},
21132	{
21133		name:           "LoweredNilCheck",
21134		argLen:         2,
21135		nilCheck:       true,
21136		faultOnNilArg0: true,
21137		reg: regInfo{
21138			inputs: []inputInfo{
21139				{0, 805044223}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21140			},
21141		},
21142	},
21143	{
21144		name:   "Equal",
21145		argLen: 1,
21146		reg: regInfo{
21147			outputs: []outputInfo{
21148				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21149			},
21150		},
21151	},
21152	{
21153		name:   "NotEqual",
21154		argLen: 1,
21155		reg: regInfo{
21156			outputs: []outputInfo{
21157				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21158			},
21159		},
21160	},
21161	{
21162		name:   "LessThan",
21163		argLen: 1,
21164		reg: regInfo{
21165			outputs: []outputInfo{
21166				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21167			},
21168		},
21169	},
21170	{
21171		name:   "LessEqual",
21172		argLen: 1,
21173		reg: regInfo{
21174			outputs: []outputInfo{
21175				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21176			},
21177		},
21178	},
21179	{
21180		name:   "GreaterThan",
21181		argLen: 1,
21182		reg: regInfo{
21183			outputs: []outputInfo{
21184				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21185			},
21186		},
21187	},
21188	{
21189		name:   "GreaterEqual",
21190		argLen: 1,
21191		reg: regInfo{
21192			outputs: []outputInfo{
21193				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21194			},
21195		},
21196	},
21197	{
21198		name:   "LessThanU",
21199		argLen: 1,
21200		reg: regInfo{
21201			outputs: []outputInfo{
21202				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21203			},
21204		},
21205	},
21206	{
21207		name:   "LessEqualU",
21208		argLen: 1,
21209		reg: regInfo{
21210			outputs: []outputInfo{
21211				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21212			},
21213		},
21214	},
21215	{
21216		name:   "GreaterThanU",
21217		argLen: 1,
21218		reg: regInfo{
21219			outputs: []outputInfo{
21220				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21221			},
21222		},
21223	},
21224	{
21225		name:   "GreaterEqualU",
21226		argLen: 1,
21227		reg: regInfo{
21228			outputs: []outputInfo{
21229				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21230			},
21231		},
21232	},
21233	{
21234		name:   "LessThanF",
21235		argLen: 1,
21236		reg: regInfo{
21237			outputs: []outputInfo{
21238				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21239			},
21240		},
21241	},
21242	{
21243		name:   "LessEqualF",
21244		argLen: 1,
21245		reg: regInfo{
21246			outputs: []outputInfo{
21247				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21248			},
21249		},
21250	},
21251	{
21252		name:   "GreaterThanF",
21253		argLen: 1,
21254		reg: regInfo{
21255			outputs: []outputInfo{
21256				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21257			},
21258		},
21259	},
21260	{
21261		name:   "GreaterEqualF",
21262		argLen: 1,
21263		reg: regInfo{
21264			outputs: []outputInfo{
21265				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21266			},
21267		},
21268	},
21269	{
21270		name:   "NotLessThanF",
21271		argLen: 1,
21272		reg: regInfo{
21273			outputs: []outputInfo{
21274				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21275			},
21276		},
21277	},
21278	{
21279		name:   "NotLessEqualF",
21280		argLen: 1,
21281		reg: regInfo{
21282			outputs: []outputInfo{
21283				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21284			},
21285		},
21286	},
21287	{
21288		name:   "NotGreaterThanF",
21289		argLen: 1,
21290		reg: regInfo{
21291			outputs: []outputInfo{
21292				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21293			},
21294		},
21295	},
21296	{
21297		name:   "NotGreaterEqualF",
21298		argLen: 1,
21299		reg: regInfo{
21300			outputs: []outputInfo{
21301				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21302			},
21303		},
21304	},
21305	{
21306		name:           "DUFFZERO",
21307		auxType:        auxInt64,
21308		argLen:         2,
21309		faultOnNilArg0: true,
21310		unsafePoint:    true,
21311		reg: regInfo{
21312			inputs: []inputInfo{
21313				{0, 1048576}, // R20
21314			},
21315			clobbers: 538116096, // R16 R17 R20 R30
21316		},
21317	},
21318	{
21319		name:           "LoweredZero",
21320		argLen:         3,
21321		clobberFlags:   true,
21322		faultOnNilArg0: true,
21323		reg: regInfo{
21324			inputs: []inputInfo{
21325				{0, 65536},     // R16
21326				{1, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21327			},
21328			clobbers: 65536, // R16
21329		},
21330	},
21331	{
21332		name:           "DUFFCOPY",
21333		auxType:        auxInt64,
21334		argLen:         3,
21335		faultOnNilArg0: true,
21336		faultOnNilArg1: true,
21337		unsafePoint:    true,
21338		reg: regInfo{
21339			inputs: []inputInfo{
21340				{0, 2097152}, // R21
21341				{1, 1048576}, // R20
21342			},
21343			clobbers: 607322112, // R16 R17 R20 R21 R26 R30
21344		},
21345	},
21346	{
21347		name:           "LoweredMove",
21348		argLen:         4,
21349		clobberFlags:   true,
21350		faultOnNilArg0: true,
21351		faultOnNilArg1: true,
21352		reg: regInfo{
21353			inputs: []inputInfo{
21354				{0, 131072},    // R17
21355				{1, 65536},     // R16
21356				{2, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21357			},
21358			clobbers: 196608, // R16 R17
21359		},
21360	},
21361	{
21362		name:      "LoweredGetClosurePtr",
21363		argLen:    0,
21364		zeroWidth: true,
21365		reg: regInfo{
21366			outputs: []outputInfo{
21367				{0, 67108864}, // R26
21368			},
21369		},
21370	},
21371	{
21372		name:              "LoweredGetCallerSP",
21373		argLen:            0,
21374		rematerializeable: true,
21375		reg: regInfo{
21376			outputs: []outputInfo{
21377				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21378			},
21379		},
21380	},
21381	{
21382		name:              "LoweredGetCallerPC",
21383		argLen:            0,
21384		rematerializeable: true,
21385		reg: regInfo{
21386			outputs: []outputInfo{
21387				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21388			},
21389		},
21390	},
21391	{
21392		name:    "FlagConstant",
21393		auxType: auxFlagConstant,
21394		argLen:  0,
21395		reg:     regInfo{},
21396	},
21397	{
21398		name:   "InvertFlags",
21399		argLen: 1,
21400		reg:    regInfo{},
21401	},
21402	{
21403		name:           "LDAR",
21404		argLen:         2,
21405		faultOnNilArg0: true,
21406		asm:            arm64.ALDAR,
21407		reg: regInfo{
21408			inputs: []inputInfo{
21409				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21410			},
21411			outputs: []outputInfo{
21412				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21413			},
21414		},
21415	},
21416	{
21417		name:           "LDARB",
21418		argLen:         2,
21419		faultOnNilArg0: true,
21420		asm:            arm64.ALDARB,
21421		reg: regInfo{
21422			inputs: []inputInfo{
21423				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21424			},
21425			outputs: []outputInfo{
21426				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21427			},
21428		},
21429	},
21430	{
21431		name:           "LDARW",
21432		argLen:         2,
21433		faultOnNilArg0: true,
21434		asm:            arm64.ALDARW,
21435		reg: regInfo{
21436			inputs: []inputInfo{
21437				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21438			},
21439			outputs: []outputInfo{
21440				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21441			},
21442		},
21443	},
21444	{
21445		name:           "STLRB",
21446		argLen:         3,
21447		faultOnNilArg0: true,
21448		hasSideEffects: true,
21449		asm:            arm64.ASTLRB,
21450		reg: regInfo{
21451			inputs: []inputInfo{
21452				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21453				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21454			},
21455		},
21456	},
21457	{
21458		name:           "STLR",
21459		argLen:         3,
21460		faultOnNilArg0: true,
21461		hasSideEffects: true,
21462		asm:            arm64.ASTLR,
21463		reg: regInfo{
21464			inputs: []inputInfo{
21465				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21466				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21467			},
21468		},
21469	},
21470	{
21471		name:           "STLRW",
21472		argLen:         3,
21473		faultOnNilArg0: true,
21474		hasSideEffects: true,
21475		asm:            arm64.ASTLRW,
21476		reg: regInfo{
21477			inputs: []inputInfo{
21478				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21479				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21480			},
21481		},
21482	},
21483	{
21484		name:            "LoweredAtomicExchange64",
21485		argLen:          3,
21486		resultNotInArgs: true,
21487		faultOnNilArg0:  true,
21488		hasSideEffects:  true,
21489		unsafePoint:     true,
21490		reg: regInfo{
21491			inputs: []inputInfo{
21492				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21493				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21494			},
21495			outputs: []outputInfo{
21496				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21497			},
21498		},
21499	},
21500	{
21501		name:            "LoweredAtomicExchange32",
21502		argLen:          3,
21503		resultNotInArgs: true,
21504		faultOnNilArg0:  true,
21505		hasSideEffects:  true,
21506		unsafePoint:     true,
21507		reg: regInfo{
21508			inputs: []inputInfo{
21509				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21510				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21511			},
21512			outputs: []outputInfo{
21513				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21514			},
21515		},
21516	},
21517	{
21518		name:            "LoweredAtomicExchange64Variant",
21519		argLen:          3,
21520		resultNotInArgs: true,
21521		faultOnNilArg0:  true,
21522		hasSideEffects:  true,
21523		reg: regInfo{
21524			inputs: []inputInfo{
21525				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21526				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21527			},
21528			outputs: []outputInfo{
21529				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21530			},
21531		},
21532	},
21533	{
21534		name:            "LoweredAtomicExchange32Variant",
21535		argLen:          3,
21536		resultNotInArgs: true,
21537		faultOnNilArg0:  true,
21538		hasSideEffects:  true,
21539		reg: regInfo{
21540			inputs: []inputInfo{
21541				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21542				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21543			},
21544			outputs: []outputInfo{
21545				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21546			},
21547		},
21548	},
21549	{
21550		name:            "LoweredAtomicAdd64",
21551		argLen:          3,
21552		resultNotInArgs: true,
21553		faultOnNilArg0:  true,
21554		hasSideEffects:  true,
21555		unsafePoint:     true,
21556		reg: regInfo{
21557			inputs: []inputInfo{
21558				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21559				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21560			},
21561			outputs: []outputInfo{
21562				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21563			},
21564		},
21565	},
21566	{
21567		name:            "LoweredAtomicAdd32",
21568		argLen:          3,
21569		resultNotInArgs: true,
21570		faultOnNilArg0:  true,
21571		hasSideEffects:  true,
21572		unsafePoint:     true,
21573		reg: regInfo{
21574			inputs: []inputInfo{
21575				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21576				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21577			},
21578			outputs: []outputInfo{
21579				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21580			},
21581		},
21582	},
21583	{
21584		name:            "LoweredAtomicAdd64Variant",
21585		argLen:          3,
21586		resultNotInArgs: true,
21587		faultOnNilArg0:  true,
21588		hasSideEffects:  true,
21589		reg: regInfo{
21590			inputs: []inputInfo{
21591				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21592				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21593			},
21594			outputs: []outputInfo{
21595				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21596			},
21597		},
21598	},
21599	{
21600		name:            "LoweredAtomicAdd32Variant",
21601		argLen:          3,
21602		resultNotInArgs: true,
21603		faultOnNilArg0:  true,
21604		hasSideEffects:  true,
21605		reg: regInfo{
21606			inputs: []inputInfo{
21607				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21608				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21609			},
21610			outputs: []outputInfo{
21611				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21612			},
21613		},
21614	},
21615	{
21616		name:            "LoweredAtomicCas64",
21617		argLen:          4,
21618		resultNotInArgs: true,
21619		clobberFlags:    true,
21620		faultOnNilArg0:  true,
21621		hasSideEffects:  true,
21622		unsafePoint:     true,
21623		reg: regInfo{
21624			inputs: []inputInfo{
21625				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21626				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21627				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21628			},
21629			outputs: []outputInfo{
21630				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21631			},
21632		},
21633	},
21634	{
21635		name:            "LoweredAtomicCas32",
21636		argLen:          4,
21637		resultNotInArgs: true,
21638		clobberFlags:    true,
21639		faultOnNilArg0:  true,
21640		hasSideEffects:  true,
21641		unsafePoint:     true,
21642		reg: regInfo{
21643			inputs: []inputInfo{
21644				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21645				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21646				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21647			},
21648			outputs: []outputInfo{
21649				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21650			},
21651		},
21652	},
21653	{
21654		name:            "LoweredAtomicCas64Variant",
21655		argLen:          4,
21656		resultNotInArgs: true,
21657		clobberFlags:    true,
21658		faultOnNilArg0:  true,
21659		hasSideEffects:  true,
21660		unsafePoint:     true,
21661		reg: regInfo{
21662			inputs: []inputInfo{
21663				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21664				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21665				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21666			},
21667			outputs: []outputInfo{
21668				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21669			},
21670		},
21671	},
21672	{
21673		name:            "LoweredAtomicCas32Variant",
21674		argLen:          4,
21675		resultNotInArgs: true,
21676		clobberFlags:    true,
21677		faultOnNilArg0:  true,
21678		hasSideEffects:  true,
21679		unsafePoint:     true,
21680		reg: regInfo{
21681			inputs: []inputInfo{
21682				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21683				{2, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21684				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21685			},
21686			outputs: []outputInfo{
21687				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21688			},
21689		},
21690	},
21691	{
21692		name:            "LoweredAtomicAnd8",
21693		argLen:          3,
21694		resultNotInArgs: true,
21695		faultOnNilArg0:  true,
21696		hasSideEffects:  true,
21697		unsafePoint:     true,
21698		asm:             arm64.AAND,
21699		reg: regInfo{
21700			inputs: []inputInfo{
21701				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21702				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21703			},
21704			outputs: []outputInfo{
21705				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21706			},
21707		},
21708	},
21709	{
21710		name:            "LoweredAtomicAnd32",
21711		argLen:          3,
21712		resultNotInArgs: true,
21713		faultOnNilArg0:  true,
21714		hasSideEffects:  true,
21715		unsafePoint:     true,
21716		asm:             arm64.AAND,
21717		reg: regInfo{
21718			inputs: []inputInfo{
21719				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21720				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21721			},
21722			outputs: []outputInfo{
21723				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21724			},
21725		},
21726	},
21727	{
21728		name:            "LoweredAtomicOr8",
21729		argLen:          3,
21730		resultNotInArgs: true,
21731		faultOnNilArg0:  true,
21732		hasSideEffects:  true,
21733		unsafePoint:     true,
21734		asm:             arm64.AORR,
21735		reg: regInfo{
21736			inputs: []inputInfo{
21737				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21738				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21739			},
21740			outputs: []outputInfo{
21741				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21742			},
21743		},
21744	},
21745	{
21746		name:            "LoweredAtomicOr32",
21747		argLen:          3,
21748		resultNotInArgs: true,
21749		faultOnNilArg0:  true,
21750		hasSideEffects:  true,
21751		unsafePoint:     true,
21752		asm:             arm64.AORR,
21753		reg: regInfo{
21754			inputs: []inputInfo{
21755				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21756				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21757			},
21758			outputs: []outputInfo{
21759				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21760			},
21761		},
21762	},
21763	{
21764		name:            "LoweredAtomicAnd8Variant",
21765		argLen:          3,
21766		resultNotInArgs: true,
21767		faultOnNilArg0:  true,
21768		hasSideEffects:  true,
21769		unsafePoint:     true,
21770		reg: regInfo{
21771			inputs: []inputInfo{
21772				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21773				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21774			},
21775			outputs: []outputInfo{
21776				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21777			},
21778		},
21779	},
21780	{
21781		name:            "LoweredAtomicAnd32Variant",
21782		argLen:          3,
21783		resultNotInArgs: true,
21784		faultOnNilArg0:  true,
21785		hasSideEffects:  true,
21786		unsafePoint:     true,
21787		reg: regInfo{
21788			inputs: []inputInfo{
21789				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21790				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21791			},
21792			outputs: []outputInfo{
21793				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21794			},
21795		},
21796	},
21797	{
21798		name:            "LoweredAtomicOr8Variant",
21799		argLen:          3,
21800		resultNotInArgs: true,
21801		faultOnNilArg0:  true,
21802		hasSideEffects:  true,
21803		reg: regInfo{
21804			inputs: []inputInfo{
21805				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21806				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21807			},
21808			outputs: []outputInfo{
21809				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21810			},
21811		},
21812	},
21813	{
21814		name:            "LoweredAtomicOr32Variant",
21815		argLen:          3,
21816		resultNotInArgs: true,
21817		faultOnNilArg0:  true,
21818		hasSideEffects:  true,
21819		reg: regInfo{
21820			inputs: []inputInfo{
21821				{1, 805044223},           // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30
21822				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21823			},
21824			outputs: []outputInfo{
21825				{0, 670826495}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 R30
21826			},
21827		},
21828	},
21829	{
21830		name:         "LoweredWB",
21831		auxType:      auxSym,
21832		argLen:       3,
21833		clobberFlags: true,
21834		symEffect:    SymNone,
21835		reg: regInfo{
21836			inputs: []inputInfo{
21837				{0, 4}, // R2
21838				{1, 8}, // R3
21839			},
21840			clobbers: 9223372035244359680, // R16 R17 R30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
21841		},
21842	},
21843	{
21844		name:    "LoweredPanicBoundsA",
21845		auxType: auxInt64,
21846		argLen:  3,
21847		call:    true,
21848		reg: regInfo{
21849			inputs: []inputInfo{
21850				{0, 4}, // R2
21851				{1, 8}, // R3
21852			},
21853		},
21854	},
21855	{
21856		name:    "LoweredPanicBoundsB",
21857		auxType: auxInt64,
21858		argLen:  3,
21859		call:    true,
21860		reg: regInfo{
21861			inputs: []inputInfo{
21862				{0, 2}, // R1
21863				{1, 4}, // R2
21864			},
21865		},
21866	},
21867	{
21868		name:    "LoweredPanicBoundsC",
21869		auxType: auxInt64,
21870		argLen:  3,
21871		call:    true,
21872		reg: regInfo{
21873			inputs: []inputInfo{
21874				{0, 1}, // R0
21875				{1, 2}, // R1
21876			},
21877		},
21878	},
21879	{
21880		name:           "PRFM",
21881		auxType:        auxInt64,
21882		argLen:         2,
21883		hasSideEffects: true,
21884		asm:            arm64.APRFM,
21885		reg: regInfo{
21886			inputs: []inputInfo{
21887				{0, 9223372038733561855}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R19 R20 R21 R22 R23 R24 R25 R26 g R30 SP SB
21888			},
21889		},
21890	},
21891	{
21892		name:           "DMB",
21893		auxType:        auxInt64,
21894		argLen:         1,
21895		hasSideEffects: true,
21896		asm:            arm64.ADMB,
21897		reg:            regInfo{},
21898	},
21899
21900	{
21901		name:        "ADD",
21902		argLen:      2,
21903		commutative: true,
21904		asm:         mips.AADDU,
21905		reg: regInfo{
21906			inputs: []inputInfo{
21907				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21908				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21909			},
21910			outputs: []outputInfo{
21911				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
21912			},
21913		},
21914	},
21915	{
21916		name:    "ADDconst",
21917		auxType: auxInt32,
21918		argLen:  1,
21919		asm:     mips.AADDU,
21920		reg: regInfo{
21921			inputs: []inputInfo{
21922				{0, 536870910}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31
21923			},
21924			outputs: []outputInfo{
21925				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
21926			},
21927		},
21928	},
21929	{
21930		name:   "SUB",
21931		argLen: 2,
21932		asm:    mips.ASUBU,
21933		reg: regInfo{
21934			inputs: []inputInfo{
21935				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21936				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21937			},
21938			outputs: []outputInfo{
21939				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
21940			},
21941		},
21942	},
21943	{
21944		name:    "SUBconst",
21945		auxType: auxInt32,
21946		argLen:  1,
21947		asm:     mips.ASUBU,
21948		reg: regInfo{
21949			inputs: []inputInfo{
21950				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21951			},
21952			outputs: []outputInfo{
21953				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
21954			},
21955		},
21956	},
21957	{
21958		name:        "MUL",
21959		argLen:      2,
21960		commutative: true,
21961		asm:         mips.AMUL,
21962		reg: regInfo{
21963			inputs: []inputInfo{
21964				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21965				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21966			},
21967			clobbers: 105553116266496, // HI LO
21968			outputs: []outputInfo{
21969				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
21970			},
21971		},
21972	},
21973	{
21974		name:        "MULT",
21975		argLen:      2,
21976		commutative: true,
21977		asm:         mips.AMUL,
21978		reg: regInfo{
21979			inputs: []inputInfo{
21980				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21981				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21982			},
21983			outputs: []outputInfo{
21984				{0, 35184372088832}, // HI
21985				{1, 70368744177664}, // LO
21986			},
21987		},
21988	},
21989	{
21990		name:        "MULTU",
21991		argLen:      2,
21992		commutative: true,
21993		asm:         mips.AMULU,
21994		reg: regInfo{
21995			inputs: []inputInfo{
21996				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21997				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
21998			},
21999			outputs: []outputInfo{
22000				{0, 35184372088832}, // HI
22001				{1, 70368744177664}, // LO
22002			},
22003		},
22004	},
22005	{
22006		name:   "DIV",
22007		argLen: 2,
22008		asm:    mips.ADIV,
22009		reg: regInfo{
22010			inputs: []inputInfo{
22011				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22012				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22013			},
22014			outputs: []outputInfo{
22015				{0, 35184372088832}, // HI
22016				{1, 70368744177664}, // LO
22017			},
22018		},
22019	},
22020	{
22021		name:   "DIVU",
22022		argLen: 2,
22023		asm:    mips.ADIVU,
22024		reg: regInfo{
22025			inputs: []inputInfo{
22026				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22027				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22028			},
22029			outputs: []outputInfo{
22030				{0, 35184372088832}, // HI
22031				{1, 70368744177664}, // LO
22032			},
22033		},
22034	},
22035	{
22036		name:        "ADDF",
22037		argLen:      2,
22038		commutative: true,
22039		asm:         mips.AADDF,
22040		reg: regInfo{
22041			inputs: []inputInfo{
22042				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22043				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22044			},
22045			outputs: []outputInfo{
22046				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22047			},
22048		},
22049	},
22050	{
22051		name:        "ADDD",
22052		argLen:      2,
22053		commutative: true,
22054		asm:         mips.AADDD,
22055		reg: regInfo{
22056			inputs: []inputInfo{
22057				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22058				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22059			},
22060			outputs: []outputInfo{
22061				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22062			},
22063		},
22064	},
22065	{
22066		name:   "SUBF",
22067		argLen: 2,
22068		asm:    mips.ASUBF,
22069		reg: regInfo{
22070			inputs: []inputInfo{
22071				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22072				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22073			},
22074			outputs: []outputInfo{
22075				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22076			},
22077		},
22078	},
22079	{
22080		name:   "SUBD",
22081		argLen: 2,
22082		asm:    mips.ASUBD,
22083		reg: regInfo{
22084			inputs: []inputInfo{
22085				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22086				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22087			},
22088			outputs: []outputInfo{
22089				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22090			},
22091		},
22092	},
22093	{
22094		name:        "MULF",
22095		argLen:      2,
22096		commutative: true,
22097		asm:         mips.AMULF,
22098		reg: regInfo{
22099			inputs: []inputInfo{
22100				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22101				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22102			},
22103			outputs: []outputInfo{
22104				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22105			},
22106		},
22107	},
22108	{
22109		name:        "MULD",
22110		argLen:      2,
22111		commutative: true,
22112		asm:         mips.AMULD,
22113		reg: regInfo{
22114			inputs: []inputInfo{
22115				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22116				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22117			},
22118			outputs: []outputInfo{
22119				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22120			},
22121		},
22122	},
22123	{
22124		name:   "DIVF",
22125		argLen: 2,
22126		asm:    mips.ADIVF,
22127		reg: regInfo{
22128			inputs: []inputInfo{
22129				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22130				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22131			},
22132			outputs: []outputInfo{
22133				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22134			},
22135		},
22136	},
22137	{
22138		name:   "DIVD",
22139		argLen: 2,
22140		asm:    mips.ADIVD,
22141		reg: regInfo{
22142			inputs: []inputInfo{
22143				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22144				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22145			},
22146			outputs: []outputInfo{
22147				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22148			},
22149		},
22150	},
22151	{
22152		name:        "AND",
22153		argLen:      2,
22154		commutative: true,
22155		asm:         mips.AAND,
22156		reg: regInfo{
22157			inputs: []inputInfo{
22158				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22159				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22160			},
22161			outputs: []outputInfo{
22162				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22163			},
22164		},
22165	},
22166	{
22167		name:    "ANDconst",
22168		auxType: auxInt32,
22169		argLen:  1,
22170		asm:     mips.AAND,
22171		reg: regInfo{
22172			inputs: []inputInfo{
22173				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22174			},
22175			outputs: []outputInfo{
22176				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22177			},
22178		},
22179	},
22180	{
22181		name:        "OR",
22182		argLen:      2,
22183		commutative: true,
22184		asm:         mips.AOR,
22185		reg: regInfo{
22186			inputs: []inputInfo{
22187				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22188				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22189			},
22190			outputs: []outputInfo{
22191				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22192			},
22193		},
22194	},
22195	{
22196		name:    "ORconst",
22197		auxType: auxInt32,
22198		argLen:  1,
22199		asm:     mips.AOR,
22200		reg: regInfo{
22201			inputs: []inputInfo{
22202				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22203			},
22204			outputs: []outputInfo{
22205				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22206			},
22207		},
22208	},
22209	{
22210		name:        "XOR",
22211		argLen:      2,
22212		commutative: true,
22213		asm:         mips.AXOR,
22214		reg: regInfo{
22215			inputs: []inputInfo{
22216				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22217				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22218			},
22219			outputs: []outputInfo{
22220				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22221			},
22222		},
22223	},
22224	{
22225		name:    "XORconst",
22226		auxType: auxInt32,
22227		argLen:  1,
22228		asm:     mips.AXOR,
22229		reg: regInfo{
22230			inputs: []inputInfo{
22231				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22232			},
22233			outputs: []outputInfo{
22234				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22235			},
22236		},
22237	},
22238	{
22239		name:        "NOR",
22240		argLen:      2,
22241		commutative: true,
22242		asm:         mips.ANOR,
22243		reg: regInfo{
22244			inputs: []inputInfo{
22245				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22246				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22247			},
22248			outputs: []outputInfo{
22249				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22250			},
22251		},
22252	},
22253	{
22254		name:    "NORconst",
22255		auxType: auxInt32,
22256		argLen:  1,
22257		asm:     mips.ANOR,
22258		reg: regInfo{
22259			inputs: []inputInfo{
22260				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22261			},
22262			outputs: []outputInfo{
22263				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22264			},
22265		},
22266	},
22267	{
22268		name:   "NEG",
22269		argLen: 1,
22270		reg: regInfo{
22271			inputs: []inputInfo{
22272				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22273			},
22274			outputs: []outputInfo{
22275				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22276			},
22277		},
22278	},
22279	{
22280		name:   "NEGF",
22281		argLen: 1,
22282		asm:    mips.ANEGF,
22283		reg: regInfo{
22284			inputs: []inputInfo{
22285				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22286			},
22287			outputs: []outputInfo{
22288				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22289			},
22290		},
22291	},
22292	{
22293		name:   "NEGD",
22294		argLen: 1,
22295		asm:    mips.ANEGD,
22296		reg: regInfo{
22297			inputs: []inputInfo{
22298				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22299			},
22300			outputs: []outputInfo{
22301				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22302			},
22303		},
22304	},
22305	{
22306		name:   "SQRTD",
22307		argLen: 1,
22308		asm:    mips.ASQRTD,
22309		reg: regInfo{
22310			inputs: []inputInfo{
22311				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22312			},
22313			outputs: []outputInfo{
22314				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22315			},
22316		},
22317	},
22318	{
22319		name:   "SQRTF",
22320		argLen: 1,
22321		asm:    mips.ASQRTF,
22322		reg: regInfo{
22323			inputs: []inputInfo{
22324				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22325			},
22326			outputs: []outputInfo{
22327				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22328			},
22329		},
22330	},
22331	{
22332		name:   "SLL",
22333		argLen: 2,
22334		asm:    mips.ASLL,
22335		reg: regInfo{
22336			inputs: []inputInfo{
22337				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22338				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22339			},
22340			outputs: []outputInfo{
22341				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22342			},
22343		},
22344	},
22345	{
22346		name:    "SLLconst",
22347		auxType: auxInt32,
22348		argLen:  1,
22349		asm:     mips.ASLL,
22350		reg: regInfo{
22351			inputs: []inputInfo{
22352				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22353			},
22354			outputs: []outputInfo{
22355				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22356			},
22357		},
22358	},
22359	{
22360		name:   "SRL",
22361		argLen: 2,
22362		asm:    mips.ASRL,
22363		reg: regInfo{
22364			inputs: []inputInfo{
22365				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22366				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22367			},
22368			outputs: []outputInfo{
22369				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22370			},
22371		},
22372	},
22373	{
22374		name:    "SRLconst",
22375		auxType: auxInt32,
22376		argLen:  1,
22377		asm:     mips.ASRL,
22378		reg: regInfo{
22379			inputs: []inputInfo{
22380				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22381			},
22382			outputs: []outputInfo{
22383				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22384			},
22385		},
22386	},
22387	{
22388		name:   "SRA",
22389		argLen: 2,
22390		asm:    mips.ASRA,
22391		reg: regInfo{
22392			inputs: []inputInfo{
22393				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22394				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22395			},
22396			outputs: []outputInfo{
22397				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22398			},
22399		},
22400	},
22401	{
22402		name:    "SRAconst",
22403		auxType: auxInt32,
22404		argLen:  1,
22405		asm:     mips.ASRA,
22406		reg: regInfo{
22407			inputs: []inputInfo{
22408				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22409			},
22410			outputs: []outputInfo{
22411				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22412			},
22413		},
22414	},
22415	{
22416		name:   "CLZ",
22417		argLen: 1,
22418		asm:    mips.ACLZ,
22419		reg: regInfo{
22420			inputs: []inputInfo{
22421				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22422			},
22423			outputs: []outputInfo{
22424				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22425			},
22426		},
22427	},
22428	{
22429		name:   "SGT",
22430		argLen: 2,
22431		asm:    mips.ASGT,
22432		reg: regInfo{
22433			inputs: []inputInfo{
22434				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22435				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22436			},
22437			outputs: []outputInfo{
22438				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22439			},
22440		},
22441	},
22442	{
22443		name:    "SGTconst",
22444		auxType: auxInt32,
22445		argLen:  1,
22446		asm:     mips.ASGT,
22447		reg: regInfo{
22448			inputs: []inputInfo{
22449				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22450			},
22451			outputs: []outputInfo{
22452				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22453			},
22454		},
22455	},
22456	{
22457		name:   "SGTzero",
22458		argLen: 1,
22459		asm:    mips.ASGT,
22460		reg: regInfo{
22461			inputs: []inputInfo{
22462				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22463			},
22464			outputs: []outputInfo{
22465				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22466			},
22467		},
22468	},
22469	{
22470		name:   "SGTU",
22471		argLen: 2,
22472		asm:    mips.ASGTU,
22473		reg: regInfo{
22474			inputs: []inputInfo{
22475				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22476				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22477			},
22478			outputs: []outputInfo{
22479				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22480			},
22481		},
22482	},
22483	{
22484		name:    "SGTUconst",
22485		auxType: auxInt32,
22486		argLen:  1,
22487		asm:     mips.ASGTU,
22488		reg: regInfo{
22489			inputs: []inputInfo{
22490				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22491			},
22492			outputs: []outputInfo{
22493				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22494			},
22495		},
22496	},
22497	{
22498		name:   "SGTUzero",
22499		argLen: 1,
22500		asm:    mips.ASGTU,
22501		reg: regInfo{
22502			inputs: []inputInfo{
22503				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22504			},
22505			outputs: []outputInfo{
22506				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22507			},
22508		},
22509	},
22510	{
22511		name:   "CMPEQF",
22512		argLen: 2,
22513		asm:    mips.ACMPEQF,
22514		reg: regInfo{
22515			inputs: []inputInfo{
22516				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22517				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22518			},
22519		},
22520	},
22521	{
22522		name:   "CMPEQD",
22523		argLen: 2,
22524		asm:    mips.ACMPEQD,
22525		reg: regInfo{
22526			inputs: []inputInfo{
22527				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22528				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22529			},
22530		},
22531	},
22532	{
22533		name:   "CMPGEF",
22534		argLen: 2,
22535		asm:    mips.ACMPGEF,
22536		reg: regInfo{
22537			inputs: []inputInfo{
22538				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22539				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22540			},
22541		},
22542	},
22543	{
22544		name:   "CMPGED",
22545		argLen: 2,
22546		asm:    mips.ACMPGED,
22547		reg: regInfo{
22548			inputs: []inputInfo{
22549				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22550				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22551			},
22552		},
22553	},
22554	{
22555		name:   "CMPGTF",
22556		argLen: 2,
22557		asm:    mips.ACMPGTF,
22558		reg: regInfo{
22559			inputs: []inputInfo{
22560				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22561				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22562			},
22563		},
22564	},
22565	{
22566		name:   "CMPGTD",
22567		argLen: 2,
22568		asm:    mips.ACMPGTD,
22569		reg: regInfo{
22570			inputs: []inputInfo{
22571				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22572				{1, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22573			},
22574		},
22575	},
22576	{
22577		name:              "MOVWconst",
22578		auxType:           auxInt32,
22579		argLen:            0,
22580		rematerializeable: true,
22581		asm:               mips.AMOVW,
22582		reg: regInfo{
22583			outputs: []outputInfo{
22584				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22585			},
22586		},
22587	},
22588	{
22589		name:              "MOVFconst",
22590		auxType:           auxFloat32,
22591		argLen:            0,
22592		rematerializeable: true,
22593		asm:               mips.AMOVF,
22594		reg: regInfo{
22595			outputs: []outputInfo{
22596				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22597			},
22598		},
22599	},
22600	{
22601		name:              "MOVDconst",
22602		auxType:           auxFloat64,
22603		argLen:            0,
22604		rematerializeable: true,
22605		asm:               mips.AMOVD,
22606		reg: regInfo{
22607			outputs: []outputInfo{
22608				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22609			},
22610		},
22611	},
22612	{
22613		name:              "MOVWaddr",
22614		auxType:           auxSymOff,
22615		argLen:            1,
22616		rematerializeable: true,
22617		symEffect:         SymAddr,
22618		asm:               mips.AMOVW,
22619		reg: regInfo{
22620			inputs: []inputInfo{
22621				{0, 140737555464192}, // SP SB
22622			},
22623			outputs: []outputInfo{
22624				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22625			},
22626		},
22627	},
22628	{
22629		name:           "MOVBload",
22630		auxType:        auxSymOff,
22631		argLen:         2,
22632		faultOnNilArg0: true,
22633		symEffect:      SymRead,
22634		asm:            mips.AMOVB,
22635		reg: regInfo{
22636			inputs: []inputInfo{
22637				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22638			},
22639			outputs: []outputInfo{
22640				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22641			},
22642		},
22643	},
22644	{
22645		name:           "MOVBUload",
22646		auxType:        auxSymOff,
22647		argLen:         2,
22648		faultOnNilArg0: true,
22649		symEffect:      SymRead,
22650		asm:            mips.AMOVBU,
22651		reg: regInfo{
22652			inputs: []inputInfo{
22653				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22654			},
22655			outputs: []outputInfo{
22656				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22657			},
22658		},
22659	},
22660	{
22661		name:           "MOVHload",
22662		auxType:        auxSymOff,
22663		argLen:         2,
22664		faultOnNilArg0: true,
22665		symEffect:      SymRead,
22666		asm:            mips.AMOVH,
22667		reg: regInfo{
22668			inputs: []inputInfo{
22669				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22670			},
22671			outputs: []outputInfo{
22672				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22673			},
22674		},
22675	},
22676	{
22677		name:           "MOVHUload",
22678		auxType:        auxSymOff,
22679		argLen:         2,
22680		faultOnNilArg0: true,
22681		symEffect:      SymRead,
22682		asm:            mips.AMOVHU,
22683		reg: regInfo{
22684			inputs: []inputInfo{
22685				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22686			},
22687			outputs: []outputInfo{
22688				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22689			},
22690		},
22691	},
22692	{
22693		name:           "MOVWload",
22694		auxType:        auxSymOff,
22695		argLen:         2,
22696		faultOnNilArg0: true,
22697		symEffect:      SymRead,
22698		asm:            mips.AMOVW,
22699		reg: regInfo{
22700			inputs: []inputInfo{
22701				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22702			},
22703			outputs: []outputInfo{
22704				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22705			},
22706		},
22707	},
22708	{
22709		name:           "MOVFload",
22710		auxType:        auxSymOff,
22711		argLen:         2,
22712		faultOnNilArg0: true,
22713		symEffect:      SymRead,
22714		asm:            mips.AMOVF,
22715		reg: regInfo{
22716			inputs: []inputInfo{
22717				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22718			},
22719			outputs: []outputInfo{
22720				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22721			},
22722		},
22723	},
22724	{
22725		name:           "MOVDload",
22726		auxType:        auxSymOff,
22727		argLen:         2,
22728		faultOnNilArg0: true,
22729		symEffect:      SymRead,
22730		asm:            mips.AMOVD,
22731		reg: regInfo{
22732			inputs: []inputInfo{
22733				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22734			},
22735			outputs: []outputInfo{
22736				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22737			},
22738		},
22739	},
22740	{
22741		name:           "MOVBstore",
22742		auxType:        auxSymOff,
22743		argLen:         3,
22744		faultOnNilArg0: true,
22745		symEffect:      SymWrite,
22746		asm:            mips.AMOVB,
22747		reg: regInfo{
22748			inputs: []inputInfo{
22749				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22750				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22751			},
22752		},
22753	},
22754	{
22755		name:           "MOVHstore",
22756		auxType:        auxSymOff,
22757		argLen:         3,
22758		faultOnNilArg0: true,
22759		symEffect:      SymWrite,
22760		asm:            mips.AMOVH,
22761		reg: regInfo{
22762			inputs: []inputInfo{
22763				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22764				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22765			},
22766		},
22767	},
22768	{
22769		name:           "MOVWstore",
22770		auxType:        auxSymOff,
22771		argLen:         3,
22772		faultOnNilArg0: true,
22773		symEffect:      SymWrite,
22774		asm:            mips.AMOVW,
22775		reg: regInfo{
22776			inputs: []inputInfo{
22777				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22778				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22779			},
22780		},
22781	},
22782	{
22783		name:           "MOVFstore",
22784		auxType:        auxSymOff,
22785		argLen:         3,
22786		faultOnNilArg0: true,
22787		symEffect:      SymWrite,
22788		asm:            mips.AMOVF,
22789		reg: regInfo{
22790			inputs: []inputInfo{
22791				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22792				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22793			},
22794		},
22795	},
22796	{
22797		name:           "MOVDstore",
22798		auxType:        auxSymOff,
22799		argLen:         3,
22800		faultOnNilArg0: true,
22801		symEffect:      SymWrite,
22802		asm:            mips.AMOVD,
22803		reg: regInfo{
22804			inputs: []inputInfo{
22805				{1, 35183835217920},  // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22806				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22807			},
22808		},
22809	},
22810	{
22811		name:           "MOVBstorezero",
22812		auxType:        auxSymOff,
22813		argLen:         2,
22814		faultOnNilArg0: true,
22815		symEffect:      SymWrite,
22816		asm:            mips.AMOVB,
22817		reg: regInfo{
22818			inputs: []inputInfo{
22819				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22820			},
22821		},
22822	},
22823	{
22824		name:           "MOVHstorezero",
22825		auxType:        auxSymOff,
22826		argLen:         2,
22827		faultOnNilArg0: true,
22828		symEffect:      SymWrite,
22829		asm:            mips.AMOVH,
22830		reg: regInfo{
22831			inputs: []inputInfo{
22832				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22833			},
22834		},
22835	},
22836	{
22837		name:           "MOVWstorezero",
22838		auxType:        auxSymOff,
22839		argLen:         2,
22840		faultOnNilArg0: true,
22841		symEffect:      SymWrite,
22842		asm:            mips.AMOVW,
22843		reg: regInfo{
22844			inputs: []inputInfo{
22845				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
22846			},
22847		},
22848	},
22849	{
22850		name:   "MOVBreg",
22851		argLen: 1,
22852		asm:    mips.AMOVB,
22853		reg: regInfo{
22854			inputs: []inputInfo{
22855				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22856			},
22857			outputs: []outputInfo{
22858				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22859			},
22860		},
22861	},
22862	{
22863		name:   "MOVBUreg",
22864		argLen: 1,
22865		asm:    mips.AMOVBU,
22866		reg: regInfo{
22867			inputs: []inputInfo{
22868				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22869			},
22870			outputs: []outputInfo{
22871				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22872			},
22873		},
22874	},
22875	{
22876		name:   "MOVHreg",
22877		argLen: 1,
22878		asm:    mips.AMOVH,
22879		reg: regInfo{
22880			inputs: []inputInfo{
22881				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22882			},
22883			outputs: []outputInfo{
22884				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22885			},
22886		},
22887	},
22888	{
22889		name:   "MOVHUreg",
22890		argLen: 1,
22891		asm:    mips.AMOVHU,
22892		reg: regInfo{
22893			inputs: []inputInfo{
22894				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22895			},
22896			outputs: []outputInfo{
22897				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22898			},
22899		},
22900	},
22901	{
22902		name:   "MOVWreg",
22903		argLen: 1,
22904		asm:    mips.AMOVW,
22905		reg: regInfo{
22906			inputs: []inputInfo{
22907				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22908			},
22909			outputs: []outputInfo{
22910				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22911			},
22912		},
22913	},
22914	{
22915		name:         "MOVWnop",
22916		argLen:       1,
22917		resultInArg0: true,
22918		reg: regInfo{
22919			inputs: []inputInfo{
22920				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22921			},
22922			outputs: []outputInfo{
22923				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22924			},
22925		},
22926	},
22927	{
22928		name:         "CMOVZ",
22929		argLen:       3,
22930		resultInArg0: true,
22931		asm:          mips.ACMOVZ,
22932		reg: regInfo{
22933			inputs: []inputInfo{
22934				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22935				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22936				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22937			},
22938			outputs: []outputInfo{
22939				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22940			},
22941		},
22942	},
22943	{
22944		name:         "CMOVZzero",
22945		argLen:       2,
22946		resultInArg0: true,
22947		asm:          mips.ACMOVZ,
22948		reg: regInfo{
22949			inputs: []inputInfo{
22950				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22951				{1, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
22952			},
22953			outputs: []outputInfo{
22954				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
22955			},
22956		},
22957	},
22958	{
22959		name:   "MOVWF",
22960		argLen: 1,
22961		asm:    mips.AMOVWF,
22962		reg: regInfo{
22963			inputs: []inputInfo{
22964				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22965			},
22966			outputs: []outputInfo{
22967				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22968			},
22969		},
22970	},
22971	{
22972		name:   "MOVWD",
22973		argLen: 1,
22974		asm:    mips.AMOVWD,
22975		reg: regInfo{
22976			inputs: []inputInfo{
22977				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22978			},
22979			outputs: []outputInfo{
22980				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22981			},
22982		},
22983	},
22984	{
22985		name:   "TRUNCFW",
22986		argLen: 1,
22987		asm:    mips.ATRUNCFW,
22988		reg: regInfo{
22989			inputs: []inputInfo{
22990				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22991			},
22992			outputs: []outputInfo{
22993				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
22994			},
22995		},
22996	},
22997	{
22998		name:   "TRUNCDW",
22999		argLen: 1,
23000		asm:    mips.ATRUNCDW,
23001		reg: regInfo{
23002			inputs: []inputInfo{
23003				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
23004			},
23005			outputs: []outputInfo{
23006				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
23007			},
23008		},
23009	},
23010	{
23011		name:   "MOVFD",
23012		argLen: 1,
23013		asm:    mips.AMOVFD,
23014		reg: regInfo{
23015			inputs: []inputInfo{
23016				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
23017			},
23018			outputs: []outputInfo{
23019				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
23020			},
23021		},
23022	},
23023	{
23024		name:   "MOVDF",
23025		argLen: 1,
23026		asm:    mips.AMOVDF,
23027		reg: regInfo{
23028			inputs: []inputInfo{
23029				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
23030			},
23031			outputs: []outputInfo{
23032				{0, 35183835217920}, // F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30
23033			},
23034		},
23035	},
23036	{
23037		name:         "CALLstatic",
23038		auxType:      auxCallOff,
23039		argLen:       1,
23040		clobberFlags: true,
23041		call:         true,
23042		reg: regInfo{
23043			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
23044		},
23045	},
23046	{
23047		name:         "CALLtail",
23048		auxType:      auxCallOff,
23049		argLen:       1,
23050		clobberFlags: true,
23051		call:         true,
23052		tailCall:     true,
23053		reg: regInfo{
23054			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
23055		},
23056	},
23057	{
23058		name:         "CALLclosure",
23059		auxType:      auxCallOff,
23060		argLen:       3,
23061		clobberFlags: true,
23062		call:         true,
23063		reg: regInfo{
23064			inputs: []inputInfo{
23065				{1, 4194304},   // R22
23066				{0, 402653182}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP R31
23067			},
23068			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
23069		},
23070	},
23071	{
23072		name:         "CALLinter",
23073		auxType:      auxCallOff,
23074		argLen:       2,
23075		clobberFlags: true,
23076		call:         true,
23077		reg: regInfo{
23078			inputs: []inputInfo{
23079				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23080			},
23081			clobbers: 140737421246462, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
23082		},
23083	},
23084	{
23085		name:           "LoweredAtomicLoad8",
23086		argLen:         2,
23087		faultOnNilArg0: true,
23088		reg: regInfo{
23089			inputs: []inputInfo{
23090				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23091			},
23092			outputs: []outputInfo{
23093				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23094			},
23095		},
23096	},
23097	{
23098		name:           "LoweredAtomicLoad32",
23099		argLen:         2,
23100		faultOnNilArg0: true,
23101		reg: regInfo{
23102			inputs: []inputInfo{
23103				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23104			},
23105			outputs: []outputInfo{
23106				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23107			},
23108		},
23109	},
23110	{
23111		name:           "LoweredAtomicStore8",
23112		argLen:         3,
23113		faultOnNilArg0: true,
23114		hasSideEffects: true,
23115		reg: regInfo{
23116			inputs: []inputInfo{
23117				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23118				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23119			},
23120		},
23121	},
23122	{
23123		name:           "LoweredAtomicStore32",
23124		argLen:         3,
23125		faultOnNilArg0: true,
23126		hasSideEffects: true,
23127		reg: regInfo{
23128			inputs: []inputInfo{
23129				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23130				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23131			},
23132		},
23133	},
23134	{
23135		name:           "LoweredAtomicStorezero",
23136		argLen:         2,
23137		faultOnNilArg0: true,
23138		hasSideEffects: true,
23139		reg: regInfo{
23140			inputs: []inputInfo{
23141				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23142			},
23143		},
23144	},
23145	{
23146		name:            "LoweredAtomicExchange",
23147		argLen:          3,
23148		resultNotInArgs: true,
23149		faultOnNilArg0:  true,
23150		hasSideEffects:  true,
23151		unsafePoint:     true,
23152		reg: regInfo{
23153			inputs: []inputInfo{
23154				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23155				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23156			},
23157			outputs: []outputInfo{
23158				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23159			},
23160		},
23161	},
23162	{
23163		name:            "LoweredAtomicAdd",
23164		argLen:          3,
23165		resultNotInArgs: true,
23166		faultOnNilArg0:  true,
23167		hasSideEffects:  true,
23168		unsafePoint:     true,
23169		reg: regInfo{
23170			inputs: []inputInfo{
23171				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23172				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23173			},
23174			outputs: []outputInfo{
23175				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23176			},
23177		},
23178	},
23179	{
23180		name:            "LoweredAtomicAddconst",
23181		auxType:         auxInt32,
23182		argLen:          2,
23183		resultNotInArgs: true,
23184		faultOnNilArg0:  true,
23185		hasSideEffects:  true,
23186		unsafePoint:     true,
23187		reg: regInfo{
23188			inputs: []inputInfo{
23189				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23190			},
23191			outputs: []outputInfo{
23192				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23193			},
23194		},
23195	},
23196	{
23197		name:            "LoweredAtomicCas",
23198		argLen:          4,
23199		resultNotInArgs: true,
23200		faultOnNilArg0:  true,
23201		hasSideEffects:  true,
23202		unsafePoint:     true,
23203		reg: regInfo{
23204			inputs: []inputInfo{
23205				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23206				{2, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23207				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23208			},
23209			outputs: []outputInfo{
23210				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23211			},
23212		},
23213	},
23214	{
23215		name:           "LoweredAtomicAnd",
23216		argLen:         3,
23217		faultOnNilArg0: true,
23218		hasSideEffects: true,
23219		unsafePoint:    true,
23220		asm:            mips.AAND,
23221		reg: regInfo{
23222			inputs: []inputInfo{
23223				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23224				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23225			},
23226		},
23227	},
23228	{
23229		name:           "LoweredAtomicOr",
23230		argLen:         3,
23231		faultOnNilArg0: true,
23232		hasSideEffects: true,
23233		unsafePoint:    true,
23234		asm:            mips.AOR,
23235		reg: regInfo{
23236			inputs: []inputInfo{
23237				{1, 469762046},       // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23238				{0, 140738025226238}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 SP g R31 SB
23239			},
23240		},
23241	},
23242	{
23243		name:           "LoweredZero",
23244		auxType:        auxInt32,
23245		argLen:         3,
23246		faultOnNilArg0: true,
23247		reg: regInfo{
23248			inputs: []inputInfo{
23249				{0, 2},         // R1
23250				{1, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23251			},
23252			clobbers: 2, // R1
23253		},
23254	},
23255	{
23256		name:           "LoweredMove",
23257		auxType:        auxInt32,
23258		argLen:         4,
23259		faultOnNilArg0: true,
23260		faultOnNilArg1: true,
23261		reg: regInfo{
23262			inputs: []inputInfo{
23263				{0, 4},         // R2
23264				{1, 2},         // R1
23265				{2, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23266			},
23267			clobbers: 6, // R1 R2
23268		},
23269	},
23270	{
23271		name:           "LoweredNilCheck",
23272		argLen:         2,
23273		nilCheck:       true,
23274		faultOnNilArg0: true,
23275		reg: regInfo{
23276			inputs: []inputInfo{
23277				{0, 469762046}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 g R31
23278			},
23279		},
23280	},
23281	{
23282		name:   "FPFlagTrue",
23283		argLen: 1,
23284		reg: regInfo{
23285			outputs: []outputInfo{
23286				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23287			},
23288		},
23289	},
23290	{
23291		name:   "FPFlagFalse",
23292		argLen: 1,
23293		reg: regInfo{
23294			outputs: []outputInfo{
23295				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23296			},
23297		},
23298	},
23299	{
23300		name:      "LoweredGetClosurePtr",
23301		argLen:    0,
23302		zeroWidth: true,
23303		reg: regInfo{
23304			outputs: []outputInfo{
23305				{0, 4194304}, // R22
23306			},
23307		},
23308	},
23309	{
23310		name:              "LoweredGetCallerSP",
23311		argLen:            0,
23312		rematerializeable: true,
23313		reg: regInfo{
23314			outputs: []outputInfo{
23315				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23316			},
23317		},
23318	},
23319	{
23320		name:              "LoweredGetCallerPC",
23321		argLen:            0,
23322		rematerializeable: true,
23323		reg: regInfo{
23324			outputs: []outputInfo{
23325				{0, 335544318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R28 R31
23326			},
23327		},
23328	},
23329	{
23330		name:         "LoweredWB",
23331		auxType:      auxSym,
23332		argLen:       3,
23333		clobberFlags: true,
23334		symEffect:    SymNone,
23335		reg: regInfo{
23336			inputs: []inputInfo{
23337				{0, 1048576}, // R20
23338				{1, 2097152}, // R21
23339			},
23340			clobbers: 140737219919872, // R31 F0 F2 F4 F6 F8 F10 F12 F14 F16 F18 F20 F22 F24 F26 F28 F30 HI LO
23341		},
23342	},
23343	{
23344		name:    "LoweredPanicBoundsA",
23345		auxType: auxInt64,
23346		argLen:  3,
23347		call:    true,
23348		reg: regInfo{
23349			inputs: []inputInfo{
23350				{0, 8},  // R3
23351				{1, 16}, // R4
23352			},
23353		},
23354	},
23355	{
23356		name:    "LoweredPanicBoundsB",
23357		auxType: auxInt64,
23358		argLen:  3,
23359		call:    true,
23360		reg: regInfo{
23361			inputs: []inputInfo{
23362				{0, 4}, // R2
23363				{1, 8}, // R3
23364			},
23365		},
23366	},
23367	{
23368		name:    "LoweredPanicBoundsC",
23369		auxType: auxInt64,
23370		argLen:  3,
23371		call:    true,
23372		reg: regInfo{
23373			inputs: []inputInfo{
23374				{0, 2}, // R1
23375				{1, 4}, // R2
23376			},
23377		},
23378	},
23379	{
23380		name:    "LoweredPanicExtendA",
23381		auxType: auxInt64,
23382		argLen:  4,
23383		call:    true,
23384		reg: regInfo{
23385			inputs: []inputInfo{
23386				{0, 32}, // R5
23387				{1, 8},  // R3
23388				{2, 16}, // R4
23389			},
23390		},
23391	},
23392	{
23393		name:    "LoweredPanicExtendB",
23394		auxType: auxInt64,
23395		argLen:  4,
23396		call:    true,
23397		reg: regInfo{
23398			inputs: []inputInfo{
23399				{0, 32}, // R5
23400				{1, 4},  // R2
23401				{2, 8},  // R3
23402			},
23403		},
23404	},
23405	{
23406		name:    "LoweredPanicExtendC",
23407		auxType: auxInt64,
23408		argLen:  4,
23409		call:    true,
23410		reg: regInfo{
23411			inputs: []inputInfo{
23412				{0, 32}, // R5
23413				{1, 2},  // R1
23414				{2, 4},  // R2
23415			},
23416		},
23417	},
23418
23419	{
23420		name:        "ADDV",
23421		argLen:      2,
23422		commutative: true,
23423		asm:         mips.AADDVU,
23424		reg: regInfo{
23425			inputs: []inputInfo{
23426				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23427				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23428			},
23429			outputs: []outputInfo{
23430				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23431			},
23432		},
23433	},
23434	{
23435		name:    "ADDVconst",
23436		auxType: auxInt64,
23437		argLen:  1,
23438		asm:     mips.AADDVU,
23439		reg: regInfo{
23440			inputs: []inputInfo{
23441				{0, 268435454}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31
23442			},
23443			outputs: []outputInfo{
23444				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23445			},
23446		},
23447	},
23448	{
23449		name:   "SUBV",
23450		argLen: 2,
23451		asm:    mips.ASUBVU,
23452		reg: regInfo{
23453			inputs: []inputInfo{
23454				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23455				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23456			},
23457			outputs: []outputInfo{
23458				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23459			},
23460		},
23461	},
23462	{
23463		name:    "SUBVconst",
23464		auxType: auxInt64,
23465		argLen:  1,
23466		asm:     mips.ASUBVU,
23467		reg: regInfo{
23468			inputs: []inputInfo{
23469				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23470			},
23471			outputs: []outputInfo{
23472				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23473			},
23474		},
23475	},
23476	{
23477		name:        "MULV",
23478		argLen:      2,
23479		commutative: true,
23480		asm:         mips.AMULV,
23481		reg: regInfo{
23482			inputs: []inputInfo{
23483				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23484				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23485			},
23486			outputs: []outputInfo{
23487				{0, 1152921504606846976}, // HI
23488				{1, 2305843009213693952}, // LO
23489			},
23490		},
23491	},
23492	{
23493		name:        "MULVU",
23494		argLen:      2,
23495		commutative: true,
23496		asm:         mips.AMULVU,
23497		reg: regInfo{
23498			inputs: []inputInfo{
23499				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23500				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23501			},
23502			outputs: []outputInfo{
23503				{0, 1152921504606846976}, // HI
23504				{1, 2305843009213693952}, // LO
23505			},
23506		},
23507	},
23508	{
23509		name:   "DIVV",
23510		argLen: 2,
23511		asm:    mips.ADIVV,
23512		reg: regInfo{
23513			inputs: []inputInfo{
23514				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23515				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23516			},
23517			outputs: []outputInfo{
23518				{0, 1152921504606846976}, // HI
23519				{1, 2305843009213693952}, // LO
23520			},
23521		},
23522	},
23523	{
23524		name:   "DIVVU",
23525		argLen: 2,
23526		asm:    mips.ADIVVU,
23527		reg: regInfo{
23528			inputs: []inputInfo{
23529				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23530				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23531			},
23532			outputs: []outputInfo{
23533				{0, 1152921504606846976}, // HI
23534				{1, 2305843009213693952}, // LO
23535			},
23536		},
23537	},
23538	{
23539		name:        "ADDF",
23540		argLen:      2,
23541		commutative: true,
23542		asm:         mips.AADDF,
23543		reg: regInfo{
23544			inputs: []inputInfo{
23545				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23546				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23547			},
23548			outputs: []outputInfo{
23549				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23550			},
23551		},
23552	},
23553	{
23554		name:        "ADDD",
23555		argLen:      2,
23556		commutative: true,
23557		asm:         mips.AADDD,
23558		reg: regInfo{
23559			inputs: []inputInfo{
23560				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23561				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23562			},
23563			outputs: []outputInfo{
23564				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23565			},
23566		},
23567	},
23568	{
23569		name:   "SUBF",
23570		argLen: 2,
23571		asm:    mips.ASUBF,
23572		reg: regInfo{
23573			inputs: []inputInfo{
23574				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23575				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23576			},
23577			outputs: []outputInfo{
23578				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23579			},
23580		},
23581	},
23582	{
23583		name:   "SUBD",
23584		argLen: 2,
23585		asm:    mips.ASUBD,
23586		reg: regInfo{
23587			inputs: []inputInfo{
23588				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23589				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23590			},
23591			outputs: []outputInfo{
23592				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23593			},
23594		},
23595	},
23596	{
23597		name:        "MULF",
23598		argLen:      2,
23599		commutative: true,
23600		asm:         mips.AMULF,
23601		reg: regInfo{
23602			inputs: []inputInfo{
23603				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23604				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23605			},
23606			outputs: []outputInfo{
23607				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23608			},
23609		},
23610	},
23611	{
23612		name:        "MULD",
23613		argLen:      2,
23614		commutative: true,
23615		asm:         mips.AMULD,
23616		reg: regInfo{
23617			inputs: []inputInfo{
23618				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23619				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23620			},
23621			outputs: []outputInfo{
23622				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23623			},
23624		},
23625	},
23626	{
23627		name:   "DIVF",
23628		argLen: 2,
23629		asm:    mips.ADIVF,
23630		reg: regInfo{
23631			inputs: []inputInfo{
23632				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23633				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23634			},
23635			outputs: []outputInfo{
23636				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23637			},
23638		},
23639	},
23640	{
23641		name:   "DIVD",
23642		argLen: 2,
23643		asm:    mips.ADIVD,
23644		reg: regInfo{
23645			inputs: []inputInfo{
23646				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23647				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23648			},
23649			outputs: []outputInfo{
23650				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23651			},
23652		},
23653	},
23654	{
23655		name:        "AND",
23656		argLen:      2,
23657		commutative: true,
23658		asm:         mips.AAND,
23659		reg: regInfo{
23660			inputs: []inputInfo{
23661				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23662				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23663			},
23664			outputs: []outputInfo{
23665				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23666			},
23667		},
23668	},
23669	{
23670		name:    "ANDconst",
23671		auxType: auxInt64,
23672		argLen:  1,
23673		asm:     mips.AAND,
23674		reg: regInfo{
23675			inputs: []inputInfo{
23676				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23677			},
23678			outputs: []outputInfo{
23679				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23680			},
23681		},
23682	},
23683	{
23684		name:        "OR",
23685		argLen:      2,
23686		commutative: true,
23687		asm:         mips.AOR,
23688		reg: regInfo{
23689			inputs: []inputInfo{
23690				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23691				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23692			},
23693			outputs: []outputInfo{
23694				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23695			},
23696		},
23697	},
23698	{
23699		name:    "ORconst",
23700		auxType: auxInt64,
23701		argLen:  1,
23702		asm:     mips.AOR,
23703		reg: regInfo{
23704			inputs: []inputInfo{
23705				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23706			},
23707			outputs: []outputInfo{
23708				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23709			},
23710		},
23711	},
23712	{
23713		name:        "XOR",
23714		argLen:      2,
23715		commutative: true,
23716		asm:         mips.AXOR,
23717		reg: regInfo{
23718			inputs: []inputInfo{
23719				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23720				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23721			},
23722			outputs: []outputInfo{
23723				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23724			},
23725		},
23726	},
23727	{
23728		name:    "XORconst",
23729		auxType: auxInt64,
23730		argLen:  1,
23731		asm:     mips.AXOR,
23732		reg: regInfo{
23733			inputs: []inputInfo{
23734				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23735			},
23736			outputs: []outputInfo{
23737				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23738			},
23739		},
23740	},
23741	{
23742		name:        "NOR",
23743		argLen:      2,
23744		commutative: true,
23745		asm:         mips.ANOR,
23746		reg: regInfo{
23747			inputs: []inputInfo{
23748				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23749				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23750			},
23751			outputs: []outputInfo{
23752				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23753			},
23754		},
23755	},
23756	{
23757		name:    "NORconst",
23758		auxType: auxInt64,
23759		argLen:  1,
23760		asm:     mips.ANOR,
23761		reg: regInfo{
23762			inputs: []inputInfo{
23763				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23764			},
23765			outputs: []outputInfo{
23766				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23767			},
23768		},
23769	},
23770	{
23771		name:   "NEGV",
23772		argLen: 1,
23773		reg: regInfo{
23774			inputs: []inputInfo{
23775				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23776			},
23777			outputs: []outputInfo{
23778				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23779			},
23780		},
23781	},
23782	{
23783		name:   "NEGF",
23784		argLen: 1,
23785		asm:    mips.ANEGF,
23786		reg: regInfo{
23787			inputs: []inputInfo{
23788				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23789			},
23790			outputs: []outputInfo{
23791				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23792			},
23793		},
23794	},
23795	{
23796		name:   "NEGD",
23797		argLen: 1,
23798		asm:    mips.ANEGD,
23799		reg: regInfo{
23800			inputs: []inputInfo{
23801				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23802			},
23803			outputs: []outputInfo{
23804				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23805			},
23806		},
23807	},
23808	{
23809		name:   "SQRTD",
23810		argLen: 1,
23811		asm:    mips.ASQRTD,
23812		reg: regInfo{
23813			inputs: []inputInfo{
23814				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23815			},
23816			outputs: []outputInfo{
23817				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23818			},
23819		},
23820	},
23821	{
23822		name:   "SQRTF",
23823		argLen: 1,
23824		asm:    mips.ASQRTF,
23825		reg: regInfo{
23826			inputs: []inputInfo{
23827				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23828			},
23829			outputs: []outputInfo{
23830				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23831			},
23832		},
23833	},
23834	{
23835		name:   "SLLV",
23836		argLen: 2,
23837		asm:    mips.ASLLV,
23838		reg: regInfo{
23839			inputs: []inputInfo{
23840				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23841				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23842			},
23843			outputs: []outputInfo{
23844				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23845			},
23846		},
23847	},
23848	{
23849		name:    "SLLVconst",
23850		auxType: auxInt64,
23851		argLen:  1,
23852		asm:     mips.ASLLV,
23853		reg: regInfo{
23854			inputs: []inputInfo{
23855				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23856			},
23857			outputs: []outputInfo{
23858				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23859			},
23860		},
23861	},
23862	{
23863		name:   "SRLV",
23864		argLen: 2,
23865		asm:    mips.ASRLV,
23866		reg: regInfo{
23867			inputs: []inputInfo{
23868				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23869				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23870			},
23871			outputs: []outputInfo{
23872				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23873			},
23874		},
23875	},
23876	{
23877		name:    "SRLVconst",
23878		auxType: auxInt64,
23879		argLen:  1,
23880		asm:     mips.ASRLV,
23881		reg: regInfo{
23882			inputs: []inputInfo{
23883				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23884			},
23885			outputs: []outputInfo{
23886				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23887			},
23888		},
23889	},
23890	{
23891		name:   "SRAV",
23892		argLen: 2,
23893		asm:    mips.ASRAV,
23894		reg: regInfo{
23895			inputs: []inputInfo{
23896				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23897				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23898			},
23899			outputs: []outputInfo{
23900				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23901			},
23902		},
23903	},
23904	{
23905		name:    "SRAVconst",
23906		auxType: auxInt64,
23907		argLen:  1,
23908		asm:     mips.ASRAV,
23909		reg: regInfo{
23910			inputs: []inputInfo{
23911				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23912			},
23913			outputs: []outputInfo{
23914				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23915			},
23916		},
23917	},
23918	{
23919		name:   "SGT",
23920		argLen: 2,
23921		asm:    mips.ASGT,
23922		reg: regInfo{
23923			inputs: []inputInfo{
23924				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23925				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23926			},
23927			outputs: []outputInfo{
23928				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23929			},
23930		},
23931	},
23932	{
23933		name:    "SGTconst",
23934		auxType: auxInt64,
23935		argLen:  1,
23936		asm:     mips.ASGT,
23937		reg: regInfo{
23938			inputs: []inputInfo{
23939				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23940			},
23941			outputs: []outputInfo{
23942				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23943			},
23944		},
23945	},
23946	{
23947		name:   "SGTU",
23948		argLen: 2,
23949		asm:    mips.ASGTU,
23950		reg: regInfo{
23951			inputs: []inputInfo{
23952				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23953				{1, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23954			},
23955			outputs: []outputInfo{
23956				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23957			},
23958		},
23959	},
23960	{
23961		name:    "SGTUconst",
23962		auxType: auxInt64,
23963		argLen:  1,
23964		asm:     mips.ASGTU,
23965		reg: regInfo{
23966			inputs: []inputInfo{
23967				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
23968			},
23969			outputs: []outputInfo{
23970				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
23971			},
23972		},
23973	},
23974	{
23975		name:   "CMPEQF",
23976		argLen: 2,
23977		asm:    mips.ACMPEQF,
23978		reg: regInfo{
23979			inputs: []inputInfo{
23980				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23981				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23982			},
23983		},
23984	},
23985	{
23986		name:   "CMPEQD",
23987		argLen: 2,
23988		asm:    mips.ACMPEQD,
23989		reg: regInfo{
23990			inputs: []inputInfo{
23991				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23992				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
23993			},
23994		},
23995	},
23996	{
23997		name:   "CMPGEF",
23998		argLen: 2,
23999		asm:    mips.ACMPGEF,
24000		reg: regInfo{
24001			inputs: []inputInfo{
24002				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24003				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24004			},
24005		},
24006	},
24007	{
24008		name:   "CMPGED",
24009		argLen: 2,
24010		asm:    mips.ACMPGED,
24011		reg: regInfo{
24012			inputs: []inputInfo{
24013				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24014				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24015			},
24016		},
24017	},
24018	{
24019		name:   "CMPGTF",
24020		argLen: 2,
24021		asm:    mips.ACMPGTF,
24022		reg: regInfo{
24023			inputs: []inputInfo{
24024				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24025				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24026			},
24027		},
24028	},
24029	{
24030		name:   "CMPGTD",
24031		argLen: 2,
24032		asm:    mips.ACMPGTD,
24033		reg: regInfo{
24034			inputs: []inputInfo{
24035				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24036				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24037			},
24038		},
24039	},
24040	{
24041		name:              "MOVVconst",
24042		auxType:           auxInt64,
24043		argLen:            0,
24044		rematerializeable: true,
24045		asm:               mips.AMOVV,
24046		reg: regInfo{
24047			outputs: []outputInfo{
24048				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24049			},
24050		},
24051	},
24052	{
24053		name:              "MOVFconst",
24054		auxType:           auxFloat64,
24055		argLen:            0,
24056		rematerializeable: true,
24057		asm:               mips.AMOVF,
24058		reg: regInfo{
24059			outputs: []outputInfo{
24060				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24061			},
24062		},
24063	},
24064	{
24065		name:              "MOVDconst",
24066		auxType:           auxFloat64,
24067		argLen:            0,
24068		rematerializeable: true,
24069		asm:               mips.AMOVD,
24070		reg: regInfo{
24071			outputs: []outputInfo{
24072				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24073			},
24074		},
24075	},
24076	{
24077		name:              "MOVVaddr",
24078		auxType:           auxSymOff,
24079		argLen:            1,
24080		rematerializeable: true,
24081		symEffect:         SymAddr,
24082		asm:               mips.AMOVV,
24083		reg: regInfo{
24084			inputs: []inputInfo{
24085				{0, 4611686018460942336}, // SP SB
24086			},
24087			outputs: []outputInfo{
24088				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24089			},
24090		},
24091	},
24092	{
24093		name:           "MOVBload",
24094		auxType:        auxSymOff,
24095		argLen:         2,
24096		faultOnNilArg0: true,
24097		symEffect:      SymRead,
24098		asm:            mips.AMOVB,
24099		reg: regInfo{
24100			inputs: []inputInfo{
24101				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24102			},
24103			outputs: []outputInfo{
24104				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24105			},
24106		},
24107	},
24108	{
24109		name:           "MOVBUload",
24110		auxType:        auxSymOff,
24111		argLen:         2,
24112		faultOnNilArg0: true,
24113		symEffect:      SymRead,
24114		asm:            mips.AMOVBU,
24115		reg: regInfo{
24116			inputs: []inputInfo{
24117				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24118			},
24119			outputs: []outputInfo{
24120				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24121			},
24122		},
24123	},
24124	{
24125		name:           "MOVHload",
24126		auxType:        auxSymOff,
24127		argLen:         2,
24128		faultOnNilArg0: true,
24129		symEffect:      SymRead,
24130		asm:            mips.AMOVH,
24131		reg: regInfo{
24132			inputs: []inputInfo{
24133				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24134			},
24135			outputs: []outputInfo{
24136				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24137			},
24138		},
24139	},
24140	{
24141		name:           "MOVHUload",
24142		auxType:        auxSymOff,
24143		argLen:         2,
24144		faultOnNilArg0: true,
24145		symEffect:      SymRead,
24146		asm:            mips.AMOVHU,
24147		reg: regInfo{
24148			inputs: []inputInfo{
24149				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24150			},
24151			outputs: []outputInfo{
24152				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24153			},
24154		},
24155	},
24156	{
24157		name:           "MOVWload",
24158		auxType:        auxSymOff,
24159		argLen:         2,
24160		faultOnNilArg0: true,
24161		symEffect:      SymRead,
24162		asm:            mips.AMOVW,
24163		reg: regInfo{
24164			inputs: []inputInfo{
24165				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24166			},
24167			outputs: []outputInfo{
24168				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24169			},
24170		},
24171	},
24172	{
24173		name:           "MOVWUload",
24174		auxType:        auxSymOff,
24175		argLen:         2,
24176		faultOnNilArg0: true,
24177		symEffect:      SymRead,
24178		asm:            mips.AMOVWU,
24179		reg: regInfo{
24180			inputs: []inputInfo{
24181				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24182			},
24183			outputs: []outputInfo{
24184				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24185			},
24186		},
24187	},
24188	{
24189		name:           "MOVVload",
24190		auxType:        auxSymOff,
24191		argLen:         2,
24192		faultOnNilArg0: true,
24193		symEffect:      SymRead,
24194		asm:            mips.AMOVV,
24195		reg: regInfo{
24196			inputs: []inputInfo{
24197				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24198			},
24199			outputs: []outputInfo{
24200				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24201			},
24202		},
24203	},
24204	{
24205		name:           "MOVFload",
24206		auxType:        auxSymOff,
24207		argLen:         2,
24208		faultOnNilArg0: true,
24209		symEffect:      SymRead,
24210		asm:            mips.AMOVF,
24211		reg: regInfo{
24212			inputs: []inputInfo{
24213				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24214			},
24215			outputs: []outputInfo{
24216				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24217			},
24218		},
24219	},
24220	{
24221		name:           "MOVDload",
24222		auxType:        auxSymOff,
24223		argLen:         2,
24224		faultOnNilArg0: true,
24225		symEffect:      SymRead,
24226		asm:            mips.AMOVD,
24227		reg: regInfo{
24228			inputs: []inputInfo{
24229				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24230			},
24231			outputs: []outputInfo{
24232				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24233			},
24234		},
24235	},
24236	{
24237		name:           "MOVBstore",
24238		auxType:        auxSymOff,
24239		argLen:         3,
24240		faultOnNilArg0: true,
24241		symEffect:      SymWrite,
24242		asm:            mips.AMOVB,
24243		reg: regInfo{
24244			inputs: []inputInfo{
24245				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24246				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24247			},
24248		},
24249	},
24250	{
24251		name:           "MOVHstore",
24252		auxType:        auxSymOff,
24253		argLen:         3,
24254		faultOnNilArg0: true,
24255		symEffect:      SymWrite,
24256		asm:            mips.AMOVH,
24257		reg: regInfo{
24258			inputs: []inputInfo{
24259				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24260				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24261			},
24262		},
24263	},
24264	{
24265		name:           "MOVWstore",
24266		auxType:        auxSymOff,
24267		argLen:         3,
24268		faultOnNilArg0: true,
24269		symEffect:      SymWrite,
24270		asm:            mips.AMOVW,
24271		reg: regInfo{
24272			inputs: []inputInfo{
24273				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24274				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24275			},
24276		},
24277	},
24278	{
24279		name:           "MOVVstore",
24280		auxType:        auxSymOff,
24281		argLen:         3,
24282		faultOnNilArg0: true,
24283		symEffect:      SymWrite,
24284		asm:            mips.AMOVV,
24285		reg: regInfo{
24286			inputs: []inputInfo{
24287				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24288				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24289			},
24290		},
24291	},
24292	{
24293		name:           "MOVFstore",
24294		auxType:        auxSymOff,
24295		argLen:         3,
24296		faultOnNilArg0: true,
24297		symEffect:      SymWrite,
24298		asm:            mips.AMOVF,
24299		reg: regInfo{
24300			inputs: []inputInfo{
24301				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24302				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24303			},
24304		},
24305	},
24306	{
24307		name:           "MOVDstore",
24308		auxType:        auxSymOff,
24309		argLen:         3,
24310		faultOnNilArg0: true,
24311		symEffect:      SymWrite,
24312		asm:            mips.AMOVD,
24313		reg: regInfo{
24314			inputs: []inputInfo{
24315				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24316				{1, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24317			},
24318		},
24319	},
24320	{
24321		name:           "MOVBstorezero",
24322		auxType:        auxSymOff,
24323		argLen:         2,
24324		faultOnNilArg0: true,
24325		symEffect:      SymWrite,
24326		asm:            mips.AMOVB,
24327		reg: regInfo{
24328			inputs: []inputInfo{
24329				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24330			},
24331		},
24332	},
24333	{
24334		name:           "MOVHstorezero",
24335		auxType:        auxSymOff,
24336		argLen:         2,
24337		faultOnNilArg0: true,
24338		symEffect:      SymWrite,
24339		asm:            mips.AMOVH,
24340		reg: regInfo{
24341			inputs: []inputInfo{
24342				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24343			},
24344		},
24345	},
24346	{
24347		name:           "MOVWstorezero",
24348		auxType:        auxSymOff,
24349		argLen:         2,
24350		faultOnNilArg0: true,
24351		symEffect:      SymWrite,
24352		asm:            mips.AMOVW,
24353		reg: regInfo{
24354			inputs: []inputInfo{
24355				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24356			},
24357		},
24358	},
24359	{
24360		name:           "MOVVstorezero",
24361		auxType:        auxSymOff,
24362		argLen:         2,
24363		faultOnNilArg0: true,
24364		symEffect:      SymWrite,
24365		asm:            mips.AMOVV,
24366		reg: regInfo{
24367			inputs: []inputInfo{
24368				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24369			},
24370		},
24371	},
24372	{
24373		name:   "MOVBreg",
24374		argLen: 1,
24375		asm:    mips.AMOVB,
24376		reg: regInfo{
24377			inputs: []inputInfo{
24378				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24379			},
24380			outputs: []outputInfo{
24381				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24382			},
24383		},
24384	},
24385	{
24386		name:   "MOVBUreg",
24387		argLen: 1,
24388		asm:    mips.AMOVBU,
24389		reg: regInfo{
24390			inputs: []inputInfo{
24391				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24392			},
24393			outputs: []outputInfo{
24394				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24395			},
24396		},
24397	},
24398	{
24399		name:   "MOVHreg",
24400		argLen: 1,
24401		asm:    mips.AMOVH,
24402		reg: regInfo{
24403			inputs: []inputInfo{
24404				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24405			},
24406			outputs: []outputInfo{
24407				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24408			},
24409		},
24410	},
24411	{
24412		name:   "MOVHUreg",
24413		argLen: 1,
24414		asm:    mips.AMOVHU,
24415		reg: regInfo{
24416			inputs: []inputInfo{
24417				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24418			},
24419			outputs: []outputInfo{
24420				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24421			},
24422		},
24423	},
24424	{
24425		name:   "MOVWreg",
24426		argLen: 1,
24427		asm:    mips.AMOVW,
24428		reg: regInfo{
24429			inputs: []inputInfo{
24430				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24431			},
24432			outputs: []outputInfo{
24433				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24434			},
24435		},
24436	},
24437	{
24438		name:   "MOVWUreg",
24439		argLen: 1,
24440		asm:    mips.AMOVWU,
24441		reg: regInfo{
24442			inputs: []inputInfo{
24443				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24444			},
24445			outputs: []outputInfo{
24446				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24447			},
24448		},
24449	},
24450	{
24451		name:   "MOVVreg",
24452		argLen: 1,
24453		asm:    mips.AMOVV,
24454		reg: regInfo{
24455			inputs: []inputInfo{
24456				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24457			},
24458			outputs: []outputInfo{
24459				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24460			},
24461		},
24462	},
24463	{
24464		name:         "MOVVnop",
24465		argLen:       1,
24466		resultInArg0: true,
24467		reg: regInfo{
24468			inputs: []inputInfo{
24469				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24470			},
24471			outputs: []outputInfo{
24472				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24473			},
24474		},
24475	},
24476	{
24477		name:   "MOVWF",
24478		argLen: 1,
24479		asm:    mips.AMOVWF,
24480		reg: regInfo{
24481			inputs: []inputInfo{
24482				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24483			},
24484			outputs: []outputInfo{
24485				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24486			},
24487		},
24488	},
24489	{
24490		name:   "MOVWD",
24491		argLen: 1,
24492		asm:    mips.AMOVWD,
24493		reg: regInfo{
24494			inputs: []inputInfo{
24495				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24496			},
24497			outputs: []outputInfo{
24498				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24499			},
24500		},
24501	},
24502	{
24503		name:   "MOVVF",
24504		argLen: 1,
24505		asm:    mips.AMOVVF,
24506		reg: regInfo{
24507			inputs: []inputInfo{
24508				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24509			},
24510			outputs: []outputInfo{
24511				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24512			},
24513		},
24514	},
24515	{
24516		name:   "MOVVD",
24517		argLen: 1,
24518		asm:    mips.AMOVVD,
24519		reg: regInfo{
24520			inputs: []inputInfo{
24521				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24522			},
24523			outputs: []outputInfo{
24524				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24525			},
24526		},
24527	},
24528	{
24529		name:   "TRUNCFW",
24530		argLen: 1,
24531		asm:    mips.ATRUNCFW,
24532		reg: regInfo{
24533			inputs: []inputInfo{
24534				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24535			},
24536			outputs: []outputInfo{
24537				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24538			},
24539		},
24540	},
24541	{
24542		name:   "TRUNCDW",
24543		argLen: 1,
24544		asm:    mips.ATRUNCDW,
24545		reg: regInfo{
24546			inputs: []inputInfo{
24547				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24548			},
24549			outputs: []outputInfo{
24550				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24551			},
24552		},
24553	},
24554	{
24555		name:   "TRUNCFV",
24556		argLen: 1,
24557		asm:    mips.ATRUNCFV,
24558		reg: regInfo{
24559			inputs: []inputInfo{
24560				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24561			},
24562			outputs: []outputInfo{
24563				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24564			},
24565		},
24566	},
24567	{
24568		name:   "TRUNCDV",
24569		argLen: 1,
24570		asm:    mips.ATRUNCDV,
24571		reg: regInfo{
24572			inputs: []inputInfo{
24573				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24574			},
24575			outputs: []outputInfo{
24576				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24577			},
24578		},
24579	},
24580	{
24581		name:   "MOVFD",
24582		argLen: 1,
24583		asm:    mips.AMOVFD,
24584		reg: regInfo{
24585			inputs: []inputInfo{
24586				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24587			},
24588			outputs: []outputInfo{
24589				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24590			},
24591		},
24592	},
24593	{
24594		name:   "MOVDF",
24595		argLen: 1,
24596		asm:    mips.AMOVDF,
24597		reg: regInfo{
24598			inputs: []inputInfo{
24599				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24600			},
24601			outputs: []outputInfo{
24602				{0, 1152921504338411520}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
24603			},
24604		},
24605	},
24606	{
24607		name:         "CALLstatic",
24608		auxType:      auxCallOff,
24609		argLen:       1,
24610		clobberFlags: true,
24611		call:         true,
24612		reg: regInfo{
24613			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
24614		},
24615	},
24616	{
24617		name:         "CALLtail",
24618		auxType:      auxCallOff,
24619		argLen:       1,
24620		clobberFlags: true,
24621		call:         true,
24622		tailCall:     true,
24623		reg: regInfo{
24624			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
24625		},
24626	},
24627	{
24628		name:         "CALLclosure",
24629		auxType:      auxCallOff,
24630		argLen:       3,
24631		clobberFlags: true,
24632		call:         true,
24633		reg: regInfo{
24634			inputs: []inputInfo{
24635				{1, 4194304},   // R22
24636				{0, 201326590}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP R31
24637			},
24638			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
24639		},
24640	},
24641	{
24642		name:         "CALLinter",
24643		auxType:      auxCallOff,
24644		argLen:       2,
24645		clobberFlags: true,
24646		call:         true,
24647		reg: regInfo{
24648			inputs: []inputInfo{
24649				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24650			},
24651			clobbers: 4611686018393833470, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
24652		},
24653	},
24654	{
24655		name:           "DUFFZERO",
24656		auxType:        auxInt64,
24657		argLen:         2,
24658		faultOnNilArg0: true,
24659		reg: regInfo{
24660			inputs: []inputInfo{
24661				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24662			},
24663			clobbers: 134217730, // R1 R31
24664		},
24665	},
24666	{
24667		name:           "DUFFCOPY",
24668		auxType:        auxInt64,
24669		argLen:         3,
24670		faultOnNilArg0: true,
24671		faultOnNilArg1: true,
24672		reg: regInfo{
24673			inputs: []inputInfo{
24674				{0, 4}, // R2
24675				{1, 2}, // R1
24676			},
24677			clobbers: 134217734, // R1 R2 R31
24678		},
24679	},
24680	{
24681		name:           "LoweredZero",
24682		auxType:        auxInt64,
24683		argLen:         3,
24684		clobberFlags:   true,
24685		faultOnNilArg0: true,
24686		reg: regInfo{
24687			inputs: []inputInfo{
24688				{0, 2},         // R1
24689				{1, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24690			},
24691			clobbers: 2, // R1
24692		},
24693	},
24694	{
24695		name:           "LoweredMove",
24696		auxType:        auxInt64,
24697		argLen:         4,
24698		clobberFlags:   true,
24699		faultOnNilArg0: true,
24700		faultOnNilArg1: true,
24701		reg: regInfo{
24702			inputs: []inputInfo{
24703				{0, 4},         // R2
24704				{1, 2},         // R1
24705				{2, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24706			},
24707			clobbers: 6, // R1 R2
24708		},
24709	},
24710	{
24711		name:           "LoweredAtomicLoad8",
24712		argLen:         2,
24713		faultOnNilArg0: true,
24714		reg: regInfo{
24715			inputs: []inputInfo{
24716				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24717			},
24718			outputs: []outputInfo{
24719				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24720			},
24721		},
24722	},
24723	{
24724		name:           "LoweredAtomicLoad32",
24725		argLen:         2,
24726		faultOnNilArg0: true,
24727		reg: regInfo{
24728			inputs: []inputInfo{
24729				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24730			},
24731			outputs: []outputInfo{
24732				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24733			},
24734		},
24735	},
24736	{
24737		name:           "LoweredAtomicLoad64",
24738		argLen:         2,
24739		faultOnNilArg0: true,
24740		reg: regInfo{
24741			inputs: []inputInfo{
24742				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24743			},
24744			outputs: []outputInfo{
24745				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24746			},
24747		},
24748	},
24749	{
24750		name:           "LoweredAtomicStore8",
24751		argLen:         3,
24752		faultOnNilArg0: true,
24753		hasSideEffects: true,
24754		reg: regInfo{
24755			inputs: []inputInfo{
24756				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24757				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24758			},
24759		},
24760	},
24761	{
24762		name:           "LoweredAtomicStore32",
24763		argLen:         3,
24764		faultOnNilArg0: true,
24765		hasSideEffects: true,
24766		reg: regInfo{
24767			inputs: []inputInfo{
24768				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24769				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24770			},
24771		},
24772	},
24773	{
24774		name:           "LoweredAtomicStore64",
24775		argLen:         3,
24776		faultOnNilArg0: true,
24777		hasSideEffects: true,
24778		reg: regInfo{
24779			inputs: []inputInfo{
24780				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24781				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24782			},
24783		},
24784	},
24785	{
24786		name:           "LoweredAtomicStorezero32",
24787		argLen:         2,
24788		faultOnNilArg0: true,
24789		hasSideEffects: true,
24790		reg: regInfo{
24791			inputs: []inputInfo{
24792				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24793			},
24794		},
24795	},
24796	{
24797		name:           "LoweredAtomicStorezero64",
24798		argLen:         2,
24799		faultOnNilArg0: true,
24800		hasSideEffects: true,
24801		reg: regInfo{
24802			inputs: []inputInfo{
24803				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24804			},
24805		},
24806	},
24807	{
24808		name:            "LoweredAtomicExchange32",
24809		argLen:          3,
24810		resultNotInArgs: true,
24811		faultOnNilArg0:  true,
24812		hasSideEffects:  true,
24813		unsafePoint:     true,
24814		reg: regInfo{
24815			inputs: []inputInfo{
24816				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24817				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24818			},
24819			outputs: []outputInfo{
24820				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24821			},
24822		},
24823	},
24824	{
24825		name:            "LoweredAtomicExchange64",
24826		argLen:          3,
24827		resultNotInArgs: true,
24828		faultOnNilArg0:  true,
24829		hasSideEffects:  true,
24830		unsafePoint:     true,
24831		reg: regInfo{
24832			inputs: []inputInfo{
24833				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24834				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24835			},
24836			outputs: []outputInfo{
24837				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24838			},
24839		},
24840	},
24841	{
24842		name:            "LoweredAtomicAdd32",
24843		argLen:          3,
24844		resultNotInArgs: true,
24845		faultOnNilArg0:  true,
24846		hasSideEffects:  true,
24847		unsafePoint:     true,
24848		reg: regInfo{
24849			inputs: []inputInfo{
24850				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24851				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24852			},
24853			outputs: []outputInfo{
24854				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24855			},
24856		},
24857	},
24858	{
24859		name:            "LoweredAtomicAdd64",
24860		argLen:          3,
24861		resultNotInArgs: true,
24862		faultOnNilArg0:  true,
24863		hasSideEffects:  true,
24864		unsafePoint:     true,
24865		reg: regInfo{
24866			inputs: []inputInfo{
24867				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24868				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24869			},
24870			outputs: []outputInfo{
24871				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24872			},
24873		},
24874	},
24875	{
24876		name:            "LoweredAtomicAddconst32",
24877		auxType:         auxInt32,
24878		argLen:          2,
24879		resultNotInArgs: true,
24880		faultOnNilArg0:  true,
24881		hasSideEffects:  true,
24882		unsafePoint:     true,
24883		reg: regInfo{
24884			inputs: []inputInfo{
24885				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24886			},
24887			outputs: []outputInfo{
24888				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24889			},
24890		},
24891	},
24892	{
24893		name:            "LoweredAtomicAddconst64",
24894		auxType:         auxInt64,
24895		argLen:          2,
24896		resultNotInArgs: true,
24897		faultOnNilArg0:  true,
24898		hasSideEffects:  true,
24899		unsafePoint:     true,
24900		reg: regInfo{
24901			inputs: []inputInfo{
24902				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24903			},
24904			outputs: []outputInfo{
24905				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24906			},
24907		},
24908	},
24909	{
24910		name:            "LoweredAtomicCas32",
24911		argLen:          4,
24912		resultNotInArgs: true,
24913		faultOnNilArg0:  true,
24914		hasSideEffects:  true,
24915		unsafePoint:     true,
24916		reg: regInfo{
24917			inputs: []inputInfo{
24918				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24919				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24920				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24921			},
24922			outputs: []outputInfo{
24923				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24924			},
24925		},
24926	},
24927	{
24928		name:            "LoweredAtomicCas64",
24929		argLen:          4,
24930		resultNotInArgs: true,
24931		faultOnNilArg0:  true,
24932		hasSideEffects:  true,
24933		unsafePoint:     true,
24934		reg: regInfo{
24935			inputs: []inputInfo{
24936				{1, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24937				{2, 234881022},           // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24938				{0, 4611686018695823358}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 SP g R31 SB
24939			},
24940			outputs: []outputInfo{
24941				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24942			},
24943		},
24944	},
24945	{
24946		name:           "LoweredNilCheck",
24947		argLen:         2,
24948		nilCheck:       true,
24949		faultOnNilArg0: true,
24950		reg: regInfo{
24951			inputs: []inputInfo{
24952				{0, 234881022}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 g R31
24953			},
24954		},
24955	},
24956	{
24957		name:   "FPFlagTrue",
24958		argLen: 1,
24959		reg: regInfo{
24960			outputs: []outputInfo{
24961				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24962			},
24963		},
24964	},
24965	{
24966		name:   "FPFlagFalse",
24967		argLen: 1,
24968		reg: regInfo{
24969			outputs: []outputInfo{
24970				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24971			},
24972		},
24973	},
24974	{
24975		name:      "LoweredGetClosurePtr",
24976		argLen:    0,
24977		zeroWidth: true,
24978		reg: regInfo{
24979			outputs: []outputInfo{
24980				{0, 4194304}, // R22
24981			},
24982		},
24983	},
24984	{
24985		name:              "LoweredGetCallerSP",
24986		argLen:            0,
24987		rematerializeable: true,
24988		reg: regInfo{
24989			outputs: []outputInfo{
24990				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
24991			},
24992		},
24993	},
24994	{
24995		name:              "LoweredGetCallerPC",
24996		argLen:            0,
24997		rematerializeable: true,
24998		reg: regInfo{
24999			outputs: []outputInfo{
25000				{0, 167772158}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R24 R25 R31
25001			},
25002		},
25003	},
25004	{
25005		name:         "LoweredWB",
25006		auxType:      auxSym,
25007		argLen:       3,
25008		clobberFlags: true,
25009		symEffect:    SymNone,
25010		reg: regInfo{
25011			inputs: []inputInfo{
25012				{0, 1048576}, // R20
25013				{1, 2097152}, // R21
25014			},
25015			clobbers: 4611686018293170176, // R31 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 HI LO
25016		},
25017	},
25018	{
25019		name:    "LoweredPanicBoundsA",
25020		auxType: auxInt64,
25021		argLen:  3,
25022		call:    true,
25023		reg: regInfo{
25024			inputs: []inputInfo{
25025				{0, 8},  // R3
25026				{1, 16}, // R4
25027			},
25028		},
25029	},
25030	{
25031		name:    "LoweredPanicBoundsB",
25032		auxType: auxInt64,
25033		argLen:  3,
25034		call:    true,
25035		reg: regInfo{
25036			inputs: []inputInfo{
25037				{0, 4}, // R2
25038				{1, 8}, // R3
25039			},
25040		},
25041	},
25042	{
25043		name:    "LoweredPanicBoundsC",
25044		auxType: auxInt64,
25045		argLen:  3,
25046		call:    true,
25047		reg: regInfo{
25048			inputs: []inputInfo{
25049				{0, 2}, // R1
25050				{1, 4}, // R2
25051			},
25052		},
25053	},
25054
25055	{
25056		name:        "ADD",
25057		argLen:      2,
25058		commutative: true,
25059		asm:         ppc64.AADD,
25060		reg: regInfo{
25061			inputs: []inputInfo{
25062				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25063				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25064			},
25065			outputs: []outputInfo{
25066				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25067			},
25068		},
25069	},
25070	{
25071		name:    "ADDconst",
25072		auxType: auxInt64,
25073		argLen:  1,
25074		asm:     ppc64.AADD,
25075		reg: regInfo{
25076			inputs: []inputInfo{
25077				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25078			},
25079			outputs: []outputInfo{
25080				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25081			},
25082		},
25083	},
25084	{
25085		name:        "FADD",
25086		argLen:      2,
25087		commutative: true,
25088		asm:         ppc64.AFADD,
25089		reg: regInfo{
25090			inputs: []inputInfo{
25091				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25092				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25093			},
25094			outputs: []outputInfo{
25095				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25096			},
25097		},
25098	},
25099	{
25100		name:        "FADDS",
25101		argLen:      2,
25102		commutative: true,
25103		asm:         ppc64.AFADDS,
25104		reg: regInfo{
25105			inputs: []inputInfo{
25106				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25107				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25108			},
25109			outputs: []outputInfo{
25110				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25111			},
25112		},
25113	},
25114	{
25115		name:   "SUB",
25116		argLen: 2,
25117		asm:    ppc64.ASUB,
25118		reg: regInfo{
25119			inputs: []inputInfo{
25120				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25121				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25122			},
25123			outputs: []outputInfo{
25124				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25125			},
25126		},
25127	},
25128	{
25129		name:    "SUBFCconst",
25130		auxType: auxInt64,
25131		argLen:  1,
25132		asm:     ppc64.ASUBC,
25133		reg: regInfo{
25134			inputs: []inputInfo{
25135				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25136			},
25137			outputs: []outputInfo{
25138				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25139			},
25140		},
25141	},
25142	{
25143		name:   "FSUB",
25144		argLen: 2,
25145		asm:    ppc64.AFSUB,
25146		reg: regInfo{
25147			inputs: []inputInfo{
25148				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25149				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25150			},
25151			outputs: []outputInfo{
25152				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25153			},
25154		},
25155	},
25156	{
25157		name:   "FSUBS",
25158		argLen: 2,
25159		asm:    ppc64.AFSUBS,
25160		reg: regInfo{
25161			inputs: []inputInfo{
25162				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25163				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25164			},
25165			outputs: []outputInfo{
25166				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25167			},
25168		},
25169	},
25170	{
25171		name:        "MULLD",
25172		argLen:      2,
25173		commutative: true,
25174		asm:         ppc64.AMULLD,
25175		reg: regInfo{
25176			inputs: []inputInfo{
25177				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25178				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25179			},
25180			outputs: []outputInfo{
25181				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25182			},
25183		},
25184	},
25185	{
25186		name:        "MULLW",
25187		argLen:      2,
25188		commutative: true,
25189		asm:         ppc64.AMULLW,
25190		reg: regInfo{
25191			inputs: []inputInfo{
25192				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25193				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25194			},
25195			outputs: []outputInfo{
25196				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25197			},
25198		},
25199	},
25200	{
25201		name:    "MULLDconst",
25202		auxType: auxInt32,
25203		argLen:  1,
25204		asm:     ppc64.AMULLD,
25205		reg: regInfo{
25206			inputs: []inputInfo{
25207				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25208			},
25209			outputs: []outputInfo{
25210				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25211			},
25212		},
25213	},
25214	{
25215		name:    "MULLWconst",
25216		auxType: auxInt32,
25217		argLen:  1,
25218		asm:     ppc64.AMULLW,
25219		reg: regInfo{
25220			inputs: []inputInfo{
25221				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25222			},
25223			outputs: []outputInfo{
25224				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25225			},
25226		},
25227	},
25228	{
25229		name:   "MADDLD",
25230		argLen: 3,
25231		asm:    ppc64.AMADDLD,
25232		reg: regInfo{
25233			inputs: []inputInfo{
25234				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25235				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25236				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25237			},
25238			outputs: []outputInfo{
25239				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25240			},
25241		},
25242	},
25243	{
25244		name:        "MULHD",
25245		argLen:      2,
25246		commutative: true,
25247		asm:         ppc64.AMULHD,
25248		reg: regInfo{
25249			inputs: []inputInfo{
25250				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25251				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25252			},
25253			outputs: []outputInfo{
25254				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25255			},
25256		},
25257	},
25258	{
25259		name:        "MULHW",
25260		argLen:      2,
25261		commutative: true,
25262		asm:         ppc64.AMULHW,
25263		reg: regInfo{
25264			inputs: []inputInfo{
25265				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25266				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25267			},
25268			outputs: []outputInfo{
25269				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25270			},
25271		},
25272	},
25273	{
25274		name:        "MULHDU",
25275		argLen:      2,
25276		commutative: true,
25277		asm:         ppc64.AMULHDU,
25278		reg: regInfo{
25279			inputs: []inputInfo{
25280				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25281				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25282			},
25283			outputs: []outputInfo{
25284				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25285			},
25286		},
25287	},
25288	{
25289		name:        "MULHWU",
25290		argLen:      2,
25291		commutative: true,
25292		asm:         ppc64.AMULHWU,
25293		reg: regInfo{
25294			inputs: []inputInfo{
25295				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25296				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25297			},
25298			outputs: []outputInfo{
25299				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25300			},
25301		},
25302	},
25303	{
25304		name:            "LoweredMuluhilo",
25305		argLen:          2,
25306		resultNotInArgs: true,
25307		reg: regInfo{
25308			inputs: []inputInfo{
25309				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25310				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25311			},
25312			outputs: []outputInfo{
25313				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25314				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25315			},
25316		},
25317	},
25318	{
25319		name:        "FMUL",
25320		argLen:      2,
25321		commutative: true,
25322		asm:         ppc64.AFMUL,
25323		reg: regInfo{
25324			inputs: []inputInfo{
25325				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25326				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25327			},
25328			outputs: []outputInfo{
25329				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25330			},
25331		},
25332	},
25333	{
25334		name:        "FMULS",
25335		argLen:      2,
25336		commutative: true,
25337		asm:         ppc64.AFMULS,
25338		reg: regInfo{
25339			inputs: []inputInfo{
25340				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25341				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25342			},
25343			outputs: []outputInfo{
25344				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25345			},
25346		},
25347	},
25348	{
25349		name:   "FMADD",
25350		argLen: 3,
25351		asm:    ppc64.AFMADD,
25352		reg: regInfo{
25353			inputs: []inputInfo{
25354				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25355				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25356				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25357			},
25358			outputs: []outputInfo{
25359				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25360			},
25361		},
25362	},
25363	{
25364		name:   "FMADDS",
25365		argLen: 3,
25366		asm:    ppc64.AFMADDS,
25367		reg: regInfo{
25368			inputs: []inputInfo{
25369				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25370				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25371				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25372			},
25373			outputs: []outputInfo{
25374				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25375			},
25376		},
25377	},
25378	{
25379		name:   "FMSUB",
25380		argLen: 3,
25381		asm:    ppc64.AFMSUB,
25382		reg: regInfo{
25383			inputs: []inputInfo{
25384				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25385				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25386				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25387			},
25388			outputs: []outputInfo{
25389				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25390			},
25391		},
25392	},
25393	{
25394		name:   "FMSUBS",
25395		argLen: 3,
25396		asm:    ppc64.AFMSUBS,
25397		reg: regInfo{
25398			inputs: []inputInfo{
25399				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25400				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25401				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25402			},
25403			outputs: []outputInfo{
25404				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25405			},
25406		},
25407	},
25408	{
25409		name:   "SRAD",
25410		argLen: 2,
25411		asm:    ppc64.ASRAD,
25412		reg: regInfo{
25413			inputs: []inputInfo{
25414				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25415				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25416			},
25417			outputs: []outputInfo{
25418				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25419			},
25420		},
25421	},
25422	{
25423		name:   "SRAW",
25424		argLen: 2,
25425		asm:    ppc64.ASRAW,
25426		reg: regInfo{
25427			inputs: []inputInfo{
25428				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25429				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25430			},
25431			outputs: []outputInfo{
25432				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25433			},
25434		},
25435	},
25436	{
25437		name:   "SRD",
25438		argLen: 2,
25439		asm:    ppc64.ASRD,
25440		reg: regInfo{
25441			inputs: []inputInfo{
25442				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25443				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25444			},
25445			outputs: []outputInfo{
25446				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25447			},
25448		},
25449	},
25450	{
25451		name:   "SRW",
25452		argLen: 2,
25453		asm:    ppc64.ASRW,
25454		reg: regInfo{
25455			inputs: []inputInfo{
25456				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25457				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25458			},
25459			outputs: []outputInfo{
25460				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25461			},
25462		},
25463	},
25464	{
25465		name:   "SLD",
25466		argLen: 2,
25467		asm:    ppc64.ASLD,
25468		reg: regInfo{
25469			inputs: []inputInfo{
25470				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25471				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25472			},
25473			outputs: []outputInfo{
25474				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25475			},
25476		},
25477	},
25478	{
25479		name:   "SLW",
25480		argLen: 2,
25481		asm:    ppc64.ASLW,
25482		reg: regInfo{
25483			inputs: []inputInfo{
25484				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25485				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25486			},
25487			outputs: []outputInfo{
25488				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25489			},
25490		},
25491	},
25492	{
25493		name:   "ROTL",
25494		argLen: 2,
25495		asm:    ppc64.AROTL,
25496		reg: regInfo{
25497			inputs: []inputInfo{
25498				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25499				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25500			},
25501			outputs: []outputInfo{
25502				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25503			},
25504		},
25505	},
25506	{
25507		name:   "ROTLW",
25508		argLen: 2,
25509		asm:    ppc64.AROTLW,
25510		reg: regInfo{
25511			inputs: []inputInfo{
25512				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25513				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25514			},
25515			outputs: []outputInfo{
25516				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25517			},
25518		},
25519	},
25520	{
25521		name:    "RLDICL",
25522		auxType: auxInt32,
25523		argLen:  1,
25524		asm:     ppc64.ARLDICL,
25525		reg: regInfo{
25526			inputs: []inputInfo{
25527				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25528			},
25529			outputs: []outputInfo{
25530				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25531			},
25532		},
25533	},
25534	{
25535		name:    "CLRLSLWI",
25536		auxType: auxInt32,
25537		argLen:  1,
25538		asm:     ppc64.ACLRLSLWI,
25539		reg: regInfo{
25540			inputs: []inputInfo{
25541				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25542			},
25543			outputs: []outputInfo{
25544				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25545			},
25546		},
25547	},
25548	{
25549		name:    "CLRLSLDI",
25550		auxType: auxInt32,
25551		argLen:  1,
25552		asm:     ppc64.ACLRLSLDI,
25553		reg: regInfo{
25554			inputs: []inputInfo{
25555				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25556			},
25557			outputs: []outputInfo{
25558				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25559			},
25560		},
25561	},
25562	{
25563		name:            "LoweredAdd64Carry",
25564		argLen:          3,
25565		resultNotInArgs: true,
25566		reg: regInfo{
25567			inputs: []inputInfo{
25568				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25569				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25570				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25571			},
25572			outputs: []outputInfo{
25573				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25574				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25575			},
25576		},
25577	},
25578	{
25579		name:    "SRADconst",
25580		auxType: auxInt64,
25581		argLen:  1,
25582		asm:     ppc64.ASRAD,
25583		reg: regInfo{
25584			inputs: []inputInfo{
25585				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25586			},
25587			outputs: []outputInfo{
25588				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25589			},
25590		},
25591	},
25592	{
25593		name:    "SRAWconst",
25594		auxType: auxInt64,
25595		argLen:  1,
25596		asm:     ppc64.ASRAW,
25597		reg: regInfo{
25598			inputs: []inputInfo{
25599				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25600			},
25601			outputs: []outputInfo{
25602				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25603			},
25604		},
25605	},
25606	{
25607		name:    "SRDconst",
25608		auxType: auxInt64,
25609		argLen:  1,
25610		asm:     ppc64.ASRD,
25611		reg: regInfo{
25612			inputs: []inputInfo{
25613				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25614			},
25615			outputs: []outputInfo{
25616				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25617			},
25618		},
25619	},
25620	{
25621		name:    "SRWconst",
25622		auxType: auxInt64,
25623		argLen:  1,
25624		asm:     ppc64.ASRW,
25625		reg: regInfo{
25626			inputs: []inputInfo{
25627				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25628			},
25629			outputs: []outputInfo{
25630				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25631			},
25632		},
25633	},
25634	{
25635		name:    "SLDconst",
25636		auxType: auxInt64,
25637		argLen:  1,
25638		asm:     ppc64.ASLD,
25639		reg: regInfo{
25640			inputs: []inputInfo{
25641				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25642			},
25643			outputs: []outputInfo{
25644				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25645			},
25646		},
25647	},
25648	{
25649		name:    "SLWconst",
25650		auxType: auxInt64,
25651		argLen:  1,
25652		asm:     ppc64.ASLW,
25653		reg: regInfo{
25654			inputs: []inputInfo{
25655				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25656			},
25657			outputs: []outputInfo{
25658				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25659			},
25660		},
25661	},
25662	{
25663		name:    "ROTLconst",
25664		auxType: auxInt64,
25665		argLen:  1,
25666		asm:     ppc64.AROTL,
25667		reg: regInfo{
25668			inputs: []inputInfo{
25669				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25670			},
25671			outputs: []outputInfo{
25672				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25673			},
25674		},
25675	},
25676	{
25677		name:    "ROTLWconst",
25678		auxType: auxInt64,
25679		argLen:  1,
25680		asm:     ppc64.AROTLW,
25681		reg: regInfo{
25682			inputs: []inputInfo{
25683				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25684			},
25685			outputs: []outputInfo{
25686				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25687			},
25688		},
25689	},
25690	{
25691		name:    "EXTSWSLconst",
25692		auxType: auxInt64,
25693		argLen:  1,
25694		asm:     ppc64.AEXTSWSLI,
25695		reg: regInfo{
25696			inputs: []inputInfo{
25697				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25698			},
25699			outputs: []outputInfo{
25700				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25701			},
25702		},
25703	},
25704	{
25705		name:    "RLWINM",
25706		auxType: auxInt64,
25707		argLen:  1,
25708		asm:     ppc64.ARLWNM,
25709		reg: regInfo{
25710			inputs: []inputInfo{
25711				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25712			},
25713			outputs: []outputInfo{
25714				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25715			},
25716		},
25717	},
25718	{
25719		name:    "RLWNM",
25720		auxType: auxInt64,
25721		argLen:  2,
25722		asm:     ppc64.ARLWNM,
25723		reg: regInfo{
25724			inputs: []inputInfo{
25725				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25726				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25727			},
25728			outputs: []outputInfo{
25729				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25730			},
25731		},
25732	},
25733	{
25734		name:         "RLWMI",
25735		auxType:      auxInt64,
25736		argLen:       2,
25737		resultInArg0: true,
25738		asm:          ppc64.ARLWMI,
25739		reg: regInfo{
25740			inputs: []inputInfo{
25741				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25742				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25743			},
25744			outputs: []outputInfo{
25745				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25746			},
25747		},
25748	},
25749	{
25750		name:         "CNTLZD",
25751		argLen:       1,
25752		clobberFlags: true,
25753		asm:          ppc64.ACNTLZD,
25754		reg: regInfo{
25755			inputs: []inputInfo{
25756				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25757			},
25758			outputs: []outputInfo{
25759				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25760			},
25761		},
25762	},
25763	{
25764		name:         "CNTLZW",
25765		argLen:       1,
25766		clobberFlags: true,
25767		asm:          ppc64.ACNTLZW,
25768		reg: regInfo{
25769			inputs: []inputInfo{
25770				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25771			},
25772			outputs: []outputInfo{
25773				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25774			},
25775		},
25776	},
25777	{
25778		name:   "CNTTZD",
25779		argLen: 1,
25780		asm:    ppc64.ACNTTZD,
25781		reg: regInfo{
25782			inputs: []inputInfo{
25783				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25784			},
25785			outputs: []outputInfo{
25786				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25787			},
25788		},
25789	},
25790	{
25791		name:   "CNTTZW",
25792		argLen: 1,
25793		asm:    ppc64.ACNTTZW,
25794		reg: regInfo{
25795			inputs: []inputInfo{
25796				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25797			},
25798			outputs: []outputInfo{
25799				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25800			},
25801		},
25802	},
25803	{
25804		name:   "POPCNTD",
25805		argLen: 1,
25806		asm:    ppc64.APOPCNTD,
25807		reg: regInfo{
25808			inputs: []inputInfo{
25809				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25810			},
25811			outputs: []outputInfo{
25812				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25813			},
25814		},
25815	},
25816	{
25817		name:   "POPCNTW",
25818		argLen: 1,
25819		asm:    ppc64.APOPCNTW,
25820		reg: regInfo{
25821			inputs: []inputInfo{
25822				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25823			},
25824			outputs: []outputInfo{
25825				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25826			},
25827		},
25828	},
25829	{
25830		name:   "POPCNTB",
25831		argLen: 1,
25832		asm:    ppc64.APOPCNTB,
25833		reg: regInfo{
25834			inputs: []inputInfo{
25835				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25836			},
25837			outputs: []outputInfo{
25838				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25839			},
25840		},
25841	},
25842	{
25843		name:   "FDIV",
25844		argLen: 2,
25845		asm:    ppc64.AFDIV,
25846		reg: regInfo{
25847			inputs: []inputInfo{
25848				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25849				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25850			},
25851			outputs: []outputInfo{
25852				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25853			},
25854		},
25855	},
25856	{
25857		name:   "FDIVS",
25858		argLen: 2,
25859		asm:    ppc64.AFDIVS,
25860		reg: regInfo{
25861			inputs: []inputInfo{
25862				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25863				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25864			},
25865			outputs: []outputInfo{
25866				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25867			},
25868		},
25869	},
25870	{
25871		name:   "DIVD",
25872		argLen: 2,
25873		asm:    ppc64.ADIVD,
25874		reg: regInfo{
25875			inputs: []inputInfo{
25876				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25877				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25878			},
25879			outputs: []outputInfo{
25880				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25881			},
25882		},
25883	},
25884	{
25885		name:   "DIVW",
25886		argLen: 2,
25887		asm:    ppc64.ADIVW,
25888		reg: regInfo{
25889			inputs: []inputInfo{
25890				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25891				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25892			},
25893			outputs: []outputInfo{
25894				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25895			},
25896		},
25897	},
25898	{
25899		name:   "DIVDU",
25900		argLen: 2,
25901		asm:    ppc64.ADIVDU,
25902		reg: regInfo{
25903			inputs: []inputInfo{
25904				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25905				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25906			},
25907			outputs: []outputInfo{
25908				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25909			},
25910		},
25911	},
25912	{
25913		name:   "DIVWU",
25914		argLen: 2,
25915		asm:    ppc64.ADIVWU,
25916		reg: regInfo{
25917			inputs: []inputInfo{
25918				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25919				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25920			},
25921			outputs: []outputInfo{
25922				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25923			},
25924		},
25925	},
25926	{
25927		name:   "MODUD",
25928		argLen: 2,
25929		asm:    ppc64.AMODUD,
25930		reg: regInfo{
25931			inputs: []inputInfo{
25932				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25933				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25934			},
25935			outputs: []outputInfo{
25936				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25937			},
25938		},
25939	},
25940	{
25941		name:   "MODSD",
25942		argLen: 2,
25943		asm:    ppc64.AMODSD,
25944		reg: regInfo{
25945			inputs: []inputInfo{
25946				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25947				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25948			},
25949			outputs: []outputInfo{
25950				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25951			},
25952		},
25953	},
25954	{
25955		name:   "MODUW",
25956		argLen: 2,
25957		asm:    ppc64.AMODUW,
25958		reg: regInfo{
25959			inputs: []inputInfo{
25960				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25961				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25962			},
25963			outputs: []outputInfo{
25964				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25965			},
25966		},
25967	},
25968	{
25969		name:   "MODSW",
25970		argLen: 2,
25971		asm:    ppc64.AMODSW,
25972		reg: regInfo{
25973			inputs: []inputInfo{
25974				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25975				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25976			},
25977			outputs: []outputInfo{
25978				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
25979			},
25980		},
25981	},
25982	{
25983		name:   "FCTIDZ",
25984		argLen: 1,
25985		asm:    ppc64.AFCTIDZ,
25986		reg: regInfo{
25987			inputs: []inputInfo{
25988				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25989			},
25990			outputs: []outputInfo{
25991				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
25992			},
25993		},
25994	},
25995	{
25996		name:   "FCTIWZ",
25997		argLen: 1,
25998		asm:    ppc64.AFCTIWZ,
25999		reg: regInfo{
26000			inputs: []inputInfo{
26001				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26002			},
26003			outputs: []outputInfo{
26004				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26005			},
26006		},
26007	},
26008	{
26009		name:   "FCFID",
26010		argLen: 1,
26011		asm:    ppc64.AFCFID,
26012		reg: regInfo{
26013			inputs: []inputInfo{
26014				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26015			},
26016			outputs: []outputInfo{
26017				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26018			},
26019		},
26020	},
26021	{
26022		name:   "FCFIDS",
26023		argLen: 1,
26024		asm:    ppc64.AFCFIDS,
26025		reg: regInfo{
26026			inputs: []inputInfo{
26027				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26028			},
26029			outputs: []outputInfo{
26030				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26031			},
26032		},
26033	},
26034	{
26035		name:   "FRSP",
26036		argLen: 1,
26037		asm:    ppc64.AFRSP,
26038		reg: regInfo{
26039			inputs: []inputInfo{
26040				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26041			},
26042			outputs: []outputInfo{
26043				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26044			},
26045		},
26046	},
26047	{
26048		name:   "MFVSRD",
26049		argLen: 1,
26050		asm:    ppc64.AMFVSRD,
26051		reg: regInfo{
26052			inputs: []inputInfo{
26053				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26054			},
26055			outputs: []outputInfo{
26056				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26057			},
26058		},
26059	},
26060	{
26061		name:   "MTVSRD",
26062		argLen: 1,
26063		asm:    ppc64.AMTVSRD,
26064		reg: regInfo{
26065			inputs: []inputInfo{
26066				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26067			},
26068			outputs: []outputInfo{
26069				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26070			},
26071		},
26072	},
26073	{
26074		name:        "AND",
26075		argLen:      2,
26076		commutative: true,
26077		asm:         ppc64.AAND,
26078		reg: regInfo{
26079			inputs: []inputInfo{
26080				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26081				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26082			},
26083			outputs: []outputInfo{
26084				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26085			},
26086		},
26087	},
26088	{
26089		name:   "ANDN",
26090		argLen: 2,
26091		asm:    ppc64.AANDN,
26092		reg: regInfo{
26093			inputs: []inputInfo{
26094				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26095				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26096			},
26097			outputs: []outputInfo{
26098				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26099			},
26100		},
26101	},
26102	{
26103		name:        "ANDCC",
26104		argLen:      2,
26105		commutative: true,
26106		asm:         ppc64.AANDCC,
26107		reg: regInfo{
26108			inputs: []inputInfo{
26109				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26110				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26111			},
26112		},
26113	},
26114	{
26115		name:        "OR",
26116		argLen:      2,
26117		commutative: true,
26118		asm:         ppc64.AOR,
26119		reg: regInfo{
26120			inputs: []inputInfo{
26121				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26122				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26123			},
26124			outputs: []outputInfo{
26125				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26126			},
26127		},
26128	},
26129	{
26130		name:   "ORN",
26131		argLen: 2,
26132		asm:    ppc64.AORN,
26133		reg: regInfo{
26134			inputs: []inputInfo{
26135				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26136				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26137			},
26138			outputs: []outputInfo{
26139				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26140			},
26141		},
26142	},
26143	{
26144		name:        "ORCC",
26145		argLen:      2,
26146		commutative: true,
26147		asm:         ppc64.AORCC,
26148		reg: regInfo{
26149			inputs: []inputInfo{
26150				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26151				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26152			},
26153		},
26154	},
26155	{
26156		name:        "NOR",
26157		argLen:      2,
26158		commutative: true,
26159		asm:         ppc64.ANOR,
26160		reg: regInfo{
26161			inputs: []inputInfo{
26162				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26163				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26164			},
26165			outputs: []outputInfo{
26166				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26167			},
26168		},
26169	},
26170	{
26171		name:        "XOR",
26172		argLen:      2,
26173		commutative: true,
26174		asm:         ppc64.AXOR,
26175		reg: regInfo{
26176			inputs: []inputInfo{
26177				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26178				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26179			},
26180			outputs: []outputInfo{
26181				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26182			},
26183		},
26184	},
26185	{
26186		name:        "XORCC",
26187		argLen:      2,
26188		commutative: true,
26189		asm:         ppc64.AXORCC,
26190		reg: regInfo{
26191			inputs: []inputInfo{
26192				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26193				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26194			},
26195		},
26196	},
26197	{
26198		name:        "EQV",
26199		argLen:      2,
26200		commutative: true,
26201		asm:         ppc64.AEQV,
26202		reg: regInfo{
26203			inputs: []inputInfo{
26204				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26205				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26206			},
26207			outputs: []outputInfo{
26208				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26209			},
26210		},
26211	},
26212	{
26213		name:   "NEG",
26214		argLen: 1,
26215		asm:    ppc64.ANEG,
26216		reg: regInfo{
26217			inputs: []inputInfo{
26218				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26219			},
26220			outputs: []outputInfo{
26221				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26222			},
26223		},
26224	},
26225	{
26226		name:   "FNEG",
26227		argLen: 1,
26228		asm:    ppc64.AFNEG,
26229		reg: regInfo{
26230			inputs: []inputInfo{
26231				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26232			},
26233			outputs: []outputInfo{
26234				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26235			},
26236		},
26237	},
26238	{
26239		name:   "FSQRT",
26240		argLen: 1,
26241		asm:    ppc64.AFSQRT,
26242		reg: regInfo{
26243			inputs: []inputInfo{
26244				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26245			},
26246			outputs: []outputInfo{
26247				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26248			},
26249		},
26250	},
26251	{
26252		name:   "FSQRTS",
26253		argLen: 1,
26254		asm:    ppc64.AFSQRTS,
26255		reg: regInfo{
26256			inputs: []inputInfo{
26257				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26258			},
26259			outputs: []outputInfo{
26260				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26261			},
26262		},
26263	},
26264	{
26265		name:   "FFLOOR",
26266		argLen: 1,
26267		asm:    ppc64.AFRIM,
26268		reg: regInfo{
26269			inputs: []inputInfo{
26270				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26271			},
26272			outputs: []outputInfo{
26273				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26274			},
26275		},
26276	},
26277	{
26278		name:   "FCEIL",
26279		argLen: 1,
26280		asm:    ppc64.AFRIP,
26281		reg: regInfo{
26282			inputs: []inputInfo{
26283				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26284			},
26285			outputs: []outputInfo{
26286				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26287			},
26288		},
26289	},
26290	{
26291		name:   "FTRUNC",
26292		argLen: 1,
26293		asm:    ppc64.AFRIZ,
26294		reg: regInfo{
26295			inputs: []inputInfo{
26296				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26297			},
26298			outputs: []outputInfo{
26299				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26300			},
26301		},
26302	},
26303	{
26304		name:   "FROUND",
26305		argLen: 1,
26306		asm:    ppc64.AFRIN,
26307		reg: regInfo{
26308			inputs: []inputInfo{
26309				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26310			},
26311			outputs: []outputInfo{
26312				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26313			},
26314		},
26315	},
26316	{
26317		name:   "FABS",
26318		argLen: 1,
26319		asm:    ppc64.AFABS,
26320		reg: regInfo{
26321			inputs: []inputInfo{
26322				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26323			},
26324			outputs: []outputInfo{
26325				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26326			},
26327		},
26328	},
26329	{
26330		name:   "FNABS",
26331		argLen: 1,
26332		asm:    ppc64.AFNABS,
26333		reg: regInfo{
26334			inputs: []inputInfo{
26335				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26336			},
26337			outputs: []outputInfo{
26338				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26339			},
26340		},
26341	},
26342	{
26343		name:   "FCPSGN",
26344		argLen: 2,
26345		asm:    ppc64.AFCPSGN,
26346		reg: regInfo{
26347			inputs: []inputInfo{
26348				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26349				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26350			},
26351			outputs: []outputInfo{
26352				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26353			},
26354		},
26355	},
26356	{
26357		name:    "ORconst",
26358		auxType: auxInt64,
26359		argLen:  1,
26360		asm:     ppc64.AOR,
26361		reg: regInfo{
26362			inputs: []inputInfo{
26363				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26364			},
26365			outputs: []outputInfo{
26366				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26367			},
26368		},
26369	},
26370	{
26371		name:    "XORconst",
26372		auxType: auxInt64,
26373		argLen:  1,
26374		asm:     ppc64.AXOR,
26375		reg: regInfo{
26376			inputs: []inputInfo{
26377				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26378			},
26379			outputs: []outputInfo{
26380				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26381			},
26382		},
26383	},
26384	{
26385		name:         "ANDconst",
26386		auxType:      auxInt64,
26387		argLen:       1,
26388		clobberFlags: true,
26389		asm:          ppc64.AANDCC,
26390		reg: regInfo{
26391			inputs: []inputInfo{
26392				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26393			},
26394			outputs: []outputInfo{
26395				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26396			},
26397		},
26398	},
26399	{
26400		name:    "ANDCCconst",
26401		auxType: auxInt64,
26402		argLen:  1,
26403		asm:     ppc64.AANDCC,
26404		reg: regInfo{
26405			inputs: []inputInfo{
26406				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26407			},
26408		},
26409	},
26410	{
26411		name:   "MOVBreg",
26412		argLen: 1,
26413		asm:    ppc64.AMOVB,
26414		reg: regInfo{
26415			inputs: []inputInfo{
26416				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26417			},
26418			outputs: []outputInfo{
26419				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26420			},
26421		},
26422	},
26423	{
26424		name:   "MOVBZreg",
26425		argLen: 1,
26426		asm:    ppc64.AMOVBZ,
26427		reg: regInfo{
26428			inputs: []inputInfo{
26429				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26430			},
26431			outputs: []outputInfo{
26432				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26433			},
26434		},
26435	},
26436	{
26437		name:   "MOVHreg",
26438		argLen: 1,
26439		asm:    ppc64.AMOVH,
26440		reg: regInfo{
26441			inputs: []inputInfo{
26442				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26443			},
26444			outputs: []outputInfo{
26445				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26446			},
26447		},
26448	},
26449	{
26450		name:   "MOVHZreg",
26451		argLen: 1,
26452		asm:    ppc64.AMOVHZ,
26453		reg: regInfo{
26454			inputs: []inputInfo{
26455				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26456			},
26457			outputs: []outputInfo{
26458				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26459			},
26460		},
26461	},
26462	{
26463		name:   "MOVWreg",
26464		argLen: 1,
26465		asm:    ppc64.AMOVW,
26466		reg: regInfo{
26467			inputs: []inputInfo{
26468				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26469			},
26470			outputs: []outputInfo{
26471				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26472			},
26473		},
26474	},
26475	{
26476		name:   "MOVWZreg",
26477		argLen: 1,
26478		asm:    ppc64.AMOVWZ,
26479		reg: regInfo{
26480			inputs: []inputInfo{
26481				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26482			},
26483			outputs: []outputInfo{
26484				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26485			},
26486		},
26487	},
26488	{
26489		name:           "MOVBZload",
26490		auxType:        auxSymOff,
26491		argLen:         2,
26492		faultOnNilArg0: true,
26493		symEffect:      SymRead,
26494		asm:            ppc64.AMOVBZ,
26495		reg: regInfo{
26496			inputs: []inputInfo{
26497				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26498			},
26499			outputs: []outputInfo{
26500				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26501			},
26502		},
26503	},
26504	{
26505		name:           "MOVHload",
26506		auxType:        auxSymOff,
26507		argLen:         2,
26508		faultOnNilArg0: true,
26509		symEffect:      SymRead,
26510		asm:            ppc64.AMOVH,
26511		reg: regInfo{
26512			inputs: []inputInfo{
26513				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26514			},
26515			outputs: []outputInfo{
26516				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26517			},
26518		},
26519	},
26520	{
26521		name:           "MOVHZload",
26522		auxType:        auxSymOff,
26523		argLen:         2,
26524		faultOnNilArg0: true,
26525		symEffect:      SymRead,
26526		asm:            ppc64.AMOVHZ,
26527		reg: regInfo{
26528			inputs: []inputInfo{
26529				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26530			},
26531			outputs: []outputInfo{
26532				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26533			},
26534		},
26535	},
26536	{
26537		name:           "MOVWload",
26538		auxType:        auxSymOff,
26539		argLen:         2,
26540		faultOnNilArg0: true,
26541		symEffect:      SymRead,
26542		asm:            ppc64.AMOVW,
26543		reg: regInfo{
26544			inputs: []inputInfo{
26545				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26546			},
26547			outputs: []outputInfo{
26548				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26549			},
26550		},
26551	},
26552	{
26553		name:           "MOVWZload",
26554		auxType:        auxSymOff,
26555		argLen:         2,
26556		faultOnNilArg0: true,
26557		symEffect:      SymRead,
26558		asm:            ppc64.AMOVWZ,
26559		reg: regInfo{
26560			inputs: []inputInfo{
26561				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26562			},
26563			outputs: []outputInfo{
26564				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26565			},
26566		},
26567	},
26568	{
26569		name:           "MOVDload",
26570		auxType:        auxSymOff,
26571		argLen:         2,
26572		faultOnNilArg0: true,
26573		symEffect:      SymRead,
26574		asm:            ppc64.AMOVD,
26575		reg: regInfo{
26576			inputs: []inputInfo{
26577				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26578			},
26579			outputs: []outputInfo{
26580				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26581			},
26582		},
26583	},
26584	{
26585		name:           "MOVDBRload",
26586		auxType:        auxSymOff,
26587		argLen:         2,
26588		faultOnNilArg0: true,
26589		symEffect:      SymRead,
26590		asm:            ppc64.AMOVDBR,
26591		reg: regInfo{
26592			inputs: []inputInfo{
26593				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26594			},
26595			outputs: []outputInfo{
26596				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26597			},
26598		},
26599	},
26600	{
26601		name:           "MOVWBRload",
26602		auxType:        auxSymOff,
26603		argLen:         2,
26604		faultOnNilArg0: true,
26605		symEffect:      SymRead,
26606		asm:            ppc64.AMOVWBR,
26607		reg: regInfo{
26608			inputs: []inputInfo{
26609				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26610			},
26611			outputs: []outputInfo{
26612				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26613			},
26614		},
26615	},
26616	{
26617		name:           "MOVHBRload",
26618		auxType:        auxSymOff,
26619		argLen:         2,
26620		faultOnNilArg0: true,
26621		symEffect:      SymRead,
26622		asm:            ppc64.AMOVHBR,
26623		reg: regInfo{
26624			inputs: []inputInfo{
26625				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26626			},
26627			outputs: []outputInfo{
26628				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26629			},
26630		},
26631	},
26632	{
26633		name:   "MOVBZloadidx",
26634		argLen: 3,
26635		asm:    ppc64.AMOVBZ,
26636		reg: regInfo{
26637			inputs: []inputInfo{
26638				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26639				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26640			},
26641			outputs: []outputInfo{
26642				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26643			},
26644		},
26645	},
26646	{
26647		name:   "MOVHloadidx",
26648		argLen: 3,
26649		asm:    ppc64.AMOVH,
26650		reg: regInfo{
26651			inputs: []inputInfo{
26652				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26653				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26654			},
26655			outputs: []outputInfo{
26656				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26657			},
26658		},
26659	},
26660	{
26661		name:   "MOVHZloadidx",
26662		argLen: 3,
26663		asm:    ppc64.AMOVHZ,
26664		reg: regInfo{
26665			inputs: []inputInfo{
26666				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26667				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26668			},
26669			outputs: []outputInfo{
26670				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26671			},
26672		},
26673	},
26674	{
26675		name:   "MOVWloadidx",
26676		argLen: 3,
26677		asm:    ppc64.AMOVW,
26678		reg: regInfo{
26679			inputs: []inputInfo{
26680				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26681				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26682			},
26683			outputs: []outputInfo{
26684				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26685			},
26686		},
26687	},
26688	{
26689		name:   "MOVWZloadidx",
26690		argLen: 3,
26691		asm:    ppc64.AMOVWZ,
26692		reg: regInfo{
26693			inputs: []inputInfo{
26694				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26695				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26696			},
26697			outputs: []outputInfo{
26698				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26699			},
26700		},
26701	},
26702	{
26703		name:   "MOVDloadidx",
26704		argLen: 3,
26705		asm:    ppc64.AMOVD,
26706		reg: regInfo{
26707			inputs: []inputInfo{
26708				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26709				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26710			},
26711			outputs: []outputInfo{
26712				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26713			},
26714		},
26715	},
26716	{
26717		name:   "MOVHBRloadidx",
26718		argLen: 3,
26719		asm:    ppc64.AMOVHBR,
26720		reg: regInfo{
26721			inputs: []inputInfo{
26722				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26723				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26724			},
26725			outputs: []outputInfo{
26726				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26727			},
26728		},
26729	},
26730	{
26731		name:   "MOVWBRloadidx",
26732		argLen: 3,
26733		asm:    ppc64.AMOVWBR,
26734		reg: regInfo{
26735			inputs: []inputInfo{
26736				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26737				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26738			},
26739			outputs: []outputInfo{
26740				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26741			},
26742		},
26743	},
26744	{
26745		name:   "MOVDBRloadidx",
26746		argLen: 3,
26747		asm:    ppc64.AMOVDBR,
26748		reg: regInfo{
26749			inputs: []inputInfo{
26750				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26751				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26752			},
26753			outputs: []outputInfo{
26754				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26755			},
26756		},
26757	},
26758	{
26759		name:   "FMOVDloadidx",
26760		argLen: 3,
26761		asm:    ppc64.AFMOVD,
26762		reg: regInfo{
26763			inputs: []inputInfo{
26764				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26765				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26766			},
26767			outputs: []outputInfo{
26768				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26769			},
26770		},
26771	},
26772	{
26773		name:   "FMOVSloadidx",
26774		argLen: 3,
26775		asm:    ppc64.AFMOVS,
26776		reg: regInfo{
26777			inputs: []inputInfo{
26778				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26779				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26780			},
26781			outputs: []outputInfo{
26782				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26783			},
26784		},
26785	},
26786	{
26787		name:           "DCBT",
26788		auxType:        auxInt64,
26789		argLen:         2,
26790		hasSideEffects: true,
26791		asm:            ppc64.ADCBT,
26792		reg: regInfo{
26793			inputs: []inputInfo{
26794				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26795			},
26796		},
26797	},
26798	{
26799		name:           "MOVDBRstore",
26800		auxType:        auxSym,
26801		argLen:         3,
26802		faultOnNilArg0: true,
26803		symEffect:      SymWrite,
26804		asm:            ppc64.AMOVDBR,
26805		reg: regInfo{
26806			inputs: []inputInfo{
26807				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26808				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26809			},
26810		},
26811	},
26812	{
26813		name:           "MOVWBRstore",
26814		auxType:        auxSym,
26815		argLen:         3,
26816		faultOnNilArg0: true,
26817		symEffect:      SymWrite,
26818		asm:            ppc64.AMOVWBR,
26819		reg: regInfo{
26820			inputs: []inputInfo{
26821				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26822				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26823			},
26824		},
26825	},
26826	{
26827		name:           "MOVHBRstore",
26828		auxType:        auxSym,
26829		argLen:         3,
26830		faultOnNilArg0: true,
26831		symEffect:      SymWrite,
26832		asm:            ppc64.AMOVHBR,
26833		reg: regInfo{
26834			inputs: []inputInfo{
26835				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26836				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26837			},
26838		},
26839	},
26840	{
26841		name:           "FMOVDload",
26842		auxType:        auxSymOff,
26843		argLen:         2,
26844		faultOnNilArg0: true,
26845		symEffect:      SymRead,
26846		asm:            ppc64.AFMOVD,
26847		reg: regInfo{
26848			inputs: []inputInfo{
26849				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26850			},
26851			outputs: []outputInfo{
26852				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26853			},
26854		},
26855	},
26856	{
26857		name:           "FMOVSload",
26858		auxType:        auxSymOff,
26859		argLen:         2,
26860		faultOnNilArg0: true,
26861		symEffect:      SymRead,
26862		asm:            ppc64.AFMOVS,
26863		reg: regInfo{
26864			inputs: []inputInfo{
26865				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26866			},
26867			outputs: []outputInfo{
26868				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26869			},
26870		},
26871	},
26872	{
26873		name:           "MOVBstore",
26874		auxType:        auxSymOff,
26875		argLen:         3,
26876		faultOnNilArg0: true,
26877		symEffect:      SymWrite,
26878		asm:            ppc64.AMOVB,
26879		reg: regInfo{
26880			inputs: []inputInfo{
26881				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26882				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26883			},
26884		},
26885	},
26886	{
26887		name:           "MOVHstore",
26888		auxType:        auxSymOff,
26889		argLen:         3,
26890		faultOnNilArg0: true,
26891		symEffect:      SymWrite,
26892		asm:            ppc64.AMOVH,
26893		reg: regInfo{
26894			inputs: []inputInfo{
26895				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26896				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26897			},
26898		},
26899	},
26900	{
26901		name:           "MOVWstore",
26902		auxType:        auxSymOff,
26903		argLen:         3,
26904		faultOnNilArg0: true,
26905		symEffect:      SymWrite,
26906		asm:            ppc64.AMOVW,
26907		reg: regInfo{
26908			inputs: []inputInfo{
26909				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26910				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26911			},
26912		},
26913	},
26914	{
26915		name:           "MOVDstore",
26916		auxType:        auxSymOff,
26917		argLen:         3,
26918		faultOnNilArg0: true,
26919		symEffect:      SymWrite,
26920		asm:            ppc64.AMOVD,
26921		reg: regInfo{
26922			inputs: []inputInfo{
26923				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26924				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26925			},
26926		},
26927	},
26928	{
26929		name:           "FMOVDstore",
26930		auxType:        auxSymOff,
26931		argLen:         3,
26932		faultOnNilArg0: true,
26933		symEffect:      SymWrite,
26934		asm:            ppc64.AFMOVD,
26935		reg: regInfo{
26936			inputs: []inputInfo{
26937				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26938				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26939			},
26940		},
26941	},
26942	{
26943		name:           "FMOVSstore",
26944		auxType:        auxSymOff,
26945		argLen:         3,
26946		faultOnNilArg0: true,
26947		symEffect:      SymWrite,
26948		asm:            ppc64.AFMOVS,
26949		reg: regInfo{
26950			inputs: []inputInfo{
26951				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
26952				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26953			},
26954		},
26955	},
26956	{
26957		name:   "MOVBstoreidx",
26958		argLen: 4,
26959		asm:    ppc64.AMOVB,
26960		reg: regInfo{
26961			inputs: []inputInfo{
26962				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26963				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26964				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26965			},
26966		},
26967	},
26968	{
26969		name:   "MOVHstoreidx",
26970		argLen: 4,
26971		asm:    ppc64.AMOVH,
26972		reg: regInfo{
26973			inputs: []inputInfo{
26974				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26975				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26976				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26977			},
26978		},
26979	},
26980	{
26981		name:   "MOVWstoreidx",
26982		argLen: 4,
26983		asm:    ppc64.AMOVW,
26984		reg: regInfo{
26985			inputs: []inputInfo{
26986				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26987				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26988				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26989			},
26990		},
26991	},
26992	{
26993		name:   "MOVDstoreidx",
26994		argLen: 4,
26995		asm:    ppc64.AMOVD,
26996		reg: regInfo{
26997			inputs: []inputInfo{
26998				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
26999				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27000				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27001			},
27002		},
27003	},
27004	{
27005		name:   "FMOVDstoreidx",
27006		argLen: 4,
27007		asm:    ppc64.AFMOVD,
27008		reg: regInfo{
27009			inputs: []inputInfo{
27010				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27011				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27012				{1, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27013			},
27014		},
27015	},
27016	{
27017		name:   "FMOVSstoreidx",
27018		argLen: 4,
27019		asm:    ppc64.AFMOVS,
27020		reg: regInfo{
27021			inputs: []inputInfo{
27022				{2, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27023				{0, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27024				{1, 1073733630},         // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27025			},
27026		},
27027	},
27028	{
27029		name:   "MOVHBRstoreidx",
27030		argLen: 4,
27031		asm:    ppc64.AMOVHBR,
27032		reg: regInfo{
27033			inputs: []inputInfo{
27034				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27035				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27036				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27037			},
27038		},
27039	},
27040	{
27041		name:   "MOVWBRstoreidx",
27042		argLen: 4,
27043		asm:    ppc64.AMOVWBR,
27044		reg: regInfo{
27045			inputs: []inputInfo{
27046				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27047				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27048				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27049			},
27050		},
27051	},
27052	{
27053		name:   "MOVDBRstoreidx",
27054		argLen: 4,
27055		asm:    ppc64.AMOVDBR,
27056		reg: regInfo{
27057			inputs: []inputInfo{
27058				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27059				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27060				{2, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27061			},
27062		},
27063	},
27064	{
27065		name:           "MOVBstorezero",
27066		auxType:        auxSymOff,
27067		argLen:         2,
27068		faultOnNilArg0: true,
27069		symEffect:      SymWrite,
27070		asm:            ppc64.AMOVB,
27071		reg: regInfo{
27072			inputs: []inputInfo{
27073				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27074			},
27075		},
27076	},
27077	{
27078		name:           "MOVHstorezero",
27079		auxType:        auxSymOff,
27080		argLen:         2,
27081		faultOnNilArg0: true,
27082		symEffect:      SymWrite,
27083		asm:            ppc64.AMOVH,
27084		reg: regInfo{
27085			inputs: []inputInfo{
27086				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27087			},
27088		},
27089	},
27090	{
27091		name:           "MOVWstorezero",
27092		auxType:        auxSymOff,
27093		argLen:         2,
27094		faultOnNilArg0: true,
27095		symEffect:      SymWrite,
27096		asm:            ppc64.AMOVW,
27097		reg: regInfo{
27098			inputs: []inputInfo{
27099				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27100			},
27101		},
27102	},
27103	{
27104		name:           "MOVDstorezero",
27105		auxType:        auxSymOff,
27106		argLen:         2,
27107		faultOnNilArg0: true,
27108		symEffect:      SymWrite,
27109		asm:            ppc64.AMOVD,
27110		reg: regInfo{
27111			inputs: []inputInfo{
27112				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27113			},
27114		},
27115	},
27116	{
27117		name:              "MOVDaddr",
27118		auxType:           auxSymOff,
27119		argLen:            1,
27120		rematerializeable: true,
27121		symEffect:         SymAddr,
27122		asm:               ppc64.AMOVD,
27123		reg: regInfo{
27124			inputs: []inputInfo{
27125				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27126			},
27127			outputs: []outputInfo{
27128				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27129			},
27130		},
27131	},
27132	{
27133		name:              "MOVDconst",
27134		auxType:           auxInt64,
27135		argLen:            0,
27136		rematerializeable: true,
27137		asm:               ppc64.AMOVD,
27138		reg: regInfo{
27139			outputs: []outputInfo{
27140				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27141			},
27142		},
27143	},
27144	{
27145		name:              "FMOVDconst",
27146		auxType:           auxFloat64,
27147		argLen:            0,
27148		rematerializeable: true,
27149		asm:               ppc64.AFMOVD,
27150		reg: regInfo{
27151			outputs: []outputInfo{
27152				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27153			},
27154		},
27155	},
27156	{
27157		name:              "FMOVSconst",
27158		auxType:           auxFloat32,
27159		argLen:            0,
27160		rematerializeable: true,
27161		asm:               ppc64.AFMOVS,
27162		reg: regInfo{
27163			outputs: []outputInfo{
27164				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27165			},
27166		},
27167	},
27168	{
27169		name:   "FCMPU",
27170		argLen: 2,
27171		asm:    ppc64.AFCMPU,
27172		reg: regInfo{
27173			inputs: []inputInfo{
27174				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27175				{1, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27176			},
27177		},
27178	},
27179	{
27180		name:   "CMP",
27181		argLen: 2,
27182		asm:    ppc64.ACMP,
27183		reg: regInfo{
27184			inputs: []inputInfo{
27185				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27186				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27187			},
27188		},
27189	},
27190	{
27191		name:   "CMPU",
27192		argLen: 2,
27193		asm:    ppc64.ACMPU,
27194		reg: regInfo{
27195			inputs: []inputInfo{
27196				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27197				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27198			},
27199		},
27200	},
27201	{
27202		name:   "CMPW",
27203		argLen: 2,
27204		asm:    ppc64.ACMPW,
27205		reg: regInfo{
27206			inputs: []inputInfo{
27207				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27208				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27209			},
27210		},
27211	},
27212	{
27213		name:   "CMPWU",
27214		argLen: 2,
27215		asm:    ppc64.ACMPWU,
27216		reg: regInfo{
27217			inputs: []inputInfo{
27218				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27219				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27220			},
27221		},
27222	},
27223	{
27224		name:    "CMPconst",
27225		auxType: auxInt64,
27226		argLen:  1,
27227		asm:     ppc64.ACMP,
27228		reg: regInfo{
27229			inputs: []inputInfo{
27230				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27231			},
27232		},
27233	},
27234	{
27235		name:    "CMPUconst",
27236		auxType: auxInt64,
27237		argLen:  1,
27238		asm:     ppc64.ACMPU,
27239		reg: regInfo{
27240			inputs: []inputInfo{
27241				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27242			},
27243		},
27244	},
27245	{
27246		name:    "CMPWconst",
27247		auxType: auxInt32,
27248		argLen:  1,
27249		asm:     ppc64.ACMPW,
27250		reg: regInfo{
27251			inputs: []inputInfo{
27252				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27253			},
27254		},
27255	},
27256	{
27257		name:    "CMPWUconst",
27258		auxType: auxInt32,
27259		argLen:  1,
27260		asm:     ppc64.ACMPWU,
27261		reg: regInfo{
27262			inputs: []inputInfo{
27263				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27264			},
27265		},
27266	},
27267	{
27268		name:    "ISEL",
27269		auxType: auxInt32,
27270		argLen:  3,
27271		asm:     ppc64.AISEL,
27272		reg: regInfo{
27273			inputs: []inputInfo{
27274				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27275				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27276			},
27277			outputs: []outputInfo{
27278				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27279			},
27280		},
27281	},
27282	{
27283		name:    "ISELB",
27284		auxType: auxInt32,
27285		argLen:  2,
27286		asm:     ppc64.AISEL,
27287		reg: regInfo{
27288			inputs: []inputInfo{
27289				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27290			},
27291			outputs: []outputInfo{
27292				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27293			},
27294		},
27295	},
27296	{
27297		name:   "Equal",
27298		argLen: 1,
27299		reg: regInfo{
27300			outputs: []outputInfo{
27301				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27302			},
27303		},
27304	},
27305	{
27306		name:   "NotEqual",
27307		argLen: 1,
27308		reg: regInfo{
27309			outputs: []outputInfo{
27310				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27311			},
27312		},
27313	},
27314	{
27315		name:   "LessThan",
27316		argLen: 1,
27317		reg: regInfo{
27318			outputs: []outputInfo{
27319				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27320			},
27321		},
27322	},
27323	{
27324		name:   "FLessThan",
27325		argLen: 1,
27326		reg: regInfo{
27327			outputs: []outputInfo{
27328				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27329			},
27330		},
27331	},
27332	{
27333		name:   "LessEqual",
27334		argLen: 1,
27335		reg: regInfo{
27336			outputs: []outputInfo{
27337				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27338			},
27339		},
27340	},
27341	{
27342		name:   "FLessEqual",
27343		argLen: 1,
27344		reg: regInfo{
27345			outputs: []outputInfo{
27346				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27347			},
27348		},
27349	},
27350	{
27351		name:   "GreaterThan",
27352		argLen: 1,
27353		reg: regInfo{
27354			outputs: []outputInfo{
27355				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27356			},
27357		},
27358	},
27359	{
27360		name:   "FGreaterThan",
27361		argLen: 1,
27362		reg: regInfo{
27363			outputs: []outputInfo{
27364				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27365			},
27366		},
27367	},
27368	{
27369		name:   "GreaterEqual",
27370		argLen: 1,
27371		reg: regInfo{
27372			outputs: []outputInfo{
27373				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27374			},
27375		},
27376	},
27377	{
27378		name:   "FGreaterEqual",
27379		argLen: 1,
27380		reg: regInfo{
27381			outputs: []outputInfo{
27382				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27383			},
27384		},
27385	},
27386	{
27387		name:      "LoweredGetClosurePtr",
27388		argLen:    0,
27389		zeroWidth: true,
27390		reg: regInfo{
27391			outputs: []outputInfo{
27392				{0, 2048}, // R11
27393			},
27394		},
27395	},
27396	{
27397		name:              "LoweredGetCallerSP",
27398		argLen:            0,
27399		rematerializeable: true,
27400		reg: regInfo{
27401			outputs: []outputInfo{
27402				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27403			},
27404		},
27405	},
27406	{
27407		name:              "LoweredGetCallerPC",
27408		argLen:            0,
27409		rematerializeable: true,
27410		reg: regInfo{
27411			outputs: []outputInfo{
27412				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27413			},
27414		},
27415	},
27416	{
27417		name:           "LoweredNilCheck",
27418		argLen:         2,
27419		clobberFlags:   true,
27420		nilCheck:       true,
27421		faultOnNilArg0: true,
27422		reg: regInfo{
27423			inputs: []inputInfo{
27424				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27425			},
27426			clobbers: 2147483648, // R31
27427		},
27428	},
27429	{
27430		name:         "LoweredRound32F",
27431		argLen:       1,
27432		resultInArg0: true,
27433		zeroWidth:    true,
27434		reg: regInfo{
27435			inputs: []inputInfo{
27436				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27437			},
27438			outputs: []outputInfo{
27439				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27440			},
27441		},
27442	},
27443	{
27444		name:         "LoweredRound64F",
27445		argLen:       1,
27446		resultInArg0: true,
27447		zeroWidth:    true,
27448		reg: regInfo{
27449			inputs: []inputInfo{
27450				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27451			},
27452			outputs: []outputInfo{
27453				{0, 576460743713488896}, // F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27454			},
27455		},
27456	},
27457	{
27458		name:         "CALLstatic",
27459		auxType:      auxCallOff,
27460		argLen:       -1,
27461		clobberFlags: true,
27462		call:         true,
27463		reg: regInfo{
27464			clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27465		},
27466	},
27467	{
27468		name:         "CALLtail",
27469		auxType:      auxCallOff,
27470		argLen:       -1,
27471		clobberFlags: true,
27472		call:         true,
27473		tailCall:     true,
27474		reg: regInfo{
27475			clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27476		},
27477	},
27478	{
27479		name:         "CALLclosure",
27480		auxType:      auxCallOff,
27481		argLen:       -1,
27482		clobberFlags: true,
27483		call:         true,
27484		reg: regInfo{
27485			inputs: []inputInfo{
27486				{0, 4096}, // R12
27487				{1, 2048}, // R11
27488			},
27489			clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27490		},
27491	},
27492	{
27493		name:         "CALLinter",
27494		auxType:      auxCallOff,
27495		argLen:       -1,
27496		clobberFlags: true,
27497		call:         true,
27498		reg: regInfo{
27499			inputs: []inputInfo{
27500				{0, 4096}, // R12
27501			},
27502			clobbers: 576460745860964344, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 g F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27503		},
27504	},
27505	{
27506		name:           "LoweredZero",
27507		auxType:        auxInt64,
27508		argLen:         2,
27509		clobberFlags:   true,
27510		faultOnNilArg0: true,
27511		unsafePoint:    true,
27512		reg: regInfo{
27513			inputs: []inputInfo{
27514				{0, 1048576}, // R20
27515			},
27516			clobbers: 1048576, // R20
27517		},
27518	},
27519	{
27520		name:           "LoweredZeroShort",
27521		auxType:        auxInt64,
27522		argLen:         2,
27523		faultOnNilArg0: true,
27524		unsafePoint:    true,
27525		reg: regInfo{
27526			inputs: []inputInfo{
27527				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27528			},
27529		},
27530	},
27531	{
27532		name:           "LoweredQuadZeroShort",
27533		auxType:        auxInt64,
27534		argLen:         2,
27535		faultOnNilArg0: true,
27536		unsafePoint:    true,
27537		reg: regInfo{
27538			inputs: []inputInfo{
27539				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27540			},
27541		},
27542	},
27543	{
27544		name:           "LoweredQuadZero",
27545		auxType:        auxInt64,
27546		argLen:         2,
27547		clobberFlags:   true,
27548		faultOnNilArg0: true,
27549		unsafePoint:    true,
27550		reg: regInfo{
27551			inputs: []inputInfo{
27552				{0, 1048576}, // R20
27553			},
27554			clobbers: 1048576, // R20
27555		},
27556	},
27557	{
27558		name:           "LoweredMove",
27559		auxType:        auxInt64,
27560		argLen:         3,
27561		clobberFlags:   true,
27562		faultOnNilArg0: true,
27563		faultOnNilArg1: true,
27564		unsafePoint:    true,
27565		reg: regInfo{
27566			inputs: []inputInfo{
27567				{0, 1048576}, // R20
27568				{1, 2097152}, // R21
27569			},
27570			clobbers: 3145728, // R20 R21
27571		},
27572	},
27573	{
27574		name:           "LoweredMoveShort",
27575		auxType:        auxInt64,
27576		argLen:         3,
27577		faultOnNilArg0: true,
27578		faultOnNilArg1: true,
27579		unsafePoint:    true,
27580		reg: regInfo{
27581			inputs: []inputInfo{
27582				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27583				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27584			},
27585		},
27586	},
27587	{
27588		name:           "LoweredQuadMove",
27589		auxType:        auxInt64,
27590		argLen:         3,
27591		clobberFlags:   true,
27592		faultOnNilArg0: true,
27593		faultOnNilArg1: true,
27594		unsafePoint:    true,
27595		reg: regInfo{
27596			inputs: []inputInfo{
27597				{0, 1048576}, // R20
27598				{1, 2097152}, // R21
27599			},
27600			clobbers: 3145728, // R20 R21
27601		},
27602	},
27603	{
27604		name:           "LoweredQuadMoveShort",
27605		auxType:        auxInt64,
27606		argLen:         3,
27607		faultOnNilArg0: true,
27608		faultOnNilArg1: true,
27609		unsafePoint:    true,
27610		reg: regInfo{
27611			inputs: []inputInfo{
27612				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27613				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27614			},
27615		},
27616	},
27617	{
27618		name:           "LoweredAtomicStore8",
27619		auxType:        auxInt64,
27620		argLen:         3,
27621		faultOnNilArg0: true,
27622		hasSideEffects: true,
27623		reg: regInfo{
27624			inputs: []inputInfo{
27625				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27626				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27627			},
27628		},
27629	},
27630	{
27631		name:           "LoweredAtomicStore32",
27632		auxType:        auxInt64,
27633		argLen:         3,
27634		faultOnNilArg0: true,
27635		hasSideEffects: true,
27636		reg: regInfo{
27637			inputs: []inputInfo{
27638				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27639				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27640			},
27641		},
27642	},
27643	{
27644		name:           "LoweredAtomicStore64",
27645		auxType:        auxInt64,
27646		argLen:         3,
27647		faultOnNilArg0: true,
27648		hasSideEffects: true,
27649		reg: regInfo{
27650			inputs: []inputInfo{
27651				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27652				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27653			},
27654		},
27655	},
27656	{
27657		name:           "LoweredAtomicLoad8",
27658		auxType:        auxInt64,
27659		argLen:         2,
27660		clobberFlags:   true,
27661		faultOnNilArg0: true,
27662		reg: regInfo{
27663			inputs: []inputInfo{
27664				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27665			},
27666			outputs: []outputInfo{
27667				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27668			},
27669		},
27670	},
27671	{
27672		name:           "LoweredAtomicLoad32",
27673		auxType:        auxInt64,
27674		argLen:         2,
27675		clobberFlags:   true,
27676		faultOnNilArg0: true,
27677		reg: regInfo{
27678			inputs: []inputInfo{
27679				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27680			},
27681			outputs: []outputInfo{
27682				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27683			},
27684		},
27685	},
27686	{
27687		name:           "LoweredAtomicLoad64",
27688		auxType:        auxInt64,
27689		argLen:         2,
27690		clobberFlags:   true,
27691		faultOnNilArg0: true,
27692		reg: regInfo{
27693			inputs: []inputInfo{
27694				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27695			},
27696			outputs: []outputInfo{
27697				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27698			},
27699		},
27700	},
27701	{
27702		name:           "LoweredAtomicLoadPtr",
27703		auxType:        auxInt64,
27704		argLen:         2,
27705		clobberFlags:   true,
27706		faultOnNilArg0: true,
27707		reg: regInfo{
27708			inputs: []inputInfo{
27709				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27710			},
27711			outputs: []outputInfo{
27712				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27713			},
27714		},
27715	},
27716	{
27717		name:            "LoweredAtomicAdd32",
27718		argLen:          3,
27719		resultNotInArgs: true,
27720		clobberFlags:    true,
27721		faultOnNilArg0:  true,
27722		hasSideEffects:  true,
27723		reg: regInfo{
27724			inputs: []inputInfo{
27725				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27726				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27727			},
27728			outputs: []outputInfo{
27729				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27730			},
27731		},
27732	},
27733	{
27734		name:            "LoweredAtomicAdd64",
27735		argLen:          3,
27736		resultNotInArgs: true,
27737		clobberFlags:    true,
27738		faultOnNilArg0:  true,
27739		hasSideEffects:  true,
27740		reg: regInfo{
27741			inputs: []inputInfo{
27742				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27743				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27744			},
27745			outputs: []outputInfo{
27746				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27747			},
27748		},
27749	},
27750	{
27751		name:            "LoweredAtomicExchange32",
27752		argLen:          3,
27753		resultNotInArgs: true,
27754		clobberFlags:    true,
27755		faultOnNilArg0:  true,
27756		hasSideEffects:  true,
27757		reg: regInfo{
27758			inputs: []inputInfo{
27759				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27760				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27761			},
27762			outputs: []outputInfo{
27763				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27764			},
27765		},
27766	},
27767	{
27768		name:            "LoweredAtomicExchange64",
27769		argLen:          3,
27770		resultNotInArgs: true,
27771		clobberFlags:    true,
27772		faultOnNilArg0:  true,
27773		hasSideEffects:  true,
27774		reg: regInfo{
27775			inputs: []inputInfo{
27776				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27777				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27778			},
27779			outputs: []outputInfo{
27780				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27781			},
27782		},
27783	},
27784	{
27785		name:            "LoweredAtomicCas64",
27786		auxType:         auxInt64,
27787		argLen:          4,
27788		resultNotInArgs: true,
27789		clobberFlags:    true,
27790		faultOnNilArg0:  true,
27791		hasSideEffects:  true,
27792		reg: regInfo{
27793			inputs: []inputInfo{
27794				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27795				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27796				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27797			},
27798			outputs: []outputInfo{
27799				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27800			},
27801		},
27802	},
27803	{
27804		name:            "LoweredAtomicCas32",
27805		auxType:         auxInt64,
27806		argLen:          4,
27807		resultNotInArgs: true,
27808		clobberFlags:    true,
27809		faultOnNilArg0:  true,
27810		hasSideEffects:  true,
27811		reg: regInfo{
27812			inputs: []inputInfo{
27813				{1, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27814				{2, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27815				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27816			},
27817			outputs: []outputInfo{
27818				{0, 1073733624}, // R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27819			},
27820		},
27821	},
27822	{
27823		name:           "LoweredAtomicAnd8",
27824		argLen:         3,
27825		faultOnNilArg0: true,
27826		hasSideEffects: true,
27827		asm:            ppc64.AAND,
27828		reg: regInfo{
27829			inputs: []inputInfo{
27830				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27831				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27832			},
27833		},
27834	},
27835	{
27836		name:           "LoweredAtomicAnd32",
27837		argLen:         3,
27838		faultOnNilArg0: true,
27839		hasSideEffects: true,
27840		asm:            ppc64.AAND,
27841		reg: regInfo{
27842			inputs: []inputInfo{
27843				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27844				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27845			},
27846		},
27847	},
27848	{
27849		name:           "LoweredAtomicOr8",
27850		argLen:         3,
27851		faultOnNilArg0: true,
27852		hasSideEffects: true,
27853		asm:            ppc64.AOR,
27854		reg: regInfo{
27855			inputs: []inputInfo{
27856				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27857				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27858			},
27859		},
27860	},
27861	{
27862		name:           "LoweredAtomicOr32",
27863		argLen:         3,
27864		faultOnNilArg0: true,
27865		hasSideEffects: true,
27866		asm:            ppc64.AOR,
27867		reg: regInfo{
27868			inputs: []inputInfo{
27869				{0, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27870				{1, 1073733630}, // SP SB R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29
27871			},
27872		},
27873	},
27874	{
27875		name:         "LoweredWB",
27876		auxType:      auxSym,
27877		argLen:       3,
27878		clobberFlags: true,
27879		symEffect:    SymNone,
27880		reg: regInfo{
27881			inputs: []inputInfo{
27882				{0, 1048576}, // R20
27883				{1, 2097152}, // R21
27884			},
27885			clobbers: 576460746931312640, // R11 R12 R18 R19 R22 R23 R24 R25 R26 R27 R28 R29 R31 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26
27886		},
27887	},
27888	{
27889		name:    "LoweredPanicBoundsA",
27890		auxType: auxInt64,
27891		argLen:  3,
27892		call:    true,
27893		reg: regInfo{
27894			inputs: []inputInfo{
27895				{0, 32}, // R5
27896				{1, 64}, // R6
27897			},
27898		},
27899	},
27900	{
27901		name:    "LoweredPanicBoundsB",
27902		auxType: auxInt64,
27903		argLen:  3,
27904		call:    true,
27905		reg: regInfo{
27906			inputs: []inputInfo{
27907				{0, 16}, // R4
27908				{1, 32}, // R5
27909			},
27910		},
27911	},
27912	{
27913		name:    "LoweredPanicBoundsC",
27914		auxType: auxInt64,
27915		argLen:  3,
27916		call:    true,
27917		reg: regInfo{
27918			inputs: []inputInfo{
27919				{0, 8},  // R3
27920				{1, 16}, // R4
27921			},
27922		},
27923	},
27924	{
27925		name:   "InvertFlags",
27926		argLen: 1,
27927		reg:    regInfo{},
27928	},
27929	{
27930		name:   "FlagEQ",
27931		argLen: 0,
27932		reg:    regInfo{},
27933	},
27934	{
27935		name:   "FlagLT",
27936		argLen: 0,
27937		reg:    regInfo{},
27938	},
27939	{
27940		name:   "FlagGT",
27941		argLen: 0,
27942		reg:    regInfo{},
27943	},
27944
27945	{
27946		name:        "ADD",
27947		argLen:      2,
27948		commutative: true,
27949		asm:         riscv.AADD,
27950		reg: regInfo{
27951			inputs: []inputInfo{
27952				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27953				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27954			},
27955			outputs: []outputInfo{
27956				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27957			},
27958		},
27959	},
27960	{
27961		name:    "ADDI",
27962		auxType: auxInt64,
27963		argLen:  1,
27964		asm:     riscv.AADDI,
27965		reg: regInfo{
27966			inputs: []inputInfo{
27967				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
27968			},
27969			outputs: []outputInfo{
27970				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27971			},
27972		},
27973	},
27974	{
27975		name:    "ADDIW",
27976		auxType: auxInt64,
27977		argLen:  1,
27978		asm:     riscv.AADDIW,
27979		reg: regInfo{
27980			inputs: []inputInfo{
27981				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27982			},
27983			outputs: []outputInfo{
27984				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27985			},
27986		},
27987	},
27988	{
27989		name:   "NEG",
27990		argLen: 1,
27991		asm:    riscv.ANEG,
27992		reg: regInfo{
27993			inputs: []inputInfo{
27994				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27995			},
27996			outputs: []outputInfo{
27997				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
27998			},
27999		},
28000	},
28001	{
28002		name:   "NEGW",
28003		argLen: 1,
28004		asm:    riscv.ANEGW,
28005		reg: regInfo{
28006			inputs: []inputInfo{
28007				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28008			},
28009			outputs: []outputInfo{
28010				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28011			},
28012		},
28013	},
28014	{
28015		name:   "SUB",
28016		argLen: 2,
28017		asm:    riscv.ASUB,
28018		reg: regInfo{
28019			inputs: []inputInfo{
28020				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28021				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28022			},
28023			outputs: []outputInfo{
28024				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28025			},
28026		},
28027	},
28028	{
28029		name:   "SUBW",
28030		argLen: 2,
28031		asm:    riscv.ASUBW,
28032		reg: regInfo{
28033			inputs: []inputInfo{
28034				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28035				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28036			},
28037			outputs: []outputInfo{
28038				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28039			},
28040		},
28041	},
28042	{
28043		name:        "MUL",
28044		argLen:      2,
28045		commutative: true,
28046		asm:         riscv.AMUL,
28047		reg: regInfo{
28048			inputs: []inputInfo{
28049				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28050				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28051			},
28052			outputs: []outputInfo{
28053				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28054			},
28055		},
28056	},
28057	{
28058		name:        "MULW",
28059		argLen:      2,
28060		commutative: true,
28061		asm:         riscv.AMULW,
28062		reg: regInfo{
28063			inputs: []inputInfo{
28064				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28065				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28066			},
28067			outputs: []outputInfo{
28068				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28069			},
28070		},
28071	},
28072	{
28073		name:        "MULH",
28074		argLen:      2,
28075		commutative: true,
28076		asm:         riscv.AMULH,
28077		reg: regInfo{
28078			inputs: []inputInfo{
28079				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28080				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28081			},
28082			outputs: []outputInfo{
28083				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28084			},
28085		},
28086	},
28087	{
28088		name:        "MULHU",
28089		argLen:      2,
28090		commutative: true,
28091		asm:         riscv.AMULHU,
28092		reg: regInfo{
28093			inputs: []inputInfo{
28094				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28095				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28096			},
28097			outputs: []outputInfo{
28098				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28099			},
28100		},
28101	},
28102	{
28103		name:            "LoweredMuluhilo",
28104		argLen:          2,
28105		resultNotInArgs: true,
28106		reg: regInfo{
28107			inputs: []inputInfo{
28108				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28109				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28110			},
28111			outputs: []outputInfo{
28112				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28113				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28114			},
28115		},
28116	},
28117	{
28118		name:            "LoweredMuluover",
28119		argLen:          2,
28120		resultNotInArgs: true,
28121		reg: regInfo{
28122			inputs: []inputInfo{
28123				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28124				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28125			},
28126			outputs: []outputInfo{
28127				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28128				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28129			},
28130		},
28131	},
28132	{
28133		name:   "DIV",
28134		argLen: 2,
28135		asm:    riscv.ADIV,
28136		reg: regInfo{
28137			inputs: []inputInfo{
28138				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28139				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28140			},
28141			outputs: []outputInfo{
28142				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28143			},
28144		},
28145	},
28146	{
28147		name:   "DIVU",
28148		argLen: 2,
28149		asm:    riscv.ADIVU,
28150		reg: regInfo{
28151			inputs: []inputInfo{
28152				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28153				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28154			},
28155			outputs: []outputInfo{
28156				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28157			},
28158		},
28159	},
28160	{
28161		name:   "DIVW",
28162		argLen: 2,
28163		asm:    riscv.ADIVW,
28164		reg: regInfo{
28165			inputs: []inputInfo{
28166				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28167				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28168			},
28169			outputs: []outputInfo{
28170				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28171			},
28172		},
28173	},
28174	{
28175		name:   "DIVUW",
28176		argLen: 2,
28177		asm:    riscv.ADIVUW,
28178		reg: regInfo{
28179			inputs: []inputInfo{
28180				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28181				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28182			},
28183			outputs: []outputInfo{
28184				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28185			},
28186		},
28187	},
28188	{
28189		name:   "REM",
28190		argLen: 2,
28191		asm:    riscv.AREM,
28192		reg: regInfo{
28193			inputs: []inputInfo{
28194				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28195				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28196			},
28197			outputs: []outputInfo{
28198				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28199			},
28200		},
28201	},
28202	{
28203		name:   "REMU",
28204		argLen: 2,
28205		asm:    riscv.AREMU,
28206		reg: regInfo{
28207			inputs: []inputInfo{
28208				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28209				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28210			},
28211			outputs: []outputInfo{
28212				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28213			},
28214		},
28215	},
28216	{
28217		name:   "REMW",
28218		argLen: 2,
28219		asm:    riscv.AREMW,
28220		reg: regInfo{
28221			inputs: []inputInfo{
28222				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28223				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28224			},
28225			outputs: []outputInfo{
28226				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28227			},
28228		},
28229	},
28230	{
28231		name:   "REMUW",
28232		argLen: 2,
28233		asm:    riscv.AREMUW,
28234		reg: regInfo{
28235			inputs: []inputInfo{
28236				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28237				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28238			},
28239			outputs: []outputInfo{
28240				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28241			},
28242		},
28243	},
28244	{
28245		name:              "MOVaddr",
28246		auxType:           auxSymOff,
28247		argLen:            1,
28248		rematerializeable: true,
28249		symEffect:         SymRdWr,
28250		asm:               riscv.AMOV,
28251		reg: regInfo{
28252			inputs: []inputInfo{
28253				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28254			},
28255			outputs: []outputInfo{
28256				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28257			},
28258		},
28259	},
28260	{
28261		name:              "MOVDconst",
28262		auxType:           auxInt64,
28263		argLen:            0,
28264		rematerializeable: true,
28265		asm:               riscv.AMOV,
28266		reg: regInfo{
28267			outputs: []outputInfo{
28268				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28269			},
28270		},
28271	},
28272	{
28273		name:           "MOVBload",
28274		auxType:        auxSymOff,
28275		argLen:         2,
28276		faultOnNilArg0: true,
28277		symEffect:      SymRead,
28278		asm:            riscv.AMOVB,
28279		reg: regInfo{
28280			inputs: []inputInfo{
28281				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28282			},
28283			outputs: []outputInfo{
28284				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28285			},
28286		},
28287	},
28288	{
28289		name:           "MOVHload",
28290		auxType:        auxSymOff,
28291		argLen:         2,
28292		faultOnNilArg0: true,
28293		symEffect:      SymRead,
28294		asm:            riscv.AMOVH,
28295		reg: regInfo{
28296			inputs: []inputInfo{
28297				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28298			},
28299			outputs: []outputInfo{
28300				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28301			},
28302		},
28303	},
28304	{
28305		name:           "MOVWload",
28306		auxType:        auxSymOff,
28307		argLen:         2,
28308		faultOnNilArg0: true,
28309		symEffect:      SymRead,
28310		asm:            riscv.AMOVW,
28311		reg: regInfo{
28312			inputs: []inputInfo{
28313				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28314			},
28315			outputs: []outputInfo{
28316				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28317			},
28318		},
28319	},
28320	{
28321		name:           "MOVDload",
28322		auxType:        auxSymOff,
28323		argLen:         2,
28324		faultOnNilArg0: true,
28325		symEffect:      SymRead,
28326		asm:            riscv.AMOV,
28327		reg: regInfo{
28328			inputs: []inputInfo{
28329				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28330			},
28331			outputs: []outputInfo{
28332				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28333			},
28334		},
28335	},
28336	{
28337		name:           "MOVBUload",
28338		auxType:        auxSymOff,
28339		argLen:         2,
28340		faultOnNilArg0: true,
28341		symEffect:      SymRead,
28342		asm:            riscv.AMOVBU,
28343		reg: regInfo{
28344			inputs: []inputInfo{
28345				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28346			},
28347			outputs: []outputInfo{
28348				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28349			},
28350		},
28351	},
28352	{
28353		name:           "MOVHUload",
28354		auxType:        auxSymOff,
28355		argLen:         2,
28356		faultOnNilArg0: true,
28357		symEffect:      SymRead,
28358		asm:            riscv.AMOVHU,
28359		reg: regInfo{
28360			inputs: []inputInfo{
28361				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28362			},
28363			outputs: []outputInfo{
28364				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28365			},
28366		},
28367	},
28368	{
28369		name:           "MOVWUload",
28370		auxType:        auxSymOff,
28371		argLen:         2,
28372		faultOnNilArg0: true,
28373		symEffect:      SymRead,
28374		asm:            riscv.AMOVWU,
28375		reg: regInfo{
28376			inputs: []inputInfo{
28377				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28378			},
28379			outputs: []outputInfo{
28380				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28381			},
28382		},
28383	},
28384	{
28385		name:           "MOVBstore",
28386		auxType:        auxSymOff,
28387		argLen:         3,
28388		faultOnNilArg0: true,
28389		symEffect:      SymWrite,
28390		asm:            riscv.AMOVB,
28391		reg: regInfo{
28392			inputs: []inputInfo{
28393				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28394				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28395			},
28396		},
28397	},
28398	{
28399		name:           "MOVHstore",
28400		auxType:        auxSymOff,
28401		argLen:         3,
28402		faultOnNilArg0: true,
28403		symEffect:      SymWrite,
28404		asm:            riscv.AMOVH,
28405		reg: regInfo{
28406			inputs: []inputInfo{
28407				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28408				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28409			},
28410		},
28411	},
28412	{
28413		name:           "MOVWstore",
28414		auxType:        auxSymOff,
28415		argLen:         3,
28416		faultOnNilArg0: true,
28417		symEffect:      SymWrite,
28418		asm:            riscv.AMOVW,
28419		reg: regInfo{
28420			inputs: []inputInfo{
28421				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28422				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28423			},
28424		},
28425	},
28426	{
28427		name:           "MOVDstore",
28428		auxType:        auxSymOff,
28429		argLen:         3,
28430		faultOnNilArg0: true,
28431		symEffect:      SymWrite,
28432		asm:            riscv.AMOV,
28433		reg: regInfo{
28434			inputs: []inputInfo{
28435				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28436				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28437			},
28438		},
28439	},
28440	{
28441		name:           "MOVBstorezero",
28442		auxType:        auxSymOff,
28443		argLen:         2,
28444		faultOnNilArg0: true,
28445		symEffect:      SymWrite,
28446		asm:            riscv.AMOVB,
28447		reg: regInfo{
28448			inputs: []inputInfo{
28449				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28450			},
28451		},
28452	},
28453	{
28454		name:           "MOVHstorezero",
28455		auxType:        auxSymOff,
28456		argLen:         2,
28457		faultOnNilArg0: true,
28458		symEffect:      SymWrite,
28459		asm:            riscv.AMOVH,
28460		reg: regInfo{
28461			inputs: []inputInfo{
28462				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28463			},
28464		},
28465	},
28466	{
28467		name:           "MOVWstorezero",
28468		auxType:        auxSymOff,
28469		argLen:         2,
28470		faultOnNilArg0: true,
28471		symEffect:      SymWrite,
28472		asm:            riscv.AMOVW,
28473		reg: regInfo{
28474			inputs: []inputInfo{
28475				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28476			},
28477		},
28478	},
28479	{
28480		name:           "MOVDstorezero",
28481		auxType:        auxSymOff,
28482		argLen:         2,
28483		faultOnNilArg0: true,
28484		symEffect:      SymWrite,
28485		asm:            riscv.AMOV,
28486		reg: regInfo{
28487			inputs: []inputInfo{
28488				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28489			},
28490		},
28491	},
28492	{
28493		name:   "MOVBreg",
28494		argLen: 1,
28495		asm:    riscv.AMOVB,
28496		reg: regInfo{
28497			inputs: []inputInfo{
28498				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28499			},
28500			outputs: []outputInfo{
28501				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28502			},
28503		},
28504	},
28505	{
28506		name:   "MOVHreg",
28507		argLen: 1,
28508		asm:    riscv.AMOVH,
28509		reg: regInfo{
28510			inputs: []inputInfo{
28511				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28512			},
28513			outputs: []outputInfo{
28514				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28515			},
28516		},
28517	},
28518	{
28519		name:   "MOVWreg",
28520		argLen: 1,
28521		asm:    riscv.AMOVW,
28522		reg: regInfo{
28523			inputs: []inputInfo{
28524				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28525			},
28526			outputs: []outputInfo{
28527				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28528			},
28529		},
28530	},
28531	{
28532		name:   "MOVDreg",
28533		argLen: 1,
28534		asm:    riscv.AMOV,
28535		reg: regInfo{
28536			inputs: []inputInfo{
28537				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28538			},
28539			outputs: []outputInfo{
28540				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28541			},
28542		},
28543	},
28544	{
28545		name:   "MOVBUreg",
28546		argLen: 1,
28547		asm:    riscv.AMOVBU,
28548		reg: regInfo{
28549			inputs: []inputInfo{
28550				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28551			},
28552			outputs: []outputInfo{
28553				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28554			},
28555		},
28556	},
28557	{
28558		name:   "MOVHUreg",
28559		argLen: 1,
28560		asm:    riscv.AMOVHU,
28561		reg: regInfo{
28562			inputs: []inputInfo{
28563				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28564			},
28565			outputs: []outputInfo{
28566				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28567			},
28568		},
28569	},
28570	{
28571		name:   "MOVWUreg",
28572		argLen: 1,
28573		asm:    riscv.AMOVWU,
28574		reg: regInfo{
28575			inputs: []inputInfo{
28576				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28577			},
28578			outputs: []outputInfo{
28579				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28580			},
28581		},
28582	},
28583	{
28584		name:         "MOVDnop",
28585		argLen:       1,
28586		resultInArg0: true,
28587		reg: regInfo{
28588			inputs: []inputInfo{
28589				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28590			},
28591			outputs: []outputInfo{
28592				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28593			},
28594		},
28595	},
28596	{
28597		name:   "SLL",
28598		argLen: 2,
28599		asm:    riscv.ASLL,
28600		reg: regInfo{
28601			inputs: []inputInfo{
28602				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28603				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28604			},
28605			outputs: []outputInfo{
28606				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28607			},
28608		},
28609	},
28610	{
28611		name:   "SRA",
28612		argLen: 2,
28613		asm:    riscv.ASRA,
28614		reg: regInfo{
28615			inputs: []inputInfo{
28616				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28617				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28618			},
28619			outputs: []outputInfo{
28620				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28621			},
28622		},
28623	},
28624	{
28625		name:   "SRL",
28626		argLen: 2,
28627		asm:    riscv.ASRL,
28628		reg: regInfo{
28629			inputs: []inputInfo{
28630				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28631				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28632			},
28633			outputs: []outputInfo{
28634				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28635			},
28636		},
28637	},
28638	{
28639		name:    "SLLI",
28640		auxType: auxInt64,
28641		argLen:  1,
28642		asm:     riscv.ASLLI,
28643		reg: regInfo{
28644			inputs: []inputInfo{
28645				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28646			},
28647			outputs: []outputInfo{
28648				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28649			},
28650		},
28651	},
28652	{
28653		name:    "SRAI",
28654		auxType: auxInt64,
28655		argLen:  1,
28656		asm:     riscv.ASRAI,
28657		reg: regInfo{
28658			inputs: []inputInfo{
28659				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28660			},
28661			outputs: []outputInfo{
28662				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28663			},
28664		},
28665	},
28666	{
28667		name:    "SRLI",
28668		auxType: auxInt64,
28669		argLen:  1,
28670		asm:     riscv.ASRLI,
28671		reg: regInfo{
28672			inputs: []inputInfo{
28673				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28674			},
28675			outputs: []outputInfo{
28676				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28677			},
28678		},
28679	},
28680	{
28681		name:        "XOR",
28682		argLen:      2,
28683		commutative: true,
28684		asm:         riscv.AXOR,
28685		reg: regInfo{
28686			inputs: []inputInfo{
28687				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28688				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28689			},
28690			outputs: []outputInfo{
28691				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28692			},
28693		},
28694	},
28695	{
28696		name:    "XORI",
28697		auxType: auxInt64,
28698		argLen:  1,
28699		asm:     riscv.AXORI,
28700		reg: regInfo{
28701			inputs: []inputInfo{
28702				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28703			},
28704			outputs: []outputInfo{
28705				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28706			},
28707		},
28708	},
28709	{
28710		name:        "OR",
28711		argLen:      2,
28712		commutative: true,
28713		asm:         riscv.AOR,
28714		reg: regInfo{
28715			inputs: []inputInfo{
28716				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28717				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28718			},
28719			outputs: []outputInfo{
28720				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28721			},
28722		},
28723	},
28724	{
28725		name:    "ORI",
28726		auxType: auxInt64,
28727		argLen:  1,
28728		asm:     riscv.AORI,
28729		reg: regInfo{
28730			inputs: []inputInfo{
28731				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28732			},
28733			outputs: []outputInfo{
28734				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28735			},
28736		},
28737	},
28738	{
28739		name:        "AND",
28740		argLen:      2,
28741		commutative: true,
28742		asm:         riscv.AAND,
28743		reg: regInfo{
28744			inputs: []inputInfo{
28745				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28746				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28747			},
28748			outputs: []outputInfo{
28749				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28750			},
28751		},
28752	},
28753	{
28754		name:    "ANDI",
28755		auxType: auxInt64,
28756		argLen:  1,
28757		asm:     riscv.AANDI,
28758		reg: regInfo{
28759			inputs: []inputInfo{
28760				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28761			},
28762			outputs: []outputInfo{
28763				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28764			},
28765		},
28766	},
28767	{
28768		name:   "NOT",
28769		argLen: 1,
28770		asm:    riscv.ANOT,
28771		reg: regInfo{
28772			inputs: []inputInfo{
28773				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28774			},
28775			outputs: []outputInfo{
28776				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28777			},
28778		},
28779	},
28780	{
28781		name:   "SEQZ",
28782		argLen: 1,
28783		asm:    riscv.ASEQZ,
28784		reg: regInfo{
28785			inputs: []inputInfo{
28786				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28787			},
28788			outputs: []outputInfo{
28789				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28790			},
28791		},
28792	},
28793	{
28794		name:   "SNEZ",
28795		argLen: 1,
28796		asm:    riscv.ASNEZ,
28797		reg: regInfo{
28798			inputs: []inputInfo{
28799				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28800			},
28801			outputs: []outputInfo{
28802				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28803			},
28804		},
28805	},
28806	{
28807		name:   "SLT",
28808		argLen: 2,
28809		asm:    riscv.ASLT,
28810		reg: regInfo{
28811			inputs: []inputInfo{
28812				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28813				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28814			},
28815			outputs: []outputInfo{
28816				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28817			},
28818		},
28819	},
28820	{
28821		name:    "SLTI",
28822		auxType: auxInt64,
28823		argLen:  1,
28824		asm:     riscv.ASLTI,
28825		reg: regInfo{
28826			inputs: []inputInfo{
28827				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28828			},
28829			outputs: []outputInfo{
28830				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28831			},
28832		},
28833	},
28834	{
28835		name:   "SLTU",
28836		argLen: 2,
28837		asm:    riscv.ASLTU,
28838		reg: regInfo{
28839			inputs: []inputInfo{
28840				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28841				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28842			},
28843			outputs: []outputInfo{
28844				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28845			},
28846		},
28847	},
28848	{
28849		name:    "SLTIU",
28850		auxType: auxInt64,
28851		argLen:  1,
28852		asm:     riscv.ASLTIU,
28853		reg: regInfo{
28854			inputs: []inputInfo{
28855				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28856			},
28857			outputs: []outputInfo{
28858				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28859			},
28860		},
28861	},
28862	{
28863		name:   "MOVconvert",
28864		argLen: 2,
28865		asm:    riscv.AMOV,
28866		reg: regInfo{
28867			inputs: []inputInfo{
28868				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28869			},
28870			outputs: []outputInfo{
28871				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28872			},
28873		},
28874	},
28875	{
28876		name:    "CALLstatic",
28877		auxType: auxCallOff,
28878		argLen:  1,
28879		call:    true,
28880		reg: regInfo{
28881			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
28882		},
28883	},
28884	{
28885		name:     "CALLtail",
28886		auxType:  auxCallOff,
28887		argLen:   1,
28888		call:     true,
28889		tailCall: true,
28890		reg: regInfo{
28891			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
28892		},
28893	},
28894	{
28895		name:    "CALLclosure",
28896		auxType: auxCallOff,
28897		argLen:  3,
28898		call:    true,
28899		reg: regInfo{
28900			inputs: []inputInfo{
28901				{1, 524288},     // X20
28902				{0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28903			},
28904			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
28905		},
28906	},
28907	{
28908		name:    "CALLinter",
28909		auxType: auxCallOff,
28910		argLen:  2,
28911		call:    true,
28912		reg: regInfo{
28913			inputs: []inputInfo{
28914				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28915			},
28916			clobbers: 9223372035781033968, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
28917		},
28918	},
28919	{
28920		name:           "DUFFZERO",
28921		auxType:        auxInt64,
28922		argLen:         2,
28923		faultOnNilArg0: true,
28924		reg: regInfo{
28925			inputs: []inputInfo{
28926				{0, 512}, // X10
28927			},
28928			clobbers: 512, // X10
28929		},
28930	},
28931	{
28932		name:           "DUFFCOPY",
28933		auxType:        auxInt64,
28934		argLen:         3,
28935		faultOnNilArg0: true,
28936		faultOnNilArg1: true,
28937		reg: regInfo{
28938			inputs: []inputInfo{
28939				{0, 1024}, // X11
28940				{1, 512},  // X10
28941			},
28942			clobbers: 1536, // X10 X11
28943		},
28944	},
28945	{
28946		name:           "LoweredZero",
28947		auxType:        auxInt64,
28948		argLen:         3,
28949		faultOnNilArg0: true,
28950		reg: regInfo{
28951			inputs: []inputInfo{
28952				{0, 16},         // X5
28953				{1, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28954			},
28955			clobbers: 16, // X5
28956		},
28957	},
28958	{
28959		name:           "LoweredMove",
28960		auxType:        auxInt64,
28961		argLen:         4,
28962		faultOnNilArg0: true,
28963		faultOnNilArg1: true,
28964		reg: regInfo{
28965			inputs: []inputInfo{
28966				{0, 16},         // X5
28967				{1, 32},         // X6
28968				{2, 1006632880}, // X5 X6 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28969			},
28970			clobbers: 112, // X5 X6 X7
28971		},
28972	},
28973	{
28974		name:           "LoweredAtomicLoad8",
28975		argLen:         2,
28976		faultOnNilArg0: true,
28977		reg: regInfo{
28978			inputs: []inputInfo{
28979				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28980			},
28981			outputs: []outputInfo{
28982				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28983			},
28984		},
28985	},
28986	{
28987		name:           "LoweredAtomicLoad32",
28988		argLen:         2,
28989		faultOnNilArg0: true,
28990		reg: regInfo{
28991			inputs: []inputInfo{
28992				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
28993			},
28994			outputs: []outputInfo{
28995				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
28996			},
28997		},
28998	},
28999	{
29000		name:           "LoweredAtomicLoad64",
29001		argLen:         2,
29002		faultOnNilArg0: true,
29003		reg: regInfo{
29004			inputs: []inputInfo{
29005				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29006			},
29007			outputs: []outputInfo{
29008				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29009			},
29010		},
29011	},
29012	{
29013		name:           "LoweredAtomicStore8",
29014		argLen:         3,
29015		faultOnNilArg0: true,
29016		hasSideEffects: true,
29017		reg: regInfo{
29018			inputs: []inputInfo{
29019				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29020				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29021			},
29022		},
29023	},
29024	{
29025		name:           "LoweredAtomicStore32",
29026		argLen:         3,
29027		faultOnNilArg0: true,
29028		hasSideEffects: true,
29029		reg: regInfo{
29030			inputs: []inputInfo{
29031				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29032				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29033			},
29034		},
29035	},
29036	{
29037		name:           "LoweredAtomicStore64",
29038		argLen:         3,
29039		faultOnNilArg0: true,
29040		hasSideEffects: true,
29041		reg: regInfo{
29042			inputs: []inputInfo{
29043				{1, 1006632946},          // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29044				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29045			},
29046		},
29047	},
29048	{
29049		name:            "LoweredAtomicExchange32",
29050		argLen:          3,
29051		resultNotInArgs: true,
29052		faultOnNilArg0:  true,
29053		hasSideEffects:  true,
29054		reg: regInfo{
29055			inputs: []inputInfo{
29056				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29057				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29058			},
29059			outputs: []outputInfo{
29060				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29061			},
29062		},
29063	},
29064	{
29065		name:            "LoweredAtomicExchange64",
29066		argLen:          3,
29067		resultNotInArgs: true,
29068		faultOnNilArg0:  true,
29069		hasSideEffects:  true,
29070		reg: regInfo{
29071			inputs: []inputInfo{
29072				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29073				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29074			},
29075			outputs: []outputInfo{
29076				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29077			},
29078		},
29079	},
29080	{
29081		name:            "LoweredAtomicAdd32",
29082		argLen:          3,
29083		resultNotInArgs: true,
29084		faultOnNilArg0:  true,
29085		hasSideEffects:  true,
29086		unsafePoint:     true,
29087		reg: regInfo{
29088			inputs: []inputInfo{
29089				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29090				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29091			},
29092			outputs: []outputInfo{
29093				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29094			},
29095		},
29096	},
29097	{
29098		name:            "LoweredAtomicAdd64",
29099		argLen:          3,
29100		resultNotInArgs: true,
29101		faultOnNilArg0:  true,
29102		hasSideEffects:  true,
29103		unsafePoint:     true,
29104		reg: regInfo{
29105			inputs: []inputInfo{
29106				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29107				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29108			},
29109			outputs: []outputInfo{
29110				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29111			},
29112		},
29113	},
29114	{
29115		name:            "LoweredAtomicCas32",
29116		argLen:          4,
29117		resultNotInArgs: true,
29118		faultOnNilArg0:  true,
29119		hasSideEffects:  true,
29120		unsafePoint:     true,
29121		reg: regInfo{
29122			inputs: []inputInfo{
29123				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29124				{2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29125				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29126			},
29127			outputs: []outputInfo{
29128				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29129			},
29130		},
29131	},
29132	{
29133		name:            "LoweredAtomicCas64",
29134		argLen:          4,
29135		resultNotInArgs: true,
29136		faultOnNilArg0:  true,
29137		hasSideEffects:  true,
29138		unsafePoint:     true,
29139		reg: regInfo{
29140			inputs: []inputInfo{
29141				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29142				{2, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29143				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29144			},
29145			outputs: []outputInfo{
29146				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29147			},
29148		},
29149	},
29150	{
29151		name:           "LoweredAtomicAnd32",
29152		argLen:         3,
29153		faultOnNilArg0: true,
29154		hasSideEffects: true,
29155		asm:            riscv.AAMOANDW,
29156		reg: regInfo{
29157			inputs: []inputInfo{
29158				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29159				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29160			},
29161		},
29162	},
29163	{
29164		name:           "LoweredAtomicOr32",
29165		argLen:         3,
29166		faultOnNilArg0: true,
29167		hasSideEffects: true,
29168		asm:            riscv.AAMOORW,
29169		reg: regInfo{
29170			inputs: []inputInfo{
29171				{1, 1073741808},          // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30
29172				{0, 9223372037928517618}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 g X28 X29 X30 SB
29173			},
29174		},
29175	},
29176	{
29177		name:           "LoweredNilCheck",
29178		argLen:         2,
29179		nilCheck:       true,
29180		faultOnNilArg0: true,
29181		reg: regInfo{
29182			inputs: []inputInfo{
29183				{0, 1006632946}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29184			},
29185		},
29186	},
29187	{
29188		name:   "LoweredGetClosurePtr",
29189		argLen: 0,
29190		reg: regInfo{
29191			outputs: []outputInfo{
29192				{0, 524288}, // X20
29193			},
29194		},
29195	},
29196	{
29197		name:              "LoweredGetCallerSP",
29198		argLen:            0,
29199		rematerializeable: true,
29200		reg: regInfo{
29201			outputs: []outputInfo{
29202				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29203			},
29204		},
29205	},
29206	{
29207		name:              "LoweredGetCallerPC",
29208		argLen:            0,
29209		rematerializeable: true,
29210		reg: regInfo{
29211			outputs: []outputInfo{
29212				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29213			},
29214		},
29215	},
29216	{
29217		name:         "LoweredWB",
29218		auxType:      auxSym,
29219		argLen:       3,
29220		clobberFlags: true,
29221		symEffect:    SymNone,
29222		reg: regInfo{
29223			inputs: []inputInfo{
29224				{0, 16}, // X5
29225				{1, 32}, // X6
29226			},
29227			clobbers: 9223372034707292160, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29228		},
29229	},
29230	{
29231		name:    "LoweredPanicBoundsA",
29232		auxType: auxInt64,
29233		argLen:  3,
29234		call:    true,
29235		reg: regInfo{
29236			inputs: []inputInfo{
29237				{0, 64},        // X7
29238				{1, 134217728}, // X28
29239			},
29240		},
29241	},
29242	{
29243		name:    "LoweredPanicBoundsB",
29244		auxType: auxInt64,
29245		argLen:  3,
29246		call:    true,
29247		reg: regInfo{
29248			inputs: []inputInfo{
29249				{0, 32}, // X6
29250				{1, 64}, // X7
29251			},
29252		},
29253	},
29254	{
29255		name:    "LoweredPanicBoundsC",
29256		auxType: auxInt64,
29257		argLen:  3,
29258		call:    true,
29259		reg: regInfo{
29260			inputs: []inputInfo{
29261				{0, 16}, // X5
29262				{1, 32}, // X6
29263			},
29264		},
29265	},
29266	{
29267		name:        "FADDS",
29268		argLen:      2,
29269		commutative: true,
29270		asm:         riscv.AFADDS,
29271		reg: regInfo{
29272			inputs: []inputInfo{
29273				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29274				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29275			},
29276			outputs: []outputInfo{
29277				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29278			},
29279		},
29280	},
29281	{
29282		name:   "FSUBS",
29283		argLen: 2,
29284		asm:    riscv.AFSUBS,
29285		reg: regInfo{
29286			inputs: []inputInfo{
29287				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29288				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29289			},
29290			outputs: []outputInfo{
29291				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29292			},
29293		},
29294	},
29295	{
29296		name:        "FMULS",
29297		argLen:      2,
29298		commutative: true,
29299		asm:         riscv.AFMULS,
29300		reg: regInfo{
29301			inputs: []inputInfo{
29302				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29303				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29304			},
29305			outputs: []outputInfo{
29306				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29307			},
29308		},
29309	},
29310	{
29311		name:   "FDIVS",
29312		argLen: 2,
29313		asm:    riscv.AFDIVS,
29314		reg: regInfo{
29315			inputs: []inputInfo{
29316				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29317				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29318			},
29319			outputs: []outputInfo{
29320				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29321			},
29322		},
29323	},
29324	{
29325		name:   "FSQRTS",
29326		argLen: 1,
29327		asm:    riscv.AFSQRTS,
29328		reg: regInfo{
29329			inputs: []inputInfo{
29330				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29331			},
29332			outputs: []outputInfo{
29333				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29334			},
29335		},
29336	},
29337	{
29338		name:   "FNEGS",
29339		argLen: 1,
29340		asm:    riscv.AFNEGS,
29341		reg: regInfo{
29342			inputs: []inputInfo{
29343				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29344			},
29345			outputs: []outputInfo{
29346				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29347			},
29348		},
29349	},
29350	{
29351		name:   "FMVSX",
29352		argLen: 1,
29353		asm:    riscv.AFMVSX,
29354		reg: regInfo{
29355			inputs: []inputInfo{
29356				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29357			},
29358			outputs: []outputInfo{
29359				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29360			},
29361		},
29362	},
29363	{
29364		name:   "FCVTSW",
29365		argLen: 1,
29366		asm:    riscv.AFCVTSW,
29367		reg: regInfo{
29368			inputs: []inputInfo{
29369				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29370			},
29371			outputs: []outputInfo{
29372				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29373			},
29374		},
29375	},
29376	{
29377		name:   "FCVTSL",
29378		argLen: 1,
29379		asm:    riscv.AFCVTSL,
29380		reg: regInfo{
29381			inputs: []inputInfo{
29382				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29383			},
29384			outputs: []outputInfo{
29385				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29386			},
29387		},
29388	},
29389	{
29390		name:   "FCVTWS",
29391		argLen: 1,
29392		asm:    riscv.AFCVTWS,
29393		reg: regInfo{
29394			inputs: []inputInfo{
29395				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29396			},
29397			outputs: []outputInfo{
29398				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29399			},
29400		},
29401	},
29402	{
29403		name:   "FCVTLS",
29404		argLen: 1,
29405		asm:    riscv.AFCVTLS,
29406		reg: regInfo{
29407			inputs: []inputInfo{
29408				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29409			},
29410			outputs: []outputInfo{
29411				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29412			},
29413		},
29414	},
29415	{
29416		name:           "FMOVWload",
29417		auxType:        auxSymOff,
29418		argLen:         2,
29419		faultOnNilArg0: true,
29420		symEffect:      SymRead,
29421		asm:            riscv.AMOVF,
29422		reg: regInfo{
29423			inputs: []inputInfo{
29424				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29425			},
29426			outputs: []outputInfo{
29427				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29428			},
29429		},
29430	},
29431	{
29432		name:           "FMOVWstore",
29433		auxType:        auxSymOff,
29434		argLen:         3,
29435		faultOnNilArg0: true,
29436		symEffect:      SymWrite,
29437		asm:            riscv.AMOVF,
29438		reg: regInfo{
29439			inputs: []inputInfo{
29440				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29441				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29442			},
29443		},
29444	},
29445	{
29446		name:        "FEQS",
29447		argLen:      2,
29448		commutative: true,
29449		asm:         riscv.AFEQS,
29450		reg: regInfo{
29451			inputs: []inputInfo{
29452				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29453				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29454			},
29455			outputs: []outputInfo{
29456				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29457			},
29458		},
29459	},
29460	{
29461		name:        "FNES",
29462		argLen:      2,
29463		commutative: true,
29464		asm:         riscv.AFNES,
29465		reg: regInfo{
29466			inputs: []inputInfo{
29467				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29468				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29469			},
29470			outputs: []outputInfo{
29471				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29472			},
29473		},
29474	},
29475	{
29476		name:   "FLTS",
29477		argLen: 2,
29478		asm:    riscv.AFLTS,
29479		reg: regInfo{
29480			inputs: []inputInfo{
29481				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29482				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29483			},
29484			outputs: []outputInfo{
29485				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29486			},
29487		},
29488	},
29489	{
29490		name:   "FLES",
29491		argLen: 2,
29492		asm:    riscv.AFLES,
29493		reg: regInfo{
29494			inputs: []inputInfo{
29495				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29496				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29497			},
29498			outputs: []outputInfo{
29499				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29500			},
29501		},
29502	},
29503	{
29504		name:        "FADDD",
29505		argLen:      2,
29506		commutative: true,
29507		asm:         riscv.AFADDD,
29508		reg: regInfo{
29509			inputs: []inputInfo{
29510				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29511				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29512			},
29513			outputs: []outputInfo{
29514				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29515			},
29516		},
29517	},
29518	{
29519		name:   "FSUBD",
29520		argLen: 2,
29521		asm:    riscv.AFSUBD,
29522		reg: regInfo{
29523			inputs: []inputInfo{
29524				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29525				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29526			},
29527			outputs: []outputInfo{
29528				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29529			},
29530		},
29531	},
29532	{
29533		name:        "FMULD",
29534		argLen:      2,
29535		commutative: true,
29536		asm:         riscv.AFMULD,
29537		reg: regInfo{
29538			inputs: []inputInfo{
29539				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29540				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29541			},
29542			outputs: []outputInfo{
29543				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29544			},
29545		},
29546	},
29547	{
29548		name:   "FDIVD",
29549		argLen: 2,
29550		asm:    riscv.AFDIVD,
29551		reg: regInfo{
29552			inputs: []inputInfo{
29553				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29554				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29555			},
29556			outputs: []outputInfo{
29557				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29558			},
29559		},
29560	},
29561	{
29562		name:        "FMADDD",
29563		argLen:      3,
29564		commutative: true,
29565		asm:         riscv.AFMADDD,
29566		reg: regInfo{
29567			inputs: []inputInfo{
29568				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29569				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29570				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29571			},
29572			outputs: []outputInfo{
29573				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29574			},
29575		},
29576	},
29577	{
29578		name:        "FMSUBD",
29579		argLen:      3,
29580		commutative: true,
29581		asm:         riscv.AFMSUBD,
29582		reg: regInfo{
29583			inputs: []inputInfo{
29584				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29585				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29586				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29587			},
29588			outputs: []outputInfo{
29589				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29590			},
29591		},
29592	},
29593	{
29594		name:        "FNMADDD",
29595		argLen:      3,
29596		commutative: true,
29597		asm:         riscv.AFNMADDD,
29598		reg: regInfo{
29599			inputs: []inputInfo{
29600				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29601				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29602				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29603			},
29604			outputs: []outputInfo{
29605				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29606			},
29607		},
29608	},
29609	{
29610		name:        "FNMSUBD",
29611		argLen:      3,
29612		commutative: true,
29613		asm:         riscv.AFNMSUBD,
29614		reg: regInfo{
29615			inputs: []inputInfo{
29616				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29617				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29618				{2, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29619			},
29620			outputs: []outputInfo{
29621				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29622			},
29623		},
29624	},
29625	{
29626		name:   "FSQRTD",
29627		argLen: 1,
29628		asm:    riscv.AFSQRTD,
29629		reg: regInfo{
29630			inputs: []inputInfo{
29631				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29632			},
29633			outputs: []outputInfo{
29634				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29635			},
29636		},
29637	},
29638	{
29639		name:   "FNEGD",
29640		argLen: 1,
29641		asm:    riscv.AFNEGD,
29642		reg: regInfo{
29643			inputs: []inputInfo{
29644				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29645			},
29646			outputs: []outputInfo{
29647				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29648			},
29649		},
29650	},
29651	{
29652		name:   "FABSD",
29653		argLen: 1,
29654		asm:    riscv.AFABSD,
29655		reg: regInfo{
29656			inputs: []inputInfo{
29657				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29658			},
29659			outputs: []outputInfo{
29660				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29661			},
29662		},
29663	},
29664	{
29665		name:   "FSGNJD",
29666		argLen: 2,
29667		asm:    riscv.AFSGNJD,
29668		reg: regInfo{
29669			inputs: []inputInfo{
29670				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29671				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29672			},
29673			outputs: []outputInfo{
29674				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29675			},
29676		},
29677	},
29678	{
29679		name:   "FMVDX",
29680		argLen: 1,
29681		asm:    riscv.AFMVDX,
29682		reg: regInfo{
29683			inputs: []inputInfo{
29684				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29685			},
29686			outputs: []outputInfo{
29687				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29688			},
29689		},
29690	},
29691	{
29692		name:   "FCVTDW",
29693		argLen: 1,
29694		asm:    riscv.AFCVTDW,
29695		reg: regInfo{
29696			inputs: []inputInfo{
29697				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29698			},
29699			outputs: []outputInfo{
29700				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29701			},
29702		},
29703	},
29704	{
29705		name:   "FCVTDL",
29706		argLen: 1,
29707		asm:    riscv.AFCVTDL,
29708		reg: regInfo{
29709			inputs: []inputInfo{
29710				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29711			},
29712			outputs: []outputInfo{
29713				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29714			},
29715		},
29716	},
29717	{
29718		name:   "FCVTWD",
29719		argLen: 1,
29720		asm:    riscv.AFCVTWD,
29721		reg: regInfo{
29722			inputs: []inputInfo{
29723				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29724			},
29725			outputs: []outputInfo{
29726				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29727			},
29728		},
29729	},
29730	{
29731		name:   "FCVTLD",
29732		argLen: 1,
29733		asm:    riscv.AFCVTLD,
29734		reg: regInfo{
29735			inputs: []inputInfo{
29736				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29737			},
29738			outputs: []outputInfo{
29739				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29740			},
29741		},
29742	},
29743	{
29744		name:   "FCVTDS",
29745		argLen: 1,
29746		asm:    riscv.AFCVTDS,
29747		reg: regInfo{
29748			inputs: []inputInfo{
29749				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29750			},
29751			outputs: []outputInfo{
29752				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29753			},
29754		},
29755	},
29756	{
29757		name:   "FCVTSD",
29758		argLen: 1,
29759		asm:    riscv.AFCVTSD,
29760		reg: regInfo{
29761			inputs: []inputInfo{
29762				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29763			},
29764			outputs: []outputInfo{
29765				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29766			},
29767		},
29768	},
29769	{
29770		name:           "FMOVDload",
29771		auxType:        auxSymOff,
29772		argLen:         2,
29773		faultOnNilArg0: true,
29774		symEffect:      SymRead,
29775		asm:            riscv.AMOVD,
29776		reg: regInfo{
29777			inputs: []inputInfo{
29778				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29779			},
29780			outputs: []outputInfo{
29781				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29782			},
29783		},
29784	},
29785	{
29786		name:           "FMOVDstore",
29787		auxType:        auxSymOff,
29788		argLen:         3,
29789		faultOnNilArg0: true,
29790		symEffect:      SymWrite,
29791		asm:            riscv.AMOVD,
29792		reg: regInfo{
29793			inputs: []inputInfo{
29794				{0, 9223372037861408754}, // SP X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30 SB
29795				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29796			},
29797		},
29798	},
29799	{
29800		name:        "FEQD",
29801		argLen:      2,
29802		commutative: true,
29803		asm:         riscv.AFEQD,
29804		reg: regInfo{
29805			inputs: []inputInfo{
29806				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29807				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29808			},
29809			outputs: []outputInfo{
29810				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29811			},
29812		},
29813	},
29814	{
29815		name:        "FNED",
29816		argLen:      2,
29817		commutative: true,
29818		asm:         riscv.AFNED,
29819		reg: regInfo{
29820			inputs: []inputInfo{
29821				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29822				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29823			},
29824			outputs: []outputInfo{
29825				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29826			},
29827		},
29828	},
29829	{
29830		name:   "FLTD",
29831		argLen: 2,
29832		asm:    riscv.AFLTD,
29833		reg: regInfo{
29834			inputs: []inputInfo{
29835				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29836				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29837			},
29838			outputs: []outputInfo{
29839				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29840			},
29841		},
29842	},
29843	{
29844		name:   "FLED",
29845		argLen: 2,
29846		asm:    riscv.AFLED,
29847		reg: regInfo{
29848			inputs: []inputInfo{
29849				{0, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29850				{1, 9223372034707292160}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
29851			},
29852			outputs: []outputInfo{
29853				{0, 1006632944}, // X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 X16 X17 X18 X19 X20 X21 X22 X23 X24 X25 X26 X28 X29 X30
29854			},
29855		},
29856	},
29857
29858	{
29859		name:         "FADDS",
29860		argLen:       2,
29861		commutative:  true,
29862		resultInArg0: true,
29863		asm:          s390x.AFADDS,
29864		reg: regInfo{
29865			inputs: []inputInfo{
29866				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29867				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29868			},
29869			outputs: []outputInfo{
29870				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29871			},
29872		},
29873	},
29874	{
29875		name:         "FADD",
29876		argLen:       2,
29877		commutative:  true,
29878		resultInArg0: true,
29879		asm:          s390x.AFADD,
29880		reg: regInfo{
29881			inputs: []inputInfo{
29882				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29883				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29884			},
29885			outputs: []outputInfo{
29886				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29887			},
29888		},
29889	},
29890	{
29891		name:         "FSUBS",
29892		argLen:       2,
29893		resultInArg0: true,
29894		asm:          s390x.AFSUBS,
29895		reg: regInfo{
29896			inputs: []inputInfo{
29897				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29898				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29899			},
29900			outputs: []outputInfo{
29901				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29902			},
29903		},
29904	},
29905	{
29906		name:         "FSUB",
29907		argLen:       2,
29908		resultInArg0: true,
29909		asm:          s390x.AFSUB,
29910		reg: regInfo{
29911			inputs: []inputInfo{
29912				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29913				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29914			},
29915			outputs: []outputInfo{
29916				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29917			},
29918		},
29919	},
29920	{
29921		name:         "FMULS",
29922		argLen:       2,
29923		commutative:  true,
29924		resultInArg0: true,
29925		asm:          s390x.AFMULS,
29926		reg: regInfo{
29927			inputs: []inputInfo{
29928				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29929				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29930			},
29931			outputs: []outputInfo{
29932				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29933			},
29934		},
29935	},
29936	{
29937		name:         "FMUL",
29938		argLen:       2,
29939		commutative:  true,
29940		resultInArg0: true,
29941		asm:          s390x.AFMUL,
29942		reg: regInfo{
29943			inputs: []inputInfo{
29944				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29945				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29946			},
29947			outputs: []outputInfo{
29948				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29949			},
29950		},
29951	},
29952	{
29953		name:         "FDIVS",
29954		argLen:       2,
29955		resultInArg0: true,
29956		asm:          s390x.AFDIVS,
29957		reg: regInfo{
29958			inputs: []inputInfo{
29959				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29960				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29961			},
29962			outputs: []outputInfo{
29963				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29964			},
29965		},
29966	},
29967	{
29968		name:         "FDIV",
29969		argLen:       2,
29970		resultInArg0: true,
29971		asm:          s390x.AFDIV,
29972		reg: regInfo{
29973			inputs: []inputInfo{
29974				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29975				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29976			},
29977			outputs: []outputInfo{
29978				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29979			},
29980		},
29981	},
29982	{
29983		name:         "FNEGS",
29984		argLen:       1,
29985		clobberFlags: true,
29986		asm:          s390x.AFNEGS,
29987		reg: regInfo{
29988			inputs: []inputInfo{
29989				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29990			},
29991			outputs: []outputInfo{
29992				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
29993			},
29994		},
29995	},
29996	{
29997		name:         "FNEG",
29998		argLen:       1,
29999		clobberFlags: true,
30000		asm:          s390x.AFNEG,
30001		reg: regInfo{
30002			inputs: []inputInfo{
30003				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30004			},
30005			outputs: []outputInfo{
30006				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30007			},
30008		},
30009	},
30010	{
30011		name:         "FMADDS",
30012		argLen:       3,
30013		resultInArg0: true,
30014		asm:          s390x.AFMADDS,
30015		reg: regInfo{
30016			inputs: []inputInfo{
30017				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30018				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30019				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30020			},
30021			outputs: []outputInfo{
30022				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30023			},
30024		},
30025	},
30026	{
30027		name:         "FMADD",
30028		argLen:       3,
30029		resultInArg0: true,
30030		asm:          s390x.AFMADD,
30031		reg: regInfo{
30032			inputs: []inputInfo{
30033				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30034				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30035				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30036			},
30037			outputs: []outputInfo{
30038				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30039			},
30040		},
30041	},
30042	{
30043		name:         "FMSUBS",
30044		argLen:       3,
30045		resultInArg0: true,
30046		asm:          s390x.AFMSUBS,
30047		reg: regInfo{
30048			inputs: []inputInfo{
30049				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30050				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30051				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30052			},
30053			outputs: []outputInfo{
30054				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30055			},
30056		},
30057	},
30058	{
30059		name:         "FMSUB",
30060		argLen:       3,
30061		resultInArg0: true,
30062		asm:          s390x.AFMSUB,
30063		reg: regInfo{
30064			inputs: []inputInfo{
30065				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30066				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30067				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30068			},
30069			outputs: []outputInfo{
30070				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30071			},
30072		},
30073	},
30074	{
30075		name:   "LPDFR",
30076		argLen: 1,
30077		asm:    s390x.ALPDFR,
30078		reg: regInfo{
30079			inputs: []inputInfo{
30080				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30081			},
30082			outputs: []outputInfo{
30083				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30084			},
30085		},
30086	},
30087	{
30088		name:   "LNDFR",
30089		argLen: 1,
30090		asm:    s390x.ALNDFR,
30091		reg: regInfo{
30092			inputs: []inputInfo{
30093				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30094			},
30095			outputs: []outputInfo{
30096				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30097			},
30098		},
30099	},
30100	{
30101		name:   "CPSDR",
30102		argLen: 2,
30103		asm:    s390x.ACPSDR,
30104		reg: regInfo{
30105			inputs: []inputInfo{
30106				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30107				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30108			},
30109			outputs: []outputInfo{
30110				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30111			},
30112		},
30113	},
30114	{
30115		name:    "FIDBR",
30116		auxType: auxInt8,
30117		argLen:  1,
30118		asm:     s390x.AFIDBR,
30119		reg: regInfo{
30120			inputs: []inputInfo{
30121				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30122			},
30123			outputs: []outputInfo{
30124				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30125			},
30126		},
30127	},
30128	{
30129		name:           "FMOVSload",
30130		auxType:        auxSymOff,
30131		argLen:         2,
30132		faultOnNilArg0: true,
30133		symEffect:      SymRead,
30134		asm:            s390x.AFMOVS,
30135		reg: regInfo{
30136			inputs: []inputInfo{
30137				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
30138			},
30139			outputs: []outputInfo{
30140				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30141			},
30142		},
30143	},
30144	{
30145		name:           "FMOVDload",
30146		auxType:        auxSymOff,
30147		argLen:         2,
30148		faultOnNilArg0: true,
30149		symEffect:      SymRead,
30150		asm:            s390x.AFMOVD,
30151		reg: regInfo{
30152			inputs: []inputInfo{
30153				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
30154			},
30155			outputs: []outputInfo{
30156				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30157			},
30158		},
30159	},
30160	{
30161		name:              "FMOVSconst",
30162		auxType:           auxFloat32,
30163		argLen:            0,
30164		rematerializeable: true,
30165		asm:               s390x.AFMOVS,
30166		reg: regInfo{
30167			outputs: []outputInfo{
30168				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30169			},
30170		},
30171	},
30172	{
30173		name:              "FMOVDconst",
30174		auxType:           auxFloat64,
30175		argLen:            0,
30176		rematerializeable: true,
30177		asm:               s390x.AFMOVD,
30178		reg: regInfo{
30179			outputs: []outputInfo{
30180				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30181			},
30182		},
30183	},
30184	{
30185		name:      "FMOVSloadidx",
30186		auxType:   auxSymOff,
30187		argLen:    3,
30188		symEffect: SymRead,
30189		asm:       s390x.AFMOVS,
30190		reg: regInfo{
30191			inputs: []inputInfo{
30192				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30193				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30194			},
30195			outputs: []outputInfo{
30196				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30197			},
30198		},
30199	},
30200	{
30201		name:      "FMOVDloadidx",
30202		auxType:   auxSymOff,
30203		argLen:    3,
30204		symEffect: SymRead,
30205		asm:       s390x.AFMOVD,
30206		reg: regInfo{
30207			inputs: []inputInfo{
30208				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30209				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30210			},
30211			outputs: []outputInfo{
30212				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30213			},
30214		},
30215	},
30216	{
30217		name:           "FMOVSstore",
30218		auxType:        auxSymOff,
30219		argLen:         3,
30220		faultOnNilArg0: true,
30221		symEffect:      SymWrite,
30222		asm:            s390x.AFMOVS,
30223		reg: regInfo{
30224			inputs: []inputInfo{
30225				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
30226				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30227			},
30228		},
30229	},
30230	{
30231		name:           "FMOVDstore",
30232		auxType:        auxSymOff,
30233		argLen:         3,
30234		faultOnNilArg0: true,
30235		symEffect:      SymWrite,
30236		asm:            s390x.AFMOVD,
30237		reg: regInfo{
30238			inputs: []inputInfo{
30239				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
30240				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30241			},
30242		},
30243	},
30244	{
30245		name:      "FMOVSstoreidx",
30246		auxType:   auxSymOff,
30247		argLen:    4,
30248		symEffect: SymWrite,
30249		asm:       s390x.AFMOVS,
30250		reg: regInfo{
30251			inputs: []inputInfo{
30252				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30253				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30254				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30255			},
30256		},
30257	},
30258	{
30259		name:      "FMOVDstoreidx",
30260		auxType:   auxSymOff,
30261		argLen:    4,
30262		symEffect: SymWrite,
30263		asm:       s390x.AFMOVD,
30264		reg: regInfo{
30265			inputs: []inputInfo{
30266				{0, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30267				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30268				{2, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
30269			},
30270		},
30271	},
30272	{
30273		name:         "ADD",
30274		argLen:       2,
30275		commutative:  true,
30276		clobberFlags: true,
30277		asm:          s390x.AADD,
30278		reg: regInfo{
30279			inputs: []inputInfo{
30280				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30281				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30282			},
30283			outputs: []outputInfo{
30284				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30285			},
30286		},
30287	},
30288	{
30289		name:         "ADDW",
30290		argLen:       2,
30291		commutative:  true,
30292		clobberFlags: true,
30293		asm:          s390x.AADDW,
30294		reg: regInfo{
30295			inputs: []inputInfo{
30296				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30297				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30298			},
30299			outputs: []outputInfo{
30300				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30301			},
30302		},
30303	},
30304	{
30305		name:         "ADDconst",
30306		auxType:      auxInt32,
30307		argLen:       1,
30308		clobberFlags: true,
30309		asm:          s390x.AADD,
30310		reg: regInfo{
30311			inputs: []inputInfo{
30312				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30313			},
30314			outputs: []outputInfo{
30315				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30316			},
30317		},
30318	},
30319	{
30320		name:         "ADDWconst",
30321		auxType:      auxInt32,
30322		argLen:       1,
30323		clobberFlags: true,
30324		asm:          s390x.AADDW,
30325		reg: regInfo{
30326			inputs: []inputInfo{
30327				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30328			},
30329			outputs: []outputInfo{
30330				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30331			},
30332		},
30333	},
30334	{
30335		name:           "ADDload",
30336		auxType:        auxSymOff,
30337		argLen:         3,
30338		resultInArg0:   true,
30339		clobberFlags:   true,
30340		faultOnNilArg1: true,
30341		symEffect:      SymRead,
30342		asm:            s390x.AADD,
30343		reg: regInfo{
30344			inputs: []inputInfo{
30345				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30346				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30347			},
30348			outputs: []outputInfo{
30349				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30350			},
30351		},
30352	},
30353	{
30354		name:           "ADDWload",
30355		auxType:        auxSymOff,
30356		argLen:         3,
30357		resultInArg0:   true,
30358		clobberFlags:   true,
30359		faultOnNilArg1: true,
30360		symEffect:      SymRead,
30361		asm:            s390x.AADDW,
30362		reg: regInfo{
30363			inputs: []inputInfo{
30364				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30365				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30366			},
30367			outputs: []outputInfo{
30368				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30369			},
30370		},
30371	},
30372	{
30373		name:         "SUB",
30374		argLen:       2,
30375		clobberFlags: true,
30376		asm:          s390x.ASUB,
30377		reg: regInfo{
30378			inputs: []inputInfo{
30379				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30380				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30381			},
30382			outputs: []outputInfo{
30383				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30384			},
30385		},
30386	},
30387	{
30388		name:         "SUBW",
30389		argLen:       2,
30390		clobberFlags: true,
30391		asm:          s390x.ASUBW,
30392		reg: regInfo{
30393			inputs: []inputInfo{
30394				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30395				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30396			},
30397			outputs: []outputInfo{
30398				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30399			},
30400		},
30401	},
30402	{
30403		name:         "SUBconst",
30404		auxType:      auxInt32,
30405		argLen:       1,
30406		resultInArg0: true,
30407		clobberFlags: true,
30408		asm:          s390x.ASUB,
30409		reg: regInfo{
30410			inputs: []inputInfo{
30411				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30412			},
30413			outputs: []outputInfo{
30414				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30415			},
30416		},
30417	},
30418	{
30419		name:         "SUBWconst",
30420		auxType:      auxInt32,
30421		argLen:       1,
30422		resultInArg0: true,
30423		clobberFlags: true,
30424		asm:          s390x.ASUBW,
30425		reg: regInfo{
30426			inputs: []inputInfo{
30427				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30428			},
30429			outputs: []outputInfo{
30430				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30431			},
30432		},
30433	},
30434	{
30435		name:           "SUBload",
30436		auxType:        auxSymOff,
30437		argLen:         3,
30438		resultInArg0:   true,
30439		clobberFlags:   true,
30440		faultOnNilArg1: true,
30441		symEffect:      SymRead,
30442		asm:            s390x.ASUB,
30443		reg: regInfo{
30444			inputs: []inputInfo{
30445				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30446				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30447			},
30448			outputs: []outputInfo{
30449				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30450			},
30451		},
30452	},
30453	{
30454		name:           "SUBWload",
30455		auxType:        auxSymOff,
30456		argLen:         3,
30457		resultInArg0:   true,
30458		clobberFlags:   true,
30459		faultOnNilArg1: true,
30460		symEffect:      SymRead,
30461		asm:            s390x.ASUBW,
30462		reg: regInfo{
30463			inputs: []inputInfo{
30464				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30465				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30466			},
30467			outputs: []outputInfo{
30468				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30469			},
30470		},
30471	},
30472	{
30473		name:         "MULLD",
30474		argLen:       2,
30475		commutative:  true,
30476		resultInArg0: true,
30477		clobberFlags: true,
30478		asm:          s390x.AMULLD,
30479		reg: regInfo{
30480			inputs: []inputInfo{
30481				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30482				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30483			},
30484			outputs: []outputInfo{
30485				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30486			},
30487		},
30488	},
30489	{
30490		name:         "MULLW",
30491		argLen:       2,
30492		commutative:  true,
30493		resultInArg0: true,
30494		clobberFlags: true,
30495		asm:          s390x.AMULLW,
30496		reg: regInfo{
30497			inputs: []inputInfo{
30498				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30499				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30500			},
30501			outputs: []outputInfo{
30502				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30503			},
30504		},
30505	},
30506	{
30507		name:         "MULLDconst",
30508		auxType:      auxInt32,
30509		argLen:       1,
30510		resultInArg0: true,
30511		clobberFlags: true,
30512		asm:          s390x.AMULLD,
30513		reg: regInfo{
30514			inputs: []inputInfo{
30515				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30516			},
30517			outputs: []outputInfo{
30518				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30519			},
30520		},
30521	},
30522	{
30523		name:         "MULLWconst",
30524		auxType:      auxInt32,
30525		argLen:       1,
30526		resultInArg0: true,
30527		clobberFlags: true,
30528		asm:          s390x.AMULLW,
30529		reg: regInfo{
30530			inputs: []inputInfo{
30531				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30532			},
30533			outputs: []outputInfo{
30534				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30535			},
30536		},
30537	},
30538	{
30539		name:           "MULLDload",
30540		auxType:        auxSymOff,
30541		argLen:         3,
30542		resultInArg0:   true,
30543		clobberFlags:   true,
30544		faultOnNilArg1: true,
30545		symEffect:      SymRead,
30546		asm:            s390x.AMULLD,
30547		reg: regInfo{
30548			inputs: []inputInfo{
30549				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30550				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30551			},
30552			outputs: []outputInfo{
30553				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30554			},
30555		},
30556	},
30557	{
30558		name:           "MULLWload",
30559		auxType:        auxSymOff,
30560		argLen:         3,
30561		resultInArg0:   true,
30562		clobberFlags:   true,
30563		faultOnNilArg1: true,
30564		symEffect:      SymRead,
30565		asm:            s390x.AMULLW,
30566		reg: regInfo{
30567			inputs: []inputInfo{
30568				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30569				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30570			},
30571			outputs: []outputInfo{
30572				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30573			},
30574		},
30575	},
30576	{
30577		name:         "MULHD",
30578		argLen:       2,
30579		commutative:  true,
30580		resultInArg0: true,
30581		clobberFlags: true,
30582		asm:          s390x.AMULHD,
30583		reg: regInfo{
30584			inputs: []inputInfo{
30585				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30586				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30587			},
30588			clobbers: 2048, // R11
30589			outputs: []outputInfo{
30590				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30591			},
30592		},
30593	},
30594	{
30595		name:         "MULHDU",
30596		argLen:       2,
30597		commutative:  true,
30598		resultInArg0: true,
30599		clobberFlags: true,
30600		asm:          s390x.AMULHDU,
30601		reg: regInfo{
30602			inputs: []inputInfo{
30603				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30604				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30605			},
30606			clobbers: 2048, // R11
30607			outputs: []outputInfo{
30608				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30609			},
30610		},
30611	},
30612	{
30613		name:         "DIVD",
30614		argLen:       2,
30615		resultInArg0: true,
30616		clobberFlags: true,
30617		asm:          s390x.ADIVD,
30618		reg: regInfo{
30619			inputs: []inputInfo{
30620				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30621				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30622			},
30623			clobbers: 2048, // R11
30624			outputs: []outputInfo{
30625				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30626			},
30627		},
30628	},
30629	{
30630		name:         "DIVW",
30631		argLen:       2,
30632		resultInArg0: true,
30633		clobberFlags: true,
30634		asm:          s390x.ADIVW,
30635		reg: regInfo{
30636			inputs: []inputInfo{
30637				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30638				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30639			},
30640			clobbers: 2048, // R11
30641			outputs: []outputInfo{
30642				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30643			},
30644		},
30645	},
30646	{
30647		name:         "DIVDU",
30648		argLen:       2,
30649		resultInArg0: true,
30650		clobberFlags: true,
30651		asm:          s390x.ADIVDU,
30652		reg: regInfo{
30653			inputs: []inputInfo{
30654				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30655				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30656			},
30657			clobbers: 2048, // R11
30658			outputs: []outputInfo{
30659				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30660			},
30661		},
30662	},
30663	{
30664		name:         "DIVWU",
30665		argLen:       2,
30666		resultInArg0: true,
30667		clobberFlags: true,
30668		asm:          s390x.ADIVWU,
30669		reg: regInfo{
30670			inputs: []inputInfo{
30671				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30672				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30673			},
30674			clobbers: 2048, // R11
30675			outputs: []outputInfo{
30676				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30677			},
30678		},
30679	},
30680	{
30681		name:         "MODD",
30682		argLen:       2,
30683		resultInArg0: true,
30684		clobberFlags: true,
30685		asm:          s390x.AMODD,
30686		reg: regInfo{
30687			inputs: []inputInfo{
30688				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30689				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30690			},
30691			clobbers: 2048, // R11
30692			outputs: []outputInfo{
30693				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30694			},
30695		},
30696	},
30697	{
30698		name:         "MODW",
30699		argLen:       2,
30700		resultInArg0: true,
30701		clobberFlags: true,
30702		asm:          s390x.AMODW,
30703		reg: regInfo{
30704			inputs: []inputInfo{
30705				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30706				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30707			},
30708			clobbers: 2048, // R11
30709			outputs: []outputInfo{
30710				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30711			},
30712		},
30713	},
30714	{
30715		name:         "MODDU",
30716		argLen:       2,
30717		resultInArg0: true,
30718		clobberFlags: true,
30719		asm:          s390x.AMODDU,
30720		reg: regInfo{
30721			inputs: []inputInfo{
30722				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30723				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30724			},
30725			clobbers: 2048, // R11
30726			outputs: []outputInfo{
30727				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30728			},
30729		},
30730	},
30731	{
30732		name:         "MODWU",
30733		argLen:       2,
30734		resultInArg0: true,
30735		clobberFlags: true,
30736		asm:          s390x.AMODWU,
30737		reg: regInfo{
30738			inputs: []inputInfo{
30739				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30740				{1, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30741			},
30742			clobbers: 2048, // R11
30743			outputs: []outputInfo{
30744				{0, 21503}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R12 R14
30745			},
30746		},
30747	},
30748	{
30749		name:         "AND",
30750		argLen:       2,
30751		commutative:  true,
30752		clobberFlags: true,
30753		asm:          s390x.AAND,
30754		reg: regInfo{
30755			inputs: []inputInfo{
30756				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30757				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30758			},
30759			outputs: []outputInfo{
30760				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30761			},
30762		},
30763	},
30764	{
30765		name:         "ANDW",
30766		argLen:       2,
30767		commutative:  true,
30768		clobberFlags: true,
30769		asm:          s390x.AANDW,
30770		reg: regInfo{
30771			inputs: []inputInfo{
30772				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30773				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30774			},
30775			outputs: []outputInfo{
30776				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30777			},
30778		},
30779	},
30780	{
30781		name:         "ANDconst",
30782		auxType:      auxInt64,
30783		argLen:       1,
30784		resultInArg0: true,
30785		clobberFlags: true,
30786		asm:          s390x.AAND,
30787		reg: regInfo{
30788			inputs: []inputInfo{
30789				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30790			},
30791			outputs: []outputInfo{
30792				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30793			},
30794		},
30795	},
30796	{
30797		name:         "ANDWconst",
30798		auxType:      auxInt32,
30799		argLen:       1,
30800		resultInArg0: true,
30801		clobberFlags: true,
30802		asm:          s390x.AANDW,
30803		reg: regInfo{
30804			inputs: []inputInfo{
30805				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30806			},
30807			outputs: []outputInfo{
30808				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30809			},
30810		},
30811	},
30812	{
30813		name:           "ANDload",
30814		auxType:        auxSymOff,
30815		argLen:         3,
30816		resultInArg0:   true,
30817		clobberFlags:   true,
30818		faultOnNilArg1: true,
30819		symEffect:      SymRead,
30820		asm:            s390x.AAND,
30821		reg: regInfo{
30822			inputs: []inputInfo{
30823				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30824				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30825			},
30826			outputs: []outputInfo{
30827				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30828			},
30829		},
30830	},
30831	{
30832		name:           "ANDWload",
30833		auxType:        auxSymOff,
30834		argLen:         3,
30835		resultInArg0:   true,
30836		clobberFlags:   true,
30837		faultOnNilArg1: true,
30838		symEffect:      SymRead,
30839		asm:            s390x.AANDW,
30840		reg: regInfo{
30841			inputs: []inputInfo{
30842				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30843				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30844			},
30845			outputs: []outputInfo{
30846				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30847			},
30848		},
30849	},
30850	{
30851		name:         "OR",
30852		argLen:       2,
30853		commutative:  true,
30854		clobberFlags: true,
30855		asm:          s390x.AOR,
30856		reg: regInfo{
30857			inputs: []inputInfo{
30858				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30859				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30860			},
30861			outputs: []outputInfo{
30862				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30863			},
30864		},
30865	},
30866	{
30867		name:         "ORW",
30868		argLen:       2,
30869		commutative:  true,
30870		clobberFlags: true,
30871		asm:          s390x.AORW,
30872		reg: regInfo{
30873			inputs: []inputInfo{
30874				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30875				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30876			},
30877			outputs: []outputInfo{
30878				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30879			},
30880		},
30881	},
30882	{
30883		name:         "ORconst",
30884		auxType:      auxInt64,
30885		argLen:       1,
30886		resultInArg0: true,
30887		clobberFlags: true,
30888		asm:          s390x.AOR,
30889		reg: regInfo{
30890			inputs: []inputInfo{
30891				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30892			},
30893			outputs: []outputInfo{
30894				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30895			},
30896		},
30897	},
30898	{
30899		name:         "ORWconst",
30900		auxType:      auxInt32,
30901		argLen:       1,
30902		resultInArg0: true,
30903		clobberFlags: true,
30904		asm:          s390x.AORW,
30905		reg: regInfo{
30906			inputs: []inputInfo{
30907				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30908			},
30909			outputs: []outputInfo{
30910				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30911			},
30912		},
30913	},
30914	{
30915		name:           "ORload",
30916		auxType:        auxSymOff,
30917		argLen:         3,
30918		resultInArg0:   true,
30919		clobberFlags:   true,
30920		faultOnNilArg1: true,
30921		symEffect:      SymRead,
30922		asm:            s390x.AOR,
30923		reg: regInfo{
30924			inputs: []inputInfo{
30925				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30926				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30927			},
30928			outputs: []outputInfo{
30929				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30930			},
30931		},
30932	},
30933	{
30934		name:           "ORWload",
30935		auxType:        auxSymOff,
30936		argLen:         3,
30937		resultInArg0:   true,
30938		clobberFlags:   true,
30939		faultOnNilArg1: true,
30940		symEffect:      SymRead,
30941		asm:            s390x.AORW,
30942		reg: regInfo{
30943			inputs: []inputInfo{
30944				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30945				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
30946			},
30947			outputs: []outputInfo{
30948				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30949			},
30950		},
30951	},
30952	{
30953		name:         "XOR",
30954		argLen:       2,
30955		commutative:  true,
30956		clobberFlags: true,
30957		asm:          s390x.AXOR,
30958		reg: regInfo{
30959			inputs: []inputInfo{
30960				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30961				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30962			},
30963			outputs: []outputInfo{
30964				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30965			},
30966		},
30967	},
30968	{
30969		name:         "XORW",
30970		argLen:       2,
30971		commutative:  true,
30972		clobberFlags: true,
30973		asm:          s390x.AXORW,
30974		reg: regInfo{
30975			inputs: []inputInfo{
30976				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30977				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30978			},
30979			outputs: []outputInfo{
30980				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30981			},
30982		},
30983	},
30984	{
30985		name:         "XORconst",
30986		auxType:      auxInt64,
30987		argLen:       1,
30988		resultInArg0: true,
30989		clobberFlags: true,
30990		asm:          s390x.AXOR,
30991		reg: regInfo{
30992			inputs: []inputInfo{
30993				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30994			},
30995			outputs: []outputInfo{
30996				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
30997			},
30998		},
30999	},
31000	{
31001		name:         "XORWconst",
31002		auxType:      auxInt32,
31003		argLen:       1,
31004		resultInArg0: true,
31005		clobberFlags: true,
31006		asm:          s390x.AXORW,
31007		reg: regInfo{
31008			inputs: []inputInfo{
31009				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31010			},
31011			outputs: []outputInfo{
31012				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31013			},
31014		},
31015	},
31016	{
31017		name:           "XORload",
31018		auxType:        auxSymOff,
31019		argLen:         3,
31020		resultInArg0:   true,
31021		clobberFlags:   true,
31022		faultOnNilArg1: true,
31023		symEffect:      SymRead,
31024		asm:            s390x.AXOR,
31025		reg: regInfo{
31026			inputs: []inputInfo{
31027				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31028				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31029			},
31030			outputs: []outputInfo{
31031				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31032			},
31033		},
31034	},
31035	{
31036		name:           "XORWload",
31037		auxType:        auxSymOff,
31038		argLen:         3,
31039		resultInArg0:   true,
31040		clobberFlags:   true,
31041		faultOnNilArg1: true,
31042		symEffect:      SymRead,
31043		asm:            s390x.AXORW,
31044		reg: regInfo{
31045			inputs: []inputInfo{
31046				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31047				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31048			},
31049			outputs: []outputInfo{
31050				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31051			},
31052		},
31053	},
31054	{
31055		name:        "ADDC",
31056		argLen:      2,
31057		commutative: true,
31058		asm:         s390x.AADDC,
31059		reg: regInfo{
31060			inputs: []inputInfo{
31061				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31062				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31063			},
31064			outputs: []outputInfo{
31065				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31066			},
31067		},
31068	},
31069	{
31070		name:    "ADDCconst",
31071		auxType: auxInt16,
31072		argLen:  1,
31073		asm:     s390x.AADDC,
31074		reg: regInfo{
31075			inputs: []inputInfo{
31076				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31077			},
31078			outputs: []outputInfo{
31079				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31080			},
31081		},
31082	},
31083	{
31084		name:         "ADDE",
31085		argLen:       3,
31086		commutative:  true,
31087		resultInArg0: true,
31088		asm:          s390x.AADDE,
31089		reg: regInfo{
31090			inputs: []inputInfo{
31091				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31092				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31093			},
31094			outputs: []outputInfo{
31095				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31096			},
31097		},
31098	},
31099	{
31100		name:   "SUBC",
31101		argLen: 2,
31102		asm:    s390x.ASUBC,
31103		reg: regInfo{
31104			inputs: []inputInfo{
31105				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31106				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31107			},
31108			outputs: []outputInfo{
31109				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31110			},
31111		},
31112	},
31113	{
31114		name:         "SUBE",
31115		argLen:       3,
31116		resultInArg0: true,
31117		asm:          s390x.ASUBE,
31118		reg: regInfo{
31119			inputs: []inputInfo{
31120				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31121				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31122			},
31123			outputs: []outputInfo{
31124				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31125			},
31126		},
31127	},
31128	{
31129		name:   "CMP",
31130		argLen: 2,
31131		asm:    s390x.ACMP,
31132		reg: regInfo{
31133			inputs: []inputInfo{
31134				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31135				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31136			},
31137		},
31138	},
31139	{
31140		name:   "CMPW",
31141		argLen: 2,
31142		asm:    s390x.ACMPW,
31143		reg: regInfo{
31144			inputs: []inputInfo{
31145				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31146				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31147			},
31148		},
31149	},
31150	{
31151		name:   "CMPU",
31152		argLen: 2,
31153		asm:    s390x.ACMPU,
31154		reg: regInfo{
31155			inputs: []inputInfo{
31156				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31157				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31158			},
31159		},
31160	},
31161	{
31162		name:   "CMPWU",
31163		argLen: 2,
31164		asm:    s390x.ACMPWU,
31165		reg: regInfo{
31166			inputs: []inputInfo{
31167				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31168				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31169			},
31170		},
31171	},
31172	{
31173		name:    "CMPconst",
31174		auxType: auxInt32,
31175		argLen:  1,
31176		asm:     s390x.ACMP,
31177		reg: regInfo{
31178			inputs: []inputInfo{
31179				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31180			},
31181		},
31182	},
31183	{
31184		name:    "CMPWconst",
31185		auxType: auxInt32,
31186		argLen:  1,
31187		asm:     s390x.ACMPW,
31188		reg: regInfo{
31189			inputs: []inputInfo{
31190				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31191			},
31192		},
31193	},
31194	{
31195		name:    "CMPUconst",
31196		auxType: auxInt32,
31197		argLen:  1,
31198		asm:     s390x.ACMPU,
31199		reg: regInfo{
31200			inputs: []inputInfo{
31201				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31202			},
31203		},
31204	},
31205	{
31206		name:    "CMPWUconst",
31207		auxType: auxInt32,
31208		argLen:  1,
31209		asm:     s390x.ACMPWU,
31210		reg: regInfo{
31211			inputs: []inputInfo{
31212				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31213			},
31214		},
31215	},
31216	{
31217		name:   "FCMPS",
31218		argLen: 2,
31219		asm:    s390x.ACEBR,
31220		reg: regInfo{
31221			inputs: []inputInfo{
31222				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31223				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31224			},
31225		},
31226	},
31227	{
31228		name:   "FCMP",
31229		argLen: 2,
31230		asm:    s390x.AFCMPU,
31231		reg: regInfo{
31232			inputs: []inputInfo{
31233				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31234				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31235			},
31236		},
31237	},
31238	{
31239		name:   "LTDBR",
31240		argLen: 1,
31241		asm:    s390x.ALTDBR,
31242		reg: regInfo{
31243			inputs: []inputInfo{
31244				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31245			},
31246		},
31247	},
31248	{
31249		name:   "LTEBR",
31250		argLen: 1,
31251		asm:    s390x.ALTEBR,
31252		reg: regInfo{
31253			inputs: []inputInfo{
31254				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31255			},
31256		},
31257	},
31258	{
31259		name:   "SLD",
31260		argLen: 2,
31261		asm:    s390x.ASLD,
31262		reg: regInfo{
31263			inputs: []inputInfo{
31264				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31265				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31266			},
31267			outputs: []outputInfo{
31268				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31269			},
31270		},
31271	},
31272	{
31273		name:   "SLW",
31274		argLen: 2,
31275		asm:    s390x.ASLW,
31276		reg: regInfo{
31277			inputs: []inputInfo{
31278				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31279				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31280			},
31281			outputs: []outputInfo{
31282				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31283			},
31284		},
31285	},
31286	{
31287		name:    "SLDconst",
31288		auxType: auxUInt8,
31289		argLen:  1,
31290		asm:     s390x.ASLD,
31291		reg: regInfo{
31292			inputs: []inputInfo{
31293				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31294			},
31295			outputs: []outputInfo{
31296				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31297			},
31298		},
31299	},
31300	{
31301		name:    "SLWconst",
31302		auxType: auxUInt8,
31303		argLen:  1,
31304		asm:     s390x.ASLW,
31305		reg: regInfo{
31306			inputs: []inputInfo{
31307				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31308			},
31309			outputs: []outputInfo{
31310				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31311			},
31312		},
31313	},
31314	{
31315		name:   "SRD",
31316		argLen: 2,
31317		asm:    s390x.ASRD,
31318		reg: regInfo{
31319			inputs: []inputInfo{
31320				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31321				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31322			},
31323			outputs: []outputInfo{
31324				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31325			},
31326		},
31327	},
31328	{
31329		name:   "SRW",
31330		argLen: 2,
31331		asm:    s390x.ASRW,
31332		reg: regInfo{
31333			inputs: []inputInfo{
31334				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31335				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31336			},
31337			outputs: []outputInfo{
31338				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31339			},
31340		},
31341	},
31342	{
31343		name:    "SRDconst",
31344		auxType: auxUInt8,
31345		argLen:  1,
31346		asm:     s390x.ASRD,
31347		reg: regInfo{
31348			inputs: []inputInfo{
31349				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31350			},
31351			outputs: []outputInfo{
31352				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31353			},
31354		},
31355	},
31356	{
31357		name:    "SRWconst",
31358		auxType: auxUInt8,
31359		argLen:  1,
31360		asm:     s390x.ASRW,
31361		reg: regInfo{
31362			inputs: []inputInfo{
31363				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31364			},
31365			outputs: []outputInfo{
31366				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31367			},
31368		},
31369	},
31370	{
31371		name:         "SRAD",
31372		argLen:       2,
31373		clobberFlags: true,
31374		asm:          s390x.ASRAD,
31375		reg: regInfo{
31376			inputs: []inputInfo{
31377				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31378				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31379			},
31380			outputs: []outputInfo{
31381				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31382			},
31383		},
31384	},
31385	{
31386		name:         "SRAW",
31387		argLen:       2,
31388		clobberFlags: true,
31389		asm:          s390x.ASRAW,
31390		reg: regInfo{
31391			inputs: []inputInfo{
31392				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31393				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31394			},
31395			outputs: []outputInfo{
31396				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31397			},
31398		},
31399	},
31400	{
31401		name:         "SRADconst",
31402		auxType:      auxUInt8,
31403		argLen:       1,
31404		clobberFlags: true,
31405		asm:          s390x.ASRAD,
31406		reg: regInfo{
31407			inputs: []inputInfo{
31408				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31409			},
31410			outputs: []outputInfo{
31411				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31412			},
31413		},
31414	},
31415	{
31416		name:         "SRAWconst",
31417		auxType:      auxUInt8,
31418		argLen:       1,
31419		clobberFlags: true,
31420		asm:          s390x.ASRAW,
31421		reg: regInfo{
31422			inputs: []inputInfo{
31423				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31424			},
31425			outputs: []outputInfo{
31426				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31427			},
31428		},
31429	},
31430	{
31431		name:   "RLLG",
31432		argLen: 2,
31433		asm:    s390x.ARLLG,
31434		reg: regInfo{
31435			inputs: []inputInfo{
31436				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31437				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31438			},
31439			outputs: []outputInfo{
31440				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31441			},
31442		},
31443	},
31444	{
31445		name:   "RLL",
31446		argLen: 2,
31447		asm:    s390x.ARLL,
31448		reg: regInfo{
31449			inputs: []inputInfo{
31450				{1, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31451				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31452			},
31453			outputs: []outputInfo{
31454				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31455			},
31456		},
31457	},
31458	{
31459		name:    "RLLconst",
31460		auxType: auxUInt8,
31461		argLen:  1,
31462		asm:     s390x.ARLL,
31463		reg: regInfo{
31464			inputs: []inputInfo{
31465				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31466			},
31467			outputs: []outputInfo{
31468				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31469			},
31470		},
31471	},
31472	{
31473		name:         "RXSBG",
31474		auxType:      auxS390XRotateParams,
31475		argLen:       2,
31476		resultInArg0: true,
31477		clobberFlags: true,
31478		asm:          s390x.ARXSBG,
31479		reg: regInfo{
31480			inputs: []inputInfo{
31481				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31482				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31483			},
31484			outputs: []outputInfo{
31485				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31486			},
31487		},
31488	},
31489	{
31490		name:         "RISBGZ",
31491		auxType:      auxS390XRotateParams,
31492		argLen:       1,
31493		clobberFlags: true,
31494		asm:          s390x.ARISBGZ,
31495		reg: regInfo{
31496			inputs: []inputInfo{
31497				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31498			},
31499			outputs: []outputInfo{
31500				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31501			},
31502		},
31503	},
31504	{
31505		name:         "NEG",
31506		argLen:       1,
31507		clobberFlags: true,
31508		asm:          s390x.ANEG,
31509		reg: regInfo{
31510			inputs: []inputInfo{
31511				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31512			},
31513			outputs: []outputInfo{
31514				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31515			},
31516		},
31517	},
31518	{
31519		name:         "NEGW",
31520		argLen:       1,
31521		clobberFlags: true,
31522		asm:          s390x.ANEGW,
31523		reg: regInfo{
31524			inputs: []inputInfo{
31525				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31526			},
31527			outputs: []outputInfo{
31528				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31529			},
31530		},
31531	},
31532	{
31533		name:         "NOT",
31534		argLen:       1,
31535		resultInArg0: true,
31536		clobberFlags: true,
31537		reg: regInfo{
31538			inputs: []inputInfo{
31539				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31540			},
31541			outputs: []outputInfo{
31542				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31543			},
31544		},
31545	},
31546	{
31547		name:         "NOTW",
31548		argLen:       1,
31549		resultInArg0: true,
31550		clobberFlags: true,
31551		reg: regInfo{
31552			inputs: []inputInfo{
31553				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31554			},
31555			outputs: []outputInfo{
31556				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31557			},
31558		},
31559	},
31560	{
31561		name:   "FSQRT",
31562		argLen: 1,
31563		asm:    s390x.AFSQRT,
31564		reg: regInfo{
31565			inputs: []inputInfo{
31566				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31567			},
31568			outputs: []outputInfo{
31569				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31570			},
31571		},
31572	},
31573	{
31574		name:   "FSQRTS",
31575		argLen: 1,
31576		asm:    s390x.AFSQRTS,
31577		reg: regInfo{
31578			inputs: []inputInfo{
31579				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31580			},
31581			outputs: []outputInfo{
31582				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31583			},
31584		},
31585	},
31586	{
31587		name:         "LOCGR",
31588		auxType:      auxS390XCCMask,
31589		argLen:       3,
31590		resultInArg0: true,
31591		asm:          s390x.ALOCGR,
31592		reg: regInfo{
31593			inputs: []inputInfo{
31594				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31595				{1, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31596			},
31597			outputs: []outputInfo{
31598				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31599			},
31600		},
31601	},
31602	{
31603		name:   "MOVBreg",
31604		argLen: 1,
31605		asm:    s390x.AMOVB,
31606		reg: regInfo{
31607			inputs: []inputInfo{
31608				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31609			},
31610			outputs: []outputInfo{
31611				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31612			},
31613		},
31614	},
31615	{
31616		name:   "MOVBZreg",
31617		argLen: 1,
31618		asm:    s390x.AMOVBZ,
31619		reg: regInfo{
31620			inputs: []inputInfo{
31621				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31622			},
31623			outputs: []outputInfo{
31624				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31625			},
31626		},
31627	},
31628	{
31629		name:   "MOVHreg",
31630		argLen: 1,
31631		asm:    s390x.AMOVH,
31632		reg: regInfo{
31633			inputs: []inputInfo{
31634				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31635			},
31636			outputs: []outputInfo{
31637				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31638			},
31639		},
31640	},
31641	{
31642		name:   "MOVHZreg",
31643		argLen: 1,
31644		asm:    s390x.AMOVHZ,
31645		reg: regInfo{
31646			inputs: []inputInfo{
31647				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31648			},
31649			outputs: []outputInfo{
31650				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31651			},
31652		},
31653	},
31654	{
31655		name:   "MOVWreg",
31656		argLen: 1,
31657		asm:    s390x.AMOVW,
31658		reg: regInfo{
31659			inputs: []inputInfo{
31660				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31661			},
31662			outputs: []outputInfo{
31663				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31664			},
31665		},
31666	},
31667	{
31668		name:   "MOVWZreg",
31669		argLen: 1,
31670		asm:    s390x.AMOVWZ,
31671		reg: regInfo{
31672			inputs: []inputInfo{
31673				{0, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31674			},
31675			outputs: []outputInfo{
31676				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31677			},
31678		},
31679	},
31680	{
31681		name:              "MOVDconst",
31682		auxType:           auxInt64,
31683		argLen:            0,
31684		rematerializeable: true,
31685		asm:               s390x.AMOVD,
31686		reg: regInfo{
31687			outputs: []outputInfo{
31688				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31689			},
31690		},
31691	},
31692	{
31693		name:   "LDGR",
31694		argLen: 1,
31695		asm:    s390x.ALDGR,
31696		reg: regInfo{
31697			inputs: []inputInfo{
31698				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31699			},
31700			outputs: []outputInfo{
31701				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31702			},
31703		},
31704	},
31705	{
31706		name:   "LGDR",
31707		argLen: 1,
31708		asm:    s390x.ALGDR,
31709		reg: regInfo{
31710			inputs: []inputInfo{
31711				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31712			},
31713			outputs: []outputInfo{
31714				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31715			},
31716		},
31717	},
31718	{
31719		name:         "CFDBRA",
31720		argLen:       1,
31721		clobberFlags: true,
31722		asm:          s390x.ACFDBRA,
31723		reg: regInfo{
31724			inputs: []inputInfo{
31725				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31726			},
31727			outputs: []outputInfo{
31728				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31729			},
31730		},
31731	},
31732	{
31733		name:         "CGDBRA",
31734		argLen:       1,
31735		clobberFlags: true,
31736		asm:          s390x.ACGDBRA,
31737		reg: regInfo{
31738			inputs: []inputInfo{
31739				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31740			},
31741			outputs: []outputInfo{
31742				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31743			},
31744		},
31745	},
31746	{
31747		name:         "CFEBRA",
31748		argLen:       1,
31749		clobberFlags: true,
31750		asm:          s390x.ACFEBRA,
31751		reg: regInfo{
31752			inputs: []inputInfo{
31753				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31754			},
31755			outputs: []outputInfo{
31756				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31757			},
31758		},
31759	},
31760	{
31761		name:         "CGEBRA",
31762		argLen:       1,
31763		clobberFlags: true,
31764		asm:          s390x.ACGEBRA,
31765		reg: regInfo{
31766			inputs: []inputInfo{
31767				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31768			},
31769			outputs: []outputInfo{
31770				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31771			},
31772		},
31773	},
31774	{
31775		name:         "CEFBRA",
31776		argLen:       1,
31777		clobberFlags: true,
31778		asm:          s390x.ACEFBRA,
31779		reg: regInfo{
31780			inputs: []inputInfo{
31781				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31782			},
31783			outputs: []outputInfo{
31784				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31785			},
31786		},
31787	},
31788	{
31789		name:         "CDFBRA",
31790		argLen:       1,
31791		clobberFlags: true,
31792		asm:          s390x.ACDFBRA,
31793		reg: regInfo{
31794			inputs: []inputInfo{
31795				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31796			},
31797			outputs: []outputInfo{
31798				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31799			},
31800		},
31801	},
31802	{
31803		name:         "CEGBRA",
31804		argLen:       1,
31805		clobberFlags: true,
31806		asm:          s390x.ACEGBRA,
31807		reg: regInfo{
31808			inputs: []inputInfo{
31809				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31810			},
31811			outputs: []outputInfo{
31812				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31813			},
31814		},
31815	},
31816	{
31817		name:         "CDGBRA",
31818		argLen:       1,
31819		clobberFlags: true,
31820		asm:          s390x.ACDGBRA,
31821		reg: regInfo{
31822			inputs: []inputInfo{
31823				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31824			},
31825			outputs: []outputInfo{
31826				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31827			},
31828		},
31829	},
31830	{
31831		name:         "CLFEBR",
31832		argLen:       1,
31833		clobberFlags: true,
31834		asm:          s390x.ACLFEBR,
31835		reg: regInfo{
31836			inputs: []inputInfo{
31837				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31838			},
31839			outputs: []outputInfo{
31840				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31841			},
31842		},
31843	},
31844	{
31845		name:         "CLFDBR",
31846		argLen:       1,
31847		clobberFlags: true,
31848		asm:          s390x.ACLFDBR,
31849		reg: regInfo{
31850			inputs: []inputInfo{
31851				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31852			},
31853			outputs: []outputInfo{
31854				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31855			},
31856		},
31857	},
31858	{
31859		name:         "CLGEBR",
31860		argLen:       1,
31861		clobberFlags: true,
31862		asm:          s390x.ACLGEBR,
31863		reg: regInfo{
31864			inputs: []inputInfo{
31865				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31866			},
31867			outputs: []outputInfo{
31868				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31869			},
31870		},
31871	},
31872	{
31873		name:         "CLGDBR",
31874		argLen:       1,
31875		clobberFlags: true,
31876		asm:          s390x.ACLGDBR,
31877		reg: regInfo{
31878			inputs: []inputInfo{
31879				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31880			},
31881			outputs: []outputInfo{
31882				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31883			},
31884		},
31885	},
31886	{
31887		name:         "CELFBR",
31888		argLen:       1,
31889		clobberFlags: true,
31890		asm:          s390x.ACELFBR,
31891		reg: regInfo{
31892			inputs: []inputInfo{
31893				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31894			},
31895			outputs: []outputInfo{
31896				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31897			},
31898		},
31899	},
31900	{
31901		name:         "CDLFBR",
31902		argLen:       1,
31903		clobberFlags: true,
31904		asm:          s390x.ACDLFBR,
31905		reg: regInfo{
31906			inputs: []inputInfo{
31907				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31908			},
31909			outputs: []outputInfo{
31910				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31911			},
31912		},
31913	},
31914	{
31915		name:         "CELGBR",
31916		argLen:       1,
31917		clobberFlags: true,
31918		asm:          s390x.ACELGBR,
31919		reg: regInfo{
31920			inputs: []inputInfo{
31921				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31922			},
31923			outputs: []outputInfo{
31924				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31925			},
31926		},
31927	},
31928	{
31929		name:         "CDLGBR",
31930		argLen:       1,
31931		clobberFlags: true,
31932		asm:          s390x.ACDLGBR,
31933		reg: regInfo{
31934			inputs: []inputInfo{
31935				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31936			},
31937			outputs: []outputInfo{
31938				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31939			},
31940		},
31941	},
31942	{
31943		name:   "LEDBR",
31944		argLen: 1,
31945		asm:    s390x.ALEDBR,
31946		reg: regInfo{
31947			inputs: []inputInfo{
31948				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31949			},
31950			outputs: []outputInfo{
31951				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31952			},
31953		},
31954	},
31955	{
31956		name:   "LDEBR",
31957		argLen: 1,
31958		asm:    s390x.ALDEBR,
31959		reg: regInfo{
31960			inputs: []inputInfo{
31961				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31962			},
31963			outputs: []outputInfo{
31964				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
31965			},
31966		},
31967	},
31968	{
31969		name:              "MOVDaddr",
31970		auxType:           auxSymOff,
31971		argLen:            1,
31972		rematerializeable: true,
31973		symEffect:         SymRead,
31974		reg: regInfo{
31975			inputs: []inputInfo{
31976				{0, 4295000064}, // SP SB
31977			},
31978			outputs: []outputInfo{
31979				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31980			},
31981		},
31982	},
31983	{
31984		name:      "MOVDaddridx",
31985		auxType:   auxSymOff,
31986		argLen:    2,
31987		symEffect: SymRead,
31988		reg: regInfo{
31989			inputs: []inputInfo{
31990				{0, 4295000064}, // SP SB
31991				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
31992			},
31993			outputs: []outputInfo{
31994				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
31995			},
31996		},
31997	},
31998	{
31999		name:           "MOVBZload",
32000		auxType:        auxSymOff,
32001		argLen:         2,
32002		faultOnNilArg0: true,
32003		symEffect:      SymRead,
32004		asm:            s390x.AMOVBZ,
32005		reg: regInfo{
32006			inputs: []inputInfo{
32007				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32008			},
32009			outputs: []outputInfo{
32010				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32011			},
32012		},
32013	},
32014	{
32015		name:           "MOVBload",
32016		auxType:        auxSymOff,
32017		argLen:         2,
32018		faultOnNilArg0: true,
32019		symEffect:      SymRead,
32020		asm:            s390x.AMOVB,
32021		reg: regInfo{
32022			inputs: []inputInfo{
32023				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32024			},
32025			outputs: []outputInfo{
32026				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32027			},
32028		},
32029	},
32030	{
32031		name:           "MOVHZload",
32032		auxType:        auxSymOff,
32033		argLen:         2,
32034		faultOnNilArg0: true,
32035		symEffect:      SymRead,
32036		asm:            s390x.AMOVHZ,
32037		reg: regInfo{
32038			inputs: []inputInfo{
32039				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32040			},
32041			outputs: []outputInfo{
32042				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32043			},
32044		},
32045	},
32046	{
32047		name:           "MOVHload",
32048		auxType:        auxSymOff,
32049		argLen:         2,
32050		faultOnNilArg0: true,
32051		symEffect:      SymRead,
32052		asm:            s390x.AMOVH,
32053		reg: regInfo{
32054			inputs: []inputInfo{
32055				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32056			},
32057			outputs: []outputInfo{
32058				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32059			},
32060		},
32061	},
32062	{
32063		name:           "MOVWZload",
32064		auxType:        auxSymOff,
32065		argLen:         2,
32066		faultOnNilArg0: true,
32067		symEffect:      SymRead,
32068		asm:            s390x.AMOVWZ,
32069		reg: regInfo{
32070			inputs: []inputInfo{
32071				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32072			},
32073			outputs: []outputInfo{
32074				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32075			},
32076		},
32077	},
32078	{
32079		name:           "MOVWload",
32080		auxType:        auxSymOff,
32081		argLen:         2,
32082		faultOnNilArg0: true,
32083		symEffect:      SymRead,
32084		asm:            s390x.AMOVW,
32085		reg: regInfo{
32086			inputs: []inputInfo{
32087				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32088			},
32089			outputs: []outputInfo{
32090				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32091			},
32092		},
32093	},
32094	{
32095		name:           "MOVDload",
32096		auxType:        auxSymOff,
32097		argLen:         2,
32098		faultOnNilArg0: true,
32099		symEffect:      SymRead,
32100		asm:            s390x.AMOVD,
32101		reg: regInfo{
32102			inputs: []inputInfo{
32103				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32104			},
32105			outputs: []outputInfo{
32106				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32107			},
32108		},
32109	},
32110	{
32111		name:   "MOVWBR",
32112		argLen: 1,
32113		asm:    s390x.AMOVWBR,
32114		reg: regInfo{
32115			inputs: []inputInfo{
32116				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32117			},
32118			outputs: []outputInfo{
32119				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32120			},
32121		},
32122	},
32123	{
32124		name:   "MOVDBR",
32125		argLen: 1,
32126		asm:    s390x.AMOVDBR,
32127		reg: regInfo{
32128			inputs: []inputInfo{
32129				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32130			},
32131			outputs: []outputInfo{
32132				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32133			},
32134		},
32135	},
32136	{
32137		name:           "MOVHBRload",
32138		auxType:        auxSymOff,
32139		argLen:         2,
32140		faultOnNilArg0: true,
32141		symEffect:      SymRead,
32142		asm:            s390x.AMOVHBR,
32143		reg: regInfo{
32144			inputs: []inputInfo{
32145				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32146			},
32147			outputs: []outputInfo{
32148				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32149			},
32150		},
32151	},
32152	{
32153		name:           "MOVWBRload",
32154		auxType:        auxSymOff,
32155		argLen:         2,
32156		faultOnNilArg0: true,
32157		symEffect:      SymRead,
32158		asm:            s390x.AMOVWBR,
32159		reg: regInfo{
32160			inputs: []inputInfo{
32161				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32162			},
32163			outputs: []outputInfo{
32164				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32165			},
32166		},
32167	},
32168	{
32169		name:           "MOVDBRload",
32170		auxType:        auxSymOff,
32171		argLen:         2,
32172		faultOnNilArg0: true,
32173		symEffect:      SymRead,
32174		asm:            s390x.AMOVDBR,
32175		reg: regInfo{
32176			inputs: []inputInfo{
32177				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32178			},
32179			outputs: []outputInfo{
32180				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32181			},
32182		},
32183	},
32184	{
32185		name:           "MOVBstore",
32186		auxType:        auxSymOff,
32187		argLen:         3,
32188		faultOnNilArg0: true,
32189		symEffect:      SymWrite,
32190		asm:            s390x.AMOVB,
32191		reg: regInfo{
32192			inputs: []inputInfo{
32193				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32194				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32195			},
32196		},
32197	},
32198	{
32199		name:           "MOVHstore",
32200		auxType:        auxSymOff,
32201		argLen:         3,
32202		faultOnNilArg0: true,
32203		symEffect:      SymWrite,
32204		asm:            s390x.AMOVH,
32205		reg: regInfo{
32206			inputs: []inputInfo{
32207				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32208				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32209			},
32210		},
32211	},
32212	{
32213		name:           "MOVWstore",
32214		auxType:        auxSymOff,
32215		argLen:         3,
32216		faultOnNilArg0: true,
32217		symEffect:      SymWrite,
32218		asm:            s390x.AMOVW,
32219		reg: regInfo{
32220			inputs: []inputInfo{
32221				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32222				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32223			},
32224		},
32225	},
32226	{
32227		name:           "MOVDstore",
32228		auxType:        auxSymOff,
32229		argLen:         3,
32230		faultOnNilArg0: true,
32231		symEffect:      SymWrite,
32232		asm:            s390x.AMOVD,
32233		reg: regInfo{
32234			inputs: []inputInfo{
32235				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32236				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32237			},
32238		},
32239	},
32240	{
32241		name:           "MOVHBRstore",
32242		auxType:        auxSymOff,
32243		argLen:         3,
32244		faultOnNilArg0: true,
32245		symEffect:      SymWrite,
32246		asm:            s390x.AMOVHBR,
32247		reg: regInfo{
32248			inputs: []inputInfo{
32249				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32250				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32251			},
32252		},
32253	},
32254	{
32255		name:           "MOVWBRstore",
32256		auxType:        auxSymOff,
32257		argLen:         3,
32258		faultOnNilArg0: true,
32259		symEffect:      SymWrite,
32260		asm:            s390x.AMOVWBR,
32261		reg: regInfo{
32262			inputs: []inputInfo{
32263				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32264				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32265			},
32266		},
32267	},
32268	{
32269		name:           "MOVDBRstore",
32270		auxType:        auxSymOff,
32271		argLen:         3,
32272		faultOnNilArg0: true,
32273		symEffect:      SymWrite,
32274		asm:            s390x.AMOVDBR,
32275		reg: regInfo{
32276			inputs: []inputInfo{
32277				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32278				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32279			},
32280		},
32281	},
32282	{
32283		name:           "MVC",
32284		auxType:        auxSymValAndOff,
32285		argLen:         3,
32286		clobberFlags:   true,
32287		faultOnNilArg0: true,
32288		faultOnNilArg1: true,
32289		symEffect:      SymNone,
32290		asm:            s390x.AMVC,
32291		reg: regInfo{
32292			inputs: []inputInfo{
32293				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32294				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32295			},
32296		},
32297	},
32298	{
32299		name:        "MOVBZloadidx",
32300		auxType:     auxSymOff,
32301		argLen:      3,
32302		commutative: true,
32303		symEffect:   SymRead,
32304		asm:         s390x.AMOVBZ,
32305		reg: regInfo{
32306			inputs: []inputInfo{
32307				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32308				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32309			},
32310			outputs: []outputInfo{
32311				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32312			},
32313		},
32314	},
32315	{
32316		name:        "MOVBloadidx",
32317		auxType:     auxSymOff,
32318		argLen:      3,
32319		commutative: true,
32320		symEffect:   SymRead,
32321		asm:         s390x.AMOVB,
32322		reg: regInfo{
32323			inputs: []inputInfo{
32324				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32325				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32326			},
32327			outputs: []outputInfo{
32328				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32329			},
32330		},
32331	},
32332	{
32333		name:        "MOVHZloadidx",
32334		auxType:     auxSymOff,
32335		argLen:      3,
32336		commutative: true,
32337		symEffect:   SymRead,
32338		asm:         s390x.AMOVHZ,
32339		reg: regInfo{
32340			inputs: []inputInfo{
32341				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32342				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32343			},
32344			outputs: []outputInfo{
32345				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32346			},
32347		},
32348	},
32349	{
32350		name:        "MOVHloadidx",
32351		auxType:     auxSymOff,
32352		argLen:      3,
32353		commutative: true,
32354		symEffect:   SymRead,
32355		asm:         s390x.AMOVH,
32356		reg: regInfo{
32357			inputs: []inputInfo{
32358				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32359				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32360			},
32361			outputs: []outputInfo{
32362				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32363			},
32364		},
32365	},
32366	{
32367		name:        "MOVWZloadidx",
32368		auxType:     auxSymOff,
32369		argLen:      3,
32370		commutative: true,
32371		symEffect:   SymRead,
32372		asm:         s390x.AMOVWZ,
32373		reg: regInfo{
32374			inputs: []inputInfo{
32375				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32376				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32377			},
32378			outputs: []outputInfo{
32379				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32380			},
32381		},
32382	},
32383	{
32384		name:        "MOVWloadidx",
32385		auxType:     auxSymOff,
32386		argLen:      3,
32387		commutative: true,
32388		symEffect:   SymRead,
32389		asm:         s390x.AMOVW,
32390		reg: regInfo{
32391			inputs: []inputInfo{
32392				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32393				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32394			},
32395			outputs: []outputInfo{
32396				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32397			},
32398		},
32399	},
32400	{
32401		name:        "MOVDloadidx",
32402		auxType:     auxSymOff,
32403		argLen:      3,
32404		commutative: true,
32405		symEffect:   SymRead,
32406		asm:         s390x.AMOVD,
32407		reg: regInfo{
32408			inputs: []inputInfo{
32409				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32410				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32411			},
32412			outputs: []outputInfo{
32413				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32414			},
32415		},
32416	},
32417	{
32418		name:        "MOVHBRloadidx",
32419		auxType:     auxSymOff,
32420		argLen:      3,
32421		commutative: true,
32422		symEffect:   SymRead,
32423		asm:         s390x.AMOVHBR,
32424		reg: regInfo{
32425			inputs: []inputInfo{
32426				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32427				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32428			},
32429			outputs: []outputInfo{
32430				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32431			},
32432		},
32433	},
32434	{
32435		name:        "MOVWBRloadidx",
32436		auxType:     auxSymOff,
32437		argLen:      3,
32438		commutative: true,
32439		symEffect:   SymRead,
32440		asm:         s390x.AMOVWBR,
32441		reg: regInfo{
32442			inputs: []inputInfo{
32443				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32444				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32445			},
32446			outputs: []outputInfo{
32447				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32448			},
32449		},
32450	},
32451	{
32452		name:        "MOVDBRloadidx",
32453		auxType:     auxSymOff,
32454		argLen:      3,
32455		commutative: true,
32456		symEffect:   SymRead,
32457		asm:         s390x.AMOVDBR,
32458		reg: regInfo{
32459			inputs: []inputInfo{
32460				{1, 56318},      // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32461				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32462			},
32463			outputs: []outputInfo{
32464				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32465			},
32466		},
32467	},
32468	{
32469		name:        "MOVBstoreidx",
32470		auxType:     auxSymOff,
32471		argLen:      4,
32472		commutative: true,
32473		symEffect:   SymWrite,
32474		asm:         s390x.AMOVB,
32475		reg: regInfo{
32476			inputs: []inputInfo{
32477				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32478				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32479				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32480			},
32481		},
32482	},
32483	{
32484		name:        "MOVHstoreidx",
32485		auxType:     auxSymOff,
32486		argLen:      4,
32487		commutative: true,
32488		symEffect:   SymWrite,
32489		asm:         s390x.AMOVH,
32490		reg: regInfo{
32491			inputs: []inputInfo{
32492				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32493				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32494				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32495			},
32496		},
32497	},
32498	{
32499		name:        "MOVWstoreidx",
32500		auxType:     auxSymOff,
32501		argLen:      4,
32502		commutative: true,
32503		symEffect:   SymWrite,
32504		asm:         s390x.AMOVW,
32505		reg: regInfo{
32506			inputs: []inputInfo{
32507				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32508				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32509				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32510			},
32511		},
32512	},
32513	{
32514		name:        "MOVDstoreidx",
32515		auxType:     auxSymOff,
32516		argLen:      4,
32517		commutative: true,
32518		symEffect:   SymWrite,
32519		asm:         s390x.AMOVD,
32520		reg: regInfo{
32521			inputs: []inputInfo{
32522				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32523				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32524				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32525			},
32526		},
32527	},
32528	{
32529		name:        "MOVHBRstoreidx",
32530		auxType:     auxSymOff,
32531		argLen:      4,
32532		commutative: true,
32533		symEffect:   SymWrite,
32534		asm:         s390x.AMOVHBR,
32535		reg: regInfo{
32536			inputs: []inputInfo{
32537				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32538				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32539				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32540			},
32541		},
32542	},
32543	{
32544		name:        "MOVWBRstoreidx",
32545		auxType:     auxSymOff,
32546		argLen:      4,
32547		commutative: true,
32548		symEffect:   SymWrite,
32549		asm:         s390x.AMOVWBR,
32550		reg: regInfo{
32551			inputs: []inputInfo{
32552				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32553				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32554				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32555			},
32556		},
32557	},
32558	{
32559		name:        "MOVDBRstoreidx",
32560		auxType:     auxSymOff,
32561		argLen:      4,
32562		commutative: true,
32563		symEffect:   SymWrite,
32564		asm:         s390x.AMOVDBR,
32565		reg: regInfo{
32566			inputs: []inputInfo{
32567				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32568				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32569				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32570			},
32571		},
32572	},
32573	{
32574		name:           "MOVBstoreconst",
32575		auxType:        auxSymValAndOff,
32576		argLen:         2,
32577		faultOnNilArg0: true,
32578		symEffect:      SymWrite,
32579		asm:            s390x.AMOVB,
32580		reg: regInfo{
32581			inputs: []inputInfo{
32582				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32583			},
32584		},
32585	},
32586	{
32587		name:           "MOVHstoreconst",
32588		auxType:        auxSymValAndOff,
32589		argLen:         2,
32590		faultOnNilArg0: true,
32591		symEffect:      SymWrite,
32592		asm:            s390x.AMOVH,
32593		reg: regInfo{
32594			inputs: []inputInfo{
32595				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32596			},
32597		},
32598	},
32599	{
32600		name:           "MOVWstoreconst",
32601		auxType:        auxSymValAndOff,
32602		argLen:         2,
32603		faultOnNilArg0: true,
32604		symEffect:      SymWrite,
32605		asm:            s390x.AMOVW,
32606		reg: regInfo{
32607			inputs: []inputInfo{
32608				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32609			},
32610		},
32611	},
32612	{
32613		name:           "MOVDstoreconst",
32614		auxType:        auxSymValAndOff,
32615		argLen:         2,
32616		faultOnNilArg0: true,
32617		symEffect:      SymWrite,
32618		asm:            s390x.AMOVD,
32619		reg: regInfo{
32620			inputs: []inputInfo{
32621				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32622			},
32623		},
32624	},
32625	{
32626		name:           "CLEAR",
32627		auxType:        auxSymValAndOff,
32628		argLen:         2,
32629		clobberFlags:   true,
32630		faultOnNilArg0: true,
32631		symEffect:      SymWrite,
32632		asm:            s390x.ACLEAR,
32633		reg: regInfo{
32634			inputs: []inputInfo{
32635				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32636			},
32637		},
32638	},
32639	{
32640		name:         "CALLstatic",
32641		auxType:      auxCallOff,
32642		argLen:       1,
32643		clobberFlags: true,
32644		call:         true,
32645		reg: regInfo{
32646			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32647		},
32648	},
32649	{
32650		name:         "CALLtail",
32651		auxType:      auxCallOff,
32652		argLen:       1,
32653		clobberFlags: true,
32654		call:         true,
32655		tailCall:     true,
32656		reg: regInfo{
32657			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32658		},
32659	},
32660	{
32661		name:         "CALLclosure",
32662		auxType:      auxCallOff,
32663		argLen:       3,
32664		clobberFlags: true,
32665		call:         true,
32666		reg: regInfo{
32667			inputs: []inputInfo{
32668				{1, 4096},  // R12
32669				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32670			},
32671			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32672		},
32673	},
32674	{
32675		name:         "CALLinter",
32676		auxType:      auxCallOff,
32677		argLen:       2,
32678		clobberFlags: true,
32679		call:         true,
32680		reg: regInfo{
32681			inputs: []inputInfo{
32682				{0, 23550}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32683			},
32684			clobbers: 4294933503, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 g R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32685		},
32686	},
32687	{
32688		name:   "InvertFlags",
32689		argLen: 1,
32690		reg:    regInfo{},
32691	},
32692	{
32693		name:   "LoweredGetG",
32694		argLen: 1,
32695		reg: regInfo{
32696			outputs: []outputInfo{
32697				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32698			},
32699		},
32700	},
32701	{
32702		name:      "LoweredGetClosurePtr",
32703		argLen:    0,
32704		zeroWidth: true,
32705		reg: regInfo{
32706			outputs: []outputInfo{
32707				{0, 4096}, // R12
32708			},
32709		},
32710	},
32711	{
32712		name:              "LoweredGetCallerSP",
32713		argLen:            0,
32714		rematerializeable: true,
32715		reg: regInfo{
32716			outputs: []outputInfo{
32717				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32718			},
32719		},
32720	},
32721	{
32722		name:              "LoweredGetCallerPC",
32723		argLen:            0,
32724		rematerializeable: true,
32725		reg: regInfo{
32726			outputs: []outputInfo{
32727				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32728			},
32729		},
32730	},
32731	{
32732		name:           "LoweredNilCheck",
32733		argLen:         2,
32734		clobberFlags:   true,
32735		nilCheck:       true,
32736		faultOnNilArg0: true,
32737		reg: regInfo{
32738			inputs: []inputInfo{
32739				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32740			},
32741		},
32742	},
32743	{
32744		name:         "LoweredRound32F",
32745		argLen:       1,
32746		resultInArg0: true,
32747		zeroWidth:    true,
32748		reg: regInfo{
32749			inputs: []inputInfo{
32750				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32751			},
32752			outputs: []outputInfo{
32753				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32754			},
32755		},
32756	},
32757	{
32758		name:         "LoweredRound64F",
32759		argLen:       1,
32760		resultInArg0: true,
32761		zeroWidth:    true,
32762		reg: regInfo{
32763			inputs: []inputInfo{
32764				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32765			},
32766			outputs: []outputInfo{
32767				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32768			},
32769		},
32770	},
32771	{
32772		name:         "LoweredWB",
32773		auxType:      auxSym,
32774		argLen:       3,
32775		clobberFlags: true,
32776		symEffect:    SymNone,
32777		reg: regInfo{
32778			inputs: []inputInfo{
32779				{0, 4}, // R2
32780				{1, 8}, // R3
32781			},
32782			clobbers: 4294918146, // R1 R14 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
32783		},
32784	},
32785	{
32786		name:    "LoweredPanicBoundsA",
32787		auxType: auxInt64,
32788		argLen:  3,
32789		call:    true,
32790		reg: regInfo{
32791			inputs: []inputInfo{
32792				{0, 4}, // R2
32793				{1, 8}, // R3
32794			},
32795		},
32796	},
32797	{
32798		name:    "LoweredPanicBoundsB",
32799		auxType: auxInt64,
32800		argLen:  3,
32801		call:    true,
32802		reg: regInfo{
32803			inputs: []inputInfo{
32804				{0, 2}, // R1
32805				{1, 4}, // R2
32806			},
32807		},
32808	},
32809	{
32810		name:    "LoweredPanicBoundsC",
32811		auxType: auxInt64,
32812		argLen:  3,
32813		call:    true,
32814		reg: regInfo{
32815			inputs: []inputInfo{
32816				{0, 1}, // R0
32817				{1, 2}, // R1
32818			},
32819		},
32820	},
32821	{
32822		name:   "FlagEQ",
32823		argLen: 0,
32824		reg:    regInfo{},
32825	},
32826	{
32827		name:   "FlagLT",
32828		argLen: 0,
32829		reg:    regInfo{},
32830	},
32831	{
32832		name:   "FlagGT",
32833		argLen: 0,
32834		reg:    regInfo{},
32835	},
32836	{
32837		name:   "FlagOV",
32838		argLen: 0,
32839		reg:    regInfo{},
32840	},
32841	{
32842		name:   "SYNC",
32843		argLen: 1,
32844		asm:    s390x.ASYNC,
32845		reg:    regInfo{},
32846	},
32847	{
32848		name:           "MOVBZatomicload",
32849		auxType:        auxSymOff,
32850		argLen:         2,
32851		faultOnNilArg0: true,
32852		symEffect:      SymRead,
32853		asm:            s390x.AMOVBZ,
32854		reg: regInfo{
32855			inputs: []inputInfo{
32856				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32857			},
32858			outputs: []outputInfo{
32859				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32860			},
32861		},
32862	},
32863	{
32864		name:           "MOVWZatomicload",
32865		auxType:        auxSymOff,
32866		argLen:         2,
32867		faultOnNilArg0: true,
32868		symEffect:      SymRead,
32869		asm:            s390x.AMOVWZ,
32870		reg: regInfo{
32871			inputs: []inputInfo{
32872				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32873			},
32874			outputs: []outputInfo{
32875				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32876			},
32877		},
32878	},
32879	{
32880		name:           "MOVDatomicload",
32881		auxType:        auxSymOff,
32882		argLen:         2,
32883		faultOnNilArg0: true,
32884		symEffect:      SymRead,
32885		asm:            s390x.AMOVD,
32886		reg: regInfo{
32887			inputs: []inputInfo{
32888				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32889			},
32890			outputs: []outputInfo{
32891				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32892			},
32893		},
32894	},
32895	{
32896		name:           "MOVBatomicstore",
32897		auxType:        auxSymOff,
32898		argLen:         3,
32899		clobberFlags:   true,
32900		faultOnNilArg0: true,
32901		hasSideEffects: true,
32902		symEffect:      SymWrite,
32903		asm:            s390x.AMOVB,
32904		reg: regInfo{
32905			inputs: []inputInfo{
32906				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32907				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32908			},
32909		},
32910	},
32911	{
32912		name:           "MOVWatomicstore",
32913		auxType:        auxSymOff,
32914		argLen:         3,
32915		clobberFlags:   true,
32916		faultOnNilArg0: true,
32917		hasSideEffects: true,
32918		symEffect:      SymWrite,
32919		asm:            s390x.AMOVW,
32920		reg: regInfo{
32921			inputs: []inputInfo{
32922				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32923				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32924			},
32925		},
32926	},
32927	{
32928		name:           "MOVDatomicstore",
32929		auxType:        auxSymOff,
32930		argLen:         3,
32931		clobberFlags:   true,
32932		faultOnNilArg0: true,
32933		hasSideEffects: true,
32934		symEffect:      SymWrite,
32935		asm:            s390x.AMOVD,
32936		reg: regInfo{
32937			inputs: []inputInfo{
32938				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32939				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32940			},
32941		},
32942	},
32943	{
32944		name:           "LAA",
32945		auxType:        auxSymOff,
32946		argLen:         3,
32947		clobberFlags:   true,
32948		faultOnNilArg0: true,
32949		hasSideEffects: true,
32950		symEffect:      SymRdWr,
32951		asm:            s390x.ALAA,
32952		reg: regInfo{
32953			inputs: []inputInfo{
32954				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32955				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32956			},
32957			outputs: []outputInfo{
32958				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32959			},
32960		},
32961	},
32962	{
32963		name:           "LAAG",
32964		auxType:        auxSymOff,
32965		argLen:         3,
32966		clobberFlags:   true,
32967		faultOnNilArg0: true,
32968		hasSideEffects: true,
32969		symEffect:      SymRdWr,
32970		asm:            s390x.ALAAG,
32971		reg: regInfo{
32972			inputs: []inputInfo{
32973				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
32974				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
32975			},
32976			outputs: []outputInfo{
32977				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
32978			},
32979		},
32980	},
32981	{
32982		name:   "AddTupleFirst32",
32983		argLen: 2,
32984		reg:    regInfo{},
32985	},
32986	{
32987		name:   "AddTupleFirst64",
32988		argLen: 2,
32989		reg:    regInfo{},
32990	},
32991	{
32992		name:           "LAN",
32993		argLen:         3,
32994		clobberFlags:   true,
32995		hasSideEffects: true,
32996		asm:            s390x.ALAN,
32997		reg: regInfo{
32998			inputs: []inputInfo{
32999				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
33000				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33001			},
33002		},
33003	},
33004	{
33005		name:           "LANfloor",
33006		argLen:         3,
33007		clobberFlags:   true,
33008		hasSideEffects: true,
33009		asm:            s390x.ALAN,
33010		reg: regInfo{
33011			inputs: []inputInfo{
33012				{0, 2},     // R1
33013				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33014			},
33015			clobbers: 2, // R1
33016		},
33017	},
33018	{
33019		name:           "LAO",
33020		argLen:         3,
33021		clobberFlags:   true,
33022		hasSideEffects: true,
33023		asm:            s390x.ALAO,
33024		reg: regInfo{
33025			inputs: []inputInfo{
33026				{0, 4295023614}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP SB
33027				{1, 56319},      // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33028			},
33029		},
33030	},
33031	{
33032		name:           "LAOfloor",
33033		argLen:         3,
33034		clobberFlags:   true,
33035		hasSideEffects: true,
33036		asm:            s390x.ALAO,
33037		reg: regInfo{
33038			inputs: []inputInfo{
33039				{0, 2},     // R1
33040				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33041			},
33042			clobbers: 2, // R1
33043		},
33044	},
33045	{
33046		name:           "LoweredAtomicCas32",
33047		auxType:        auxSymOff,
33048		argLen:         4,
33049		clobberFlags:   true,
33050		faultOnNilArg0: true,
33051		hasSideEffects: true,
33052		symEffect:      SymRdWr,
33053		asm:            s390x.ACS,
33054		reg: regInfo{
33055			inputs: []inputInfo{
33056				{1, 1},     // R0
33057				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33058				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33059			},
33060			clobbers: 1, // R0
33061			outputs: []outputInfo{
33062				{1, 0},
33063				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33064			},
33065		},
33066	},
33067	{
33068		name:           "LoweredAtomicCas64",
33069		auxType:        auxSymOff,
33070		argLen:         4,
33071		clobberFlags:   true,
33072		faultOnNilArg0: true,
33073		hasSideEffects: true,
33074		symEffect:      SymRdWr,
33075		asm:            s390x.ACSG,
33076		reg: regInfo{
33077			inputs: []inputInfo{
33078				{1, 1},     // R0
33079				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33080				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33081			},
33082			clobbers: 1, // R0
33083			outputs: []outputInfo{
33084				{1, 0},
33085				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33086			},
33087		},
33088	},
33089	{
33090		name:           "LoweredAtomicExchange32",
33091		auxType:        auxSymOff,
33092		argLen:         3,
33093		clobberFlags:   true,
33094		faultOnNilArg0: true,
33095		hasSideEffects: true,
33096		symEffect:      SymRdWr,
33097		asm:            s390x.ACS,
33098		reg: regInfo{
33099			inputs: []inputInfo{
33100				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33101				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33102			},
33103			outputs: []outputInfo{
33104				{1, 0},
33105				{0, 1}, // R0
33106			},
33107		},
33108	},
33109	{
33110		name:           "LoweredAtomicExchange64",
33111		auxType:        auxSymOff,
33112		argLen:         3,
33113		clobberFlags:   true,
33114		faultOnNilArg0: true,
33115		hasSideEffects: true,
33116		symEffect:      SymRdWr,
33117		asm:            s390x.ACSG,
33118		reg: regInfo{
33119			inputs: []inputInfo{
33120				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33121				{1, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33122			},
33123			outputs: []outputInfo{
33124				{1, 0},
33125				{0, 1}, // R0
33126			},
33127		},
33128	},
33129	{
33130		name:         "FLOGR",
33131		argLen:       1,
33132		clobberFlags: true,
33133		asm:          s390x.AFLOGR,
33134		reg: regInfo{
33135			inputs: []inputInfo{
33136				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33137			},
33138			clobbers: 2, // R1
33139			outputs: []outputInfo{
33140				{0, 1}, // R0
33141			},
33142		},
33143	},
33144	{
33145		name:         "POPCNT",
33146		argLen:       1,
33147		clobberFlags: true,
33148		asm:          s390x.APOPCNT,
33149		reg: regInfo{
33150			inputs: []inputInfo{
33151				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33152			},
33153			outputs: []outputInfo{
33154				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33155			},
33156		},
33157	},
33158	{
33159		name:   "MLGR",
33160		argLen: 2,
33161		asm:    s390x.AMLGR,
33162		reg: regInfo{
33163			inputs: []inputInfo{
33164				{1, 8},     // R3
33165				{0, 23551}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14
33166			},
33167			outputs: []outputInfo{
33168				{0, 4}, // R2
33169				{1, 8}, // R3
33170			},
33171		},
33172	},
33173	{
33174		name:   "SumBytes2",
33175		argLen: 1,
33176		reg:    regInfo{},
33177	},
33178	{
33179		name:   "SumBytes4",
33180		argLen: 1,
33181		reg:    regInfo{},
33182	},
33183	{
33184		name:   "SumBytes8",
33185		argLen: 1,
33186		reg:    regInfo{},
33187	},
33188	{
33189		name:           "STMG2",
33190		auxType:        auxSymOff,
33191		argLen:         4,
33192		clobberFlags:   true,
33193		faultOnNilArg0: true,
33194		symEffect:      SymWrite,
33195		asm:            s390x.ASTMG,
33196		reg: regInfo{
33197			inputs: []inputInfo{
33198				{1, 2},     // R1
33199				{2, 4},     // R2
33200				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33201			},
33202		},
33203	},
33204	{
33205		name:           "STMG3",
33206		auxType:        auxSymOff,
33207		argLen:         5,
33208		clobberFlags:   true,
33209		faultOnNilArg0: true,
33210		symEffect:      SymWrite,
33211		asm:            s390x.ASTMG,
33212		reg: regInfo{
33213			inputs: []inputInfo{
33214				{1, 2},     // R1
33215				{2, 4},     // R2
33216				{3, 8},     // R3
33217				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33218			},
33219		},
33220	},
33221	{
33222		name:           "STMG4",
33223		auxType:        auxSymOff,
33224		argLen:         6,
33225		clobberFlags:   true,
33226		faultOnNilArg0: true,
33227		symEffect:      SymWrite,
33228		asm:            s390x.ASTMG,
33229		reg: regInfo{
33230			inputs: []inputInfo{
33231				{1, 2},     // R1
33232				{2, 4},     // R2
33233				{3, 8},     // R3
33234				{4, 16},    // R4
33235				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33236			},
33237		},
33238	},
33239	{
33240		name:           "STM2",
33241		auxType:        auxSymOff,
33242		argLen:         4,
33243		clobberFlags:   true,
33244		faultOnNilArg0: true,
33245		symEffect:      SymWrite,
33246		asm:            s390x.ASTMY,
33247		reg: regInfo{
33248			inputs: []inputInfo{
33249				{1, 2},     // R1
33250				{2, 4},     // R2
33251				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33252			},
33253		},
33254	},
33255	{
33256		name:           "STM3",
33257		auxType:        auxSymOff,
33258		argLen:         5,
33259		clobberFlags:   true,
33260		faultOnNilArg0: true,
33261		symEffect:      SymWrite,
33262		asm:            s390x.ASTMY,
33263		reg: regInfo{
33264			inputs: []inputInfo{
33265				{1, 2},     // R1
33266				{2, 4},     // R2
33267				{3, 8},     // R3
33268				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33269			},
33270		},
33271	},
33272	{
33273		name:           "STM4",
33274		auxType:        auxSymOff,
33275		argLen:         6,
33276		clobberFlags:   true,
33277		faultOnNilArg0: true,
33278		symEffect:      SymWrite,
33279		asm:            s390x.ASTMY,
33280		reg: regInfo{
33281			inputs: []inputInfo{
33282				{1, 2},     // R1
33283				{2, 4},     // R2
33284				{3, 8},     // R3
33285				{4, 16},    // R4
33286				{0, 56318}, // R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33287			},
33288		},
33289	},
33290	{
33291		name:           "LoweredMove",
33292		auxType:        auxInt64,
33293		argLen:         4,
33294		clobberFlags:   true,
33295		faultOnNilArg0: true,
33296		faultOnNilArg1: true,
33297		reg: regInfo{
33298			inputs: []inputInfo{
33299				{0, 2},     // R1
33300				{1, 4},     // R2
33301				{2, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33302			},
33303			clobbers: 6, // R1 R2
33304		},
33305	},
33306	{
33307		name:           "LoweredZero",
33308		auxType:        auxInt64,
33309		argLen:         3,
33310		clobberFlags:   true,
33311		faultOnNilArg0: true,
33312		reg: regInfo{
33313			inputs: []inputInfo{
33314				{0, 2},     // R1
33315				{1, 56319}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R11 R12 R14 SP
33316			},
33317			clobbers: 2, // R1
33318		},
33319	},
33320
33321	{
33322		name:    "LoweredStaticCall",
33323		auxType: auxCallOff,
33324		argLen:  1,
33325		call:    true,
33326		reg: regInfo{
33327			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
33328		},
33329	},
33330	{
33331		name:     "LoweredTailCall",
33332		auxType:  auxCallOff,
33333		argLen:   1,
33334		call:     true,
33335		tailCall: true,
33336		reg: regInfo{
33337			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
33338		},
33339	},
33340	{
33341		name:    "LoweredClosureCall",
33342		auxType: auxCallOff,
33343		argLen:  3,
33344		call:    true,
33345		reg: regInfo{
33346			inputs: []inputInfo{
33347				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33348				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33349			},
33350			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
33351		},
33352	},
33353	{
33354		name:    "LoweredInterCall",
33355		auxType: auxCallOff,
33356		argLen:  2,
33357		call:    true,
33358		reg: regInfo{
33359			inputs: []inputInfo{
33360				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33361			},
33362			clobbers: 844424930131967, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31 g
33363		},
33364	},
33365	{
33366		name:              "LoweredAddr",
33367		auxType:           auxSymOff,
33368		argLen:            1,
33369		rematerializeable: true,
33370		symEffect:         SymAddr,
33371		reg: regInfo{
33372			inputs: []inputInfo{
33373				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33374			},
33375			outputs: []outputInfo{
33376				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33377			},
33378		},
33379	},
33380	{
33381		name:    "LoweredMove",
33382		auxType: auxInt64,
33383		argLen:  3,
33384		reg: regInfo{
33385			inputs: []inputInfo{
33386				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33387				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33388			},
33389		},
33390	},
33391	{
33392		name:    "LoweredZero",
33393		auxType: auxInt64,
33394		argLen:  2,
33395		reg: regInfo{
33396			inputs: []inputInfo{
33397				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33398			},
33399		},
33400	},
33401	{
33402		name:   "LoweredGetClosurePtr",
33403		argLen: 0,
33404		reg: regInfo{
33405			outputs: []outputInfo{
33406				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33407			},
33408		},
33409	},
33410	{
33411		name:              "LoweredGetCallerPC",
33412		argLen:            0,
33413		rematerializeable: true,
33414		reg: regInfo{
33415			outputs: []outputInfo{
33416				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33417			},
33418		},
33419	},
33420	{
33421		name:              "LoweredGetCallerSP",
33422		argLen:            0,
33423		rematerializeable: true,
33424		reg: regInfo{
33425			outputs: []outputInfo{
33426				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33427			},
33428		},
33429	},
33430	{
33431		name:           "LoweredNilCheck",
33432		argLen:         2,
33433		nilCheck:       true,
33434		faultOnNilArg0: true,
33435		reg: regInfo{
33436			inputs: []inputInfo{
33437				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33438			},
33439		},
33440	},
33441	{
33442		name:      "LoweredWB",
33443		auxType:   auxSym,
33444		argLen:    3,
33445		symEffect: SymNone,
33446		reg: regInfo{
33447			inputs: []inputInfo{
33448				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33449				{1, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33450			},
33451		},
33452	},
33453	{
33454		name:   "LoweredConvert",
33455		argLen: 2,
33456		reg: regInfo{
33457			inputs: []inputInfo{
33458				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33459			},
33460			outputs: []outputInfo{
33461				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33462			},
33463		},
33464	},
33465	{
33466		name:   "Select",
33467		argLen: 3,
33468		asm:    wasm.ASelect,
33469		reg: regInfo{
33470			inputs: []inputInfo{
33471				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33472				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33473				{2, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33474			},
33475			outputs: []outputInfo{
33476				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33477			},
33478		},
33479	},
33480	{
33481		name:    "I64Load8U",
33482		auxType: auxInt64,
33483		argLen:  2,
33484		asm:     wasm.AI64Load8U,
33485		reg: regInfo{
33486			inputs: []inputInfo{
33487				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33488			},
33489			outputs: []outputInfo{
33490				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33491			},
33492		},
33493	},
33494	{
33495		name:    "I64Load8S",
33496		auxType: auxInt64,
33497		argLen:  2,
33498		asm:     wasm.AI64Load8S,
33499		reg: regInfo{
33500			inputs: []inputInfo{
33501				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33502			},
33503			outputs: []outputInfo{
33504				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33505			},
33506		},
33507	},
33508	{
33509		name:    "I64Load16U",
33510		auxType: auxInt64,
33511		argLen:  2,
33512		asm:     wasm.AI64Load16U,
33513		reg: regInfo{
33514			inputs: []inputInfo{
33515				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33516			},
33517			outputs: []outputInfo{
33518				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33519			},
33520		},
33521	},
33522	{
33523		name:    "I64Load16S",
33524		auxType: auxInt64,
33525		argLen:  2,
33526		asm:     wasm.AI64Load16S,
33527		reg: regInfo{
33528			inputs: []inputInfo{
33529				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33530			},
33531			outputs: []outputInfo{
33532				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33533			},
33534		},
33535	},
33536	{
33537		name:    "I64Load32U",
33538		auxType: auxInt64,
33539		argLen:  2,
33540		asm:     wasm.AI64Load32U,
33541		reg: regInfo{
33542			inputs: []inputInfo{
33543				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33544			},
33545			outputs: []outputInfo{
33546				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33547			},
33548		},
33549	},
33550	{
33551		name:    "I64Load32S",
33552		auxType: auxInt64,
33553		argLen:  2,
33554		asm:     wasm.AI64Load32S,
33555		reg: regInfo{
33556			inputs: []inputInfo{
33557				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33558			},
33559			outputs: []outputInfo{
33560				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33561			},
33562		},
33563	},
33564	{
33565		name:    "I64Load",
33566		auxType: auxInt64,
33567		argLen:  2,
33568		asm:     wasm.AI64Load,
33569		reg: regInfo{
33570			inputs: []inputInfo{
33571				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33572			},
33573			outputs: []outputInfo{
33574				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33575			},
33576		},
33577	},
33578	{
33579		name:    "I64Store8",
33580		auxType: auxInt64,
33581		argLen:  3,
33582		asm:     wasm.AI64Store8,
33583		reg: regInfo{
33584			inputs: []inputInfo{
33585				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33586				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33587			},
33588		},
33589	},
33590	{
33591		name:    "I64Store16",
33592		auxType: auxInt64,
33593		argLen:  3,
33594		asm:     wasm.AI64Store16,
33595		reg: regInfo{
33596			inputs: []inputInfo{
33597				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33598				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33599			},
33600		},
33601	},
33602	{
33603		name:    "I64Store32",
33604		auxType: auxInt64,
33605		argLen:  3,
33606		asm:     wasm.AI64Store32,
33607		reg: regInfo{
33608			inputs: []inputInfo{
33609				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33610				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33611			},
33612		},
33613	},
33614	{
33615		name:    "I64Store",
33616		auxType: auxInt64,
33617		argLen:  3,
33618		asm:     wasm.AI64Store,
33619		reg: regInfo{
33620			inputs: []inputInfo{
33621				{1, 281474976776191},  // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33622				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33623			},
33624		},
33625	},
33626	{
33627		name:    "F32Load",
33628		auxType: auxInt64,
33629		argLen:  2,
33630		asm:     wasm.AF32Load,
33631		reg: regInfo{
33632			inputs: []inputInfo{
33633				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33634			},
33635			outputs: []outputInfo{
33636				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33637			},
33638		},
33639	},
33640	{
33641		name:    "F64Load",
33642		auxType: auxInt64,
33643		argLen:  2,
33644		asm:     wasm.AF64Load,
33645		reg: regInfo{
33646			inputs: []inputInfo{
33647				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33648			},
33649			outputs: []outputInfo{
33650				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33651			},
33652		},
33653	},
33654	{
33655		name:    "F32Store",
33656		auxType: auxInt64,
33657		argLen:  3,
33658		asm:     wasm.AF32Store,
33659		reg: regInfo{
33660			inputs: []inputInfo{
33661				{1, 4294901760},       // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33662				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33663			},
33664		},
33665	},
33666	{
33667		name:    "F64Store",
33668		auxType: auxInt64,
33669		argLen:  3,
33670		asm:     wasm.AF64Store,
33671		reg: regInfo{
33672			inputs: []inputInfo{
33673				{1, 281470681743360},  // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33674				{0, 1407374883618815}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP SB
33675			},
33676		},
33677	},
33678	{
33679		name:              "I64Const",
33680		auxType:           auxInt64,
33681		argLen:            0,
33682		rematerializeable: true,
33683		reg: regInfo{
33684			outputs: []outputInfo{
33685				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33686			},
33687		},
33688	},
33689	{
33690		name:              "F32Const",
33691		auxType:           auxFloat32,
33692		argLen:            0,
33693		rematerializeable: true,
33694		reg: regInfo{
33695			outputs: []outputInfo{
33696				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33697			},
33698		},
33699	},
33700	{
33701		name:              "F64Const",
33702		auxType:           auxFloat64,
33703		argLen:            0,
33704		rematerializeable: true,
33705		reg: regInfo{
33706			outputs: []outputInfo{
33707				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33708			},
33709		},
33710	},
33711	{
33712		name:   "I64Eqz",
33713		argLen: 1,
33714		asm:    wasm.AI64Eqz,
33715		reg: regInfo{
33716			inputs: []inputInfo{
33717				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33718			},
33719			outputs: []outputInfo{
33720				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33721			},
33722		},
33723	},
33724	{
33725		name:   "I64Eq",
33726		argLen: 2,
33727		asm:    wasm.AI64Eq,
33728		reg: regInfo{
33729			inputs: []inputInfo{
33730				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33731				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33732			},
33733			outputs: []outputInfo{
33734				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33735			},
33736		},
33737	},
33738	{
33739		name:   "I64Ne",
33740		argLen: 2,
33741		asm:    wasm.AI64Ne,
33742		reg: regInfo{
33743			inputs: []inputInfo{
33744				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33745				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33746			},
33747			outputs: []outputInfo{
33748				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33749			},
33750		},
33751	},
33752	{
33753		name:   "I64LtS",
33754		argLen: 2,
33755		asm:    wasm.AI64LtS,
33756		reg: regInfo{
33757			inputs: []inputInfo{
33758				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33759				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33760			},
33761			outputs: []outputInfo{
33762				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33763			},
33764		},
33765	},
33766	{
33767		name:   "I64LtU",
33768		argLen: 2,
33769		asm:    wasm.AI64LtU,
33770		reg: regInfo{
33771			inputs: []inputInfo{
33772				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33773				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33774			},
33775			outputs: []outputInfo{
33776				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33777			},
33778		},
33779	},
33780	{
33781		name:   "I64GtS",
33782		argLen: 2,
33783		asm:    wasm.AI64GtS,
33784		reg: regInfo{
33785			inputs: []inputInfo{
33786				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33787				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33788			},
33789			outputs: []outputInfo{
33790				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33791			},
33792		},
33793	},
33794	{
33795		name:   "I64GtU",
33796		argLen: 2,
33797		asm:    wasm.AI64GtU,
33798		reg: regInfo{
33799			inputs: []inputInfo{
33800				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33801				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33802			},
33803			outputs: []outputInfo{
33804				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33805			},
33806		},
33807	},
33808	{
33809		name:   "I64LeS",
33810		argLen: 2,
33811		asm:    wasm.AI64LeS,
33812		reg: regInfo{
33813			inputs: []inputInfo{
33814				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33815				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33816			},
33817			outputs: []outputInfo{
33818				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33819			},
33820		},
33821	},
33822	{
33823		name:   "I64LeU",
33824		argLen: 2,
33825		asm:    wasm.AI64LeU,
33826		reg: regInfo{
33827			inputs: []inputInfo{
33828				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33829				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33830			},
33831			outputs: []outputInfo{
33832				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33833			},
33834		},
33835	},
33836	{
33837		name:   "I64GeS",
33838		argLen: 2,
33839		asm:    wasm.AI64GeS,
33840		reg: regInfo{
33841			inputs: []inputInfo{
33842				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33843				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33844			},
33845			outputs: []outputInfo{
33846				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33847			},
33848		},
33849	},
33850	{
33851		name:   "I64GeU",
33852		argLen: 2,
33853		asm:    wasm.AI64GeU,
33854		reg: regInfo{
33855			inputs: []inputInfo{
33856				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33857				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
33858			},
33859			outputs: []outputInfo{
33860				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33861			},
33862		},
33863	},
33864	{
33865		name:   "F32Eq",
33866		argLen: 2,
33867		asm:    wasm.AF32Eq,
33868		reg: regInfo{
33869			inputs: []inputInfo{
33870				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33871				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33872			},
33873			outputs: []outputInfo{
33874				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33875			},
33876		},
33877	},
33878	{
33879		name:   "F32Ne",
33880		argLen: 2,
33881		asm:    wasm.AF32Ne,
33882		reg: regInfo{
33883			inputs: []inputInfo{
33884				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33885				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33886			},
33887			outputs: []outputInfo{
33888				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33889			},
33890		},
33891	},
33892	{
33893		name:   "F32Lt",
33894		argLen: 2,
33895		asm:    wasm.AF32Lt,
33896		reg: regInfo{
33897			inputs: []inputInfo{
33898				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33899				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33900			},
33901			outputs: []outputInfo{
33902				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33903			},
33904		},
33905	},
33906	{
33907		name:   "F32Gt",
33908		argLen: 2,
33909		asm:    wasm.AF32Gt,
33910		reg: regInfo{
33911			inputs: []inputInfo{
33912				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33913				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33914			},
33915			outputs: []outputInfo{
33916				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33917			},
33918		},
33919	},
33920	{
33921		name:   "F32Le",
33922		argLen: 2,
33923		asm:    wasm.AF32Le,
33924		reg: regInfo{
33925			inputs: []inputInfo{
33926				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33927				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33928			},
33929			outputs: []outputInfo{
33930				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33931			},
33932		},
33933	},
33934	{
33935		name:   "F32Ge",
33936		argLen: 2,
33937		asm:    wasm.AF32Ge,
33938		reg: regInfo{
33939			inputs: []inputInfo{
33940				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33941				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
33942			},
33943			outputs: []outputInfo{
33944				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33945			},
33946		},
33947	},
33948	{
33949		name:   "F64Eq",
33950		argLen: 2,
33951		asm:    wasm.AF64Eq,
33952		reg: regInfo{
33953			inputs: []inputInfo{
33954				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33955				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33956			},
33957			outputs: []outputInfo{
33958				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33959			},
33960		},
33961	},
33962	{
33963		name:   "F64Ne",
33964		argLen: 2,
33965		asm:    wasm.AF64Ne,
33966		reg: regInfo{
33967			inputs: []inputInfo{
33968				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33969				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33970			},
33971			outputs: []outputInfo{
33972				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33973			},
33974		},
33975	},
33976	{
33977		name:   "F64Lt",
33978		argLen: 2,
33979		asm:    wasm.AF64Lt,
33980		reg: regInfo{
33981			inputs: []inputInfo{
33982				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33983				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33984			},
33985			outputs: []outputInfo{
33986				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
33987			},
33988		},
33989	},
33990	{
33991		name:   "F64Gt",
33992		argLen: 2,
33993		asm:    wasm.AF64Gt,
33994		reg: regInfo{
33995			inputs: []inputInfo{
33996				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33997				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
33998			},
33999			outputs: []outputInfo{
34000				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34001			},
34002		},
34003	},
34004	{
34005		name:   "F64Le",
34006		argLen: 2,
34007		asm:    wasm.AF64Le,
34008		reg: regInfo{
34009			inputs: []inputInfo{
34010				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34011				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34012			},
34013			outputs: []outputInfo{
34014				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34015			},
34016		},
34017	},
34018	{
34019		name:   "F64Ge",
34020		argLen: 2,
34021		asm:    wasm.AF64Ge,
34022		reg: regInfo{
34023			inputs: []inputInfo{
34024				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34025				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34026			},
34027			outputs: []outputInfo{
34028				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34029			},
34030		},
34031	},
34032	{
34033		name:   "I64Add",
34034		argLen: 2,
34035		asm:    wasm.AI64Add,
34036		reg: regInfo{
34037			inputs: []inputInfo{
34038				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34039				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34040			},
34041			outputs: []outputInfo{
34042				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34043			},
34044		},
34045	},
34046	{
34047		name:    "I64AddConst",
34048		auxType: auxInt64,
34049		argLen:  1,
34050		asm:     wasm.AI64Add,
34051		reg: regInfo{
34052			inputs: []inputInfo{
34053				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34054			},
34055			outputs: []outputInfo{
34056				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34057			},
34058		},
34059	},
34060	{
34061		name:   "I64Sub",
34062		argLen: 2,
34063		asm:    wasm.AI64Sub,
34064		reg: regInfo{
34065			inputs: []inputInfo{
34066				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34067				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34068			},
34069			outputs: []outputInfo{
34070				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34071			},
34072		},
34073	},
34074	{
34075		name:   "I64Mul",
34076		argLen: 2,
34077		asm:    wasm.AI64Mul,
34078		reg: regInfo{
34079			inputs: []inputInfo{
34080				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34081				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34082			},
34083			outputs: []outputInfo{
34084				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34085			},
34086		},
34087	},
34088	{
34089		name:   "I64DivS",
34090		argLen: 2,
34091		asm:    wasm.AI64DivS,
34092		reg: regInfo{
34093			inputs: []inputInfo{
34094				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34095				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34096			},
34097			outputs: []outputInfo{
34098				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34099			},
34100		},
34101	},
34102	{
34103		name:   "I64DivU",
34104		argLen: 2,
34105		asm:    wasm.AI64DivU,
34106		reg: regInfo{
34107			inputs: []inputInfo{
34108				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34109				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34110			},
34111			outputs: []outputInfo{
34112				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34113			},
34114		},
34115	},
34116	{
34117		name:   "I64RemS",
34118		argLen: 2,
34119		asm:    wasm.AI64RemS,
34120		reg: regInfo{
34121			inputs: []inputInfo{
34122				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34123				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34124			},
34125			outputs: []outputInfo{
34126				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34127			},
34128		},
34129	},
34130	{
34131		name:   "I64RemU",
34132		argLen: 2,
34133		asm:    wasm.AI64RemU,
34134		reg: regInfo{
34135			inputs: []inputInfo{
34136				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34137				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34138			},
34139			outputs: []outputInfo{
34140				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34141			},
34142		},
34143	},
34144	{
34145		name:   "I64And",
34146		argLen: 2,
34147		asm:    wasm.AI64And,
34148		reg: regInfo{
34149			inputs: []inputInfo{
34150				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34151				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34152			},
34153			outputs: []outputInfo{
34154				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34155			},
34156		},
34157	},
34158	{
34159		name:   "I64Or",
34160		argLen: 2,
34161		asm:    wasm.AI64Or,
34162		reg: regInfo{
34163			inputs: []inputInfo{
34164				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34165				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34166			},
34167			outputs: []outputInfo{
34168				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34169			},
34170		},
34171	},
34172	{
34173		name:   "I64Xor",
34174		argLen: 2,
34175		asm:    wasm.AI64Xor,
34176		reg: regInfo{
34177			inputs: []inputInfo{
34178				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34179				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34180			},
34181			outputs: []outputInfo{
34182				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34183			},
34184		},
34185	},
34186	{
34187		name:   "I64Shl",
34188		argLen: 2,
34189		asm:    wasm.AI64Shl,
34190		reg: regInfo{
34191			inputs: []inputInfo{
34192				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34193				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34194			},
34195			outputs: []outputInfo{
34196				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34197			},
34198		},
34199	},
34200	{
34201		name:   "I64ShrS",
34202		argLen: 2,
34203		asm:    wasm.AI64ShrS,
34204		reg: regInfo{
34205			inputs: []inputInfo{
34206				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34207				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34208			},
34209			outputs: []outputInfo{
34210				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34211			},
34212		},
34213	},
34214	{
34215		name:   "I64ShrU",
34216		argLen: 2,
34217		asm:    wasm.AI64ShrU,
34218		reg: regInfo{
34219			inputs: []inputInfo{
34220				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34221				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34222			},
34223			outputs: []outputInfo{
34224				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34225			},
34226		},
34227	},
34228	{
34229		name:   "F32Neg",
34230		argLen: 1,
34231		asm:    wasm.AF32Neg,
34232		reg: regInfo{
34233			inputs: []inputInfo{
34234				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34235			},
34236			outputs: []outputInfo{
34237				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34238			},
34239		},
34240	},
34241	{
34242		name:   "F32Add",
34243		argLen: 2,
34244		asm:    wasm.AF32Add,
34245		reg: regInfo{
34246			inputs: []inputInfo{
34247				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34248				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34249			},
34250			outputs: []outputInfo{
34251				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34252			},
34253		},
34254	},
34255	{
34256		name:   "F32Sub",
34257		argLen: 2,
34258		asm:    wasm.AF32Sub,
34259		reg: regInfo{
34260			inputs: []inputInfo{
34261				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34262				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34263			},
34264			outputs: []outputInfo{
34265				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34266			},
34267		},
34268	},
34269	{
34270		name:   "F32Mul",
34271		argLen: 2,
34272		asm:    wasm.AF32Mul,
34273		reg: regInfo{
34274			inputs: []inputInfo{
34275				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34276				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34277			},
34278			outputs: []outputInfo{
34279				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34280			},
34281		},
34282	},
34283	{
34284		name:   "F32Div",
34285		argLen: 2,
34286		asm:    wasm.AF32Div,
34287		reg: regInfo{
34288			inputs: []inputInfo{
34289				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34290				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34291			},
34292			outputs: []outputInfo{
34293				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34294			},
34295		},
34296	},
34297	{
34298		name:   "F64Neg",
34299		argLen: 1,
34300		asm:    wasm.AF64Neg,
34301		reg: regInfo{
34302			inputs: []inputInfo{
34303				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34304			},
34305			outputs: []outputInfo{
34306				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34307			},
34308		},
34309	},
34310	{
34311		name:   "F64Add",
34312		argLen: 2,
34313		asm:    wasm.AF64Add,
34314		reg: regInfo{
34315			inputs: []inputInfo{
34316				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34317				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34318			},
34319			outputs: []outputInfo{
34320				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34321			},
34322		},
34323	},
34324	{
34325		name:   "F64Sub",
34326		argLen: 2,
34327		asm:    wasm.AF64Sub,
34328		reg: regInfo{
34329			inputs: []inputInfo{
34330				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34331				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34332			},
34333			outputs: []outputInfo{
34334				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34335			},
34336		},
34337	},
34338	{
34339		name:   "F64Mul",
34340		argLen: 2,
34341		asm:    wasm.AF64Mul,
34342		reg: regInfo{
34343			inputs: []inputInfo{
34344				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34345				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34346			},
34347			outputs: []outputInfo{
34348				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34349			},
34350		},
34351	},
34352	{
34353		name:   "F64Div",
34354		argLen: 2,
34355		asm:    wasm.AF64Div,
34356		reg: regInfo{
34357			inputs: []inputInfo{
34358				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34359				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34360			},
34361			outputs: []outputInfo{
34362				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34363			},
34364		},
34365	},
34366	{
34367		name:   "I64TruncSatF64S",
34368		argLen: 1,
34369		asm:    wasm.AI64TruncSatF64S,
34370		reg: regInfo{
34371			inputs: []inputInfo{
34372				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34373			},
34374			outputs: []outputInfo{
34375				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34376			},
34377		},
34378	},
34379	{
34380		name:   "I64TruncSatF64U",
34381		argLen: 1,
34382		asm:    wasm.AI64TruncSatF64U,
34383		reg: regInfo{
34384			inputs: []inputInfo{
34385				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34386			},
34387			outputs: []outputInfo{
34388				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34389			},
34390		},
34391	},
34392	{
34393		name:   "I64TruncSatF32S",
34394		argLen: 1,
34395		asm:    wasm.AI64TruncSatF32S,
34396		reg: regInfo{
34397			inputs: []inputInfo{
34398				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34399			},
34400			outputs: []outputInfo{
34401				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34402			},
34403		},
34404	},
34405	{
34406		name:   "I64TruncSatF32U",
34407		argLen: 1,
34408		asm:    wasm.AI64TruncSatF32U,
34409		reg: regInfo{
34410			inputs: []inputInfo{
34411				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34412			},
34413			outputs: []outputInfo{
34414				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34415			},
34416		},
34417	},
34418	{
34419		name:   "F32ConvertI64S",
34420		argLen: 1,
34421		asm:    wasm.AF32ConvertI64S,
34422		reg: regInfo{
34423			inputs: []inputInfo{
34424				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34425			},
34426			outputs: []outputInfo{
34427				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34428			},
34429		},
34430	},
34431	{
34432		name:   "F32ConvertI64U",
34433		argLen: 1,
34434		asm:    wasm.AF32ConvertI64U,
34435		reg: regInfo{
34436			inputs: []inputInfo{
34437				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34438			},
34439			outputs: []outputInfo{
34440				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34441			},
34442		},
34443	},
34444	{
34445		name:   "F64ConvertI64S",
34446		argLen: 1,
34447		asm:    wasm.AF64ConvertI64S,
34448		reg: regInfo{
34449			inputs: []inputInfo{
34450				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34451			},
34452			outputs: []outputInfo{
34453				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34454			},
34455		},
34456	},
34457	{
34458		name:   "F64ConvertI64U",
34459		argLen: 1,
34460		asm:    wasm.AF64ConvertI64U,
34461		reg: regInfo{
34462			inputs: []inputInfo{
34463				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34464			},
34465			outputs: []outputInfo{
34466				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34467			},
34468		},
34469	},
34470	{
34471		name:   "F32DemoteF64",
34472		argLen: 1,
34473		asm:    wasm.AF32DemoteF64,
34474		reg: regInfo{
34475			inputs: []inputInfo{
34476				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34477			},
34478			outputs: []outputInfo{
34479				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34480			},
34481		},
34482	},
34483	{
34484		name:   "F64PromoteF32",
34485		argLen: 1,
34486		asm:    wasm.AF64PromoteF32,
34487		reg: regInfo{
34488			inputs: []inputInfo{
34489				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34490			},
34491			outputs: []outputInfo{
34492				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34493			},
34494		},
34495	},
34496	{
34497		name:   "I64Extend8S",
34498		argLen: 1,
34499		asm:    wasm.AI64Extend8S,
34500		reg: regInfo{
34501			inputs: []inputInfo{
34502				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34503			},
34504			outputs: []outputInfo{
34505				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34506			},
34507		},
34508	},
34509	{
34510		name:   "I64Extend16S",
34511		argLen: 1,
34512		asm:    wasm.AI64Extend16S,
34513		reg: regInfo{
34514			inputs: []inputInfo{
34515				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34516			},
34517			outputs: []outputInfo{
34518				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34519			},
34520		},
34521	},
34522	{
34523		name:   "I64Extend32S",
34524		argLen: 1,
34525		asm:    wasm.AI64Extend32S,
34526		reg: regInfo{
34527			inputs: []inputInfo{
34528				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34529			},
34530			outputs: []outputInfo{
34531				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34532			},
34533		},
34534	},
34535	{
34536		name:   "F32Sqrt",
34537		argLen: 1,
34538		asm:    wasm.AF32Sqrt,
34539		reg: regInfo{
34540			inputs: []inputInfo{
34541				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34542			},
34543			outputs: []outputInfo{
34544				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34545			},
34546		},
34547	},
34548	{
34549		name:   "F32Trunc",
34550		argLen: 1,
34551		asm:    wasm.AF32Trunc,
34552		reg: regInfo{
34553			inputs: []inputInfo{
34554				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34555			},
34556			outputs: []outputInfo{
34557				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34558			},
34559		},
34560	},
34561	{
34562		name:   "F32Ceil",
34563		argLen: 1,
34564		asm:    wasm.AF32Ceil,
34565		reg: regInfo{
34566			inputs: []inputInfo{
34567				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34568			},
34569			outputs: []outputInfo{
34570				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34571			},
34572		},
34573	},
34574	{
34575		name:   "F32Floor",
34576		argLen: 1,
34577		asm:    wasm.AF32Floor,
34578		reg: regInfo{
34579			inputs: []inputInfo{
34580				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34581			},
34582			outputs: []outputInfo{
34583				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34584			},
34585		},
34586	},
34587	{
34588		name:   "F32Nearest",
34589		argLen: 1,
34590		asm:    wasm.AF32Nearest,
34591		reg: regInfo{
34592			inputs: []inputInfo{
34593				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34594			},
34595			outputs: []outputInfo{
34596				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34597			},
34598		},
34599	},
34600	{
34601		name:   "F32Abs",
34602		argLen: 1,
34603		asm:    wasm.AF32Abs,
34604		reg: regInfo{
34605			inputs: []inputInfo{
34606				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34607			},
34608			outputs: []outputInfo{
34609				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34610			},
34611		},
34612	},
34613	{
34614		name:   "F32Copysign",
34615		argLen: 2,
34616		asm:    wasm.AF32Copysign,
34617		reg: regInfo{
34618			inputs: []inputInfo{
34619				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34620				{1, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34621			},
34622			outputs: []outputInfo{
34623				{0, 4294901760}, // F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15
34624			},
34625		},
34626	},
34627	{
34628		name:   "F64Sqrt",
34629		argLen: 1,
34630		asm:    wasm.AF64Sqrt,
34631		reg: regInfo{
34632			inputs: []inputInfo{
34633				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34634			},
34635			outputs: []outputInfo{
34636				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34637			},
34638		},
34639	},
34640	{
34641		name:   "F64Trunc",
34642		argLen: 1,
34643		asm:    wasm.AF64Trunc,
34644		reg: regInfo{
34645			inputs: []inputInfo{
34646				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34647			},
34648			outputs: []outputInfo{
34649				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34650			},
34651		},
34652	},
34653	{
34654		name:   "F64Ceil",
34655		argLen: 1,
34656		asm:    wasm.AF64Ceil,
34657		reg: regInfo{
34658			inputs: []inputInfo{
34659				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34660			},
34661			outputs: []outputInfo{
34662				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34663			},
34664		},
34665	},
34666	{
34667		name:   "F64Floor",
34668		argLen: 1,
34669		asm:    wasm.AF64Floor,
34670		reg: regInfo{
34671			inputs: []inputInfo{
34672				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34673			},
34674			outputs: []outputInfo{
34675				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34676			},
34677		},
34678	},
34679	{
34680		name:   "F64Nearest",
34681		argLen: 1,
34682		asm:    wasm.AF64Nearest,
34683		reg: regInfo{
34684			inputs: []inputInfo{
34685				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34686			},
34687			outputs: []outputInfo{
34688				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34689			},
34690		},
34691	},
34692	{
34693		name:   "F64Abs",
34694		argLen: 1,
34695		asm:    wasm.AF64Abs,
34696		reg: regInfo{
34697			inputs: []inputInfo{
34698				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34699			},
34700			outputs: []outputInfo{
34701				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34702			},
34703		},
34704	},
34705	{
34706		name:   "F64Copysign",
34707		argLen: 2,
34708		asm:    wasm.AF64Copysign,
34709		reg: regInfo{
34710			inputs: []inputInfo{
34711				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34712				{1, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34713			},
34714			outputs: []outputInfo{
34715				{0, 281470681743360}, // F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30 F31
34716			},
34717		},
34718	},
34719	{
34720		name:   "I64Ctz",
34721		argLen: 1,
34722		asm:    wasm.AI64Ctz,
34723		reg: regInfo{
34724			inputs: []inputInfo{
34725				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34726			},
34727			outputs: []outputInfo{
34728				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34729			},
34730		},
34731	},
34732	{
34733		name:   "I64Clz",
34734		argLen: 1,
34735		asm:    wasm.AI64Clz,
34736		reg: regInfo{
34737			inputs: []inputInfo{
34738				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34739			},
34740			outputs: []outputInfo{
34741				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34742			},
34743		},
34744	},
34745	{
34746		name:   "I32Rotl",
34747		argLen: 2,
34748		asm:    wasm.AI32Rotl,
34749		reg: regInfo{
34750			inputs: []inputInfo{
34751				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34752				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34753			},
34754			outputs: []outputInfo{
34755				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34756			},
34757		},
34758	},
34759	{
34760		name:   "I64Rotl",
34761		argLen: 2,
34762		asm:    wasm.AI64Rotl,
34763		reg: regInfo{
34764			inputs: []inputInfo{
34765				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34766				{1, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34767			},
34768			outputs: []outputInfo{
34769				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34770			},
34771		},
34772	},
34773	{
34774		name:   "I64Popcnt",
34775		argLen: 1,
34776		asm:    wasm.AI64Popcnt,
34777		reg: regInfo{
34778			inputs: []inputInfo{
34779				{0, 281474976776191}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 SP
34780			},
34781			outputs: []outputInfo{
34782				{0, 65535}, // R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15
34783			},
34784		},
34785	},
34786
34787	{
34788		name:        "Add8",
34789		argLen:      2,
34790		commutative: true,
34791		generic:     true,
34792	},
34793	{
34794		name:        "Add16",
34795		argLen:      2,
34796		commutative: true,
34797		generic:     true,
34798	},
34799	{
34800		name:        "Add32",
34801		argLen:      2,
34802		commutative: true,
34803		generic:     true,
34804	},
34805	{
34806		name:        "Add64",
34807		argLen:      2,
34808		commutative: true,
34809		generic:     true,
34810	},
34811	{
34812		name:    "AddPtr",
34813		argLen:  2,
34814		generic: true,
34815	},
34816	{
34817		name:        "Add32F",
34818		argLen:      2,
34819		commutative: true,
34820		generic:     true,
34821	},
34822	{
34823		name:        "Add64F",
34824		argLen:      2,
34825		commutative: true,
34826		generic:     true,
34827	},
34828	{
34829		name:    "Sub8",
34830		argLen:  2,
34831		generic: true,
34832	},
34833	{
34834		name:    "Sub16",
34835		argLen:  2,
34836		generic: true,
34837	},
34838	{
34839		name:    "Sub32",
34840		argLen:  2,
34841		generic: true,
34842	},
34843	{
34844		name:    "Sub64",
34845		argLen:  2,
34846		generic: true,
34847	},
34848	{
34849		name:    "SubPtr",
34850		argLen:  2,
34851		generic: true,
34852	},
34853	{
34854		name:    "Sub32F",
34855		argLen:  2,
34856		generic: true,
34857	},
34858	{
34859		name:    "Sub64F",
34860		argLen:  2,
34861		generic: true,
34862	},
34863	{
34864		name:        "Mul8",
34865		argLen:      2,
34866		commutative: true,
34867		generic:     true,
34868	},
34869	{
34870		name:        "Mul16",
34871		argLen:      2,
34872		commutative: true,
34873		generic:     true,
34874	},
34875	{
34876		name:        "Mul32",
34877		argLen:      2,
34878		commutative: true,
34879		generic:     true,
34880	},
34881	{
34882		name:        "Mul64",
34883		argLen:      2,
34884		commutative: true,
34885		generic:     true,
34886	},
34887	{
34888		name:        "Mul32F",
34889		argLen:      2,
34890		commutative: true,
34891		generic:     true,
34892	},
34893	{
34894		name:        "Mul64F",
34895		argLen:      2,
34896		commutative: true,
34897		generic:     true,
34898	},
34899	{
34900		name:    "Div32F",
34901		argLen:  2,
34902		generic: true,
34903	},
34904	{
34905		name:    "Div64F",
34906		argLen:  2,
34907		generic: true,
34908	},
34909	{
34910		name:        "Hmul32",
34911		argLen:      2,
34912		commutative: true,
34913		generic:     true,
34914	},
34915	{
34916		name:        "Hmul32u",
34917		argLen:      2,
34918		commutative: true,
34919		generic:     true,
34920	},
34921	{
34922		name:        "Hmul64",
34923		argLen:      2,
34924		commutative: true,
34925		generic:     true,
34926	},
34927	{
34928		name:        "Hmul64u",
34929		argLen:      2,
34930		commutative: true,
34931		generic:     true,
34932	},
34933	{
34934		name:        "Mul32uhilo",
34935		argLen:      2,
34936		commutative: true,
34937		generic:     true,
34938	},
34939	{
34940		name:        "Mul64uhilo",
34941		argLen:      2,
34942		commutative: true,
34943		generic:     true,
34944	},
34945	{
34946		name:        "Mul32uover",
34947		argLen:      2,
34948		commutative: true,
34949		generic:     true,
34950	},
34951	{
34952		name:        "Mul64uover",
34953		argLen:      2,
34954		commutative: true,
34955		generic:     true,
34956	},
34957	{
34958		name:    "Avg32u",
34959		argLen:  2,
34960		generic: true,
34961	},
34962	{
34963		name:    "Avg64u",
34964		argLen:  2,
34965		generic: true,
34966	},
34967	{
34968		name:    "Div8",
34969		argLen:  2,
34970		generic: true,
34971	},
34972	{
34973		name:    "Div8u",
34974		argLen:  2,
34975		generic: true,
34976	},
34977	{
34978		name:    "Div16",
34979		auxType: auxBool,
34980		argLen:  2,
34981		generic: true,
34982	},
34983	{
34984		name:    "Div16u",
34985		argLen:  2,
34986		generic: true,
34987	},
34988	{
34989		name:    "Div32",
34990		auxType: auxBool,
34991		argLen:  2,
34992		generic: true,
34993	},
34994	{
34995		name:    "Div32u",
34996		argLen:  2,
34997		generic: true,
34998	},
34999	{
35000		name:    "Div64",
35001		auxType: auxBool,
35002		argLen:  2,
35003		generic: true,
35004	},
35005	{
35006		name:    "Div64u",
35007		argLen:  2,
35008		generic: true,
35009	},
35010	{
35011		name:    "Div128u",
35012		argLen:  3,
35013		generic: true,
35014	},
35015	{
35016		name:    "Mod8",
35017		argLen:  2,
35018		generic: true,
35019	},
35020	{
35021		name:    "Mod8u",
35022		argLen:  2,
35023		generic: true,
35024	},
35025	{
35026		name:    "Mod16",
35027		auxType: auxBool,
35028		argLen:  2,
35029		generic: true,
35030	},
35031	{
35032		name:    "Mod16u",
35033		argLen:  2,
35034		generic: true,
35035	},
35036	{
35037		name:    "Mod32",
35038		auxType: auxBool,
35039		argLen:  2,
35040		generic: true,
35041	},
35042	{
35043		name:    "Mod32u",
35044		argLen:  2,
35045		generic: true,
35046	},
35047	{
35048		name:    "Mod64",
35049		auxType: auxBool,
35050		argLen:  2,
35051		generic: true,
35052	},
35053	{
35054		name:    "Mod64u",
35055		argLen:  2,
35056		generic: true,
35057	},
35058	{
35059		name:        "And8",
35060		argLen:      2,
35061		commutative: true,
35062		generic:     true,
35063	},
35064	{
35065		name:        "And16",
35066		argLen:      2,
35067		commutative: true,
35068		generic:     true,
35069	},
35070	{
35071		name:        "And32",
35072		argLen:      2,
35073		commutative: true,
35074		generic:     true,
35075	},
35076	{
35077		name:        "And64",
35078		argLen:      2,
35079		commutative: true,
35080		generic:     true,
35081	},
35082	{
35083		name:        "Or8",
35084		argLen:      2,
35085		commutative: true,
35086		generic:     true,
35087	},
35088	{
35089		name:        "Or16",
35090		argLen:      2,
35091		commutative: true,
35092		generic:     true,
35093	},
35094	{
35095		name:        "Or32",
35096		argLen:      2,
35097		commutative: true,
35098		generic:     true,
35099	},
35100	{
35101		name:        "Or64",
35102		argLen:      2,
35103		commutative: true,
35104		generic:     true,
35105	},
35106	{
35107		name:        "Xor8",
35108		argLen:      2,
35109		commutative: true,
35110		generic:     true,
35111	},
35112	{
35113		name:        "Xor16",
35114		argLen:      2,
35115		commutative: true,
35116		generic:     true,
35117	},
35118	{
35119		name:        "Xor32",
35120		argLen:      2,
35121		commutative: true,
35122		generic:     true,
35123	},
35124	{
35125		name:        "Xor64",
35126		argLen:      2,
35127		commutative: true,
35128		generic:     true,
35129	},
35130	{
35131		name:    "Lsh8x8",
35132		auxType: auxBool,
35133		argLen:  2,
35134		generic: true,
35135	},
35136	{
35137		name:    "Lsh8x16",
35138		auxType: auxBool,
35139		argLen:  2,
35140		generic: true,
35141	},
35142	{
35143		name:    "Lsh8x32",
35144		auxType: auxBool,
35145		argLen:  2,
35146		generic: true,
35147	},
35148	{
35149		name:    "Lsh8x64",
35150		auxType: auxBool,
35151		argLen:  2,
35152		generic: true,
35153	},
35154	{
35155		name:    "Lsh16x8",
35156		auxType: auxBool,
35157		argLen:  2,
35158		generic: true,
35159	},
35160	{
35161		name:    "Lsh16x16",
35162		auxType: auxBool,
35163		argLen:  2,
35164		generic: true,
35165	},
35166	{
35167		name:    "Lsh16x32",
35168		auxType: auxBool,
35169		argLen:  2,
35170		generic: true,
35171	},
35172	{
35173		name:    "Lsh16x64",
35174		auxType: auxBool,
35175		argLen:  2,
35176		generic: true,
35177	},
35178	{
35179		name:    "Lsh32x8",
35180		auxType: auxBool,
35181		argLen:  2,
35182		generic: true,
35183	},
35184	{
35185		name:    "Lsh32x16",
35186		auxType: auxBool,
35187		argLen:  2,
35188		generic: true,
35189	},
35190	{
35191		name:    "Lsh32x32",
35192		auxType: auxBool,
35193		argLen:  2,
35194		generic: true,
35195	},
35196	{
35197		name:    "Lsh32x64",
35198		auxType: auxBool,
35199		argLen:  2,
35200		generic: true,
35201	},
35202	{
35203		name:    "Lsh64x8",
35204		auxType: auxBool,
35205		argLen:  2,
35206		generic: true,
35207	},
35208	{
35209		name:    "Lsh64x16",
35210		auxType: auxBool,
35211		argLen:  2,
35212		generic: true,
35213	},
35214	{
35215		name:    "Lsh64x32",
35216		auxType: auxBool,
35217		argLen:  2,
35218		generic: true,
35219	},
35220	{
35221		name:    "Lsh64x64",
35222		auxType: auxBool,
35223		argLen:  2,
35224		generic: true,
35225	},
35226	{
35227		name:    "Rsh8x8",
35228		auxType: auxBool,
35229		argLen:  2,
35230		generic: true,
35231	},
35232	{
35233		name:    "Rsh8x16",
35234		auxType: auxBool,
35235		argLen:  2,
35236		generic: true,
35237	},
35238	{
35239		name:    "Rsh8x32",
35240		auxType: auxBool,
35241		argLen:  2,
35242		generic: true,
35243	},
35244	{
35245		name:    "Rsh8x64",
35246		auxType: auxBool,
35247		argLen:  2,
35248		generic: true,
35249	},
35250	{
35251		name:    "Rsh16x8",
35252		auxType: auxBool,
35253		argLen:  2,
35254		generic: true,
35255	},
35256	{
35257		name:    "Rsh16x16",
35258		auxType: auxBool,
35259		argLen:  2,
35260		generic: true,
35261	},
35262	{
35263		name:    "Rsh16x32",
35264		auxType: auxBool,
35265		argLen:  2,
35266		generic: true,
35267	},
35268	{
35269		name:    "Rsh16x64",
35270		auxType: auxBool,
35271		argLen:  2,
35272		generic: true,
35273	},
35274	{
35275		name:    "Rsh32x8",
35276		auxType: auxBool,
35277		argLen:  2,
35278		generic: true,
35279	},
35280	{
35281		name:    "Rsh32x16",
35282		auxType: auxBool,
35283		argLen:  2,
35284		generic: true,
35285	},
35286	{
35287		name:    "Rsh32x32",
35288		auxType: auxBool,
35289		argLen:  2,
35290		generic: true,
35291	},
35292	{
35293		name:    "Rsh32x64",
35294		auxType: auxBool,
35295		argLen:  2,
35296		generic: true,
35297	},
35298	{
35299		name:    "Rsh64x8",
35300		auxType: auxBool,
35301		argLen:  2,
35302		generic: true,
35303	},
35304	{
35305		name:    "Rsh64x16",
35306		auxType: auxBool,
35307		argLen:  2,
35308		generic: true,
35309	},
35310	{
35311		name:    "Rsh64x32",
35312		auxType: auxBool,
35313		argLen:  2,
35314		generic: true,
35315	},
35316	{
35317		name:    "Rsh64x64",
35318		auxType: auxBool,
35319		argLen:  2,
35320		generic: true,
35321	},
35322	{
35323		name:    "Rsh8Ux8",
35324		auxType: auxBool,
35325		argLen:  2,
35326		generic: true,
35327	},
35328	{
35329		name:    "Rsh8Ux16",
35330		auxType: auxBool,
35331		argLen:  2,
35332		generic: true,
35333	},
35334	{
35335		name:    "Rsh8Ux32",
35336		auxType: auxBool,
35337		argLen:  2,
35338		generic: true,
35339	},
35340	{
35341		name:    "Rsh8Ux64",
35342		auxType: auxBool,
35343		argLen:  2,
35344		generic: true,
35345	},
35346	{
35347		name:    "Rsh16Ux8",
35348		auxType: auxBool,
35349		argLen:  2,
35350		generic: true,
35351	},
35352	{
35353		name:    "Rsh16Ux16",
35354		auxType: auxBool,
35355		argLen:  2,
35356		generic: true,
35357	},
35358	{
35359		name:    "Rsh16Ux32",
35360		auxType: auxBool,
35361		argLen:  2,
35362		generic: true,
35363	},
35364	{
35365		name:    "Rsh16Ux64",
35366		auxType: auxBool,
35367		argLen:  2,
35368		generic: true,
35369	},
35370	{
35371		name:    "Rsh32Ux8",
35372		auxType: auxBool,
35373		argLen:  2,
35374		generic: true,
35375	},
35376	{
35377		name:    "Rsh32Ux16",
35378		auxType: auxBool,
35379		argLen:  2,
35380		generic: true,
35381	},
35382	{
35383		name:    "Rsh32Ux32",
35384		auxType: auxBool,
35385		argLen:  2,
35386		generic: true,
35387	},
35388	{
35389		name:    "Rsh32Ux64",
35390		auxType: auxBool,
35391		argLen:  2,
35392		generic: true,
35393	},
35394	{
35395		name:    "Rsh64Ux8",
35396		auxType: auxBool,
35397		argLen:  2,
35398		generic: true,
35399	},
35400	{
35401		name:    "Rsh64Ux16",
35402		auxType: auxBool,
35403		argLen:  2,
35404		generic: true,
35405	},
35406	{
35407		name:    "Rsh64Ux32",
35408		auxType: auxBool,
35409		argLen:  2,
35410		generic: true,
35411	},
35412	{
35413		name:    "Rsh64Ux64",
35414		auxType: auxBool,
35415		argLen:  2,
35416		generic: true,
35417	},
35418	{
35419		name:        "Eq8",
35420		argLen:      2,
35421		commutative: true,
35422		generic:     true,
35423	},
35424	{
35425		name:        "Eq16",
35426		argLen:      2,
35427		commutative: true,
35428		generic:     true,
35429	},
35430	{
35431		name:        "Eq32",
35432		argLen:      2,
35433		commutative: true,
35434		generic:     true,
35435	},
35436	{
35437		name:        "Eq64",
35438		argLen:      2,
35439		commutative: true,
35440		generic:     true,
35441	},
35442	{
35443		name:        "EqPtr",
35444		argLen:      2,
35445		commutative: true,
35446		generic:     true,
35447	},
35448	{
35449		name:    "EqInter",
35450		argLen:  2,
35451		generic: true,
35452	},
35453	{
35454		name:    "EqSlice",
35455		argLen:  2,
35456		generic: true,
35457	},
35458	{
35459		name:        "Eq32F",
35460		argLen:      2,
35461		commutative: true,
35462		generic:     true,
35463	},
35464	{
35465		name:        "Eq64F",
35466		argLen:      2,
35467		commutative: true,
35468		generic:     true,
35469	},
35470	{
35471		name:        "Neq8",
35472		argLen:      2,
35473		commutative: true,
35474		generic:     true,
35475	},
35476	{
35477		name:        "Neq16",
35478		argLen:      2,
35479		commutative: true,
35480		generic:     true,
35481	},
35482	{
35483		name:        "Neq32",
35484		argLen:      2,
35485		commutative: true,
35486		generic:     true,
35487	},
35488	{
35489		name:        "Neq64",
35490		argLen:      2,
35491		commutative: true,
35492		generic:     true,
35493	},
35494	{
35495		name:        "NeqPtr",
35496		argLen:      2,
35497		commutative: true,
35498		generic:     true,
35499	},
35500	{
35501		name:    "NeqInter",
35502		argLen:  2,
35503		generic: true,
35504	},
35505	{
35506		name:    "NeqSlice",
35507		argLen:  2,
35508		generic: true,
35509	},
35510	{
35511		name:        "Neq32F",
35512		argLen:      2,
35513		commutative: true,
35514		generic:     true,
35515	},
35516	{
35517		name:        "Neq64F",
35518		argLen:      2,
35519		commutative: true,
35520		generic:     true,
35521	},
35522	{
35523		name:    "Less8",
35524		argLen:  2,
35525		generic: true,
35526	},
35527	{
35528		name:    "Less8U",
35529		argLen:  2,
35530		generic: true,
35531	},
35532	{
35533		name:    "Less16",
35534		argLen:  2,
35535		generic: true,
35536	},
35537	{
35538		name:    "Less16U",
35539		argLen:  2,
35540		generic: true,
35541	},
35542	{
35543		name:    "Less32",
35544		argLen:  2,
35545		generic: true,
35546	},
35547	{
35548		name:    "Less32U",
35549		argLen:  2,
35550		generic: true,
35551	},
35552	{
35553		name:    "Less64",
35554		argLen:  2,
35555		generic: true,
35556	},
35557	{
35558		name:    "Less64U",
35559		argLen:  2,
35560		generic: true,
35561	},
35562	{
35563		name:    "Less32F",
35564		argLen:  2,
35565		generic: true,
35566	},
35567	{
35568		name:    "Less64F",
35569		argLen:  2,
35570		generic: true,
35571	},
35572	{
35573		name:    "Leq8",
35574		argLen:  2,
35575		generic: true,
35576	},
35577	{
35578		name:    "Leq8U",
35579		argLen:  2,
35580		generic: true,
35581	},
35582	{
35583		name:    "Leq16",
35584		argLen:  2,
35585		generic: true,
35586	},
35587	{
35588		name:    "Leq16U",
35589		argLen:  2,
35590		generic: true,
35591	},
35592	{
35593		name:    "Leq32",
35594		argLen:  2,
35595		generic: true,
35596	},
35597	{
35598		name:    "Leq32U",
35599		argLen:  2,
35600		generic: true,
35601	},
35602	{
35603		name:    "Leq64",
35604		argLen:  2,
35605		generic: true,
35606	},
35607	{
35608		name:    "Leq64U",
35609		argLen:  2,
35610		generic: true,
35611	},
35612	{
35613		name:    "Leq32F",
35614		argLen:  2,
35615		generic: true,
35616	},
35617	{
35618		name:    "Leq64F",
35619		argLen:  2,
35620		generic: true,
35621	},
35622	{
35623		name:    "CondSelect",
35624		argLen:  3,
35625		generic: true,
35626	},
35627	{
35628		name:        "AndB",
35629		argLen:      2,
35630		commutative: true,
35631		generic:     true,
35632	},
35633	{
35634		name:        "OrB",
35635		argLen:      2,
35636		commutative: true,
35637		generic:     true,
35638	},
35639	{
35640		name:        "EqB",
35641		argLen:      2,
35642		commutative: true,
35643		generic:     true,
35644	},
35645	{
35646		name:        "NeqB",
35647		argLen:      2,
35648		commutative: true,
35649		generic:     true,
35650	},
35651	{
35652		name:    "Not",
35653		argLen:  1,
35654		generic: true,
35655	},
35656	{
35657		name:    "Neg8",
35658		argLen:  1,
35659		generic: true,
35660	},
35661	{
35662		name:    "Neg16",
35663		argLen:  1,
35664		generic: true,
35665	},
35666	{
35667		name:    "Neg32",
35668		argLen:  1,
35669		generic: true,
35670	},
35671	{
35672		name:    "Neg64",
35673		argLen:  1,
35674		generic: true,
35675	},
35676	{
35677		name:    "Neg32F",
35678		argLen:  1,
35679		generic: true,
35680	},
35681	{
35682		name:    "Neg64F",
35683		argLen:  1,
35684		generic: true,
35685	},
35686	{
35687		name:    "Com8",
35688		argLen:  1,
35689		generic: true,
35690	},
35691	{
35692		name:    "Com16",
35693		argLen:  1,
35694		generic: true,
35695	},
35696	{
35697		name:    "Com32",
35698		argLen:  1,
35699		generic: true,
35700	},
35701	{
35702		name:    "Com64",
35703		argLen:  1,
35704		generic: true,
35705	},
35706	{
35707		name:    "Ctz8",
35708		argLen:  1,
35709		generic: true,
35710	},
35711	{
35712		name:    "Ctz16",
35713		argLen:  1,
35714		generic: true,
35715	},
35716	{
35717		name:    "Ctz32",
35718		argLen:  1,
35719		generic: true,
35720	},
35721	{
35722		name:    "Ctz64",
35723		argLen:  1,
35724		generic: true,
35725	},
35726	{
35727		name:    "Ctz8NonZero",
35728		argLen:  1,
35729		generic: true,
35730	},
35731	{
35732		name:    "Ctz16NonZero",
35733		argLen:  1,
35734		generic: true,
35735	},
35736	{
35737		name:    "Ctz32NonZero",
35738		argLen:  1,
35739		generic: true,
35740	},
35741	{
35742		name:    "Ctz64NonZero",
35743		argLen:  1,
35744		generic: true,
35745	},
35746	{
35747		name:    "BitLen8",
35748		argLen:  1,
35749		generic: true,
35750	},
35751	{
35752		name:    "BitLen16",
35753		argLen:  1,
35754		generic: true,
35755	},
35756	{
35757		name:    "BitLen32",
35758		argLen:  1,
35759		generic: true,
35760	},
35761	{
35762		name:    "BitLen64",
35763		argLen:  1,
35764		generic: true,
35765	},
35766	{
35767		name:    "Bswap32",
35768		argLen:  1,
35769		generic: true,
35770	},
35771	{
35772		name:    "Bswap64",
35773		argLen:  1,
35774		generic: true,
35775	},
35776	{
35777		name:    "BitRev8",
35778		argLen:  1,
35779		generic: true,
35780	},
35781	{
35782		name:    "BitRev16",
35783		argLen:  1,
35784		generic: true,
35785	},
35786	{
35787		name:    "BitRev32",
35788		argLen:  1,
35789		generic: true,
35790	},
35791	{
35792		name:    "BitRev64",
35793		argLen:  1,
35794		generic: true,
35795	},
35796	{
35797		name:    "PopCount8",
35798		argLen:  1,
35799		generic: true,
35800	},
35801	{
35802		name:    "PopCount16",
35803		argLen:  1,
35804		generic: true,
35805	},
35806	{
35807		name:    "PopCount32",
35808		argLen:  1,
35809		generic: true,
35810	},
35811	{
35812		name:    "PopCount64",
35813		argLen:  1,
35814		generic: true,
35815	},
35816	{
35817		name:    "RotateLeft8",
35818		argLen:  2,
35819		generic: true,
35820	},
35821	{
35822		name:    "RotateLeft16",
35823		argLen:  2,
35824		generic: true,
35825	},
35826	{
35827		name:    "RotateLeft32",
35828		argLen:  2,
35829		generic: true,
35830	},
35831	{
35832		name:    "RotateLeft64",
35833		argLen:  2,
35834		generic: true,
35835	},
35836	{
35837		name:    "Sqrt",
35838		argLen:  1,
35839		generic: true,
35840	},
35841	{
35842		name:    "Sqrt32",
35843		argLen:  1,
35844		generic: true,
35845	},
35846	{
35847		name:    "Floor",
35848		argLen:  1,
35849		generic: true,
35850	},
35851	{
35852		name:    "Ceil",
35853		argLen:  1,
35854		generic: true,
35855	},
35856	{
35857		name:    "Trunc",
35858		argLen:  1,
35859		generic: true,
35860	},
35861	{
35862		name:    "Round",
35863		argLen:  1,
35864		generic: true,
35865	},
35866	{
35867		name:    "RoundToEven",
35868		argLen:  1,
35869		generic: true,
35870	},
35871	{
35872		name:    "Abs",
35873		argLen:  1,
35874		generic: true,
35875	},
35876	{
35877		name:    "Copysign",
35878		argLen:  2,
35879		generic: true,
35880	},
35881	{
35882		name:    "FMA",
35883		argLen:  3,
35884		generic: true,
35885	},
35886	{
35887		name:      "Phi",
35888		argLen:    -1,
35889		zeroWidth: true,
35890		generic:   true,
35891	},
35892	{
35893		name:    "Copy",
35894		argLen:  1,
35895		generic: true,
35896	},
35897	{
35898		name:         "Convert",
35899		argLen:       2,
35900		resultInArg0: true,
35901		zeroWidth:    true,
35902		generic:      true,
35903	},
35904	{
35905		name:    "ConstBool",
35906		auxType: auxBool,
35907		argLen:  0,
35908		generic: true,
35909	},
35910	{
35911		name:    "ConstString",
35912		auxType: auxString,
35913		argLen:  0,
35914		generic: true,
35915	},
35916	{
35917		name:    "ConstNil",
35918		argLen:  0,
35919		generic: true,
35920	},
35921	{
35922		name:    "Const8",
35923		auxType: auxInt8,
35924		argLen:  0,
35925		generic: true,
35926	},
35927	{
35928		name:    "Const16",
35929		auxType: auxInt16,
35930		argLen:  0,
35931		generic: true,
35932	},
35933	{
35934		name:    "Const32",
35935		auxType: auxInt32,
35936		argLen:  0,
35937		generic: true,
35938	},
35939	{
35940		name:    "Const64",
35941		auxType: auxInt64,
35942		argLen:  0,
35943		generic: true,
35944	},
35945	{
35946		name:    "Const32F",
35947		auxType: auxFloat32,
35948		argLen:  0,
35949		generic: true,
35950	},
35951	{
35952		name:    "Const64F",
35953		auxType: auxFloat64,
35954		argLen:  0,
35955		generic: true,
35956	},
35957	{
35958		name:    "ConstInterface",
35959		argLen:  0,
35960		generic: true,
35961	},
35962	{
35963		name:    "ConstSlice",
35964		argLen:  0,
35965		generic: true,
35966	},
35967	{
35968		name:      "InitMem",
35969		argLen:    0,
35970		zeroWidth: true,
35971		generic:   true,
35972	},
35973	{
35974		name:      "Arg",
35975		auxType:   auxSymOff,
35976		argLen:    0,
35977		zeroWidth: true,
35978		symEffect: SymRead,
35979		generic:   true,
35980	},
35981	{
35982		name:      "ArgIntReg",
35983		auxType:   auxNameOffsetInt8,
35984		argLen:    0,
35985		zeroWidth: true,
35986		generic:   true,
35987	},
35988	{
35989		name:      "ArgFloatReg",
35990		auxType:   auxNameOffsetInt8,
35991		argLen:    0,
35992		zeroWidth: true,
35993		generic:   true,
35994	},
35995	{
35996		name:      "Addr",
35997		auxType:   auxSym,
35998		argLen:    1,
35999		symEffect: SymAddr,
36000		generic:   true,
36001	},
36002	{
36003		name:      "LocalAddr",
36004		auxType:   auxSym,
36005		argLen:    2,
36006		symEffect: SymAddr,
36007		generic:   true,
36008	},
36009	{
36010		name:      "SP",
36011		argLen:    0,
36012		zeroWidth: true,
36013		generic:   true,
36014	},
36015	{
36016		name:      "SB",
36017		argLen:    0,
36018		zeroWidth: true,
36019		generic:   true,
36020	},
36021	{
36022		name:    "Load",
36023		argLen:  2,
36024		generic: true,
36025	},
36026	{
36027		name:    "Dereference",
36028		argLen:  2,
36029		generic: true,
36030	},
36031	{
36032		name:    "Store",
36033		auxType: auxTyp,
36034		argLen:  3,
36035		generic: true,
36036	},
36037	{
36038		name:    "Move",
36039		auxType: auxTypSize,
36040		argLen:  3,
36041		generic: true,
36042	},
36043	{
36044		name:    "Zero",
36045		auxType: auxTypSize,
36046		argLen:  2,
36047		generic: true,
36048	},
36049	{
36050		name:    "StoreWB",
36051		auxType: auxTyp,
36052		argLen:  3,
36053		generic: true,
36054	},
36055	{
36056		name:    "MoveWB",
36057		auxType: auxTypSize,
36058		argLen:  3,
36059		generic: true,
36060	},
36061	{
36062		name:    "ZeroWB",
36063		auxType: auxTypSize,
36064		argLen:  2,
36065		generic: true,
36066	},
36067	{
36068		name:      "WB",
36069		auxType:   auxSym,
36070		argLen:    3,
36071		symEffect: SymNone,
36072		generic:   true,
36073	},
36074	{
36075		name:      "HasCPUFeature",
36076		auxType:   auxSym,
36077		argLen:    0,
36078		symEffect: SymNone,
36079		generic:   true,
36080	},
36081	{
36082		name:    "PanicBounds",
36083		auxType: auxInt64,
36084		argLen:  3,
36085		call:    true,
36086		generic: true,
36087	},
36088	{
36089		name:    "PanicExtend",
36090		auxType: auxInt64,
36091		argLen:  4,
36092		call:    true,
36093		generic: true,
36094	},
36095	{
36096		name:    "ClosureCall",
36097		auxType: auxCallOff,
36098		argLen:  -1,
36099		call:    true,
36100		generic: true,
36101	},
36102	{
36103		name:    "StaticCall",
36104		auxType: auxCallOff,
36105		argLen:  -1,
36106		call:    true,
36107		generic: true,
36108	},
36109	{
36110		name:    "InterCall",
36111		auxType: auxCallOff,
36112		argLen:  -1,
36113		call:    true,
36114		generic: true,
36115	},
36116	{
36117		name:    "TailCall",
36118		auxType: auxCallOff,
36119		argLen:  -1,
36120		call:    true,
36121		generic: true,
36122	},
36123	{
36124		name:    "ClosureLECall",
36125		auxType: auxCallOff,
36126		argLen:  -1,
36127		call:    true,
36128		generic: true,
36129	},
36130	{
36131		name:    "StaticLECall",
36132		auxType: auxCallOff,
36133		argLen:  -1,
36134		call:    true,
36135		generic: true,
36136	},
36137	{
36138		name:    "InterLECall",
36139		auxType: auxCallOff,
36140		argLen:  -1,
36141		call:    true,
36142		generic: true,
36143	},
36144	{
36145		name:    "TailLECall",
36146		auxType: auxCallOff,
36147		argLen:  -1,
36148		call:    true,
36149		generic: true,
36150	},
36151	{
36152		name:    "SignExt8to16",
36153		argLen:  1,
36154		generic: true,
36155	},
36156	{
36157		name:    "SignExt8to32",
36158		argLen:  1,
36159		generic: true,
36160	},
36161	{
36162		name:    "SignExt8to64",
36163		argLen:  1,
36164		generic: true,
36165	},
36166	{
36167		name:    "SignExt16to32",
36168		argLen:  1,
36169		generic: true,
36170	},
36171	{
36172		name:    "SignExt16to64",
36173		argLen:  1,
36174		generic: true,
36175	},
36176	{
36177		name:    "SignExt32to64",
36178		argLen:  1,
36179		generic: true,
36180	},
36181	{
36182		name:    "ZeroExt8to16",
36183		argLen:  1,
36184		generic: true,
36185	},
36186	{
36187		name:    "ZeroExt8to32",
36188		argLen:  1,
36189		generic: true,
36190	},
36191	{
36192		name:    "ZeroExt8to64",
36193		argLen:  1,
36194		generic: true,
36195	},
36196	{
36197		name:    "ZeroExt16to32",
36198		argLen:  1,
36199		generic: true,
36200	},
36201	{
36202		name:    "ZeroExt16to64",
36203		argLen:  1,
36204		generic: true,
36205	},
36206	{
36207		name:    "ZeroExt32to64",
36208		argLen:  1,
36209		generic: true,
36210	},
36211	{
36212		name:    "Trunc16to8",
36213		argLen:  1,
36214		generic: true,
36215	},
36216	{
36217		name:    "Trunc32to8",
36218		argLen:  1,
36219		generic: true,
36220	},
36221	{
36222		name:    "Trunc32to16",
36223		argLen:  1,
36224		generic: true,
36225	},
36226	{
36227		name:    "Trunc64to8",
36228		argLen:  1,
36229		generic: true,
36230	},
36231	{
36232		name:    "Trunc64to16",
36233		argLen:  1,
36234		generic: true,
36235	},
36236	{
36237		name:    "Trunc64to32",
36238		argLen:  1,
36239		generic: true,
36240	},
36241	{
36242		name:    "Cvt32to32F",
36243		argLen:  1,
36244		generic: true,
36245	},
36246	{
36247		name:    "Cvt32to64F",
36248		argLen:  1,
36249		generic: true,
36250	},
36251	{
36252		name:    "Cvt64to32F",
36253		argLen:  1,
36254		generic: true,
36255	},
36256	{
36257		name:    "Cvt64to64F",
36258		argLen:  1,
36259		generic: true,
36260	},
36261	{
36262		name:    "Cvt32Fto32",
36263		argLen:  1,
36264		generic: true,
36265	},
36266	{
36267		name:    "Cvt32Fto64",
36268		argLen:  1,
36269		generic: true,
36270	},
36271	{
36272		name:    "Cvt64Fto32",
36273		argLen:  1,
36274		generic: true,
36275	},
36276	{
36277		name:    "Cvt64Fto64",
36278		argLen:  1,
36279		generic: true,
36280	},
36281	{
36282		name:    "Cvt32Fto64F",
36283		argLen:  1,
36284		generic: true,
36285	},
36286	{
36287		name:    "Cvt64Fto32F",
36288		argLen:  1,
36289		generic: true,
36290	},
36291	{
36292		name:    "CvtBoolToUint8",
36293		argLen:  1,
36294		generic: true,
36295	},
36296	{
36297		name:    "Round32F",
36298		argLen:  1,
36299		generic: true,
36300	},
36301	{
36302		name:    "Round64F",
36303		argLen:  1,
36304		generic: true,
36305	},
36306	{
36307		name:    "IsNonNil",
36308		argLen:  1,
36309		generic: true,
36310	},
36311	{
36312		name:    "IsInBounds",
36313		argLen:  2,
36314		generic: true,
36315	},
36316	{
36317		name:    "IsSliceInBounds",
36318		argLen:  2,
36319		generic: true,
36320	},
36321	{
36322		name:    "NilCheck",
36323		argLen:  2,
36324		generic: true,
36325	},
36326	{
36327		name:      "GetG",
36328		argLen:    1,
36329		zeroWidth: true,
36330		generic:   true,
36331	},
36332	{
36333		name:    "GetClosurePtr",
36334		argLen:  0,
36335		generic: true,
36336	},
36337	{
36338		name:    "GetCallerPC",
36339		argLen:  0,
36340		generic: true,
36341	},
36342	{
36343		name:    "GetCallerSP",
36344		argLen:  0,
36345		generic: true,
36346	},
36347	{
36348		name:    "PtrIndex",
36349		argLen:  2,
36350		generic: true,
36351	},
36352	{
36353		name:    "OffPtr",
36354		auxType: auxInt64,
36355		argLen:  1,
36356		generic: true,
36357	},
36358	{
36359		name:    "SliceMake",
36360		argLen:  3,
36361		generic: true,
36362	},
36363	{
36364		name:    "SlicePtr",
36365		argLen:  1,
36366		generic: true,
36367	},
36368	{
36369		name:    "SliceLen",
36370		argLen:  1,
36371		generic: true,
36372	},
36373	{
36374		name:    "SliceCap",
36375		argLen:  1,
36376		generic: true,
36377	},
36378	{
36379		name:    "SlicePtrUnchecked",
36380		argLen:  1,
36381		generic: true,
36382	},
36383	{
36384		name:    "ComplexMake",
36385		argLen:  2,
36386		generic: true,
36387	},
36388	{
36389		name:    "ComplexReal",
36390		argLen:  1,
36391		generic: true,
36392	},
36393	{
36394		name:    "ComplexImag",
36395		argLen:  1,
36396		generic: true,
36397	},
36398	{
36399		name:    "StringMake",
36400		argLen:  2,
36401		generic: true,
36402	},
36403	{
36404		name:    "StringPtr",
36405		argLen:  1,
36406		generic: true,
36407	},
36408	{
36409		name:    "StringLen",
36410		argLen:  1,
36411		generic: true,
36412	},
36413	{
36414		name:    "IMake",
36415		argLen:  2,
36416		generic: true,
36417	},
36418	{
36419		name:    "ITab",
36420		argLen:  1,
36421		generic: true,
36422	},
36423	{
36424		name:    "IData",
36425		argLen:  1,
36426		generic: true,
36427	},
36428	{
36429		name:    "StructMake0",
36430		argLen:  0,
36431		generic: true,
36432	},
36433	{
36434		name:    "StructMake1",
36435		argLen:  1,
36436		generic: true,
36437	},
36438	{
36439		name:    "StructMake2",
36440		argLen:  2,
36441		generic: true,
36442	},
36443	{
36444		name:    "StructMake3",
36445		argLen:  3,
36446		generic: true,
36447	},
36448	{
36449		name:    "StructMake4",
36450		argLen:  4,
36451		generic: true,
36452	},
36453	{
36454		name:    "StructSelect",
36455		auxType: auxInt64,
36456		argLen:  1,
36457		generic: true,
36458	},
36459	{
36460		name:    "ArrayMake0",
36461		argLen:  0,
36462		generic: true,
36463	},
36464	{
36465		name:    "ArrayMake1",
36466		argLen:  1,
36467		generic: true,
36468	},
36469	{
36470		name:    "ArraySelect",
36471		auxType: auxInt64,
36472		argLen:  1,
36473		generic: true,
36474	},
36475	{
36476		name:    "StoreReg",
36477		argLen:  1,
36478		generic: true,
36479	},
36480	{
36481		name:    "LoadReg",
36482		argLen:  1,
36483		generic: true,
36484	},
36485	{
36486		name:      "FwdRef",
36487		auxType:   auxSym,
36488		argLen:    0,
36489		symEffect: SymNone,
36490		generic:   true,
36491	},
36492	{
36493		name:    "Unknown",
36494		argLen:  0,
36495		generic: true,
36496	},
36497	{
36498		name:      "VarDef",
36499		auxType:   auxSym,
36500		argLen:    1,
36501		zeroWidth: true,
36502		symEffect: SymNone,
36503		generic:   true,
36504	},
36505	{
36506		name:      "VarKill",
36507		auxType:   auxSym,
36508		argLen:    1,
36509		symEffect: SymNone,
36510		generic:   true,
36511	},
36512	{
36513		name:      "VarLive",
36514		auxType:   auxSym,
36515		argLen:    1,
36516		zeroWidth: true,
36517		symEffect: SymRead,
36518		generic:   true,
36519	},
36520	{
36521		name:      "KeepAlive",
36522		argLen:    2,
36523		zeroWidth: true,
36524		generic:   true,
36525	},
36526	{
36527		name:    "InlMark",
36528		auxType: auxInt32,
36529		argLen:  1,
36530		generic: true,
36531	},
36532	{
36533		name:    "Int64Make",
36534		argLen:  2,
36535		generic: true,
36536	},
36537	{
36538		name:    "Int64Hi",
36539		argLen:  1,
36540		generic: true,
36541	},
36542	{
36543		name:    "Int64Lo",
36544		argLen:  1,
36545		generic: true,
36546	},
36547	{
36548		name:        "Add32carry",
36549		argLen:      2,
36550		commutative: true,
36551		generic:     true,
36552	},
36553	{
36554		name:        "Add32withcarry",
36555		argLen:      3,
36556		commutative: true,
36557		generic:     true,
36558	},
36559	{
36560		name:    "Sub32carry",
36561		argLen:  2,
36562		generic: true,
36563	},
36564	{
36565		name:    "Sub32withcarry",
36566		argLen:  3,
36567		generic: true,
36568	},
36569	{
36570		name:        "Add64carry",
36571		argLen:      3,
36572		commutative: true,
36573		generic:     true,
36574	},
36575	{
36576		name:    "Sub64borrow",
36577		argLen:  3,
36578		generic: true,
36579	},
36580	{
36581		name:    "Signmask",
36582		argLen:  1,
36583		generic: true,
36584	},
36585	{
36586		name:    "Zeromask",
36587		argLen:  1,
36588		generic: true,
36589	},
36590	{
36591		name:    "Slicemask",
36592		argLen:  1,
36593		generic: true,
36594	},
36595	{
36596		name:    "SpectreIndex",
36597		argLen:  2,
36598		generic: true,
36599	},
36600	{
36601		name:    "SpectreSliceIndex",
36602		argLen:  2,
36603		generic: true,
36604	},
36605	{
36606		name:    "Cvt32Uto32F",
36607		argLen:  1,
36608		generic: true,
36609	},
36610	{
36611		name:    "Cvt32Uto64F",
36612		argLen:  1,
36613		generic: true,
36614	},
36615	{
36616		name:    "Cvt32Fto32U",
36617		argLen:  1,
36618		generic: true,
36619	},
36620	{
36621		name:    "Cvt64Fto32U",
36622		argLen:  1,
36623		generic: true,
36624	},
36625	{
36626		name:    "Cvt64Uto32F",
36627		argLen:  1,
36628		generic: true,
36629	},
36630	{
36631		name:    "Cvt64Uto64F",
36632		argLen:  1,
36633		generic: true,
36634	},
36635	{
36636		name:    "Cvt32Fto64U",
36637		argLen:  1,
36638		generic: true,
36639	},
36640	{
36641		name:    "Cvt64Fto64U",
36642		argLen:  1,
36643		generic: true,
36644	},
36645	{
36646		name:      "Select0",
36647		argLen:    1,
36648		zeroWidth: true,
36649		generic:   true,
36650	},
36651	{
36652		name:      "Select1",
36653		argLen:    1,
36654		zeroWidth: true,
36655		generic:   true,
36656	},
36657	{
36658		name:    "SelectN",
36659		auxType: auxInt64,
36660		argLen:  1,
36661		generic: true,
36662	},
36663	{
36664		name:    "SelectNAddr",
36665		auxType: auxInt64,
36666		argLen:  1,
36667		generic: true,
36668	},
36669	{
36670		name:    "MakeResult",
36671		argLen:  -1,
36672		generic: true,
36673	},
36674	{
36675		name:    "AtomicLoad8",
36676		argLen:  2,
36677		generic: true,
36678	},
36679	{
36680		name:    "AtomicLoad32",
36681		argLen:  2,
36682		generic: true,
36683	},
36684	{
36685		name:    "AtomicLoad64",
36686		argLen:  2,
36687		generic: true,
36688	},
36689	{
36690		name:    "AtomicLoadPtr",
36691		argLen:  2,
36692		generic: true,
36693	},
36694	{
36695		name:    "AtomicLoadAcq32",
36696		argLen:  2,
36697		generic: true,
36698	},
36699	{
36700		name:    "AtomicLoadAcq64",
36701		argLen:  2,
36702		generic: true,
36703	},
36704	{
36705		name:           "AtomicStore8",
36706		argLen:         3,
36707		hasSideEffects: true,
36708		generic:        true,
36709	},
36710	{
36711		name:           "AtomicStore32",
36712		argLen:         3,
36713		hasSideEffects: true,
36714		generic:        true,
36715	},
36716	{
36717		name:           "AtomicStore64",
36718		argLen:         3,
36719		hasSideEffects: true,
36720		generic:        true,
36721	},
36722	{
36723		name:           "AtomicStorePtrNoWB",
36724		argLen:         3,
36725		hasSideEffects: true,
36726		generic:        true,
36727	},
36728	{
36729		name:           "AtomicStoreRel32",
36730		argLen:         3,
36731		hasSideEffects: true,
36732		generic:        true,
36733	},
36734	{
36735		name:           "AtomicStoreRel64",
36736		argLen:         3,
36737		hasSideEffects: true,
36738		generic:        true,
36739	},
36740	{
36741		name:           "AtomicExchange32",
36742		argLen:         3,
36743		hasSideEffects: true,
36744		generic:        true,
36745	},
36746	{
36747		name:           "AtomicExchange64",
36748		argLen:         3,
36749		hasSideEffects: true,
36750		generic:        true,
36751	},
36752	{
36753		name:           "AtomicAdd32",
36754		argLen:         3,
36755		hasSideEffects: true,
36756		generic:        true,
36757	},
36758	{
36759		name:           "AtomicAdd64",
36760		argLen:         3,
36761		hasSideEffects: true,
36762		generic:        true,
36763	},
36764	{
36765		name:           "AtomicCompareAndSwap32",
36766		argLen:         4,
36767		hasSideEffects: true,
36768		generic:        true,
36769	},
36770	{
36771		name:           "AtomicCompareAndSwap64",
36772		argLen:         4,
36773		hasSideEffects: true,
36774		generic:        true,
36775	},
36776	{
36777		name:           "AtomicCompareAndSwapRel32",
36778		argLen:         4,
36779		hasSideEffects: true,
36780		generic:        true,
36781	},
36782	{
36783		name:           "AtomicAnd8",
36784		argLen:         3,
36785		hasSideEffects: true,
36786		generic:        true,
36787	},
36788	{
36789		name:           "AtomicAnd32",
36790		argLen:         3,
36791		hasSideEffects: true,
36792		generic:        true,
36793	},
36794	{
36795		name:           "AtomicOr8",
36796		argLen:         3,
36797		hasSideEffects: true,
36798		generic:        true,
36799	},
36800	{
36801		name:           "AtomicOr32",
36802		argLen:         3,
36803		hasSideEffects: true,
36804		generic:        true,
36805	},
36806	{
36807		name:           "AtomicAdd32Variant",
36808		argLen:         3,
36809		hasSideEffects: true,
36810		generic:        true,
36811	},
36812	{
36813		name:           "AtomicAdd64Variant",
36814		argLen:         3,
36815		hasSideEffects: true,
36816		generic:        true,
36817	},
36818	{
36819		name:           "AtomicExchange32Variant",
36820		argLen:         3,
36821		hasSideEffects: true,
36822		generic:        true,
36823	},
36824	{
36825		name:           "AtomicExchange64Variant",
36826		argLen:         3,
36827		hasSideEffects: true,
36828		generic:        true,
36829	},
36830	{
36831		name:           "AtomicCompareAndSwap32Variant",
36832		argLen:         4,
36833		hasSideEffects: true,
36834		generic:        true,
36835	},
36836	{
36837		name:           "AtomicCompareAndSwap64Variant",
36838		argLen:         4,
36839		hasSideEffects: true,
36840		generic:        true,
36841	},
36842	{
36843		name:           "AtomicAnd8Variant",
36844		argLen:         3,
36845		hasSideEffects: true,
36846		generic:        true,
36847	},
36848	{
36849		name:           "AtomicAnd32Variant",
36850		argLen:         3,
36851		hasSideEffects: true,
36852		generic:        true,
36853	},
36854	{
36855		name:           "AtomicOr8Variant",
36856		argLen:         3,
36857		hasSideEffects: true,
36858		generic:        true,
36859	},
36860	{
36861		name:           "AtomicOr32Variant",
36862		argLen:         3,
36863		hasSideEffects: true,
36864		generic:        true,
36865	},
36866	{
36867		name:           "PubBarrier",
36868		argLen:         1,
36869		hasSideEffects: true,
36870		generic:        true,
36871	},
36872	{
36873		name:      "Clobber",
36874		auxType:   auxSymOff,
36875		argLen:    0,
36876		symEffect: SymNone,
36877		generic:   true,
36878	},
36879	{
36880		name:    "ClobberReg",
36881		argLen:  0,
36882		generic: true,
36883	},
36884	{
36885		name:           "PrefetchCache",
36886		argLen:         2,
36887		hasSideEffects: true,
36888		generic:        true,
36889	},
36890	{
36891		name:           "PrefetchCacheStreamed",
36892		argLen:         2,
36893		hasSideEffects: true,
36894		generic:        true,
36895	},
36896}
36897
36898func (o Op) Asm() obj.As          { return opcodeTable[o].asm }
36899func (o Op) Scale() int16         { return int16(opcodeTable[o].scale) }
36900func (o Op) String() string       { return opcodeTable[o].name }
36901func (o Op) SymEffect() SymEffect { return opcodeTable[o].symEffect }
36902func (o Op) IsCall() bool         { return opcodeTable[o].call }
36903func (o Op) IsTailCall() bool     { return opcodeTable[o].tailCall }
36904func (o Op) HasSideEffects() bool { return opcodeTable[o].hasSideEffects }
36905func (o Op) UnsafePoint() bool    { return opcodeTable[o].unsafePoint }
36906func (o Op) ResultInArg0() bool   { return opcodeTable[o].resultInArg0 }
36907
36908var registers386 = [...]Register{
36909	{0, x86.REG_AX, 0, "AX"},
36910	{1, x86.REG_CX, 1, "CX"},
36911	{2, x86.REG_DX, 2, "DX"},
36912	{3, x86.REG_BX, 3, "BX"},
36913	{4, x86.REGSP, -1, "SP"},
36914	{5, x86.REG_BP, 4, "BP"},
36915	{6, x86.REG_SI, 5, "SI"},
36916	{7, x86.REG_DI, 6, "DI"},
36917	{8, x86.REG_X0, -1, "X0"},
36918	{9, x86.REG_X1, -1, "X1"},
36919	{10, x86.REG_X2, -1, "X2"},
36920	{11, x86.REG_X3, -1, "X3"},
36921	{12, x86.REG_X4, -1, "X4"},
36922	{13, x86.REG_X5, -1, "X5"},
36923	{14, x86.REG_X6, -1, "X6"},
36924	{15, x86.REG_X7, -1, "X7"},
36925	{16, 0, -1, "SB"},
36926}
36927var paramIntReg386 = []int8(nil)
36928var paramFloatReg386 = []int8(nil)
36929var gpRegMask386 = regMask(239)
36930var fpRegMask386 = regMask(65280)
36931var specialRegMask386 = regMask(0)
36932var framepointerReg386 = int8(5)
36933var linkReg386 = int8(-1)
36934var registersAMD64 = [...]Register{
36935	{0, x86.REG_AX, 0, "AX"},
36936	{1, x86.REG_CX, 1, "CX"},
36937	{2, x86.REG_DX, 2, "DX"},
36938	{3, x86.REG_BX, 3, "BX"},
36939	{4, x86.REGSP, -1, "SP"},
36940	{5, x86.REG_BP, 4, "BP"},
36941	{6, x86.REG_SI, 5, "SI"},
36942	{7, x86.REG_DI, 6, "DI"},
36943	{8, x86.REG_R8, 7, "R8"},
36944	{9, x86.REG_R9, 8, "R9"},
36945	{10, x86.REG_R10, 9, "R10"},
36946	{11, x86.REG_R11, 10, "R11"},
36947	{12, x86.REG_R12, 11, "R12"},
36948	{13, x86.REG_R13, 12, "R13"},
36949	{14, x86.REGG, -1, "g"},
36950	{15, x86.REG_R15, 13, "R15"},
36951	{16, x86.REG_X0, -1, "X0"},
36952	{17, x86.REG_X1, -1, "X1"},
36953	{18, x86.REG_X2, -1, "X2"},
36954	{19, x86.REG_X3, -1, "X3"},
36955	{20, x86.REG_X4, -1, "X4"},
36956	{21, x86.REG_X5, -1, "X5"},
36957	{22, x86.REG_X6, -1, "X6"},
36958	{23, x86.REG_X7, -1, "X7"},
36959	{24, x86.REG_X8, -1, "X8"},
36960	{25, x86.REG_X9, -1, "X9"},
36961	{26, x86.REG_X10, -1, "X10"},
36962	{27, x86.REG_X11, -1, "X11"},
36963	{28, x86.REG_X12, -1, "X12"},
36964	{29, x86.REG_X13, -1, "X13"},
36965	{30, x86.REG_X14, -1, "X14"},
36966	{31, x86.REG_X15, -1, "X15"},
36967	{32, 0, -1, "SB"},
36968}
36969var paramIntRegAMD64 = []int8{0, 3, 1, 7, 6, 8, 9, 10, 11}
36970var paramFloatRegAMD64 = []int8{16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30}
36971var gpRegMaskAMD64 = regMask(49135)
36972var fpRegMaskAMD64 = regMask(2147418112)
36973var specialRegMaskAMD64 = regMask(2147483648)
36974var framepointerRegAMD64 = int8(5)
36975var linkRegAMD64 = int8(-1)
36976var registersARM = [...]Register{
36977	{0, arm.REG_R0, 0, "R0"},
36978	{1, arm.REG_R1, 1, "R1"},
36979	{2, arm.REG_R2, 2, "R2"},
36980	{3, arm.REG_R3, 3, "R3"},
36981	{4, arm.REG_R4, 4, "R4"},
36982	{5, arm.REG_R5, 5, "R5"},
36983	{6, arm.REG_R6, 6, "R6"},
36984	{7, arm.REG_R7, 7, "R7"},
36985	{8, arm.REG_R8, 8, "R8"},
36986	{9, arm.REG_R9, 9, "R9"},
36987	{10, arm.REGG, -1, "g"},
36988	{11, arm.REG_R11, -1, "R11"},
36989	{12, arm.REG_R12, 10, "R12"},
36990	{13, arm.REGSP, -1, "SP"},
36991	{14, arm.REG_R14, 11, "R14"},
36992	{15, arm.REG_R15, -1, "R15"},
36993	{16, arm.REG_F0, -1, "F0"},
36994	{17, arm.REG_F1, -1, "F1"},
36995	{18, arm.REG_F2, -1, "F2"},
36996	{19, arm.REG_F3, -1, "F3"},
36997	{20, arm.REG_F4, -1, "F4"},
36998	{21, arm.REG_F5, -1, "F5"},
36999	{22, arm.REG_F6, -1, "F6"},
37000	{23, arm.REG_F7, -1, "F7"},
37001	{24, arm.REG_F8, -1, "F8"},
37002	{25, arm.REG_F9, -1, "F9"},
37003	{26, arm.REG_F10, -1, "F10"},
37004	{27, arm.REG_F11, -1, "F11"},
37005	{28, arm.REG_F12, -1, "F12"},
37006	{29, arm.REG_F13, -1, "F13"},
37007	{30, arm.REG_F14, -1, "F14"},
37008	{31, arm.REG_F15, -1, "F15"},
37009	{32, 0, -1, "SB"},
37010}
37011var paramIntRegARM = []int8(nil)
37012var paramFloatRegARM = []int8(nil)
37013var gpRegMaskARM = regMask(21503)
37014var fpRegMaskARM = regMask(4294901760)
37015var specialRegMaskARM = regMask(0)
37016var framepointerRegARM = int8(-1)
37017var linkRegARM = int8(14)
37018var registersARM64 = [...]Register{
37019	{0, arm64.REG_R0, 0, "R0"},
37020	{1, arm64.REG_R1, 1, "R1"},
37021	{2, arm64.REG_R2, 2, "R2"},
37022	{3, arm64.REG_R3, 3, "R3"},
37023	{4, arm64.REG_R4, 4, "R4"},
37024	{5, arm64.REG_R5, 5, "R5"},
37025	{6, arm64.REG_R6, 6, "R6"},
37026	{7, arm64.REG_R7, 7, "R7"},
37027	{8, arm64.REG_R8, 8, "R8"},
37028	{9, arm64.REG_R9, 9, "R9"},
37029	{10, arm64.REG_R10, 10, "R10"},
37030	{11, arm64.REG_R11, 11, "R11"},
37031	{12, arm64.REG_R12, 12, "R12"},
37032	{13, arm64.REG_R13, 13, "R13"},
37033	{14, arm64.REG_R14, 14, "R14"},
37034	{15, arm64.REG_R15, 15, "R15"},
37035	{16, arm64.REG_R16, 16, "R16"},
37036	{17, arm64.REG_R17, 17, "R17"},
37037	{18, arm64.REG_R18, -1, "R18"},
37038	{19, arm64.REG_R19, 18, "R19"},
37039	{20, arm64.REG_R20, 19, "R20"},
37040	{21, arm64.REG_R21, 20, "R21"},
37041	{22, arm64.REG_R22, 21, "R22"},
37042	{23, arm64.REG_R23, 22, "R23"},
37043	{24, arm64.REG_R24, 23, "R24"},
37044	{25, arm64.REG_R25, 24, "R25"},
37045	{26, arm64.REG_R26, 25, "R26"},
37046	{27, arm64.REGG, -1, "g"},
37047	{28, arm64.REG_R29, -1, "R29"},
37048	{29, arm64.REG_R30, 26, "R30"},
37049	{30, arm64.REGSP, -1, "SP"},
37050	{31, arm64.REG_F0, -1, "F0"},
37051	{32, arm64.REG_F1, -1, "F1"},
37052	{33, arm64.REG_F2, -1, "F2"},
37053	{34, arm64.REG_F3, -1, "F3"},
37054	{35, arm64.REG_F4, -1, "F4"},
37055	{36, arm64.REG_F5, -1, "F5"},
37056	{37, arm64.REG_F6, -1, "F6"},
37057	{38, arm64.REG_F7, -1, "F7"},
37058	{39, arm64.REG_F8, -1, "F8"},
37059	{40, arm64.REG_F9, -1, "F9"},
37060	{41, arm64.REG_F10, -1, "F10"},
37061	{42, arm64.REG_F11, -1, "F11"},
37062	{43, arm64.REG_F12, -1, "F12"},
37063	{44, arm64.REG_F13, -1, "F13"},
37064	{45, arm64.REG_F14, -1, "F14"},
37065	{46, arm64.REG_F15, -1, "F15"},
37066	{47, arm64.REG_F16, -1, "F16"},
37067	{48, arm64.REG_F17, -1, "F17"},
37068	{49, arm64.REG_F18, -1, "F18"},
37069	{50, arm64.REG_F19, -1, "F19"},
37070	{51, arm64.REG_F20, -1, "F20"},
37071	{52, arm64.REG_F21, -1, "F21"},
37072	{53, arm64.REG_F22, -1, "F22"},
37073	{54, arm64.REG_F23, -1, "F23"},
37074	{55, arm64.REG_F24, -1, "F24"},
37075	{56, arm64.REG_F25, -1, "F25"},
37076	{57, arm64.REG_F26, -1, "F26"},
37077	{58, arm64.REG_F27, -1, "F27"},
37078	{59, arm64.REG_F28, -1, "F28"},
37079	{60, arm64.REG_F29, -1, "F29"},
37080	{61, arm64.REG_F30, -1, "F30"},
37081	{62, arm64.REG_F31, -1, "F31"},
37082	{63, 0, -1, "SB"},
37083}
37084var paramIntRegARM64 = []int8{0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15}
37085var paramFloatRegARM64 = []int8{31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46}
37086var gpRegMaskARM64 = regMask(670826495)
37087var fpRegMaskARM64 = regMask(9223372034707292160)
37088var specialRegMaskARM64 = regMask(0)
37089var framepointerRegARM64 = int8(-1)
37090var linkRegARM64 = int8(29)
37091var registersMIPS = [...]Register{
37092	{0, mips.REG_R0, -1, "R0"},
37093	{1, mips.REG_R1, 0, "R1"},
37094	{2, mips.REG_R2, 1, "R2"},
37095	{3, mips.REG_R3, 2, "R3"},
37096	{4, mips.REG_R4, 3, "R4"},
37097	{5, mips.REG_R5, 4, "R5"},
37098	{6, mips.REG_R6, 5, "R6"},
37099	{7, mips.REG_R7, 6, "R7"},
37100	{8, mips.REG_R8, 7, "R8"},
37101	{9, mips.REG_R9, 8, "R9"},
37102	{10, mips.REG_R10, 9, "R10"},
37103	{11, mips.REG_R11, 10, "R11"},
37104	{12, mips.REG_R12, 11, "R12"},
37105	{13, mips.REG_R13, 12, "R13"},
37106	{14, mips.REG_R14, 13, "R14"},
37107	{15, mips.REG_R15, 14, "R15"},
37108	{16, mips.REG_R16, 15, "R16"},
37109	{17, mips.REG_R17, 16, "R17"},
37110	{18, mips.REG_R18, 17, "R18"},
37111	{19, mips.REG_R19, 18, "R19"},
37112	{20, mips.REG_R20, 19, "R20"},
37113	{21, mips.REG_R21, 20, "R21"},
37114	{22, mips.REG_R22, 21, "R22"},
37115	{23, mips.REG_R24, 22, "R24"},
37116	{24, mips.REG_R25, 23, "R25"},
37117	{25, mips.REG_R28, 24, "R28"},
37118	{26, mips.REGSP, -1, "SP"},
37119	{27, mips.REGG, -1, "g"},
37120	{28, mips.REG_R31, 25, "R31"},
37121	{29, mips.REG_F0, -1, "F0"},
37122	{30, mips.REG_F2, -1, "F2"},
37123	{31, mips.REG_F4, -1, "F4"},
37124	{32, mips.REG_F6, -1, "F6"},
37125	{33, mips.REG_F8, -1, "F8"},
37126	{34, mips.REG_F10, -1, "F10"},
37127	{35, mips.REG_F12, -1, "F12"},
37128	{36, mips.REG_F14, -1, "F14"},
37129	{37, mips.REG_F16, -1, "F16"},
37130	{38, mips.REG_F18, -1, "F18"},
37131	{39, mips.REG_F20, -1, "F20"},
37132	{40, mips.REG_F22, -1, "F22"},
37133	{41, mips.REG_F24, -1, "F24"},
37134	{42, mips.REG_F26, -1, "F26"},
37135	{43, mips.REG_F28, -1, "F28"},
37136	{44, mips.REG_F30, -1, "F30"},
37137	{45, mips.REG_HI, -1, "HI"},
37138	{46, mips.REG_LO, -1, "LO"},
37139	{47, 0, -1, "SB"},
37140}
37141var paramIntRegMIPS = []int8(nil)
37142var paramFloatRegMIPS = []int8(nil)
37143var gpRegMaskMIPS = regMask(335544318)
37144var fpRegMaskMIPS = regMask(35183835217920)
37145var specialRegMaskMIPS = regMask(105553116266496)
37146var framepointerRegMIPS = int8(-1)
37147var linkRegMIPS = int8(28)
37148var registersMIPS64 = [...]Register{
37149	{0, mips.REG_R0, -1, "R0"},
37150	{1, mips.REG_R1, 0, "R1"},
37151	{2, mips.REG_R2, 1, "R2"},
37152	{3, mips.REG_R3, 2, "R3"},
37153	{4, mips.REG_R4, 3, "R4"},
37154	{5, mips.REG_R5, 4, "R5"},
37155	{6, mips.REG_R6, 5, "R6"},
37156	{7, mips.REG_R7, 6, "R7"},
37157	{8, mips.REG_R8, 7, "R8"},
37158	{9, mips.REG_R9, 8, "R9"},
37159	{10, mips.REG_R10, 9, "R10"},
37160	{11, mips.REG_R11, 10, "R11"},
37161	{12, mips.REG_R12, 11, "R12"},
37162	{13, mips.REG_R13, 12, "R13"},
37163	{14, mips.REG_R14, 13, "R14"},
37164	{15, mips.REG_R15, 14, "R15"},
37165	{16, mips.REG_R16, 15, "R16"},
37166	{17, mips.REG_R17, 16, "R17"},
37167	{18, mips.REG_R18, 17, "R18"},
37168	{19, mips.REG_R19, 18, "R19"},
37169	{20, mips.REG_R20, 19, "R20"},
37170	{21, mips.REG_R21, 20, "R21"},
37171	{22, mips.REG_R22, 21, "R22"},
37172	{23, mips.REG_R24, 22, "R24"},
37173	{24, mips.REG_R25, 23, "R25"},
37174	{25, mips.REGSP, -1, "SP"},
37175	{26, mips.REGG, -1, "g"},
37176	{27, mips.REG_R31, 24, "R31"},
37177	{28, mips.REG_F0, -1, "F0"},
37178	{29, mips.REG_F1, -1, "F1"},
37179	{30, mips.REG_F2, -1, "F2"},
37180	{31, mips.REG_F3, -1, "F3"},
37181	{32, mips.REG_F4, -1, "F4"},
37182	{33, mips.REG_F5, -1, "F5"},
37183	{34, mips.REG_F6, -1, "F6"},
37184	{35, mips.REG_F7, -1, "F7"},
37185	{36, mips.REG_F8, -1, "F8"},
37186	{37, mips.REG_F9, -1, "F9"},
37187	{38, mips.REG_F10, -1, "F10"},
37188	{39, mips.REG_F11, -1, "F11"},
37189	{40, mips.REG_F12, -1, "F12"},
37190	{41, mips.REG_F13, -1, "F13"},
37191	{42, mips.REG_F14, -1, "F14"},
37192	{43, mips.REG_F15, -1, "F15"},
37193	{44, mips.REG_F16, -1, "F16"},
37194	{45, mips.REG_F17, -1, "F17"},
37195	{46, mips.REG_F18, -1, "F18"},
37196	{47, mips.REG_F19, -1, "F19"},
37197	{48, mips.REG_F20, -1, "F20"},
37198	{49, mips.REG_F21, -1, "F21"},
37199	{50, mips.REG_F22, -1, "F22"},
37200	{51, mips.REG_F23, -1, "F23"},
37201	{52, mips.REG_F24, -1, "F24"},
37202	{53, mips.REG_F25, -1, "F25"},
37203	{54, mips.REG_F26, -1, "F26"},
37204	{55, mips.REG_F27, -1, "F27"},
37205	{56, mips.REG_F28, -1, "F28"},
37206	{57, mips.REG_F29, -1, "F29"},
37207	{58, mips.REG_F30, -1, "F30"},
37208	{59, mips.REG_F31, -1, "F31"},
37209	{60, mips.REG_HI, -1, "HI"},
37210	{61, mips.REG_LO, -1, "LO"},
37211	{62, 0, -1, "SB"},
37212}
37213var paramIntRegMIPS64 = []int8(nil)
37214var paramFloatRegMIPS64 = []int8(nil)
37215var gpRegMaskMIPS64 = regMask(167772158)
37216var fpRegMaskMIPS64 = regMask(1152921504338411520)
37217var specialRegMaskMIPS64 = regMask(3458764513820540928)
37218var framepointerRegMIPS64 = int8(-1)
37219var linkRegMIPS64 = int8(27)
37220var registersPPC64 = [...]Register{
37221	{0, ppc64.REG_R0, -1, "R0"},
37222	{1, ppc64.REGSP, -1, "SP"},
37223	{2, 0, -1, "SB"},
37224	{3, ppc64.REG_R3, 0, "R3"},
37225	{4, ppc64.REG_R4, 1, "R4"},
37226	{5, ppc64.REG_R5, 2, "R5"},
37227	{6, ppc64.REG_R6, 3, "R6"},
37228	{7, ppc64.REG_R7, 4, "R7"},
37229	{8, ppc64.REG_R8, 5, "R8"},
37230	{9, ppc64.REG_R9, 6, "R9"},
37231	{10, ppc64.REG_R10, 7, "R10"},
37232	{11, ppc64.REG_R11, 8, "R11"},
37233	{12, ppc64.REG_R12, 9, "R12"},
37234	{13, ppc64.REG_R13, -1, "R13"},
37235	{14, ppc64.REG_R14, 10, "R14"},
37236	{15, ppc64.REG_R15, 11, "R15"},
37237	{16, ppc64.REG_R16, 12, "R16"},
37238	{17, ppc64.REG_R17, 13, "R17"},
37239	{18, ppc64.REG_R18, 14, "R18"},
37240	{19, ppc64.REG_R19, 15, "R19"},
37241	{20, ppc64.REG_R20, 16, "R20"},
37242	{21, ppc64.REG_R21, 17, "R21"},
37243	{22, ppc64.REG_R22, 18, "R22"},
37244	{23, ppc64.REG_R23, 19, "R23"},
37245	{24, ppc64.REG_R24, 20, "R24"},
37246	{25, ppc64.REG_R25, 21, "R25"},
37247	{26, ppc64.REG_R26, 22, "R26"},
37248	{27, ppc64.REG_R27, 23, "R27"},
37249	{28, ppc64.REG_R28, 24, "R28"},
37250	{29, ppc64.REG_R29, 25, "R29"},
37251	{30, ppc64.REGG, -1, "g"},
37252	{31, ppc64.REG_R31, -1, "R31"},
37253	{32, ppc64.REG_F0, -1, "F0"},
37254	{33, ppc64.REG_F1, -1, "F1"},
37255	{34, ppc64.REG_F2, -1, "F2"},
37256	{35, ppc64.REG_F3, -1, "F3"},
37257	{36, ppc64.REG_F4, -1, "F4"},
37258	{37, ppc64.REG_F5, -1, "F5"},
37259	{38, ppc64.REG_F6, -1, "F6"},
37260	{39, ppc64.REG_F7, -1, "F7"},
37261	{40, ppc64.REG_F8, -1, "F8"},
37262	{41, ppc64.REG_F9, -1, "F9"},
37263	{42, ppc64.REG_F10, -1, "F10"},
37264	{43, ppc64.REG_F11, -1, "F11"},
37265	{44, ppc64.REG_F12, -1, "F12"},
37266	{45, ppc64.REG_F13, -1, "F13"},
37267	{46, ppc64.REG_F14, -1, "F14"},
37268	{47, ppc64.REG_F15, -1, "F15"},
37269	{48, ppc64.REG_F16, -1, "F16"},
37270	{49, ppc64.REG_F17, -1, "F17"},
37271	{50, ppc64.REG_F18, -1, "F18"},
37272	{51, ppc64.REG_F19, -1, "F19"},
37273	{52, ppc64.REG_F20, -1, "F20"},
37274	{53, ppc64.REG_F21, -1, "F21"},
37275	{54, ppc64.REG_F22, -1, "F22"},
37276	{55, ppc64.REG_F23, -1, "F23"},
37277	{56, ppc64.REG_F24, -1, "F24"},
37278	{57, ppc64.REG_F25, -1, "F25"},
37279	{58, ppc64.REG_F26, -1, "F26"},
37280	{59, ppc64.REG_F27, -1, "F27"},
37281	{60, ppc64.REG_F28, -1, "F28"},
37282	{61, ppc64.REG_F29, -1, "F29"},
37283	{62, ppc64.REG_F30, -1, "F30"},
37284	{63, ppc64.REG_F31, -1, "F31"},
37285}
37286var paramIntRegPPC64 = []int8{3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 17}
37287var paramFloatRegPPC64 = []int8{33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44}
37288var gpRegMaskPPC64 = regMask(1073733624)
37289var fpRegMaskPPC64 = regMask(576460743713488896)
37290var specialRegMaskPPC64 = regMask(0)
37291var framepointerRegPPC64 = int8(-1)
37292var linkRegPPC64 = int8(-1)
37293var registersRISCV64 = [...]Register{
37294	{0, riscv.REG_X0, -1, "X0"},
37295	{1, riscv.REGSP, -1, "SP"},
37296	{2, riscv.REG_X3, -1, "X3"},
37297	{3, riscv.REG_X4, -1, "X4"},
37298	{4, riscv.REG_X5, 0, "X5"},
37299	{5, riscv.REG_X6, 1, "X6"},
37300	{6, riscv.REG_X7, 2, "X7"},
37301	{7, riscv.REG_X8, 3, "X8"},
37302	{8, riscv.REG_X9, 4, "X9"},
37303	{9, riscv.REG_X10, 5, "X10"},
37304	{10, riscv.REG_X11, 6, "X11"},
37305	{11, riscv.REG_X12, 7, "X12"},
37306	{12, riscv.REG_X13, 8, "X13"},
37307	{13, riscv.REG_X14, 9, "X14"},
37308	{14, riscv.REG_X15, 10, "X15"},
37309	{15, riscv.REG_X16, 11, "X16"},
37310	{16, riscv.REG_X17, 12, "X17"},
37311	{17, riscv.REG_X18, 13, "X18"},
37312	{18, riscv.REG_X19, 14, "X19"},
37313	{19, riscv.REG_X20, 15, "X20"},
37314	{20, riscv.REG_X21, 16, "X21"},
37315	{21, riscv.REG_X22, 17, "X22"},
37316	{22, riscv.REG_X23, 18, "X23"},
37317	{23, riscv.REG_X24, 19, "X24"},
37318	{24, riscv.REG_X25, 20, "X25"},
37319	{25, riscv.REG_X26, 21, "X26"},
37320	{26, riscv.REGG, -1, "g"},
37321	{27, riscv.REG_X28, 22, "X28"},
37322	{28, riscv.REG_X29, 23, "X29"},
37323	{29, riscv.REG_X30, 24, "X30"},
37324	{30, riscv.REG_X31, -1, "X31"},
37325	{31, riscv.REG_F0, -1, "F0"},
37326	{32, riscv.REG_F1, -1, "F1"},
37327	{33, riscv.REG_F2, -1, "F2"},
37328	{34, riscv.REG_F3, -1, "F3"},
37329	{35, riscv.REG_F4, -1, "F4"},
37330	{36, riscv.REG_F5, -1, "F5"},
37331	{37, riscv.REG_F6, -1, "F6"},
37332	{38, riscv.REG_F7, -1, "F7"},
37333	{39, riscv.REG_F8, -1, "F8"},
37334	{40, riscv.REG_F9, -1, "F9"},
37335	{41, riscv.REG_F10, -1, "F10"},
37336	{42, riscv.REG_F11, -1, "F11"},
37337	{43, riscv.REG_F12, -1, "F12"},
37338	{44, riscv.REG_F13, -1, "F13"},
37339	{45, riscv.REG_F14, -1, "F14"},
37340	{46, riscv.REG_F15, -1, "F15"},
37341	{47, riscv.REG_F16, -1, "F16"},
37342	{48, riscv.REG_F17, -1, "F17"},
37343	{49, riscv.REG_F18, -1, "F18"},
37344	{50, riscv.REG_F19, -1, "F19"},
37345	{51, riscv.REG_F20, -1, "F20"},
37346	{52, riscv.REG_F21, -1, "F21"},
37347	{53, riscv.REG_F22, -1, "F22"},
37348	{54, riscv.REG_F23, -1, "F23"},
37349	{55, riscv.REG_F24, -1, "F24"},
37350	{56, riscv.REG_F25, -1, "F25"},
37351	{57, riscv.REG_F26, -1, "F26"},
37352	{58, riscv.REG_F27, -1, "F27"},
37353	{59, riscv.REG_F28, -1, "F28"},
37354	{60, riscv.REG_F29, -1, "F29"},
37355	{61, riscv.REG_F30, -1, "F30"},
37356	{62, riscv.REG_F31, -1, "F31"},
37357	{63, 0, -1, "SB"},
37358}
37359var paramIntRegRISCV64 = []int8(nil)
37360var paramFloatRegRISCV64 = []int8(nil)
37361var gpRegMaskRISCV64 = regMask(1006632944)
37362var fpRegMaskRISCV64 = regMask(9223372034707292160)
37363var specialRegMaskRISCV64 = regMask(0)
37364var framepointerRegRISCV64 = int8(-1)
37365var linkRegRISCV64 = int8(0)
37366var registersS390X = [...]Register{
37367	{0, s390x.REG_R0, 0, "R0"},
37368	{1, s390x.REG_R1, 1, "R1"},
37369	{2, s390x.REG_R2, 2, "R2"},
37370	{3, s390x.REG_R3, 3, "R3"},
37371	{4, s390x.REG_R4, 4, "R4"},
37372	{5, s390x.REG_R5, 5, "R5"},
37373	{6, s390x.REG_R6, 6, "R6"},
37374	{7, s390x.REG_R7, 7, "R7"},
37375	{8, s390x.REG_R8, 8, "R8"},
37376	{9, s390x.REG_R9, 9, "R9"},
37377	{10, s390x.REG_R10, -1, "R10"},
37378	{11, s390x.REG_R11, 10, "R11"},
37379	{12, s390x.REG_R12, 11, "R12"},
37380	{13, s390x.REGG, -1, "g"},
37381	{14, s390x.REG_R14, 12, "R14"},
37382	{15, s390x.REGSP, -1, "SP"},
37383	{16, s390x.REG_F0, -1, "F0"},
37384	{17, s390x.REG_F1, -1, "F1"},
37385	{18, s390x.REG_F2, -1, "F2"},
37386	{19, s390x.REG_F3, -1, "F3"},
37387	{20, s390x.REG_F4, -1, "F4"},
37388	{21, s390x.REG_F5, -1, "F5"},
37389	{22, s390x.REG_F6, -1, "F6"},
37390	{23, s390x.REG_F7, -1, "F7"},
37391	{24, s390x.REG_F8, -1, "F8"},
37392	{25, s390x.REG_F9, -1, "F9"},
37393	{26, s390x.REG_F10, -1, "F10"},
37394	{27, s390x.REG_F11, -1, "F11"},
37395	{28, s390x.REG_F12, -1, "F12"},
37396	{29, s390x.REG_F13, -1, "F13"},
37397	{30, s390x.REG_F14, -1, "F14"},
37398	{31, s390x.REG_F15, -1, "F15"},
37399	{32, 0, -1, "SB"},
37400}
37401var paramIntRegS390X = []int8(nil)
37402var paramFloatRegS390X = []int8(nil)
37403var gpRegMaskS390X = regMask(23551)
37404var fpRegMaskS390X = regMask(4294901760)
37405var specialRegMaskS390X = regMask(0)
37406var framepointerRegS390X = int8(-1)
37407var linkRegS390X = int8(14)
37408var registersWasm = [...]Register{
37409	{0, wasm.REG_R0, 0, "R0"},
37410	{1, wasm.REG_R1, 1, "R1"},
37411	{2, wasm.REG_R2, 2, "R2"},
37412	{3, wasm.REG_R3, 3, "R3"},
37413	{4, wasm.REG_R4, 4, "R4"},
37414	{5, wasm.REG_R5, 5, "R5"},
37415	{6, wasm.REG_R6, 6, "R6"},
37416	{7, wasm.REG_R7, 7, "R7"},
37417	{8, wasm.REG_R8, 8, "R8"},
37418	{9, wasm.REG_R9, 9, "R9"},
37419	{10, wasm.REG_R10, 10, "R10"},
37420	{11, wasm.REG_R11, 11, "R11"},
37421	{12, wasm.REG_R12, 12, "R12"},
37422	{13, wasm.REG_R13, 13, "R13"},
37423	{14, wasm.REG_R14, 14, "R14"},
37424	{15, wasm.REG_R15, 15, "R15"},
37425	{16, wasm.REG_F0, -1, "F0"},
37426	{17, wasm.REG_F1, -1, "F1"},
37427	{18, wasm.REG_F2, -1, "F2"},
37428	{19, wasm.REG_F3, -1, "F3"},
37429	{20, wasm.REG_F4, -1, "F4"},
37430	{21, wasm.REG_F5, -1, "F5"},
37431	{22, wasm.REG_F6, -1, "F6"},
37432	{23, wasm.REG_F7, -1, "F7"},
37433	{24, wasm.REG_F8, -1, "F8"},
37434	{25, wasm.REG_F9, -1, "F9"},
37435	{26, wasm.REG_F10, -1, "F10"},
37436	{27, wasm.REG_F11, -1, "F11"},
37437	{28, wasm.REG_F12, -1, "F12"},
37438	{29, wasm.REG_F13, -1, "F13"},
37439	{30, wasm.REG_F14, -1, "F14"},
37440	{31, wasm.REG_F15, -1, "F15"},
37441	{32, wasm.REG_F16, -1, "F16"},
37442	{33, wasm.REG_F17, -1, "F17"},
37443	{34, wasm.REG_F18, -1, "F18"},
37444	{35, wasm.REG_F19, -1, "F19"},
37445	{36, wasm.REG_F20, -1, "F20"},
37446	{37, wasm.REG_F21, -1, "F21"},
37447	{38, wasm.REG_F22, -1, "F22"},
37448	{39, wasm.REG_F23, -1, "F23"},
37449	{40, wasm.REG_F24, -1, "F24"},
37450	{41, wasm.REG_F25, -1, "F25"},
37451	{42, wasm.REG_F26, -1, "F26"},
37452	{43, wasm.REG_F27, -1, "F27"},
37453	{44, wasm.REG_F28, -1, "F28"},
37454	{45, wasm.REG_F29, -1, "F29"},
37455	{46, wasm.REG_F30, -1, "F30"},
37456	{47, wasm.REG_F31, -1, "F31"},
37457	{48, wasm.REGSP, -1, "SP"},
37458	{49, wasm.REGG, -1, "g"},
37459	{50, 0, -1, "SB"},
37460}
37461var paramIntRegWasm = []int8(nil)
37462var paramFloatRegWasm = []int8(nil)
37463var gpRegMaskWasm = regMask(65535)
37464var fpRegMaskWasm = regMask(281474976645120)
37465var fp32RegMaskWasm = regMask(4294901760)
37466var fp64RegMaskWasm = regMask(281470681743360)
37467var specialRegMaskWasm = regMask(0)
37468var framepointerRegWasm = int8(-1)
37469var linkRegWasm = int8(-1)
37470