1// cmd/9l/optab.c, cmd/9l/asmout.c from Vita Nuova. 2// 3// Copyright © 1994-1999 Lucent Technologies Inc. All rights reserved. 4// Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net) 5// Portions Copyright © 1997-1999 Vita Nuova Limited 6// Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com) 7// Portions Copyright © 2004,2006 Bruce Ellis 8// Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net) 9// Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others 10// Portions Copyright © 2009 The Go Authors. All rights reserved. 11// 12// Permission is hereby granted, free of charge, to any person obtaining a copy 13// of this software and associated documentation files (the "Software"), to deal 14// in the Software without restriction, including without limitation the rights 15// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16// copies of the Software, and to permit persons to whom the Software is 17// furnished to do so, subject to the following conditions: 18// 19// The above copyright notice and this permission notice shall be included in 20// all copies or substantial portions of the Software. 21// 22// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE 25// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28// THE SOFTWARE. 29 30package ppc64 31 32import ( 33 "cmd/internal/obj" 34 "cmd/internal/objabi" 35 "encoding/binary" 36 "fmt" 37 "log" 38 "math" 39 "sort" 40) 41 42// ctxt9 holds state while assembling a single function. 43// Each function gets a fresh ctxt9. 44// This allows for multiple functions to be safely concurrently assembled. 45type ctxt9 struct { 46 ctxt *obj.Link 47 newprog obj.ProgAlloc 48 cursym *obj.LSym 49 autosize int32 50 instoffset int64 51 pc int64 52} 53 54// Instruction layout. 55 56const ( 57 funcAlign = 16 58) 59 60const ( 61 r0iszero = 1 62) 63 64type Optab struct { 65 as obj.As // Opcode 66 a1 uint8 67 a2 uint8 68 a3 uint8 69 a4 uint8 70 type_ int8 // cases in asmout below. E.g., 44 = st r,(ra+rb); 45 = ld (ra+rb), r 71 size int8 72 param int16 73} 74 75// This optab contains a list of opcodes with the operand 76// combinations that are implemented. Not all opcodes are in this 77// table, but are added later in buildop by calling opset for those 78// opcodes which allow the same operand combinations as an opcode 79// already in the table. 80// 81// The type field in the Optabl identifies the case in asmout where 82// the instruction word is assembled. 83var optab = []Optab{ 84 {obj.ATEXT, C_LEXT, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 85 {obj.ATEXT, C_LEXT, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 86 {obj.ATEXT, C_ADDR, C_NONE, C_NONE, C_TEXTSIZE, 0, 0, 0}, 87 {obj.ATEXT, C_ADDR, C_NONE, C_LCON, C_TEXTSIZE, 0, 0, 0}, 88 /* move register */ 89 {AMOVD, C_REG, C_NONE, C_NONE, C_REG, 1, 4, 0}, 90 {AMOVB, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 91 {AMOVBZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 92 {AMOVW, C_REG, C_NONE, C_NONE, C_REG, 12, 4, 0}, 93 {AMOVWZ, C_REG, C_NONE, C_NONE, C_REG, 13, 4, 0}, 94 {AADD, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 95 {AADD, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 96 {AADD, C_SCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 97 {AADD, C_SCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 98 {AADD, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 99 {AADD, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 100 {AADD, C_UCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 101 {AADD, C_UCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 102 {AADD, C_ANDCON, C_REG, C_NONE, C_REG, 22, 8, 0}, 103 {AADD, C_ANDCON, C_NONE, C_NONE, C_REG, 22, 8, 0}, 104 {AADD, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 105 {AADD, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 106 {AADDIS, C_ADDCON, C_REG, C_NONE, C_REG, 20, 4, 0}, 107 {AADDIS, C_ADDCON, C_NONE, C_NONE, C_REG, 20, 4, 0}, 108 {AADDC, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 109 {AADDC, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 110 {AADDC, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 111 {AADDC, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 112 {AADDC, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 113 {AADDC, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 114 {AAND, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, no literal */ 115 {AAND, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 116 {AANDCC, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 117 {AANDCC, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 118 {AANDCC, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 119 {AANDCC, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 120 {AANDCC, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 121 {AANDCC, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 122 {AANDCC, C_ADDCON, C_NONE, C_NONE, C_REG, 23, 8, 0}, 123 {AANDCC, C_ADDCON, C_REG, C_NONE, C_REG, 23, 8, 0}, 124 {AANDCC, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 125 {AANDCC, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 126 {AANDISCC, C_ANDCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 127 {AANDISCC, C_ANDCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 128 {AMULLW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, 129 {AMULLW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 130 {AMULLW, C_ADDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 131 {AMULLW, C_ADDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 132 {AMULLW, C_ANDCON, C_REG, C_NONE, C_REG, 4, 4, 0}, 133 {AMULLW, C_ANDCON, C_NONE, C_NONE, C_REG, 4, 4, 0}, 134 {AMULLW, C_LCON, C_REG, C_NONE, C_REG, 22, 12, 0}, 135 {AMULLW, C_LCON, C_NONE, C_NONE, C_REG, 22, 12, 0}, 136 {ASUBC, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, 137 {ASUBC, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 138 {ASUBC, C_REG, C_NONE, C_ADDCON, C_REG, 27, 4, 0}, 139 {ASUBC, C_REG, C_NONE, C_LCON, C_REG, 28, 12, 0}, 140 {AOR, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, /* logical, literal not cc (or/xor) */ 141 {AOR, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 142 {AOR, C_ANDCON, C_NONE, C_NONE, C_REG, 58, 4, 0}, 143 {AOR, C_ANDCON, C_REG, C_NONE, C_REG, 58, 4, 0}, 144 {AOR, C_UCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 145 {AOR, C_UCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 146 {AOR, C_ADDCON, C_NONE, C_NONE, C_REG, 23, 8, 0}, 147 {AOR, C_ADDCON, C_REG, C_NONE, C_REG, 23, 8, 0}, 148 {AOR, C_LCON, C_NONE, C_NONE, C_REG, 23, 12, 0}, 149 {AOR, C_LCON, C_REG, C_NONE, C_REG, 23, 12, 0}, 150 {AORIS, C_ANDCON, C_NONE, C_NONE, C_REG, 59, 4, 0}, 151 {AORIS, C_ANDCON, C_REG, C_NONE, C_REG, 59, 4, 0}, 152 {ADIVW, C_REG, C_REG, C_NONE, C_REG, 2, 4, 0}, /* op r1[,r2],r3 */ 153 {ADIVW, C_REG, C_NONE, C_NONE, C_REG, 2, 4, 0}, 154 {ASUB, C_REG, C_REG, C_NONE, C_REG, 10, 4, 0}, /* op r2[,r1],r3 */ 155 {ASUB, C_REG, C_NONE, C_NONE, C_REG, 10, 4, 0}, 156 {ASLW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 157 {ASLW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 158 {ASLD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 159 {ASLD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 160 {ASLD, C_SCON, C_REG, C_NONE, C_REG, 25, 4, 0}, 161 {ASLD, C_SCON, C_NONE, C_NONE, C_REG, 25, 4, 0}, 162 {ASLW, C_SCON, C_REG, C_NONE, C_REG, 57, 4, 0}, 163 {ASLW, C_SCON, C_NONE, C_NONE, C_REG, 57, 4, 0}, 164 {ASRAW, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 165 {ASRAW, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 166 {ASRAW, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 167 {ASRAW, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 168 {ASRAD, C_REG, C_NONE, C_NONE, C_REG, 6, 4, 0}, 169 {ASRAD, C_REG, C_REG, C_NONE, C_REG, 6, 4, 0}, 170 {ASRAD, C_SCON, C_REG, C_NONE, C_REG, 56, 4, 0}, 171 {ASRAD, C_SCON, C_NONE, C_NONE, C_REG, 56, 4, 0}, 172 {ARLWMI, C_SCON, C_REG, C_LCON, C_REG, 62, 4, 0}, 173 {ARLWMI, C_REG, C_REG, C_LCON, C_REG, 63, 4, 0}, 174 {ARLDMI, C_SCON, C_REG, C_LCON, C_REG, 30, 4, 0}, 175 {ARLDC, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 176 {ARLDCL, C_SCON, C_REG, C_LCON, C_REG, 29, 4, 0}, 177 {ARLDCL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 178 {ARLDICL, C_REG, C_REG, C_LCON, C_REG, 14, 4, 0}, 179 {ARLDICL, C_SCON, C_REG, C_LCON, C_REG, 14, 4, 0}, 180 {ARLDCL, C_REG, C_NONE, C_LCON, C_REG, 14, 4, 0}, 181 {AFADD, C_FREG, C_NONE, C_NONE, C_FREG, 2, 4, 0}, 182 {AFADD, C_FREG, C_FREG, C_NONE, C_FREG, 2, 4, 0}, 183 {AFABS, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 184 {AFABS, C_NONE, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 185 {AFMOVD, C_FREG, C_NONE, C_NONE, C_FREG, 33, 4, 0}, 186 {AFMADD, C_FREG, C_FREG, C_FREG, C_FREG, 34, 4, 0}, 187 {AFMUL, C_FREG, C_NONE, C_NONE, C_FREG, 32, 4, 0}, 188 {AFMUL, C_FREG, C_FREG, C_NONE, C_FREG, 32, 4, 0}, 189 190 /* store, short offset */ 191 {AMOVD, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 192 {AMOVW, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 193 {AMOVWZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 194 {AMOVBZ, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 195 {AMOVBZU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 196 {AMOVB, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 197 {AMOVBU, C_REG, C_REG, C_NONE, C_ZOREG, 7, 4, REGZERO}, 198 {AMOVD, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 199 {AMOVW, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 200 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 201 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 202 {AMOVB, C_REG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 203 {AMOVD, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 204 {AMOVW, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 205 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 206 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 207 {AMOVB, C_REG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 208 {AMOVD, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 209 {AMOVW, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 210 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 211 {AMOVBZ, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 212 {AMOVBZU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 213 {AMOVB, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 214 {AMOVBU, C_REG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 215 216 /* load, short offset */ 217 {AMOVD, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 218 {AMOVW, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 219 {AMOVWZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 220 {AMOVBZ, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 221 {AMOVBZU, C_ZOREG, C_REG, C_NONE, C_REG, 8, 4, REGZERO}, 222 {AMOVB, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 223 {AMOVBU, C_ZOREG, C_REG, C_NONE, C_REG, 9, 8, REGZERO}, 224 {AMOVD, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 225 {AMOVW, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 226 {AMOVWZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 227 {AMOVBZ, C_SEXT, C_NONE, C_NONE, C_REG, 8, 4, REGSB}, 228 {AMOVB, C_SEXT, C_NONE, C_NONE, C_REG, 9, 8, REGSB}, 229 {AMOVD, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 230 {AMOVW, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 231 {AMOVWZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 232 {AMOVBZ, C_SAUTO, C_NONE, C_NONE, C_REG, 8, 4, REGSP}, 233 {AMOVB, C_SAUTO, C_NONE, C_NONE, C_REG, 9, 8, REGSP}, 234 {AMOVD, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 235 {AMOVW, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 236 {AMOVWZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 237 {AMOVBZ, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 238 {AMOVBZU, C_SOREG, C_NONE, C_NONE, C_REG, 8, 4, REGZERO}, 239 {AMOVB, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 240 {AMOVBU, C_SOREG, C_NONE, C_NONE, C_REG, 9, 8, REGZERO}, 241 242 /* store, long offset */ 243 {AMOVD, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 244 {AMOVW, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 245 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 246 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 247 {AMOVB, C_REG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 248 {AMOVD, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 249 {AMOVW, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 250 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 251 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 252 {AMOVB, C_REG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 253 {AMOVD, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 254 {AMOVW, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 255 {AMOVWZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 256 {AMOVBZ, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 257 {AMOVB, C_REG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 258 {AMOVD, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 259 {AMOVW, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 260 {AMOVWZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 261 {AMOVBZ, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 262 {AMOVB, C_REG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 263 264 /* load, long offset */ 265 {AMOVD, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 266 {AMOVW, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 267 {AMOVWZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 268 {AMOVBZ, C_LEXT, C_NONE, C_NONE, C_REG, 36, 8, REGSB}, 269 {AMOVB, C_LEXT, C_NONE, C_NONE, C_REG, 37, 12, REGSB}, 270 {AMOVD, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 271 {AMOVW, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 272 {AMOVWZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 273 {AMOVBZ, C_LAUTO, C_NONE, C_NONE, C_REG, 36, 8, REGSP}, 274 {AMOVB, C_LAUTO, C_NONE, C_NONE, C_REG, 37, 12, REGSP}, 275 {AMOVD, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 276 {AMOVW, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 277 {AMOVWZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 278 {AMOVBZ, C_LOREG, C_NONE, C_NONE, C_REG, 36, 8, REGZERO}, 279 {AMOVB, C_LOREG, C_NONE, C_NONE, C_REG, 37, 12, REGZERO}, 280 {AMOVD, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 281 {AMOVW, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 282 {AMOVWZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 283 {AMOVBZ, C_ADDR, C_NONE, C_NONE, C_REG, 75, 8, 0}, 284 {AMOVB, C_ADDR, C_NONE, C_NONE, C_REG, 76, 12, 0}, 285 286 {AMOVD, C_TLS_LE, C_NONE, C_NONE, C_REG, 79, 4, 0}, 287 {AMOVD, C_TLS_IE, C_NONE, C_NONE, C_REG, 80, 8, 0}, 288 289 {AMOVD, C_GOTADDR, C_NONE, C_NONE, C_REG, 81, 8, 0}, 290 {AMOVD, C_TOCADDR, C_NONE, C_NONE, C_REG, 95, 8, 0}, 291 292 /* load constant */ 293 {AMOVD, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, 294 {AMOVD, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 295 {AMOVD, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 296 {AMOVD, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 297 {AMOVD, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 298 {AMOVD, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 299 {AMOVW, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 300 {AMOVW, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 301 {AMOVW, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 302 {AMOVW, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 303 {AMOVW, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 304 {AMOVW, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 305 {AMOVWZ, C_SECON, C_NONE, C_NONE, C_REG, 3, 4, REGSB}, /* TO DO: check */ 306 {AMOVWZ, C_SACON, C_NONE, C_NONE, C_REG, 3, 4, REGSP}, 307 {AMOVWZ, C_LECON, C_NONE, C_NONE, C_REG, 26, 8, REGSB}, 308 {AMOVWZ, C_LACON, C_NONE, C_NONE, C_REG, 26, 8, REGSP}, 309 {AMOVWZ, C_ADDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 310 {AMOVWZ, C_ANDCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 311 312 /* load unsigned/long constants (TO DO: check) */ 313 {AMOVD, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 314 {AMOVD, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 315 {AMOVW, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 316 {AMOVW, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 317 {AMOVWZ, C_UCON, C_NONE, C_NONE, C_REG, 3, 4, REGZERO}, 318 {AMOVWZ, C_LCON, C_NONE, C_NONE, C_REG, 19, 8, 0}, 319 {AMOVHBR, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 320 {AMOVHBR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 321 {AMOVHBR, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 322 {AMOVHBR, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 323 {ASYSCALL, C_NONE, C_NONE, C_NONE, C_NONE, 5, 4, 0}, 324 {ASYSCALL, C_REG, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 325 {ASYSCALL, C_SCON, C_NONE, C_NONE, C_NONE, 77, 12, 0}, 326 {ABEQ, C_NONE, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 327 {ABEQ, C_CREG, C_NONE, C_NONE, C_SBRA, 16, 4, 0}, 328 {ABR, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, 329 {ABR, C_NONE, C_NONE, C_NONE, C_LBRAPIC, 11, 8, 0}, 330 {ABC, C_SCON, C_REG, C_NONE, C_SBRA, 16, 4, 0}, 331 {ABC, C_SCON, C_REG, C_NONE, C_LBRA, 17, 4, 0}, 332 {ABR, C_NONE, C_NONE, C_NONE, C_LR, 18, 4, 0}, 333 {ABR, C_NONE, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 334 {ABR, C_REG, C_NONE, C_NONE, C_CTR, 18, 4, 0}, 335 {ABR, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 336 {ABC, C_NONE, C_REG, C_NONE, C_LR, 18, 4, 0}, 337 {ABC, C_NONE, C_REG, C_NONE, C_CTR, 18, 4, 0}, 338 {ABC, C_SCON, C_REG, C_NONE, C_LR, 18, 4, 0}, 339 {ABC, C_SCON, C_REG, C_NONE, C_CTR, 18, 4, 0}, 340 {ABC, C_NONE, C_NONE, C_NONE, C_ZOREG, 15, 8, 0}, 341 {AFMOVD, C_SEXT, C_NONE, C_NONE, C_FREG, 8, 4, REGSB}, 342 {AFMOVD, C_SAUTO, C_NONE, C_NONE, C_FREG, 8, 4, REGSP}, 343 {AFMOVD, C_SOREG, C_NONE, C_NONE, C_FREG, 8, 4, REGZERO}, 344 {AFMOVD, C_LEXT, C_NONE, C_NONE, C_FREG, 36, 8, REGSB}, 345 {AFMOVD, C_LAUTO, C_NONE, C_NONE, C_FREG, 36, 8, REGSP}, 346 {AFMOVD, C_LOREG, C_NONE, C_NONE, C_FREG, 36, 8, REGZERO}, 347 {AFMOVD, C_ZCON, C_NONE, C_NONE, C_FREG, 24, 4, 0}, 348 {AFMOVD, C_ADDCON, C_NONE, C_NONE, C_FREG, 24, 8, 0}, 349 {AFMOVD, C_ADDR, C_NONE, C_NONE, C_FREG, 75, 8, 0}, 350 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SEXT, 7, 4, REGSB}, 351 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SAUTO, 7, 4, REGSP}, 352 {AFMOVD, C_FREG, C_NONE, C_NONE, C_SOREG, 7, 4, REGZERO}, 353 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LEXT, 35, 8, REGSB}, 354 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LAUTO, 35, 8, REGSP}, 355 {AFMOVD, C_FREG, C_NONE, C_NONE, C_LOREG, 35, 8, REGZERO}, 356 {AFMOVD, C_FREG, C_NONE, C_NONE, C_ADDR, 74, 8, 0}, 357 {AFMOVSX, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 358 {AFMOVSX, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 359 {AFMOVSX, C_FREG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 360 {AFMOVSX, C_FREG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 361 {AFMOVSZ, C_ZOREG, C_REG, C_NONE, C_FREG, 45, 4, 0}, 362 {AFMOVSZ, C_ZOREG, C_NONE, C_NONE, C_FREG, 45, 4, 0}, 363 {ASYNC, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 364 {AWORD, C_LCON, C_NONE, C_NONE, C_NONE, 40, 4, 0}, 365 {ADWORD, C_LCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 366 {ADWORD, C_DCON, C_NONE, C_NONE, C_NONE, 31, 8, 0}, 367 {AADDME, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 368 {AEXTSB, C_REG, C_NONE, C_NONE, C_REG, 48, 4, 0}, 369 {AEXTSB, C_NONE, C_NONE, C_NONE, C_REG, 48, 4, 0}, 370 {AISEL, C_LCON, C_REG, C_REG, C_REG, 84, 4, 0}, 371 {AISEL, C_ZCON, C_REG, C_REG, C_REG, 84, 4, 0}, 372 {ANEG, C_REG, C_NONE, C_NONE, C_REG, 47, 4, 0}, 373 {ANEG, C_NONE, C_NONE, C_NONE, C_REG, 47, 4, 0}, 374 {AREM, C_REG, C_NONE, C_NONE, C_REG, 50, 12, 0}, 375 {AREM, C_REG, C_REG, C_NONE, C_REG, 50, 12, 0}, 376 {AREMU, C_REG, C_NONE, C_NONE, C_REG, 50, 16, 0}, 377 {AREMU, C_REG, C_REG, C_NONE, C_REG, 50, 16, 0}, 378 {AREMD, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 379 {AREMD, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 380 {AREMDU, C_REG, C_NONE, C_NONE, C_REG, 51, 12, 0}, 381 {AREMDU, C_REG, C_REG, C_NONE, C_REG, 51, 12, 0}, 382 {AMTFSB0, C_SCON, C_NONE, C_NONE, C_NONE, 52, 4, 0}, 383 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_FREG, 53, 4, 0}, 384 {AMOVFL, C_FREG, C_NONE, C_NONE, C_FPSCR, 64, 4, 0}, 385 {AMOVFL, C_FREG, C_NONE, C_LCON, C_FPSCR, 64, 4, 0}, 386 {AMOVFL, C_LCON, C_NONE, C_NONE, C_FPSCR, 65, 4, 0}, 387 {AMOVD, C_MSR, C_NONE, C_NONE, C_REG, 54, 4, 0}, /* mfmsr */ 388 {AMOVD, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsrd */ 389 {AMOVWZ, C_REG, C_NONE, C_NONE, C_MSR, 54, 4, 0}, /* mtmsr */ 390 391 /* Other ISA 2.05+ instructions */ 392 {APOPCNTD, C_REG, C_NONE, C_NONE, C_REG, 93, 4, 0}, /* population count, x-form */ 393 {ACMPB, C_REG, C_REG, C_NONE, C_REG, 92, 4, 0}, /* compare byte, x-form */ 394 {ACMPEQB, C_REG, C_REG, C_NONE, C_CREG, 92, 4, 0}, /* compare equal byte, x-form, ISA 3.0 */ 395 {ACMPEQB, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 396 {AFTDIV, C_FREG, C_FREG, C_NONE, C_SCON, 92, 4, 0}, /* floating test for sw divide, x-form */ 397 {AFTSQRT, C_FREG, C_NONE, C_NONE, C_SCON, 93, 4, 0}, /* floating test for sw square root, x-form */ 398 {ACOPY, C_REG, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* copy/paste facility, x-form */ 399 {ADARN, C_SCON, C_NONE, C_NONE, C_REG, 92, 4, 0}, /* deliver random number, x-form */ 400 {ALDMX, C_SOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, /* load doubleword monitored, x-form */ 401 {AMADDHD, C_REG, C_REG, C_REG, C_REG, 83, 4, 0}, /* multiply-add high/low doubleword, va-form */ 402 {AADDEX, C_REG, C_REG, C_SCON, C_REG, 94, 4, 0}, /* add extended using alternate carry, z23-form */ 403 404 /* Vector instructions */ 405 406 /* Vector load */ 407 {ALV, C_SOREG, C_NONE, C_NONE, C_VREG, 45, 4, 0}, /* vector load, x-form */ 408 409 /* Vector store */ 410 {ASTV, C_VREG, C_NONE, C_NONE, C_SOREG, 44, 4, 0}, /* vector store, x-form */ 411 412 /* Vector logical */ 413 {AVAND, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector and, vx-form */ 414 {AVOR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector or, vx-form */ 415 416 /* Vector add */ 417 {AVADDUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned modulo, vx-form */ 418 {AVADDCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add & write carry unsigned, vx-form */ 419 {AVADDUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add unsigned saturate, vx-form */ 420 {AVADDSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector add signed saturate, vx-form */ 421 {AVADDE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector add extended, va-form */ 422 423 /* Vector subtract */ 424 {AVSUBUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned modulo, vx-form */ 425 {AVSUBCU, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract & write carry unsigned, vx-form */ 426 {AVSUBUS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract unsigned saturate, vx-form */ 427 {AVSUBSS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector subtract signed saturate, vx-form */ 428 {AVSUBE, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector subtract extended, va-form */ 429 430 /* Vector multiply */ 431 {AVMULESB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 9}, /* vector multiply, vx-form */ 432 {AVPMSUM, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector polynomial multiply & sum, vx-form */ 433 {AVMSUMUDM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector multiply-sum, va-form */ 434 435 /* Vector rotate */ 436 {AVR, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector rotate, vx-form */ 437 438 /* Vector shift */ 439 {AVS, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift, vx-form */ 440 {AVSA, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector shift algebraic, vx-form */ 441 {AVSOI, C_ANDCON, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector shift by octet immediate, va-form */ 442 443 /* Vector count */ 444 {AVCLZ, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector count leading zeros, vx-form */ 445 {AVPOPCNT, C_VREG, C_NONE, C_NONE, C_VREG, 85, 4, 0}, /* vector population count, vx-form */ 446 447 /* Vector compare */ 448 {AVCMPEQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare equal, vc-form */ 449 {AVCMPGT, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare greater than, vc-form */ 450 {AVCMPNEZB, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector compare not equal, vx-form */ 451 452 /* Vector merge */ 453 {AVMRGOW, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector merge odd word, vx-form */ 454 455 /* Vector permute */ 456 {AVPERM, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector permute, va-form */ 457 458 /* Vector bit permute */ 459 {AVBPERMQ, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector bit permute, vx-form */ 460 461 /* Vector select */ 462 {AVSEL, C_VREG, C_VREG, C_VREG, C_VREG, 83, 4, 0}, /* vector select, va-form */ 463 464 /* Vector splat */ 465 {AVSPLT, C_SCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector splat, vx-form */ 466 {AVSPLT, C_ADDCON, C_VREG, C_NONE, C_VREG, 82, 4, 0}, 467 {AVSPLTI, C_SCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector splat immediate, vx-form */ 468 {AVSPLTI, C_ADDCON, C_NONE, C_NONE, C_VREG, 82, 4, 0}, 469 470 /* Vector AES */ 471 {AVCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES cipher, vx-form */ 472 {AVNCIPH, C_VREG, C_VREG, C_NONE, C_VREG, 82, 4, 0}, /* vector AES inverse cipher, vx-form */ 473 {AVSBOX, C_VREG, C_NONE, C_NONE, C_VREG, 82, 4, 0}, /* vector AES subbytes, vx-form */ 474 475 /* Vector SHA */ 476 {AVSHASIGMA, C_ANDCON, C_VREG, C_ANDCON, C_VREG, 82, 4, 0}, /* vector SHA sigma, vx-form */ 477 478 /* VSX vector load */ 479 {ALXVD2X, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx vector load, xx1-form */ 480 {ALXV, C_SOREG, C_NONE, C_NONE, C_VSREG, 96, 4, 0}, /* vsx vector load, dq-form */ 481 482 /* VSX vector store */ 483 {ASTXVD2X, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx vector store, xx1-form */ 484 {ASTXV, C_VSREG, C_NONE, C_NONE, C_SOREG, 97, 4, 0}, /* vsx vector store, dq-form */ 485 486 /* VSX scalar load */ 487 {ALXS, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar load, xx1-form */ 488 489 /* VSX scalar store */ 490 {ASTXS, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar store, xx1-form */ 491 492 /* VSX scalar as integer load */ 493 {ALXSI, C_SOREG, C_NONE, C_NONE, C_VSREG, 87, 4, 0}, /* vsx scalar as integer load, xx1-form */ 494 495 /* VSX scalar store as integer */ 496 {ASTXSI, C_VSREG, C_NONE, C_NONE, C_SOREG, 86, 4, 0}, /* vsx scalar as integer store, xx1-form */ 497 498 /* VSX move from VSR */ 499 {AMFVSR, C_VSREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, /* vsx move from vsr, xx1-form */ 500 {AMFVSR, C_FREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 501 {AMFVSR, C_VREG, C_NONE, C_NONE, C_REG, 88, 4, 0}, 502 503 /* VSX move to VSR */ 504 {AMTVSR, C_REG, C_NONE, C_NONE, C_VSREG, 88, 4, 0}, /* vsx move to vsr, xx1-form */ 505 {AMTVSR, C_REG, C_REG, C_NONE, C_VSREG, 88, 4, 0}, 506 {AMTVSR, C_REG, C_NONE, C_NONE, C_FREG, 88, 4, 0}, 507 {AMTVSR, C_REG, C_NONE, C_NONE, C_VREG, 88, 4, 0}, 508 509 /* VSX logical */ 510 {AXXLAND, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx and, xx3-form */ 511 {AXXLOR, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx or, xx3-form */ 512 513 /* VSX select */ 514 {AXXSEL, C_VSREG, C_VSREG, C_VSREG, C_VSREG, 91, 4, 0}, /* vsx select, xx4-form */ 515 516 /* VSX merge */ 517 {AXXMRG, C_VSREG, C_VSREG, C_NONE, C_VSREG, 90, 4, 0}, /* vsx merge, xx3-form */ 518 519 /* VSX splat */ 520 {AXXSPLT, C_VSREG, C_NONE, C_SCON, C_VSREG, 89, 4, 0}, /* vsx splat, xx2-form */ 521 522 /* VSX permute */ 523 {AXXPERM, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx permute, xx3-form */ 524 525 /* VSX shift */ 526 {AXXSI, C_VSREG, C_VSREG, C_SCON, C_VSREG, 90, 4, 0}, /* vsx shift immediate, xx3-form */ 527 528 /* VSX scalar FP-FP conversion */ 529 {AXSCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-fp conversion, xx2-form */ 530 531 /* VSX vector FP-FP conversion */ 532 {AXVCV, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-fp conversion, xx2-form */ 533 534 /* VSX scalar FP-integer conversion */ 535 {AXSCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar fp-integer conversion, xx2-form */ 536 537 /* VSX scalar integer-FP conversion */ 538 {AXSCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx scalar integer-fp conversion, xx2-form */ 539 540 /* VSX vector FP-integer conversion */ 541 {AXVCVX, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector fp-integer conversion, xx2-form */ 542 543 /* VSX vector integer-FP conversion */ 544 {AXVCVXP, C_VSREG, C_NONE, C_NONE, C_VSREG, 89, 4, 0}, /* vsx vector integer-fp conversion, xx2-form */ 545 546 /* 64-bit special registers */ 547 {AMOVD, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 548 {AMOVD, C_REG, C_NONE, C_NONE, C_LR, 66, 4, 0}, 549 {AMOVD, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 550 {AMOVD, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 551 {AMOVD, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 552 {AMOVD, C_LR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 553 {AMOVD, C_CTR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 554 {AMOVD, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 555 556 /* 32-bit special registers (gloss over sign-extension or not?) */ 557 {AMOVW, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 558 {AMOVW, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 559 {AMOVW, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 560 {AMOVW, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 561 {AMOVW, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 562 {AMOVWZ, C_REG, C_NONE, C_NONE, C_SPR, 66, 4, 0}, 563 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CTR, 66, 4, 0}, 564 {AMOVWZ, C_REG, C_NONE, C_NONE, C_XER, 66, 4, 0}, 565 {AMOVWZ, C_SPR, C_NONE, C_NONE, C_REG, 66, 4, 0}, 566 {AMOVWZ, C_XER, C_NONE, C_NONE, C_REG, 66, 4, 0}, 567 {AMOVFL, C_FPSCR, C_NONE, C_NONE, C_CREG, 73, 4, 0}, 568 {AMOVFL, C_CREG, C_NONE, C_NONE, C_CREG, 67, 4, 0}, 569 {AMOVW, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 570 {AMOVWZ, C_CREG, C_NONE, C_NONE, C_REG, 68, 4, 0}, 571 {AMOVFL, C_REG, C_NONE, C_NONE, C_LCON, 69, 4, 0}, 572 {AMOVFL, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 573 {AMOVW, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 574 {AMOVWZ, C_REG, C_NONE, C_NONE, C_CREG, 69, 4, 0}, 575 {ACMP, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 576 {ACMP, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 577 {ACMP, C_REG, C_NONE, C_NONE, C_ADDCON, 71, 4, 0}, 578 {ACMP, C_REG, C_REG, C_NONE, C_ADDCON, 71, 4, 0}, 579 {ACMPU, C_REG, C_NONE, C_NONE, C_REG, 70, 4, 0}, 580 {ACMPU, C_REG, C_REG, C_NONE, C_REG, 70, 4, 0}, 581 {ACMPU, C_REG, C_NONE, C_NONE, C_ANDCON, 71, 4, 0}, 582 {ACMPU, C_REG, C_REG, C_NONE, C_ANDCON, 71, 4, 0}, 583 {AFCMPO, C_FREG, C_NONE, C_NONE, C_FREG, 70, 4, 0}, 584 {AFCMPO, C_FREG, C_REG, C_NONE, C_FREG, 70, 4, 0}, 585 {ATW, C_LCON, C_REG, C_NONE, C_REG, 60, 4, 0}, 586 {ATW, C_LCON, C_REG, C_NONE, C_ADDCON, 61, 4, 0}, 587 {ADCBF, C_ZOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 588 {ADCBF, C_SOREG, C_NONE, C_NONE, C_NONE, 43, 4, 0}, 589 {ADCBF, C_ZOREG, C_REG, C_NONE, C_SCON, 43, 4, 0}, 590 {ADCBF, C_SOREG, C_NONE, C_NONE, C_SCON, 43, 4, 0}, 591 {AECOWX, C_REG, C_REG, C_NONE, C_ZOREG, 44, 4, 0}, 592 {AECIWX, C_ZOREG, C_REG, C_NONE, C_REG, 45, 4, 0}, 593 {AECOWX, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 594 {AECIWX, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 595 {ALDAR, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 596 {ALDAR, C_ZOREG, C_NONE, C_ANDCON, C_REG, 45, 4, 0}, 597 {AEIEIO, C_NONE, C_NONE, C_NONE, C_NONE, 46, 4, 0}, 598 {ATLBIE, C_REG, C_NONE, C_NONE, C_NONE, 49, 4, 0}, 599 {ATLBIE, C_SCON, C_NONE, C_NONE, C_REG, 49, 4, 0}, 600 {ASLBMFEE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 601 {ASLBMTE, C_REG, C_NONE, C_NONE, C_REG, 55, 4, 0}, 602 {ASTSW, C_REG, C_NONE, C_NONE, C_ZOREG, 44, 4, 0}, 603 {ASTSW, C_REG, C_NONE, C_LCON, C_ZOREG, 41, 4, 0}, 604 {ALSW, C_ZOREG, C_NONE, C_NONE, C_REG, 45, 4, 0}, 605 {ALSW, C_ZOREG, C_NONE, C_LCON, C_REG, 42, 4, 0}, 606 {obj.AUNDEF, C_NONE, C_NONE, C_NONE, C_NONE, 78, 4, 0}, 607 {obj.APCDATA, C_LCON, C_NONE, C_NONE, C_LCON, 0, 0, 0}, 608 {obj.AFUNCDATA, C_SCON, C_NONE, C_NONE, C_ADDR, 0, 0, 0}, 609 {obj.ANOP, C_NONE, C_NONE, C_NONE, C_NONE, 0, 0, 0}, 610 {obj.ADUFFZERO, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 611 {obj.ADUFFCOPY, C_NONE, C_NONE, C_NONE, C_LBRA, 11, 4, 0}, // same as ABR/ABL 612 {obj.APCALIGN, C_LCON, C_NONE, C_NONE, C_NONE, 0, 0, 0}, // align code 613 614 {obj.AXXX, C_NONE, C_NONE, C_NONE, C_NONE, 0, 4, 0}, 615} 616 617var oprange [ALAST & obj.AMask][]Optab 618 619var xcmp [C_NCLASS][C_NCLASS]bool 620 621// padding bytes to add to align code as requested 622func addpad(pc, a int64, ctxt *obj.Link) int { 623 switch a { 624 case 8: 625 if pc%8 != 0 { 626 return 4 627 } 628 case 16: 629 switch pc % 16 { 630 // When currently aligned to 4, avoid 3 NOPs and set to 631 // 8 byte alignment which should still help. 632 case 4, 12: 633 return 4 634 case 8: 635 return 8 636 } 637 default: 638 ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a) 639 } 640 return 0 641} 642 643func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) { 644 p := cursym.Func.Text 645 if p == nil || p.Link == nil { // handle external functions and ELF section symbols 646 return 647 } 648 649 if oprange[AANDN&obj.AMask] == nil { 650 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first") 651 } 652 653 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)} 654 655 pc := int64(0) 656 p.Pc = pc 657 658 var m int 659 var o *Optab 660 for p = p.Link; p != nil; p = p.Link { 661 p.Pc = pc 662 o = c.oplook(p) 663 m = int(o.size) 664 if m == 0 { 665 if p.As == obj.APCALIGN { 666 a := c.vregoff(&p.From) 667 m = addpad(pc, a, ctxt) 668 } else { 669 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 670 ctxt.Diag("zero-width instruction\n%v", p) 671 } 672 continue 673 } 674 } 675 pc += int64(m) 676 } 677 678 c.cursym.Size = pc 679 680 /* 681 * if any procedure is large enough to 682 * generate a large SBRA branch, then 683 * generate extra passes putting branches 684 * around jmps to fix. this is rare. 685 */ 686 bflag := 1 687 688 var otxt int64 689 var q *obj.Prog 690 for bflag != 0 { 691 bflag = 0 692 pc = 0 693 for p = c.cursym.Func.Text.Link; p != nil; p = p.Link { 694 p.Pc = pc 695 o = c.oplook(p) 696 697 // very large conditional branches 698 if (o.type_ == 16 || o.type_ == 17) && p.Pcond != nil { 699 otxt = p.Pcond.Pc - pc 700 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 { 701 q = c.newprog() 702 q.Link = p.Link 703 p.Link = q 704 q.As = ABR 705 q.To.Type = obj.TYPE_BRANCH 706 q.Pcond = p.Pcond 707 p.Pcond = q 708 q = c.newprog() 709 q.Link = p.Link 710 p.Link = q 711 q.As = ABR 712 q.To.Type = obj.TYPE_BRANCH 713 q.Pcond = q.Link.Link 714 715 //addnop(p->link); 716 //addnop(p); 717 bflag = 1 718 } 719 } 720 721 m = int(o.size) 722 if m == 0 { 723 if p.As == obj.APCALIGN { 724 a := c.vregoff(&p.From) 725 m = addpad(pc, a, ctxt) 726 } else { 727 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA { 728 ctxt.Diag("zero-width instruction\n%v", p) 729 } 730 continue 731 } 732 } 733 734 pc += int64(m) 735 } 736 737 c.cursym.Size = pc 738 } 739 740 if pc%funcAlign != 0 { 741 pc += funcAlign - (pc % funcAlign) 742 } 743 744 c.cursym.Size = pc 745 746 /* 747 * lay out the code, emitting code and data relocations. 748 */ 749 750 c.cursym.Grow(c.cursym.Size) 751 752 bp := c.cursym.P 753 var i int32 754 var out [6]uint32 755 for p := c.cursym.Func.Text.Link; p != nil; p = p.Link { 756 c.pc = p.Pc 757 o = c.oplook(p) 758 if int(o.size) > 4*len(out) { 759 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p) 760 } 761 origsize := o.size 762 c.asmout(p, o, out[:]) 763 if origsize == 0 && o.size > 0 { 764 for i = 0; i < int32(o.size/4); i++ { 765 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[0]) 766 bp = bp[4:] 767 } 768 o.size = origsize 769 } else { 770 for i = 0; i < int32(o.size/4); i++ { 771 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i]) 772 bp = bp[4:] 773 } 774 } 775 } 776} 777 778func isint32(v int64) bool { 779 return int64(int32(v)) == v 780} 781 782func isuint32(v uint64) bool { 783 return uint64(uint32(v)) == v 784} 785 786func (c *ctxt9) aclass(a *obj.Addr) int { 787 switch a.Type { 788 case obj.TYPE_NONE: 789 return C_NONE 790 791 case obj.TYPE_REG: 792 if REG_R0 <= a.Reg && a.Reg <= REG_R31 { 793 return C_REG 794 } 795 if REG_F0 <= a.Reg && a.Reg <= REG_F31 { 796 return C_FREG 797 } 798 if REG_V0 <= a.Reg && a.Reg <= REG_V31 { 799 return C_VREG 800 } 801 if REG_VS0 <= a.Reg && a.Reg <= REG_VS63 { 802 return C_VSREG 803 } 804 if REG_CR0 <= a.Reg && a.Reg <= REG_CR7 || a.Reg == REG_CR { 805 return C_CREG 806 } 807 if REG_SPR0 <= a.Reg && a.Reg <= REG_SPR0+1023 { 808 switch a.Reg { 809 case REG_LR: 810 return C_LR 811 812 case REG_XER: 813 return C_XER 814 815 case REG_CTR: 816 return C_CTR 817 } 818 819 return C_SPR 820 } 821 822 if REG_DCR0 <= a.Reg && a.Reg <= REG_DCR0+1023 { 823 return C_SPR 824 } 825 if a.Reg == REG_FPSCR { 826 return C_FPSCR 827 } 828 if a.Reg == REG_MSR { 829 return C_MSR 830 } 831 return C_GOK 832 833 case obj.TYPE_MEM: 834 switch a.Name { 835 case obj.NAME_EXTERN, 836 obj.NAME_STATIC: 837 if a.Sym == nil { 838 break 839 } 840 c.instoffset = a.Offset 841 if a.Sym != nil { // use relocation 842 if a.Sym.Type == objabi.STLSBSS { 843 if c.ctxt.Flag_shared { 844 return C_TLS_IE 845 } else { 846 return C_TLS_LE 847 } 848 } 849 return C_ADDR 850 } 851 return C_LEXT 852 853 case obj.NAME_GOTREF: 854 return C_GOTADDR 855 856 case obj.NAME_TOCREF: 857 return C_TOCADDR 858 859 case obj.NAME_AUTO: 860 c.instoffset = int64(c.autosize) + a.Offset 861 if c.instoffset >= -BIG && c.instoffset < BIG { 862 return C_SAUTO 863 } 864 return C_LAUTO 865 866 case obj.NAME_PARAM: 867 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 868 if c.instoffset >= -BIG && c.instoffset < BIG { 869 return C_SAUTO 870 } 871 return C_LAUTO 872 873 case obj.NAME_NONE: 874 c.instoffset = a.Offset 875 if c.instoffset == 0 { 876 return C_ZOREG 877 } 878 if c.instoffset >= -BIG && c.instoffset < BIG { 879 return C_SOREG 880 } 881 return C_LOREG 882 } 883 884 return C_GOK 885 886 case obj.TYPE_TEXTSIZE: 887 return C_TEXTSIZE 888 889 case obj.TYPE_FCONST: 890 // The only cases where FCONST will occur are with float64 +/- 0. 891 // All other float constants are generated in memory. 892 f64 := a.Val.(float64) 893 if f64 == 0 { 894 if math.Signbit(f64) { 895 return C_ADDCON 896 } 897 return C_ZCON 898 } 899 log.Fatalf("Unexpected nonzero FCONST operand %v", a) 900 901 case obj.TYPE_CONST, 902 obj.TYPE_ADDR: 903 switch a.Name { 904 case obj.NAME_NONE: 905 c.instoffset = a.Offset 906 if a.Reg != 0 { 907 if -BIG <= c.instoffset && c.instoffset <= BIG { 908 return C_SACON 909 } 910 if isint32(c.instoffset) { 911 return C_LACON 912 } 913 return C_DACON 914 } 915 916 case obj.NAME_EXTERN, 917 obj.NAME_STATIC: 918 s := a.Sym 919 if s == nil { 920 return C_GOK 921 } 922 923 c.instoffset = a.Offset 924 925 /* not sure why this barfs */ 926 return C_LCON 927 928 case obj.NAME_AUTO: 929 c.instoffset = int64(c.autosize) + a.Offset 930 if c.instoffset >= -BIG && c.instoffset < BIG { 931 return C_SACON 932 } 933 return C_LACON 934 935 case obj.NAME_PARAM: 936 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.FixedFrameSize() 937 if c.instoffset >= -BIG && c.instoffset < BIG { 938 return C_SACON 939 } 940 return C_LACON 941 942 default: 943 return C_GOK 944 } 945 946 if c.instoffset >= 0 { 947 if c.instoffset == 0 { 948 return C_ZCON 949 } 950 if c.instoffset <= 0x7fff { 951 return C_SCON 952 } 953 if c.instoffset <= 0xffff { 954 return C_ANDCON 955 } 956 if c.instoffset&0xffff == 0 && isuint32(uint64(c.instoffset)) { /* && (instoffset & (1<<31)) == 0) */ 957 return C_UCON 958 } 959 if isint32(c.instoffset) || isuint32(uint64(c.instoffset)) { 960 return C_LCON 961 } 962 return C_DCON 963 } 964 965 if c.instoffset >= -0x8000 { 966 return C_ADDCON 967 } 968 if c.instoffset&0xffff == 0 && isint32(c.instoffset) { 969 return C_UCON 970 } 971 if isint32(c.instoffset) { 972 return C_LCON 973 } 974 return C_DCON 975 976 case obj.TYPE_BRANCH: 977 if a.Sym != nil && c.ctxt.Flag_dynlink { 978 return C_LBRAPIC 979 } 980 return C_SBRA 981 } 982 983 return C_GOK 984} 985 986func prasm(p *obj.Prog) { 987 fmt.Printf("%v\n", p) 988} 989 990func (c *ctxt9) oplook(p *obj.Prog) *Optab { 991 a1 := int(p.Optab) 992 if a1 != 0 { 993 return &optab[a1-1] 994 } 995 a1 = int(p.From.Class) 996 if a1 == 0 { 997 a1 = c.aclass(&p.From) + 1 998 p.From.Class = int8(a1) 999 } 1000 1001 a1-- 1002 a3 := C_NONE + 1 1003 if p.GetFrom3() != nil { 1004 a3 = int(p.GetFrom3().Class) 1005 if a3 == 0 { 1006 a3 = c.aclass(p.GetFrom3()) + 1 1007 p.GetFrom3().Class = int8(a3) 1008 } 1009 } 1010 1011 a3-- 1012 a4 := int(p.To.Class) 1013 if a4 == 0 { 1014 a4 = c.aclass(&p.To) + 1 1015 p.To.Class = int8(a4) 1016 } 1017 1018 a4-- 1019 a2 := C_NONE 1020 if p.Reg != 0 { 1021 if REG_R0 <= p.Reg && p.Reg <= REG_R31 { 1022 a2 = C_REG 1023 } else if REG_V0 <= p.Reg && p.Reg <= REG_V31 { 1024 a2 = C_VREG 1025 } else if REG_VS0 <= p.Reg && p.Reg <= REG_VS63 { 1026 a2 = C_VSREG 1027 } else if REG_F0 <= p.Reg && p.Reg <= REG_F31 { 1028 a2 = C_FREG 1029 } 1030 } 1031 1032 // c.ctxt.Logf("oplook %v %d %d %d %d\n", p, a1, a2, a3, a4) 1033 ops := oprange[p.As&obj.AMask] 1034 c1 := &xcmp[a1] 1035 c3 := &xcmp[a3] 1036 c4 := &xcmp[a4] 1037 for i := range ops { 1038 op := &ops[i] 1039 if int(op.a2) == a2 && c1[op.a1] && c3[op.a3] && c4[op.a4] { 1040 p.Optab = uint16(cap(optab) - cap(ops) + i + 1) 1041 return op 1042 } 1043 } 1044 1045 c.ctxt.Diag("illegal combination %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4)) 1046 prasm(p) 1047 if ops == nil { 1048 ops = optab 1049 } 1050 return &ops[0] 1051} 1052 1053func cmp(a int, b int) bool { 1054 if a == b { 1055 return true 1056 } 1057 switch a { 1058 case C_LCON: 1059 if b == C_ZCON || b == C_SCON || b == C_UCON || b == C_ADDCON || b == C_ANDCON { 1060 return true 1061 } 1062 1063 case C_ADDCON: 1064 if b == C_ZCON || b == C_SCON { 1065 return true 1066 } 1067 1068 case C_ANDCON: 1069 if b == C_ZCON || b == C_SCON { 1070 return true 1071 } 1072 1073 case C_SPR: 1074 if b == C_LR || b == C_XER || b == C_CTR { 1075 return true 1076 } 1077 1078 case C_UCON: 1079 if b == C_ZCON { 1080 return true 1081 } 1082 1083 case C_SCON: 1084 if b == C_ZCON { 1085 return true 1086 } 1087 1088 case C_LACON: 1089 if b == C_SACON { 1090 return true 1091 } 1092 1093 case C_LBRA: 1094 if b == C_SBRA { 1095 return true 1096 } 1097 1098 case C_LEXT: 1099 if b == C_SEXT { 1100 return true 1101 } 1102 1103 case C_LAUTO: 1104 if b == C_SAUTO { 1105 return true 1106 } 1107 1108 case C_REG: 1109 if b == C_ZCON { 1110 return r0iszero != 0 /*TypeKind(100016)*/ 1111 } 1112 1113 case C_LOREG: 1114 if b == C_ZOREG || b == C_SOREG { 1115 return true 1116 } 1117 1118 case C_SOREG: 1119 if b == C_ZOREG { 1120 return true 1121 } 1122 1123 case C_ANY: 1124 return true 1125 } 1126 1127 return false 1128} 1129 1130type ocmp []Optab 1131 1132func (x ocmp) Len() int { 1133 return len(x) 1134} 1135 1136func (x ocmp) Swap(i, j int) { 1137 x[i], x[j] = x[j], x[i] 1138} 1139 1140// Used when sorting the optab. Sorting is 1141// done in a way so that the best choice of 1142// opcode/operand combination is considered first. 1143func (x ocmp) Less(i, j int) bool { 1144 p1 := &x[i] 1145 p2 := &x[j] 1146 n := int(p1.as) - int(p2.as) 1147 // same opcode 1148 if n != 0 { 1149 return n < 0 1150 } 1151 // Consider those that generate fewer 1152 // instructions first. 1153 n = int(p1.size) - int(p2.size) 1154 if n != 0 { 1155 return n < 0 1156 } 1157 // operand order should match 1158 // better choices first 1159 n = int(p1.a1) - int(p2.a1) 1160 if n != 0 { 1161 return n < 0 1162 } 1163 n = int(p1.a2) - int(p2.a2) 1164 if n != 0 { 1165 return n < 0 1166 } 1167 n = int(p1.a3) - int(p2.a3) 1168 if n != 0 { 1169 return n < 0 1170 } 1171 n = int(p1.a4) - int(p2.a4) 1172 if n != 0 { 1173 return n < 0 1174 } 1175 return false 1176} 1177 1178// Add an entry to the opcode table for 1179// a new opcode b0 with the same operand combinations 1180// as opcode a. 1181func opset(a, b0 obj.As) { 1182 oprange[a&obj.AMask] = oprange[b0] 1183} 1184 1185// Build the opcode table 1186func buildop(ctxt *obj.Link) { 1187 if oprange[AANDN&obj.AMask] != nil { 1188 // Already initialized; stop now. 1189 // This happens in the cmd/asm tests, 1190 // each of which re-initializes the arch. 1191 return 1192 } 1193 1194 var n int 1195 1196 for i := 0; i < C_NCLASS; i++ { 1197 for n = 0; n < C_NCLASS; n++ { 1198 if cmp(n, i) { 1199 xcmp[i][n] = true 1200 } 1201 } 1202 } 1203 for n = 0; optab[n].as != obj.AXXX; n++ { 1204 } 1205 sort.Sort(ocmp(optab[:n])) 1206 for i := 0; i < n; i++ { 1207 r := optab[i].as 1208 r0 := r & obj.AMask 1209 start := i 1210 for optab[i].as == r { 1211 i++ 1212 } 1213 oprange[r0] = optab[start:i] 1214 i-- 1215 1216 switch r { 1217 default: 1218 ctxt.Diag("unknown op in build: %v", r) 1219 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r) 1220 1221 case ADCBF: /* unary indexed: op (b+a); op (b) */ 1222 opset(ADCBI, r0) 1223 1224 opset(ADCBST, r0) 1225 opset(ADCBT, r0) 1226 opset(ADCBTST, r0) 1227 opset(ADCBZ, r0) 1228 opset(AICBI, r0) 1229 1230 case AECOWX: /* indexed store: op s,(b+a); op s,(b) */ 1231 opset(ASTWCCC, r0) 1232 opset(ASTBCCC, r0) 1233 1234 opset(ASTDCCC, r0) 1235 1236 case AREM: /* macro */ 1237 opset(AREMCC, r0) 1238 1239 opset(AREMV, r0) 1240 opset(AREMVCC, r0) 1241 1242 case AREMU: 1243 opset(AREMU, r0) 1244 opset(AREMUCC, r0) 1245 opset(AREMUV, r0) 1246 opset(AREMUVCC, r0) 1247 1248 case AREMD: 1249 opset(AREMDCC, r0) 1250 opset(AREMDV, r0) 1251 opset(AREMDVCC, r0) 1252 1253 case AREMDU: 1254 opset(AREMDU, r0) 1255 opset(AREMDUCC, r0) 1256 opset(AREMDUV, r0) 1257 opset(AREMDUVCC, r0) 1258 1259 case ADIVW: /* op Rb[,Ra],Rd */ 1260 opset(AMULHW, r0) 1261 1262 opset(AMULHWCC, r0) 1263 opset(AMULHWU, r0) 1264 opset(AMULHWUCC, r0) 1265 opset(AMULLWCC, r0) 1266 opset(AMULLWVCC, r0) 1267 opset(AMULLWV, r0) 1268 opset(ADIVWCC, r0) 1269 opset(ADIVWV, r0) 1270 opset(ADIVWVCC, r0) 1271 opset(ADIVWU, r0) 1272 opset(ADIVWUCC, r0) 1273 opset(ADIVWUV, r0) 1274 opset(ADIVWUVCC, r0) 1275 opset(AADDCC, r0) 1276 opset(AADDCV, r0) 1277 opset(AADDCVCC, r0) 1278 opset(AADDV, r0) 1279 opset(AADDVCC, r0) 1280 opset(AADDE, r0) 1281 opset(AADDECC, r0) 1282 opset(AADDEV, r0) 1283 opset(AADDEVCC, r0) 1284 opset(ACRAND, r0) 1285 opset(ACRANDN, r0) 1286 opset(ACREQV, r0) 1287 opset(ACRNAND, r0) 1288 opset(ACRNOR, r0) 1289 opset(ACROR, r0) 1290 opset(ACRORN, r0) 1291 opset(ACRXOR, r0) 1292 opset(AMULHD, r0) 1293 opset(AMULHDCC, r0) 1294 opset(AMULHDU, r0) 1295 opset(AMULHDUCC, r0) 1296 opset(AMULLD, r0) 1297 opset(AMULLDCC, r0) 1298 opset(AMULLDVCC, r0) 1299 opset(AMULLDV, r0) 1300 opset(ADIVD, r0) 1301 opset(ADIVDCC, r0) 1302 opset(ADIVDE, r0) 1303 opset(ADIVDEU, r0) 1304 opset(ADIVDECC, r0) 1305 opset(ADIVDEUCC, r0) 1306 opset(ADIVDVCC, r0) 1307 opset(ADIVDV, r0) 1308 opset(ADIVDU, r0) 1309 opset(ADIVDUCC, r0) 1310 opset(ADIVDUVCC, r0) 1311 opset(ADIVDUCC, r0) 1312 1313 case APOPCNTD: /* popcntd, popcntw, popcntb, cnttzw, cnttzd */ 1314 opset(APOPCNTW, r0) 1315 opset(APOPCNTB, r0) 1316 opset(ACNTTZW, r0) 1317 opset(ACNTTZWCC, r0) 1318 opset(ACNTTZD, r0) 1319 opset(ACNTTZDCC, r0) 1320 1321 case ACOPY: /* copy, paste. */ 1322 opset(APASTECC, r0) 1323 1324 case AMADDHD: /* maddhd, maddhdu, maddld */ 1325 opset(AMADDHDU, r0) 1326 opset(AMADDLD, r0) 1327 1328 case AMOVBZ: /* lbz, stz, rlwm(r/r), lhz, lha, stz, and x variants */ 1329 opset(AMOVH, r0) 1330 opset(AMOVHZ, r0) 1331 1332 case AMOVBZU: /* lbz[x]u, stb[x]u, lhz[x]u, lha[x]u, sth[u]x, ld[x]u, std[u]x */ 1333 opset(AMOVHU, r0) 1334 1335 opset(AMOVHZU, r0) 1336 opset(AMOVWU, r0) 1337 opset(AMOVWZU, r0) 1338 opset(AMOVDU, r0) 1339 opset(AMOVMW, r0) 1340 1341 case ALV: /* lvebx, lvehx, lvewx, lvx, lvxl, lvsl, lvsr */ 1342 opset(ALVEBX, r0) 1343 opset(ALVEHX, r0) 1344 opset(ALVEWX, r0) 1345 opset(ALVX, r0) 1346 opset(ALVXL, r0) 1347 opset(ALVSL, r0) 1348 opset(ALVSR, r0) 1349 1350 case ASTV: /* stvebx, stvehx, stvewx, stvx, stvxl */ 1351 opset(ASTVEBX, r0) 1352 opset(ASTVEHX, r0) 1353 opset(ASTVEWX, r0) 1354 opset(ASTVX, r0) 1355 opset(ASTVXL, r0) 1356 1357 case AVAND: /* vand, vandc, vnand */ 1358 opset(AVAND, r0) 1359 opset(AVANDC, r0) 1360 opset(AVNAND, r0) 1361 1362 case AVMRGOW: /* vmrgew, vmrgow */ 1363 opset(AVMRGEW, r0) 1364 1365 case AVOR: /* vor, vorc, vxor, vnor, veqv */ 1366 opset(AVOR, r0) 1367 opset(AVORC, r0) 1368 opset(AVXOR, r0) 1369 opset(AVNOR, r0) 1370 opset(AVEQV, r0) 1371 1372 case AVADDUM: /* vaddubm, vadduhm, vadduwm, vaddudm, vadduqm */ 1373 opset(AVADDUBM, r0) 1374 opset(AVADDUHM, r0) 1375 opset(AVADDUWM, r0) 1376 opset(AVADDUDM, r0) 1377 opset(AVADDUQM, r0) 1378 1379 case AVADDCU: /* vaddcuq, vaddcuw */ 1380 opset(AVADDCUQ, r0) 1381 opset(AVADDCUW, r0) 1382 1383 case AVADDUS: /* vaddubs, vadduhs, vadduws */ 1384 opset(AVADDUBS, r0) 1385 opset(AVADDUHS, r0) 1386 opset(AVADDUWS, r0) 1387 1388 case AVADDSS: /* vaddsbs, vaddshs, vaddsws */ 1389 opset(AVADDSBS, r0) 1390 opset(AVADDSHS, r0) 1391 opset(AVADDSWS, r0) 1392 1393 case AVADDE: /* vaddeuqm, vaddecuq */ 1394 opset(AVADDEUQM, r0) 1395 opset(AVADDECUQ, r0) 1396 1397 case AVSUBUM: /* vsububm, vsubuhm, vsubuwm, vsubudm, vsubuqm */ 1398 opset(AVSUBUBM, r0) 1399 opset(AVSUBUHM, r0) 1400 opset(AVSUBUWM, r0) 1401 opset(AVSUBUDM, r0) 1402 opset(AVSUBUQM, r0) 1403 1404 case AVSUBCU: /* vsubcuq, vsubcuw */ 1405 opset(AVSUBCUQ, r0) 1406 opset(AVSUBCUW, r0) 1407 1408 case AVSUBUS: /* vsububs, vsubuhs, vsubuws */ 1409 opset(AVSUBUBS, r0) 1410 opset(AVSUBUHS, r0) 1411 opset(AVSUBUWS, r0) 1412 1413 case AVSUBSS: /* vsubsbs, vsubshs, vsubsws */ 1414 opset(AVSUBSBS, r0) 1415 opset(AVSUBSHS, r0) 1416 opset(AVSUBSWS, r0) 1417 1418 case AVSUBE: /* vsubeuqm, vsubecuq */ 1419 opset(AVSUBEUQM, r0) 1420 opset(AVSUBECUQ, r0) 1421 1422 case AVMULESB: /* vmulesb, vmulosb, vmuleub, vmuloub, vmulosh, vmulouh, vmulesw, vmulosw, vmuleuw, vmulouw, vmuluwm */ 1423 opset(AVMULOSB, r0) 1424 opset(AVMULEUB, r0) 1425 opset(AVMULOUB, r0) 1426 opset(AVMULESH, r0) 1427 opset(AVMULOSH, r0) 1428 opset(AVMULEUH, r0) 1429 opset(AVMULOUH, r0) 1430 opset(AVMULESW, r0) 1431 opset(AVMULOSW, r0) 1432 opset(AVMULEUW, r0) 1433 opset(AVMULOUW, r0) 1434 opset(AVMULUWM, r0) 1435 case AVPMSUM: /* vpmsumb, vpmsumh, vpmsumw, vpmsumd */ 1436 opset(AVPMSUMB, r0) 1437 opset(AVPMSUMH, r0) 1438 opset(AVPMSUMW, r0) 1439 opset(AVPMSUMD, r0) 1440 1441 case AVR: /* vrlb, vrlh, vrlw, vrld */ 1442 opset(AVRLB, r0) 1443 opset(AVRLH, r0) 1444 opset(AVRLW, r0) 1445 opset(AVRLD, r0) 1446 1447 case AVS: /* vs[l,r], vs[l,r]o, vs[l,r]b, vs[l,r]h, vs[l,r]w, vs[l,r]d */ 1448 opset(AVSLB, r0) 1449 opset(AVSLH, r0) 1450 opset(AVSLW, r0) 1451 opset(AVSL, r0) 1452 opset(AVSLO, r0) 1453 opset(AVSRB, r0) 1454 opset(AVSRH, r0) 1455 opset(AVSRW, r0) 1456 opset(AVSR, r0) 1457 opset(AVSRO, r0) 1458 opset(AVSLD, r0) 1459 opset(AVSRD, r0) 1460 1461 case AVSA: /* vsrab, vsrah, vsraw, vsrad */ 1462 opset(AVSRAB, r0) 1463 opset(AVSRAH, r0) 1464 opset(AVSRAW, r0) 1465 opset(AVSRAD, r0) 1466 1467 case AVSOI: /* vsldoi */ 1468 opset(AVSLDOI, r0) 1469 1470 case AVCLZ: /* vclzb, vclzh, vclzw, vclzd */ 1471 opset(AVCLZB, r0) 1472 opset(AVCLZH, r0) 1473 opset(AVCLZW, r0) 1474 opset(AVCLZD, r0) 1475 1476 case AVPOPCNT: /* vpopcntb, vpopcnth, vpopcntw, vpopcntd */ 1477 opset(AVPOPCNTB, r0) 1478 opset(AVPOPCNTH, r0) 1479 opset(AVPOPCNTW, r0) 1480 opset(AVPOPCNTD, r0) 1481 1482 case AVCMPEQ: /* vcmpequb[.], vcmpequh[.], vcmpequw[.], vcmpequd[.] */ 1483 opset(AVCMPEQUB, r0) 1484 opset(AVCMPEQUBCC, r0) 1485 opset(AVCMPEQUH, r0) 1486 opset(AVCMPEQUHCC, r0) 1487 opset(AVCMPEQUW, r0) 1488 opset(AVCMPEQUWCC, r0) 1489 opset(AVCMPEQUD, r0) 1490 opset(AVCMPEQUDCC, r0) 1491 1492 case AVCMPGT: /* vcmpgt[u,s]b[.], vcmpgt[u,s]h[.], vcmpgt[u,s]w[.], vcmpgt[u,s]d[.] */ 1493 opset(AVCMPGTUB, r0) 1494 opset(AVCMPGTUBCC, r0) 1495 opset(AVCMPGTUH, r0) 1496 opset(AVCMPGTUHCC, r0) 1497 opset(AVCMPGTUW, r0) 1498 opset(AVCMPGTUWCC, r0) 1499 opset(AVCMPGTUD, r0) 1500 opset(AVCMPGTUDCC, r0) 1501 opset(AVCMPGTSB, r0) 1502 opset(AVCMPGTSBCC, r0) 1503 opset(AVCMPGTSH, r0) 1504 opset(AVCMPGTSHCC, r0) 1505 opset(AVCMPGTSW, r0) 1506 opset(AVCMPGTSWCC, r0) 1507 opset(AVCMPGTSD, r0) 1508 opset(AVCMPGTSDCC, r0) 1509 1510 case AVCMPNEZB: /* vcmpnezb[.] */ 1511 opset(AVCMPNEZBCC, r0) 1512 1513 case AVPERM: /* vperm */ 1514 opset(AVPERMXOR, r0) 1515 1516 case AVBPERMQ: /* vbpermq, vbpermd */ 1517 opset(AVBPERMD, r0) 1518 1519 case AVSEL: /* vsel */ 1520 opset(AVSEL, r0) 1521 1522 case AVSPLT: /* vspltb, vsplth, vspltw */ 1523 opset(AVSPLTB, r0) 1524 opset(AVSPLTH, r0) 1525 opset(AVSPLTW, r0) 1526 1527 case AVSPLTI: /* vspltisb, vspltish, vspltisw */ 1528 opset(AVSPLTISB, r0) 1529 opset(AVSPLTISH, r0) 1530 opset(AVSPLTISW, r0) 1531 1532 case AVCIPH: /* vcipher, vcipherlast */ 1533 opset(AVCIPHER, r0) 1534 opset(AVCIPHERLAST, r0) 1535 1536 case AVNCIPH: /* vncipher, vncipherlast */ 1537 opset(AVNCIPHER, r0) 1538 opset(AVNCIPHERLAST, r0) 1539 1540 case AVSBOX: /* vsbox */ 1541 opset(AVSBOX, r0) 1542 1543 case AVSHASIGMA: /* vshasigmaw, vshasigmad */ 1544 opset(AVSHASIGMAW, r0) 1545 opset(AVSHASIGMAD, r0) 1546 1547 case ALXVD2X: /* lxvd2x, lxvdsx, lxvw4x, lxvh8x, lxvb16x */ 1548 opset(ALXVDSX, r0) 1549 opset(ALXVW4X, r0) 1550 opset(ALXVH8X, r0) 1551 opset(ALXVB16X, r0) 1552 1553 case ALXV: /* lxv */ 1554 opset(ALXV, r0) 1555 1556 case ASTXVD2X: /* stxvd2x, stxvdsx, stxvw4x, stxvh8x, stxvb16x */ 1557 opset(ASTXVW4X, r0) 1558 opset(ASTXVH8X, r0) 1559 opset(ASTXVB16X, r0) 1560 1561 case ASTXV: /* stxv */ 1562 opset(ASTXV, r0) 1563 1564 case ALXS: /* lxsdx */ 1565 opset(ALXSDX, r0) 1566 1567 case ASTXS: /* stxsdx */ 1568 opset(ASTXSDX, r0) 1569 1570 case ALXSI: /* lxsiwax, lxsiwzx */ 1571 opset(ALXSIWAX, r0) 1572 opset(ALXSIWZX, r0) 1573 1574 case ASTXSI: /* stxsiwx */ 1575 opset(ASTXSIWX, r0) 1576 1577 case AMFVSR: /* mfvsrd, mfvsrwz (and extended mnemonics), mfvsrld */ 1578 opset(AMFVSRD, r0) 1579 opset(AMFFPRD, r0) 1580 opset(AMFVRD, r0) 1581 opset(AMFVSRWZ, r0) 1582 opset(AMFVSRLD, r0) 1583 1584 case AMTVSR: /* mtvsrd, mtvsrwa, mtvsrwz (and extended mnemonics), mtvsrdd, mtvsrws */ 1585 opset(AMTVSRD, r0) 1586 opset(AMTFPRD, r0) 1587 opset(AMTVRD, r0) 1588 opset(AMTVSRWA, r0) 1589 opset(AMTVSRWZ, r0) 1590 opset(AMTVSRDD, r0) 1591 opset(AMTVSRWS, r0) 1592 1593 case AXXLAND: /* xxland, xxlandc, xxleqv, xxlnand */ 1594 opset(AXXLANDQ, r0) 1595 opset(AXXLANDC, r0) 1596 opset(AXXLEQV, r0) 1597 opset(AXXLNAND, r0) 1598 1599 case AXXLOR: /* xxlorc, xxlnor, xxlor, xxlxor */ 1600 opset(AXXLORC, r0) 1601 opset(AXXLNOR, r0) 1602 opset(AXXLORQ, r0) 1603 opset(AXXLXOR, r0) 1604 1605 case AXXSEL: /* xxsel */ 1606 opset(AXXSEL, r0) 1607 1608 case AXXMRG: /* xxmrghw, xxmrglw */ 1609 opset(AXXMRGHW, r0) 1610 opset(AXXMRGLW, r0) 1611 1612 case AXXSPLT: /* xxspltw */ 1613 opset(AXXSPLTW, r0) 1614 1615 case AXXPERM: /* xxpermdi */ 1616 opset(AXXPERMDI, r0) 1617 1618 case AXXSI: /* xxsldwi */ 1619 opset(AXXSLDWI, r0) 1620 1621 case AXSCV: /* xscvdpsp, xscvspdp, xscvdpspn, xscvspdpn */ 1622 opset(AXSCVDPSP, r0) 1623 opset(AXSCVSPDP, r0) 1624 opset(AXSCVDPSPN, r0) 1625 opset(AXSCVSPDPN, r0) 1626 1627 case AXVCV: /* xvcvdpsp, xvcvspdp */ 1628 opset(AXVCVDPSP, r0) 1629 opset(AXVCVSPDP, r0) 1630 1631 case AXSCVX: /* xscvdpsxds, xscvdpsxws, xscvdpuxds, xscvdpuxws */ 1632 opset(AXSCVDPSXDS, r0) 1633 opset(AXSCVDPSXWS, r0) 1634 opset(AXSCVDPUXDS, r0) 1635 opset(AXSCVDPUXWS, r0) 1636 1637 case AXSCVXP: /* xscvsxddp, xscvuxddp, xscvsxdsp, xscvuxdsp */ 1638 opset(AXSCVSXDDP, r0) 1639 opset(AXSCVUXDDP, r0) 1640 opset(AXSCVSXDSP, r0) 1641 opset(AXSCVUXDSP, r0) 1642 1643 case AXVCVX: /* xvcvdpsxds, xvcvdpsxws, xvcvdpuxds, xvcvdpuxws, xvcvspsxds, xvcvspsxws, xvcvspuxds, xvcvspuxws */ 1644 opset(AXVCVDPSXDS, r0) 1645 opset(AXVCVDPSXWS, r0) 1646 opset(AXVCVDPUXDS, r0) 1647 opset(AXVCVDPUXWS, r0) 1648 opset(AXVCVSPSXDS, r0) 1649 opset(AXVCVSPSXWS, r0) 1650 opset(AXVCVSPUXDS, r0) 1651 opset(AXVCVSPUXWS, r0) 1652 1653 case AXVCVXP: /* xvcvsxddp, xvcvsxwdp, xvcvuxddp, xvcvuxwdp, xvcvsxdsp, xvcvsxwsp, xvcvuxdsp, xvcvuxwsp */ 1654 opset(AXVCVSXDDP, r0) 1655 opset(AXVCVSXWDP, r0) 1656 opset(AXVCVUXDDP, r0) 1657 opset(AXVCVUXWDP, r0) 1658 opset(AXVCVSXDSP, r0) 1659 opset(AXVCVSXWSP, r0) 1660 opset(AXVCVUXDSP, r0) 1661 opset(AXVCVUXWSP, r0) 1662 1663 case AAND: /* logical op Rb,Rs,Ra; no literal */ 1664 opset(AANDN, r0) 1665 opset(AANDNCC, r0) 1666 opset(AEQV, r0) 1667 opset(AEQVCC, r0) 1668 opset(ANAND, r0) 1669 opset(ANANDCC, r0) 1670 opset(ANOR, r0) 1671 opset(ANORCC, r0) 1672 opset(AORCC, r0) 1673 opset(AORN, r0) 1674 opset(AORNCC, r0) 1675 opset(AXORCC, r0) 1676 1677 case AADDME: /* op Ra, Rd */ 1678 opset(AADDMECC, r0) 1679 1680 opset(AADDMEV, r0) 1681 opset(AADDMEVCC, r0) 1682 opset(AADDZE, r0) 1683 opset(AADDZECC, r0) 1684 opset(AADDZEV, r0) 1685 opset(AADDZEVCC, r0) 1686 opset(ASUBME, r0) 1687 opset(ASUBMECC, r0) 1688 opset(ASUBMEV, r0) 1689 opset(ASUBMEVCC, r0) 1690 opset(ASUBZE, r0) 1691 opset(ASUBZECC, r0) 1692 opset(ASUBZEV, r0) 1693 opset(ASUBZEVCC, r0) 1694 1695 case AADDC: 1696 opset(AADDCCC, r0) 1697 1698 case ABEQ: 1699 opset(ABGE, r0) 1700 opset(ABGT, r0) 1701 opset(ABLE, r0) 1702 opset(ABLT, r0) 1703 opset(ABNE, r0) 1704 opset(ABVC, r0) 1705 opset(ABVS, r0) 1706 1707 case ABR: 1708 opset(ABL, r0) 1709 1710 case ABC: 1711 opset(ABCL, r0) 1712 1713 case AEXTSB: /* op Rs, Ra */ 1714 opset(AEXTSBCC, r0) 1715 1716 opset(AEXTSH, r0) 1717 opset(AEXTSHCC, r0) 1718 opset(ACNTLZW, r0) 1719 opset(ACNTLZWCC, r0) 1720 opset(ACNTLZD, r0) 1721 opset(AEXTSW, r0) 1722 opset(AEXTSWCC, r0) 1723 opset(ACNTLZDCC, r0) 1724 1725 case AFABS: /* fop [s,]d */ 1726 opset(AFABSCC, r0) 1727 1728 opset(AFNABS, r0) 1729 opset(AFNABSCC, r0) 1730 opset(AFNEG, r0) 1731 opset(AFNEGCC, r0) 1732 opset(AFRSP, r0) 1733 opset(AFRSPCC, r0) 1734 opset(AFCTIW, r0) 1735 opset(AFCTIWCC, r0) 1736 opset(AFCTIWZ, r0) 1737 opset(AFCTIWZCC, r0) 1738 opset(AFCTID, r0) 1739 opset(AFCTIDCC, r0) 1740 opset(AFCTIDZ, r0) 1741 opset(AFCTIDZCC, r0) 1742 opset(AFCFID, r0) 1743 opset(AFCFIDCC, r0) 1744 opset(AFCFIDU, r0) 1745 opset(AFCFIDUCC, r0) 1746 opset(AFCFIDS, r0) 1747 opset(AFCFIDSCC, r0) 1748 opset(AFRES, r0) 1749 opset(AFRESCC, r0) 1750 opset(AFRIM, r0) 1751 opset(AFRIMCC, r0) 1752 opset(AFRIP, r0) 1753 opset(AFRIPCC, r0) 1754 opset(AFRIZ, r0) 1755 opset(AFRIZCC, r0) 1756 opset(AFRIN, r0) 1757 opset(AFRINCC, r0) 1758 opset(AFRSQRTE, r0) 1759 opset(AFRSQRTECC, r0) 1760 opset(AFSQRT, r0) 1761 opset(AFSQRTCC, r0) 1762 opset(AFSQRTS, r0) 1763 opset(AFSQRTSCC, r0) 1764 1765 case AFADD: 1766 opset(AFADDS, r0) 1767 opset(AFADDCC, r0) 1768 opset(AFADDSCC, r0) 1769 opset(AFCPSGN, r0) 1770 opset(AFCPSGNCC, r0) 1771 opset(AFDIV, r0) 1772 opset(AFDIVS, r0) 1773 opset(AFDIVCC, r0) 1774 opset(AFDIVSCC, r0) 1775 opset(AFSUB, r0) 1776 opset(AFSUBS, r0) 1777 opset(AFSUBCC, r0) 1778 opset(AFSUBSCC, r0) 1779 1780 case AFMADD: 1781 opset(AFMADDCC, r0) 1782 opset(AFMADDS, r0) 1783 opset(AFMADDSCC, r0) 1784 opset(AFMSUB, r0) 1785 opset(AFMSUBCC, r0) 1786 opset(AFMSUBS, r0) 1787 opset(AFMSUBSCC, r0) 1788 opset(AFNMADD, r0) 1789 opset(AFNMADDCC, r0) 1790 opset(AFNMADDS, r0) 1791 opset(AFNMADDSCC, r0) 1792 opset(AFNMSUB, r0) 1793 opset(AFNMSUBCC, r0) 1794 opset(AFNMSUBS, r0) 1795 opset(AFNMSUBSCC, r0) 1796 opset(AFSEL, r0) 1797 opset(AFSELCC, r0) 1798 1799 case AFMUL: 1800 opset(AFMULS, r0) 1801 opset(AFMULCC, r0) 1802 opset(AFMULSCC, r0) 1803 1804 case AFCMPO: 1805 opset(AFCMPU, r0) 1806 1807 case AISEL: 1808 opset(AISEL, r0) 1809 1810 case AMTFSB0: 1811 opset(AMTFSB0CC, r0) 1812 opset(AMTFSB1, r0) 1813 opset(AMTFSB1CC, r0) 1814 1815 case ANEG: /* op [Ra,] Rd */ 1816 opset(ANEGCC, r0) 1817 1818 opset(ANEGV, r0) 1819 opset(ANEGVCC, r0) 1820 1821 case AOR: /* or/xor Rb,Rs,Ra; ori/xori $uimm,Rs,R */ 1822 opset(AXOR, r0) 1823 1824 case AORIS: /* oris/xoris $uimm,Rs,Ra */ 1825 opset(AXORIS, r0) 1826 1827 case ASLW: 1828 opset(ASLWCC, r0) 1829 opset(ASRW, r0) 1830 opset(ASRWCC, r0) 1831 opset(AROTLW, r0) 1832 1833 case ASLD: 1834 opset(ASLDCC, r0) 1835 opset(ASRD, r0) 1836 opset(ASRDCC, r0) 1837 opset(AROTL, r0) 1838 1839 case ASRAW: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1840 opset(ASRAWCC, r0) 1841 1842 case ASRAD: /* sraw Rb,Rs,Ra; srawi sh,Rs,Ra */ 1843 opset(ASRADCC, r0) 1844 1845 case ASUB: /* SUB Ra,Rb,Rd => subf Rd,ra,rb */ 1846 opset(ASUB, r0) 1847 1848 opset(ASUBCC, r0) 1849 opset(ASUBV, r0) 1850 opset(ASUBVCC, r0) 1851 opset(ASUBCCC, r0) 1852 opset(ASUBCV, r0) 1853 opset(ASUBCVCC, r0) 1854 opset(ASUBE, r0) 1855 opset(ASUBECC, r0) 1856 opset(ASUBEV, r0) 1857 opset(ASUBEVCC, r0) 1858 1859 case ASYNC: 1860 opset(AISYNC, r0) 1861 opset(ALWSYNC, r0) 1862 opset(APTESYNC, r0) 1863 opset(ATLBSYNC, r0) 1864 1865 case ARLWMI: 1866 opset(ARLWMICC, r0) 1867 opset(ARLWNM, r0) 1868 opset(ARLWNMCC, r0) 1869 1870 case ARLDMI: 1871 opset(ARLDMICC, r0) 1872 opset(ARLDIMI, r0) 1873 opset(ARLDIMICC, r0) 1874 1875 case ARLDC: 1876 opset(ARLDCCC, r0) 1877 1878 case ARLDCL: 1879 opset(ARLDCR, r0) 1880 opset(ARLDCLCC, r0) 1881 opset(ARLDCRCC, r0) 1882 1883 case ARLDICL: 1884 opset(ARLDICLCC, r0) 1885 opset(ARLDICR, r0) 1886 opset(ARLDICRCC, r0) 1887 1888 case AFMOVD: 1889 opset(AFMOVDCC, r0) 1890 opset(AFMOVDU, r0) 1891 opset(AFMOVS, r0) 1892 opset(AFMOVSU, r0) 1893 1894 case ALDAR: 1895 opset(ALBAR, r0) 1896 opset(ALHAR, r0) 1897 opset(ALWAR, r0) 1898 1899 case ASYSCALL: /* just the op; flow of control */ 1900 opset(ARFI, r0) 1901 1902 opset(ARFCI, r0) 1903 opset(ARFID, r0) 1904 opset(AHRFID, r0) 1905 1906 case AMOVHBR: 1907 opset(AMOVWBR, r0) 1908 opset(AMOVDBR, r0) 1909 1910 case ASLBMFEE: 1911 opset(ASLBMFEV, r0) 1912 1913 case ATW: 1914 opset(ATD, r0) 1915 1916 case ATLBIE: 1917 opset(ASLBIE, r0) 1918 opset(ATLBIEL, r0) 1919 1920 case AEIEIO: 1921 opset(ASLBIA, r0) 1922 1923 case ACMP: 1924 opset(ACMPW, r0) 1925 1926 case ACMPU: 1927 opset(ACMPWU, r0) 1928 1929 case ACMPB: 1930 opset(ACMPB, r0) 1931 1932 case AFTDIV: 1933 opset(AFTDIV, r0) 1934 1935 case AFTSQRT: 1936 opset(AFTSQRT, r0) 1937 1938 case AADD, 1939 AADDIS, 1940 AANDCC, /* and. Rb,Rs,Ra; andi. $uimm,Rs,Ra */ 1941 AANDISCC, 1942 AFMOVSX, 1943 AFMOVSZ, 1944 ALSW, 1945 AMOVW, 1946 /* load/store/move word with sign extension; special 32-bit move; move 32-bit literals */ 1947 AMOVWZ, /* load/store/move word with zero extension; move 32-bit literals */ 1948 AMOVD, /* load/store/move 64-bit values, including 32-bit literals with/without sign-extension */ 1949 AMOVB, /* macro: move byte with sign extension */ 1950 AMOVBU, /* macro: move byte with sign extension & update */ 1951 AMOVFL, 1952 AMULLW, 1953 /* op $s[,r2],r3; op r1[,r2],r3; no cc/v */ 1954 ASUBC, /* op r1,$s,r3; op r1[,r2],r3 */ 1955 ASTSW, 1956 ASLBMTE, 1957 AWORD, 1958 ADWORD, 1959 ADARN, 1960 ALDMX, 1961 AVMSUMUDM, 1962 AADDEX, 1963 ACMPEQB, 1964 AECIWX, 1965 obj.ANOP, 1966 obj.ATEXT, 1967 obj.AUNDEF, 1968 obj.AFUNCDATA, 1969 obj.APCALIGN, 1970 obj.APCDATA, 1971 obj.ADUFFZERO, 1972 obj.ADUFFCOPY: 1973 break 1974 } 1975 } 1976} 1977 1978func OPVXX1(o uint32, xo uint32, oe uint32) uint32 { 1979 return o<<26 | xo<<1 | oe<<11 1980} 1981 1982func OPVXX2(o uint32, xo uint32, oe uint32) uint32 { 1983 return o<<26 | xo<<2 | oe<<11 1984} 1985 1986func OPVXX3(o uint32, xo uint32, oe uint32) uint32 { 1987 return o<<26 | xo<<3 | oe<<11 1988} 1989 1990func OPVXX4(o uint32, xo uint32, oe uint32) uint32 { 1991 return o<<26 | xo<<4 | oe<<11 1992} 1993 1994func OPDQ(o uint32, xo uint32, oe uint32) uint32 { 1995 return o<<26 | xo | oe<<4 1996} 1997 1998func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 1999 return o<<26 | xo | oe<<11 | rc&1 2000} 2001 2002func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 2003 return o<<26 | xo | oe<<11 | (rc&1)<<10 2004} 2005 2006func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 { 2007 return o<<26 | xo<<1 | oe<<10 | rc&1 2008} 2009 2010func OPCC(o uint32, xo uint32, rc uint32) uint32 { 2011 return OPVCC(o, xo, 0, rc) 2012} 2013 2014func OP(o uint32, xo uint32) uint32 { 2015 return OPVCC(o, xo, 0, 0) 2016} 2017 2018/* the order is dest, a/s, b/imm for both arithmetic and logical operations */ 2019func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 { 2020 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 2021} 2022 2023/* VX-form 2-register operands, r/none/r */ 2024func AOP_RR(op uint32, d uint32, a uint32) uint32 { 2025 return op | (d&31)<<21 | (a&31)<<11 2026} 2027 2028/* VA-form 4-register operands */ 2029func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 2030 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6 2031} 2032 2033func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 2034 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF 2035} 2036 2037/* VX-form 2-register + UIM operands */ 2038func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 { 2039 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11 2040} 2041 2042/* VX-form 2-register + ST + SIX operands */ 2043func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 { 2044 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11 2045} 2046 2047/* VA-form 3-register + SHB operands */ 2048func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 { 2049 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6 2050} 2051 2052/* VX-form 1-register + SIM operands */ 2053func AOP_IR(op uint32, d uint32, simm uint32) uint32 { 2054 return op | (d&31)<<21 | (simm&31)<<16 2055} 2056 2057/* XX1-form 3-register operands, 1 VSR operand */ 2058func AOP_XX1(op uint32, d uint32, a uint32, b uint32) uint32 { 2059 /* For the XX-form encodings, we need the VSX register number to be exactly */ 2060 /* between 0-63, so we can properly set the rightmost bits. */ 2061 r := d - REG_VS0 2062 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5 2063} 2064 2065/* XX2-form 3-register operands, 2 VSR operands */ 2066func AOP_XX2(op uint32, d uint32, a uint32, b uint32) uint32 { 2067 xt := d - REG_VS0 2068 xb := b - REG_VS0 2069 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5 2070} 2071 2072/* XX3-form 3 VSR operands */ 2073func AOP_XX3(op uint32, d uint32, a uint32, b uint32) uint32 { 2074 xt := d - REG_VS0 2075 xa := a - REG_VS0 2076 xb := b - REG_VS0 2077 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 2078} 2079 2080/* XX3-form 3 VSR operands + immediate */ 2081func AOP_XX3I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 2082 xt := d - REG_VS0 2083 xa := a - REG_VS0 2084 xb := b - REG_VS0 2085 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 2086} 2087 2088/* XX4-form, 4 VSR operands */ 2089func AOP_XX4(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 2090 xt := d - REG_VS0 2091 xa := a - REG_VS0 2092 xb := b - REG_VS0 2093 xc := c - REG_VS0 2094 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5 2095} 2096 2097/* DQ-form, VSR register, register + offset operands */ 2098func AOP_DQ(op uint32, d uint32, a uint32, b uint32) uint32 { 2099 /* For the DQ-form encodings, we need the VSX register number to be exactly */ 2100 /* between 0-63, so we can properly set the SX bit. */ 2101 r := d - REG_VS0 2102 /* The EA for this instruction form is (RA) + DQ << 4, where DQ is a 12-bit signed integer. */ 2103 /* In order to match the output of the GNU objdump (and make the usage in Go asm easier), the */ 2104 /* instruction is called using the sign extended value (i.e. a valid offset would be -32752 or 32752, */ 2105 /* not -2047 or 2047), so 'b' needs to be adjusted to the expected 12-bit DQ value. Bear in mind that */ 2106 /* bits 0 to 3 in 'dq' need to be zero, otherwise this will generate an illegal instruction. */ 2107 /* If in doubt how this instruction form is encoded, refer to ISA 3.0b, pages 492 and 507. */ 2108 dq := b >> 4 2109 return op | (r&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (r&32)>>2 2110} 2111 2112/* Z23-form, 3-register operands + CY field */ 2113func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 2114 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<7 2115} 2116 2117/* X-form, 3-register operands + EH field */ 2118func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 { 2119 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1) 2120} 2121 2122func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 { 2123 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11 2124} 2125 2126func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 { 2127 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF 2128} 2129 2130func OP_BR(op uint32, li uint32, aa uint32) uint32 { 2131 return op | li&0x03FFFFFC | aa<<1 2132} 2133 2134func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 { 2135 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1 2136} 2137 2138func OP_BCR(op uint32, bo uint32, bi uint32) uint32 { 2139 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 2140} 2141 2142func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 { 2143 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1 2144} 2145 2146func AOP_RLDIC(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 { 2147 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5 2148} 2149 2150func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 { 2151 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6 2152} 2153 2154const ( 2155 /* each rhs is OPVCC(_, _, _, _) */ 2156 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0 2157 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0 2158 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0 2159 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0 2160 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0 2161 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0 2162 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0 2163 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0 2164 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0 2165 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0 2166 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0 2167 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0 2168 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0 2169 OP_MFMSR = 31<<26 | 83<<1 | 0<<10 | 0 2170 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0 2171 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0 2172 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0 2173 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0 2174 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0 2175 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0 2176 OP_MTMSR = 31<<26 | 146<<1 | 0<<10 | 0 2177 OP_MTMSRD = 31<<26 | 178<<1 | 0<<10 | 0 2178 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0 2179 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0 2180 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0 2181 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0 2182 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0 2183 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0 2184 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0 2185 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0 2186 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0 2187 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0 2188 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0 2189 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0 2190 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0 2191 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0 2192 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0 2193) 2194 2195func oclass(a *obj.Addr) int { 2196 return int(a.Class) - 1 2197} 2198 2199const ( 2200 D_FORM = iota 2201 DS_FORM 2202) 2203 2204// This function determines when a non-indexed load or store is D or 2205// DS form for use in finding the size of the offset field in the instruction. 2206// The size is needed when setting the offset value in the instruction 2207// and when generating relocation for that field. 2208// DS form instructions include: ld, ldu, lwa, std, stdu. All other 2209// loads and stores with an offset field are D form. This function should 2210// only be called with the same opcodes as are handled by opstore and opload. 2211func (c *ctxt9) opform(insn uint32) int { 2212 switch insn { 2213 default: 2214 c.ctxt.Diag("bad insn in loadform: %x", insn) 2215 case OPVCC(58, 0, 0, 0), // ld 2216 OPVCC(58, 0, 0, 1), // ldu 2217 OPVCC(58, 0, 0, 0) | 1<<1, // lwa 2218 OPVCC(62, 0, 0, 0), // std 2219 OPVCC(62, 0, 0, 1): //stdu 2220 return DS_FORM 2221 case OP_ADDI, // add 2222 OPVCC(32, 0, 0, 0), // lwz 2223 OPVCC(33, 0, 0, 0), // lwzu 2224 OPVCC(34, 0, 0, 0), // lbz 2225 OPVCC(35, 0, 0, 0), // lbzu 2226 OPVCC(40, 0, 0, 0), // lhz 2227 OPVCC(41, 0, 0, 0), // lhzu 2228 OPVCC(42, 0, 0, 0), // lha 2229 OPVCC(43, 0, 0, 0), // lhau 2230 OPVCC(46, 0, 0, 0), // lmw 2231 OPVCC(48, 0, 0, 0), // lfs 2232 OPVCC(49, 0, 0, 0), // lfsu 2233 OPVCC(50, 0, 0, 0), // lfd 2234 OPVCC(51, 0, 0, 0), // lfdu 2235 OPVCC(36, 0, 0, 0), // stw 2236 OPVCC(37, 0, 0, 0), // stwu 2237 OPVCC(38, 0, 0, 0), // stb 2238 OPVCC(39, 0, 0, 0), // stbu 2239 OPVCC(44, 0, 0, 0), // sth 2240 OPVCC(45, 0, 0, 0), // sthu 2241 OPVCC(47, 0, 0, 0), // stmw 2242 OPVCC(52, 0, 0, 0), // stfs 2243 OPVCC(53, 0, 0, 0), // stfsu 2244 OPVCC(54, 0, 0, 0), // stfd 2245 OPVCC(55, 0, 0, 0): // stfdu 2246 return D_FORM 2247 } 2248 return 0 2249} 2250 2251// Encode instructions and create relocation for accessing s+d according to the 2252// instruction op with source or destination (as appropriate) register reg. 2253func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32) (o1, o2 uint32) { 2254 if c.ctxt.Headtype == objabi.Haix { 2255 // Every symbol access must be made via a TOC anchor. 2256 c.ctxt.Diag("symbolAccess called for %s", s.Name) 2257 } 2258 var base uint32 2259 form := c.opform(op) 2260 if c.ctxt.Flag_shared { 2261 base = REG_R2 2262 } else { 2263 base = REG_R0 2264 } 2265 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0) 2266 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0) 2267 rel := obj.Addrel(c.cursym) 2268 rel.Off = int32(c.pc) 2269 rel.Siz = 8 2270 rel.Sym = s 2271 rel.Add = d 2272 if c.ctxt.Flag_shared { 2273 switch form { 2274 case D_FORM: 2275 rel.Type = objabi.R_ADDRPOWER_TOCREL 2276 case DS_FORM: 2277 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 2278 } 2279 2280 } else { 2281 switch form { 2282 case D_FORM: 2283 rel.Type = objabi.R_ADDRPOWER 2284 case DS_FORM: 2285 rel.Type = objabi.R_ADDRPOWER_DS 2286 } 2287 } 2288 return 2289} 2290 2291/* 2292 * 32-bit masks 2293 */ 2294func getmask(m []byte, v uint32) bool { 2295 m[1] = 0 2296 m[0] = m[1] 2297 if v != ^uint32(0) && v&(1<<31) != 0 && v&1 != 0 { /* MB > ME */ 2298 if getmask(m, ^v) { 2299 i := int(m[0]) 2300 m[0] = m[1] + 1 2301 m[1] = byte(i - 1) 2302 return true 2303 } 2304 2305 return false 2306 } 2307 2308 for i := 0; i < 32; i++ { 2309 if v&(1<<uint(31-i)) != 0 { 2310 m[0] = byte(i) 2311 for { 2312 m[1] = byte(i) 2313 i++ 2314 if i >= 32 || v&(1<<uint(31-i)) == 0 { 2315 break 2316 } 2317 } 2318 2319 for ; i < 32; i++ { 2320 if v&(1<<uint(31-i)) != 0 { 2321 return false 2322 } 2323 } 2324 return true 2325 } 2326 } 2327 2328 return false 2329} 2330 2331func (c *ctxt9) maskgen(p *obj.Prog, m []byte, v uint32) { 2332 if !getmask(m, v) { 2333 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2334 } 2335} 2336 2337/* 2338 * 64-bit masks (rldic etc) 2339 */ 2340func getmask64(m []byte, v uint64) bool { 2341 m[1] = 0 2342 m[0] = m[1] 2343 for i := 0; i < 64; i++ { 2344 if v&(uint64(1)<<uint(63-i)) != 0 { 2345 m[0] = byte(i) 2346 for { 2347 m[1] = byte(i) 2348 i++ 2349 if i >= 64 || v&(uint64(1)<<uint(63-i)) == 0 { 2350 break 2351 } 2352 } 2353 2354 for ; i < 64; i++ { 2355 if v&(uint64(1)<<uint(63-i)) != 0 { 2356 return false 2357 } 2358 } 2359 return true 2360 } 2361 } 2362 2363 return false 2364} 2365 2366func (c *ctxt9) maskgen64(p *obj.Prog, m []byte, v uint64) { 2367 if !getmask64(m, v) { 2368 c.ctxt.Diag("cannot generate mask #%x\n%v", v, p) 2369 } 2370} 2371 2372func loadu32(r int, d int64) uint32 { 2373 v := int32(d >> 16) 2374 if isuint32(uint64(d)) { 2375 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v)) 2376 } 2377 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v)) 2378} 2379 2380func high16adjusted(d int32) uint16 { 2381 if d&0x8000 != 0 { 2382 return uint16((d >> 16) + 1) 2383 } 2384 return uint16(d >> 16) 2385} 2386 2387func (c *ctxt9) asmout(p *obj.Prog, o *Optab, out []uint32) { 2388 o1 := uint32(0) 2389 o2 := uint32(0) 2390 o3 := uint32(0) 2391 o4 := uint32(0) 2392 o5 := uint32(0) 2393 2394 //print("%v => case %d\n", p, o->type); 2395 switch o.type_ { 2396 default: 2397 c.ctxt.Diag("unknown type %d", o.type_) 2398 prasm(p) 2399 2400 case 0: /* pseudo ops */ 2401 if p.As == obj.APCALIGN { 2402 aln := c.vregoff(&p.From) 2403 v := addpad(p.Pc, aln, c.ctxt) 2404 if v > 0 { 2405 for i := 0; i < 6; i++ { 2406 out[i] = uint32(0) 2407 } 2408 o.size = int8(v) 2409 out[0] = LOP_RRR(OP_OR, REGZERO, REGZERO, REGZERO) 2410 return 2411 } 2412 o.size = 0 2413 } 2414 break 2415 2416 case 1: /* mov r1,r2 ==> OR Rs,Rs,Ra */ 2417 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2418 v := c.regoff(&p.From) 2419 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2420 //nerrors--; 2421 c.ctxt.Diag("literal operation on R0\n%v", p) 2422 } 2423 2424 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2425 break 2426 } 2427 2428 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg)) 2429 2430 case 2: /* int/cr/fp op Rb,[Ra],Rd */ 2431 r := int(p.Reg) 2432 2433 if r == 0 { 2434 r = int(p.To.Reg) 2435 } 2436 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2437 2438 case 3: /* mov $soreg/addcon/andcon/ucon, r ==> addis/oris/addi/ori $i,reg',r */ 2439 d := c.vregoff(&p.From) 2440 2441 v := int32(d) 2442 r := int(p.From.Reg) 2443 if r == 0 { 2444 r = int(o.param) 2445 } 2446 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 && (r != 0 || v != 0) { 2447 c.ctxt.Diag("literal operation on R0\n%v", p) 2448 } 2449 a := OP_ADDI 2450 if o.a1 == C_UCON { 2451 if d&0xffff != 0 { 2452 log.Fatalf("invalid handling of %v", p) 2453 } 2454 // For UCON operands the value is right shifted 16, using ADDIS if the 2455 // value should be signed, ORIS if unsigned. 2456 v >>= 16 2457 if r == REGZERO && isuint32(uint64(d)) { 2458 o1 = LOP_IRR(OP_ORIS, uint32(p.To.Reg), REGZERO, uint32(v)) 2459 break 2460 } 2461 2462 a = OP_ADDIS 2463 } else if int64(int16(d)) != d { 2464 // Operand is 16 bit value with sign bit set 2465 if o.a1 == C_ANDCON { 2466 // Needs unsigned 16 bit so use ORI 2467 if r == 0 || r == REGZERO { 2468 o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v)) 2469 break 2470 } 2471 // With ADDCON, needs signed 16 bit value, fall through to use ADDI 2472 } else if o.a1 != C_ADDCON { 2473 log.Fatalf("invalid handling of %v", p) 2474 } 2475 } 2476 2477 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v)) 2478 2479 case 4: /* add/mul $scon,[r1],r2 */ 2480 v := c.regoff(&p.From) 2481 2482 r := int(p.Reg) 2483 if r == 0 { 2484 r = int(p.To.Reg) 2485 } 2486 if r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0 { 2487 c.ctxt.Diag("literal operation on R0\n%v", p) 2488 } 2489 if int32(int16(v)) != v { 2490 log.Fatalf("mishandled instruction %v", p) 2491 } 2492 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2493 2494 case 5: /* syscall */ 2495 o1 = c.oprrr(p.As) 2496 2497 case 6: /* logical op Rb,[Rs,]Ra; no literal */ 2498 r := int(p.Reg) 2499 2500 if r == 0 { 2501 r = int(p.To.Reg) 2502 } 2503 // AROTL and AROTLW are extended mnemonics, which map to RLDCL and RLWNM. 2504 switch p.As { 2505 case AROTL: 2506 o1 = AOP_RLDIC(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0)) 2507 case AROTLW: 2508 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31) 2509 default: 2510 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2511 } 2512 2513 case 7: /* mov r, soreg ==> stw o(r) */ 2514 r := int(p.To.Reg) 2515 2516 if r == 0 { 2517 r = int(o.param) 2518 } 2519 v := c.regoff(&p.To) 2520 if p.To.Type == obj.TYPE_MEM && p.To.Index != 0 { 2521 if v != 0 { 2522 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2523 } 2524 if c.ctxt.Flag_shared && r == REG_R13 { 2525 rel := obj.Addrel(c.cursym) 2526 rel.Off = int32(c.pc) 2527 rel.Siz = 4 2528 // This (and the matching part in the load case 2529 // below) are the only places in the ppc64 toolchain 2530 // that knows the name of the tls variable. Possibly 2531 // we could add some assembly syntax so that the name 2532 // of the variable does not have to be assumed. 2533 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2534 rel.Type = objabi.R_POWER_TLS 2535 } 2536 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r)) 2537 } else { 2538 if int32(int16(v)) != v { 2539 log.Fatalf("mishandled instruction %v", p) 2540 } 2541 // Offsets in DS form stores must be a multiple of 4 2542 inst := c.opstore(p.As) 2543 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2544 log.Fatalf("invalid offset for DS form load/store %v", p) 2545 } 2546 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v)) 2547 } 2548 2549 case 8: /* mov soreg, r ==> lbz/lhz/lwz o(r) */ 2550 r := int(p.From.Reg) 2551 2552 if r == 0 { 2553 r = int(o.param) 2554 } 2555 v := c.regoff(&p.From) 2556 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2557 if v != 0 { 2558 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2559 } 2560 if c.ctxt.Flag_shared && r == REG_R13 { 2561 rel := obj.Addrel(c.cursym) 2562 rel.Off = int32(c.pc) 2563 rel.Siz = 4 2564 rel.Sym = c.ctxt.Lookup("runtime.tls_g") 2565 rel.Type = objabi.R_POWER_TLS 2566 } 2567 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2568 } else { 2569 if int32(int16(v)) != v { 2570 log.Fatalf("mishandled instruction %v", p) 2571 } 2572 // Offsets in DS form loads must be a multiple of 4 2573 inst := c.opload(p.As) 2574 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 2575 log.Fatalf("invalid offset for DS form load/store %v", p) 2576 } 2577 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v)) 2578 } 2579 2580 case 9: /* movb soreg, r ==> lbz o(r),r2; extsb r2,r2 */ 2581 r := int(p.From.Reg) 2582 2583 if r == 0 { 2584 r = int(o.param) 2585 } 2586 v := c.regoff(&p.From) 2587 if p.From.Type == obj.TYPE_MEM && p.From.Index != 0 { 2588 if v != 0 { 2589 c.ctxt.Diag("illegal indexed instruction\n%v", p) 2590 } 2591 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r)) 2592 } else { 2593 o1 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2594 } 2595 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 2596 2597 case 10: /* sub Ra,[Rb],Rd => subf Rd,Ra,Rb */ 2598 r := int(p.Reg) 2599 2600 if r == 0 { 2601 r = int(p.To.Reg) 2602 } 2603 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r)) 2604 2605 case 11: /* br/bl lbra */ 2606 v := int32(0) 2607 2608 if p.Pcond != nil { 2609 v = int32(p.Pcond.Pc - p.Pc) 2610 if v&03 != 0 { 2611 c.ctxt.Diag("odd branch target address\n%v", p) 2612 v &^= 03 2613 } 2614 2615 if v < -(1<<25) || v >= 1<<24 { 2616 c.ctxt.Diag("branch too far\n%v", p) 2617 } 2618 } 2619 2620 o1 = OP_BR(c.opirr(p.As), uint32(v), 0) 2621 if p.To.Sym != nil { 2622 rel := obj.Addrel(c.cursym) 2623 rel.Off = int32(c.pc) 2624 rel.Siz = 4 2625 rel.Sym = p.To.Sym 2626 v += int32(p.To.Offset) 2627 if v&03 != 0 { 2628 c.ctxt.Diag("odd branch target address\n%v", p) 2629 v &^= 03 2630 } 2631 2632 rel.Add = int64(v) 2633 rel.Type = objabi.R_CALLPOWER 2634 } 2635 o2 = 0x60000000 // nop, sometimes overwritten by ld r2, 24(r1) when dynamic linking 2636 2637 case 12: /* movb r,r (extsb); movw r,r (extsw) */ 2638 if p.To.Reg == REGZERO && p.From.Type == obj.TYPE_CONST { 2639 v := c.regoff(&p.From) 2640 if r0iszero != 0 /*TypeKind(100016)*/ && v != 0 { 2641 c.ctxt.Diag("literal operation on R0\n%v", p) 2642 } 2643 2644 o1 = LOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(v)) 2645 break 2646 } 2647 2648 if p.As == AMOVW { 2649 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2650 } else { 2651 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2652 } 2653 2654 case 13: /* mov[bhw]z r,r; uses rlwinm not andi. to avoid changing CC */ 2655 if p.As == AMOVBZ { 2656 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31) 2657 } else if p.As == AMOVH { 2658 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0) 2659 } else if p.As == AMOVHZ { 2660 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31) 2661 } else if p.As == AMOVWZ { 2662 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5 /* MB=32 */ 2663 } else { 2664 c.ctxt.Diag("internal: bad mov[bhw]z\n%v", p) 2665 } 2666 2667 case 14: /* rldc[lr] Rb,Rs,$mask,Ra -- left, right give different masks */ 2668 r := int(p.Reg) 2669 2670 if r == 0 { 2671 r = int(p.To.Reg) 2672 } 2673 d := c.vregoff(p.GetFrom3()) 2674 var a int 2675 switch p.As { 2676 2677 // These opcodes expect a mask operand that has to be converted into the 2678 // appropriate operand. The way these were defined, not all valid masks are possible. 2679 // Left here for compatibility in case they were used or generated. 2680 case ARLDCL, ARLDCLCC: 2681 var mask [2]uint8 2682 c.maskgen64(p, mask[:], uint64(d)) 2683 2684 a = int(mask[0]) /* MB */ 2685 if mask[1] != 63 { 2686 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p) 2687 } 2688 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2689 o1 |= (uint32(a) & 31) << 6 2690 if a&0x20 != 0 { 2691 o1 |= 1 << 5 /* mb[5] is top bit */ 2692 } 2693 2694 case ARLDCR, ARLDCRCC: 2695 var mask [2]uint8 2696 c.maskgen64(p, mask[:], uint64(d)) 2697 2698 a = int(mask[1]) /* ME */ 2699 if mask[0] != 0 { 2700 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p) 2701 } 2702 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg)) 2703 o1 |= (uint32(a) & 31) << 6 2704 if a&0x20 != 0 { 2705 o1 |= 1 << 5 /* mb[5] is top bit */ 2706 } 2707 2708 // These opcodes use a shift count like the ppc64 asm, no mask conversion done 2709 case ARLDICR, ARLDICRCC: 2710 me := int(d) 2711 sh := c.regoff(&p.From) 2712 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(me)) 2713 2714 case ARLDICL, ARLDICLCC: 2715 mb := int(d) 2716 sh := c.regoff(&p.From) 2717 o1 = AOP_RLDIC(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(sh), uint32(mb)) 2718 2719 default: 2720 c.ctxt.Diag("unexpected op in rldc case\n%v", p) 2721 a = 0 2722 } 2723 2724 case 17, /* bc bo,bi,lbra (same for now) */ 2725 16: /* bc bo,bi,sbra */ 2726 a := 0 2727 2728 r := int(p.Reg) 2729 2730 if p.From.Type == obj.TYPE_CONST { 2731 a = int(c.regoff(&p.From)) 2732 } else if p.From.Type == obj.TYPE_REG { 2733 if r != 0 { 2734 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r) 2735 } 2736 // BI values for the CR 2737 switch p.From.Reg { 2738 case REG_CR0: 2739 r = BI_CR0 2740 case REG_CR1: 2741 r = BI_CR1 2742 case REG_CR2: 2743 r = BI_CR2 2744 case REG_CR3: 2745 r = BI_CR3 2746 case REG_CR4: 2747 r = BI_CR4 2748 case REG_CR5: 2749 r = BI_CR5 2750 case REG_CR6: 2751 r = BI_CR6 2752 case REG_CR7: 2753 r = BI_CR7 2754 default: 2755 c.ctxt.Diag("unrecognized register: expecting CR\n") 2756 } 2757 } 2758 v := int32(0) 2759 if p.Pcond != nil { 2760 v = int32(p.Pcond.Pc - p.Pc) 2761 } 2762 if v&03 != 0 { 2763 c.ctxt.Diag("odd branch target address\n%v", p) 2764 v &^= 03 2765 } 2766 2767 if v < -(1<<16) || v >= 1<<15 { 2768 c.ctxt.Diag("branch too far\n%v", p) 2769 } 2770 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0) 2771 2772 case 15: /* br/bl (r) => mov r,lr; br/bl (lr) */ 2773 var v int32 2774 if p.As == ABC || p.As == ABCL { 2775 v = c.regoff(&p.To) & 31 2776 } else { 2777 v = 20 /* unconditional */ 2778 } 2779 o1 = AOP_RRR(OP_MTSPR, uint32(p.To.Reg), 0, 0) | (REG_LR&0x1f)<<16 | ((REG_LR>>5)&0x1f)<<11 2780 o2 = OPVCC(19, 16, 0, 0) 2781 if p.As == ABL || p.As == ABCL { 2782 o2 |= 1 2783 } 2784 o2 = OP_BCR(o2, uint32(v), uint32(p.To.Index)) 2785 2786 case 18: /* br/bl (lr/ctr); bc/bcl bo,bi,(lr/ctr) */ 2787 var v int32 2788 if p.As == ABC || p.As == ABCL { 2789 v = c.regoff(&p.From) & 31 2790 } else { 2791 v = 20 /* unconditional */ 2792 } 2793 r := int(p.Reg) 2794 if r == 0 { 2795 r = 0 2796 } 2797 switch oclass(&p.To) { 2798 case C_CTR: 2799 o1 = OPVCC(19, 528, 0, 0) 2800 2801 case C_LR: 2802 o1 = OPVCC(19, 16, 0, 0) 2803 2804 default: 2805 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p) 2806 v = 0 2807 } 2808 2809 if p.As == ABL || p.As == ABCL { 2810 o1 |= 1 2811 } 2812 o1 = OP_BCR(o1, uint32(v), uint32(r)) 2813 2814 case 19: /* mov $lcon,r ==> cau+or */ 2815 d := c.vregoff(&p.From) 2816 2817 if p.From.Sym == nil { 2818 o1 = loadu32(int(p.To.Reg), d) 2819 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d))) 2820 } else { 2821 o1, o2 = c.symbolAccess(p.From.Sym, d, p.To.Reg, OP_ADDI) 2822 } 2823 2824 case 20: /* add $ucon,,r | addis $addcon,r,r */ 2825 v := c.regoff(&p.From) 2826 2827 r := int(p.Reg) 2828 if r == 0 { 2829 r = int(p.To.Reg) 2830 } 2831 if p.As == AADD && (r0iszero == 0 /*TypeKind(100016)*/ && p.Reg == 0 || r0iszero != 0 /*TypeKind(100016)*/ && p.To.Reg == 0) { 2832 c.ctxt.Diag("literal operation on R0\n%v", p) 2833 } 2834 if p.As == AADDIS { 2835 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2836 } else { 2837 o1 = AOP_IRR(c.opirr(AADDIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 2838 } 2839 2840 case 22: /* add $lcon/$andcon,r1,r2 ==> oris+ori+add/ori+add */ 2841 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2842 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2843 } 2844 d := c.vregoff(&p.From) 2845 r := int(p.Reg) 2846 if r == 0 { 2847 r = int(p.To.Reg) 2848 } 2849 if p.From.Sym != nil { 2850 c.ctxt.Diag("%v is not supported", p) 2851 } 2852 // If operand is ANDCON, generate 2 instructions using 2853 // ORI for unsigned value; with LCON 3 instructions. 2854 if o.size == 8 { 2855 o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d))) 2856 o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2857 } else { 2858 o1 = loadu32(REGTMP, d) 2859 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2860 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2861 } 2862 2863 case 23: /* and $lcon/$addcon,r1,r2 ==> oris+ori+and/addi+and */ 2864 if p.To.Reg == REGTMP || p.Reg == REGTMP { 2865 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2866 } 2867 d := c.vregoff(&p.From) 2868 r := int(p.Reg) 2869 if r == 0 { 2870 r = int(p.To.Reg) 2871 } 2872 2873 // With ADDCON operand, generate 2 instructions using ADDI for signed value, 2874 // with LCON operand generate 3 instructions. 2875 if o.size == 8 { 2876 o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d))) 2877 o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2878 } else { 2879 o1 = loadu32(REGTMP, d) 2880 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(int32(d))) 2881 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r)) 2882 } 2883 if p.From.Sym != nil { 2884 c.ctxt.Diag("%v is not supported", p) 2885 } 2886 2887 case 24: /* lfd fA,float64(0) -> xxlxor xsA,xsaA,xsaA + fneg for -0 */ 2888 o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0)) 2889 // This is needed for -0. 2890 if o.size == 8 { 2891 o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg)) 2892 } 2893 2894 case 25: 2895 /* sld[.] $sh,rS,rA -> rldicr[.] $sh,rS,mask(0,63-sh),rA; srd[.] -> rldicl */ 2896 v := c.regoff(&p.From) 2897 2898 if v < 0 { 2899 v = 0 2900 } else if v > 63 { 2901 v = 63 2902 } 2903 r := int(p.Reg) 2904 if r == 0 { 2905 r = int(p.To.Reg) 2906 } 2907 var a int 2908 op := uint32(0) 2909 switch p.As { 2910 case ASLD, ASLDCC: 2911 a = int(63 - v) 2912 op = OP_RLDICR 2913 2914 case ASRD, ASRDCC: 2915 a = int(v) 2916 v = 64 - v 2917 op = OP_RLDICL 2918 case AROTL: 2919 a = int(0) 2920 op = OP_RLDICL 2921 default: 2922 c.ctxt.Diag("unexpected op in sldi case\n%v", p) 2923 a = 0 2924 o1 = 0 2925 } 2926 2927 o1 = AOP_RLDIC(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a)) 2928 if p.As == ASLDCC || p.As == ASRDCC { 2929 o1 |= 1 // Set the condition code bit 2930 } 2931 2932 case 26: /* mov $lsext/auto/oreg,,r2 ==> addis+addi */ 2933 if p.To.Reg == REGTMP { 2934 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2935 } 2936 v := c.regoff(&p.From) 2937 r := int(p.From.Reg) 2938 if r == 0 { 2939 r = int(o.param) 2940 } 2941 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 2942 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGTMP, uint32(v)) 2943 2944 case 27: /* subc ra,$simm,rd => subfic rd,ra,$simm */ 2945 v := c.regoff(p.GetFrom3()) 2946 2947 r := int(p.From.Reg) 2948 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 2949 2950 case 28: /* subc r1,$lcon,r2 ==> cau+or+subfc */ 2951 if p.To.Reg == REGTMP || p.From.Reg == REGTMP { 2952 c.ctxt.Diag("can't synthesize large constant\n%v", p) 2953 } 2954 v := c.regoff(p.GetFrom3()) 2955 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16) 2956 o2 = LOP_IRR(OP_ORI, REGTMP, REGTMP, uint32(v)) 2957 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP) 2958 if p.From.Sym != nil { 2959 c.ctxt.Diag("%v is not supported", p) 2960 } 2961 2962 //if(dlm) reloc(&p->from3, p->pc, 0); 2963 2964 case 29: /* rldic[lr]? $sh,s,$mask,a -- left, right, plain give different masks */ 2965 v := c.regoff(&p.From) 2966 2967 d := c.vregoff(p.GetFrom3()) 2968 var mask [2]uint8 2969 c.maskgen64(p, mask[:], uint64(d)) 2970 var a int 2971 switch p.As { 2972 case ARLDC, ARLDCCC: 2973 a = int(mask[0]) /* MB */ 2974 if int32(mask[1]) != (63 - v) { 2975 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2976 } 2977 2978 case ARLDCL, ARLDCLCC: 2979 a = int(mask[0]) /* MB */ 2980 if mask[1] != 63 { 2981 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2982 } 2983 2984 case ARLDCR, ARLDCRCC: 2985 a = int(mask[1]) /* ME */ 2986 if mask[0] != 0 { 2987 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 2988 } 2989 2990 default: 2991 c.ctxt.Diag("unexpected op in rldic case\n%v", p) 2992 a = 0 2993 } 2994 2995 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 2996 o1 |= (uint32(a) & 31) << 6 2997 if v&0x20 != 0 { 2998 o1 |= 1 << 1 2999 } 3000 if a&0x20 != 0 { 3001 o1 |= 1 << 5 /* mb[5] is top bit */ 3002 } 3003 3004 case 30: /* rldimi $sh,s,$mask,a */ 3005 v := c.regoff(&p.From) 3006 3007 d := c.vregoff(p.GetFrom3()) 3008 3009 // Original opcodes had mask operands which had to be converted to a shift count as expected by 3010 // the ppc64 asm. 3011 switch p.As { 3012 case ARLDMI, ARLDMICC: 3013 var mask [2]uint8 3014 c.maskgen64(p, mask[:], uint64(d)) 3015 if int32(mask[1]) != (63 - v) { 3016 c.ctxt.Diag("invalid mask for shift: %x (shift %d)\n%v", uint64(d), v, p) 3017 } 3018 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 3019 o1 |= (uint32(mask[0]) & 31) << 6 3020 if v&0x20 != 0 { 3021 o1 |= 1 << 1 3022 } 3023 if mask[0]&0x20 != 0 { 3024 o1 |= 1 << 5 /* mb[5] is top bit */ 3025 } 3026 3027 // Opcodes with shift count operands. 3028 case ARLDIMI, ARLDIMICC: 3029 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), (uint32(v) & 0x1F)) 3030 o1 |= (uint32(d) & 31) << 6 3031 if d&0x20 != 0 { 3032 o1 |= 1 << 5 3033 } 3034 if v&0x20 != 0 { 3035 o1 |= 1 << 1 3036 } 3037 } 3038 3039 case 31: /* dword */ 3040 d := c.vregoff(&p.From) 3041 3042 if c.ctxt.Arch.ByteOrder == binary.BigEndian { 3043 o1 = uint32(d >> 32) 3044 o2 = uint32(d) 3045 } else { 3046 o1 = uint32(d) 3047 o2 = uint32(d >> 32) 3048 } 3049 3050 if p.From.Sym != nil { 3051 rel := obj.Addrel(c.cursym) 3052 rel.Off = int32(c.pc) 3053 rel.Siz = 8 3054 rel.Sym = p.From.Sym 3055 rel.Add = p.From.Offset 3056 rel.Type = objabi.R_ADDR 3057 o2 = 0 3058 o1 = o2 3059 } 3060 3061 case 32: /* fmul frc,fra,frd */ 3062 r := int(p.Reg) 3063 3064 if r == 0 { 3065 r = int(p.To.Reg) 3066 } 3067 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6 3068 3069 case 33: /* fabs [frb,]frd; fmr. frb,frd */ 3070 r := int(p.From.Reg) 3071 3072 if oclass(&p.From) == C_NONE { 3073 r = int(p.To.Reg) 3074 } 3075 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r)) 3076 3077 case 34: /* FMADDx fra,frb,frc,frt (t=a*c±b) */ 3078 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6 3079 3080 case 35: /* mov r,lext/lauto/loreg ==> cau $(v>>16),sb,r'; store o(r') */ 3081 v := c.regoff(&p.To) 3082 3083 r := int(p.To.Reg) 3084 if r == 0 { 3085 r = int(o.param) 3086 } 3087 // Offsets in DS form stores must be a multiple of 4 3088 inst := c.opstore(p.As) 3089 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3090 log.Fatalf("invalid offset for DS form load/store %v", p) 3091 } 3092 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 3093 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v)) 3094 3095 case 36: /* mov bz/h/hz lext/lauto/lreg,r ==> lbz/lha/lhz etc */ 3096 v := c.regoff(&p.From) 3097 3098 r := int(p.From.Reg) 3099 if r == 0 { 3100 r = int(o.param) 3101 } 3102 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 3103 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 3104 3105 case 37: /* movb lext/lauto/lreg,r ==> lbz o(reg),r; extsb r */ 3106 v := c.regoff(&p.From) 3107 3108 r := int(p.From.Reg) 3109 if r == 0 { 3110 r = int(o.param) 3111 } 3112 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v))) 3113 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), REGTMP, uint32(v)) 3114 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3115 3116 case 40: /* word */ 3117 o1 = uint32(c.regoff(&p.From)) 3118 3119 case 41: /* stswi */ 3120 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 3121 3122 case 42: /* lswi */ 3123 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11 3124 3125 case 43: /* data cache instructions: op (Ra+[Rb]), [th|l] */ 3126 /* TH field for dcbt/dcbtst: */ 3127 /* 0 = Block access - program will soon access EA. */ 3128 /* 8-15 = Stream access - sequence of access (data stream). See section 4.3.2 of the ISA for details. */ 3129 /* 16 = Block access - program will soon make a transient access to EA. */ 3130 /* 17 = Block access - program will not access EA for a long time. */ 3131 3132 /* L field for dcbf: */ 3133 /* 0 = invalidates the block containing EA in all processors. */ 3134 /* 1 = same as 0, but with limited scope (i.e. block in the current processor will not be reused soon). */ 3135 /* 3 = same as 1, but with even more limited scope (i.e. block in the current processor primary cache will not be reused soon). */ 3136 if p.To.Type == obj.TYPE_NONE { 3137 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg)) 3138 } else { 3139 th := c.regoff(&p.To) 3140 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg)) 3141 } 3142 3143 case 44: /* indexed store */ 3144 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3145 3146 case 45: /* indexed load */ 3147 switch p.As { 3148 /* The assembler accepts a 4-operand l*arx instruction. The fourth operand is an Exclusive Access Hint (EH) */ 3149 /* The EH field can be used as a lock acquire/release hint as follows: */ 3150 /* 0 = Atomic Update (fetch-and-operate or similar algorithm) */ 3151 /* 1 = Exclusive Access (lock acquire and release) */ 3152 case ALBAR, ALHAR, ALWAR, ALDAR: 3153 if p.From3Type() != obj.TYPE_NONE { 3154 eh := int(c.regoff(p.GetFrom3())) 3155 if eh > 1 { 3156 c.ctxt.Diag("illegal EH field\n%v", p) 3157 } 3158 o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh)) 3159 } else { 3160 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3161 } 3162 default: 3163 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3164 } 3165 case 46: /* plain op */ 3166 o1 = c.oprrr(p.As) 3167 3168 case 47: /* op Ra, Rd; also op [Ra,] Rd */ 3169 r := int(p.From.Reg) 3170 3171 if r == 0 { 3172 r = int(p.To.Reg) 3173 } 3174 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 3175 3176 case 48: /* op Rs, Ra */ 3177 r := int(p.From.Reg) 3178 3179 if r == 0 { 3180 r = int(p.To.Reg) 3181 } 3182 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) 3183 3184 case 49: /* op Rb; op $n, Rb */ 3185 if p.From.Type != obj.TYPE_REG { /* tlbie $L, rB */ 3186 v := c.regoff(&p.From) & 1 3187 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21 3188 } else { 3189 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg)) 3190 } 3191 3192 case 50: /* rem[u] r1[,r2],r3 */ 3193 r := int(p.Reg) 3194 3195 if r == 0 { 3196 r = int(p.To.Reg) 3197 } 3198 v := c.oprrr(p.As) 3199 t := v & (1<<10 | 1) /* OE|Rc */ 3200 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 3201 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg)) 3202 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 3203 if p.As == AREMU { 3204 o4 = o3 3205 3206 /* Clear top 32 bits */ 3207 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5 3208 } 3209 3210 case 51: /* remd[u] r1[,r2],r3 */ 3211 r := int(p.Reg) 3212 3213 if r == 0 { 3214 r = int(p.To.Reg) 3215 } 3216 v := c.oprrr(p.As) 3217 t := v & (1<<10 | 1) /* OE|Rc */ 3218 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg)) 3219 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg)) 3220 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r)) 3221 3222 case 52: /* mtfsbNx cr(n) */ 3223 v := c.regoff(&p.From) & 31 3224 3225 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0) 3226 3227 case 53: /* mffsX ,fr1 */ 3228 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0) 3229 3230 case 54: /* mov msr,r1; mov r1, msr*/ 3231 if oclass(&p.From) == C_REG { 3232 if p.As == AMOVD { 3233 o1 = AOP_RRR(OP_MTMSRD, uint32(p.From.Reg), 0, 0) 3234 } else { 3235 o1 = AOP_RRR(OP_MTMSR, uint32(p.From.Reg), 0, 0) 3236 } 3237 } else { 3238 o1 = AOP_RRR(OP_MFMSR, uint32(p.To.Reg), 0, 0) 3239 } 3240 3241 case 55: /* op Rb, Rd */ 3242 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg)) 3243 3244 case 56: /* sra $sh,[s,]a; srd $sh,[s,]a */ 3245 v := c.regoff(&p.From) 3246 3247 r := int(p.Reg) 3248 if r == 0 { 3249 r = int(p.To.Reg) 3250 } 3251 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31) 3252 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) { 3253 o1 |= 1 << 1 /* mb[5] */ 3254 } 3255 3256 case 57: /* slw $sh,[s,]a -> rlwinm ... */ 3257 v := c.regoff(&p.From) 3258 3259 r := int(p.Reg) 3260 if r == 0 { 3261 r = int(p.To.Reg) 3262 } 3263 3264 /* 3265 * Let user (gs) shoot himself in the foot. 3266 * qc has already complained. 3267 * 3268 if(v < 0 || v > 31) 3269 ctxt->diag("illegal shift %ld\n%v", v, p); 3270 */ 3271 if v < 0 { 3272 v = 0 3273 } else if v > 32 { 3274 v = 32 3275 } 3276 var mask [2]uint8 3277 switch p.As { 3278 case AROTLW: 3279 mask[0], mask[1] = 0, 31 3280 case ASRW, ASRWCC: 3281 mask[0], mask[1] = uint8(v), 31 3282 v = 32 - v 3283 default: 3284 mask[0], mask[1] = 0, uint8(31-v) 3285 } 3286 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1])) 3287 if p.As == ASLWCC || p.As == ASRWCC { 3288 o1 |= 1 // set the condition code 3289 } 3290 3291 case 58: /* logical $andcon,[s],a */ 3292 v := c.regoff(&p.From) 3293 3294 r := int(p.Reg) 3295 if r == 0 { 3296 r = int(p.To.Reg) 3297 } 3298 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3299 3300 case 59: /* or/xor/and $ucon,,r | oris/xoris/andis $addcon,r,r */ 3301 v := c.regoff(&p.From) 3302 3303 r := int(p.Reg) 3304 if r == 0 { 3305 r = int(p.To.Reg) 3306 } 3307 switch p.As { 3308 case AOR: 3309 o1 = LOP_IRR(c.opirr(AORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16) /* oris, xoris, andis. */ 3310 case AXOR: 3311 o1 = LOP_IRR(c.opirr(AXORIS), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 3312 case AANDCC: 3313 o1 = LOP_IRR(c.opirr(AANDISCC), uint32(p.To.Reg), uint32(r), uint32(v)>>16) 3314 default: 3315 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v)) 3316 } 3317 3318 case 60: /* tw to,a,b */ 3319 r := int(c.regoff(&p.From) & 31) 3320 3321 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg)) 3322 3323 case 61: /* tw to,a,$simm */ 3324 r := int(c.regoff(&p.From) & 31) 3325 3326 v := c.regoff(&p.To) 3327 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v)) 3328 3329 case 62: /* rlwmi $sh,s,$mask,a */ 3330 v := c.regoff(&p.From) 3331 3332 var mask [2]uint8 3333 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3334 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(v)) 3335 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3336 3337 case 63: /* rlwmi b,s,$mask,a */ 3338 var mask [2]uint8 3339 c.maskgen(p, mask[:], uint32(c.regoff(p.GetFrom3()))) 3340 3341 o1 = AOP_RRR(c.opirr(p.As), uint32(p.Reg), uint32(p.To.Reg), uint32(p.From.Reg)) 3342 o1 |= (uint32(mask[0])&31)<<6 | (uint32(mask[1])&31)<<1 3343 3344 case 64: /* mtfsf fr[, $m] {,fpcsr} */ 3345 var v int32 3346 if p.From3Type() != obj.TYPE_NONE { 3347 v = c.regoff(p.GetFrom3()) & 255 3348 } else { 3349 v = 255 3350 } 3351 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11 3352 3353 case 65: /* MOVFL $imm,FPSCR(n) => mtfsfi crfd,imm */ 3354 if p.To.Reg == 0 { 3355 c.ctxt.Diag("must specify FPSCR(n)\n%v", p) 3356 } 3357 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12 3358 3359 case 66: /* mov spr,r1; mov r1,spr, also dcr */ 3360 var r int 3361 var v int32 3362 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 { 3363 r = int(p.From.Reg) 3364 v = int32(p.To.Reg) 3365 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3366 o1 = OPVCC(31, 451, 0, 0) /* mtdcr */ 3367 } else { 3368 o1 = OPVCC(31, 467, 0, 0) /* mtspr */ 3369 } 3370 } else { 3371 r = int(p.To.Reg) 3372 v = int32(p.From.Reg) 3373 if REG_DCR0 <= v && v <= REG_DCR0+1023 { 3374 o1 = OPVCC(31, 323, 0, 0) /* mfdcr */ 3375 } else { 3376 o1 = OPVCC(31, 339, 0, 0) /* mfspr */ 3377 } 3378 } 3379 3380 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11 3381 3382 case 67: /* mcrf crfD,crfS */ 3383 if p.From.Type != obj.TYPE_REG || p.From.Reg < REG_CR0 || REG_CR7 < p.From.Reg || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3384 c.ctxt.Diag("illegal CR field number\n%v", p) 3385 } 3386 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0) 3387 3388 case 68: /* mfcr rD; mfocrf CRM,rD */ 3389 if p.From.Type == obj.TYPE_REG && REG_CR0 <= p.From.Reg && p.From.Reg <= REG_CR7 { 3390 v := int32(1 << uint(7-(p.To.Reg&7))) /* CR(n) */ 3391 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) | 1<<20 | uint32(v)<<12 /* new form, mfocrf */ 3392 } else { 3393 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0) /* old form, whole register */ 3394 } 3395 3396 case 69: /* mtcrf CRM,rS */ 3397 var v int32 3398 if p.From3Type() != obj.TYPE_NONE { 3399 if p.To.Reg != 0 { 3400 c.ctxt.Diag("can't use both mask and CR(n)\n%v", p) 3401 } 3402 v = c.regoff(p.GetFrom3()) & 0xff 3403 } else { 3404 if p.To.Reg == 0 { 3405 v = 0xff /* CR */ 3406 } else { 3407 v = 1 << uint(7-(p.To.Reg&7)) /* CR(n) */ 3408 } 3409 } 3410 3411 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12 3412 3413 case 70: /* [f]cmp r,r,cr*/ 3414 var r int 3415 if p.Reg == 0 { 3416 r = 0 3417 } else { 3418 r = (int(p.Reg) & 7) << 2 3419 } 3420 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg)) 3421 3422 case 71: /* cmp[l] r,i,cr*/ 3423 var r int 3424 if p.Reg == 0 { 3425 r = 0 3426 } else { 3427 r = (int(p.Reg) & 7) << 2 3428 } 3429 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff 3430 3431 case 72: /* slbmte (Rb+Rs -> slb[Rb]) -> Rs, Rb */ 3432 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg)) 3433 3434 case 73: /* mcrfs crfD,crfS */ 3435 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg { 3436 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p) 3437 } 3438 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0) 3439 3440 case 77: /* syscall $scon, syscall Rx */ 3441 if p.From.Type == obj.TYPE_CONST { 3442 if p.From.Offset > BIG || p.From.Offset < -BIG { 3443 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p) 3444 } 3445 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset)) 3446 } else if p.From.Type == obj.TYPE_REG { 3447 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg)) 3448 } else { 3449 c.ctxt.Diag("illegal syscall: %v", p) 3450 o1 = 0x7fe00008 // trap always 3451 } 3452 3453 o2 = c.oprrr(p.As) 3454 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO) // XOR R0, R0 3455 3456 case 78: /* undef */ 3457 o1 = 0 /* "An instruction consisting entirely of binary 0s is guaranteed 3458 always to be an illegal instruction." */ 3459 3460 /* relocation operations */ 3461 case 74: 3462 v := c.vregoff(&p.To) 3463 // Offsets in DS form stores must be a multiple of 4 3464 inst := c.opstore(p.As) 3465 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3466 log.Fatalf("invalid offset for DS form load/store %v", p) 3467 } 3468 o1, o2 = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst) 3469 3470 //if(dlm) reloc(&p->to, p->pc, 1); 3471 3472 case 75: 3473 v := c.vregoff(&p.From) 3474 // Offsets in DS form loads must be a multiple of 4 3475 inst := c.opload(p.As) 3476 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3477 log.Fatalf("invalid offset for DS form load/store %v", p) 3478 } 3479 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3480 3481 //if(dlm) reloc(&p->from, p->pc, 1); 3482 3483 case 76: 3484 v := c.vregoff(&p.From) 3485 // Offsets in DS form loads must be a multiple of 4 3486 inst := c.opload(p.As) 3487 if c.opform(inst) == DS_FORM && v&0x3 != 0 { 3488 log.Fatalf("invalid offset for DS form load/store %v", p) 3489 } 3490 o1, o2 = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst) 3491 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3492 3493 //if(dlm) reloc(&p->from, p->pc, 1); 3494 3495 case 79: 3496 if p.From.Offset != 0 { 3497 c.ctxt.Diag("invalid offset against tls var %v", p) 3498 } 3499 o1 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), REGZERO, 0) 3500 rel := obj.Addrel(c.cursym) 3501 rel.Off = int32(c.pc) 3502 rel.Siz = 4 3503 rel.Sym = p.From.Sym 3504 rel.Type = objabi.R_POWER_TLS_LE 3505 3506 case 80: 3507 if p.From.Offset != 0 { 3508 c.ctxt.Diag("invalid offset against tls var %v", p) 3509 } 3510 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3511 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3512 rel := obj.Addrel(c.cursym) 3513 rel.Off = int32(c.pc) 3514 rel.Siz = 8 3515 rel.Sym = p.From.Sym 3516 rel.Type = objabi.R_POWER_TLS_IE 3517 3518 case 81: 3519 v := c.vregoff(&p.To) 3520 if v != 0 { 3521 c.ctxt.Diag("invalid offset against GOT slot %v", p) 3522 } 3523 3524 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3525 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0) 3526 rel := obj.Addrel(c.cursym) 3527 rel.Off = int32(c.pc) 3528 rel.Siz = 8 3529 rel.Sym = p.From.Sym 3530 rel.Type = objabi.R_ADDRPOWER_GOT 3531 case 82: /* vector instructions, VX-form and VC-form */ 3532 if p.From.Type == obj.TYPE_REG { 3533 /* reg reg none OR reg reg reg */ 3534 /* 3-register operand order: VRA, VRB, VRT */ 3535 /* 2-register operand order: VRA, VRT */ 3536 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3537 } else if p.From3Type() == obj.TYPE_CONST { 3538 /* imm imm reg reg */ 3539 /* operand order: SIX, VRA, ST, VRT */ 3540 six := int(c.regoff(&p.From)) 3541 st := int(c.regoff(p.GetFrom3())) 3542 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six)) 3543 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 { 3544 /* imm reg reg */ 3545 /* operand order: UIM, VRB, VRT */ 3546 uim := int(c.regoff(&p.From)) 3547 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim)) 3548 } else { 3549 /* imm reg */ 3550 /* operand order: SIM, VRT */ 3551 sim := int(c.regoff(&p.From)) 3552 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim)) 3553 } 3554 3555 case 83: /* vector instructions, VA-form */ 3556 if p.From.Type == obj.TYPE_REG { 3557 /* reg reg reg reg */ 3558 /* 4-register operand order: VRA, VRB, VRC, VRT */ 3559 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3560 } else if p.From.Type == obj.TYPE_CONST { 3561 /* imm reg reg reg */ 3562 /* operand order: SHB, VRA, VRB, VRT */ 3563 shb := int(c.regoff(&p.From)) 3564 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb)) 3565 } 3566 3567 case 84: // ISEL BC,RA,RB,RT -> isel rt,ra,rb,bc 3568 bc := c.vregoff(&p.From) 3569 3570 // rt = To.Reg, ra = p.Reg, rb = p.From3.Reg 3571 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc)) 3572 3573 case 85: /* vector instructions, VX-form */ 3574 /* reg none reg */ 3575 /* 2-register operand order: VRB, VRT */ 3576 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg)) 3577 3578 case 86: /* VSX indexed store, XX1-form */ 3579 /* reg reg reg */ 3580 /* 3-register operand order: XT, (RB)(RA*1) */ 3581 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg)) 3582 3583 case 87: /* VSX indexed load, XX1-form */ 3584 /* reg reg reg */ 3585 /* 3-register operand order: (RB)(RA*1), XT */ 3586 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg)) 3587 3588 case 88: /* VSX instructions, XX1-form */ 3589 /* reg reg none OR reg reg reg */ 3590 /* 3-register operand order: RA, RB, XT */ 3591 /* 2-register operand order: XS, RA or RA, XT */ 3592 xt := int32(p.To.Reg) 3593 xs := int32(p.From.Reg) 3594 /* We need to treat the special case of extended mnemonics that may have a FREG/VREG as an argument */ 3595 if REG_V0 <= xt && xt <= REG_V31 { 3596 /* Convert V0-V31 to VS32-VS63 */ 3597 xt = xt + 64 3598 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg)) 3599 } else if REG_F0 <= xt && xt <= REG_F31 { 3600 /* Convert F0-F31 to VS0-VS31 */ 3601 xt = xt + 64 3602 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg)) 3603 } else if REG_VS0 <= xt && xt <= REG_VS63 { 3604 o1 = AOP_XX1(c.oprrr(p.As), uint32(xt), uint32(p.From.Reg), uint32(p.Reg)) 3605 } else if REG_V0 <= xs && xs <= REG_V31 { 3606 /* Likewise for XS */ 3607 xs = xs + 64 3608 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg)) 3609 } else if REG_F0 <= xs && xs <= REG_F31 { 3610 xs = xs + 64 3611 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg)) 3612 } else if REG_VS0 <= xs && xs <= REG_VS63 { 3613 o1 = AOP_XX1(c.oprrr(p.As), uint32(xs), uint32(p.To.Reg), uint32(p.Reg)) 3614 } 3615 3616 case 89: /* VSX instructions, XX2-form */ 3617 /* reg none reg OR reg imm reg */ 3618 /* 2-register operand order: XB, XT or XB, UIM, XT*/ 3619 uim := int(c.regoff(p.GetFrom3())) 3620 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg)) 3621 3622 case 90: /* VSX instructions, XX3-form */ 3623 if p.From3Type() == obj.TYPE_NONE { 3624 /* reg reg reg */ 3625 /* 3-register operand order: XA, XB, XT */ 3626 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) 3627 } else if p.From3Type() == obj.TYPE_CONST { 3628 /* reg reg reg imm */ 3629 /* operand order: XA, XB, DM, XT */ 3630 dm := int(c.regoff(p.GetFrom3())) 3631 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm)) 3632 } 3633 3634 case 91: /* VSX instructions, XX4-form */ 3635 /* reg reg reg reg */ 3636 /* 3-register operand order: XA, XB, XC, XT */ 3637 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg)) 3638 3639 case 92: /* X-form instructions, 3-operands */ 3640 if p.To.Type == obj.TYPE_CONST { 3641 /* imm reg reg */ 3642 xf := int32(p.From.Reg) 3643 if REG_F0 <= xf && xf <= REG_F31 { 3644 /* operand order: FRA, FRB, BF */ 3645 bf := int(c.regoff(&p.To)) << 2 3646 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3647 } else { 3648 /* operand order: RA, RB, L */ 3649 l := int(c.regoff(&p.To)) 3650 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg)) 3651 } 3652 } else if p.From3Type() == obj.TYPE_CONST { 3653 /* reg reg imm */ 3654 /* operand order: RB, L, RA */ 3655 l := int(c.regoff(p.GetFrom3())) 3656 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg)) 3657 } else if p.To.Type == obj.TYPE_REG { 3658 cr := int32(p.To.Reg) 3659 if REG_CR0 <= cr && cr <= REG_CR7 { 3660 /* cr reg reg */ 3661 /* operand order: RA, RB, BF */ 3662 bf := (int(p.To.Reg) & 7) << 2 3663 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg)) 3664 } else if p.From.Type == obj.TYPE_CONST { 3665 /* reg imm */ 3666 /* operand order: L, RT */ 3667 l := int(c.regoff(&p.From)) 3668 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg)) 3669 } else { 3670 switch p.As { 3671 case ACOPY, APASTECC: 3672 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg)) 3673 default: 3674 /* reg reg reg */ 3675 /* operand order: RS, RB, RA */ 3676 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3677 } 3678 } 3679 } 3680 3681 case 93: /* X-form instructions, 2-operands */ 3682 if p.To.Type == obj.TYPE_CONST { 3683 /* imm reg */ 3684 /* operand order: FRB, BF */ 3685 bf := int(c.regoff(&p.To)) << 2 3686 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg)) 3687 } else if p.Reg == 0 { 3688 /* popcnt* r,r, X-form */ 3689 /* operand order: RS, RA */ 3690 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg)) 3691 } 3692 3693 case 94: /* Z23-form instructions, 4-operands */ 3694 /* reg reg reg imm */ 3695 /* operand order: RA, RB, CY, RT */ 3696 cy := int(c.regoff(p.GetFrom3())) 3697 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy)) 3698 3699 case 95: /* Retrieve TOC relative symbol */ 3700 /* This code is for AIX only */ 3701 v := c.vregoff(&p.From) 3702 if v != 0 { 3703 c.ctxt.Diag("invalid offset against TOC slot %v", p) 3704 } 3705 3706 inst := c.opload(p.As) 3707 if c.opform(inst) != DS_FORM { 3708 c.ctxt.Diag("invalid form for a TOC access in %v", p) 3709 } 3710 3711 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0) 3712 o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0) 3713 rel := obj.Addrel(c.cursym) 3714 rel.Off = int32(c.pc) 3715 rel.Siz = 8 3716 rel.Sym = p.From.Sym 3717 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS 3718 3719 case 96: /* VSX load, DQ-form */ 3720 /* reg imm reg */ 3721 /* operand order: (RA)(DQ), XT */ 3722 dq := int16(c.regoff(&p.From)) 3723 if (dq & 15) != 0 { 3724 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq) 3725 } 3726 o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq)) 3727 3728 case 97: /* VSX store, DQ-form */ 3729 /* reg imm reg */ 3730 /* operand order: XT, (RA)(DQ) */ 3731 dq := int16(c.regoff(&p.To)) 3732 if (dq & 15) != 0 { 3733 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq) 3734 } 3735 o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq)) 3736 } 3737 3738 out[0] = o1 3739 out[1] = o2 3740 out[2] = o3 3741 out[3] = o4 3742 out[4] = o5 3743} 3744 3745func (c *ctxt9) vregoff(a *obj.Addr) int64 { 3746 c.instoffset = 0 3747 if a != nil { 3748 c.aclass(a) 3749 } 3750 return c.instoffset 3751} 3752 3753func (c *ctxt9) regoff(a *obj.Addr) int32 { 3754 return int32(c.vregoff(a)) 3755} 3756 3757func (c *ctxt9) oprrr(a obj.As) uint32 { 3758 switch a { 3759 case AADD: 3760 return OPVCC(31, 266, 0, 0) 3761 case AADDCC: 3762 return OPVCC(31, 266, 0, 1) 3763 case AADDV: 3764 return OPVCC(31, 266, 1, 0) 3765 case AADDVCC: 3766 return OPVCC(31, 266, 1, 1) 3767 case AADDC: 3768 return OPVCC(31, 10, 0, 0) 3769 case AADDCCC: 3770 return OPVCC(31, 10, 0, 1) 3771 case AADDCV: 3772 return OPVCC(31, 10, 1, 0) 3773 case AADDCVCC: 3774 return OPVCC(31, 10, 1, 1) 3775 case AADDE: 3776 return OPVCC(31, 138, 0, 0) 3777 case AADDECC: 3778 return OPVCC(31, 138, 0, 1) 3779 case AADDEV: 3780 return OPVCC(31, 138, 1, 0) 3781 case AADDEVCC: 3782 return OPVCC(31, 138, 1, 1) 3783 case AADDME: 3784 return OPVCC(31, 234, 0, 0) 3785 case AADDMECC: 3786 return OPVCC(31, 234, 0, 1) 3787 case AADDMEV: 3788 return OPVCC(31, 234, 1, 0) 3789 case AADDMEVCC: 3790 return OPVCC(31, 234, 1, 1) 3791 case AADDZE: 3792 return OPVCC(31, 202, 0, 0) 3793 case AADDZECC: 3794 return OPVCC(31, 202, 0, 1) 3795 case AADDZEV: 3796 return OPVCC(31, 202, 1, 0) 3797 case AADDZEVCC: 3798 return OPVCC(31, 202, 1, 1) 3799 case AADDEX: 3800 return OPVCC(31, 170, 0, 0) /* addex - v3.0b */ 3801 3802 case AAND: 3803 return OPVCC(31, 28, 0, 0) 3804 case AANDCC: 3805 return OPVCC(31, 28, 0, 1) 3806 case AANDN: 3807 return OPVCC(31, 60, 0, 0) 3808 case AANDNCC: 3809 return OPVCC(31, 60, 0, 1) 3810 3811 case ACMP: 3812 return OPVCC(31, 0, 0, 0) | 1<<21 /* L=1 */ 3813 case ACMPU: 3814 return OPVCC(31, 32, 0, 0) | 1<<21 3815 case ACMPW: 3816 return OPVCC(31, 0, 0, 0) /* L=0 */ 3817 case ACMPWU: 3818 return OPVCC(31, 32, 0, 0) 3819 case ACMPB: 3820 return OPVCC(31, 508, 0, 0) /* cmpb - v2.05 */ 3821 case ACMPEQB: 3822 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */ 3823 3824 case ACNTLZW: 3825 return OPVCC(31, 26, 0, 0) 3826 case ACNTLZWCC: 3827 return OPVCC(31, 26, 0, 1) 3828 case ACNTLZD: 3829 return OPVCC(31, 58, 0, 0) 3830 case ACNTLZDCC: 3831 return OPVCC(31, 58, 0, 1) 3832 3833 case ACRAND: 3834 return OPVCC(19, 257, 0, 0) 3835 case ACRANDN: 3836 return OPVCC(19, 129, 0, 0) 3837 case ACREQV: 3838 return OPVCC(19, 289, 0, 0) 3839 case ACRNAND: 3840 return OPVCC(19, 225, 0, 0) 3841 case ACRNOR: 3842 return OPVCC(19, 33, 0, 0) 3843 case ACROR: 3844 return OPVCC(19, 449, 0, 0) 3845 case ACRORN: 3846 return OPVCC(19, 417, 0, 0) 3847 case ACRXOR: 3848 return OPVCC(19, 193, 0, 0) 3849 3850 case ADCBF: 3851 return OPVCC(31, 86, 0, 0) 3852 case ADCBI: 3853 return OPVCC(31, 470, 0, 0) 3854 case ADCBST: 3855 return OPVCC(31, 54, 0, 0) 3856 case ADCBT: 3857 return OPVCC(31, 278, 0, 0) 3858 case ADCBTST: 3859 return OPVCC(31, 246, 0, 0) 3860 case ADCBZ: 3861 return OPVCC(31, 1014, 0, 0) 3862 3863 case AREM, ADIVW: 3864 return OPVCC(31, 491, 0, 0) 3865 3866 case AREMCC, ADIVWCC: 3867 return OPVCC(31, 491, 0, 1) 3868 3869 case AREMV, ADIVWV: 3870 return OPVCC(31, 491, 1, 0) 3871 3872 case AREMVCC, ADIVWVCC: 3873 return OPVCC(31, 491, 1, 1) 3874 3875 case AREMU, ADIVWU: 3876 return OPVCC(31, 459, 0, 0) 3877 3878 case AREMUCC, ADIVWUCC: 3879 return OPVCC(31, 459, 0, 1) 3880 3881 case AREMUV, ADIVWUV: 3882 return OPVCC(31, 459, 1, 0) 3883 3884 case AREMUVCC, ADIVWUVCC: 3885 return OPVCC(31, 459, 1, 1) 3886 3887 case AREMD, ADIVD: 3888 return OPVCC(31, 489, 0, 0) 3889 3890 case AREMDCC, ADIVDCC: 3891 return OPVCC(31, 489, 0, 1) 3892 3893 case ADIVDE: 3894 return OPVCC(31, 425, 0, 0) 3895 3896 case ADIVDECC: 3897 return OPVCC(31, 425, 0, 1) 3898 3899 case ADIVDEU: 3900 return OPVCC(31, 393, 0, 0) 3901 3902 case ADIVDEUCC: 3903 return OPVCC(31, 393, 0, 1) 3904 3905 case AREMDV, ADIVDV: 3906 return OPVCC(31, 489, 1, 0) 3907 3908 case AREMDVCC, ADIVDVCC: 3909 return OPVCC(31, 489, 1, 1) 3910 3911 case AREMDU, ADIVDU: 3912 return OPVCC(31, 457, 0, 0) 3913 3914 case AREMDUCC, ADIVDUCC: 3915 return OPVCC(31, 457, 0, 1) 3916 3917 case AREMDUV, ADIVDUV: 3918 return OPVCC(31, 457, 1, 0) 3919 3920 case AREMDUVCC, ADIVDUVCC: 3921 return OPVCC(31, 457, 1, 1) 3922 3923 case AEIEIO: 3924 return OPVCC(31, 854, 0, 0) 3925 3926 case AEQV: 3927 return OPVCC(31, 284, 0, 0) 3928 case AEQVCC: 3929 return OPVCC(31, 284, 0, 1) 3930 3931 case AEXTSB: 3932 return OPVCC(31, 954, 0, 0) 3933 case AEXTSBCC: 3934 return OPVCC(31, 954, 0, 1) 3935 case AEXTSH: 3936 return OPVCC(31, 922, 0, 0) 3937 case AEXTSHCC: 3938 return OPVCC(31, 922, 0, 1) 3939 case AEXTSW: 3940 return OPVCC(31, 986, 0, 0) 3941 case AEXTSWCC: 3942 return OPVCC(31, 986, 0, 1) 3943 3944 case AFABS: 3945 return OPVCC(63, 264, 0, 0) 3946 case AFABSCC: 3947 return OPVCC(63, 264, 0, 1) 3948 case AFADD: 3949 return OPVCC(63, 21, 0, 0) 3950 case AFADDCC: 3951 return OPVCC(63, 21, 0, 1) 3952 case AFADDS: 3953 return OPVCC(59, 21, 0, 0) 3954 case AFADDSCC: 3955 return OPVCC(59, 21, 0, 1) 3956 case AFCMPO: 3957 return OPVCC(63, 32, 0, 0) 3958 case AFCMPU: 3959 return OPVCC(63, 0, 0, 0) 3960 case AFCFID: 3961 return OPVCC(63, 846, 0, 0) 3962 case AFCFIDCC: 3963 return OPVCC(63, 846, 0, 1) 3964 case AFCFIDU: 3965 return OPVCC(63, 974, 0, 0) 3966 case AFCFIDUCC: 3967 return OPVCC(63, 974, 0, 1) 3968 case AFCFIDS: 3969 return OPVCC(59, 846, 0, 0) 3970 case AFCFIDSCC: 3971 return OPVCC(59, 846, 0, 1) 3972 case AFCTIW: 3973 return OPVCC(63, 14, 0, 0) 3974 case AFCTIWCC: 3975 return OPVCC(63, 14, 0, 1) 3976 case AFCTIWZ: 3977 return OPVCC(63, 15, 0, 0) 3978 case AFCTIWZCC: 3979 return OPVCC(63, 15, 0, 1) 3980 case AFCTID: 3981 return OPVCC(63, 814, 0, 0) 3982 case AFCTIDCC: 3983 return OPVCC(63, 814, 0, 1) 3984 case AFCTIDZ: 3985 return OPVCC(63, 815, 0, 0) 3986 case AFCTIDZCC: 3987 return OPVCC(63, 815, 0, 1) 3988 case AFDIV: 3989 return OPVCC(63, 18, 0, 0) 3990 case AFDIVCC: 3991 return OPVCC(63, 18, 0, 1) 3992 case AFDIVS: 3993 return OPVCC(59, 18, 0, 0) 3994 case AFDIVSCC: 3995 return OPVCC(59, 18, 0, 1) 3996 case AFMADD: 3997 return OPVCC(63, 29, 0, 0) 3998 case AFMADDCC: 3999 return OPVCC(63, 29, 0, 1) 4000 case AFMADDS: 4001 return OPVCC(59, 29, 0, 0) 4002 case AFMADDSCC: 4003 return OPVCC(59, 29, 0, 1) 4004 4005 case AFMOVS, AFMOVD: 4006 return OPVCC(63, 72, 0, 0) /* load */ 4007 case AFMOVDCC: 4008 return OPVCC(63, 72, 0, 1) 4009 case AFMSUB: 4010 return OPVCC(63, 28, 0, 0) 4011 case AFMSUBCC: 4012 return OPVCC(63, 28, 0, 1) 4013 case AFMSUBS: 4014 return OPVCC(59, 28, 0, 0) 4015 case AFMSUBSCC: 4016 return OPVCC(59, 28, 0, 1) 4017 case AFMUL: 4018 return OPVCC(63, 25, 0, 0) 4019 case AFMULCC: 4020 return OPVCC(63, 25, 0, 1) 4021 case AFMULS: 4022 return OPVCC(59, 25, 0, 0) 4023 case AFMULSCC: 4024 return OPVCC(59, 25, 0, 1) 4025 case AFNABS: 4026 return OPVCC(63, 136, 0, 0) 4027 case AFNABSCC: 4028 return OPVCC(63, 136, 0, 1) 4029 case AFNEG: 4030 return OPVCC(63, 40, 0, 0) 4031 case AFNEGCC: 4032 return OPVCC(63, 40, 0, 1) 4033 case AFNMADD: 4034 return OPVCC(63, 31, 0, 0) 4035 case AFNMADDCC: 4036 return OPVCC(63, 31, 0, 1) 4037 case AFNMADDS: 4038 return OPVCC(59, 31, 0, 0) 4039 case AFNMADDSCC: 4040 return OPVCC(59, 31, 0, 1) 4041 case AFNMSUB: 4042 return OPVCC(63, 30, 0, 0) 4043 case AFNMSUBCC: 4044 return OPVCC(63, 30, 0, 1) 4045 case AFNMSUBS: 4046 return OPVCC(59, 30, 0, 0) 4047 case AFNMSUBSCC: 4048 return OPVCC(59, 30, 0, 1) 4049 case AFCPSGN: 4050 return OPVCC(63, 8, 0, 0) 4051 case AFCPSGNCC: 4052 return OPVCC(63, 8, 0, 1) 4053 case AFRES: 4054 return OPVCC(59, 24, 0, 0) 4055 case AFRESCC: 4056 return OPVCC(59, 24, 0, 1) 4057 case AFRIM: 4058 return OPVCC(63, 488, 0, 0) 4059 case AFRIMCC: 4060 return OPVCC(63, 488, 0, 1) 4061 case AFRIP: 4062 return OPVCC(63, 456, 0, 0) 4063 case AFRIPCC: 4064 return OPVCC(63, 456, 0, 1) 4065 case AFRIZ: 4066 return OPVCC(63, 424, 0, 0) 4067 case AFRIZCC: 4068 return OPVCC(63, 424, 0, 1) 4069 case AFRIN: 4070 return OPVCC(63, 392, 0, 0) 4071 case AFRINCC: 4072 return OPVCC(63, 392, 0, 1) 4073 case AFRSP: 4074 return OPVCC(63, 12, 0, 0) 4075 case AFRSPCC: 4076 return OPVCC(63, 12, 0, 1) 4077 case AFRSQRTE: 4078 return OPVCC(63, 26, 0, 0) 4079 case AFRSQRTECC: 4080 return OPVCC(63, 26, 0, 1) 4081 case AFSEL: 4082 return OPVCC(63, 23, 0, 0) 4083 case AFSELCC: 4084 return OPVCC(63, 23, 0, 1) 4085 case AFSQRT: 4086 return OPVCC(63, 22, 0, 0) 4087 case AFSQRTCC: 4088 return OPVCC(63, 22, 0, 1) 4089 case AFSQRTS: 4090 return OPVCC(59, 22, 0, 0) 4091 case AFSQRTSCC: 4092 return OPVCC(59, 22, 0, 1) 4093 case AFSUB: 4094 return OPVCC(63, 20, 0, 0) 4095 case AFSUBCC: 4096 return OPVCC(63, 20, 0, 1) 4097 case AFSUBS: 4098 return OPVCC(59, 20, 0, 0) 4099 case AFSUBSCC: 4100 return OPVCC(59, 20, 0, 1) 4101 4102 case AICBI: 4103 return OPVCC(31, 982, 0, 0) 4104 case AISYNC: 4105 return OPVCC(19, 150, 0, 0) 4106 4107 case AMTFSB0: 4108 return OPVCC(63, 70, 0, 0) 4109 case AMTFSB0CC: 4110 return OPVCC(63, 70, 0, 1) 4111 case AMTFSB1: 4112 return OPVCC(63, 38, 0, 0) 4113 case AMTFSB1CC: 4114 return OPVCC(63, 38, 0, 1) 4115 4116 case AMULHW: 4117 return OPVCC(31, 75, 0, 0) 4118 case AMULHWCC: 4119 return OPVCC(31, 75, 0, 1) 4120 case AMULHWU: 4121 return OPVCC(31, 11, 0, 0) 4122 case AMULHWUCC: 4123 return OPVCC(31, 11, 0, 1) 4124 case AMULLW: 4125 return OPVCC(31, 235, 0, 0) 4126 case AMULLWCC: 4127 return OPVCC(31, 235, 0, 1) 4128 case AMULLWV: 4129 return OPVCC(31, 235, 1, 0) 4130 case AMULLWVCC: 4131 return OPVCC(31, 235, 1, 1) 4132 4133 case AMULHD: 4134 return OPVCC(31, 73, 0, 0) 4135 case AMULHDCC: 4136 return OPVCC(31, 73, 0, 1) 4137 case AMULHDU: 4138 return OPVCC(31, 9, 0, 0) 4139 case AMULHDUCC: 4140 return OPVCC(31, 9, 0, 1) 4141 case AMULLD: 4142 return OPVCC(31, 233, 0, 0) 4143 case AMULLDCC: 4144 return OPVCC(31, 233, 0, 1) 4145 case AMULLDV: 4146 return OPVCC(31, 233, 1, 0) 4147 case AMULLDVCC: 4148 return OPVCC(31, 233, 1, 1) 4149 4150 case ANAND: 4151 return OPVCC(31, 476, 0, 0) 4152 case ANANDCC: 4153 return OPVCC(31, 476, 0, 1) 4154 case ANEG: 4155 return OPVCC(31, 104, 0, 0) 4156 case ANEGCC: 4157 return OPVCC(31, 104, 0, 1) 4158 case ANEGV: 4159 return OPVCC(31, 104, 1, 0) 4160 case ANEGVCC: 4161 return OPVCC(31, 104, 1, 1) 4162 case ANOR: 4163 return OPVCC(31, 124, 0, 0) 4164 case ANORCC: 4165 return OPVCC(31, 124, 0, 1) 4166 case AOR: 4167 return OPVCC(31, 444, 0, 0) 4168 case AORCC: 4169 return OPVCC(31, 444, 0, 1) 4170 case AORN: 4171 return OPVCC(31, 412, 0, 0) 4172 case AORNCC: 4173 return OPVCC(31, 412, 0, 1) 4174 4175 case APOPCNTD: 4176 return OPVCC(31, 506, 0, 0) /* popcntd - v2.06 */ 4177 case APOPCNTW: 4178 return OPVCC(31, 378, 0, 0) /* popcntw - v2.06 */ 4179 case APOPCNTB: 4180 return OPVCC(31, 122, 0, 0) /* popcntb - v2.02 */ 4181 case ACNTTZW: 4182 return OPVCC(31, 538, 0, 0) /* cnttzw - v3.00 */ 4183 case ACNTTZWCC: 4184 return OPVCC(31, 538, 0, 1) /* cnttzw. - v3.00 */ 4185 case ACNTTZD: 4186 return OPVCC(31, 570, 0, 0) /* cnttzd - v3.00 */ 4187 case ACNTTZDCC: 4188 return OPVCC(31, 570, 0, 1) /* cnttzd. - v3.00 */ 4189 4190 case ARFI: 4191 return OPVCC(19, 50, 0, 0) 4192 case ARFCI: 4193 return OPVCC(19, 51, 0, 0) 4194 case ARFID: 4195 return OPVCC(19, 18, 0, 0) 4196 case AHRFID: 4197 return OPVCC(19, 274, 0, 0) 4198 4199 case ARLWMI: 4200 return OPVCC(20, 0, 0, 0) 4201 case ARLWMICC: 4202 return OPVCC(20, 0, 0, 1) 4203 case ARLWNM: 4204 return OPVCC(23, 0, 0, 0) 4205 case ARLWNMCC: 4206 return OPVCC(23, 0, 0, 1) 4207 4208 case ARLDCL: 4209 return OPVCC(30, 8, 0, 0) 4210 case ARLDCR: 4211 return OPVCC(30, 9, 0, 0) 4212 4213 case ARLDICL: 4214 return OPVCC(30, 0, 0, 0) 4215 case ARLDICLCC: 4216 return OPVCC(30, 0, 0, 1) 4217 case ARLDICR: 4218 return OPVCC(30, 0, 0, 0) | 2<<1 // rldicr 4219 case ARLDICRCC: 4220 return OPVCC(30, 0, 0, 1) | 2<<1 // rldicr. 4221 4222 case ASYSCALL: 4223 return OPVCC(17, 1, 0, 0) 4224 4225 case ASLW: 4226 return OPVCC(31, 24, 0, 0) 4227 case ASLWCC: 4228 return OPVCC(31, 24, 0, 1) 4229 case ASLD: 4230 return OPVCC(31, 27, 0, 0) 4231 case ASLDCC: 4232 return OPVCC(31, 27, 0, 1) 4233 4234 case ASRAW: 4235 return OPVCC(31, 792, 0, 0) 4236 case ASRAWCC: 4237 return OPVCC(31, 792, 0, 1) 4238 case ASRAD: 4239 return OPVCC(31, 794, 0, 0) 4240 case ASRADCC: 4241 return OPVCC(31, 794, 0, 1) 4242 4243 case ASRW: 4244 return OPVCC(31, 536, 0, 0) 4245 case ASRWCC: 4246 return OPVCC(31, 536, 0, 1) 4247 case ASRD: 4248 return OPVCC(31, 539, 0, 0) 4249 case ASRDCC: 4250 return OPVCC(31, 539, 0, 1) 4251 4252 case ASUB: 4253 return OPVCC(31, 40, 0, 0) 4254 case ASUBCC: 4255 return OPVCC(31, 40, 0, 1) 4256 case ASUBV: 4257 return OPVCC(31, 40, 1, 0) 4258 case ASUBVCC: 4259 return OPVCC(31, 40, 1, 1) 4260 case ASUBC: 4261 return OPVCC(31, 8, 0, 0) 4262 case ASUBCCC: 4263 return OPVCC(31, 8, 0, 1) 4264 case ASUBCV: 4265 return OPVCC(31, 8, 1, 0) 4266 case ASUBCVCC: 4267 return OPVCC(31, 8, 1, 1) 4268 case ASUBE: 4269 return OPVCC(31, 136, 0, 0) 4270 case ASUBECC: 4271 return OPVCC(31, 136, 0, 1) 4272 case ASUBEV: 4273 return OPVCC(31, 136, 1, 0) 4274 case ASUBEVCC: 4275 return OPVCC(31, 136, 1, 1) 4276 case ASUBME: 4277 return OPVCC(31, 232, 0, 0) 4278 case ASUBMECC: 4279 return OPVCC(31, 232, 0, 1) 4280 case ASUBMEV: 4281 return OPVCC(31, 232, 1, 0) 4282 case ASUBMEVCC: 4283 return OPVCC(31, 232, 1, 1) 4284 case ASUBZE: 4285 return OPVCC(31, 200, 0, 0) 4286 case ASUBZECC: 4287 return OPVCC(31, 200, 0, 1) 4288 case ASUBZEV: 4289 return OPVCC(31, 200, 1, 0) 4290 case ASUBZEVCC: 4291 return OPVCC(31, 200, 1, 1) 4292 4293 case ASYNC: 4294 return OPVCC(31, 598, 0, 0) 4295 case ALWSYNC: 4296 return OPVCC(31, 598, 0, 0) | 1<<21 4297 4298 case APTESYNC: 4299 return OPVCC(31, 598, 0, 0) | 2<<21 4300 4301 case ATLBIE: 4302 return OPVCC(31, 306, 0, 0) 4303 case ATLBIEL: 4304 return OPVCC(31, 274, 0, 0) 4305 case ATLBSYNC: 4306 return OPVCC(31, 566, 0, 0) 4307 case ASLBIA: 4308 return OPVCC(31, 498, 0, 0) 4309 case ASLBIE: 4310 return OPVCC(31, 434, 0, 0) 4311 case ASLBMFEE: 4312 return OPVCC(31, 915, 0, 0) 4313 case ASLBMFEV: 4314 return OPVCC(31, 851, 0, 0) 4315 case ASLBMTE: 4316 return OPVCC(31, 402, 0, 0) 4317 4318 case ATW: 4319 return OPVCC(31, 4, 0, 0) 4320 case ATD: 4321 return OPVCC(31, 68, 0, 0) 4322 4323 /* Vector (VMX/Altivec) instructions */ 4324 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4325 /* are enabled starting at POWER6 (ISA 2.05). */ 4326 case AVAND: 4327 return OPVX(4, 1028, 0, 0) /* vand - v2.03 */ 4328 case AVANDC: 4329 return OPVX(4, 1092, 0, 0) /* vandc - v2.03 */ 4330 case AVNAND: 4331 return OPVX(4, 1412, 0, 0) /* vnand - v2.07 */ 4332 4333 case AVOR: 4334 return OPVX(4, 1156, 0, 0) /* vor - v2.03 */ 4335 case AVORC: 4336 return OPVX(4, 1348, 0, 0) /* vorc - v2.07 */ 4337 case AVNOR: 4338 return OPVX(4, 1284, 0, 0) /* vnor - v2.03 */ 4339 case AVXOR: 4340 return OPVX(4, 1220, 0, 0) /* vxor - v2.03 */ 4341 case AVEQV: 4342 return OPVX(4, 1668, 0, 0) /* veqv - v2.07 */ 4343 4344 case AVADDUBM: 4345 return OPVX(4, 0, 0, 0) /* vaddubm - v2.03 */ 4346 case AVADDUHM: 4347 return OPVX(4, 64, 0, 0) /* vadduhm - v2.03 */ 4348 case AVADDUWM: 4349 return OPVX(4, 128, 0, 0) /* vadduwm - v2.03 */ 4350 case AVADDUDM: 4351 return OPVX(4, 192, 0, 0) /* vaddudm - v2.07 */ 4352 case AVADDUQM: 4353 return OPVX(4, 256, 0, 0) /* vadduqm - v2.07 */ 4354 4355 case AVADDCUQ: 4356 return OPVX(4, 320, 0, 0) /* vaddcuq - v2.07 */ 4357 case AVADDCUW: 4358 return OPVX(4, 384, 0, 0) /* vaddcuw - v2.03 */ 4359 4360 case AVADDUBS: 4361 return OPVX(4, 512, 0, 0) /* vaddubs - v2.03 */ 4362 case AVADDUHS: 4363 return OPVX(4, 576, 0, 0) /* vadduhs - v2.03 */ 4364 case AVADDUWS: 4365 return OPVX(4, 640, 0, 0) /* vadduws - v2.03 */ 4366 4367 case AVADDSBS: 4368 return OPVX(4, 768, 0, 0) /* vaddsbs - v2.03 */ 4369 case AVADDSHS: 4370 return OPVX(4, 832, 0, 0) /* vaddshs - v2.03 */ 4371 case AVADDSWS: 4372 return OPVX(4, 896, 0, 0) /* vaddsws - v2.03 */ 4373 4374 case AVADDEUQM: 4375 return OPVX(4, 60, 0, 0) /* vaddeuqm - v2.07 */ 4376 case AVADDECUQ: 4377 return OPVX(4, 61, 0, 0) /* vaddecuq - v2.07 */ 4378 4379 case AVMULESB: 4380 return OPVX(4, 776, 0, 0) /* vmulesb - v2.03 */ 4381 case AVMULOSB: 4382 return OPVX(4, 264, 0, 0) /* vmulosb - v2.03 */ 4383 case AVMULEUB: 4384 return OPVX(4, 520, 0, 0) /* vmuleub - v2.03 */ 4385 case AVMULOUB: 4386 return OPVX(4, 8, 0, 0) /* vmuloub - v2.03 */ 4387 case AVMULESH: 4388 return OPVX(4, 840, 0, 0) /* vmulesh - v2.03 */ 4389 case AVMULOSH: 4390 return OPVX(4, 328, 0, 0) /* vmulosh - v2.03 */ 4391 case AVMULEUH: 4392 return OPVX(4, 584, 0, 0) /* vmuleuh - v2.03 */ 4393 case AVMULOUH: 4394 return OPVX(4, 72, 0, 0) /* vmulouh - v2.03 */ 4395 case AVMULESW: 4396 return OPVX(4, 904, 0, 0) /* vmulesw - v2.07 */ 4397 case AVMULOSW: 4398 return OPVX(4, 392, 0, 0) /* vmulosw - v2.07 */ 4399 case AVMULEUW: 4400 return OPVX(4, 648, 0, 0) /* vmuleuw - v2.07 */ 4401 case AVMULOUW: 4402 return OPVX(4, 136, 0, 0) /* vmulouw - v2.07 */ 4403 case AVMULUWM: 4404 return OPVX(4, 137, 0, 0) /* vmuluwm - v2.07 */ 4405 4406 case AVPMSUMB: 4407 return OPVX(4, 1032, 0, 0) /* vpmsumb - v2.07 */ 4408 case AVPMSUMH: 4409 return OPVX(4, 1096, 0, 0) /* vpmsumh - v2.07 */ 4410 case AVPMSUMW: 4411 return OPVX(4, 1160, 0, 0) /* vpmsumw - v2.07 */ 4412 case AVPMSUMD: 4413 return OPVX(4, 1224, 0, 0) /* vpmsumd - v2.07 */ 4414 4415 case AVMSUMUDM: 4416 return OPVX(4, 35, 0, 0) /* vmsumudm - v3.00b */ 4417 4418 case AVSUBUBM: 4419 return OPVX(4, 1024, 0, 0) /* vsububm - v2.03 */ 4420 case AVSUBUHM: 4421 return OPVX(4, 1088, 0, 0) /* vsubuhm - v2.03 */ 4422 case AVSUBUWM: 4423 return OPVX(4, 1152, 0, 0) /* vsubuwm - v2.03 */ 4424 case AVSUBUDM: 4425 return OPVX(4, 1216, 0, 0) /* vsubudm - v2.07 */ 4426 case AVSUBUQM: 4427 return OPVX(4, 1280, 0, 0) /* vsubuqm - v2.07 */ 4428 4429 case AVSUBCUQ: 4430 return OPVX(4, 1344, 0, 0) /* vsubcuq - v2.07 */ 4431 case AVSUBCUW: 4432 return OPVX(4, 1408, 0, 0) /* vsubcuw - v2.03 */ 4433 4434 case AVSUBUBS: 4435 return OPVX(4, 1536, 0, 0) /* vsububs - v2.03 */ 4436 case AVSUBUHS: 4437 return OPVX(4, 1600, 0, 0) /* vsubuhs - v2.03 */ 4438 case AVSUBUWS: 4439 return OPVX(4, 1664, 0, 0) /* vsubuws - v2.03 */ 4440 4441 case AVSUBSBS: 4442 return OPVX(4, 1792, 0, 0) /* vsubsbs - v2.03 */ 4443 case AVSUBSHS: 4444 return OPVX(4, 1856, 0, 0) /* vsubshs - v2.03 */ 4445 case AVSUBSWS: 4446 return OPVX(4, 1920, 0, 0) /* vsubsws - v2.03 */ 4447 4448 case AVSUBEUQM: 4449 return OPVX(4, 62, 0, 0) /* vsubeuqm - v2.07 */ 4450 case AVSUBECUQ: 4451 return OPVX(4, 63, 0, 0) /* vsubecuq - v2.07 */ 4452 4453 case AVRLB: 4454 return OPVX(4, 4, 0, 0) /* vrlb - v2.03 */ 4455 case AVRLH: 4456 return OPVX(4, 68, 0, 0) /* vrlh - v2.03 */ 4457 case AVRLW: 4458 return OPVX(4, 132, 0, 0) /* vrlw - v2.03 */ 4459 case AVRLD: 4460 return OPVX(4, 196, 0, 0) /* vrld - v2.07 */ 4461 4462 case AVMRGOW: 4463 return OPVX(4, 1676, 0, 0) /* vmrgow - v2.07 */ 4464 case AVMRGEW: 4465 return OPVX(4, 1932, 0, 0) /* vmrgew - v2.07 */ 4466 4467 case AVSLB: 4468 return OPVX(4, 260, 0, 0) /* vslh - v2.03 */ 4469 case AVSLH: 4470 return OPVX(4, 324, 0, 0) /* vslh - v2.03 */ 4471 case AVSLW: 4472 return OPVX(4, 388, 0, 0) /* vslw - v2.03 */ 4473 case AVSL: 4474 return OPVX(4, 452, 0, 0) /* vsl - v2.03 */ 4475 case AVSLO: 4476 return OPVX(4, 1036, 0, 0) /* vsl - v2.03 */ 4477 case AVSRB: 4478 return OPVX(4, 516, 0, 0) /* vsrb - v2.03 */ 4479 case AVSRH: 4480 return OPVX(4, 580, 0, 0) /* vsrh - v2.03 */ 4481 case AVSRW: 4482 return OPVX(4, 644, 0, 0) /* vsrw - v2.03 */ 4483 case AVSR: 4484 return OPVX(4, 708, 0, 0) /* vsr - v2.03 */ 4485 case AVSRO: 4486 return OPVX(4, 1100, 0, 0) /* vsro - v2.03 */ 4487 case AVSLD: 4488 return OPVX(4, 1476, 0, 0) /* vsld - v2.07 */ 4489 case AVSRD: 4490 return OPVX(4, 1732, 0, 0) /* vsrd - v2.07 */ 4491 4492 case AVSRAB: 4493 return OPVX(4, 772, 0, 0) /* vsrab - v2.03 */ 4494 case AVSRAH: 4495 return OPVX(4, 836, 0, 0) /* vsrah - v2.03 */ 4496 case AVSRAW: 4497 return OPVX(4, 900, 0, 0) /* vsraw - v2.03 */ 4498 case AVSRAD: 4499 return OPVX(4, 964, 0, 0) /* vsrad - v2.07 */ 4500 4501 case AVBPERMQ: 4502 return OPVC(4, 1356, 0, 0) /* vbpermq - v2.07 */ 4503 case AVBPERMD: 4504 return OPVC(4, 1484, 0, 0) /* vbpermd - v3.00 */ 4505 4506 case AVCLZB: 4507 return OPVX(4, 1794, 0, 0) /* vclzb - v2.07 */ 4508 case AVCLZH: 4509 return OPVX(4, 1858, 0, 0) /* vclzh - v2.07 */ 4510 case AVCLZW: 4511 return OPVX(4, 1922, 0, 0) /* vclzw - v2.07 */ 4512 case AVCLZD: 4513 return OPVX(4, 1986, 0, 0) /* vclzd - v2.07 */ 4514 4515 case AVPOPCNTB: 4516 return OPVX(4, 1795, 0, 0) /* vpopcntb - v2.07 */ 4517 case AVPOPCNTH: 4518 return OPVX(4, 1859, 0, 0) /* vpopcnth - v2.07 */ 4519 case AVPOPCNTW: 4520 return OPVX(4, 1923, 0, 0) /* vpopcntw - v2.07 */ 4521 case AVPOPCNTD: 4522 return OPVX(4, 1987, 0, 0) /* vpopcntd - v2.07 */ 4523 4524 case AVCMPEQUB: 4525 return OPVC(4, 6, 0, 0) /* vcmpequb - v2.03 */ 4526 case AVCMPEQUBCC: 4527 return OPVC(4, 6, 0, 1) /* vcmpequb. - v2.03 */ 4528 case AVCMPEQUH: 4529 return OPVC(4, 70, 0, 0) /* vcmpequh - v2.03 */ 4530 case AVCMPEQUHCC: 4531 return OPVC(4, 70, 0, 1) /* vcmpequh. - v2.03 */ 4532 case AVCMPEQUW: 4533 return OPVC(4, 134, 0, 0) /* vcmpequw - v2.03 */ 4534 case AVCMPEQUWCC: 4535 return OPVC(4, 134, 0, 1) /* vcmpequw. - v2.03 */ 4536 case AVCMPEQUD: 4537 return OPVC(4, 199, 0, 0) /* vcmpequd - v2.07 */ 4538 case AVCMPEQUDCC: 4539 return OPVC(4, 199, 0, 1) /* vcmpequd. - v2.07 */ 4540 4541 case AVCMPGTUB: 4542 return OPVC(4, 518, 0, 0) /* vcmpgtub - v2.03 */ 4543 case AVCMPGTUBCC: 4544 return OPVC(4, 518, 0, 1) /* vcmpgtub. - v2.03 */ 4545 case AVCMPGTUH: 4546 return OPVC(4, 582, 0, 0) /* vcmpgtuh - v2.03 */ 4547 case AVCMPGTUHCC: 4548 return OPVC(4, 582, 0, 1) /* vcmpgtuh. - v2.03 */ 4549 case AVCMPGTUW: 4550 return OPVC(4, 646, 0, 0) /* vcmpgtuw - v2.03 */ 4551 case AVCMPGTUWCC: 4552 return OPVC(4, 646, 0, 1) /* vcmpgtuw. - v2.03 */ 4553 case AVCMPGTUD: 4554 return OPVC(4, 711, 0, 0) /* vcmpgtud - v2.07 */ 4555 case AVCMPGTUDCC: 4556 return OPVC(4, 711, 0, 1) /* vcmpgtud. v2.07 */ 4557 case AVCMPGTSB: 4558 return OPVC(4, 774, 0, 0) /* vcmpgtsb - v2.03 */ 4559 case AVCMPGTSBCC: 4560 return OPVC(4, 774, 0, 1) /* vcmpgtsb. - v2.03 */ 4561 case AVCMPGTSH: 4562 return OPVC(4, 838, 0, 0) /* vcmpgtsh - v2.03 */ 4563 case AVCMPGTSHCC: 4564 return OPVC(4, 838, 0, 1) /* vcmpgtsh. - v2.03 */ 4565 case AVCMPGTSW: 4566 return OPVC(4, 902, 0, 0) /* vcmpgtsw - v2.03 */ 4567 case AVCMPGTSWCC: 4568 return OPVC(4, 902, 0, 1) /* vcmpgtsw. - v2.03 */ 4569 case AVCMPGTSD: 4570 return OPVC(4, 967, 0, 0) /* vcmpgtsd - v2.07 */ 4571 case AVCMPGTSDCC: 4572 return OPVC(4, 967, 0, 1) /* vcmpgtsd. - v2.07 */ 4573 4574 case AVCMPNEZB: 4575 return OPVC(4, 263, 0, 0) /* vcmpnezb - v3.00 */ 4576 case AVCMPNEZBCC: 4577 return OPVC(4, 263, 0, 1) /* vcmpnezb. - v3.00 */ 4578 4579 case AVPERM: 4580 return OPVX(4, 43, 0, 0) /* vperm - v2.03 */ 4581 case AVPERMXOR: 4582 return OPVX(4, 45, 0, 0) /* vpermxor - v2.03 */ 4583 4584 case AVSEL: 4585 return OPVX(4, 42, 0, 0) /* vsel - v2.03 */ 4586 4587 case AVCIPHER: 4588 return OPVX(4, 1288, 0, 0) /* vcipher - v2.07 */ 4589 case AVCIPHERLAST: 4590 return OPVX(4, 1289, 0, 0) /* vcipherlast - v2.07 */ 4591 case AVNCIPHER: 4592 return OPVX(4, 1352, 0, 0) /* vncipher - v2.07 */ 4593 case AVNCIPHERLAST: 4594 return OPVX(4, 1353, 0, 0) /* vncipherlast - v2.07 */ 4595 case AVSBOX: 4596 return OPVX(4, 1480, 0, 0) /* vsbox - v2.07 */ 4597 /* End of vector instructions */ 4598 4599 /* Vector scalar (VSX) instructions */ 4600 /* ISA 2.06 enables these for POWER7. */ 4601 case AMFVSRD, AMFVRD, AMFFPRD: 4602 return OPVXX1(31, 51, 0) /* mfvsrd - v2.07 */ 4603 case AMFVSRWZ: 4604 return OPVXX1(31, 115, 0) /* mfvsrwz - v2.07 */ 4605 case AMFVSRLD: 4606 return OPVXX1(31, 307, 0) /* mfvsrld - v3.00 */ 4607 4608 case AMTVSRD, AMTFPRD, AMTVRD: 4609 return OPVXX1(31, 179, 0) /* mtvsrd - v2.07 */ 4610 case AMTVSRWA: 4611 return OPVXX1(31, 211, 0) /* mtvsrwa - v2.07 */ 4612 case AMTVSRWZ: 4613 return OPVXX1(31, 243, 0) /* mtvsrwz - v2.07 */ 4614 case AMTVSRDD: 4615 return OPVXX1(31, 435, 0) /* mtvsrdd - v3.00 */ 4616 case AMTVSRWS: 4617 return OPVXX1(31, 403, 0) /* mtvsrws - v3.00 */ 4618 4619 case AXXLANDQ: 4620 return OPVXX3(60, 130, 0) /* xxland - v2.06 */ 4621 case AXXLANDC: 4622 return OPVXX3(60, 138, 0) /* xxlandc - v2.06 */ 4623 case AXXLEQV: 4624 return OPVXX3(60, 186, 0) /* xxleqv - v2.07 */ 4625 case AXXLNAND: 4626 return OPVXX3(60, 178, 0) /* xxlnand - v2.07 */ 4627 4628 case AXXLORC: 4629 return OPVXX3(60, 170, 0) /* xxlorc - v2.07 */ 4630 case AXXLNOR: 4631 return OPVXX3(60, 162, 0) /* xxlnor - v2.06 */ 4632 case AXXLORQ: 4633 return OPVXX3(60, 146, 0) /* xxlor - v2.06 */ 4634 case AXXLXOR: 4635 return OPVXX3(60, 154, 0) /* xxlxor - v2.06 */ 4636 4637 case AXXSEL: 4638 return OPVXX4(60, 3, 0) /* xxsel - v2.06 */ 4639 4640 case AXXMRGHW: 4641 return OPVXX3(60, 18, 0) /* xxmrghw - v2.06 */ 4642 case AXXMRGLW: 4643 return OPVXX3(60, 50, 0) /* xxmrglw - v2.06 */ 4644 4645 case AXXSPLTW: 4646 return OPVXX2(60, 164, 0) /* xxspltw - v2.06 */ 4647 4648 case AXXPERMDI: 4649 return OPVXX3(60, 10, 0) /* xxpermdi - v2.06 */ 4650 4651 case AXXSLDWI: 4652 return OPVXX3(60, 2, 0) /* xxsldwi - v2.06 */ 4653 4654 case AXSCVDPSP: 4655 return OPVXX2(60, 265, 0) /* xscvdpsp - v2.06 */ 4656 case AXSCVSPDP: 4657 return OPVXX2(60, 329, 0) /* xscvspdp - v2.06 */ 4658 case AXSCVDPSPN: 4659 return OPVXX2(60, 267, 0) /* xscvdpspn - v2.07 */ 4660 case AXSCVSPDPN: 4661 return OPVXX2(60, 331, 0) /* xscvspdpn - v2.07 */ 4662 4663 case AXVCVDPSP: 4664 return OPVXX2(60, 393, 0) /* xvcvdpsp - v2.06 */ 4665 case AXVCVSPDP: 4666 return OPVXX2(60, 457, 0) /* xvcvspdp - v2.06 */ 4667 4668 case AXSCVDPSXDS: 4669 return OPVXX2(60, 344, 0) /* xscvdpsxds - v2.06 */ 4670 case AXSCVDPSXWS: 4671 return OPVXX2(60, 88, 0) /* xscvdpsxws - v2.06 */ 4672 case AXSCVDPUXDS: 4673 return OPVXX2(60, 328, 0) /* xscvdpuxds - v2.06 */ 4674 case AXSCVDPUXWS: 4675 return OPVXX2(60, 72, 0) /* xscvdpuxws - v2.06 */ 4676 4677 case AXSCVSXDDP: 4678 return OPVXX2(60, 376, 0) /* xscvsxddp - v2.06 */ 4679 case AXSCVUXDDP: 4680 return OPVXX2(60, 360, 0) /* xscvuxddp - v2.06 */ 4681 case AXSCVSXDSP: 4682 return OPVXX2(60, 312, 0) /* xscvsxdsp - v2.06 */ 4683 case AXSCVUXDSP: 4684 return OPVXX2(60, 296, 0) /* xscvuxdsp - v2.06 */ 4685 4686 case AXVCVDPSXDS: 4687 return OPVXX2(60, 472, 0) /* xvcvdpsxds - v2.06 */ 4688 case AXVCVDPSXWS: 4689 return OPVXX2(60, 216, 0) /* xvcvdpsxws - v2.06 */ 4690 case AXVCVDPUXDS: 4691 return OPVXX2(60, 456, 0) /* xvcvdpuxds - v2.06 */ 4692 case AXVCVDPUXWS: 4693 return OPVXX2(60, 200, 0) /* xvcvdpuxws - v2.06 */ 4694 case AXVCVSPSXDS: 4695 return OPVXX2(60, 408, 0) /* xvcvspsxds - v2.07 */ 4696 case AXVCVSPSXWS: 4697 return OPVXX2(60, 152, 0) /* xvcvspsxws - v2.07 */ 4698 case AXVCVSPUXDS: 4699 return OPVXX2(60, 392, 0) /* xvcvspuxds - v2.07 */ 4700 case AXVCVSPUXWS: 4701 return OPVXX2(60, 136, 0) /* xvcvspuxws - v2.07 */ 4702 4703 case AXVCVSXDDP: 4704 return OPVXX2(60, 504, 0) /* xvcvsxddp - v2.06 */ 4705 case AXVCVSXWDP: 4706 return OPVXX2(60, 248, 0) /* xvcvsxwdp - v2.06 */ 4707 case AXVCVUXDDP: 4708 return OPVXX2(60, 488, 0) /* xvcvuxddp - v2.06 */ 4709 case AXVCVUXWDP: 4710 return OPVXX2(60, 232, 0) /* xvcvuxwdp - v2.06 */ 4711 case AXVCVSXDSP: 4712 return OPVXX2(60, 440, 0) /* xvcvsxdsp - v2.06 */ 4713 case AXVCVSXWSP: 4714 return OPVXX2(60, 184, 0) /* xvcvsxwsp - v2.06 */ 4715 case AXVCVUXDSP: 4716 return OPVXX2(60, 424, 0) /* xvcvuxdsp - v2.06 */ 4717 case AXVCVUXWSP: 4718 return OPVXX2(60, 168, 0) /* xvcvuxwsp - v2.06 */ 4719 /* End of VSX instructions */ 4720 4721 case AMADDHD: 4722 return OPVX(4, 48, 0, 0) /* maddhd - v3.00 */ 4723 case AMADDHDU: 4724 return OPVX(4, 49, 0, 0) /* maddhdu - v3.00 */ 4725 case AMADDLD: 4726 return OPVX(4, 51, 0, 0) /* maddld - v3.00 */ 4727 4728 case AXOR: 4729 return OPVCC(31, 316, 0, 0) 4730 case AXORCC: 4731 return OPVCC(31, 316, 0, 1) 4732 } 4733 4734 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a) 4735 return 0 4736} 4737 4738func (c *ctxt9) opirrr(a obj.As) uint32 { 4739 switch a { 4740 /* Vector (VMX/Altivec) instructions */ 4741 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4742 /* are enabled starting at POWER6 (ISA 2.05). */ 4743 case AVSLDOI: 4744 return OPVX(4, 44, 0, 0) /* vsldoi - v2.03 */ 4745 } 4746 4747 c.ctxt.Diag("bad i/r/r/r opcode %v", a) 4748 return 0 4749} 4750 4751func (c *ctxt9) opiirr(a obj.As) uint32 { 4752 switch a { 4753 /* Vector (VMX/Altivec) instructions */ 4754 /* ISA 2.07 enables these for POWER8 and beyond. */ 4755 case AVSHASIGMAW: 4756 return OPVX(4, 1666, 0, 0) /* vshasigmaw - v2.07 */ 4757 case AVSHASIGMAD: 4758 return OPVX(4, 1730, 0, 0) /* vshasigmad - v2.07 */ 4759 } 4760 4761 c.ctxt.Diag("bad i/i/r/r opcode %v", a) 4762 return 0 4763} 4764 4765func (c *ctxt9) opirr(a obj.As) uint32 { 4766 switch a { 4767 case AADD: 4768 return OPVCC(14, 0, 0, 0) 4769 case AADDC: 4770 return OPVCC(12, 0, 0, 0) 4771 case AADDCCC: 4772 return OPVCC(13, 0, 0, 0) 4773 case AADDIS: 4774 return OPVCC(15, 0, 0, 0) /* ADDIS */ 4775 4776 case AANDCC: 4777 return OPVCC(28, 0, 0, 0) 4778 case AANDISCC: 4779 return OPVCC(29, 0, 0, 0) /* ANDIS. */ 4780 4781 case ABR: 4782 return OPVCC(18, 0, 0, 0) 4783 case ABL: 4784 return OPVCC(18, 0, 0, 0) | 1 4785 case obj.ADUFFZERO: 4786 return OPVCC(18, 0, 0, 0) | 1 4787 case obj.ADUFFCOPY: 4788 return OPVCC(18, 0, 0, 0) | 1 4789 case ABC: 4790 return OPVCC(16, 0, 0, 0) 4791 case ABCL: 4792 return OPVCC(16, 0, 0, 0) | 1 4793 4794 case ABEQ: 4795 return AOP_RRR(16<<26, 12, 2, 0) 4796 case ABGE: 4797 return AOP_RRR(16<<26, 4, 0, 0) 4798 case ABGT: 4799 return AOP_RRR(16<<26, 12, 1, 0) 4800 case ABLE: 4801 return AOP_RRR(16<<26, 4, 1, 0) 4802 case ABLT: 4803 return AOP_RRR(16<<26, 12, 0, 0) 4804 case ABNE: 4805 return AOP_RRR(16<<26, 4, 2, 0) 4806 case ABVC: 4807 return AOP_RRR(16<<26, 4, 3, 0) // apparently unordered-clear 4808 case ABVS: 4809 return AOP_RRR(16<<26, 12, 3, 0) // apparently unordered-set 4810 4811 case ACMP: 4812 return OPVCC(11, 0, 0, 0) | 1<<21 /* L=1 */ 4813 case ACMPU: 4814 return OPVCC(10, 0, 0, 0) | 1<<21 4815 case ACMPW: 4816 return OPVCC(11, 0, 0, 0) /* L=0 */ 4817 case ACMPWU: 4818 return OPVCC(10, 0, 0, 0) 4819 case ACMPEQB: 4820 return OPVCC(31, 224, 0, 0) /* cmpeqb - v3.00 */ 4821 4822 case ALSW: 4823 return OPVCC(31, 597, 0, 0) 4824 4825 case ACOPY: 4826 return OPVCC(31, 774, 0, 0) /* copy - v3.00 */ 4827 case APASTECC: 4828 return OPVCC(31, 902, 0, 1) /* paste. - v3.00 */ 4829 case ADARN: 4830 return OPVCC(31, 755, 0, 0) /* darn - v3.00 */ 4831 4832 case AMULLW: 4833 return OPVCC(7, 0, 0, 0) 4834 4835 case AOR: 4836 return OPVCC(24, 0, 0, 0) 4837 case AORIS: 4838 return OPVCC(25, 0, 0, 0) /* ORIS */ 4839 4840 case ARLWMI: 4841 return OPVCC(20, 0, 0, 0) /* rlwimi */ 4842 case ARLWMICC: 4843 return OPVCC(20, 0, 0, 1) 4844 case ARLDMI: 4845 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4846 case ARLDMICC: 4847 return OPVCC(30, 0, 0, 1) | 3<<2 4848 case ARLDIMI: 4849 return OPVCC(30, 0, 0, 0) | 3<<2 /* rldimi */ 4850 case ARLDIMICC: 4851 return OPVCC(30, 0, 0, 1) | 3<<2 4852 case ARLWNM: 4853 return OPVCC(21, 0, 0, 0) /* rlwinm */ 4854 case ARLWNMCC: 4855 return OPVCC(21, 0, 0, 1) 4856 4857 case ARLDCL: 4858 return OPVCC(30, 0, 0, 0) /* rldicl */ 4859 case ARLDCLCC: 4860 return OPVCC(30, 0, 0, 1) 4861 case ARLDCR: 4862 return OPVCC(30, 1, 0, 0) /* rldicr */ 4863 case ARLDCRCC: 4864 return OPVCC(30, 1, 0, 1) 4865 case ARLDC: 4866 return OPVCC(30, 0, 0, 0) | 2<<2 4867 case ARLDCCC: 4868 return OPVCC(30, 0, 0, 1) | 2<<2 4869 4870 case ASRAW: 4871 return OPVCC(31, 824, 0, 0) 4872 case ASRAWCC: 4873 return OPVCC(31, 824, 0, 1) 4874 case ASRAD: 4875 return OPVCC(31, (413 << 1), 0, 0) 4876 case ASRADCC: 4877 return OPVCC(31, (413 << 1), 0, 1) 4878 4879 case ASTSW: 4880 return OPVCC(31, 725, 0, 0) 4881 4882 case ASUBC: 4883 return OPVCC(8, 0, 0, 0) 4884 4885 case ATW: 4886 return OPVCC(3, 0, 0, 0) 4887 case ATD: 4888 return OPVCC(2, 0, 0, 0) 4889 4890 /* Vector (VMX/Altivec) instructions */ 4891 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 4892 /* are enabled starting at POWER6 (ISA 2.05). */ 4893 case AVSPLTB: 4894 return OPVX(4, 524, 0, 0) /* vspltb - v2.03 */ 4895 case AVSPLTH: 4896 return OPVX(4, 588, 0, 0) /* vsplth - v2.03 */ 4897 case AVSPLTW: 4898 return OPVX(4, 652, 0, 0) /* vspltw - v2.03 */ 4899 4900 case AVSPLTISB: 4901 return OPVX(4, 780, 0, 0) /* vspltisb - v2.03 */ 4902 case AVSPLTISH: 4903 return OPVX(4, 844, 0, 0) /* vspltish - v2.03 */ 4904 case AVSPLTISW: 4905 return OPVX(4, 908, 0, 0) /* vspltisw - v2.03 */ 4906 /* End of vector instructions */ 4907 4908 case AFTDIV: 4909 return OPVCC(63, 128, 0, 0) /* ftdiv - v2.06 */ 4910 case AFTSQRT: 4911 return OPVCC(63, 160, 0, 0) /* ftsqrt - v2.06 */ 4912 4913 case AXOR: 4914 return OPVCC(26, 0, 0, 0) /* XORIL */ 4915 case AXORIS: 4916 return OPVCC(27, 0, 0, 0) /* XORIS */ 4917 } 4918 4919 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a) 4920 return 0 4921} 4922 4923/* 4924 * load o(a),d 4925 */ 4926func (c *ctxt9) opload(a obj.As) uint32 { 4927 switch a { 4928 case AMOVD: 4929 return OPVCC(58, 0, 0, 0) /* ld */ 4930 case AMOVDU: 4931 return OPVCC(58, 0, 0, 1) /* ldu */ 4932 case AMOVWZ: 4933 return OPVCC(32, 0, 0, 0) /* lwz */ 4934 case AMOVWZU: 4935 return OPVCC(33, 0, 0, 0) /* lwzu */ 4936 case AMOVW: 4937 return OPVCC(58, 0, 0, 0) | 1<<1 /* lwa */ 4938 case ALXV: 4939 return OPDQ(61, 1, 0) /* lxv - ISA v3.00 */ 4940 4941 /* no AMOVWU */ 4942 case AMOVB, AMOVBZ: 4943 return OPVCC(34, 0, 0, 0) 4944 /* load */ 4945 4946 case AMOVBU, AMOVBZU: 4947 return OPVCC(35, 0, 0, 0) 4948 case AFMOVD: 4949 return OPVCC(50, 0, 0, 0) 4950 case AFMOVDU: 4951 return OPVCC(51, 0, 0, 0) 4952 case AFMOVS: 4953 return OPVCC(48, 0, 0, 0) 4954 case AFMOVSU: 4955 return OPVCC(49, 0, 0, 0) 4956 case AMOVH: 4957 return OPVCC(42, 0, 0, 0) 4958 case AMOVHU: 4959 return OPVCC(43, 0, 0, 0) 4960 case AMOVHZ: 4961 return OPVCC(40, 0, 0, 0) 4962 case AMOVHZU: 4963 return OPVCC(41, 0, 0, 0) 4964 case AMOVMW: 4965 return OPVCC(46, 0, 0, 0) /* lmw */ 4966 } 4967 4968 c.ctxt.Diag("bad load opcode %v", a) 4969 return 0 4970} 4971 4972/* 4973 * indexed load a(b),d 4974 */ 4975func (c *ctxt9) oploadx(a obj.As) uint32 { 4976 switch a { 4977 case AMOVWZ: 4978 return OPVCC(31, 23, 0, 0) /* lwzx */ 4979 case AMOVWZU: 4980 return OPVCC(31, 55, 0, 0) /* lwzux */ 4981 case AMOVW: 4982 return OPVCC(31, 341, 0, 0) /* lwax */ 4983 case AMOVWU: 4984 return OPVCC(31, 373, 0, 0) /* lwaux */ 4985 4986 case AMOVB, AMOVBZ: 4987 return OPVCC(31, 87, 0, 0) /* lbzx */ 4988 4989 case AMOVBU, AMOVBZU: 4990 return OPVCC(31, 119, 0, 0) /* lbzux */ 4991 case AFMOVD: 4992 return OPVCC(31, 599, 0, 0) /* lfdx */ 4993 case AFMOVDU: 4994 return OPVCC(31, 631, 0, 0) /* lfdux */ 4995 case AFMOVS: 4996 return OPVCC(31, 535, 0, 0) /* lfsx */ 4997 case AFMOVSU: 4998 return OPVCC(31, 567, 0, 0) /* lfsux */ 4999 case AFMOVSX: 5000 return OPVCC(31, 855, 0, 0) /* lfiwax - power6, isa 2.05 */ 5001 case AFMOVSZ: 5002 return OPVCC(31, 887, 0, 0) /* lfiwzx - power7, isa 2.06 */ 5003 case AMOVH: 5004 return OPVCC(31, 343, 0, 0) /* lhax */ 5005 case AMOVHU: 5006 return OPVCC(31, 375, 0, 0) /* lhaux */ 5007 case AMOVHBR: 5008 return OPVCC(31, 790, 0, 0) /* lhbrx */ 5009 case AMOVWBR: 5010 return OPVCC(31, 534, 0, 0) /* lwbrx */ 5011 case AMOVDBR: 5012 return OPVCC(31, 532, 0, 0) /* ldbrx */ 5013 case AMOVHZ: 5014 return OPVCC(31, 279, 0, 0) /* lhzx */ 5015 case AMOVHZU: 5016 return OPVCC(31, 311, 0, 0) /* lhzux */ 5017 case AECIWX: 5018 return OPVCC(31, 310, 0, 0) /* eciwx */ 5019 case ALBAR: 5020 return OPVCC(31, 52, 0, 0) /* lbarx */ 5021 case ALHAR: 5022 return OPVCC(31, 116, 0, 0) /* lharx */ 5023 case ALWAR: 5024 return OPVCC(31, 20, 0, 0) /* lwarx */ 5025 case ALDAR: 5026 return OPVCC(31, 84, 0, 0) /* ldarx */ 5027 case ALSW: 5028 return OPVCC(31, 533, 0, 0) /* lswx */ 5029 case AMOVD: 5030 return OPVCC(31, 21, 0, 0) /* ldx */ 5031 case AMOVDU: 5032 return OPVCC(31, 53, 0, 0) /* ldux */ 5033 case ALDMX: 5034 return OPVCC(31, 309, 0, 0) /* ldmx */ 5035 5036 /* Vector (VMX/Altivec) instructions */ 5037 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 5038 /* are enabled starting at POWER6 (ISA 2.05). */ 5039 case ALVEBX: 5040 return OPVCC(31, 7, 0, 0) /* lvebx - v2.03 */ 5041 case ALVEHX: 5042 return OPVCC(31, 39, 0, 0) /* lvehx - v2.03 */ 5043 case ALVEWX: 5044 return OPVCC(31, 71, 0, 0) /* lvewx - v2.03 */ 5045 case ALVX: 5046 return OPVCC(31, 103, 0, 0) /* lvx - v2.03 */ 5047 case ALVXL: 5048 return OPVCC(31, 359, 0, 0) /* lvxl - v2.03 */ 5049 case ALVSL: 5050 return OPVCC(31, 6, 0, 0) /* lvsl - v2.03 */ 5051 case ALVSR: 5052 return OPVCC(31, 38, 0, 0) /* lvsr - v2.03 */ 5053 /* End of vector instructions */ 5054 5055 /* Vector scalar (VSX) instructions */ 5056 /* ISA 2.06 enables these for POWER7. */ 5057 case ALXVD2X: 5058 return OPVXX1(31, 844, 0) /* lxvd2x - v2.06 */ 5059 case ALXVW4X: 5060 return OPVXX1(31, 780, 0) /* lxvw4x - v2.06 */ 5061 case ALXVH8X: 5062 return OPVXX1(31, 812, 0) /* lxvh8x - v3.00 */ 5063 case ALXVB16X: 5064 return OPVXX1(31, 876, 0) /* lxvb16x - v3.00 */ 5065 case ALXVDSX: 5066 return OPVXX1(31, 332, 0) /* lxvdsx - v2.06 */ 5067 case ALXSDX: 5068 return OPVXX1(31, 588, 0) /* lxsdx - v2.06 */ 5069 case ALXSIWAX: 5070 return OPVXX1(31, 76, 0) /* lxsiwax - v2.07 */ 5071 case ALXSIWZX: 5072 return OPVXX1(31, 12, 0) /* lxsiwzx - v2.07 */ 5073 /* End of vector scalar instructions */ 5074 5075 } 5076 5077 c.ctxt.Diag("bad loadx opcode %v", a) 5078 return 0 5079} 5080 5081/* 5082 * store s,o(d) 5083 */ 5084func (c *ctxt9) opstore(a obj.As) uint32 { 5085 switch a { 5086 case AMOVB, AMOVBZ: 5087 return OPVCC(38, 0, 0, 0) /* stb */ 5088 5089 case AMOVBU, AMOVBZU: 5090 return OPVCC(39, 0, 0, 0) /* stbu */ 5091 case AFMOVD: 5092 return OPVCC(54, 0, 0, 0) /* stfd */ 5093 case AFMOVDU: 5094 return OPVCC(55, 0, 0, 0) /* stfdu */ 5095 case AFMOVS: 5096 return OPVCC(52, 0, 0, 0) /* stfs */ 5097 case AFMOVSU: 5098 return OPVCC(53, 0, 0, 0) /* stfsu */ 5099 5100 case AMOVHZ, AMOVH: 5101 return OPVCC(44, 0, 0, 0) /* sth */ 5102 5103 case AMOVHZU, AMOVHU: 5104 return OPVCC(45, 0, 0, 0) /* sthu */ 5105 case AMOVMW: 5106 return OPVCC(47, 0, 0, 0) /* stmw */ 5107 case ASTSW: 5108 return OPVCC(31, 725, 0, 0) /* stswi */ 5109 5110 case AMOVWZ, AMOVW: 5111 return OPVCC(36, 0, 0, 0) /* stw */ 5112 5113 case AMOVWZU, AMOVWU: 5114 return OPVCC(37, 0, 0, 0) /* stwu */ 5115 case AMOVD: 5116 return OPVCC(62, 0, 0, 0) /* std */ 5117 case AMOVDU: 5118 return OPVCC(62, 0, 0, 1) /* stdu */ 5119 case ASTXV: 5120 return OPDQ(61, 5, 0) /* stxv */ 5121 } 5122 5123 c.ctxt.Diag("unknown store opcode %v", a) 5124 return 0 5125} 5126 5127/* 5128 * indexed store s,a(b) 5129 */ 5130func (c *ctxt9) opstorex(a obj.As) uint32 { 5131 switch a { 5132 case AMOVB, AMOVBZ: 5133 return OPVCC(31, 215, 0, 0) /* stbx */ 5134 5135 case AMOVBU, AMOVBZU: 5136 return OPVCC(31, 247, 0, 0) /* stbux */ 5137 case AFMOVD: 5138 return OPVCC(31, 727, 0, 0) /* stfdx */ 5139 case AFMOVDU: 5140 return OPVCC(31, 759, 0, 0) /* stfdux */ 5141 case AFMOVS: 5142 return OPVCC(31, 663, 0, 0) /* stfsx */ 5143 case AFMOVSU: 5144 return OPVCC(31, 695, 0, 0) /* stfsux */ 5145 case AFMOVSX: 5146 return OPVCC(31, 983, 0, 0) /* stfiwx */ 5147 5148 case AMOVHZ, AMOVH: 5149 return OPVCC(31, 407, 0, 0) /* sthx */ 5150 case AMOVHBR: 5151 return OPVCC(31, 918, 0, 0) /* sthbrx */ 5152 5153 case AMOVHZU, AMOVHU: 5154 return OPVCC(31, 439, 0, 0) /* sthux */ 5155 5156 case AMOVWZ, AMOVW: 5157 return OPVCC(31, 151, 0, 0) /* stwx */ 5158 5159 case AMOVWZU, AMOVWU: 5160 return OPVCC(31, 183, 0, 0) /* stwux */ 5161 case ASTSW: 5162 return OPVCC(31, 661, 0, 0) /* stswx */ 5163 case AMOVWBR: 5164 return OPVCC(31, 662, 0, 0) /* stwbrx */ 5165 case AMOVDBR: 5166 return OPVCC(31, 660, 0, 0) /* stdbrx */ 5167 case ASTBCCC: 5168 return OPVCC(31, 694, 0, 1) /* stbcx. */ 5169 case ASTWCCC: 5170 return OPVCC(31, 150, 0, 1) /* stwcx. */ 5171 case ASTDCCC: 5172 return OPVCC(31, 214, 0, 1) /* stwdx. */ 5173 case AECOWX: 5174 return OPVCC(31, 438, 0, 0) /* ecowx */ 5175 case AMOVD: 5176 return OPVCC(31, 149, 0, 0) /* stdx */ 5177 case AMOVDU: 5178 return OPVCC(31, 181, 0, 0) /* stdux */ 5179 5180 /* Vector (VMX/Altivec) instructions */ 5181 /* ISA 2.03 enables these for PPC970. For POWERx processors, these */ 5182 /* are enabled starting at POWER6 (ISA 2.05). */ 5183 case ASTVEBX: 5184 return OPVCC(31, 135, 0, 0) /* stvebx - v2.03 */ 5185 case ASTVEHX: 5186 return OPVCC(31, 167, 0, 0) /* stvehx - v2.03 */ 5187 case ASTVEWX: 5188 return OPVCC(31, 199, 0, 0) /* stvewx - v2.03 */ 5189 case ASTVX: 5190 return OPVCC(31, 231, 0, 0) /* stvx - v2.03 */ 5191 case ASTVXL: 5192 return OPVCC(31, 487, 0, 0) /* stvxl - v2.03 */ 5193 /* End of vector instructions */ 5194 5195 /* Vector scalar (VSX) instructions */ 5196 /* ISA 2.06 enables these for POWER7. */ 5197 case ASTXVD2X: 5198 return OPVXX1(31, 972, 0) /* stxvd2x - v2.06 */ 5199 case ASTXVW4X: 5200 return OPVXX1(31, 908, 0) /* stxvw4x - v2.06 */ 5201 case ASTXVH8X: 5202 return OPVXX1(31, 940, 0) /* stxvh8x - v3.00 */ 5203 case ASTXVB16X: 5204 return OPVXX1(31, 1004, 0) /* stxvb16x - v3.00 */ 5205 5206 case ASTXSDX: 5207 return OPVXX1(31, 716, 0) /* stxsdx - v2.06 */ 5208 5209 case ASTXSIWX: 5210 return OPVXX1(31, 140, 0) /* stxsiwx - v2.07 */ 5211 5212 /* End of vector scalar instructions */ 5213 5214 } 5215 5216 c.ctxt.Diag("unknown storex opcode %v", a) 5217 return 0 5218} 5219