1 /*
2  * This file is part of the MicroPython project, http://micropython.org/
3  *
4  * The MIT License (MIT)
5  *
6  * Copyright (c) 2016 Damien P. George
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a copy
9  * of this software and associated documentation files (the "Software"), to deal
10  * in the Software without restriction, including without limitation the rights
11  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12  * copies of the Software, and to permit persons to whom the Software is
13  * furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice shall be included in
16  * all copies or substantial portions of the Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
21  * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24  * THE SOFTWARE.
25  */
26 #ifndef MICROPY_INCLUDED_PY_ASMXTENSA_H
27 #define MICROPY_INCLUDED_PY_ASMXTENSA_H
28 
29 #include "py/misc.h"
30 #include "py/asmbase.h"
31 
32 // calling conventions:
33 // up to 6 args in a2-a7
34 // return value in a2
35 // PC stored in a0
36 // stack pointer is a1, stack full descending, is aligned to 16 bytes
37 // callee save: a1, a12, a13, a14, a15
38 // caller save: a3
39 
40 // With windowed registers, size 8:
41 // - a0: return PC
42 // - a1: stack pointer, full descending, aligned to 16 bytes
43 // - a2-a7: incoming args, and essentially callee save
44 // - a2: return value
45 // - a8-a15: caller save temporaries
46 // - a10-a15: input args to called function
47 // - a10: return value of called function
48 // note: a0-a7 are saved automatically via window shift of called function
49 
50 #define ASM_XTENSA_REG_A0  (0)
51 #define ASM_XTENSA_REG_A1  (1)
52 #define ASM_XTENSA_REG_A2  (2)
53 #define ASM_XTENSA_REG_A3  (3)
54 #define ASM_XTENSA_REG_A4  (4)
55 #define ASM_XTENSA_REG_A5  (5)
56 #define ASM_XTENSA_REG_A6  (6)
57 #define ASM_XTENSA_REG_A7  (7)
58 #define ASM_XTENSA_REG_A8  (8)
59 #define ASM_XTENSA_REG_A9  (9)
60 #define ASM_XTENSA_REG_A10 (10)
61 #define ASM_XTENSA_REG_A11 (11)
62 #define ASM_XTENSA_REG_A12 (12)
63 #define ASM_XTENSA_REG_A13 (13)
64 #define ASM_XTENSA_REG_A14 (14)
65 #define ASM_XTENSA_REG_A15 (15)
66 
67 // for bccz
68 #define ASM_XTENSA_CCZ_EQ (0)
69 #define ASM_XTENSA_CCZ_NE (1)
70 
71 // for bcc and setcc
72 #define ASM_XTENSA_CC_NONE  (0)
73 #define ASM_XTENSA_CC_EQ    (1)
74 #define ASM_XTENSA_CC_LT    (2)
75 #define ASM_XTENSA_CC_LTU   (3)
76 #define ASM_XTENSA_CC_ALL   (4)
77 #define ASM_XTENSA_CC_BC    (5)
78 #define ASM_XTENSA_CC_ANY   (8)
79 #define ASM_XTENSA_CC_NE    (9)
80 #define ASM_XTENSA_CC_GE    (10)
81 #define ASM_XTENSA_CC_GEU   (11)
82 #define ASM_XTENSA_CC_NALL  (12)
83 #define ASM_XTENSA_CC_BS    (13)
84 
85 // macros for encoding instructions (little endian versions)
86 #define ASM_XTENSA_ENCODE_RRR(op0, op1, op2, r, s, t) \
87     ((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
88 #define ASM_XTENSA_ENCODE_RRI4(op0, op1, r, s, t, imm4) \
89     (((imm4) << 20) | ((op1) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
90 #define ASM_XTENSA_ENCODE_RRI8(op0, r, s, t, imm8) \
91     ((((uint32_t)imm8) << 16) | ((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
92 #define ASM_XTENSA_ENCODE_RI16(op0, t, imm16) \
93     (((imm16) << 8) | ((t) << 4) | (op0))
94 #define ASM_XTENSA_ENCODE_RSR(op0, op1, op2, rs, t) \
95     (((op2) << 20) | ((op1) << 16) | ((rs) << 8) | ((t) << 4) | (op0))
96 #define ASM_XTENSA_ENCODE_CALL(op0, n, offset) \
97     (((offset) << 6) | ((n) << 4) | (op0))
98 #define ASM_XTENSA_ENCODE_CALLX(op0, op1, op2, r, s, m, n) \
99     ((((uint32_t)op2) << 20) | (((uint32_t)op1) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
100 #define ASM_XTENSA_ENCODE_BRI8(op0, r, s, m, n, imm8) \
101     (((imm8) << 16) | ((r) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
102 #define ASM_XTENSA_ENCODE_BRI12(op0, s, m, n, imm12) \
103     (((imm12) << 12) | ((s) << 8) | ((m) << 6) | ((n) << 4) | (op0))
104 #define ASM_XTENSA_ENCODE_RRRN(op0, r, s, t) \
105     (((r) << 12) | ((s) << 8) | ((t) << 4) | (op0))
106 #define ASM_XTENSA_ENCODE_RI7(op0, s, imm7) \
107     ((((imm7) & 0xf) << 12) | ((s) << 8) | ((imm7) & 0x70) | (op0))
108 
109 // Number of registers saved on the stack upon entry to function
110 #define ASM_XTENSA_NUM_REGS_SAVED (5)
111 #define ASM_XTENSA_NUM_REGS_SAVED_WIN (1)
112 
113 typedef struct _asm_xtensa_t {
114     mp_asm_base_t base;
115     uint32_t cur_const;
116     uint32_t num_const;
117     uint32_t *const_table;
118     uint32_t stack_adjust;
119 } asm_xtensa_t;
120 
121 void asm_xtensa_end_pass(asm_xtensa_t *as);
122 
123 void asm_xtensa_entry(asm_xtensa_t *as, int num_locals);
124 void asm_xtensa_exit(asm_xtensa_t *as);
125 
126 void asm_xtensa_entry_win(asm_xtensa_t *as, int num_locals);
127 void asm_xtensa_exit_win(asm_xtensa_t *as);
128 
129 void asm_xtensa_op16(asm_xtensa_t *as, uint16_t op);
130 void asm_xtensa_op24(asm_xtensa_t *as, uint32_t op);
131 
132 // raw instructions
133 
asm_xtensa_op_entry(asm_xtensa_t * as,uint reg_src,int32_t num_bytes)134 static inline void asm_xtensa_op_entry(asm_xtensa_t *as, uint reg_src, int32_t num_bytes) {
135     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_BRI12(6, reg_src, 0, 3, (num_bytes / 8) & 0xfff));
136 }
137 
asm_xtensa_op_add_n(asm_xtensa_t * as,uint reg_dest,uint reg_src_a,uint reg_src_b)138 static inline void asm_xtensa_op_add_n(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
139     asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(10, reg_dest, reg_src_a, reg_src_b));
140 }
141 
asm_xtensa_op_addi(asm_xtensa_t * as,uint reg_dest,uint reg_src,int imm8)142 static inline void asm_xtensa_op_addi(asm_xtensa_t *as, uint reg_dest, uint reg_src, int imm8) {
143     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 12, reg_src, reg_dest, imm8 & 0xff));
144 }
145 
asm_xtensa_op_and(asm_xtensa_t * as,uint reg_dest,uint reg_src_a,uint reg_src_b)146 static inline void asm_xtensa_op_and(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
147     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 1, reg_dest, reg_src_a, reg_src_b));
148 }
149 
asm_xtensa_op_bcc(asm_xtensa_t * as,uint cond,uint reg_src1,uint reg_src2,int32_t rel8)150 static inline void asm_xtensa_op_bcc(asm_xtensa_t *as, uint cond, uint reg_src1, uint reg_src2, int32_t rel8) {
151     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(7, cond, reg_src1, reg_src2, rel8 & 0xff));
152 }
153 
asm_xtensa_op_bccz(asm_xtensa_t * as,uint cond,uint reg_src,int32_t rel12)154 static inline void asm_xtensa_op_bccz(asm_xtensa_t *as, uint cond, uint reg_src, int32_t rel12) {
155     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_BRI12(6, reg_src, cond, 1, rel12 & 0xfff));
156 }
157 
asm_xtensa_op_call0(asm_xtensa_t * as,int32_t rel18)158 static inline void asm_xtensa_op_call0(asm_xtensa_t *as, int32_t rel18) {
159     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALL(5, 0, rel18 & 0x3ffff));
160 }
161 
asm_xtensa_op_callx0(asm_xtensa_t * as,uint reg)162 static inline void asm_xtensa_op_callx0(asm_xtensa_t *as, uint reg) {
163     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALLX(0, 0, 0, 0, reg, 3, 0));
164 }
165 
asm_xtensa_op_callx8(asm_xtensa_t * as,uint reg)166 static inline void asm_xtensa_op_callx8(asm_xtensa_t *as, uint reg) {
167     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALLX(0, 0, 0, 0, reg, 3, 2));
168 }
169 
asm_xtensa_op_j(asm_xtensa_t * as,int32_t rel18)170 static inline void asm_xtensa_op_j(asm_xtensa_t *as, int32_t rel18) {
171     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALL(6, 0, rel18 & 0x3ffff));
172 }
173 
asm_xtensa_op_jx(asm_xtensa_t * as,uint reg)174 static inline void asm_xtensa_op_jx(asm_xtensa_t *as, uint reg) {
175     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_CALLX(0, 0, 0, 0, reg, 2, 2));
176 }
177 
asm_xtensa_op_l8ui(asm_xtensa_t * as,uint reg_dest,uint reg_base,uint byte_offset)178 static inline void asm_xtensa_op_l8ui(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint byte_offset) {
179     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 0, reg_base, reg_dest, byte_offset & 0xff));
180 }
181 
asm_xtensa_op_l16ui(asm_xtensa_t * as,uint reg_dest,uint reg_base,uint half_word_offset)182 static inline void asm_xtensa_op_l16ui(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint half_word_offset) {
183     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 1, reg_base, reg_dest, half_word_offset & 0xff));
184 }
185 
asm_xtensa_op_l32i(asm_xtensa_t * as,uint reg_dest,uint reg_base,uint word_offset)186 static inline void asm_xtensa_op_l32i(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint word_offset) {
187     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 2, reg_base, reg_dest, word_offset & 0xff));
188 }
189 
asm_xtensa_op_l32i_n(asm_xtensa_t * as,uint reg_dest,uint reg_base,uint word_offset)190 static inline void asm_xtensa_op_l32i_n(asm_xtensa_t *as, uint reg_dest, uint reg_base, uint word_offset) {
191     asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(8, word_offset & 0xf, reg_base, reg_dest));
192 }
193 
asm_xtensa_op_l32r(asm_xtensa_t * as,uint reg_dest,uint32_t op_off,uint32_t dest_off)194 static inline void asm_xtensa_op_l32r(asm_xtensa_t *as, uint reg_dest, uint32_t op_off, uint32_t dest_off) {
195     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RI16(1, reg_dest, ((dest_off - ((op_off + 3) & ~3)) >> 2) & 0xffff));
196 }
197 
asm_xtensa_op_mov_n(asm_xtensa_t * as,uint reg_dest,uint reg_src)198 static inline void asm_xtensa_op_mov_n(asm_xtensa_t *as, uint reg_dest, uint reg_src) {
199     asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(13, 0, reg_src, reg_dest));
200 }
201 
asm_xtensa_op_movi(asm_xtensa_t * as,uint reg_dest,int32_t imm12)202 static inline void asm_xtensa_op_movi(asm_xtensa_t *as, uint reg_dest, int32_t imm12) {
203     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 10, (imm12 >> 8) & 0xf, reg_dest, imm12 & 0xff));
204 }
205 
asm_xtensa_op_movi_n(asm_xtensa_t * as,uint reg_dest,int imm4)206 static inline void asm_xtensa_op_movi_n(asm_xtensa_t *as, uint reg_dest, int imm4) {
207     asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RI7(12, reg_dest, imm4));
208 }
209 
asm_xtensa_op_mull(asm_xtensa_t * as,uint reg_dest,uint reg_src_a,uint reg_src_b)210 static inline void asm_xtensa_op_mull(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
211     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 2, 8, reg_dest, reg_src_a, reg_src_b));
212 }
213 
asm_xtensa_op_or(asm_xtensa_t * as,uint reg_dest,uint reg_src_a,uint reg_src_b)214 static inline void asm_xtensa_op_or(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
215     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 2, reg_dest, reg_src_a, reg_src_b));
216 }
217 
asm_xtensa_op_ret_n(asm_xtensa_t * as)218 static inline void asm_xtensa_op_ret_n(asm_xtensa_t *as) {
219     asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(13, 15, 0, 0));
220 }
221 
asm_xtensa_op_retw_n(asm_xtensa_t * as)222 static inline void asm_xtensa_op_retw_n(asm_xtensa_t *as) {
223     asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(13, 15, 0, 1));
224 }
225 
asm_xtensa_op_s8i(asm_xtensa_t * as,uint reg_src,uint reg_base,uint byte_offset)226 static inline void asm_xtensa_op_s8i(asm_xtensa_t *as, uint reg_src, uint reg_base, uint byte_offset) {
227     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 4, reg_base, reg_src, byte_offset & 0xff));
228 }
229 
asm_xtensa_op_s16i(asm_xtensa_t * as,uint reg_src,uint reg_base,uint half_word_offset)230 static inline void asm_xtensa_op_s16i(asm_xtensa_t *as, uint reg_src, uint reg_base, uint half_word_offset) {
231     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 5, reg_base, reg_src, half_word_offset & 0xff));
232 }
233 
asm_xtensa_op_s32i(asm_xtensa_t * as,uint reg_src,uint reg_base,uint word_offset)234 static inline void asm_xtensa_op_s32i(asm_xtensa_t *as, uint reg_src, uint reg_base, uint word_offset) {
235     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRI8(2, 6, reg_base, reg_src, word_offset & 0xff));
236 }
237 
asm_xtensa_op_s32i_n(asm_xtensa_t * as,uint reg_src,uint reg_base,uint word_offset)238 static inline void asm_xtensa_op_s32i_n(asm_xtensa_t *as, uint reg_src, uint reg_base, uint word_offset) {
239     asm_xtensa_op16(as, ASM_XTENSA_ENCODE_RRRN(9, word_offset & 0xf, reg_base, reg_src));
240 }
241 
asm_xtensa_op_sll(asm_xtensa_t * as,uint reg_dest,uint reg_src)242 static inline void asm_xtensa_op_sll(asm_xtensa_t *as, uint reg_dest, uint reg_src) {
243     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 10, reg_dest, reg_src, 0));
244 }
245 
asm_xtensa_op_srl(asm_xtensa_t * as,uint reg_dest,uint reg_src)246 static inline void asm_xtensa_op_srl(asm_xtensa_t *as, uint reg_dest, uint reg_src) {
247     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 9, reg_dest, 0, reg_src));
248 }
249 
asm_xtensa_op_sra(asm_xtensa_t * as,uint reg_dest,uint reg_src)250 static inline void asm_xtensa_op_sra(asm_xtensa_t *as, uint reg_dest, uint reg_src) {
251     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 1, 11, reg_dest, 0, reg_src));
252 }
253 
asm_xtensa_op_ssl(asm_xtensa_t * as,uint reg_src)254 static inline void asm_xtensa_op_ssl(asm_xtensa_t *as, uint reg_src) {
255     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 4, 1, reg_src, 0));
256 }
257 
asm_xtensa_op_ssr(asm_xtensa_t * as,uint reg_src)258 static inline void asm_xtensa_op_ssr(asm_xtensa_t *as, uint reg_src) {
259     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 4, 0, reg_src, 0));
260 }
261 
asm_xtensa_op_sub(asm_xtensa_t * as,uint reg_dest,uint reg_src_a,uint reg_src_b)262 static inline void asm_xtensa_op_sub(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
263     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 12, reg_dest, reg_src_a, reg_src_b));
264 }
265 
asm_xtensa_op_xor(asm_xtensa_t * as,uint reg_dest,uint reg_src_a,uint reg_src_b)266 static inline void asm_xtensa_op_xor(asm_xtensa_t *as, uint reg_dest, uint reg_src_a, uint reg_src_b) {
267     asm_xtensa_op24(as, ASM_XTENSA_ENCODE_RRR(0, 0, 3, reg_dest, reg_src_a, reg_src_b));
268 }
269 
270 // convenience functions
271 void asm_xtensa_j_label(asm_xtensa_t *as, uint label);
272 void asm_xtensa_bccz_reg_label(asm_xtensa_t *as, uint cond, uint reg, uint label);
273 void asm_xtensa_bcc_reg_reg_label(asm_xtensa_t *as, uint cond, uint reg1, uint reg2, uint label);
274 void asm_xtensa_setcc_reg_reg_reg(asm_xtensa_t *as, uint cond, uint reg_dest, uint reg_src1, uint reg_src2);
275 size_t asm_xtensa_mov_reg_i32(asm_xtensa_t *as, uint reg_dest, uint32_t i32);
276 void asm_xtensa_mov_reg_i32_optimised(asm_xtensa_t *as, uint reg_dest, uint32_t i32);
277 void asm_xtensa_mov_local_reg(asm_xtensa_t *as, int local_num, uint reg_src);
278 void asm_xtensa_mov_reg_local(asm_xtensa_t *as, uint reg_dest, int local_num);
279 void asm_xtensa_mov_reg_local_addr(asm_xtensa_t *as, uint reg_dest, int local_num);
280 void asm_xtensa_mov_reg_pcrel(asm_xtensa_t *as, uint reg_dest, uint label);
281 void asm_xtensa_call_ind(asm_xtensa_t *as, uint idx);
282 void asm_xtensa_call_ind_win(asm_xtensa_t *as, uint idx);
283 
284 // Holds a pointer to mp_fun_table
285 #define ASM_XTENSA_REG_FUN_TABLE ASM_XTENSA_REG_A15
286 #define ASM_XTENSA_REG_FUN_TABLE_WIN ASM_XTENSA_REG_A7
287 
288 #if GENERIC_ASM_API
289 
290 // The following macros provide a (mostly) arch-independent API to
291 // generate native code, and are used by the native emitter.
292 
293 #define ASM_WORD_SIZE (4)
294 
295 #if !GENERIC_ASM_API_WIN
296 // Configuration for non-windowed calls
297 
298 #define REG_RET ASM_XTENSA_REG_A2
299 #define REG_ARG_1 ASM_XTENSA_REG_A2
300 #define REG_ARG_2 ASM_XTENSA_REG_A3
301 #define REG_ARG_3 ASM_XTENSA_REG_A4
302 #define REG_ARG_4 ASM_XTENSA_REG_A5
303 #define REG_ARG_5 ASM_XTENSA_REG_A6
304 
305 #define REG_TEMP0 ASM_XTENSA_REG_A2
306 #define REG_TEMP1 ASM_XTENSA_REG_A3
307 #define REG_TEMP2 ASM_XTENSA_REG_A4
308 
309 #define REG_LOCAL_1 ASM_XTENSA_REG_A12
310 #define REG_LOCAL_2 ASM_XTENSA_REG_A13
311 #define REG_LOCAL_3 ASM_XTENSA_REG_A14
312 #define REG_LOCAL_NUM (3)
313 
314 #define ASM_NUM_REGS_SAVED ASM_XTENSA_NUM_REGS_SAVED
315 #define REG_FUN_TABLE ASM_XTENSA_REG_FUN_TABLE
316 
317 #define ASM_ENTRY(as, nlocal)   asm_xtensa_entry((as), (nlocal))
318 #define ASM_EXIT(as)            asm_xtensa_exit((as))
319 #define ASM_CALL_IND(as, idx)   asm_xtensa_call_ind((as), (idx))
320 
321 #else
322 // Configuration for windowed calls with window size 8
323 
324 #define REG_PARENT_RET ASM_XTENSA_REG_A2
325 #define REG_PARENT_ARG_1 ASM_XTENSA_REG_A2
326 #define REG_PARENT_ARG_2 ASM_XTENSA_REG_A3
327 #define REG_PARENT_ARG_3 ASM_XTENSA_REG_A4
328 #define REG_PARENT_ARG_4 ASM_XTENSA_REG_A5
329 #define REG_RET ASM_XTENSA_REG_A10
330 #define REG_ARG_1 ASM_XTENSA_REG_A10
331 #define REG_ARG_2 ASM_XTENSA_REG_A11
332 #define REG_ARG_3 ASM_XTENSA_REG_A12
333 #define REG_ARG_4 ASM_XTENSA_REG_A13
334 
335 #define REG_TEMP0 ASM_XTENSA_REG_A10
336 #define REG_TEMP1 ASM_XTENSA_REG_A11
337 #define REG_TEMP2 ASM_XTENSA_REG_A12
338 
339 #define REG_LOCAL_1 ASM_XTENSA_REG_A4
340 #define REG_LOCAL_2 ASM_XTENSA_REG_A5
341 #define REG_LOCAL_3 ASM_XTENSA_REG_A6
342 #define REG_LOCAL_NUM (3)
343 
344 #define ASM_NUM_REGS_SAVED ASM_XTENSA_NUM_REGS_SAVED_WIN
345 #define REG_FUN_TABLE ASM_XTENSA_REG_FUN_TABLE_WIN
346 
347 #define ASM_ENTRY(as, nlocal)   asm_xtensa_entry_win((as), (nlocal))
348 #define ASM_EXIT(as)            asm_xtensa_exit_win((as))
349 #define ASM_CALL_IND(as, idx)   asm_xtensa_call_ind_win((as), (idx))
350 
351 #endif
352 
353 #define ASM_T               asm_xtensa_t
354 #define ASM_END_PASS        asm_xtensa_end_pass
355 
356 #define ASM_JUMP            asm_xtensa_j_label
357 #define ASM_JUMP_IF_REG_ZERO(as, reg, label, bool_test) \
358     asm_xtensa_bccz_reg_label(as, ASM_XTENSA_CCZ_EQ, reg, label)
359 #define ASM_JUMP_IF_REG_NONZERO(as, reg, label, bool_test) \
360     asm_xtensa_bccz_reg_label(as, ASM_XTENSA_CCZ_NE, reg, label)
361 #define ASM_JUMP_IF_REG_EQ(as, reg1, reg2, label) \
362     asm_xtensa_bcc_reg_reg_label(as, ASM_XTENSA_CC_EQ, reg1, reg2, label)
363 #define ASM_JUMP_REG(as, reg) asm_xtensa_op_jx((as), (reg))
364 
365 #define ASM_MOV_LOCAL_REG(as, local_num, reg_src) asm_xtensa_mov_local_reg((as), ASM_NUM_REGS_SAVED + (local_num), (reg_src))
366 #define ASM_MOV_REG_IMM(as, reg_dest, imm) asm_xtensa_mov_reg_i32_optimised((as), (reg_dest), (imm))
367 #define ASM_MOV_REG_IMM_FIX_U16(as, reg_dest, imm) asm_xtensa_mov_reg_i32((as), (reg_dest), (imm))
368 #define ASM_MOV_REG_IMM_FIX_WORD(as, reg_dest, imm) asm_xtensa_mov_reg_i32((as), (reg_dest), (imm))
369 #define ASM_MOV_REG_LOCAL(as, reg_dest, local_num) asm_xtensa_mov_reg_local((as), (reg_dest), ASM_NUM_REGS_SAVED + (local_num))
370 #define ASM_MOV_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_mov_n((as), (reg_dest), (reg_src))
371 #define ASM_MOV_REG_LOCAL_ADDR(as, reg_dest, local_num) asm_xtensa_mov_reg_local_addr((as), (reg_dest), ASM_NUM_REGS_SAVED + (local_num))
372 #define ASM_MOV_REG_PCREL(as, reg_dest, label) asm_xtensa_mov_reg_pcrel((as), (reg_dest), (label))
373 
374 #define ASM_LSL_REG_REG(as, reg_dest, reg_shift) \
375     do { \
376         asm_xtensa_op_ssl((as), (reg_shift)); \
377         asm_xtensa_op_sll((as), (reg_dest), (reg_dest)); \
378     } while (0)
379 #define ASM_LSR_REG_REG(as, reg_dest, reg_shift) \
380     do { \
381         asm_xtensa_op_ssr((as), (reg_shift)); \
382         asm_xtensa_op_srl((as), (reg_dest), (reg_dest)); \
383     } while (0)
384 #define ASM_ASR_REG_REG(as, reg_dest, reg_shift) \
385     do { \
386         asm_xtensa_op_ssr((as), (reg_shift)); \
387         asm_xtensa_op_sra((as), (reg_dest), (reg_dest)); \
388     } while (0)
389 #define ASM_OR_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_or((as), (reg_dest), (reg_dest), (reg_src))
390 #define ASM_XOR_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_xor((as), (reg_dest), (reg_dest), (reg_src))
391 #define ASM_AND_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_and((as), (reg_dest), (reg_dest), (reg_src))
392 #define ASM_ADD_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_add_n((as), (reg_dest), (reg_dest), (reg_src))
393 #define ASM_SUB_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_sub((as), (reg_dest), (reg_dest), (reg_src))
394 #define ASM_MUL_REG_REG(as, reg_dest, reg_src) asm_xtensa_op_mull((as), (reg_dest), (reg_dest), (reg_src))
395 
396 #define ASM_LOAD_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) asm_xtensa_op_l32i_n((as), (reg_dest), (reg_base), (word_offset))
397 #define ASM_LOAD8_REG_REG(as, reg_dest, reg_base) asm_xtensa_op_l8ui((as), (reg_dest), (reg_base), 0)
398 #define ASM_LOAD16_REG_REG(as, reg_dest, reg_base) asm_xtensa_op_l16ui((as), (reg_dest), (reg_base), 0)
399 #define ASM_LOAD32_REG_REG(as, reg_dest, reg_base) asm_xtensa_op_l32i_n((as), (reg_dest), (reg_base), 0)
400 
401 #define ASM_STORE_REG_REG_OFFSET(as, reg_dest, reg_base, word_offset) asm_xtensa_op_s32i_n((as), (reg_dest), (reg_base), (word_offset))
402 #define ASM_STORE8_REG_REG(as, reg_src, reg_base) asm_xtensa_op_s8i((as), (reg_src), (reg_base), 0)
403 #define ASM_STORE16_REG_REG(as, reg_src, reg_base) asm_xtensa_op_s16i((as), (reg_src), (reg_base), 0)
404 #define ASM_STORE32_REG_REG(as, reg_src, reg_base) asm_xtensa_op_s32i_n((as), (reg_src), (reg_base), 0)
405 
406 #endif // GENERIC_ASM_API
407 
408 #endif // MICROPY_INCLUDED_PY_ASMXTENSA_H
409