1-- Module generated by TTA Codesign Environment 2-- 3-- Generated on Sun Jul 7 16:19:19 2019 4-- 5-- Function Unit: alu_comp 6-- 7-- Operations: 8-- add : 0 9-- and : 1 10-- eq : 2 11-- gt : 3 12-- gtu : 4 13-- ior : 5 14-- mul : 6 15-- shl : 7 16-- shr : 8 17-- shru : 9 18-- sub : 10 19-- xor : 11 20-- 21 22library ieee; 23use ieee.std_logic_1164.all; 24use ieee.numeric_std.all; 25use ieee.std_logic_misc.all; 26 27entity fu_alu_comp is 28 port ( 29 clk : in std_logic; 30 rstx : in std_logic; 31 glock_in : in std_logic; 32 glockreq_out : out std_logic; 33 operation_in : in std_logic_vector(4-1 downto 0); 34 data_in1t_in : in std_logic_vector(32-1 downto 0); 35 load_in1t_in : in std_logic; 36 data_in2_in : in std_logic_vector(32-1 downto 0); 37 load_in2_in : in std_logic; 38 data_out1_out : out std_logic_vector(32-1 downto 0); 39 data_out2_out : out std_logic_vector(32-1 downto 0); 40 data_out3_out : out std_logic_vector(32-1 downto 0)); 41end entity fu_alu_comp; 42 43architecture rtl of fu_alu_comp is 44 45 constant op_add_c : std_logic_vector(3 downto 0) := "0000"; 46 constant op_and_c : std_logic_vector(3 downto 0) := "0001"; 47 constant op_eq_c : std_logic_vector(3 downto 0) := "0010"; 48 constant op_gt_c : std_logic_vector(3 downto 0) := "0011"; 49 constant op_gtu_c : std_logic_vector(3 downto 0) := "0100"; 50 constant op_ior_c : std_logic_vector(3 downto 0) := "0101"; 51 constant op_mul_c : std_logic_vector(3 downto 0) := "0110"; 52 constant op_shl_c : std_logic_vector(3 downto 0) := "0111"; 53 constant op_shr_c : std_logic_vector(3 downto 0) := "1000"; 54 constant op_shru_c : std_logic_vector(3 downto 0) := "1001"; 55 constant op_sub_c : std_logic_vector(3 downto 0) := "1010"; 56 constant op_xor_c : std_logic_vector(3 downto 0) := "1011"; 57 58 signal operation : std_logic_vector(3 downto 0); 59 signal mul_dsp_2cycle_1_clk : std_logic; 60 signal mul_dsp_2cycle_1_rstx : std_logic; 61 signal mul_dsp_2cycle_1_glock_in : std_logic; 62 signal mul_dsp_2cycle_1_load_in : std_logic; 63 signal mul_dsp_2cycle_1_operand_a_in : std_logic_vector(31+1-1 downto 0); 64 signal mul_dsp_2cycle_1_operand_b_in : std_logic_vector(31+1-1 downto 0); 65 signal mul_dsp_2cycle_1_operand_c_in : std_logic_vector(31+1-1 downto 0); 66 signal mul_dsp_2cycle_1_result_out : std_logic_vector(31+1-1 downto 0); 67 signal generic_sru_1_clk : std_logic; 68 signal generic_sru_1_opa_i : std_logic_vector(31+1-1 downto 0); 69 signal generic_sru_1_opb_i : std_logic_vector(31+1-1 downto 0); 70 signal generic_sru_1_shift_dir_i : std_logic; 71 signal generic_sru_1_arith_shift_i : std_logic; 72 signal generic_sru_1_rnd_en_i : std_logic; 73 signal generic_sru_1_rnd_mode_i : std_logic; 74 signal generic_sru_1_data_o : std_logic_vector(31+1-1 downto 0); 75 signal add_op1 : std_logic_vector(31 downto 0); 76 signal add_op2 : std_logic_vector(31 downto 0); 77 signal add_op3 : std_logic_vector(31 downto 0); 78 signal and_op1 : std_logic_vector(31 downto 0); 79 signal and_op2 : std_logic_vector(31 downto 0); 80 signal and_op3 : std_logic_vector(31 downto 0); 81 signal eq_op1 : std_logic_vector(31 downto 0); 82 signal eq_op2 : std_logic_vector(31 downto 0); 83 signal eq_op3 : std_logic; 84 signal gt_op1 : std_logic_vector(31 downto 0); 85 signal gt_op2 : std_logic_vector(31 downto 0); 86 signal gt_op3 : std_logic; 87 signal gtu_op1 : std_logic_vector(31 downto 0); 88 signal gtu_op2 : std_logic_vector(31 downto 0); 89 signal gtu_op3 : std_logic; 90 signal ior_op1 : std_logic_vector(31 downto 0); 91 signal ior_op2 : std_logic_vector(31 downto 0); 92 signal ior_op3 : std_logic_vector(31 downto 0); 93 signal mul_op1 : std_logic_vector(31 downto 0); 94 signal mul_op2 : std_logic_vector(31 downto 0); 95 signal mul_op3 : std_logic_vector(31 downto 0); 96 signal shl_op1 : std_logic_vector(31 downto 0); 97 signal shl_op2 : std_logic_vector(4 downto 0); 98 signal shl_op3 : std_logic_vector(31 downto 0); 99 signal shr_op1 : std_logic_vector(31 downto 0); 100 signal shr_op2 : std_logic_vector(4 downto 0); 101 signal shr_op3 : std_logic_vector(31 downto 0); 102 signal shru_op1 : std_logic_vector(31 downto 0); 103 signal shru_op2 : std_logic_vector(4 downto 0); 104 signal shru_op3 : std_logic_vector(31 downto 0); 105 signal sub_op1 : std_logic_vector(31 downto 0); 106 signal sub_op2 : std_logic_vector(31 downto 0); 107 signal sub_op3 : std_logic_vector(31 downto 0); 108 signal xor_op1 : std_logic_vector(31 downto 0); 109 signal xor_op2 : std_logic_vector(31 downto 0); 110 signal xor_op3 : std_logic_vector(31 downto 0); 111 signal data_in1t : std_logic_vector(31 downto 0); 112 signal data_in2 : std_logic_vector(31 downto 0); 113 114 signal shadow_in2_r : std_logic_vector(31 downto 0); 115 signal operation_1_r : std_logic_vector(3 downto 0); 116 signal optrig_1_r : std_logic; 117 signal operation_2_r : std_logic_vector(3 downto 0); 118 signal optrig_2_r : std_logic; 119 signal data_in1t_1_r : std_logic_vector(31 downto 0); 120 signal data_in2_1_r : std_logic_vector(31 downto 0); 121 signal trigger_in1t_1_r : std_logic; 122 signal trigger_in2_1_r : std_logic; 123 signal data_in1t_2_r : std_logic_vector(31 downto 0); 124 signal data_in1t_3_r : std_logic_vector(31 downto 0); 125 signal trigger_in1t_2_r : std_logic; 126 signal data_in2_2_r : std_logic_vector(31 downto 0); 127 signal data_in2_3_r : std_logic_vector(31 downto 0); 128 signal trigger_in2_2_r : std_logic; 129 signal optrig_3_r : std_logic; 130 signal operation_3_r : std_logic_vector(3 downto 0); 131 signal data_out1_out_r : std_logic_vector(31 downto 0); 132 signal data_out2_out_r : std_logic_vector(31 downto 0); 133 signal data_out3_out_r : std_logic_vector(31 downto 0); 134 135 component mul_dsp48 is 136 generic ( 137 latency_g : integer); 138 port ( 139 clk : in std_logic; 140 rstx : in std_logic; 141 glock_in : in std_logic; 142 load_in : in std_logic; 143 operand_a_in : in std_logic_vector(31+1-1 downto 0); 144 operand_b_in : in std_logic_vector(31+1-1 downto 0); 145 operand_c_in : in std_logic_vector(31+1-1 downto 0); 146 result_out : out std_logic_vector(31+1-1 downto 0)); 147 end component mul_dsp48; 148 149 component generic_sru is 150 port ( 151 clk : in std_logic; 152 opa_i : in std_logic_vector(31+1-1 downto 0); 153 opb_i : in std_logic_vector(31+1-1 downto 0); 154 shift_dir_i : in std_logic; 155 arith_shift_i : in std_logic; 156 rnd_en_i : in std_logic; 157 rnd_mode_i : in std_logic; 158 data_o : out std_logic_vector(31+1-1 downto 0)); 159 end component generic_sru; 160 161begin 162 163 mul_dsp_2cycle_1 : mul_dsp48 164 generic map ( 165 latency_g => 2) 166 port map ( 167 clk => clk, 168 rstx => rstx, 169 glock_in => mul_dsp_2cycle_1_glock_in, 170 load_in => mul_dsp_2cycle_1_load_in, 171 operand_a_in => mul_dsp_2cycle_1_operand_a_in, 172 operand_b_in => mul_dsp_2cycle_1_operand_b_in, 173 operand_c_in => mul_dsp_2cycle_1_operand_c_in, 174 result_out => mul_dsp_2cycle_1_result_out); 175 176 generic_sru_1 : generic_sru 177 port map ( 178 clk => clk, 179 opa_i => generic_sru_1_opa_i, 180 opb_i => generic_sru_1_opb_i, 181 shift_dir_i => generic_sru_1_shift_dir_i, 182 arith_shift_i => generic_sru_1_arith_shift_i, 183 rnd_en_i => generic_sru_1_rnd_en_i, 184 rnd_mode_i => generic_sru_1_rnd_mode_i, 185 data_o => generic_sru_1_data_o); 186 187 add_op1 <= data_in1t_1_r; 188 add_op2 <= data_in2_1_r; 189 and_op1 <= data_in2_1_r; 190 and_op2 <= data_in1t_1_r; 191 eq_op1 <= data_in1t_1_r; 192 eq_op2 <= data_in2_1_r; 193 gt_op1 <= data_in1t_1_r; 194 gt_op2 <= data_in2_1_r; 195 gtu_op1 <= data_in1t_1_r; 196 gtu_op2 <= data_in2_1_r; 197 ior_op1 <= data_in2_1_r; 198 ior_op2 <= data_in1t_1_r; 199 mul_op1 <= data_in2_1_r; 200 mul_op2 <= data_in1t_1_r; 201 shl_op1 <= data_in1t_2_r; 202 shl_op2 <= data_in2_2_r(4 downto 0); 203 shr_op1 <= data_in1t_2_r; 204 shr_op2 <= data_in2_2_r(4 downto 0); 205 shru_op1 <= data_in1t_2_r; 206 shru_op2 <= data_in2_2_r(4 downto 0); 207 sub_op1 <= data_in1t_1_r; 208 sub_op2 <= data_in2_1_r; 209 xor_op1 <= data_in2_1_r; 210 xor_op2 <= data_in1t_1_r; 211 data_in1t <= data_in1t_in; 212 213 shadow_in2_sp : process(clk, rstx) 214 begin 215 if rstx = '0' then 216 shadow_in2_r <= (others => '0'); 217 elsif clk = '1' and clk'event then 218 if ((glock_in = '0') and (load_in2_in = '1')) then 219 shadow_in2_r <= data_in2_in; 220 end if; 221 end if; 222 end process shadow_in2_sp; 223 224 shadow_in2_cp : process(shadow_in2_r, data_in2_in, load_in2_in, load_in1t_in) 225 begin 226 if ((load_in1t_in = '1') and (load_in2_in = '1')) then 227 data_in2 <= data_in2_in; 228 else 229 data_in2 <= shadow_in2_r; 230 end if; 231 end process shadow_in2_cp; 232 233 operations_actual_cp : process(operation_2_r, shru_op2, shr_op2, generic_sru_1_data_o, shl_op2, eq_op2, eq_op1, ior_op2, and_op2, and_op1, add_op2, add_op1, gt_op2, xor_op2, glock_in, mul_op1, operation_1_r, mul_dsp_2cycle_1_result_out, mul_op2, xor_op1, gt_op1, gtu_op1, shru_op1, gtu_op2, ior_op1, sub_op2, sub_op1, shr_op1, shl_op1) 234 begin 235 add_op3 <= (others => '-'); 236 and_op3 <= (others => '-'); 237 eq_op3 <= '-'; 238 gt_op3 <= '-'; 239 gtu_op3 <= '-'; 240 ior_op3 <= (others => '-'); 241 mul_op3 <= (others => '-'); 242 shl_op3 <= (others => '-'); 243 shr_op3 <= (others => '-'); 244 shru_op3 <= (others => '-'); 245 sub_op3 <= (others => '-'); 246 xor_op3 <= (others => '-'); 247 add_op3 <= (others => '-'); 248 and_op3 <= (others => '-'); 249 eq_op3 <= '-'; 250 eq_op3 <= '-'; 251 gt_op3 <= '-'; 252 gt_op3 <= '-'; 253 gtu_op3 <= '-'; 254 gtu_op3 <= '-'; 255 ior_op3 <= (others => '-'); 256 mul_dsp_2cycle_1_glock_in <= '-'; 257 mul_op3 <= (others => '-'); 258 mul_dsp_2cycle_1_load_in <= '-'; 259 mul_dsp_2cycle_1_operand_a_in <= (others => '-'); 260 mul_dsp_2cycle_1_operand_b_in <= (others => '-'); 261 mul_dsp_2cycle_1_operand_c_in <= (others => '-'); 262 mul_dsp_2cycle_1_load_in <= '-'; 263 mul_dsp_2cycle_1_glock_in <= glock_in; 264 mul_op3 <= mul_dsp_2cycle_1_result_out; 265 mul_dsp_2cycle_1_load_in <= '0'; 266 sub_op3 <= (others => '-'); 267 xor_op3 <= (others => '-'); 268 case operation_1_r is 269 when op_add_c => 270 add_op3 <= std_logic_vector(signed(add_op1) + signed(add_op2)); 271 when op_and_c => 272 and_op3 <= and_op1 and and_op2; 273 when op_eq_c => 274 if eq_op1 = eq_op2 then 275 eq_op3 <= '1'; 276 else 277 eq_op3 <= '0'; 278 end if; 279 when op_gt_c => 280 if signed(gt_op1) > signed(gt_op2) then 281 gt_op3 <= '1'; 282 else 283 gt_op3 <= '0'; 284 end if; 285 when op_gtu_c => 286 if unsigned(gtu_op1) > unsigned(gtu_op2) then 287 gtu_op3 <= '1'; 288 else 289 gtu_op3 <= '0'; 290 end if; 291 when op_ior_c => 292 ior_op3 <= ior_op1 or ior_op2; 293 when op_mul_c => 294 mul_dsp_2cycle_1_operand_a_in <= mul_op1; 295 mul_dsp_2cycle_1_operand_b_in <= mul_op2; 296 mul_dsp_2cycle_1_operand_c_in <= (others => '0'); 297 mul_dsp_2cycle_1_load_in <= '1'; 298 when op_sub_c => 299 sub_op3 <= std_logic_vector(signed(sub_op1) - signed(sub_op2)); 300 when op_xor_c => 301 xor_op3 <= xor_op1 xor xor_op2; 302 when others => 303 end case; 304 generic_sru_1_opa_i <= (others => '-'); 305 generic_sru_1_opb_i <= (others => '-'); 306 generic_sru_1_shift_dir_i <= '-'; 307 generic_sru_1_arith_shift_i <= '-'; 308 generic_sru_1_rnd_en_i <= '-'; 309 generic_sru_1_rnd_mode_i <= '-'; 310 shl_op3 <= (others => '-'); 311 generic_sru_1_opa_i <= (others => '-'); 312 generic_sru_1_opb_i <= (others => '-'); 313 generic_sru_1_shift_dir_i <= '-'; 314 generic_sru_1_arith_shift_i <= '-'; 315 generic_sru_1_rnd_en_i <= '-'; 316 generic_sru_1_rnd_mode_i <= '-'; 317 shr_op3 <= (others => '-'); 318 generic_sru_1_opa_i <= (others => '-'); 319 generic_sru_1_opb_i <= (others => '-'); 320 generic_sru_1_shift_dir_i <= '-'; 321 generic_sru_1_arith_shift_i <= '-'; 322 generic_sru_1_rnd_en_i <= '-'; 323 generic_sru_1_rnd_mode_i <= '-'; 324 shru_op3 <= (others => '-'); 325 case operation_2_r is 326 when op_shl_c => 327 generic_sru_1_opa_i <= shl_op1; 328 generic_sru_1_opb_i <= "000000000000000000000000000" & shl_op2; 329 generic_sru_1_shift_dir_i <= '1'; -- 0: right, 1: left (shift dreiction) 330 generic_sru_1_arith_shift_i <= '0'; -- 0: logical, 1: arithmetical (only for right shifts) 331 generic_sru_1_rnd_en_i <= '0'; 332 generic_sru_1_rnd_mode_i <= '0'; 333 shl_op3 <= generic_sru_1_data_o; 334 when op_shr_c => 335 generic_sru_1_opa_i <= shr_op1; 336 generic_sru_1_opb_i <= "000000000000000000000000000" & shr_op2; 337 generic_sru_1_shift_dir_i <= '0'; -- 0: right, 1: left (shift dreiction) 338 generic_sru_1_arith_shift_i <= '1'; -- 0: logical, 1: arithmetical (only for right shifts) 339 generic_sru_1_rnd_en_i <= '0'; 340 generic_sru_1_rnd_mode_i <= '0'; 341 shr_op3 <= generic_sru_1_data_o; 342 when op_shru_c => 343 generic_sru_1_opa_i <= shru_op1; 344 generic_sru_1_opb_i <= "000000000000000000000000000" & shru_op2; 345 generic_sru_1_shift_dir_i <= '0'; -- 0: right, 1: left (shift dreiction) 346 generic_sru_1_arith_shift_i <= '0'; -- 0: logical, 1: arithmetical (only for right shifts) 347 generic_sru_1_rnd_en_i <= '0'; 348 generic_sru_1_rnd_mode_i <= '0'; 349 shru_op3 <= generic_sru_1_data_o; 350 when others => 351 end case; 352 end process operations_actual_cp; 353 354 operation <= operation_3_r; 355 356 operation_input_sp : process(clk, rstx) 357 begin 358 if rstx = '0' then 359 data_in2_1_r <= (others => '0'); 360 data_in1t_1_r <= (others => '0'); 361 operation_1_r <= (others => '0'); 362 operation_3_r <= (others => '0'); 363 optrig_3_r <= '0'; 364 trigger_in2_2_r <= '0'; 365 data_in1t_2_r <= (others => '0'); 366 data_in2_3_r <= (others => '0'); 367 trigger_in2_1_r <= '0'; 368 trigger_in1t_2_r <= '0'; 369 data_in2_2_r <= (others => '0'); 370 operation_2_r <= (others => '0'); 371 trigger_in1t_1_r <= '0'; 372 data_in1t_3_r <= (others => '0'); 373 optrig_1_r <= '0'; 374 optrig_2_r <= '0'; 375 elsif clk = '1' and clk'event then 376 if (glock_in = '0') then 377 trigger_in1t_1_r <= load_in1t_in; 378 trigger_in1t_2_r <= trigger_in1t_1_r; 379 trigger_in2_1_r <= load_in1t_in; 380 trigger_in2_2_r <= trigger_in2_1_r; 381 if (trigger_in1t_1_r = '1') then 382 data_in1t_2_r <= data_in1t_1_r; 383 end if; 384 if (trigger_in1t_2_r = '1') then 385 data_in1t_3_r <= data_in1t_2_r; 386 end if; 387 if (trigger_in2_1_r = '1') then 388 data_in2_2_r <= data_in2_1_r; 389 end if; 390 if (trigger_in2_2_r = '1') then 391 data_in2_3_r <= data_in2_2_r; 392 end if; 393 optrig_1_r <= '0'; 394 optrig_2_r <= optrig_1_r; 395 if (optrig_1_r = '1') then 396 operation_2_r <= operation_1_r; 397 end if; 398 optrig_3_r <= optrig_2_r; 399 if (optrig_2_r = '1') then 400 operation_3_r <= operation_2_r; 401 end if; 402 end if; 403 if ((glock_in = '0') and (load_in1t_in = '1')) then 404 case operation_in is 405 when op_add_c => 406 operation_1_r <= operation_in; 407 data_in1t_1_r <= data_in1t; 408 optrig_1_r <= '1'; 409 data_in2_1_r <= data_in2; 410 optrig_1_r <= '1'; 411 when op_and_c => 412 operation_1_r <= operation_in; 413 data_in2_1_r <= data_in2; 414 optrig_1_r <= '1'; 415 data_in1t_1_r <= data_in1t; 416 optrig_1_r <= '1'; 417 when op_eq_c => 418 operation_1_r <= operation_in; 419 data_in1t_1_r <= data_in1t; 420 optrig_1_r <= '1'; 421 data_in2_1_r <= data_in2; 422 optrig_1_r <= '1'; 423 when op_gt_c => 424 operation_1_r <= operation_in; 425 data_in1t_1_r <= data_in1t; 426 optrig_1_r <= '1'; 427 data_in2_1_r <= data_in2; 428 optrig_1_r <= '1'; 429 when op_gtu_c => 430 operation_1_r <= operation_in; 431 data_in1t_1_r <= data_in1t; 432 optrig_1_r <= '1'; 433 data_in2_1_r <= data_in2; 434 optrig_1_r <= '1'; 435 when op_ior_c => 436 operation_1_r <= operation_in; 437 data_in2_1_r <= data_in2; 438 optrig_1_r <= '1'; 439 data_in1t_1_r <= data_in1t; 440 optrig_1_r <= '1'; 441 when op_mul_c => 442 operation_1_r <= operation_in; 443 data_in2_1_r <= data_in2; 444 optrig_1_r <= '1'; 445 data_in1t_1_r <= data_in1t; 446 optrig_1_r <= '1'; 447 when op_shl_c => 448 operation_1_r <= operation_in; 449 data_in1t_1_r <= data_in1t; 450 optrig_1_r <= '1'; 451 data_in2_1_r <= data_in2; 452 optrig_1_r <= '1'; 453 when op_shr_c => 454 operation_1_r <= operation_in; 455 data_in1t_1_r <= data_in1t; 456 optrig_1_r <= '1'; 457 data_in2_1_r <= data_in2; 458 optrig_1_r <= '1'; 459 when op_shru_c => 460 operation_1_r <= operation_in; 461 data_in1t_1_r <= data_in1t; 462 optrig_1_r <= '1'; 463 data_in2_1_r <= data_in2; 464 optrig_1_r <= '1'; 465 when op_sub_c => 466 operation_1_r <= operation_in; 467 data_in1t_1_r <= data_in1t; 468 optrig_1_r <= '1'; 469 data_in2_1_r <= data_in2; 470 optrig_1_r <= '1'; 471 when op_xor_c => 472 operation_1_r <= operation_in; 473 data_in2_1_r <= data_in2; 474 optrig_1_r <= '1'; 475 data_in1t_1_r <= data_in1t; 476 optrig_1_r <= '1'; 477 when others => 478 end case; 479 end if; 480 end if; 481 end process operation_input_sp; 482 data_out1_out <= data_out1_out_r; 483 data_out2_out <= data_out2_out_r; 484 data_out3_out <= data_out3_out_r; 485 486 operations_output_sp : process(clk, rstx) 487 begin 488 if rstx = '0' then 489 data_out3_out_r <= (others => '0'); 490 data_out2_out_r <= (others => '0'); 491 data_out1_out_r <= (others => '0'); 492 elsif clk = '1' and clk'event then 493 if ((glock_in = '0') and (optrig_1_r = '1')) then 494 case operation_1_r is 495 when op_add_c => 496 data_out1_out_r <= add_op3; 497 when op_and_c => 498 data_out1_out_r <= and_op3; 499 when op_eq_c => 500 data_out1_out_r <= ((32-1 downto 1 => '0') & eq_op3); 501 when op_gt_c => 502 data_out1_out_r <= ((32-1 downto 1 => '0') & gt_op3); 503 when op_gtu_c => 504 data_out1_out_r <= ((32-1 downto 1 => '0') & gtu_op3); 505 when op_ior_c => 506 data_out1_out_r <= ior_op3; 507 when op_sub_c => 508 data_out1_out_r <= sub_op3; 509 when op_xor_c => 510 data_out1_out_r <= xor_op3; 511 when others => 512 end case; 513 end if; 514 if ((glock_in = '0') and (optrig_2_r = '1')) then 515 case operation_2_r is 516 when op_shl_c => 517 data_out2_out_r <= shl_op3; 518 when op_shr_c => 519 data_out2_out_r <= shr_op3; 520 when op_shru_c => 521 data_out2_out_r <= shru_op3; 522 when others => 523 end case; 524 end if; 525 if ((glock_in = '0') and (optrig_3_r = '1')) then 526 case operation_3_r is 527 when op_mul_c => 528 data_out3_out_r <= mul_op3; 529 when others => 530 end case; 531 end if; 532 end if; 533 end process operations_output_sp; 534 535 glockreq_out <= '0'; 536 537end architecture rtl; 538 539