1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp -x c -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 
4 // RUN: %clang_cc1 -verify -triple powerpc64le-unknown-linux-gnu -fopenmp-simd -x c -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}"
5 
6 int a;
7 
foo()8 void foo() {
9   int(*b)[a];
10   int *(**c)[a];
11 #pragma omp parallel if (0)
12   b[0][0] = c[0][a][0][a];
13 }
14 
15 
bar(int n,int * a)16 void bar(int n, int *a) {
17   // expected-warning@+1 {{incompatible pointer types initializing 'int (*)[n]' with an expression of type 'int **'}}
18   int(*p)[n] = &a;
19 #pragma omp parallel if(0)
20   // expected-warning@+1 {{comparison of distinct pointer types ('int (*)[n]' and 'int **')}}
21   if (p == &a) {
22   }
23 }
24 
25 // CHECK1-LABEL: define {{[^@]+}}@foo
26 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
27 // CHECK1-NEXT:  entry:
28 // CHECK1-NEXT:    [[B:%.*]] = alloca i32*, align 8
29 // CHECK1-NEXT:    [[C:%.*]] = alloca i32***, align 8
30 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
31 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
32 // CHECK1-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
33 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
34 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* @a, align 4
35 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
36 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* @a, align 4
37 // CHECK1-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
38 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
39 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
40 // CHECK1-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]], i32** [[B]], i64 [[TMP4]], i32**** [[C]]) #[[ATTR2:[0-9]+]]
41 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
42 // CHECK1-NEXT:    ret void
43 //
44 //
45 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
46 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32** nonnull align 8 dereferenceable(8) [[B:%.*]], i64 [[VLA1:%.*]], i32**** nonnull align 8 dereferenceable(8) [[C:%.*]]) #[[ATTR1:[0-9]+]] {
47 // CHECK1-NEXT:  entry:
48 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
49 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
50 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
51 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i32**, align 8
52 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
53 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i32****, align 8
54 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
55 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
56 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
57 // CHECK1-NEXT:    store i32** [[B]], i32*** [[B_ADDR]], align 8
58 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
59 // CHECK1-NEXT:    store i32**** [[C]], i32***** [[C_ADDR]], align 8
60 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
61 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32**, i32*** [[B_ADDR]], align 8
62 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
63 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32****, i32***** [[C_ADDR]], align 8
64 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32***, i32**** [[TMP3]], align 8
65 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i32**, i32*** [[TMP4]], i64 0
66 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32**, i32*** [[ARRAYIDX]], align 8
67 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* @a, align 4
68 // CHECK1-NEXT:    [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
69 // CHECK1-NEXT:    [[TMP7:%.*]] = mul nsw i64 [[IDXPROM]], [[TMP2]]
70 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds i32*, i32** [[TMP5]], i64 [[TMP7]]
71 // CHECK1-NEXT:    [[ARRAYIDX4:%.*]] = getelementptr inbounds i32*, i32** [[ARRAYIDX3]], i64 0
72 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32*, i32** [[ARRAYIDX4]], align 8
73 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* @a, align 4
74 // CHECK1-NEXT:    [[IDXPROM5:%.*]] = sext i32 [[TMP9]] to i64
75 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, i32* [[TMP8]], i64 [[IDXPROM5]]
76 // CHECK1-NEXT:    [[TMP10:%.*]] = load i32, i32* [[ARRAYIDX6]], align 4
77 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32*, i32** [[TMP1]], align 8
78 // CHECK1-NEXT:    [[TMP12:%.*]] = mul nsw i64 0, [[TMP0]]
79 // CHECK1-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, i32* [[TMP11]], i64 [[TMP12]]
80 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds i32, i32* [[ARRAYIDX7]], i64 0
81 // CHECK1-NEXT:    store i32 [[TMP10]], i32* [[ARRAYIDX8]], align 4
82 // CHECK1-NEXT:    ret void
83 //
84 //
85 // CHECK1-LABEL: define {{[^@]+}}@bar
86 // CHECK1-SAME: (i32 signext [[N:%.*]], i32* [[A:%.*]]) #[[ATTR0]] {
87 // CHECK1-NEXT:  entry:
88 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
89 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32*, align 8
90 // CHECK1-NEXT:    [[P:%.*]] = alloca i32*, align 8
91 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
92 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
93 // CHECK1-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
94 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
95 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
96 // CHECK1-NEXT:    store i32* [[A]], i32** [[A_ADDR]], align 8
97 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
98 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
99 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i32** [[A_ADDR]] to i32*
100 // CHECK1-NEXT:    store i32* [[TMP3]], i32** [[P]], align 8
101 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
102 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
103 // CHECK1-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]], i32** [[P]], i32** [[A_ADDR]]) #[[ATTR2]]
104 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
105 // CHECK1-NEXT:    ret void
106 //
107 //
108 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
109 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[VLA:%.*]], i32** nonnull align 8 dereferenceable(8) [[P:%.*]], i32** nonnull align 8 dereferenceable(8) [[A:%.*]]) #[[ATTR1]] {
110 // CHECK1-NEXT:  entry:
111 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
112 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
113 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
114 // CHECK1-NEXT:    [[P_ADDR:%.*]] = alloca i32**, align 8
115 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32**, align 8
116 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
117 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
118 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
119 // CHECK1-NEXT:    store i32** [[P]], i32*** [[P_ADDR]], align 8
120 // CHECK1-NEXT:    store i32** [[A]], i32*** [[A_ADDR]], align 8
121 // CHECK1-NEXT:    [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
122 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32**, i32*** [[P_ADDR]], align 8
123 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32**, i32*** [[A_ADDR]], align 8
124 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32*, i32** [[TMP1]], align 8
125 // CHECK1-NEXT:    [[TMP4:%.*]] = bitcast i32** [[TMP2]] to i32*
126 // CHECK1-NEXT:    [[CMP:%.*]] = icmp eq i32* [[TMP3]], [[TMP4]]
127 // CHECK1-NEXT:    br i1 [[CMP]], label [[IF_THEN:%.*]], label [[IF_END:%.*]]
128 // CHECK1:       if.then:
129 // CHECK1-NEXT:    br label [[IF_END]]
130 // CHECK1:       if.end:
131 // CHECK1-NEXT:    ret void
132 //
133 //