1//===-- HexagonRegisterInfo.td - Hexagon Register defs -----*- tablegen -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9//===----------------------------------------------------------------------===// 10// Declarations that describe the Hexagon register file. 11//===----------------------------------------------------------------------===// 12 13let Namespace = "Hexagon" in { 14 15 class HexagonReg<bits<5> num, string n, list<string> alt = [], 16 list<Register> alias = []> : Register<n, alt> { 17 let Aliases = alias; 18 let HWEncoding{4-0} = num; 19 } 20 21 // These registers are used to preserve a distinction between 22 // vector register pairs of differing order. 23 class HexagonFakeReg<string n> : Register<n> { 24 let isArtificial = 1; 25 } 26 27 class HexagonDoubleReg<bits<5> num, string n, list<Register> subregs, 28 list<string> alt = []> : 29 RegisterWithSubRegs<n, subregs> { 30 let AltNames = alt; 31 let HWEncoding{4-0} = num; 32 } 33 34 // Registers are identified with 5-bit ID numbers. 35 // Ri - 32-bit integer registers. 36 class Ri<bits<5> num, string n, list<string> alt = []> : 37 HexagonReg<num, n, alt>; 38 39 // Rp - false/pseudo registers. These registers are used 40 // to provide a distinct set of aliases for both styles of vector 41 // register pairs without encountering subregister indexing constraints. 42 class R_fake<string n> : 43 HexagonFakeReg<n>; 44 45 46 // Rf - 32-bit floating-point registers. 47 class Rf<bits<5> num, string n> : HexagonReg<num, n>; 48 49 // Rd - 64-bit registers. 50 class Rd<bits<5> num, string n, list<Register> subregs, 51 list<string> alt = []> : 52 HexagonDoubleReg<num, n, subregs, alt> { 53 let SubRegs = subregs; 54 } 55 56 // Rp - predicate registers 57 class Rp<bits<5> num, string n> : HexagonReg<num, n>; 58 59 60 // Rq - vector predicate registers 61 class Rq<bits<3> num, string n> : Register<n, []> { 62 let HWEncoding{2-0} = num; 63 } 64 65 // Rc - control registers 66 class Rc<bits<5> num, string n, 67 list<string> alt = [], list<Register> alias = []> : 68 HexagonReg<num, n, alt, alias>; 69 70 // Rcc - 64-bit control registers. 71 class Rcc<bits<5> num, string n, list<Register> subregs, 72 list<string> alt = []> : 73 HexagonDoubleReg<num, n, subregs, alt> { 74 let SubRegs = subregs; 75 } 76 77 // Mx - address modifier registers 78 class Mx<bits<1> num, string n> : Register<n, []> { 79 let HWEncoding{0} = num; 80 } 81 82 // Rg - Guest/Hypervisor registers 83 class Rg<bits<5> num, string n, 84 list<string> alt = [], list<Register> alias = []> : 85 HexagonReg<num, n, alt, alias>; 86 87 // Rgg - 64-bit Guest/Hypervisor registers 88 class Rgg<bits<5> num, string n, list<Register> subregs> : 89 HexagonDoubleReg<num, n, subregs> { 90 let SubRegs = subregs; 91 } 92 93 def isub_lo : SubRegIndex<32>; 94 def isub_hi : SubRegIndex<32, 32>; 95 def vsub_lo : SubRegIndex<512>; 96 def vsub_hi : SubRegIndex<512, 512>; 97 def vsub_fake: SubRegIndex<512>; 98 def wsub_lo : SubRegIndex<1024>; 99 def wsub_hi : SubRegIndex<1024, 1024>; 100 def subreg_overflow : SubRegIndex<1, 0>; 101 102 // Integer registers. 103 foreach i = 0-28 in { 104 def R#i : Ri<i, "r"#i>, DwarfRegNum<[i]>; 105 } 106 def R29 : Ri<29, "r29", ["sp"]>, DwarfRegNum<[29]>; 107 def R30 : Ri<30, "r30", ["fp"]>, DwarfRegNum<[30]>; 108 def R31 : Ri<31, "r31", ["lr"]>, DwarfRegNum<[31]>; 109 110 // Aliases of the R* registers used to hold 64-bit int values (doubles). 111 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 112 def D0 : Rd< 0, "r1:0", [R0, R1]>, DwarfRegNum<[32]>; 113 def D1 : Rd< 2, "r3:2", [R2, R3]>, DwarfRegNum<[34]>; 114 def D2 : Rd< 4, "r5:4", [R4, R5]>, DwarfRegNum<[36]>; 115 def D3 : Rd< 6, "r7:6", [R6, R7]>, DwarfRegNum<[38]>; 116 def D4 : Rd< 8, "r9:8", [R8, R9]>, DwarfRegNum<[40]>; 117 def D5 : Rd<10, "r11:10", [R10, R11]>, DwarfRegNum<[42]>; 118 def D6 : Rd<12, "r13:12", [R12, R13]>, DwarfRegNum<[44]>; 119 def D7 : Rd<14, "r15:14", [R14, R15]>, DwarfRegNum<[46]>; 120 def D8 : Rd<16, "r17:16", [R16, R17]>, DwarfRegNum<[48]>; 121 def D9 : Rd<18, "r19:18", [R18, R19]>, DwarfRegNum<[50]>; 122 def D10 : Rd<20, "r21:20", [R20, R21]>, DwarfRegNum<[52]>; 123 def D11 : Rd<22, "r23:22", [R22, R23]>, DwarfRegNum<[54]>; 124 def D12 : Rd<24, "r25:24", [R24, R25]>, DwarfRegNum<[56]>; 125 def D13 : Rd<26, "r27:26", [R26, R27]>, DwarfRegNum<[58]>; 126 def D14 : Rd<28, "r29:28", [R28, R29]>, DwarfRegNum<[60]>; 127 def D15 : Rd<30, "r31:30", [R30, R31], ["lr:fp"]>, DwarfRegNum<[62]>; 128 } 129 130 // Predicate registers. 131 def P0 : Rp<0, "p0">, DwarfRegNum<[63]>; 132 def P1 : Rp<1, "p1">, DwarfRegNum<[64]>; 133 def P2 : Rp<2, "p2">, DwarfRegNum<[65]>; 134 def P3 : Rp<3, "p3">, DwarfRegNum<[66]>; 135 136 // Fake register to represent USR.OVF bit. Arithmetic/saturating instruc- 137 // tions modify this bit, and multiple such instructions are allowed in the 138 // same packet. We need to ignore output dependencies on this bit, but not 139 // on the entire USR. 140 def USR_OVF : Rc<?, "usr.ovf">; 141 142 def USR : Rc<8, "usr", ["c8"]>, DwarfRegNum<[75]> { 143 let SubRegIndices = [subreg_overflow]; 144 let SubRegs = [USR_OVF]; 145 } 146 147 // Control registers. 148 def SA0: Rc<0, "sa0", ["c0"]>, DwarfRegNum<[67]>; 149 def LC0: Rc<1, "lc0", ["c1"]>, DwarfRegNum<[68]>; 150 def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>; 151 def LC1: Rc<3, "lc1", ["c3"]>, DwarfRegNum<[70]>; 152 def P3_0: Rc<4, "p3:0", ["c4"], [P0, P1, P2, P3]>, 153 DwarfRegNum<[71]>; 154 // When defining more Cn registers, make sure to explicitly mark them 155 // as reserved in HexagonRegisterInfo.cpp. 156 def C5: Rc<5, "c5", ["c5"]>, DwarfRegNum<[72]>; 157 def M0: Rc<6, "m0", ["c6"]>, DwarfRegNum<[73]>; 158 def M1: Rc<7, "m1", ["c7"]>, DwarfRegNum<[74]>; 159 // Define C8 separately and make it aliased with USR. 160 // The problem is that USR has subregisters (e.g. overflow). If USR was 161 // specified as a subregister of C9_8, it would imply that subreg_overflow 162 // and isub_lo can be composed, which leads to all kinds of issues 163 // with lane masks. 164 def C8: Rc<8, "c8", [], [USR]>, DwarfRegNum<[75]>; 165 def PC: Rc<9, "pc", ["c9"]>, DwarfRegNum<[76]>; 166 def UGP: Rc<10, "ugp", ["c10"]>, DwarfRegNum<[77]>; 167 def GP: Rc<11, "gp", ["c11"]>, DwarfRegNum<[78]>; 168 def CS0: Rc<12, "cs0", ["c12"]>, DwarfRegNum<[79]>; 169 def CS1: Rc<13, "cs1", ["c13"]>, DwarfRegNum<[80]>; 170 def UPCYCLELO: Rc<14, "upcyclelo", ["c14"]>, DwarfRegNum<[81]>; 171 def UPCYCLEHI: Rc<15, "upcyclehi", ["c15"]>, DwarfRegNum<[82]>; 172 def FRAMELIMIT: Rc<16, "framelimit", ["c16"]>, DwarfRegNum<[83]>; 173 def FRAMEKEY: Rc<17, "framekey", ["c17"]>, DwarfRegNum<[84]>; 174 def PKTCOUNTLO: Rc<18, "pktcountlo", ["c18"]>, DwarfRegNum<[85]>; 175 def PKTCOUNTHI: Rc<19, "pktcounthi", ["c19"]>, DwarfRegNum<[86]>; 176 def UTIMERLO: Rc<30, "utimerlo", ["c30"]>, DwarfRegNum<[97]>; 177 def UTIMERHI: Rc<31, "utimerhi", ["c31"]>, DwarfRegNum<[98]>; 178 179 // Control registers pairs. 180 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 181 def C1_0 : Rcc<0, "c1:0", [SA0, LC0], ["lc0:sa0"]>, DwarfRegNum<[67]>; 182 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>; 183 def C5_4 : Rcc<4, "c5:4", [P3_0, C5]>, DwarfRegNum<[71]>; 184 def C7_6 : Rcc<6, "c7:6", [M0, M1], ["m1:0"]>, DwarfRegNum<[72]>; 185 // Use C8 instead of USR as a subregister of C9_8. 186 def C9_8 : Rcc<8, "c9:8", [C8, PC]>, DwarfRegNum<[74]>; 187 def C11_10 : Rcc<10, "c11:10", [UGP, GP]>, DwarfRegNum<[76]>; 188 def CS : Rcc<12, "c13:12", [CS0, CS1], ["cs1:0"]>, DwarfRegNum<[78]>; 189 def UPCYCLE: Rcc<14, "c15:14", [UPCYCLELO, UPCYCLEHI], ["upcycle"]>, 190 DwarfRegNum<[80]>; 191 def C17_16 : Rcc<16, "c17:16", [FRAMELIMIT, FRAMEKEY]>, DwarfRegNum<[83]>; 192 def PKTCOUNT : Rcc<18, "c19:18", [PKTCOUNTLO, PKTCOUNTHI], ["pktcount"]>, 193 DwarfRegNum<[85]>; 194 def UTIMER : Rcc<30, "c31:30", [UTIMERLO, UTIMERHI], ["utimer"]>, 195 DwarfRegNum<[97]>; 196 } 197 198 foreach i = 0-31 in { 199 def V#i : Ri<i, "v"#i>, DwarfRegNum<[!add(i, 99)]>; 200 def VF#i : R_fake<"__"#!add(i,999999)>, DwarfRegNum<[!add(i, 999999)]>; 201 def VFR#i : R_fake<"__"#!add(i,9999999)>, DwarfRegNum<[!add(i, 9999999)]>; 202 } 203 def VTMP : Ri<0, "vtmp">, DwarfRegNum<[131]>; 204 205 // Aliases of the V* registers used to hold double vec values. 206 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { 207 def W0 : Rd< 0, "v1:0", [V0, V1, VF0]>, DwarfRegNum<[99]>; 208 def W1 : Rd< 2, "v3:2", [V2, V3, VF1]>, DwarfRegNum<[101]>; 209 def W2 : Rd< 4, "v5:4", [V4, V5, VF2]>, DwarfRegNum<[103]>; 210 def W3 : Rd< 6, "v7:6", [V6, V7, VF3]>, DwarfRegNum<[105]>; 211 def W4 : Rd< 8, "v9:8", [V8, V9, VF4]>, DwarfRegNum<[107]>; 212 def W5 : Rd<10, "v11:10", [V10, V11, VF5]>, DwarfRegNum<[109]>; 213 def W6 : Rd<12, "v13:12", [V12, V13, VF6]>, DwarfRegNum<[111]>; 214 def W7 : Rd<14, "v15:14", [V14, V15, VF7]>, DwarfRegNum<[113]>; 215 def W8 : Rd<16, "v17:16", [V16, V17, VF8]>, DwarfRegNum<[115]>; 216 def W9 : Rd<18, "v19:18", [V18, V19, VF9]>, DwarfRegNum<[117]>; 217 def W10 : Rd<20, "v21:20", [V20, V21, VF10]>, DwarfRegNum<[119]>; 218 def W11 : Rd<22, "v23:22", [V22, V23, VF11]>, DwarfRegNum<[121]>; 219 def W12 : Rd<24, "v25:24", [V24, V25, VF12]>, DwarfRegNum<[123]>; 220 def W13 : Rd<26, "v27:26", [V26, V27, VF13]>, DwarfRegNum<[125]>; 221 def W14 : Rd<28, "v29:28", [V28, V29, VF14]>, DwarfRegNum<[127]>; 222 def W15 : Rd<30, "v31:30", [V30, V31, VF15]>, DwarfRegNum<[129]>; 223 } 224 225 // Reverse Aliases of the V* registers used to hold double vec values. 226 let SubRegIndices = [vsub_lo, vsub_hi, vsub_fake], CoveredBySubRegs = 1 in { 227 def WR0 : Rd< 1, "v0:1", [V0, V1, VFR0]>, DwarfRegNum<[161]>; 228 def WR1 : Rd< 3, "v2:3", [V2, V3, VFR1]>, DwarfRegNum<[162]>; 229 def WR2 : Rd< 5, "v4:5", [V4, V5, VFR2]>, DwarfRegNum<[163]>; 230 def WR3 : Rd< 7, "v6:7", [V6, V7, VFR3]>, DwarfRegNum<[164]>; 231 def WR4 : Rd< 9, "v8:9", [V8, V9, VFR4]>, DwarfRegNum<[165]>; 232 def WR5 : Rd<11, "v10:11", [V10, V11, VFR5]>, DwarfRegNum<[166]>; 233 def WR6 : Rd<13, "v12:13", [V12, V13, VFR6]>, DwarfRegNum<[167]>; 234 def WR7 : Rd<15, "v14:15", [V14, V15, VFR7]>, DwarfRegNum<[168]>; 235 def WR8 : Rd<17, "v16:17", [V16, V17, VFR8]>, DwarfRegNum<[169]>; 236 def WR9 : Rd<19, "v18:19", [V18, V19, VFR9]>, DwarfRegNum<[170]>; 237 def WR10: Rd<21, "v20:21", [V20, V21, VFR10]>, DwarfRegNum<[171]>; 238 def WR11: Rd<23, "v22:23", [V22, V23, VFR11]>, DwarfRegNum<[172]>; 239 def WR12: Rd<25, "v24:25", [V24, V25, VFR12]>, DwarfRegNum<[173]>; 240 def WR13: Rd<27, "v26:27", [V26, V27, VFR13]>, DwarfRegNum<[174]>; 241 def WR14: Rd<29, "v28:29", [V28, V29, VFR14]>, DwarfRegNum<[175]>; 242 def WR15: Rd<31, "v30:31", [V30, V31, VFR15]>, DwarfRegNum<[176]>; 243 } 244 245 // Aliases of the V* registers used to hold quad vec values. 246 let SubRegIndices = [wsub_lo, wsub_hi], CoveredBySubRegs = 1 in { 247 def VQ0 : Rd< 0, "v3:0", [W0, W1]>, DwarfRegNum<[252]>; 248 def VQ1 : Rd< 4, "v7:4", [W2, W3]>, DwarfRegNum<[253]>; 249 def VQ2 : Rd< 8, "v11:8", [W4, W5]>, DwarfRegNum<[254]>; 250 def VQ3 : Rd<12, "v15:12", [W6, W7]>, DwarfRegNum<[255]>; 251 def VQ4 : Rd<16, "v19:16", [W8, W9]>, DwarfRegNum<[256]>; 252 def VQ5 : Rd<20, "v23:20", [W10, W11]>, DwarfRegNum<[257]>; 253 def VQ6 : Rd<24, "v27:24", [W12, W13]>, DwarfRegNum<[258]>; 254 def VQ7 : Rd<28, "v31:28", [W14, W15]>, DwarfRegNum<[259]>; 255 } 256 257 // Vector Predicate registers. 258 def Q0 : Rq<0, "q0">, DwarfRegNum<[131]>; 259 def Q1 : Rq<1, "q1">, DwarfRegNum<[132]>; 260 def Q2 : Rq<2, "q2">, DwarfRegNum<[133]>; 261 def Q3 : Rq<3, "q3">, DwarfRegNum<[134]>; 262 263 // Guest Registers 264 def GELR: Rg<0, "gelr", ["g0"]>, DwarfRegNum<[220]>; 265 def GSR: Rg<1, "gsr", ["g1"]>, DwarfRegNum<[221]>; 266 def GOSP: Rg<2, "gosp", ["g2"]>, DwarfRegNum<[222]>; 267 def G3: Rg<3, "gbadva", ["g3"]>, DwarfRegNum<[223]>; 268 def G4: Rg<4, "g4">, DwarfRegNum<[224]>; 269 def G5: Rg<5, "g5">, DwarfRegNum<[225]>; 270 def G6: Rg<6, "g6">, DwarfRegNum<[226]>; 271 def G7: Rg<7, "g7">, DwarfRegNum<[227]>; 272 def G8: Rg<8, "g8">, DwarfRegNum<[228]>; 273 def G9: Rg<9, "g9">, DwarfRegNum<[229]>; 274 def G10: Rg<10, "g10">, DwarfRegNum<[230]>; 275 def G11: Rg<11, "g11">, DwarfRegNum<[231]>; 276 def G12: Rg<12, "g12">, DwarfRegNum<[232]>; 277 def G13: Rg<13, "g13">, DwarfRegNum<[233]>; 278 def G14: Rg<14, "g14">, DwarfRegNum<[234]>; 279 def G15: Rg<15, "g15">, DwarfRegNum<[235]>; 280 def GPMUCNT4: Rg<16, "gpmucnt4", ["g16"]>, DwarfRegNum<[236]>; 281 def GPMUCNT5: Rg<17, "gpmucnt5", ["g17"]>, DwarfRegNum<[237]>; 282 def GPMUCNT6: Rg<18, "gpmucnt6", ["g18"]>, DwarfRegNum<[238]>; 283 def GPMUCNT7: Rg<19, "gpmucnt7", ["g19"]>, DwarfRegNum<[239]>; 284 def G20: Rg<20, "g20">, DwarfRegNum<[240]>; 285 def G21: Rg<21, "g21">, DwarfRegNum<[241]>; 286 def G22: Rg<22, "g22">, DwarfRegNum<[242]>; 287 def G23: Rg<23, "g23">, DwarfRegNum<[243]>; 288 def GPCYCLELO: Rg<24, "gpcyclelo", ["g24"]>, DwarfRegNum<[244]>; 289 def GPCYCLEHI: Rg<25, "gpcyclehi", ["g25"]>, DwarfRegNum<[245]>; 290 def GPMUCNT0: Rg<26, "gpmucnt0", ["g26"]>, DwarfRegNum<[246]>; 291 def GPMUCNT1: Rg<27, "gpmucnt1", ["g27"]>, DwarfRegNum<[247]>; 292 def GPMUCNT2: Rg<28, "gpmucnt2", ["g28"]>, DwarfRegNum<[248]>; 293 def GPMUCNT3: Rg<29, "gpmucnt3", ["g29"]>, DwarfRegNum<[249]>; 294 def G30: Rg<30, "g30">, DwarfRegNum<[250]>; 295 def G31: Rg<31, "g31">, DwarfRegNum<[251]>; 296 297 // Guest Register Pairs 298 let SubRegIndices = [isub_lo, isub_hi], CoveredBySubRegs = 1 in { 299 def G1_0 : Rgg<0, "g1:0", [GELR, GSR]>, DwarfRegNum<[220]>; 300 def G3_2 : Rgg<2, "g3:2", [GOSP, G3]>, DwarfRegNum<[222]>; 301 def G5_4 : Rgg<4, "g5:4", [G4, G5]>, DwarfRegNum<[224]>; 302 def G7_6 : Rgg<6, "g7:6", [G6, G7]>, DwarfRegNum<[226]>; 303 def G9_8 : Rgg<8, "g9:8", [G8, G9]>, DwarfRegNum<[228]>; 304 def G11_10 : Rgg<10, "g11:10", [G10, G11]>, DwarfRegNum<[230]>; 305 def G13_12 : Rgg<12, "g13:12", [G12, G13]>, DwarfRegNum<[232]>; 306 def G15_14 : Rgg<14, "g15:14", [G14, G15]>, DwarfRegNum<[234]>; 307 def G17_16 : Rgg<16, "g17:16", [GPMUCNT4, GPMUCNT5]>, DwarfRegNum<[236]>; 308 def G19_18 : Rgg<18, "g19:18", [GPMUCNT6, GPMUCNT7]>, DwarfRegNum<[238]>; 309 def G21_20 : Rgg<20, "g21:20", [G20, G21]>, DwarfRegNum<[240]>; 310 def G23_22 : Rgg<22, "g23:22", [G22, G23]>, DwarfRegNum<[242]>; 311 def G25_24 : Rgg<24, "g25:24", [GPCYCLELO, GPCYCLEHI]>, DwarfRegNum<[244]>; 312 def G27_26 : Rgg<26, "g27:26", [GPMUCNT0, GPMUCNT1]>, DwarfRegNum<[246]>; 313 def G29_28 : Rgg<28, "g29:28", [GPMUCNT2, GPMUCNT3]>, DwarfRegNum<[248]>; 314 def G31_30 : Rgg<30, "g31:30", [G30, G31]>, DwarfRegNum<[250]>; 315 } 316 317} 318 319// HVX types 320 321def VecI1: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 322 [v64i1, v128i1, v64i1]>; 323def VecI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 324 [v64i8, v128i8, v64i8]>; 325def VecI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 326 [v32i16, v64i16, v32i16]>; 327def VecI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 328 [v16i32, v32i32, v16i32]>; 329 330def VecPI8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 331 [v128i8, v256i8, v128i8]>; 332def VecPI16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 333 [v64i16, v128i16, v64i16]>; 334def VecPI32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 335 [v32i32, v64i32, v32i32]>; 336 337def VecQ8: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 338 [v64i1, v128i1, v64i1]>; 339def VecQ16: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 340 [v32i1, v64i1, v32i1]>; 341def VecQ32: ValueTypeByHwMode<[Hvx64, Hvx128, DefaultMode], 342 [v16i1, v32i1, v16i1]>; 343 344// HVX register classes 345 346def HvxVR : RegisterClass<"Hexagon", [VecI8, VecI16, VecI32], 512, 347 (add (sequence "V%u", 0, 31), VTMP)> { 348 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 349 [RegInfo<512,512,512>, RegInfo<1024,1024,1024>, RegInfo<512,512,512>]>; 350} 351 352def HvxWR : RegisterClass<"Hexagon", [VecPI8, VecPI16, VecPI32], 1024, 353 (add (sequence "W%u", 0, 15), (sequence "WR%u", 0, 15))> { 354 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 355 [RegInfo<1024,1024,1024>, RegInfo<2048,2048,2048>, RegInfo<1024,1024,1024>]>; 356} 357 358def HvxQR : RegisterClass<"Hexagon", [VecI1, VecQ8, VecQ16, VecQ32], 128, 359 (add Q0, Q1, Q2, Q3)> { 360 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 361 [RegInfo<64,512,512>, RegInfo<128,1024,1024>, RegInfo<64,512,512>]>; 362} 363 364def HvxVQR : RegisterClass<"Hexagon", [untyped], 2048, 365 (add (sequence "VQ%u", 0, 7))> { 366 let RegInfos = RegInfoByHwMode<[Hvx64, Hvx128, DefaultMode], 367 [RegInfo<2048,2048,2048>, RegInfo<4096,4096,4096>, RegInfo<2048,2048,2048>]>; 368} 369 370// Core register classes 371 372def IntRegs : RegisterClass<"Hexagon", [i32, f32, v4i8, v2i16], 32, 373 (add (sequence "R%u", 0, 9), (sequence "R%u", 12, 28), 374 R10, R11, R29, R30, R31)>; 375 376// Registers are listed in reverse order for allocation preference reasons. 377def GeneralSubRegs : RegisterClass<"Hexagon", [i32], 32, 378 (add R23, R22, R21, R20, R19, R18, R17, R16, 379 R7, R6, R5, R4, R3, R2, R1, R0)>; 380 381def IntRegsLow8 : RegisterClass<"Hexagon", [i32], 32, 382 (add R7, R6, R5, R4, R3, R2, R1, R0)> ; 383 384def DoubleRegs : RegisterClass<"Hexagon", [i64, f64, v8i8, v4i16, v2i32], 64, 385 (add (sequence "D%u", 0, 4), (sequence "D%u", 6, 13), D5, D14, D15)>; 386 387def GeneralDoubleLow8Regs : RegisterClass<"Hexagon", [i64], 64, 388 (add D11, D10, D9, D8, D3, D2, D1, D0)>; 389 390let Size = 32 in 391def PredRegs : RegisterClass<"Hexagon", 392 [i1, v2i1, v4i1, v8i1, v4i8, v2i16, i32], 32, (add P0, P1, P2, P3)>; 393 394let Size = 32 in 395def ModRegs : RegisterClass<"Hexagon", [i32], 32, (add M0, M1)>; 396 397let Size = 32, isAllocatable = 0 in 398def CtrRegs : RegisterClass<"Hexagon", [i32], 32, 399 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1, 400 UPCYCLELO, UPCYCLEHI, 401 FRAMELIMIT, FRAMEKEY, PKTCOUNTLO, PKTCOUNTHI, UTIMERLO, UTIMERHI, 402 M0, M1, USR)>; 403 404let Size = 64 in 405def VectRegRev : RegisterClass<"Hexagon", [i64], 64, 406 (add (sequence "WR%u", 0, 15))>; 407 408let isAllocatable = 0 in 409def UsrBits : RegisterClass<"Hexagon", [i1], 0, (add USR_OVF)>; 410 411let Size = 64, isAllocatable = 0 in 412def CtrRegs64 : RegisterClass<"Hexagon", [i64], 64, 413 (add C1_0, C3_2, C5_4, C7_6, C9_8, C11_10, CS, UPCYCLE, C17_16, 414 PKTCOUNT, UTIMER)>; 415 416let Size = 32, isAllocatable = 0 in 417def GuestRegs : RegisterClass<"Hexagon", [i32], 32, 418 (add GELR, GSR, GOSP, 419 (sequence "G%u", 3, 15), 420 GPMUCNT4, GPMUCNT5, GPMUCNT6, GPMUCNT7, 421 G20, G21, G22, G23, 422 GPCYCLELO, GPCYCLEHI, GPMUCNT0, GPMUCNT1, 423 GPMUCNT2, GPMUCNT3, 424 G30, G31)>; 425 426let Size = 64, isAllocatable = 0 in 427def GuestRegs64 : RegisterClass<"Hexagon", [i64], 64, 428 (add G1_0, G3_2, 429 G5_4, G7_6, G9_8, G11_10, G13_12, G15_14, 430 G17_16, G19_18, 431 G21_20, G23_22, 432 G25_24, G27_26, G29_28, 433 G31_30)>; 434 435// These registers are new for v62 and onward. 436// The function RegisterMatchesArch() uses this list for validation. 437let isAllocatable = 0 in 438def V62Regs : RegisterClass<"Hexagon", [i32], 32, 439 (add FRAMELIMIT, FRAMEKEY, C17_16, PKTCOUNTLO, PKTCOUNTHI, PKTCOUNT, 440 UTIMERLO, UTIMERHI, UTIMER)>; 441 442// These registers are new for v65 and onward. 443let Size = 32, isAllocatable = 0 in 444def V65Regs : RegisterClass<"Hexagon", [i32], 32, (add VTMP)>; 445 446 447def HexagonCSR 448 : CalleeSavedRegs<(add R16, R17, R18, R19, R20, R21, R22, R23, 449 R24, R25, R26, R27)>; 450