1 /*------------------------------------------------------------------------- 2 ax8052f143.h - Register Declarations for the Axsem Integrated Radio 3 4 Copyright (C) 2010, 2011, Axsem AG 5 Author: Thomas Sailer, thomas.sailer@axsem.com 6 7 This library is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published by the 9 Free Software Foundation; either version 2.1, or (at your option) any 10 later version. 11 12 This library is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this library; see the file COPYING. If not, write to the 19 Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston, 20 MA 02110-1301, USA. 21 22 As a special exception, if you link this library with other files, 23 some of which are compiled with SDCC, to produce an executable, 24 this library does not by itself cause the resulting executable to 25 be covered by the GNU General Public License. This exception does 26 not however invalidate any other reasons why the executable file 27 might be covered by the GNU General Public License. 28 -------------------------------------------------------------------------*/ 29 30 31 #ifndef AX8052F143_H 32 #define AX8052F143_H 33 34 #include <compiler.h> 35 36 /* SFR Address Space */ 37 38 SFR(ACC, 0xE0); /* Accumulator */ 39 SBIT(ACC_0, 0xE0, 0); /* Accumulator bit 0 */ 40 SBIT(ACC_1, 0xE0, 1); /* Accumulator bit 1 */ 41 SBIT(ACC_2, 0xE0, 2); /* Accumulator bit 2 */ 42 SBIT(ACC_3, 0xE0, 3); /* Accumulator bit 3 */ 43 SBIT(ACC_4, 0xE0, 4); /* Accumulator bit 4 */ 44 SBIT(ACC_5, 0xE0, 5); /* Accumulator bit 5 */ 45 SBIT(ACC_6, 0xE0, 6); /* Accumulator bit 6 */ 46 SBIT(ACC_7, 0xE0, 7); /* Accumulator bit 7 */ 47 SFR(B, 0xF0); /* B Register */ 48 SBIT(B_0, 0xF0, 0); /* Register B bit 0 */ 49 SBIT(B_1, 0xF0, 1); /* Register B bit 1 */ 50 SBIT(B_2, 0xF0, 2); /* Register B bit 2 */ 51 SBIT(B_3, 0xF0, 3); /* Register B bit 3 */ 52 SBIT(B_4, 0xF0, 4); /* Register B bit 4 */ 53 SBIT(B_5, 0xF0, 5); /* Register B bit 5 */ 54 SBIT(B_6, 0xF0, 6); /* Register B bit 6 */ 55 SBIT(B_7, 0xF0, 7); /* Register B bit 7 */ 56 SFR(DPH, 0x83); /* Data Pointer 0 High Byte */ 57 SFR(DPH1, 0x85); /* Data Pointer 1 High Byte */ 58 SFR(DPL, 0x82); /* Data Pointer 0 Low Byte */ 59 SFR(DPL1, 0x84); /* Data Pointer 1 Low Byte */ 60 SFR16(DPTR0, 0x82); /* Data Pointer 0 */ 61 SFR16(DPTR1, 0x84); /* Data Pointer 1 */ 62 SFR(DPS, 0x86); /* Data Pointer Select */ 63 SFR(E2IE, 0xA0); /* 2nd Extended Interrupt Enable */ 64 SBIT(E2IE_0, 0xA0, 0); /* Output Compare 0 Interrupt Enable */ 65 SBIT(E2IE_1, 0xA0, 1); /* Output Compare 1 Interrupt Enable */ 66 SBIT(E2IE_2, 0xA0, 2); /* Input Capture 0 Interrupt Enable */ 67 SBIT(E2IE_3, 0xA0, 3); /* Input Capture 1 Interrupt Enable */ 68 SBIT(E2IE_4, 0xA0, 4); /* Random Number Generator Interrupt Enable */ 69 SBIT(E2IE_5, 0xA0, 5); /* AES Interrupt Enable */ 70 SBIT(E2IE_6, 0xA0, 6); /* DebugLink Interrupt Enable */ 71 SBIT(E2IE_7, 0xA0, 7); /* */ 72 SFR(E2IP, 0xC0); /* 2nd Extended Interrupt Priority */ 73 SBIT(E2IP_0, 0xC0, 0); /* Output Compare 0 Interrupt Priority */ 74 SBIT(E2IP_1, 0xC0, 1); /* Output Compare 1 Interrupt Priority */ 75 SBIT(E2IP_2, 0xC0, 2); /* Input Capture 0 Interrupt Priority */ 76 SBIT(E2IP_3, 0xC0, 3); /* Input Capture 1 Interrupt Priority */ 77 SBIT(E2IP_4, 0xC0, 4); /* Random Number Generator Interrupt Priority */ 78 SBIT(E2IP_5, 0xC0, 5); /* AES Interrupt Priority */ 79 SBIT(E2IP_6, 0xC0, 6); /* DebugLink Interrupt Priority */ 80 SBIT(E2IP_7, 0xC0, 7); /* */ 81 SFR(EIE, 0x98); /* Extended Interrupt Enable */ 82 SBIT(EIE_0, 0x98, 0); /* Timer 0 Interrupt Enable */ 83 SBIT(EIE_1, 0x98, 1); /* Timer 1 Interrupt Enable */ 84 SBIT(EIE_2, 0x98, 2); /* Timer 2 Interrupt Enable */ 85 SBIT(EIE_3, 0x98, 3); /* SPI 0 Interrupt Enable */ 86 SBIT(EIE_4, 0x98, 4); /* UART 0 Interrupt Enable */ 87 SBIT(EIE_5, 0x98, 5); /* UART 1 Interrupt Enable */ 88 SBIT(EIE_6, 0x98, 6); /* GPADC Interrupt Enable */ 89 SBIT(EIE_7, 0x98, 7); /* DMA Interrupt Enable */ 90 SFR(EIP, 0xB0); /* Extended Interrupt Priority */ 91 SBIT(EIP_0, 0xB0, 0); /* Timer 0 Interrupt Priority */ 92 SBIT(EIP_1, 0xB0, 1); /* Timer 1 Interrupt Priority */ 93 SBIT(EIP_2, 0xB0, 2); /* Timer 2 Interrupt Priority */ 94 SBIT(EIP_3, 0xB0, 3); /* SPI 0 Interrupt Priority */ 95 SBIT(EIP_4, 0xB0, 4); /* UART 0 Interrupt Priority */ 96 SBIT(EIP_5, 0xB0, 5); /* UART 1 Interrupt Priority */ 97 SBIT(EIP_6, 0xB0, 6); /* GPADC Interrupt Priority */ 98 SBIT(EIP_7, 0xB0, 7); /* DMA Interrupt Priority */ 99 SFR(IE, 0xA8); /* Interrupt Enable */ 100 SBIT(IE_0, 0xA8, 0); /* External 0 Interrupt Enable */ 101 SBIT(IE_1, 0xA8, 1); /* Wakeup Timer Interrupt Enable */ 102 SBIT(IE_2, 0xA8, 2); /* External 1 Interrupt Enable */ 103 SBIT(IE_3, 0xA8, 3); /* GPIO Interrupt Enable */ 104 SBIT(IE_4, 0xA8, 4); /* Radio Interrupt Enable */ 105 SBIT(IE_5, 0xA8, 5); /* Clock Management Interrupt Enable */ 106 SBIT(IE_6, 0xA8, 6); /* Power Management Interrupt Enable */ 107 SBIT(IE_7, 0xA8, 7); /* Global Interrupt Enable */ 108 SBIT(EA, 0xA8, 7); /* Global Interrupt Enable */ 109 SFR(IP, 0xB8); /* Interrupt Priority */ 110 SBIT(IP_0, 0xB8, 0); /* External 0 Interrupt Priority */ 111 SBIT(IP_1, 0xB8, 1); /* Wakeup Timer Interrupt Priority */ 112 SBIT(IP_2, 0xB8, 2); /* External 1 Interrupt Priority */ 113 SBIT(IP_3, 0xB8, 3); /* GPIO Interrupt Priority */ 114 SBIT(IP_4, 0xB8, 4); /* Radio Interrupt Priority */ 115 SBIT(IP_5, 0xB8, 5); /* Clock Management Interrupt Priority */ 116 SBIT(IP_6, 0xB8, 6); /* Power Management Interrupt Priority */ 117 SBIT(IP_7, 0xB8, 7); /* */ 118 SFR(PCON, 0x87); /* Power Mode Control */ 119 SFR(PSW, 0xD0); /* Program Status Word */ 120 SBIT(P, 0xD0, 0); /* Parity Flag */ 121 SBIT(F1, 0xD0, 1); /* User-Defined Flag */ 122 SBIT(OV, 0xD0, 2); /* Overflow Flag */ 123 SBIT(RS0, 0xD0, 3); /* Register Bank Select 0 */ 124 SBIT(RS1, 0xD0, 4); /* Register Bank Select 1 */ 125 SBIT(F0, 0xD0, 5); /* User-Defined Flag */ 126 SBIT(AC, 0xD0, 6); /* Auxiliary Carry Flag */ 127 SBIT(CY, 0xD0, 7); /* Carry Flag */ 128 SFR(SP, 0x81); /* Stack Pointer */ 129 SFR(WBTEST, 0x8F); /* Debug Breakpoint Register */ 130 SFR(XPAGE, 0xD9); /* Memory Page Select */ 131 SFR(_XPAGE, 0xD9); /* Memory Page Select, SDCC name */ 132 SFR(ADCCH0CONFIG, 0xCA); /* ADC Channel 0 Configuration */ 133 SFR(ADCCH1CONFIG, 0xCB); /* ADC Channel 1 Configuration */ 134 SFR(ADCCH2CONFIG, 0xD2); /* ADC Channel 2 Configuration */ 135 SFR(ADCCH3CONFIG, 0xD3); /* ADC Channel 3 Configuration */ 136 SFR(ADCCLKSRC, 0xD1); /* ADC Clock Source */ 137 SFR(ADCCONV, 0xC9); /* ADC Conversion Source */ 138 SFR(ANALOGCOMP, 0xE1); /* Analog Comparators */ 139 SFR(CLKCON, 0xC6); /* Clock Control */ 140 SFR(CLKSTAT, 0xC7); /* Clock Status */ 141 SFR(CODECONFIG, 0x97); /* Code Space Configuration */ 142 SFR(DBGLNKBUF, 0xE3); /* Debug Link Buffer */ 143 SFR(DBGLNKSTAT, 0xE2); /* Debug Link Status */ 144 SFR(DIRA, 0x89); /* Port A Direction */ 145 SFR(DIRB, 0x8A); /* Port B Direction */ 146 SFR(DIRC, 0x8B); /* Port C Direction */ 147 SFR(DIRR, 0x8E); /* Port R Direction */ 148 SFR(PINA, 0xC8); /* Port A Input */ 149 SBIT(PINA_0, 0xC8, 0); /* */ 150 SBIT(PINA_1, 0xC8, 1); /* */ 151 SBIT(PINA_2, 0xC8, 2); /* */ 152 SBIT(PINA_3, 0xC8, 3); /* */ 153 SBIT(PINA_4, 0xC8, 4); /* */ 154 SBIT(PINA_5, 0xC8, 5); /* */ 155 SBIT(PINA_6, 0xC8, 6); /* */ 156 SBIT(PINA_7, 0xC8, 7); /* */ 157 SFR(PINB, 0xE8); /* Port B Input */ 158 SBIT(PINB_0, 0xE8, 0); /* */ 159 SBIT(PINB_1, 0xE8, 1); /* */ 160 SBIT(PINB_2, 0xE8, 2); /* */ 161 SBIT(PINB_3, 0xE8, 3); /* */ 162 SBIT(PINB_4, 0xE8, 4); /* */ 163 SBIT(PINB_5, 0xE8, 5); /* */ 164 SBIT(PINB_6, 0xE8, 6); /* */ 165 SBIT(PINB_7, 0xE8, 7); /* */ 166 SFR(PINC, 0xF8); /* Port C Input */ 167 SBIT(PINC_0, 0xF8, 0); /* */ 168 SBIT(PINC_1, 0xF8, 1); /* */ 169 SBIT(PINC_2, 0xF8, 2); /* */ 170 SBIT(PINC_3, 0xF8, 3); /* */ 171 SBIT(PINC_4, 0xF8, 4); /* */ 172 SBIT(PINC_5, 0xF8, 5); /* */ 173 SBIT(PINC_6, 0xF8, 6); /* */ 174 SBIT(PINC_7, 0xF8, 7); /* */ 175 SFR(PINR, 0x8D); /* Port R Input */ 176 SFR(PORTA, 0x80); /* Port A Output */ 177 SBIT(PORTA_0, 0x80, 0); /* */ 178 SBIT(PORTA_1, 0x80, 1); /* */ 179 SBIT(PORTA_2, 0x80, 2); /* */ 180 SBIT(PORTA_3, 0x80, 3); /* */ 181 SBIT(PORTA_4, 0x80, 4); /* */ 182 SBIT(PORTA_5, 0x80, 5); /* */ 183 SBIT(PORTA_6, 0x80, 6); /* */ 184 SBIT(PORTA_7, 0x80, 7); /* */ 185 SFR(PORTB, 0x88); /* Port B Output */ 186 SBIT(PORTB_0, 0x88, 0); /* */ 187 SBIT(PORTB_1, 0x88, 1); /* */ 188 SBIT(PORTB_2, 0x88, 2); /* */ 189 SBIT(PORTB_3, 0x88, 3); /* */ 190 SBIT(PORTB_4, 0x88, 4); /* */ 191 SBIT(PORTB_5, 0x88, 5); /* */ 192 SBIT(PORTB_6, 0x88, 6); /* */ 193 SBIT(PORTB_7, 0x88, 7); /* */ 194 SFR(PORTC, 0x90); /* Port C Output */ 195 SBIT(PORTC_0, 0x90, 0); /* */ 196 SBIT(PORTC_1, 0x90, 1); /* */ 197 SBIT(PORTC_2, 0x90, 2); /* */ 198 SBIT(PORTC_3, 0x90, 3); /* */ 199 SBIT(PORTC_4, 0x90, 4); /* */ 200 SBIT(PORTC_5, 0x90, 5); /* */ 201 SBIT(PORTC_6, 0x90, 6); /* */ 202 SBIT(PORTC_7, 0x90, 7); /* */ 203 SFR(PORTR, 0x8C); /* Port R Output */ 204 SFR(IC0CAPT0, 0xCE); /* Input Capture 0 Low Byte */ 205 SFR(IC0CAPT1, 0xCF); /* Input Capture 0 High Byte */ 206 SFR16(IC0CAPT, 0xCE); /* Input Capture 0 */ 207 SFR(IC0MODE, 0xCC); /* Input Capture 0 Mode */ 208 SFR(IC0STATUS, 0xCD); /* Input Capture 0 Status */ 209 SFR(IC1CAPT0, 0xD6); /* Input Capture 1 Low Byte */ 210 SFR(IC1CAPT1, 0xD7); /* Input Capture 1 High Byte */ 211 SFR16(IC1CAPT, 0xD6); /* Input Capture 1 */ 212 SFR(IC1MODE, 0xD4); /* Input Capture 1 Mode */ 213 SFR(IC1STATUS, 0xD5); /* Input Capture 1 Status */ 214 SFR(NVADDR0, 0x92); /* Non-Volatile Memory Address Low Byte */ 215 SFR(NVADDR1, 0x93); /* Non-Volatile Memory Address High Byte */ 216 SFR16(NVADDR, 0x92); /* Non-Volatile Memory Address */ 217 SFR(NVDATA0, 0x94); /* Non-Volatile Memory Data Low Byte */ 218 SFR(NVDATA1, 0x95); /* Non-Volatile Memory Data High Byte */ 219 SFR16(NVDATA, 0x94); /* Non-Volatile Memory Data */ 220 SFR(NVKEY, 0x96); /* Non-Volatile Memory Write/Erase Key */ 221 SFR(NVSTATUS, 0x91); /* Non-Volatile Memory Command / Status */ 222 SFR(OC0COMP0, 0xBC); /* Output Compare 0 Low Byte */ 223 SFR(OC0COMP1, 0xBD); /* Output Compare 0 High Byte */ 224 SFR16(OC0COMP, 0xBC); /* Output Compare 0 */ 225 SFR(OC0MODE, 0xB9); /* Output Compare 0 Mode */ 226 SFR(OC0PIN, 0xBA); /* Output Compare 0 Pin Configuration */ 227 SFR(OC0STATUS, 0xBB); /* Output Compare 0 Status */ 228 SFR(OC1COMP0, 0xC4); /* Output Compare 1 Low Byte */ 229 SFR(OC1COMP1, 0xC5); /* Output Compare 1 High Byte */ 230 SFR16(OC1COMP, 0xC4); /* Output Compare 1 */ 231 SFR(OC1MODE, 0xC1); /* Output Compare 1 Mode */ 232 SFR(OC1PIN, 0xC2); /* Output Compare 1 Pin Configuration */ 233 SFR(OC1STATUS, 0xC3); /* Output Compare 1 Status */ 234 SFR(RADIOACC, 0xB1); /* Radio Controller Access Mode */ 235 SFR(RADIOADDR0, 0xB3); /* Radio Register Address Low Byte */ 236 SFR(RADIOADDR1, 0xB2); /* Radio Register Address High Byte */ 237 SFR16E(RADIOADDR, 0xB2B3); /* Radio Register Address */ 238 SFR(RADIODATA0, 0xB7); /* Radio Register Data 0 */ 239 SFR(RADIODATA1, 0xB6); /* Radio Register Data 1 */ 240 SFR(RADIODATA2, 0xB5); /* Radio Register Data 2 */ 241 SFR(RADIODATA3, 0xB4); /* Radio Register Data 3 */ 242 SFR32E(RADIODATA, 0xB4B5B6B7); /* Radio Register Data */ 243 SFR(RADIOSTAT0, 0xBE); /* Radio Access Status Low Byte */ 244 SFR(RADIOSTAT1, 0xBF); /* Radio Access Status High Byte */ 245 SFR16(RADIOSTAT, 0xBE); /* Radio Access Status */ 246 SFR(SPCLKSRC, 0xDF); /* SPI Clock Source */ 247 SFR(SPMODE, 0xDC); /* SPI Mode */ 248 SFR(SPSHREG, 0xDE); /* SPI Shift Register */ 249 SFR(SPSTATUS, 0xDD); /* SPI Status */ 250 SFR(T0CLKSRC, 0x9A); /* Timer 0 Clock Source */ 251 SFR(T0CNT0, 0x9C); /* Timer 0 Count Low Byte */ 252 SFR(T0CNT1, 0x9D); /* Timer 0 Count High Byte */ 253 SFR16(T0CNT, 0x9C); /* Timer 0 Count */ 254 SFR(T0MODE, 0x99); /* Timer 0 Mode */ 255 SFR(T0PERIOD0, 0x9E); /* Timer 0 Period Low Byte */ 256 SFR(T0PERIOD1, 0x9F); /* Timer 0 Period High Byte */ 257 SFR16(T0PERIOD, 0x9E); /* Timer 0 Period */ 258 SFR(T0STATUS, 0x9B); /* Timer 0 Status */ 259 SFR(T1CLKSRC, 0xA2); /* Timer 1 Clock Source */ 260 SFR(T1CNT0, 0xA4); /* Timer 1 Count Low Byte */ 261 SFR(T1CNT1, 0xA5); /* Timer 1 Count High Byte */ 262 SFR16(T1CNT, 0xA4); /* Timer 1 Count */ 263 SFR(T1MODE, 0xA1); /* Timer 1 Mode */ 264 SFR(T1PERIOD0, 0xA6); /* Timer 1 Period Low Byte */ 265 SFR(T1PERIOD1, 0xA7); /* Timer 1 Period High Byte */ 266 SFR16(T1PERIOD, 0xA6); /* Timer 1 Period */ 267 SFR(T1STATUS, 0xA3); /* Timer 1 Status */ 268 SFR(T2CLKSRC, 0xAA); /* Timer 2 Clock Source */ 269 SFR(T2CNT0, 0xAC); /* Timer 2 Count Low Byte */ 270 SFR(T2CNT1, 0xAD); /* Timer 2 Count High Byte */ 271 SFR16(T2CNT, 0xAC); /* Timer 2 Count */ 272 SFR(T2MODE, 0xA9); /* Timer 2 Mode */ 273 SFR(T2PERIOD0, 0xAE); /* Timer 2 Period Low Byte */ 274 SFR(T2PERIOD1, 0xAF); /* Timer 2 Period High Byte */ 275 SFR16(T2PERIOD, 0xAE); /* Timer 2 Period */ 276 SFR(T2STATUS, 0xAB); /* Timer 2 Status */ 277 SFR(U0CTRL, 0xE4); /* UART 0 Control */ 278 SFR(U0MODE, 0xE7); /* UART 0 Mode */ 279 SFR(U0SHREG, 0xE6); /* UART 0 Shift Register */ 280 SFR(U0STATUS, 0xE5); /* UART 0 Status */ 281 SFR(U1CTRL, 0xEC); /* UART 1 Control */ 282 SFR(U1MODE, 0xEF); /* UART 1 Mode */ 283 SFR(U1SHREG, 0xEE); /* UART 1 Shift Register */ 284 SFR(U1STATUS, 0xED); /* UART 1 Status */ 285 SFR(WDTCFG, 0xDA); /* Watchdog Configuration */ 286 SFR(WDTRESET, 0xDB); /* Watchdog Reset */ 287 SFR(WTCFGA, 0xF1); /* Wakeup Timer A Configuration */ 288 SFR(WTCFGB, 0xF9); /* Wakeup Timer B Configuration */ 289 SFR(WTCNTA0, 0xF2); /* Wakeup Counter A Low Byte */ 290 SFR(WTCNTA1, 0xF3); /* Wakeup Counter A High Byte */ 291 SFR16(WTCNTA, 0xF2); /* Wakeup Counter A */ 292 SFR(WTCNTB0, 0xFA); /* Wakeup Counter B Low Byte */ 293 SFR(WTCNTB1, 0xFB); /* Wakeup Counter B High Byte */ 294 SFR16(WTCNTB, 0xFA); /* Wakeup Counter B */ 295 SFR(WTCNTR1, 0xEB); /* Wakeup Counter High Byte Latch */ 296 SFR(WTEVTA0, 0xF4); /* Wakeup Event A Low Byte */ 297 SFR(WTEVTA1, 0xF5); /* Wakeup Event A High Byte */ 298 SFR16(WTEVTA, 0xF4); /* Wakeup Event A */ 299 SFR(WTEVTB0, 0xF6); /* Wakeup Event B Low Byte */ 300 SFR(WTEVTB1, 0xF7); /* Wakeup Event B High Byte */ 301 SFR16(WTEVTB, 0xF6); /* Wakeup Event B */ 302 SFR(WTEVTC0, 0xFC); /* Wakeup Event C Low Byte */ 303 SFR(WTEVTC1, 0xFD); /* Wakeup Event C High Byte */ 304 SFR16(WTEVTC, 0xFC); /* Wakeup Event C */ 305 SFR(WTEVTD0, 0xFE); /* Wakeup Event D Low Byte */ 306 SFR(WTEVTD1, 0xFF); /* Wakeup Event D High Byte */ 307 SFR16(WTEVTD, 0xFE); /* Wakeup Event D */ 308 SFR(WTIRQEN, 0xE9); /* Wakeup Timer Interrupt Enable */ 309 SFR(WTSTAT, 0xEA); /* Wakeup Timer Status */ 310 311 /* X Address Space */ 312 313 #define AX8052_RADIOBASE 0x4000 314 #define AX8052_RADIOBASENB 0x5000 315 316 SFRX(ADCCALG00GAIN0, 0x7030); /* ADC Calibration Range 00 Gain Low Byte */ 317 SFRX(ADCCALG00GAIN1, 0x7031); /* ADC Calibration Range 00 Gain High Byte */ 318 SFR16LEX(ADCCALG00GAIN, 0x7030); /* ADC Calibration Range 00 Gain */ 319 SFRX(ADCCALG01GAIN0, 0x7032); /* ADC Calibration Range 01 Gain Low Byte */ 320 SFRX(ADCCALG01GAIN1, 0x7033); /* ADC Calibration Range 01 Gain High Byte */ 321 SFR16LEX(ADCCALG01GAIN, 0x7032); /* ADC Calibration Range 01 Gain */ 322 SFRX(ADCCALG10GAIN0, 0x7034); /* ADC Calibration Range 10 Gain Low Byte */ 323 SFRX(ADCCALG10GAIN1, 0x7035); /* ADC Calibration Range 10 Gain High Byte */ 324 SFR16LEX(ADCCALG10GAIN, 0x7034); /* ADC Calibration Range 10 Gain */ 325 SFRX(ADCCALTEMPGAIN0, 0x7038); /* ADC Calibration Temperature Gain Low Byte */ 326 SFRX(ADCCALTEMPGAIN1, 0x7039); /* ADC Calibration Temperature Gain High Byte */ 327 SFR16LEX(ADCCALTEMPGAIN, 0x7038); /* ADC Calibration Temperature Gain */ 328 SFRX(ADCCALTEMPOFFS0, 0x703A); /* ADC Calibration Temperature Offset Low Byte */ 329 SFRX(ADCCALTEMPOFFS1, 0x703B); /* ADC Calibration Temperature Offset High Byte */ 330 SFR16LEX(ADCCALTEMPOFFS, 0x703A); /* ADC Calibration Temperature Offset */ 331 SFRX(ADCCH0VAL0, 0x7020); /* ADC Channel 0 Low Byte */ 332 SFRX(ADCCH0VAL1, 0x7021); /* ADC Channel 0 High Byte */ 333 SFR16LEX(ADCCH0VAL, 0x7020); /* ADC Channel 0 */ 334 SFRX(ADCCH1VAL0, 0x7022); /* ADC Channel 1 Low Byte */ 335 SFRX(ADCCH1VAL1, 0x7023); /* ADC Channel 1 High Byte */ 336 SFR16LEX(ADCCH1VAL, 0x7022); /* ADC Channel 1 */ 337 SFRX(ADCCH2VAL0, 0x7024); /* ADC Channel 2 Low Byte */ 338 SFRX(ADCCH2VAL1, 0x7025); /* ADC Channel 2 High Byte */ 339 SFR16LEX(ADCCH2VAL, 0x7024); /* ADC Channel 2 */ 340 SFRX(ADCCH3VAL0, 0x7026); /* ADC Channel 3 Low Byte */ 341 SFRX(ADCCH3VAL1, 0x7027); /* ADC Channel 3 High Byte */ 342 SFR16LEX(ADCCH3VAL, 0x7026); /* ADC Channel 3 */ 343 SFRX(ADCTUNE0, 0x7028); /* ADC Tuning 0 */ 344 SFRX(ADCTUNE1, 0x7029); /* ADC Tuning 1 */ 345 SFRX(ADCTUNE2, 0x702A); /* ADC Tuning 2 */ 346 SFRX(AESCONFIG, 0x7091); /* AES Configuration */ 347 SFRX(AESCURBLOCK, 0x7098); /* AES Current Block Number */ 348 SFRX(AESINADDR0, 0x7094); /* AES Input Address Low Byte */ 349 SFRX(AESINADDR1, 0x7095); /* AES Input Address High Byte */ 350 SFR16LEX(AESINADDR, 0x7094); /* AES Input Address */ 351 SFRX(AESKEYADDR0, 0x7092); /* AES Keystream Address Low Byte */ 352 SFRX(AESKEYADDR1, 0x7093); /* AES Keystream Address High Byte */ 353 SFR16LEX(AESKEYADDR, 0x7092); /* AES Keystream Address */ 354 SFRX(AESMODE, 0x7090); /* AES Mode */ 355 SFRX(AESOUTADDR0, 0x7096); /* AES Output Address Low Byte */ 356 SFRX(AESOUTADDR1, 0x7097); /* AES Output Address High Byte */ 357 SFR16LEX(AESOUTADDR, 0x7096); /* AES Output Address */ 358 SFRX(CLOCKGATE, 0x7F1B); /* Clock Gating */ 359 SFRX(DMA0ADDR0, 0x7010); /* DMA Channel 0 Address Low Byte */ 360 SFRX(DMA0ADDR1, 0x7011); /* DMA Channel 0 Address High Byte */ 361 SFR16LEX(DMA0ADDR, 0x7010); /* DMA Channel 0 Address */ 362 SFRX(DMA0CONFIG, 0x7014); /* DMA Channel 0 Configuration */ 363 SFRX(DMA1ADDR0, 0x7012); /* DMA Channel 1 Address Low Byte */ 364 SFRX(DMA1ADDR1, 0x7013); /* DMA Channel 1 Address High Byte */ 365 SFR16LEX(DMA1ADDR, 0x7012); /* DMA Channel 1 Address */ 366 SFRX(DMA1CONFIG, 0x7015); /* DMA Channel 1 Configuration */ 367 SFRX(FRCOSCCONFIG, 0x7070); /* Fast RC Oscillator Calibration Configuration */ 368 SFRX(FRCOSCCTRL, 0x7071); /* Fast RC Oscillator Control */ 369 SFRX(FRCOSCFREQ0, 0x7076); /* Fast RC Oscillator Frequency Tuning Low Byte */ 370 SFRX(FRCOSCFREQ1, 0x7077); /* Fast RC Oscillator Frequency Tuning High Byte */ 371 SFR16LEX(FRCOSCFREQ, 0x7076); /* Fast RC Oscillator Frequency Tuning */ 372 SFRX(FRCOSCKFILT0, 0x7072); /* Fast RC Oscillator Calibration Filter Constant Low Byte */ 373 SFRX(FRCOSCKFILT1, 0x7073); /* Fast RC Oscillator Calibration Filter Constant High Byte */ 374 SFR16LEX(FRCOSCKFILT, 0x7072); /* Fast RC Oscillator Calibration Filter Constant */ 375 SFRX(FRCOSCPER0, 0x7078); /* Fast RC Oscillator Period Low Byte */ 376 SFRX(FRCOSCPER1, 0x7079); /* Fast RC Oscillator Period High Byte */ 377 SFR16LEX(FRCOSCPER, 0x7078); /* Fast RC Oscillator Period */ 378 SFRX(FRCOSCREF0, 0x7074); /* Fast RC Oscillator Reference Frequency Low Byte */ 379 SFRX(FRCOSCREF1, 0x7075); /* Fast RC Oscillator Reference Frequency High Byte */ 380 SFR16LEX(FRCOSCREF, 0x7074); /* Fast RC Oscillator Reference Frequency */ 381 SFRX(ANALOGA, 0x7007); /* Port A Analog Mode */ 382 SFRX(GPIOENABLE, 0x700C); /* GPIO Port Enable */ 383 SFRX(EXTIRQ, 0x7003); /* External IRQ Configuration */ 384 SFRX(INTCHGA, 0x7000); /* Port A Interrupt on Change */ 385 SFRX(INTCHGB, 0x7001); /* Port B Interrupt on Change */ 386 SFRX(INTCHGC, 0x7002); /* Port C Interrupt on Change */ 387 SFRX(PALTA, 0x7008); /* Port A Alternate Function */ 388 SFRX(PALTB, 0x7009); /* Port B Alternate Function */ 389 SFRX(PALTC, 0x700A); /* Port C Alternate Function */ 390 SFRX(PINCHGA, 0x7004); /* Port A Level Change */ 391 SFRX(PINCHGB, 0x7005); /* Port B Level Change */ 392 SFRX(PINCHGC, 0x7006); /* Port C Level Change */ 393 SFRX(PINSEL, 0x700B); /* Port Input Selection */ 394 SFRX(LPOSCCONFIG, 0x7060); /* Low Power Oscillator Calibration Configuration */ 395 SFRX(LPOSCFREQ0, 0x7066); /* Low Power Oscillator Frequency Tuning Low Byte */ 396 SFRX(LPOSCFREQ1, 0x7067); /* Low Power Oscillator Frequency Tuning High Byte */ 397 SFR16LEX(LPOSCFREQ, 0x7066); /* Low Power Oscillator Frequency Tuning */ 398 SFRX(LPOSCKFILT0, 0x7062); /* Low Power Oscillator Calibration Filter Constant Low Byte */ 399 SFRX(LPOSCKFILT1, 0x7063); /* Low Power Oscillator Calibration Filter Constant High Byte */ 400 SFR16LEX(LPOSCKFILT, 0x7062); /* Low Power Oscillator Calibration Filter Constant */ 401 SFRX(LPOSCPER0, 0x7068); /* Low Power Oscillator Period Low Byte */ 402 SFRX(LPOSCPER1, 0x7069); /* Low Power Oscillator Period High Byte */ 403 SFR16LEX(LPOSCPER, 0x7068); /* Low Power Oscillator Period */ 404 SFRX(LPOSCREF0, 0x7064); /* Low Power Oscillator Reference Frequency Low Byte */ 405 SFRX(LPOSCREF1, 0x7065); /* Low Power Oscillator Reference Frequency High Byte */ 406 SFR16LEX(LPOSCREF, 0x7064); /* Low Power Oscillator Reference Frequency */ 407 SFRX(LPXOSCGM, 0x7054); /* Low Power Crystal Oscillator Transconductance */ 408 SFRX(OSCCALIB, 0x7053); /* Oscillator Calibration Interrupt / Status */ 409 SFRX(OSCFORCERUN, 0x7050); /* Oscillator Run Force */ 410 SFRX(OSCREADY, 0x7052); /* Oscillator Ready Status */ 411 SFRX(OSCRUN, 0x7051); /* Oscillator Run Status */ 412 SFRX(POWCTRL0, 0x7F10); /* Power Control 0 */ 413 SFRX(POWCTRL1, 0x7F11); /* Power Control 1 */ 414 SFRX(POWCTRL2, 0x7F12); /* Power Control 2 */ 415 SFRX(RADIOFDATAADDR0, 0x7040); /* Radio FIFO Data Register Address Low Byte */ 416 SFRX(RADIOFDATAADDR1, 0x7041); /* Radio FIFO Data Register Address High Byte */ 417 SFR16LEX(RADIOFDATAADDR, 0x7040); /* Radio FIFO Data Register Address */ 418 SFRX(RADIOFSTATADDR0, 0x7042); /* Radio FIFO Status Register Address Low Byte */ 419 SFRX(RADIOFSTATADDR1, 0x7043); /* Radio FIFO Status Register Address High Byte */ 420 SFR16LEX(RADIOFSTATADDR, 0x7042); /* Radio FIFO Status Register Address */ 421 SFRX(RADIOMUX, 0x7044); /* Radio Multiplexer Control */ 422 SFRX(RNGBYTE, 0x7081); /* True Random Byte */ 423 SFRX(RNGCLKSRC0, 0x7082); /* True Random Number Generator Clock Source 0 */ 424 SFRX(RNGCLKSRC1, 0x7083); /* True Random Number Generator Clock Source 1 */ 425 SFRX(RNGMODE, 0x7080); /* True Random Number Generator Mode */ 426 SFRX(SCRATCH0, 0x7084); /* Scratch Register 0 */ 427 SFRX(SCRATCH1, 0x7085); /* Scratch Register 1 */ 428 SFRX(SCRATCH2, 0x7086); /* Scratch Register 2 */ 429 SFRX(SCRATCH3, 0x7087); /* Scratch Register 3 */ 430 SFRX(SILICONREV, 0x7F00); /* Silicon Revision */ 431 SFRX(SPAREIN, 0x7F02); /* Spare Input */ 432 SFRX(SPAREOUT, 0x7F01); /* Spare Output */ 433 SFRX(TESTMUXA, 0x7F09); /* Test Multiplexer Port A */ 434 SFRX(TESTMUXB, 0x7F0A); /* Test Multiplexer Port B */ 435 SFRX(TESTMUXC, 0x7F0B); /* Test Multiplexer Port C */ 436 SFRX(TESTOBS, 0x7F08); /* Test Observation Address */ 437 SFRX(TESTOBSREAD0, 0x7F0E); /* Test Observation Vector Low Byte */ 438 SFRX(TESTOBSREAD1, 0x7F0F); /* Test Observation Vector High Byte */ 439 SFRX(TESTOBSSKIP0, 0x7F0C); /* Test Observation Vector Skip Low Byte */ 440 SFRX(TESTOBSSKIP1, 0x7F0D); /* Test Observation Vector Skip High Byte */ 441 SFRX(TMMUX, 0x7F03); /* Test Multiplexer Control */ 442 SFRX(XTALAMPL, 0x7F19); /* Crystal Oscillator Amplitude Control */ 443 SFRX(XTALOSC, 0x7F18); /* Crystal Oscillator Configuration */ 444 SFRX(XTALREADY, 0x7F1A); /* Crystal Oscillator Ready Mode */ 445 446 /* X Address Space aliases of SFR Address Space Registers */ 447 448 SFR16LEX(XDPTR0, 0x3F82); /* Data Pointer 0 */ 449 SFR16LEX(XDPTR1, 0x3F84); /* Data Pointer 1 */ 450 SFRX(XIE, 0x3FA8); /* Interrupt Enable */ 451 SFRX(XIP, 0x3FB8); /* Interrupt Priority */ 452 SFRX(XPCON, 0x3F87); /* Power Mode Control */ 453 SFRX(XADCCH0CONFIG, 0x3FCA); /* ADC Channel 0 Configuration */ 454 SFRX(XADCCH1CONFIG, 0x3FCB); /* ADC Channel 1 Configuration */ 455 SFRX(XADCCH2CONFIG, 0x3FD2); /* ADC Channel 2 Configuration */ 456 SFRX(XADCCH3CONFIG, 0x3FD3); /* ADC Channel 3 Configuration */ 457 SFRX(XADCCLKSRC, 0x3FD1); /* ADC Clock Source */ 458 SFRX(XADCCONV, 0x3FC9); /* ADC Conversion Source */ 459 SFRX(XANALOGCOMP, 0x3FE1); /* Analog Comparators */ 460 SFRX(XCLKCON, 0x3FC6); /* Clock Control */ 461 SFRX(XCLKSTAT, 0x3FC7); /* Clock Status */ 462 SFRX(XCODECONFIG, 0x3F97); /* Code Space Configuration */ 463 SFRX(XDBGLNKBUF, 0x3FE3); /* Debug Link Buffer */ 464 SFRX(XDBGLNKSTAT, 0x3FE2); /* Debug Link Status */ 465 SFRX(XDIRA, 0x3F89); /* Port A Direction */ 466 SFRX(XDIRB, 0x3F8A); /* Port B Direction */ 467 SFRX(XDIRC, 0x3F8B); /* Port C Direction */ 468 SFRX(XDIRR, 0x3F8E); /* Port R Direction */ 469 SFRX(XPINA, 0x3FC8); /* Port A Input */ 470 SFRX(XPINB, 0x3FE8); /* Port B Input */ 471 SFRX(XPINC, 0x3FF8); /* Port C Input */ 472 SFRX(XPINR, 0x3F8D); /* Port R Input */ 473 SFRX(XPORTA, 0x3F80); /* Port A Output */ 474 SFRX(XPORTB, 0x3F88); /* Port B Output */ 475 SFRX(XPORTC, 0x3F90); /* Port C Output */ 476 SFRX(XPORTR, 0x3F8C); /* Port R Output */ 477 SFRX(XIC0CAPT0, 0x3FCE); /* Input Capture 0 Low Byte */ 478 SFRX(XIC0CAPT1, 0x3FCF); /* Input Capture 0 High Byte */ 479 SFR16LEX(XIC0CAPT, 0x3FCE); /* Input Capture 0 */ 480 SFRX(XIC0MODE, 0x3FCC); /* Input Capture 0 Mode */ 481 SFRX(XIC0STATUS, 0x3FCD); /* Input Capture 0 Status */ 482 SFRX(XIC1CAPT0, 0x3FD6); /* Input Capture 1 Low Byte */ 483 SFRX(XIC1CAPT1, 0x3FD7); /* Input Capture 1 High Byte */ 484 SFR16LEX(XIC1CAPT, 0x3FD6); /* Input Capture 1 */ 485 SFRX(XIC1MODE, 0x3FD4); /* Input Capture 1 Mode */ 486 SFRX(XIC1STATUS, 0x3FD5); /* Input Capture 1 Status */ 487 SFRX(XNVADDR0, 0x3F92); /* Non-Volatile Memory Address Low Byte */ 488 SFRX(XNVADDR1, 0x3F93); /* Non-Volatile Memory Address High Byte */ 489 SFR16LEX(XNVADDR, 0x3F92); /* Non-Volatile Memory Address */ 490 SFRX(XNVDATA0, 0x3F94); /* Non-Volatile Memory Data Low Byte */ 491 SFRX(XNVDATA1, 0x3F95); /* Non-Volatile Memory Data High Byte */ 492 SFR16LEX(XNVDATA, 0x3F94); /* Non-Volatile Memory Data */ 493 SFRX(XNVKEY, 0x3F96); /* Non-Volatile Memory Write/Erase Key */ 494 SFRX(XNVSTATUS, 0x3F91); /* Non-Volatile Memory Command / Status */ 495 SFRX(XOC0COMP0, 0x3FBC); /* Output Compare 0 Low Byte */ 496 SFRX(XOC0COMP1, 0x3FBD); /* Output Compare 0 High Byte */ 497 SFR16LEX(XOC0COMP, 0x3FBC); /* Output Compare 0 */ 498 SFRX(XOC0MODE, 0x3FB9); /* Output Compare 0 Mode */ 499 SFRX(XOC0PIN, 0x3FBA); /* Output Compare 0 Pin Configuration */ 500 SFRX(XOC0STATUS, 0x3FBB); /* Output Compare 0 Status */ 501 SFRX(XOC1COMP0, 0x3FC4); /* Output Compare 1 Low Byte */ 502 SFRX(XOC1COMP1, 0x3FC5); /* Output Compare 1 High Byte */ 503 SFR16LEX(XOC1COMP, 0x3FC4); /* Output Compare 1 */ 504 SFRX(XOC1MODE, 0x3FC1); /* Output Compare 1 Mode */ 505 SFRX(XOC1PIN, 0x3FC2); /* Output Compare 1 Pin Configuration */ 506 SFRX(XOC1STATUS, 0x3FC3); /* Output Compare 1 Status */ 507 SFRX(XRADIOACC, 0x3FB1); /* Radio Controller Access Mode */ 508 SFRX(XRADIOADDR0, 0x3FB3); /* Radio Register Address Low Byte */ 509 SFRX(XRADIOADDR1, 0x3FB2); /* Radio Register Address High Byte */ 510 SFRX(XRADIODATA0, 0x3FB7); /* Radio Register Data 0 */ 511 SFRX(XRADIODATA1, 0x3FB6); /* Radio Register Data 1 */ 512 SFRX(XRADIODATA2, 0x3FB5); /* Radio Register Data 2 */ 513 SFRX(XRADIODATA3, 0x3FB4); /* Radio Register Data 3 */ 514 SFRX(XRADIOSTAT0, 0x3FBE); /* Radio Access Status Low Byte */ 515 SFRX(XRADIOSTAT1, 0x3FBF); /* Radio Access Status High Byte */ 516 SFR16LEX(XRADIOSTAT, 0x3FBE); /* Radio Access Status */ 517 SFRX(XSPCLKSRC, 0x3FDF); /* SPI Clock Source */ 518 SFRX(XSPMODE, 0x3FDC); /* SPI Mode */ 519 SFRX(XSPSHREG, 0x3FDE); /* SPI Shift Register */ 520 SFRX(XSPSTATUS, 0x3FDD); /* SPI Status */ 521 SFRX(XT0CLKSRC, 0x3F9A); /* Timer 0 Clock Source */ 522 SFRX(XT0CNT0, 0x3F9C); /* Timer 0 Count Low Byte */ 523 SFRX(XT0CNT1, 0x3F9D); /* Timer 0 Count High Byte */ 524 SFR16LEX(XT0CNT, 0x3F9C); /* Timer 0 Count */ 525 SFRX(XT0MODE, 0x3F99); /* Timer 0 Mode */ 526 SFRX(XT0PERIOD0, 0x3F9E); /* Timer 0 Period Low Byte */ 527 SFRX(XT0PERIOD1, 0x3F9F); /* Timer 0 Period High Byte */ 528 SFR16LEX(XT0PERIOD, 0x3F9E); /* Timer 0 Period */ 529 SFRX(XT0STATUS, 0x3F9B); /* Timer 0 Status */ 530 SFRX(XT1CLKSRC, 0x3FA2); /* Timer 1 Clock Source */ 531 SFRX(XT1CNT0, 0x3FA4); /* Timer 1 Count Low Byte */ 532 SFRX(XT1CNT1, 0x3FA5); /* Timer 1 Count High Byte */ 533 SFR16LEX(XT1CNT, 0x3FA4); /* Timer 1 Count */ 534 SFRX(XT1MODE, 0x3FA1); /* Timer 1 Mode */ 535 SFRX(XT1PERIOD0, 0x3FA6); /* Timer 1 Period Low Byte */ 536 SFRX(XT1PERIOD1, 0x3FA7); /* Timer 1 Period High Byte */ 537 SFR16LEX(XT1PERIOD, 0x3FA6); /* Timer 1 Period */ 538 SFRX(XT1STATUS, 0x3FA3); /* Timer 1 Status */ 539 SFRX(XT2CLKSRC, 0x3FAA); /* Timer 2 Clock Source */ 540 SFRX(XT2CNT0, 0x3FAC); /* Timer 2 Count Low Byte */ 541 SFRX(XT2CNT1, 0x3FAD); /* Timer 2 Count High Byte */ 542 SFR16LEX(XT2CNT, 0x3FAC); /* Timer 2 Count */ 543 SFRX(XT2MODE, 0x3FA9); /* Timer 2 Mode */ 544 SFRX(XT2PERIOD0, 0x3FAE); /* Timer 2 Period Low Byte */ 545 SFRX(XT2PERIOD1, 0x3FAF); /* Timer 2 Period High Byte */ 546 SFR16LEX(XT2PERIOD, 0x3FAE); /* Timer 2 Period */ 547 SFRX(XT2STATUS, 0x3FAB); /* Timer 2 Status */ 548 SFRX(XU0CTRL, 0x3FE4); /* UART 0 Control */ 549 SFRX(XU0MODE, 0x3FE7); /* UART 0 Mode */ 550 SFRX(XU0SHREG, 0x3FE6); /* UART 0 Shift Register */ 551 SFRX(XU0STATUS, 0x3FE5); /* UART 0 Status */ 552 SFRX(XU1CTRL, 0x3FEC); /* UART 1 Control */ 553 SFRX(XU1MODE, 0x3FEF); /* UART 1 Mode */ 554 SFRX(XU1SHREG, 0x3FEE); /* UART 1 Shift Register */ 555 SFRX(XU1STATUS, 0x3FED); /* UART 1 Status */ 556 SFRX(XWDTCFG, 0x3FDA); /* Watchdog Configuration */ 557 SFRX(XWDTRESET, 0x3FDB); /* Watchdog Reset */ 558 SFRX(XWTCFGA, 0x3FF1); /* Wakeup Timer A Configuration */ 559 SFRX(XWTCFGB, 0x3FF9); /* Wakeup Timer B Configuration */ 560 SFRX(XWTCNTA0, 0x3FF2); /* Wakeup Counter A Low Byte */ 561 SFRX(XWTCNTA1, 0x3FF3); /* Wakeup Counter A High Byte */ 562 SFR16LEX(XWTCNTA, 0x3FF2); /* Wakeup Counter A */ 563 SFRX(XWTCNTB0, 0x3FFA); /* Wakeup Counter B Low Byte */ 564 SFRX(XWTCNTB1, 0x3FFB); /* Wakeup Counter B High Byte */ 565 SFR16LEX(XWTCNTB, 0x3FFA); /* Wakeup Counter B */ 566 SFRX(XWTCNTR1, 0x3FEB); /* Wakeup Counter High Byte Latch */ 567 SFRX(XWTEVTA0, 0x3FF4); /* Wakeup Event A Low Byte */ 568 SFRX(XWTEVTA1, 0x3FF5); /* Wakeup Event A High Byte */ 569 SFR16LEX(XWTEVTA, 0x3FF4); /* Wakeup Event A */ 570 SFRX(XWTEVTB0, 0x3FF6); /* Wakeup Event B Low Byte */ 571 SFRX(XWTEVTB1, 0x3FF7); /* Wakeup Event B High Byte */ 572 SFR16LEX(XWTEVTB, 0x3FF6); /* Wakeup Event B */ 573 SFRX(XWTEVTC0, 0x3FFC); /* Wakeup Event C Low Byte */ 574 SFRX(XWTEVTC1, 0x3FFD); /* Wakeup Event C High Byte */ 575 SFR16LEX(XWTEVTC, 0x3FFC); /* Wakeup Event C */ 576 SFRX(XWTEVTD0, 0x3FFE); /* Wakeup Event D Low Byte */ 577 SFRX(XWTEVTD1, 0x3FFF); /* Wakeup Event D High Byte */ 578 SFR16LEX(XWTEVTD, 0x3FFE); /* Wakeup Event D */ 579 SFRX(XWTIRQEN, 0x3FE9); /* Wakeup Timer Interrupt Enable */ 580 SFRX(XWTSTAT, 0x3FEA); /* Wakeup Timer Status */ 581 582 583 /* Radio Registers, X Address Space */ 584 585 SFRX(AX5043_AFSKCTRL, 0x4114); /* AFSK Control */ 586 SFRX(AX5043_AFSKMARK0, 0x4113); /* AFSK Mark (1) Frequency 0 */ 587 SFRX(AX5043_AFSKMARK1, 0x4112); /* AFSK Mark (1) Frequency 1 */ 588 SFRX(AX5043_AFSKSPACE0, 0x4111); /* AFSK Space (0) Frequency 0 */ 589 SFRX(AX5043_AFSKSPACE1, 0x4110); /* AFSK Space (0) Frequency 1 */ 590 SFRX(AX5043_AGCCOUNTER, 0x4043); /* AGC Counter */ 591 SFRX(AX5043_AMPLFILTER, 0x4115); /* Amplitude Filter */ 592 SFRX(AX5043_BBOFFSCAP, 0x4189); /* Baseband Offset Compensation Capacitors */ 593 SFRX(AX5043_BBTUNE, 0x4188); /* Baseband Tuning */ 594 SFRX(AX5043_BGNDRSSI, 0x4041); /* Background RSSI */ 595 SFRX(AX5043_BGNDRSSIGAIN, 0x422E); /* Background RSSI Averaging Time Constant */ 596 SFRX(AX5043_BGNDRSSITHR, 0x422F); /* Background RSSI Relative Threshold */ 597 SFRX(AX5043_CRCINIT0, 0x4017); /* CRC Initial Value 0 */ 598 SFRX(AX5043_CRCINIT1, 0x4016); /* CRC Initial Value 1 */ 599 SFRX(AX5043_CRCINIT2, 0x4015); /* CRC Initial Value 2 */ 600 SFRX(AX5043_CRCINIT3, 0x4014); /* CRC Initial Value 3 */ 601 SFRX(AX5043_DACCONFIG, 0x4332); /* DAC Configuration */ 602 SFRX(AX5043_DACVALUE0, 0x4331); /* DAC Value 0 */ 603 SFRX(AX5043_DACVALUE1, 0x4330); /* DAC Value 1 */ 604 SFRX(AX5043_DECIMATION, 0x4102); /* Decimation Factor */ 605 SFRX(AX5043_DIVERSITY, 0x4042); /* Antenna Diversity Configuration */ 606 SFRX(AX5043_DSPMODECFG, 0x4320); /* DSP Mode Setting */ 607 SFRX(AX5043_DSPMODESHREG, 0x406F); /* DSPmode SPI Shift Register Access */ 608 SFRX(AX5043_DSPMODESKIP0, 0x4322); /* DSP Mode Skip 0 */ 609 SFRX(AX5043_DSPMODESKIP1, 0x4321); /* DSP Mode Skip 1 */ 610 SFRX(AX5043_ENCODING, 0x4011); /* Encoding */ 611 SFRX(AX5043_FEC, 0x4018); /* Forward Error Correction */ 612 SFRX(AX5043_FECSTATUS, 0x401A); /* Forward Error Correction Status */ 613 SFRX(AX5043_FECSYNC, 0x4019); /* Forward Error Correction Sync Threshold */ 614 SFRX(AX5043_FIFOCOUNT0, 0x402B); /* Number of Words currently in FIFO 0 */ 615 SFRX(AX5043_FIFOCOUNT1, 0x402A); /* Number of Words currently in FIFO 1 */ 616 SFRX(AX5043_FIFODATA, 0x4029); /* FIFO Data */ 617 SFRX(AX5043_FIFOFREE0, 0x402D); /* Number of Words that can be written to FIFO 0 */ 618 SFRX(AX5043_FIFOFREE1, 0x402C); /* Number of Words that can be written to FIFO 1 */ 619 SFRX(AX5043_FIFOSTAT, 0x4028); /* FIFO Control */ 620 SFRX(AX5043_FIFOTHRESH0, 0x402F); /* FIFO Threshold 0 */ 621 SFRX(AX5043_FIFOTHRESH1, 0x402E); /* FIFO Threshold 1 */ 622 SFRX(AX5043_FRAMING, 0x4012); /* Framing Mode */ 623 SFRX(AX5043_FREQA0, 0x4037); /* Frequency A 0 */ 624 SFRX(AX5043_FREQA1, 0x4036); /* Frequency A 1 */ 625 SFRX(AX5043_FREQA2, 0x4035); /* Frequency A 2 */ 626 SFRX(AX5043_FREQA3, 0x4034); /* Frequency A 3 */ 627 SFRX(AX5043_FREQB0, 0x403F); /* Frequency B 0 */ 628 SFRX(AX5043_FREQB1, 0x403E); /* Frequency B 1 */ 629 SFRX(AX5043_FREQB2, 0x403D); /* Frequency B 2 */ 630 SFRX(AX5043_FREQB3, 0x403C); /* Frequency B 3 */ 631 SFRX(AX5043_FSKDEV0, 0x4163); /* FSK Deviation 0 */ 632 SFRX(AX5043_FSKDEV1, 0x4162); /* FSK Deviation 1 */ 633 SFRX(AX5043_FSKDEV2, 0x4161); /* FSK Deviation 2 */ 634 SFRX(AX5043_FSKDMAX0, 0x410D); /* Four FSK Rx Maximum Deviation 0 */ 635 SFRX(AX5043_FSKDMAX1, 0x410C); /* Four FSK Rx Maximum Deviation 1 */ 636 SFRX(AX5043_FSKDMIN0, 0x410F); /* Four FSK Rx Minimum Deviation 0 */ 637 SFRX(AX5043_FSKDMIN1, 0x410E); /* Four FSK Rx Minimum Deviation 1 */ 638 SFRX(AX5043_GPADC13VALUE0, 0x4309); /* GPADC13 Value 0 */ 639 SFRX(AX5043_GPADC13VALUE1, 0x4308); /* GPADC13 Value 1 */ 640 SFRX(AX5043_GPADC1VALUE0, 0x430B); /* GPADC1 Value 0 */ 641 SFRX(AX5043_GPADC1VALUE1, 0x430A); /* GPADC1 Value 1 */ 642 SFRX(AX5043_GPADC2VALUE0, 0x430D); /* GPADC2 Value 0 */ 643 SFRX(AX5043_GPADC2VALUE1, 0x430C); /* GPADC2 Value 1 */ 644 SFRX(AX5043_GPADC3VALUE0, 0x430F); /* GPADC3 Value 0 */ 645 SFRX(AX5043_GPADC3VALUE1, 0x430E); /* GPADC3 Value 1 */ 646 SFRX(AX5043_GPADCCTRL, 0x4300); /* General Purpose ADC Control */ 647 SFRX(AX5043_GPADCPERIOD, 0x4301); /* GPADC Sampling Period */ 648 SFRX(AX5043_IFFREQ0, 0x4101); /* 2nd LO / IF Frequency 0 */ 649 SFRX(AX5043_IFFREQ1, 0x4100); /* 2nd LO / IF Frequency 1 */ 650 SFRX(AX5043_IRQINVERSION0, 0x400B); /* IRQ Inversion 0 */ 651 SFRX(AX5043_IRQINVERSION1, 0x400A); /* IRQ Inversion 1 */ 652 SFRX(AX5043_IRQMASK0, 0x4007); /* IRQ Mask 0 */ 653 SFRX(AX5043_IRQMASK1, 0x4006); /* IRQ Mask 1 */ 654 SFRX(AX5043_IRQREQUEST0, 0x400D); /* IRQ Request 0 */ 655 SFRX(AX5043_IRQREQUEST1, 0x400C); /* IRQ Request 1 */ 656 SFRX(AX5043_LPOSCCONFIG, 0x4310); /* Low Power Oscillator Calibration Configuration */ 657 SFRX(AX5043_LPOSCFREQ0, 0x4317); /* Low Power Oscillator Frequency Tuning Low Byte */ 658 SFRX(AX5043_LPOSCFREQ1, 0x4316); /* Low Power Oscillator Frequency Tuning High Byte */ 659 SFRX(AX5043_LPOSCKFILT0, 0x4313); /* Low Power Oscillator Calibration Filter Constant Low Byte */ 660 SFRX(AX5043_LPOSCKFILT1, 0x4312); /* Low Power Oscillator Calibration Filter Constant High Byte */ 661 SFRX(AX5043_LPOSCPER0, 0x4319); /* Low Power Oscillator Period Low Byte */ 662 SFRX(AX5043_LPOSCPER1, 0x4318); /* Low Power Oscillator Period High Byte */ 663 SFRX(AX5043_LPOSCREF0, 0x4315); /* Low Power Oscillator Reference Frequency Low Byte */ 664 SFRX(AX5043_LPOSCREF1, 0x4314); /* Low Power Oscillator Reference Frequency High Byte */ 665 SFRX(AX5043_LPOSCSTATUS, 0x4311); /* Low Power Oscillator Calibration Status */ 666 SFRX(AX5043_MATCH0LEN, 0x4214); /* Pattern Match Unit 0, Pattern Length */ 667 SFRX(AX5043_MATCH0MAX, 0x4216); /* Pattern Match Unit 0, Maximum Match */ 668 SFRX(AX5043_MATCH0MIN, 0x4215); /* Pattern Match Unit 0, Minimum Match */ 669 SFRX(AX5043_MATCH0PAT0, 0x4213); /* Pattern Match Unit 0, Pattern 0 */ 670 SFRX(AX5043_MATCH0PAT1, 0x4212); /* Pattern Match Unit 0, Pattern 1 */ 671 SFRX(AX5043_MATCH0PAT2, 0x4211); /* Pattern Match Unit 0, Pattern 2 */ 672 SFRX(AX5043_MATCH0PAT3, 0x4210); /* Pattern Match Unit 0, Pattern 3 */ 673 SFRX(AX5043_MATCH1LEN, 0x421C); /* Pattern Match Unit 1, Pattern Length */ 674 SFRX(AX5043_MATCH1MAX, 0x421E); /* Pattern Match Unit 1, Maximum Match */ 675 SFRX(AX5043_MATCH1MIN, 0x421D); /* Pattern Match Unit 1, Minimum Match */ 676 SFRX(AX5043_MATCH1PAT0, 0x4219); /* Pattern Match Unit 1, Pattern 0 */ 677 SFRX(AX5043_MATCH1PAT1, 0x4218); /* Pattern Match Unit 1, Pattern 1 */ 678 SFRX(AX5043_MAXDROFFSET0, 0x4108); /* Maximum Receiver Datarate Offset 0 */ 679 SFRX(AX5043_MAXDROFFSET1, 0x4107); /* Maximum Receiver Datarate Offset 1 */ 680 SFRX(AX5043_MAXDROFFSET2, 0x4106); /* Maximum Receiver Datarate Offset 2 */ 681 SFRX(AX5043_MAXRFOFFSET0, 0x410B); /* Maximum Receiver RF Offset 0 */ 682 SFRX(AX5043_MAXRFOFFSET1, 0x410A); /* Maximum Receiver RF Offset 1 */ 683 SFRX(AX5043_MAXRFOFFSET2, 0x4109); /* Maximum Receiver RF Offset 2 */ 684 SFRX(AX5043_MODCFGA, 0x4164); /* Modulator Configuration A */ 685 SFRX(AX5043_MODCFGF, 0x4160); /* Modulator Configuration F */ 686 SFRX(AX5043_MODULATION, 0x4010); /* Modulation */ 687 SFRX(AX5043_PINFUNCANTSEL, 0x4025); /* Pin Function ANTSEL */ 688 SFRX(AX5043_PINFUNCDATA, 0x4023); /* Pin Function DATA */ 689 SFRX(AX5043_PINFUNCDCLK, 0x4022); /* Pin Function DCLK */ 690 SFRX(AX5043_PINFUNCIRQ, 0x4024); /* Pin Function IRQ */ 691 SFRX(AX5043_PINFUNCPWRAMP, 0x4026); /* Pin Function PWRAMP */ 692 SFRX(AX5043_PINFUNCSYSCLK, 0x4021); /* Pin Function SYSCLK */ 693 SFRX(AX5043_PINSTATE, 0x4020); /* Pin State */ 694 SFRX(AX5043_PKTACCEPTFLAGS, 0x4233); /* Packet Controller Accept Flags */ 695 SFRX(AX5043_PKTCHUNKSIZE, 0x4230); /* Packet Chunk Size */ 696 SFRX(AX5043_PKTMISCFLAGS, 0x4231); /* Packet Controller Miscellaneous Flags */ 697 SFRX(AX5043_PKTSTOREFLAGS, 0x4232); /* Packet Controller Store Flags */ 698 SFRX(AX5043_PLLCPI, 0x4031); /* PLL Charge Pump Current */ 699 SFRX(AX5043_PLLCPIBOOST, 0x4039); /* PLL Charge Pump Current (Boosted) */ 700 SFRX(AX5043_PLLLOCKDET, 0x4182); /* PLL Lock Detect Delay */ 701 SFRX(AX5043_PLLLOOP, 0x4030); /* PLL Loop Filter Settings */ 702 SFRX(AX5043_PLLLOOPBOOST, 0x4038); /* PLL Loop Filter Settings (Boosted) */ 703 SFRX(AX5043_PLLRANGINGA, 0x4033); /* PLL Autoranging A */ 704 SFRX(AX5043_PLLRANGINGB, 0x403B); /* PLL Autoranging B */ 705 SFRX(AX5043_PLLRNGCLK, 0x4183); /* PLL Autoranging Clock */ 706 SFRX(AX5043_PLLVCODIV, 0x4032); /* PLL Divider Settings */ 707 SFRX(AX5043_PLLVCOI, 0x4180); /* PLL VCO Current */ 708 SFRX(AX5043_PLLVCOIR, 0x4181); /* PLL VCO Current Readback */ 709 SFRX(AX5043_POWIRQMASK, 0x4005); /* Power Management Interrupt Mask */ 710 SFRX(AX5043_POWSTAT, 0x4003); /* Power Management Status */ 711 SFRX(AX5043_POWSTICKYSTAT, 0x4004); /* Power Management Sticky Status */ 712 SFRX(AX5043_PWRAMP, 0x4027); /* PWRAMP Control */ 713 SFRX(AX5043_PWRMODE, 0x4002); /* Power Mode */ 714 SFRX(AX5043_RADIOEVENTMASK0, 0x4009); /* Radio Event Mask 0 */ 715 SFRX(AX5043_RADIOEVENTMASK1, 0x4008); /* Radio Event Mask 1 */ 716 SFRX(AX5043_RADIOEVENTREQ0, 0x400F); /* Radio Event Request 0 */ 717 SFRX(AX5043_RADIOEVENTREQ1, 0x400E); /* Radio Event Request 1 */ 718 SFRX(AX5043_RADIOSTATE, 0x401C); /* Radio Controller State */ 719 SFRX(AX5043_RSSI, 0x4040); /* Received Signal Strength Indicator */ 720 SFRX(AX5043_RSSIABSTHR, 0x422D); /* RSSI Absolute Threshold */ 721 SFRX(AX5043_RSSIREFERENCE, 0x422C); /* RSSI Offset */ 722 SFRX(AX5043_RXDATARATE0, 0x4105); /* Receiver Datarate 0 */ 723 SFRX(AX5043_RXDATARATE1, 0x4104); /* Receiver Datarate 1 */ 724 SFRX(AX5043_RXDATARATE2, 0x4103); /* Receiver Datarate 2 */ 725 SFRX(AX5043_SCRATCH, 0x4001); /* Scratch */ 726 SFRX(AX5043_SILICONREVISION, 0x4000); /* Silicon Revision */ 727 SFRX(AX5043_TIMER0, 0x405B); /* 1MHz Timer 0 */ 728 SFRX(AX5043_TIMER1, 0x405A); /* 1MHz Timer 1 */ 729 SFRX(AX5043_TIMER2, 0x4059); /* 1MHz Timer 2 */ 730 SFRX(AX5043_TMGRXAGC, 0x4227); /* Receiver AGC Settling Time */ 731 SFRX(AX5043_TMGRXBOOST, 0x4223); /* Receive PLL Boost Time */ 732 SFRX(AX5043_TMGRXCOARSEAGC, 0x4226); /* Receive Coarse AGC Time */ 733 SFRX(AX5043_TMGRXOFFSACQ, 0x4225); /* Receive Baseband DC Offset Acquisition Time */ 734 SFRX(AX5043_TMGRXPREAMBLE1, 0x4229); /* Receiver Preamble 1 Timeout */ 735 SFRX(AX5043_TMGRXPREAMBLE2, 0x422A); /* Receiver Preamble 2 Timeout */ 736 SFRX(AX5043_TMGRXPREAMBLE3, 0x422B); /* Receiver Preamble 3 Timeout */ 737 SFRX(AX5043_TMGRXRSSI, 0x4228); /* Receiver RSSI Settling Time */ 738 SFRX(AX5043_TMGRXSETTLE, 0x4224); /* Receive PLL (post Boost) Settling Time */ 739 SFRX(AX5043_TMGTXBOOST, 0x4220); /* Transmit PLL Boost Time */ 740 SFRX(AX5043_TMGTXSETTLE, 0x4221); /* Transmit PLL (post Boost) Settling Time */ 741 SFRX(AX5043_TRKAFSKDEMOD0, 0x4055); /* AFSK Demodulator Tracking 0 */ 742 SFRX(AX5043_TRKAFSKDEMOD1, 0x4054); /* AFSK Demodulator Tracking 1 */ 743 SFRX(AX5043_TRKAMPLITUDE0, 0x4049); /* Amplitude Tracking 0 */ 744 SFRX(AX5043_TRKAMPLITUDE1, 0x4048); /* Amplitude Tracking 1 */ 745 SFRX(AX5043_TRKDATARATE0, 0x4047); /* Datarate Tracking 0 */ 746 SFRX(AX5043_TRKDATARATE1, 0x4046); /* Datarate Tracking 1 */ 747 SFRX(AX5043_TRKDATARATE2, 0x4045); /* Datarate Tracking 2 */ 748 SFRX(AX5043_TRKFREQ0, 0x4051); /* Frequency Tracking 0 */ 749 SFRX(AX5043_TRKFREQ1, 0x4050); /* Frequency Tracking 1 */ 750 SFRX(AX5043_TRKFSKDEMOD0, 0x4053); /* FSK Demodulator Tracking 0 */ 751 SFRX(AX5043_TRKFSKDEMOD1, 0x4052); /* FSK Demodulator Tracking 1 */ 752 SFRX(AX5043_TRKPHASE0, 0x404B); /* Phase Tracking 0 */ 753 SFRX(AX5043_TRKPHASE1, 0x404A); /* Phase Tracking 1 */ 754 SFRX(AX5043_TRKRFFREQ0, 0x404F); /* RF Frequency Tracking 0 */ 755 SFRX(AX5043_TRKRFFREQ1, 0x404E); /* RF Frequency Tracking 1 */ 756 SFRX(AX5043_TRKRFFREQ2, 0x404D); /* RF Frequency Tracking 2 */ 757 SFRX(AX5043_TXPWRCOEFFA0, 0x4169); /* Transmitter Predistortion Coefficient A 0 */ 758 SFRX(AX5043_TXPWRCOEFFA1, 0x4168); /* Transmitter Predistortion Coefficient A 1 */ 759 SFRX(AX5043_TXPWRCOEFFB0, 0x416B); /* Transmitter Predistortion Coefficient B 0 */ 760 SFRX(AX5043_TXPWRCOEFFB1, 0x416A); /* Transmitter Predistortion Coefficient B 1 */ 761 SFRX(AX5043_TXPWRCOEFFC0, 0x416D); /* Transmitter Predistortion Coefficient C 0 */ 762 SFRX(AX5043_TXPWRCOEFFC1, 0x416C); /* Transmitter Predistortion Coefficient C 1 */ 763 SFRX(AX5043_TXPWRCOEFFD0, 0x416F); /* Transmitter Predistortion Coefficient D 0 */ 764 SFRX(AX5043_TXPWRCOEFFD1, 0x416E); /* Transmitter Predistortion Coefficient D 1 */ 765 SFRX(AX5043_TXPWRCOEFFE0, 0x4171); /* Transmitter Predistortion Coefficient E 0 */ 766 SFRX(AX5043_TXPWRCOEFFE1, 0x4170); /* Transmitter Predistortion Coefficient E 1 */ 767 SFRX(AX5043_TXRATE0, 0x4167); /* Transmitter Bitrate 0 */ 768 SFRX(AX5043_TXRATE1, 0x4166); /* Transmitter Bitrate 1 */ 769 SFRX(AX5043_TXRATE2, 0x4165); /* Transmitter Bitrate 2 */ 770 SFRX(AX5043_WAKEUP0, 0x406B); /* Wakeup Time 0 */ 771 SFRX(AX5043_WAKEUP1, 0x406A); /* Wakeup Time 1 */ 772 SFRX(AX5043_WAKEUPFREQ0, 0x406D); /* Wakeup Frequency 0 */ 773 SFRX(AX5043_WAKEUPFREQ1, 0x406C); /* Wakeup Frequency 1 */ 774 SFRX(AX5043_WAKEUPTIMER0, 0x4069); /* Wakeup Timer 0 */ 775 SFRX(AX5043_WAKEUPTIMER1, 0x4068); /* Wakeup Timer 1 */ 776 SFRX(AX5043_WAKEUPXOEARLY, 0x406E); /* Wakeup Crystal Oscillator Early */ 777 SFRX(AX5043_XTALCAP, 0x4184); /* Crystal Oscillator Load Capacitance */ 778 SFRX(AX5043_XTALSTATUS, 0x401D); /* Crystal Oscillator Status */ 779 780 #if defined AX5043V1 781 SFRX(AX5043_AGCGAIN0, 0x4120); /* AGC Speed */ 782 SFRX(AX5043_AGCGAIN1, 0x412E); /* AGC Speed */ 783 SFRX(AX5043_AGCGAIN2, 0x413C); /* AGC Speed */ 784 SFRX(AX5043_AGCGAIN3, 0x414A); /* AGC Speed */ 785 SFRX(AX5043_AGCTARGET0, 0x4121); /* AGC Target */ 786 SFRX(AX5043_AGCTARGET1, 0x412F); /* AGC Target */ 787 SFRX(AX5043_AGCTARGET2, 0x413D); /* AGC Target */ 788 SFRX(AX5043_AGCTARGET3, 0x414B); /* AGC Target */ 789 SFRX(AX5043_AMPLITUDEGAIN0, 0x4129); /* Amplitude Estimator Bandwidth */ 790 SFRX(AX5043_AMPLITUDEGAIN1, 0x4137); /* Amplitude Estimator Bandwidth */ 791 SFRX(AX5043_AMPLITUDEGAIN2, 0x4145); /* Amplitude Estimator Bandwidth */ 792 SFRX(AX5043_AMPLITUDEGAIN3, 0x4153); /* Amplitude Estimator Bandwidth */ 793 SFRX(AX5043_BBOFFSRES0, 0x412D); /* Baseband Offset Compensation Resistors */ 794 SFRX(AX5043_BBOFFSRES1, 0x413B); /* Baseband Offset Compensation Resistors */ 795 SFRX(AX5043_BBOFFSRES2, 0x4149); /* Baseband Offset Compensation Resistors */ 796 SFRX(AX5043_BBOFFSRES3, 0x4157); /* Baseband Offset Compensation Resistors */ 797 SFRX(AX5043_DRGAIN0, 0x4123); /* Data Rate Estimator Bandwidth */ 798 SFRX(AX5043_DRGAIN1, 0x4131); /* Data Rate Estimator Bandwidth */ 799 SFRX(AX5043_DRGAIN2, 0x413F); /* Data Rate Estimator Bandwidth */ 800 SFRX(AX5043_DRGAIN3, 0x414D); /* Data Rate Estimator Bandwidth */ 801 SFRX(AX5043_FOURFSK0, 0x412C); /* Four FSK Control */ 802 SFRX(AX5043_FOURFSK1, 0x413A); /* Four FSK Control */ 803 SFRX(AX5043_FOURFSK2, 0x4148); /* Four FSK Control */ 804 SFRX(AX5043_FOURFSK3, 0x4156); /* Four FSK Control */ 805 SFRX(AX5043_FREQDEV00, 0x412B); /* Receiver Frequency Deviation 0 */ 806 SFRX(AX5043_FREQDEV01, 0x4139); /* Receiver Frequency Deviation 0 */ 807 SFRX(AX5043_FREQDEV02, 0x4147); /* Receiver Frequency Deviation 0 */ 808 SFRX(AX5043_FREQDEV03, 0x4155); /* Receiver Frequency Deviation 0 */ 809 SFRX(AX5043_FREQDEV10, 0x412A); /* Receiver Frequency Deviation 1 */ 810 SFRX(AX5043_FREQDEV11, 0x4138); /* Receiver Frequency Deviation 1 */ 811 SFRX(AX5043_FREQDEV12, 0x4146); /* Receiver Frequency Deviation 1 */ 812 SFRX(AX5043_FREQDEV13, 0x4154); /* Receiver Frequency Deviation 1 */ 813 SFRX(AX5043_FREQUENCYGAINA0, 0x4125); /* Frequency Estimator Bandwidth A */ 814 SFRX(AX5043_FREQUENCYGAINA1, 0x4133); /* Frequency Estimator Bandwidth A */ 815 SFRX(AX5043_FREQUENCYGAINA2, 0x4141); /* Frequency Estimator Bandwidth A */ 816 SFRX(AX5043_FREQUENCYGAINA3, 0x414F); /* Frequency Estimator Bandwidth A */ 817 SFRX(AX5043_FREQUENCYGAINB0, 0x4126); /* Frequency Estimator Bandwidth B */ 818 SFRX(AX5043_FREQUENCYGAINB1, 0x4134); /* Frequency Estimator Bandwidth B */ 819 SFRX(AX5043_FREQUENCYGAINB2, 0x4142); /* Frequency Estimator Bandwidth B */ 820 SFRX(AX5043_FREQUENCYGAINB3, 0x4150); /* Frequency Estimator Bandwidth B */ 821 SFRX(AX5043_FREQUENCYGAINC0, 0x4127); /* Frequency Estimator Bandwidth C */ 822 SFRX(AX5043_FREQUENCYGAINC1, 0x4135); /* Frequency Estimator Bandwidth C */ 823 SFRX(AX5043_FREQUENCYGAINC2, 0x4143); /* Frequency Estimator Bandwidth C */ 824 SFRX(AX5043_FREQUENCYGAINC3, 0x4151); /* Frequency Estimator Bandwidth C */ 825 SFRX(AX5043_FREQUENCYGAIND0, 0x4128); /* Frequency Estimator Bandwidth D */ 826 SFRX(AX5043_FREQUENCYGAIND1, 0x4136); /* Frequency Estimator Bandwidth D */ 827 SFRX(AX5043_FREQUENCYGAIND2, 0x4144); /* Frequency Estimator Bandwidth D */ 828 SFRX(AX5043_FREQUENCYGAIND3, 0x4152); /* Frequency Estimator Bandwidth D */ 829 SFRX(AX5043_PHASEGAIN0, 0x4124); /* Phase Estimator Bandwidth */ 830 SFRX(AX5043_PHASEGAIN1, 0x4132); /* Phase Estimator Bandwidth */ 831 SFRX(AX5043_PHASEGAIN2, 0x4140); /* Phase Estimator Bandwidth */ 832 SFRX(AX5043_PHASEGAIN3, 0x414E); /* Phase Estimator Bandwidth */ 833 SFRX(AX5043_PKTADDR0, 0x4203); /* Packet Address 0 */ 834 SFRX(AX5043_PKTADDR1, 0x4202); /* Packet Address 1 */ 835 SFRX(AX5043_PKTADDRCFG, 0x4201); /* Packet Address Config */ 836 SFRX(AX5043_PKTADDRMASK0, 0x4205); /* Packet Address Mask 0 */ 837 SFRX(AX5043_PKTADDRMASK1, 0x4204); /* Packet Address Mask 1 */ 838 SFRX(AX5043_PKTLENCFG, 0x4206); /* Packet Length Configuration */ 839 SFRX(AX5043_PKTLENOFFSET, 0x4207); /* Packet Length Offset */ 840 SFRX(AX5043_PKTMAXLEN, 0x4208); /* Packet Maximum Length */ 841 SFRX(AX5043_RXPARAMCURSET, 0x4117); /* Receiver Parameter Current Set */ 842 SFRX(AX5043_RXPARAMSETS, 0x4116); /* Receiver Parameter Set Indirection */ 843 SFRX(AX5043_TIMEGAIN0, 0x4122); /* Time Estimator Bandwidth */ 844 SFRX(AX5043_TIMEGAIN1, 0x4130); /* Time Estimator Bandwidth */ 845 SFRX(AX5043_TIMEGAIN2, 0x413E); /* Time Estimator Bandwidth */ 846 SFRX(AX5043_TIMEGAIN3, 0x414C); /* Time Estimator Bandwidth */ 847 #else 848 SFRX(AX5043_AGCAHYST0, 0x4122); /* AGC Analog Hysteresis */ 849 SFRX(AX5043_AGCAHYST1, 0x4132); /* AGC Analog Hysteresis */ 850 SFRX(AX5043_AGCAHYST2, 0x4142); /* AGC Analog Hysteresis */ 851 SFRX(AX5043_AGCAHYST3, 0x4152); /* AGC Analog Hysteresis */ 852 SFRX(AX5043_AGCGAIN0, 0x4120); /* AGC Speed */ 853 SFRX(AX5043_AGCGAIN1, 0x4130); /* AGC Speed */ 854 SFRX(AX5043_AGCGAIN2, 0x4140); /* AGC Speed */ 855 SFRX(AX5043_AGCGAIN3, 0x4150); /* AGC Speed */ 856 SFRX(AX5043_AGCMINMAX0, 0x4123); /* AGC Analog Update Behaviour */ 857 SFRX(AX5043_AGCMINMAX1, 0x4133); /* AGC Analog Update Behaviour */ 858 SFRX(AX5043_AGCMINMAX2, 0x4143); /* AGC Analog Update Behaviour */ 859 SFRX(AX5043_AGCMINMAX3, 0x4153); /* AGC Analog Update Behaviour */ 860 SFRX(AX5043_AGCTARGET0, 0x4121); /* AGC Target */ 861 SFRX(AX5043_AGCTARGET1, 0x4131); /* AGC Target */ 862 SFRX(AX5043_AGCTARGET2, 0x4141); /* AGC Target */ 863 SFRX(AX5043_AGCTARGET3, 0x4151); /* AGC Target */ 864 SFRX(AX5043_AMPLITUDEGAIN0, 0x412B); /* Amplitude Estimator Bandwidth */ 865 SFRX(AX5043_AMPLITUDEGAIN1, 0x413B); /* Amplitude Estimator Bandwidth */ 866 SFRX(AX5043_AMPLITUDEGAIN2, 0x414B); /* Amplitude Estimator Bandwidth */ 867 SFRX(AX5043_AMPLITUDEGAIN3, 0x415B); /* Amplitude Estimator Bandwidth */ 868 SFRX(AX5043_BBOFFSRES0, 0x412F); /* Baseband Offset Compensation Resistors */ 869 SFRX(AX5043_BBOFFSRES1, 0x413F); /* Baseband Offset Compensation Resistors */ 870 SFRX(AX5043_BBOFFSRES2, 0x414F); /* Baseband Offset Compensation Resistors */ 871 SFRX(AX5043_BBOFFSRES3, 0x415F); /* Baseband Offset Compensation Resistors */ 872 SFRX(AX5043_DRGAIN0, 0x4125); /* Data Rate Estimator Bandwidth */ 873 SFRX(AX5043_DRGAIN1, 0x4135); /* Data Rate Estimator Bandwidth */ 874 SFRX(AX5043_DRGAIN2, 0x4145); /* Data Rate Estimator Bandwidth */ 875 SFRX(AX5043_DRGAIN3, 0x4155); /* Data Rate Estimator Bandwidth */ 876 SFRX(AX5043_FOURFSK0, 0x412E); /* Four FSK Control */ 877 SFRX(AX5043_FOURFSK1, 0x413E); /* Four FSK Control */ 878 SFRX(AX5043_FOURFSK2, 0x414E); /* Four FSK Control */ 879 SFRX(AX5043_FOURFSK3, 0x415E); /* Four FSK Control */ 880 SFRX(AX5043_FREQDEV00, 0x412D); /* Receiver Frequency Deviation 0 */ 881 SFRX(AX5043_FREQDEV01, 0x413D); /* Receiver Frequency Deviation 0 */ 882 SFRX(AX5043_FREQDEV02, 0x414D); /* Receiver Frequency Deviation 0 */ 883 SFRX(AX5043_FREQDEV03, 0x415D); /* Receiver Frequency Deviation 0 */ 884 SFRX(AX5043_FREQDEV10, 0x412C); /* Receiver Frequency Deviation 1 */ 885 SFRX(AX5043_FREQDEV11, 0x413C); /* Receiver Frequency Deviation 1 */ 886 SFRX(AX5043_FREQDEV12, 0x414C); /* Receiver Frequency Deviation 1 */ 887 SFRX(AX5043_FREQDEV13, 0x415C); /* Receiver Frequency Deviation 1 */ 888 SFRX(AX5043_FREQUENCYGAINA0, 0x4127); /* Frequency Estimator Bandwidth A */ 889 SFRX(AX5043_FREQUENCYGAINA1, 0x4137); /* Frequency Estimator Bandwidth A */ 890 SFRX(AX5043_FREQUENCYGAINA2, 0x4147); /* Frequency Estimator Bandwidth A */ 891 SFRX(AX5043_FREQUENCYGAINA3, 0x4157); /* Frequency Estimator Bandwidth A */ 892 SFRX(AX5043_FREQUENCYGAINB0, 0x4128); /* Frequency Estimator Bandwidth B */ 893 SFRX(AX5043_FREQUENCYGAINB1, 0x4138); /* Frequency Estimator Bandwidth B */ 894 SFRX(AX5043_FREQUENCYGAINB2, 0x4148); /* Frequency Estimator Bandwidth B */ 895 SFRX(AX5043_FREQUENCYGAINB3, 0x4158); /* Frequency Estimator Bandwidth B */ 896 SFRX(AX5043_FREQUENCYGAINC0, 0x4129); /* Frequency Estimator Bandwidth C */ 897 SFRX(AX5043_FREQUENCYGAINC1, 0x4139); /* Frequency Estimator Bandwidth C */ 898 SFRX(AX5043_FREQUENCYGAINC2, 0x4149); /* Frequency Estimator Bandwidth C */ 899 SFRX(AX5043_FREQUENCYGAINC3, 0x4159); /* Frequency Estimator Bandwidth C */ 900 SFRX(AX5043_FREQUENCYGAIND0, 0x412A); /* Frequency Estimator Bandwidth D */ 901 SFRX(AX5043_FREQUENCYGAIND1, 0x413A); /* Frequency Estimator Bandwidth D */ 902 SFRX(AX5043_FREQUENCYGAIND2, 0x414A); /* Frequency Estimator Bandwidth D */ 903 SFRX(AX5043_FREQUENCYGAIND3, 0x415A); /* Frequency Estimator Bandwidth D */ 904 SFRX(AX5043_FREQUENCYLEAK, 0x4116); /* Baseband Frequency Recovery Loop Leakiness */ 905 SFRX(AX5043_PHASEGAIN0, 0x4126); /* Phase Estimator Bandwidth */ 906 SFRX(AX5043_PHASEGAIN1, 0x4136); /* Phase Estimator Bandwidth */ 907 SFRX(AX5043_PHASEGAIN2, 0x4146); /* Phase Estimator Bandwidth */ 908 SFRX(AX5043_PHASEGAIN3, 0x4156); /* Phase Estimator Bandwidth */ 909 SFRX(AX5043_PKTADDR0, 0x4207); /* Packet Address 0 */ 910 SFRX(AX5043_PKTADDR1, 0x4206); /* Packet Address 1 */ 911 SFRX(AX5043_PKTADDR2, 0x4205); /* Packet Address 2 */ 912 SFRX(AX5043_PKTADDR3, 0x4204); /* Packet Address 3 */ 913 SFRX(AX5043_PKTADDRCFG, 0x4200); /* Packet Address Config */ 914 SFRX(AX5043_PKTADDRMASK0, 0x420B); /* Packet Address Mask 0 */ 915 SFRX(AX5043_PKTADDRMASK1, 0x420A); /* Packet Address Mask 1 */ 916 SFRX(AX5043_PKTADDRMASK2, 0x4209); /* Packet Address Mask 2 */ 917 SFRX(AX5043_PKTADDRMASK3, 0x4208); /* Packet Address Mask 3 */ 918 SFRX(AX5043_PKTLENCFG, 0x4201); /* Packet Length Configuration */ 919 SFRX(AX5043_PKTLENOFFSET, 0x4202); /* Packet Length Offset */ 920 SFRX(AX5043_PKTMAXLEN, 0x4203); /* Packet Maximum Length */ 921 SFRX(AX5043_RXPARAMCURSET, 0x4118); /* Receiver Parameter Current Set */ 922 SFRX(AX5043_RXPARAMSETS, 0x4117); /* Receiver Parameter Set Indirection */ 923 SFRX(AX5043_TIMEGAIN0, 0x4124); /* Time Estimator Bandwidth */ 924 SFRX(AX5043_TIMEGAIN1, 0x4134); /* Time Estimator Bandwidth */ 925 SFRX(AX5043_TIMEGAIN2, 0x4144); /* Time Estimator Bandwidth */ 926 SFRX(AX5043_TIMEGAIN3, 0x4154); /* Time Estimator Bandwidth */ 927 #endif 928 929 /* Radio Registers, X Address Space, Non-Blocking Version */ 930 931 SFRX(AX5043_AFSKCTRLNB, 0x5114); /* AFSK Control, Non-Blocking */ 932 SFRX(AX5043_AFSKMARK0NB, 0x5113); /* AFSK Mark (1) Frequency 0, Non-Blocking */ 933 SFRX(AX5043_AFSKMARK1NB, 0x5112); /* AFSK Mark (1) Frequency 1, Non-Blocking */ 934 SFRX(AX5043_AFSKSPACE0NB, 0x5111); /* AFSK Space (0) Frequency 0, Non-Blocking */ 935 SFRX(AX5043_AFSKSPACE1NB, 0x5110); /* AFSK Space (0) Frequency 1, Non-Blocking */ 936 SFRX(AX5043_AGCCOUNTERNB, 0x5043); /* AGC Counter, Non-Blocking */ 937 SFRX(AX5043_AMPLFILTERNB, 0x5115); /* Amplitude Filter, Non-Blocking */ 938 SFRX(AX5043_BBOFFSCAPNB, 0x5189); /* Baseband Offset Compensation Capacitors, Non-Blocking */ 939 SFRX(AX5043_BBTUNENB, 0x5188); /* Baseband Tuning, Non-Blocking */ 940 SFRX(AX5043_BGNDRSSINB, 0x5041); /* Background RSSI, Non-Blocking */ 941 SFRX(AX5043_BGNDRSSIGAINNB, 0x522E); /* Background RSSI Averaging Time Constant, Non-Blocking */ 942 SFRX(AX5043_BGNDRSSITHRNB, 0x522F); /* Background RSSI Relative Threshold, Non-Blocking */ 943 SFRX(AX5043_CRCINIT0NB, 0x5017); /* CRC Initial Value 0, Non-Blocking */ 944 SFRX(AX5043_CRCINIT1NB, 0x5016); /* CRC Initial Value 1, Non-Blocking */ 945 SFRX(AX5043_CRCINIT2NB, 0x5015); /* CRC Initial Value 2, Non-Blocking */ 946 SFRX(AX5043_CRCINIT3NB, 0x5014); /* CRC Initial Value 3, Non-Blocking */ 947 SFRX(AX5043_DACCONFIGNB, 0x5332); /* DAC Configuration, Non-Blocking */ 948 SFRX(AX5043_DACVALUE0NB, 0x5331); /* DAC Value 0, Non-Blocking */ 949 SFRX(AX5043_DACVALUE1NB, 0x5330); /* DAC Value 1, Non-Blocking */ 950 SFRX(AX5043_DECIMATIONNB, 0x5102); /* Decimation Factor , Non-Blocking */ 951 SFRX(AX5043_DIVERSITYNB, 0x5042); /* Antenna Diversity Configuration, Non-Blocking */ 952 SFRX(AX5043_DSPMODECFGNB, 0x5320); /* DSP Mode Setting, Non-Blocking */ 953 SFRX(AX5043_DSPMODESHREGNB, 0x506F); /* DSPmode SPI Shift Register Access, Non-Blocking */ 954 SFRX(AX5043_DSPMODESKIP0NB, 0x5322); /* DSP Mode Skip 0, Non-Blocking */ 955 SFRX(AX5043_DSPMODESKIP1NB, 0x5321); /* DSP Mode Skip 1, Non-Blocking */ 956 SFRX(AX5043_ENCODINGNB, 0x5011); /* Encoding, Non-Blocking */ 957 SFRX(AX5043_FECNB, 0x5018); /* Forward Error Correction, Non-Blocking */ 958 SFRX(AX5043_FECSTATUSNB, 0x501A); /* Forward Error Correction Status, Non-Blocking */ 959 SFRX(AX5043_FECSYNCNB, 0x5019); /* Forward Error Correction Sync Threshold, Non-Blocking */ 960 SFRX(AX5043_FIFOCOUNT0NB, 0x502B); /* Number of Words currently in FIFO 0, Non-Blocking */ 961 SFRX(AX5043_FIFOCOUNT1NB, 0x502A); /* Number of Words currently in FIFO 1, Non-Blocking */ 962 SFRX(AX5043_FIFODATANB, 0x5029); /* FIFO Data, Non-Blocking */ 963 SFRX(AX5043_FIFOFREE0NB, 0x502D); /* Number of Words that can be written to FIFO 0, Non-Blocking */ 964 SFRX(AX5043_FIFOFREE1NB, 0x502C); /* Number of Words that can be written to FIFO 1, Non-Blocking */ 965 SFRX(AX5043_FIFOSTATNB, 0x5028); /* FIFO Control, Non-Blocking */ 966 SFRX(AX5043_FIFOTHRESH0NB, 0x502F); /* FIFO Threshold 0, Non-Blocking */ 967 SFRX(AX5043_FIFOTHRESH1NB, 0x502E); /* FIFO Threshold 1, Non-Blocking */ 968 SFRX(AX5043_FRAMINGNB, 0x5012); /* Framing Mode, Non-Blocking */ 969 SFRX(AX5043_FREQA0NB, 0x5037); /* Frequency A 0, Non-Blocking */ 970 SFRX(AX5043_FREQA1NB, 0x5036); /* Frequency A 1, Non-Blocking */ 971 SFRX(AX5043_FREQA2NB, 0x5035); /* Frequency A 2, Non-Blocking */ 972 SFRX(AX5043_FREQA3NB, 0x5034); /* Frequency A 3, Non-Blocking */ 973 SFRX(AX5043_FREQB0NB, 0x503F); /* Frequency B 0, Non-Blocking */ 974 SFRX(AX5043_FREQB1NB, 0x503E); /* Frequency B 1, Non-Blocking */ 975 SFRX(AX5043_FREQB2NB, 0x503D); /* Frequency B 2, Non-Blocking */ 976 SFRX(AX5043_FREQB3NB, 0x503C); /* Frequency B 3, Non-Blocking */ 977 SFRX(AX5043_FSKDEV0NB, 0x5163); /* FSK Deviation 0, Non-Blocking */ 978 SFRX(AX5043_FSKDEV1NB, 0x5162); /* FSK Deviation 1, Non-Blocking */ 979 SFRX(AX5043_FSKDEV2NB, 0x5161); /* FSK Deviation 2, Non-Blocking */ 980 SFRX(AX5043_FSKDMAX0NB, 0x510D); /* Four FSK Rx Maximum Deviation 0, Non-Blocking */ 981 SFRX(AX5043_FSKDMAX1NB, 0x510C); /* Four FSK Rx Maximum Deviation 1, Non-Blocking */ 982 SFRX(AX5043_FSKDMIN0NB, 0x510F); /* Four FSK Rx Minimum Deviation 0, Non-Blocking */ 983 SFRX(AX5043_FSKDMIN1NB, 0x510E); /* Four FSK Rx Minimum Deviation 1, Non-Blocking */ 984 SFRX(AX5043_GPADC13VALUE0NB, 0x5309); /* GPADC13 Value 0, Non-Blocking */ 985 SFRX(AX5043_GPADC13VALUE1NB, 0x5308); /* GPADC13 Value 1, Non-Blocking */ 986 SFRX(AX5043_GPADC1VALUE0NB, 0x530B); /* GPADC1 Value 0, Non-Blocking */ 987 SFRX(AX5043_GPADC1VALUE1NB, 0x530A); /* GPADC1 Value 1, Non-Blocking */ 988 SFRX(AX5043_GPADC2VALUE0NB, 0x530D); /* GPADC2 Value 0, Non-Blocking */ 989 SFRX(AX5043_GPADC2VALUE1NB, 0x530C); /* GPADC2 Value 1, Non-Blocking */ 990 SFRX(AX5043_GPADC3VALUE0NB, 0x530F); /* GPADC3 Value 0, Non-Blocking */ 991 SFRX(AX5043_GPADC3VALUE1NB, 0x530E); /* GPADC3 Value 1, Non-Blocking */ 992 SFRX(AX5043_GPADCCTRLNB, 0x5300); /* General Purpose ADC Control, Non-Blocking */ 993 SFRX(AX5043_GPADCPERIODNB, 0x5301); /* GPADC Sampling Period, Non-Blocking */ 994 SFRX(AX5043_IFFREQ0NB, 0x5101); /* 2nd LO / IF Frequency 0, Non-Blocking */ 995 SFRX(AX5043_IFFREQ1NB, 0x5100); /* 2nd LO / IF Frequency 1, Non-Blocking */ 996 SFRX(AX5043_IRQINVERSION0NB, 0x500B); /* IRQ Inversion 0, Non-Blocking */ 997 SFRX(AX5043_IRQINVERSION1NB, 0x500A); /* IRQ Inversion 1, Non-Blocking */ 998 SFRX(AX5043_IRQMASK0NB, 0x5007); /* IRQ Mask 0, Non-Blocking */ 999 SFRX(AX5043_IRQMASK1NB, 0x5006); /* IRQ Mask 1, Non-Blocking */ 1000 SFRX(AX5043_IRQREQUEST0NB, 0x500D); /* IRQ Request 0, Non-Blocking */ 1001 SFRX(AX5043_IRQREQUEST1NB, 0x500C); /* IRQ Request 1, Non-Blocking */ 1002 SFRX(AX5043_LPOSCCONFIGNB, 0x5310); /* Low Power Oscillator Calibration Configuration, Non-Blocking */ 1003 SFRX(AX5043_LPOSCFREQ0NB, 0x5317); /* Low Power Oscillator Frequency Tuning Low Byte, Non-Blocking */ 1004 SFRX(AX5043_LPOSCFREQ1NB, 0x5316); /* Low Power Oscillator Frequency Tuning High Byte, Non-Blocking */ 1005 SFRX(AX5043_LPOSCKFILT0NB, 0x5313); /* Low Power Oscillator Calibration Filter Constant Low Byte, Non-Blocking */ 1006 SFRX(AX5043_LPOSCKFILT1NB, 0x5312); /* Low Power Oscillator Calibration Filter Constant High Byte, Non-Blocking */ 1007 SFRX(AX5043_LPOSCPER0NB, 0x5319); /* Low Power Oscillator Period Low Byte, Non-Blocking */ 1008 SFRX(AX5043_LPOSCPER1NB, 0x5318); /* Low Power Oscillator Period High Byte, Non-Blocking */ 1009 SFRX(AX5043_LPOSCREF0NB, 0x5315); /* Low Power Oscillator Reference Frequency Low Byte, Non-Blocking */ 1010 SFRX(AX5043_LPOSCREF1NB, 0x5314); /* Low Power Oscillator Reference Frequency High Byte, Non-Blocking */ 1011 SFRX(AX5043_LPOSCSTATUSNB, 0x5311); /* Low Power Oscillator Calibration Status, Non-Blocking */ 1012 SFRX(AX5043_MATCH0LENNB, 0x5214); /* Pattern Match Unit 0, Pattern Length, Non-Blocking */ 1013 SFRX(AX5043_MATCH0MAXNB, 0x5216); /* Pattern Match Unit 0, Maximum Match, Non-Blocking */ 1014 SFRX(AX5043_MATCH0MINNB, 0x5215); /* Pattern Match Unit 0, Minimum Match, Non-Blocking */ 1015 SFRX(AX5043_MATCH0PAT0NB, 0x5213); /* Pattern Match Unit 0, Pattern 0, Non-Blocking */ 1016 SFRX(AX5043_MATCH0PAT1NB, 0x5212); /* Pattern Match Unit 0, Pattern 1, Non-Blocking */ 1017 SFRX(AX5043_MATCH0PAT2NB, 0x5211); /* Pattern Match Unit 0, Pattern 2, Non-Blocking */ 1018 SFRX(AX5043_MATCH0PAT3NB, 0x5210); /* Pattern Match Unit 0, Pattern 3, Non-Blocking */ 1019 SFRX(AX5043_MATCH1LENNB, 0x521C); /* Pattern Match Unit 1, Pattern Length, Non-Blocking */ 1020 SFRX(AX5043_MATCH1MAXNB, 0x521E); /* Pattern Match Unit 1, Maximum Match, Non-Blocking */ 1021 SFRX(AX5043_MATCH1MINNB, 0x521D); /* Pattern Match Unit 1, Minimum Match, Non-Blocking */ 1022 SFRX(AX5043_MATCH1PAT0NB, 0x5219); /* Pattern Match Unit 1, Pattern 0, Non-Blocking */ 1023 SFRX(AX5043_MATCH1PAT1NB, 0x5218); /* Pattern Match Unit 1, Pattern 1, Non-Blocking */ 1024 SFRX(AX5043_MAXDROFFSET0NB, 0x5108); /* Maximum Receiver Datarate Offset 0, Non-Blocking */ 1025 SFRX(AX5043_MAXDROFFSET1NB, 0x5107); /* Maximum Receiver Datarate Offset 1, Non-Blocking */ 1026 SFRX(AX5043_MAXDROFFSET2NB, 0x5106); /* Maximum Receiver Datarate Offset 2, Non-Blocking */ 1027 SFRX(AX5043_MAXRFOFFSET0NB, 0x510B); /* Maximum Receiver RF Offset 0, Non-Blocking */ 1028 SFRX(AX5043_MAXRFOFFSET1NB, 0x510A); /* Maximum Receiver RF Offset 1, Non-Blocking */ 1029 SFRX(AX5043_MAXRFOFFSET2NB, 0x5109); /* Maximum Receiver RF Offset 2, Non-Blocking */ 1030 SFRX(AX5043_MODCFGANB, 0x5164); /* Modulator Configuration A, Non-Blocking */ 1031 SFRX(AX5043_MODCFGFNB, 0x5160); /* Modulator Configuration F, Non-Blocking */ 1032 SFRX(AX5043_MODULATIONNB, 0x5010); /* Modulation, Non-Blocking */ 1033 SFRX(AX5043_PINFUNCANTSELNB, 0x5025); /* Pin Function ANTSEL, Non-Blocking */ 1034 SFRX(AX5043_PINFUNCDATANB, 0x5023); /* Pin Function DATA, Non-Blocking */ 1035 SFRX(AX5043_PINFUNCDCLKNB, 0x5022); /* Pin Function DCLK, Non-Blocking */ 1036 SFRX(AX5043_PINFUNCIRQNB, 0x5024); /* Pin Function IRQ, Non-Blocking */ 1037 SFRX(AX5043_PINFUNCPWRAMPNB, 0x5026); /* Pin Function PWRAMP, Non-Blocking */ 1038 SFRX(AX5043_PINFUNCSYSCLKNB, 0x5021); /* Pin Function SYSCLK, Non-Blocking */ 1039 SFRX(AX5043_PINSTATENB, 0x5020); /* Pin State, Non-Blocking */ 1040 SFRX(AX5043_PKTACCEPTFLAGSNB, 0x5233); /* Packet Controller Accept Flags, Non-Blocking */ 1041 SFRX(AX5043_PKTCHUNKSIZENB, 0x5230); /* Packet Chunk Size, Non-Blocking */ 1042 SFRX(AX5043_PKTMISCFLAGSNB, 0x5231); /* Packet Controller Miscellaneous Flags, Non-Blocking */ 1043 SFRX(AX5043_PKTSTOREFLAGSNB, 0x5232); /* Packet Controller Store Flags, Non-Blocking */ 1044 SFRX(AX5043_PLLCPINB, 0x5031); /* PLL Charge Pump Current, Non-Blocking */ 1045 SFRX(AX5043_PLLCPIBOOSTNB, 0x5039); /* PLL Charge Pump Current (Boosted), Non-Blocking */ 1046 SFRX(AX5043_PLLLOCKDETNB, 0x5182); /* PLL Lock Detect Delay, Non-Blocking */ 1047 SFRX(AX5043_PLLLOOPNB, 0x5030); /* PLL Loop Filter Settings, Non-Blocking */ 1048 SFRX(AX5043_PLLLOOPBOOSTNB, 0x5038); /* PLL Loop Filter Settings (Boosted), Non-Blocking */ 1049 SFRX(AX5043_PLLRANGINGANB, 0x5033); /* PLL Autoranging A, Non-Blocking */ 1050 SFRX(AX5043_PLLRANGINGBNB, 0x503B); /* PLL Autoranging B, Non-Blocking */ 1051 SFRX(AX5043_PLLRNGCLKNB, 0x5183); /* PLL Autoranging Clock, Non-Blocking */ 1052 SFRX(AX5043_PLLVCODIVNB, 0x5032); /* PLL Divider Settings, Non-Blocking */ 1053 SFRX(AX5043_PLLVCOINB, 0x5180); /* PLL VCO Current, Non-Blocking */ 1054 SFRX(AX5043_PLLVCOIRNB, 0x5181); /* PLL VCO Current Readback, Non-Blocking */ 1055 SFRX(AX5043_POWIRQMASKNB, 0x5005); /* Power Management Interrupt Mask, Non-Blocking */ 1056 SFRX(AX5043_POWSTATNB, 0x5003); /* Power Management Status, Non-Blocking */ 1057 SFRX(AX5043_POWSTICKYSTATNB, 0x5004); /* Power Management Sticky Status, Non-Blocking */ 1058 SFRX(AX5043_PWRAMPNB, 0x5027); /* PWRAMP Control, Non-Blocking */ 1059 SFRX(AX5043_PWRMODENB, 0x5002); /* Power Mode, Non-Blocking */ 1060 SFRX(AX5043_RADIOEVENTMASK0NB, 0x5009); /* Radio Event Mask 0, Non-Blocking */ 1061 SFRX(AX5043_RADIOEVENTMASK1NB, 0x5008); /* Radio Event Mask 1, Non-Blocking */ 1062 SFRX(AX5043_RADIOEVENTREQ0NB, 0x500F); /* Radio Event Request 0, Non-Blocking */ 1063 SFRX(AX5043_RADIOEVENTREQ1NB, 0x500E); /* Radio Event Request 1, Non-Blocking */ 1064 SFRX(AX5043_RADIOSTATENB, 0x501C); /* Radio Controller State, Non-Blocking */ 1065 SFRX(AX5043_RSSINB, 0x5040); /* Received Signal Strength Indicator, Non-Blocking */ 1066 SFRX(AX5043_RSSIABSTHRNB, 0x522D); /* RSSI Absolute Threshold, Non-Blocking */ 1067 SFRX(AX5043_RSSIREFERENCENB, 0x522C); /* RSSI Offset, Non-Blocking */ 1068 SFRX(AX5043_RXDATARATE0NB, 0x5105); /* Receiver Datarate 0, Non-Blocking */ 1069 SFRX(AX5043_RXDATARATE1NB, 0x5104); /* Receiver Datarate 1, Non-Blocking */ 1070 SFRX(AX5043_RXDATARATE2NB, 0x5103); /* Receiver Datarate 2, Non-Blocking */ 1071 SFRX(AX5043_SCRATCHNB, 0x5001); /* Scratch, Non-Blocking */ 1072 SFRX(AX5043_SILICONREVISIONNB, 0x5000); /* Silicon Revision, Non-Blocking */ 1073 SFRX(AX5043_TIMER0NB, 0x505B); /* 1MHz Timer 0, Non-Blocking */ 1074 SFRX(AX5043_TIMER1NB, 0x505A); /* 1MHz Timer 1, Non-Blocking */ 1075 SFRX(AX5043_TIMER2NB, 0x5059); /* 1MHz Timer 2, Non-Blocking */ 1076 SFRX(AX5043_TMGRXAGCNB, 0x5227); /* Receiver AGC Settling Time, Non-Blocking */ 1077 SFRX(AX5043_TMGRXBOOSTNB, 0x5223); /* Receive PLL Boost Time, Non-Blocking */ 1078 SFRX(AX5043_TMGRXCOARSEAGCNB, 0x5226); /* Receive Coarse AGC Time, Non-Blocking */ 1079 SFRX(AX5043_TMGRXOFFSACQNB, 0x5225); /* Receive Baseband DC Offset Acquisition Time, Non-Blocking */ 1080 SFRX(AX5043_TMGRXPREAMBLE1NB, 0x5229); /* Receiver Preamble 1 Timeout, Non-Blocking */ 1081 SFRX(AX5043_TMGRXPREAMBLE2NB, 0x522A); /* Receiver Preamble 2 Timeout, Non-Blocking */ 1082 SFRX(AX5043_TMGRXPREAMBLE3NB, 0x522B); /* Receiver Preamble 3 Timeout, Non-Blocking */ 1083 SFRX(AX5043_TMGRXRSSINB, 0x5228); /* Receiver RSSI Settling Time, Non-Blocking */ 1084 SFRX(AX5043_TMGRXSETTLENB, 0x5224); /* Receive PLL (post Boost) Settling Time, Non-Blocking */ 1085 SFRX(AX5043_TMGTXBOOSTNB, 0x5220); /* Transmit PLL Boost Time, Non-Blocking */ 1086 SFRX(AX5043_TMGTXSETTLENB, 0x5221); /* Transmit PLL (post Boost) Settling Time, Non-Blocking */ 1087 SFRX(AX5043_TRKAFSKDEMOD0NB, 0x5055); /* AFSK Demodulator Tracking 0, Non-Blocking */ 1088 SFRX(AX5043_TRKAFSKDEMOD1NB, 0x5054); /* AFSK Demodulator Tracking 1, Non-Blocking */ 1089 SFRX(AX5043_TRKAMPLITUDE0NB, 0x5049); /* Amplitude Tracking 0, Non-Blocking */ 1090 SFRX(AX5043_TRKAMPLITUDE1NB, 0x5048); /* Amplitude Tracking 1, Non-Blocking */ 1091 SFRX(AX5043_TRKDATARATE0NB, 0x5047); /* Datarate Tracking 0, Non-Blocking */ 1092 SFRX(AX5043_TRKDATARATE1NB, 0x5046); /* Datarate Tracking 1, Non-Blocking */ 1093 SFRX(AX5043_TRKDATARATE2NB, 0x5045); /* Datarate Tracking 2, Non-Blocking */ 1094 SFRX(AX5043_TRKFREQ0NB, 0x5051); /* Frequency Tracking 0, Non-Blocking */ 1095 SFRX(AX5043_TRKFREQ1NB, 0x5050); /* Frequency Tracking 1, Non-Blocking */ 1096 SFRX(AX5043_TRKFSKDEMOD0NB, 0x5053); /* FSK Demodulator Tracking 0, Non-Blocking */ 1097 SFRX(AX5043_TRKFSKDEMOD1NB, 0x5052); /* FSK Demodulator Tracking 1, Non-Blocking */ 1098 SFRX(AX5043_TRKPHASE0NB, 0x504B); /* Phase Tracking 0, Non-Blocking */ 1099 SFRX(AX5043_TRKPHASE1NB, 0x504A); /* Phase Tracking 1, Non-Blocking */ 1100 SFRX(AX5043_TRKRFFREQ0NB, 0x504F); /* RF Frequency Tracking 0, Non-Blocking */ 1101 SFRX(AX5043_TRKRFFREQ1NB, 0x504E); /* RF Frequency Tracking 1, Non-Blocking */ 1102 SFRX(AX5043_TRKRFFREQ2NB, 0x504D); /* RF Frequency Tracking 2, Non-Blocking */ 1103 SFRX(AX5043_TXPWRCOEFFA0NB, 0x5169); /* Transmitter Predistortion Coefficient A 0, Non-Blocking */ 1104 SFRX(AX5043_TXPWRCOEFFA1NB, 0x5168); /* Transmitter Predistortion Coefficient A 1, Non-Blocking */ 1105 SFRX(AX5043_TXPWRCOEFFB0NB, 0x516B); /* Transmitter Predistortion Coefficient B 0, Non-Blocking */ 1106 SFRX(AX5043_TXPWRCOEFFB1NB, 0x516A); /* Transmitter Predistortion Coefficient B 1, Non-Blocking */ 1107 SFRX(AX5043_TXPWRCOEFFC0NB, 0x516D); /* Transmitter Predistortion Coefficient C 0, Non-Blocking */ 1108 SFRX(AX5043_TXPWRCOEFFC1NB, 0x516C); /* Transmitter Predistortion Coefficient C 1, Non-Blocking */ 1109 SFRX(AX5043_TXPWRCOEFFD0NB, 0x516F); /* Transmitter Predistortion Coefficient D 0, Non-Blocking */ 1110 SFRX(AX5043_TXPWRCOEFFD1NB, 0x516E); /* Transmitter Predistortion Coefficient D 1, Non-Blocking */ 1111 SFRX(AX5043_TXPWRCOEFFE0NB, 0x5171); /* Transmitter Predistortion Coefficient E 0, Non-Blocking */ 1112 SFRX(AX5043_TXPWRCOEFFE1NB, 0x5170); /* Transmitter Predistortion Coefficient E 1, Non-Blocking */ 1113 SFRX(AX5043_TXRATE0NB, 0x5167); /* Transmitter Bitrate 0, Non-Blocking */ 1114 SFRX(AX5043_TXRATE1NB, 0x5166); /* Transmitter Bitrate 1, Non-Blocking */ 1115 SFRX(AX5043_TXRATE2NB, 0x5165); /* Transmitter Bitrate 2, Non-Blocking */ 1116 SFRX(AX5043_WAKEUP0NB, 0x506B); /* Wakeup Time 0, Non-Blocking */ 1117 SFRX(AX5043_WAKEUP1NB, 0x506A); /* Wakeup Time 1, Non-Blocking */ 1118 SFRX(AX5043_WAKEUPFREQ0NB, 0x506D); /* Wakeup Frequency 0, Non-Blocking */ 1119 SFRX(AX5043_WAKEUPFREQ1NB, 0x506C); /* Wakeup Frequency 1, Non-Blocking */ 1120 SFRX(AX5043_WAKEUPTIMER0NB, 0x5069); /* Wakeup Timer 0, Non-Blocking */ 1121 SFRX(AX5043_WAKEUPTIMER1NB, 0x5068); /* Wakeup Timer 1, Non-Blocking */ 1122 SFRX(AX5043_WAKEUPXOEARLYNB, 0x506E); /* Wakeup Crystal Oscillator Early, Non-Blocking */ 1123 SFRX(AX5043_XTALCAPNB, 0x5184); /* Crystal Oscillator Load Capacitance, Non-Blocking */ 1124 SFRX(AX5043_XTALSTATUSNB, 0x501D); /* Crystal Oscillator Status, Non-Blocking */ 1125 1126 #if defined AX5043V1 1127 SFRX(AX5043_AGCGAIN0NB, 0x5120); /* AGC Speed, Non-Blocking */ 1128 SFRX(AX5043_AGCGAIN1NB, 0x512E); /* AGC Speed, Non-Blocking */ 1129 SFRX(AX5043_AGCGAIN2NB, 0x513C); /* AGC Speed, Non-Blocking */ 1130 SFRX(AX5043_AGCGAIN3NB, 0x514A); /* AGC Speed, Non-Blocking */ 1131 SFRX(AX5043_AGCTARGET0NB, 0x5121); /* AGC Target, Non-Blocking */ 1132 SFRX(AX5043_AGCTARGET1NB, 0x512F); /* AGC Target, Non-Blocking */ 1133 SFRX(AX5043_AGCTARGET2NB, 0x513D); /* AGC Target, Non-Blocking */ 1134 SFRX(AX5043_AGCTARGET3NB, 0x514B); /* AGC Target, Non-Blocking */ 1135 SFRX(AX5043_AMPLITUDEGAIN0NB, 0x5129); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1136 SFRX(AX5043_AMPLITUDEGAIN1NB, 0x5137); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1137 SFRX(AX5043_AMPLITUDEGAIN2NB, 0x5145); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1138 SFRX(AX5043_AMPLITUDEGAIN3NB, 0x5153); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1139 SFRX(AX5043_BBOFFSRES0NB, 0x512D); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1140 SFRX(AX5043_BBOFFSRES1NB, 0x513B); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1141 SFRX(AX5043_BBOFFSRES2NB, 0x5149); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1142 SFRX(AX5043_BBOFFSRES3NB, 0x5157); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1143 SFRX(AX5043_DRGAIN0NB, 0x5123); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1144 SFRX(AX5043_DRGAIN1NB, 0x5131); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1145 SFRX(AX5043_DRGAIN2NB, 0x513F); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1146 SFRX(AX5043_DRGAIN3NB, 0x514D); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1147 SFRX(AX5043_FOURFSK0NB, 0x512C); /* Four FSK Control, Non-Blocking */ 1148 SFRX(AX5043_FOURFSK1NB, 0x513A); /* Four FSK Control, Non-Blocking */ 1149 SFRX(AX5043_FOURFSK2NB, 0x5148); /* Four FSK Control, Non-Blocking */ 1150 SFRX(AX5043_FOURFSK3NB, 0x5156); /* Four FSK Control, Non-Blocking */ 1151 SFRX(AX5043_FREQDEV00NB, 0x512B); /* Receiver Frequency Deviation 0, Non-Blocking */ 1152 SFRX(AX5043_FREQDEV01NB, 0x5139); /* Receiver Frequency Deviation 0, Non-Blocking */ 1153 SFRX(AX5043_FREQDEV02NB, 0x5147); /* Receiver Frequency Deviation 0, Non-Blocking */ 1154 SFRX(AX5043_FREQDEV03NB, 0x5155); /* Receiver Frequency Deviation 0, Non-Blocking */ 1155 SFRX(AX5043_FREQDEV10NB, 0x512A); /* Receiver Frequency Deviation 1, Non-Blocking */ 1156 SFRX(AX5043_FREQDEV11NB, 0x5138); /* Receiver Frequency Deviation 1, Non-Blocking */ 1157 SFRX(AX5043_FREQDEV12NB, 0x5146); /* Receiver Frequency Deviation 1, Non-Blocking */ 1158 SFRX(AX5043_FREQDEV13NB, 0x5154); /* Receiver Frequency Deviation 1, Non-Blocking */ 1159 SFRX(AX5043_FREQUENCYGAINA0NB, 0x5125); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1160 SFRX(AX5043_FREQUENCYGAINA1NB, 0x5133); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1161 SFRX(AX5043_FREQUENCYGAINA2NB, 0x5141); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1162 SFRX(AX5043_FREQUENCYGAINA3NB, 0x514F); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1163 SFRX(AX5043_FREQUENCYGAINB0NB, 0x5126); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1164 SFRX(AX5043_FREQUENCYGAINB1NB, 0x5134); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1165 SFRX(AX5043_FREQUENCYGAINB2NB, 0x5142); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1166 SFRX(AX5043_FREQUENCYGAINB3NB, 0x5150); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1167 SFRX(AX5043_FREQUENCYGAINC0NB, 0x5127); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1168 SFRX(AX5043_FREQUENCYGAINC1NB, 0x5135); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1169 SFRX(AX5043_FREQUENCYGAINC2NB, 0x5143); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1170 SFRX(AX5043_FREQUENCYGAINC3NB, 0x5151); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1171 SFRX(AX5043_FREQUENCYGAIND0NB, 0x5128); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1172 SFRX(AX5043_FREQUENCYGAIND1NB, 0x5136); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1173 SFRX(AX5043_FREQUENCYGAIND2NB, 0x5144); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1174 SFRX(AX5043_FREQUENCYGAIND3NB, 0x5152); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1175 SFRX(AX5043_PHASEGAIN0NB, 0x5124); /* Phase Estimator Bandwidth, Non-Blocking */ 1176 SFRX(AX5043_PHASEGAIN1NB, 0x5132); /* Phase Estimator Bandwidth, Non-Blocking */ 1177 SFRX(AX5043_PHASEGAIN2NB, 0x5140); /* Phase Estimator Bandwidth, Non-Blocking */ 1178 SFRX(AX5043_PHASEGAIN3NB, 0x514E); /* Phase Estimator Bandwidth, Non-Blocking */ 1179 SFRX(AX5043_PKTADDR0NB, 0x5203); /* Packet Address 0, Non-Blocking */ 1180 SFRX(AX5043_PKTADDR1NB, 0x5202); /* Packet Address 1, Non-Blocking */ 1181 SFRX(AX5043_PKTADDRCFGNB, 0x5201); /* Packet Address Config, Non-Blocking */ 1182 SFRX(AX5043_PKTADDRMASK0NB, 0x5205); /* Packet Address Mask 0, Non-Blocking */ 1183 SFRX(AX5043_PKTADDRMASK1NB, 0x5204); /* Packet Address Mask 1, Non-Blocking */ 1184 SFRX(AX5043_PKTLENCFGNB, 0x5206); /* Packet Length Configuration, Non-Blocking */ 1185 SFRX(AX5043_PKTLENOFFSETNB, 0x5207); /* Packet Length Offset, Non-Blocking */ 1186 SFRX(AX5043_PKTMAXLENNB, 0x5208); /* Packet Maximum Length, Non-Blocking */ 1187 SFRX(AX5043_RXPARAMCURSETNB, 0x5117); /* Receiver Parameter Current Set, Non-Blocking */ 1188 SFRX(AX5043_RXPARAMSETSNB, 0x5116); /* Receiver Parameter Set Indirection, Non-Blocking */ 1189 SFRX(AX5043_TIMEGAIN0NB, 0x5122); /* Time Estimator Bandwidth, Non-Blocking */ 1190 SFRX(AX5043_TIMEGAIN1NB, 0x5130); /* Time Estimator Bandwidth, Non-Blocking */ 1191 SFRX(AX5043_TIMEGAIN2NB, 0x513E); /* Time Estimator Bandwidth, Non-Blocking */ 1192 SFRX(AX5043_TIMEGAIN3NB, 0x514C); /* Time Estimator Bandwidth, Non-Blocking */ 1193 #else 1194 SFRX(AX5043_AGCAHYST0NB, 0x5122); /* AGC Analog Hysteresis, Non-Blocking */ 1195 SFRX(AX5043_AGCAHYST1NB, 0x5132); /* AGC Analog Hysteresis, Non-Blocking */ 1196 SFRX(AX5043_AGCAHYST2NB, 0x5142); /* AGC Analog Hysteresis, Non-Blocking */ 1197 SFRX(AX5043_AGCAHYST3NB, 0x5152); /* AGC Analog Hysteresis, Non-Blocking */ 1198 SFRX(AX5043_AGCGAIN0NB, 0x5120); /* AGC Speed, Non-Blocking */ 1199 SFRX(AX5043_AGCGAIN1NB, 0x5130); /* AGC Speed, Non-Blocking */ 1200 SFRX(AX5043_AGCGAIN2NB, 0x5140); /* AGC Speed, Non-Blocking */ 1201 SFRX(AX5043_AGCGAIN3NB, 0x5150); /* AGC Speed, Non-Blocking */ 1202 SFRX(AX5043_AGCMINMAX0NB, 0x5123); /* AGC Analog Update Behaviour, Non-Blocking */ 1203 SFRX(AX5043_AGCMINMAX1NB, 0x5133); /* AGC Analog Update Behaviour, Non-Blocking */ 1204 SFRX(AX5043_AGCMINMAX2NB, 0x5143); /* AGC Analog Update Behaviour, Non-Blocking */ 1205 SFRX(AX5043_AGCMINMAX3NB, 0x5153); /* AGC Analog Update Behaviour, Non-Blocking */ 1206 SFRX(AX5043_AGCTARGET0NB, 0x5121); /* AGC Target, Non-Blocking */ 1207 SFRX(AX5043_AGCTARGET1NB, 0x5131); /* AGC Target, Non-Blocking */ 1208 SFRX(AX5043_AGCTARGET2NB, 0x5141); /* AGC Target, Non-Blocking */ 1209 SFRX(AX5043_AGCTARGET3NB, 0x5151); /* AGC Target, Non-Blocking */ 1210 SFRX(AX5043_AMPLITUDEGAIN0NB, 0x512B); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1211 SFRX(AX5043_AMPLITUDEGAIN1NB, 0x513B); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1212 SFRX(AX5043_AMPLITUDEGAIN2NB, 0x514B); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1213 SFRX(AX5043_AMPLITUDEGAIN3NB, 0x515B); /* Amplitude Estimator Bandwidth, Non-Blocking */ 1214 SFRX(AX5043_BBOFFSRES0NB, 0x512F); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1215 SFRX(AX5043_BBOFFSRES1NB, 0x513F); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1216 SFRX(AX5043_BBOFFSRES2NB, 0x514F); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1217 SFRX(AX5043_BBOFFSRES3NB, 0x515F); /* Baseband Offset Compensation Resistors, Non-Blocking */ 1218 SFRX(AX5043_DRGAIN0NB, 0x5125); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1219 SFRX(AX5043_DRGAIN1NB, 0x5135); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1220 SFRX(AX5043_DRGAIN2NB, 0x5145); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1221 SFRX(AX5043_DRGAIN3NB, 0x5155); /* Data Rate Estimator Bandwidth, Non-Blocking */ 1222 SFRX(AX5043_FOURFSK0NB, 0x512E); /* Four FSK Control, Non-Blocking */ 1223 SFRX(AX5043_FOURFSK1NB, 0x513E); /* Four FSK Control, Non-Blocking */ 1224 SFRX(AX5043_FOURFSK2NB, 0x514E); /* Four FSK Control, Non-Blocking */ 1225 SFRX(AX5043_FOURFSK3NB, 0x515E); /* Four FSK Control, Non-Blocking */ 1226 SFRX(AX5043_FREQDEV00NB, 0x512D); /* Receiver Frequency Deviation 0, Non-Blocking */ 1227 SFRX(AX5043_FREQDEV01NB, 0x513D); /* Receiver Frequency Deviation 0, Non-Blocking */ 1228 SFRX(AX5043_FREQDEV02NB, 0x514D); /* Receiver Frequency Deviation 0, Non-Blocking */ 1229 SFRX(AX5043_FREQDEV03NB, 0x515D); /* Receiver Frequency Deviation 0, Non-Blocking */ 1230 SFRX(AX5043_FREQDEV10NB, 0x512C); /* Receiver Frequency Deviation 1, Non-Blocking */ 1231 SFRX(AX5043_FREQDEV11NB, 0x513C); /* Receiver Frequency Deviation 1, Non-Blocking */ 1232 SFRX(AX5043_FREQDEV12NB, 0x514C); /* Receiver Frequency Deviation 1, Non-Blocking */ 1233 SFRX(AX5043_FREQDEV13NB, 0x515C); /* Receiver Frequency Deviation 1, Non-Blocking */ 1234 SFRX(AX5043_FREQUENCYGAINA0NB, 0x5127); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1235 SFRX(AX5043_FREQUENCYGAINA1NB, 0x5137); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1236 SFRX(AX5043_FREQUENCYGAINA2NB, 0x5147); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1237 SFRX(AX5043_FREQUENCYGAINA3NB, 0x5157); /* Frequency Estimator Bandwidth A, Non-Blocking */ 1238 SFRX(AX5043_FREQUENCYGAINB0NB, 0x5128); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1239 SFRX(AX5043_FREQUENCYGAINB1NB, 0x5138); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1240 SFRX(AX5043_FREQUENCYGAINB2NB, 0x5148); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1241 SFRX(AX5043_FREQUENCYGAINB3NB, 0x5158); /* Frequency Estimator Bandwidth B, Non-Blocking */ 1242 SFRX(AX5043_FREQUENCYGAINC0NB, 0x5129); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1243 SFRX(AX5043_FREQUENCYGAINC1NB, 0x5139); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1244 SFRX(AX5043_FREQUENCYGAINC2NB, 0x5149); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1245 SFRX(AX5043_FREQUENCYGAINC3NB, 0x5159); /* Frequency Estimator Bandwidth C, Non-Blocking */ 1246 SFRX(AX5043_FREQUENCYGAIND0NB, 0x512A); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1247 SFRX(AX5043_FREQUENCYGAIND1NB, 0x513A); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1248 SFRX(AX5043_FREQUENCYGAIND2NB, 0x514A); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1249 SFRX(AX5043_FREQUENCYGAIND3NB, 0x515A); /* Frequency Estimator Bandwidth D, Non-Blocking */ 1250 SFRX(AX5043_FREQUENCYLEAKNB, 0x5116); /* Baseband Frequency Recovery Loop Leakiness, Non-Blocking */ 1251 SFRX(AX5043_PHASEGAIN0NB, 0x5126); /* Phase Estimator Bandwidth, Non-Blocking */ 1252 SFRX(AX5043_PHASEGAIN1NB, 0x5136); /* Phase Estimator Bandwidth, Non-Blocking */ 1253 SFRX(AX5043_PHASEGAIN2NB, 0x5146); /* Phase Estimator Bandwidth, Non-Blocking */ 1254 SFRX(AX5043_PHASEGAIN3NB, 0x5156); /* Phase Estimator Bandwidth, Non-Blocking */ 1255 SFRX(AX5043_PKTADDR0NB, 0x5207); /* Packet Address 0, Non-Blocking */ 1256 SFRX(AX5043_PKTADDR1NB, 0x5206); /* Packet Address 1, Non-Blocking */ 1257 SFRX(AX5043_PKTADDR2NB, 0x5205); /* Packet Address 2, Non-Blocking */ 1258 SFRX(AX5043_PKTADDR3NB, 0x5204); /* Packet Address 3, Non-Blocking */ 1259 SFRX(AX5043_PKTADDRCFGNB, 0x5200); /* Packet Address Config, Non-Blocking */ 1260 SFRX(AX5043_PKTADDRMASK0NB, 0x520B); /* Packet Address Mask 0, Non-Blocking */ 1261 SFRX(AX5043_PKTADDRMASK1NB, 0x520A); /* Packet Address Mask 1, Non-Blocking */ 1262 SFRX(AX5043_PKTADDRMASK2NB, 0x5209); /* Packet Address Mask 2, Non-Blocking */ 1263 SFRX(AX5043_PKTADDRMASK3NB, 0x5208); /* Packet Address Mask 3, Non-Blocking */ 1264 SFRX(AX5043_PKTLENCFGNB, 0x5201); /* Packet Length Configuration, Non-Blocking */ 1265 SFRX(AX5043_PKTLENOFFSETNB, 0x5202); /* Packet Length Offset, Non-Blocking */ 1266 SFRX(AX5043_PKTMAXLENNB, 0x5203); /* Packet Maximum Length, Non-Blocking */ 1267 SFRX(AX5043_RXPARAMCURSETNB, 0x5118); /* Receiver Parameter Current Set, Non-Blocking */ 1268 SFRX(AX5043_RXPARAMSETSNB, 0x5117); /* Receiver Parameter Set Indirection, Non-Blocking */ 1269 SFRX(AX5043_TIMEGAIN0NB, 0x5124); /* Time Estimator Bandwidth, Non-Blocking */ 1270 SFRX(AX5043_TIMEGAIN1NB, 0x5134); /* Time Estimator Bandwidth, Non-Blocking */ 1271 SFRX(AX5043_TIMEGAIN2NB, 0x5144); /* Time Estimator Bandwidth, Non-Blocking */ 1272 SFRX(AX5043_TIMEGAIN3NB, 0x5154); /* Time Estimator Bandwidth, Non-Blocking */ 1273 #endif 1274 1275 /* Interrupt Numbers */ 1276 1277 #define INT_EXTERNAL0 0 1278 #define INT_WAKEUPTIMER 1 1279 #define INT_EXTERNAL1 2 1280 #define INT_GPIO 3 1281 #define INT_RADIO 4 1282 #define INT_CLOCKMGMT 5 1283 #define INT_POWERMGMT 6 1284 #define INT_TIMER0 7 1285 #define INT_TIMER1 8 1286 #define INT_TIMER2 9 1287 #define INT_SPI0 10 1288 #define INT_UART0 11 1289 #define INT_UART1 12 1290 #define INT_GPADC 13 1291 #define INT_DMA 14 1292 #define INT_OUTPUTCOMP0 15 1293 #define INT_OUTPUTCOMP1 16 1294 #define INT_INPUTCAPT0 17 1295 #define INT_INPUTCAPT1 18 1296 #define INT_RNG 19 1297 #define INT_AES 20 1298 #define INT_DEBUGLINK 21 1299 1300 /* DMA Sources */ 1301 1302 #define DMASOURCE_XRAMTOOTHER 0x00 1303 #define DMASOURCE_SPITX 0x01 1304 #define DMASOURCE_UART0TX 0x02 1305 #define DMASOURCE_UART1TX 0x03 1306 #define DMASOURCE_TIMER0 0x04 1307 #define DMASOURCE_TIMER1 0x05 1308 #define DMASOURCE_TIMER2 0x06 1309 #define DMASOURCE_RADIOTX 0x07 1310 #define DMASOURCE_OC0 0x08 1311 #define DMASOURCE_OC1 0x09 1312 #define DMASOURCE_OTHERTOXRAM 0x10 1313 #define DMASOURCE_SPIRX 0x11 1314 #define DMASOURCE_UART0RX 0x12 1315 #define DMASOURCE_UART1RX 0x13 1316 #define DMASOURCE_ADC 0x14 1317 #define DMASOURCE_RADIORX 0x17 1318 #define DMASOURCE_IC0 0x18 1319 #define DMASOURCE_IC1 0x19 1320 1321 #endif /* AX8052F143_H */ 1322