1 /* 2 * This definitions of the PIC18F96J65 MCU. 3 * 4 * This file is part of the GNU PIC library for SDCC, originally 5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016. 6 * 7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:40 UTC. 8 * 9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that 10 * this license covers the code to the compiler and other executables, 11 * but explicitly does not cover any code or objects generated by sdcc. 12 * 13 * For pic device libraries and header files which are derived from 14 * Microchip header (.inc) and linker script (.lkr) files Microchip 15 * requires that "The header files should state that they are only to be 16 * used with authentic Microchip devices" which makes them incompatible 17 * with the GPL. Pic device libraries and header files are located at 18 * non-free/lib and non-free/include directories respectively. 19 * Sdcc should be run with the --use-non-free command line option in 20 * order to include non-free header files and libraries. 21 * 22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc. 23 */ 24 25 #include <pic18f96j65.h> 26 27 //============================================================================== 28 29 __at(0x0E80) __sfr MAADR5; 30 31 __at(0x0E81) __sfr MAADR6; 32 33 __at(0x0E82) __sfr MAADR3; 34 35 __at(0x0E83) __sfr MAADR4; 36 37 __at(0x0E84) __sfr MAADR1; 38 39 __at(0x0E85) __sfr MAADR2; 40 41 __at(0x0E8A) __sfr MISTAT; 42 __at(0x0E8A) volatile __MISTATbits_t MISTATbits; 43 44 __at(0x0E97) __sfr EFLOCON; 45 __at(0x0E97) volatile __EFLOCONbits_t EFLOCONbits; 46 47 __at(0x0E98) __sfr EPAUS; 48 49 __at(0x0E98) __sfr EPAUSL; 50 51 __at(0x0E99) __sfr EPAUSH; 52 53 __at(0x0EA0) __sfr MACON1; 54 __at(0x0EA0) volatile __MACON1bits_t MACON1bits; 55 56 __at(0x0EA2) __sfr MACON3; 57 __at(0x0EA2) volatile __MACON3bits_t MACON3bits; 58 59 __at(0x0EA3) __sfr MACON4; 60 __at(0x0EA3) volatile __MACON4bits_t MACON4bits; 61 62 __at(0x0EA4) __sfr MABBIPG; 63 __at(0x0EA4) volatile __MABBIPGbits_t MABBIPGbits; 64 65 __at(0x0EA6) __sfr MAIPG; 66 67 __at(0x0EA6) __sfr MAIPGL; 68 69 __at(0x0EA7) __sfr MAIPGH; 70 71 __at(0x0EAA) __sfr MAMXFL; 72 73 __at(0x0EAA) __sfr MAMXFLL; 74 75 __at(0x0EAB) __sfr MAMXFLH; 76 77 __at(0x0EB2) __sfr MICMD; 78 __at(0x0EB2) volatile __MICMDbits_t MICMDbits; 79 80 __at(0x0EB4) __sfr MIREGADR; 81 82 __at(0x0EB6) __sfr MIWR; 83 84 __at(0x0EB6) __sfr MIWRL; 85 86 __at(0x0EB7) __sfr MIWRH; 87 88 __at(0x0EB8) __sfr MIRD; 89 90 __at(0x0EB8) __sfr MIRDL; 91 92 __at(0x0EB9) __sfr MIRDH; 93 94 __at(0x0EC0) __sfr EHT0; 95 96 __at(0x0EC1) __sfr EHT1; 97 98 __at(0x0EC2) __sfr EHT2; 99 100 __at(0x0EC3) __sfr EHT3; 101 102 __at(0x0EC4) __sfr EHT4; 103 104 __at(0x0EC5) __sfr EHT5; 105 106 __at(0x0EC6) __sfr EHT6; 107 108 __at(0x0EC7) __sfr EHT7; 109 110 __at(0x0EC8) __sfr EPMM0; 111 112 __at(0x0EC9) __sfr EPMM1; 113 114 __at(0x0ECA) __sfr EPMM2; 115 116 __at(0x0ECB) __sfr EPMM3; 117 118 __at(0x0ECC) __sfr EPMM4; 119 120 __at(0x0ECD) __sfr EPMM5; 121 122 __at(0x0ECE) __sfr EPMM6; 123 124 __at(0x0ECF) __sfr EPMM7; 125 126 __at(0x0ED0) __sfr EPMCS; 127 128 __at(0x0ED0) __sfr EPMCSL; 129 130 __at(0x0ED1) __sfr EPMCSH; 131 132 __at(0x0ED4) __sfr EPMO; 133 134 __at(0x0ED4) __sfr EPMOL; 135 136 __at(0x0ED5) __sfr EPMOH; 137 138 __at(0x0ED8) __sfr ERXFCON; 139 __at(0x0ED8) volatile __ERXFCONbits_t ERXFCONbits; 140 141 __at(0x0ED9) __sfr EPKTCNT; 142 143 __at(0x0EE2) __sfr EWRPT; 144 145 __at(0x0EE2) __sfr EWRPTL; 146 147 __at(0x0EE3) __sfr EWRPTH; 148 149 __at(0x0EE4) __sfr ETXST; 150 151 __at(0x0EE4) __sfr ETXSTL; 152 153 __at(0x0EE5) __sfr ETXSTH; 154 155 __at(0x0EE6) __sfr ETXND; 156 157 __at(0x0EE6) __sfr ETXNDL; 158 159 __at(0x0EE7) __sfr ETXNDH; 160 161 __at(0x0EE8) __sfr ERXST; 162 163 __at(0x0EE8) __sfr ERXSTL; 164 165 __at(0x0EE9) __sfr ERXSTH; 166 167 __at(0x0EEA) __sfr ERXND; 168 169 __at(0x0EEA) __sfr ERXNDL; 170 171 __at(0x0EEB) __sfr ERXNDH; 172 173 __at(0x0EEC) __sfr ERXRDPT; 174 175 __at(0x0EEC) __sfr ERXRDPTL; 176 177 __at(0x0EED) __sfr ERXRDPTH; 178 179 __at(0x0EEE) __sfr ERXWRPT; 180 181 __at(0x0EEE) __sfr ERXWRPTL; 182 183 __at(0x0EEF) __sfr ERXWRPTH; 184 185 __at(0x0EF0) __sfr EDMAST; 186 187 __at(0x0EF0) __sfr EDMASTL; 188 189 __at(0x0EF1) __sfr EDMASTH; 190 191 __at(0x0EF2) __sfr EDMAND; 192 193 __at(0x0EF2) __sfr EDMANDL; 194 195 __at(0x0EF3) __sfr EDMANDH; 196 197 __at(0x0EF4) __sfr EDMADST; 198 199 __at(0x0EF4) __sfr EDMADSTL; 200 201 __at(0x0EF5) __sfr EDMADSTH; 202 203 __at(0x0EF6) __sfr EDMACS; 204 205 __at(0x0EF6) __sfr EDMACSL; 206 207 __at(0x0EF7) __sfr EDMACSH; 208 209 __at(0x0EFB) __sfr EIE; 210 __at(0x0EFB) volatile __EIEbits_t EIEbits; 211 212 __at(0x0EFD) __sfr ESTAT; 213 __at(0x0EFD) volatile __ESTATbits_t ESTATbits; 214 215 __at(0x0EFE) __sfr ECON2; 216 __at(0x0EFE) volatile __ECON2bits_t ECON2bits; 217 218 __at(0x0F60) __sfr EIR; 219 __at(0x0F60) volatile __EIRbits_t EIRbits; 220 221 __at(0x0F61) __sfr EDATA; 222 __at(0x0F61) volatile __EDATAbits_t EDATAbits; 223 224 __at(0x0F62) __sfr SSP2CON2; 225 __at(0x0F62) volatile __SSP2CON2bits_t SSP2CON2bits; 226 227 __at(0x0F63) __sfr SSP2CON1; 228 __at(0x0F63) volatile __SSP2CON1bits_t SSP2CON1bits; 229 230 __at(0x0F64) __sfr SSP2STAT; 231 __at(0x0F64) volatile __SSP2STATbits_t SSP2STATbits; 232 233 __at(0x0F65) __sfr SSP2ADD; 234 235 __at(0x0F66) __sfr SSP2BUF; 236 237 __at(0x0F67) __sfr ECCP2DEL; 238 __at(0x0F67) volatile __ECCP2DELbits_t ECCP2DELbits; 239 240 __at(0x0F68) __sfr ECCP2AS; 241 __at(0x0F68) volatile __ECCP2ASbits_t ECCP2ASbits; 242 243 __at(0x0F69) __sfr ECCP3DEL; 244 __at(0x0F69) volatile __ECCP3DELbits_t ECCP3DELbits; 245 246 __at(0x0F6A) __sfr ECCP3AS; 247 __at(0x0F6A) volatile __ECCP3ASbits_t ECCP3ASbits; 248 249 __at(0x0F6B) __sfr RCSTA2; 250 __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits; 251 252 __at(0x0F6C) __sfr TXSTA2; 253 __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits; 254 255 __at(0x0F6D) __sfr TXREG2; 256 257 __at(0x0F6E) __sfr RCREG2; 258 259 __at(0x0F6F) __sfr SPBRG2; 260 261 __at(0x0F70) __sfr CCP5CON; 262 __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits; 263 264 __at(0x0F71) __sfr CCPR5; 265 266 __at(0x0F71) __sfr CCPR5L; 267 268 __at(0x0F72) __sfr CCPR5H; 269 270 __at(0x0F73) __sfr CCP4CON; 271 __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits; 272 273 __at(0x0F74) __sfr CCPR4; 274 275 __at(0x0F74) __sfr CCPR4L; 276 277 __at(0x0F75) __sfr CCPR4H; 278 279 __at(0x0F76) __sfr T4CON; 280 __at(0x0F76) volatile __T4CONbits_t T4CONbits; 281 282 __at(0x0F77) __sfr PR4; 283 284 __at(0x0F78) __sfr TMR4; 285 286 __at(0x0F79) __sfr ECCP1DEL; 287 __at(0x0F79) volatile __ECCP1DELbits_t ECCP1DELbits; 288 289 __at(0x0F7A) __sfr ERDPT; 290 291 __at(0x0F7A) __sfr ERDPTL; 292 293 __at(0x0F7B) __sfr ERDPTH; 294 295 __at(0x0F7C) __sfr BAUDCON2; 296 __at(0x0F7C) volatile __BAUDCON2bits_t BAUDCON2bits; 297 298 __at(0x0F7C) __sfr BAUDCTL2; 299 __at(0x0F7C) volatile __BAUDCTL2bits_t BAUDCTL2bits; 300 301 __at(0x0F7D) __sfr SPBRGH2; 302 303 __at(0x0F7E) __sfr BAUDCON; 304 __at(0x0F7E) volatile __BAUDCONbits_t BAUDCONbits; 305 306 __at(0x0F7E) __sfr BAUDCON1; 307 __at(0x0F7E) volatile __BAUDCON1bits_t BAUDCON1bits; 308 309 __at(0x0F7E) __sfr BAUDCTL; 310 __at(0x0F7E) volatile __BAUDCTLbits_t BAUDCTLbits; 311 312 __at(0x0F7E) __sfr BAUDCTL1; 313 __at(0x0F7E) volatile __BAUDCTL1bits_t BAUDCTL1bits; 314 315 __at(0x0F7F) __sfr SPBRGH; 316 317 __at(0x0F7F) __sfr SPBRGH1; 318 319 __at(0x0F80) __sfr PORTA; 320 __at(0x0F80) volatile __PORTAbits_t PORTAbits; 321 322 __at(0x0F81) __sfr PORTB; 323 __at(0x0F81) volatile __PORTBbits_t PORTBbits; 324 325 __at(0x0F82) __sfr PORTC; 326 __at(0x0F82) volatile __PORTCbits_t PORTCbits; 327 328 __at(0x0F83) __sfr PORTD; 329 __at(0x0F83) volatile __PORTDbits_t PORTDbits; 330 331 __at(0x0F84) __sfr PORTE; 332 __at(0x0F84) volatile __PORTEbits_t PORTEbits; 333 334 __at(0x0F85) __sfr PORTF; 335 __at(0x0F85) volatile __PORTFbits_t PORTFbits; 336 337 __at(0x0F86) __sfr PORTG; 338 __at(0x0F86) volatile __PORTGbits_t PORTGbits; 339 340 __at(0x0F87) __sfr PORTH; 341 __at(0x0F87) volatile __PORTHbits_t PORTHbits; 342 343 __at(0x0F88) __sfr PORTJ; 344 __at(0x0F88) volatile __PORTJbits_t PORTJbits; 345 346 __at(0x0F89) __sfr LATA; 347 __at(0x0F89) volatile __LATAbits_t LATAbits; 348 349 __at(0x0F8A) __sfr LATB; 350 __at(0x0F8A) volatile __LATBbits_t LATBbits; 351 352 __at(0x0F8B) __sfr LATC; 353 __at(0x0F8B) volatile __LATCbits_t LATCbits; 354 355 __at(0x0F8C) __sfr LATD; 356 __at(0x0F8C) volatile __LATDbits_t LATDbits; 357 358 __at(0x0F8D) __sfr LATE; 359 __at(0x0F8D) volatile __LATEbits_t LATEbits; 360 361 __at(0x0F8E) __sfr LATF; 362 __at(0x0F8E) volatile __LATFbits_t LATFbits; 363 364 __at(0x0F8F) __sfr LATG; 365 __at(0x0F8F) volatile __LATGbits_t LATGbits; 366 367 __at(0x0F90) __sfr LATH; 368 __at(0x0F90) volatile __LATHbits_t LATHbits; 369 370 __at(0x0F91) __sfr LATJ; 371 __at(0x0F91) volatile __LATJbits_t LATJbits; 372 373 __at(0x0F92) __sfr DDRA; 374 __at(0x0F92) volatile __DDRAbits_t DDRAbits; 375 376 __at(0x0F92) __sfr TRISA; 377 __at(0x0F92) volatile __TRISAbits_t TRISAbits; 378 379 __at(0x0F93) __sfr DDRB; 380 __at(0x0F93) volatile __DDRBbits_t DDRBbits; 381 382 __at(0x0F93) __sfr TRISB; 383 __at(0x0F93) volatile __TRISBbits_t TRISBbits; 384 385 __at(0x0F94) __sfr DDRC; 386 __at(0x0F94) volatile __DDRCbits_t DDRCbits; 387 388 __at(0x0F94) __sfr TRISC; 389 __at(0x0F94) volatile __TRISCbits_t TRISCbits; 390 391 __at(0x0F95) __sfr DDRD; 392 __at(0x0F95) volatile __DDRDbits_t DDRDbits; 393 394 __at(0x0F95) __sfr TRISD; 395 __at(0x0F95) volatile __TRISDbits_t TRISDbits; 396 397 __at(0x0F96) __sfr DDRE; 398 __at(0x0F96) volatile __DDREbits_t DDREbits; 399 400 __at(0x0F96) __sfr TRISE; 401 __at(0x0F96) volatile __TRISEbits_t TRISEbits; 402 403 __at(0x0F97) __sfr DDRF; 404 __at(0x0F97) volatile __DDRFbits_t DDRFbits; 405 406 __at(0x0F97) __sfr TRISF; 407 __at(0x0F97) volatile __TRISFbits_t TRISFbits; 408 409 __at(0x0F98) __sfr DDRG; 410 __at(0x0F98) volatile __DDRGbits_t DDRGbits; 411 412 __at(0x0F98) __sfr TRISG; 413 __at(0x0F98) volatile __TRISGbits_t TRISGbits; 414 415 __at(0x0F99) __sfr DDRH; 416 __at(0x0F99) volatile __DDRHbits_t DDRHbits; 417 418 __at(0x0F99) __sfr TRISH; 419 __at(0x0F99) volatile __TRISHbits_t TRISHbits; 420 421 __at(0x0F9A) __sfr DDRJ; 422 __at(0x0F9A) volatile __DDRJbits_t DDRJbits; 423 424 __at(0x0F9A) __sfr TRISJ; 425 __at(0x0F9A) volatile __TRISJbits_t TRISJbits; 426 427 __at(0x0F9B) __sfr OSCTUNE; 428 __at(0x0F9B) volatile __OSCTUNEbits_t OSCTUNEbits; 429 430 __at(0x0F9C) __sfr MEMCON; 431 __at(0x0F9C) volatile __MEMCONbits_t MEMCONbits; 432 433 __at(0x0F9D) __sfr PIE1; 434 __at(0x0F9D) volatile __PIE1bits_t PIE1bits; 435 436 __at(0x0F9E) __sfr PIR1; 437 __at(0x0F9E) volatile __PIR1bits_t PIR1bits; 438 439 __at(0x0F9F) __sfr IPR1; 440 __at(0x0F9F) volatile __IPR1bits_t IPR1bits; 441 442 __at(0x0FA0) __sfr PIE2; 443 __at(0x0FA0) volatile __PIE2bits_t PIE2bits; 444 445 __at(0x0FA1) __sfr PIR2; 446 __at(0x0FA1) volatile __PIR2bits_t PIR2bits; 447 448 __at(0x0FA2) __sfr IPR2; 449 __at(0x0FA2) volatile __IPR2bits_t IPR2bits; 450 451 __at(0x0FA3) __sfr PIE3; 452 __at(0x0FA3) volatile __PIE3bits_t PIE3bits; 453 454 __at(0x0FA4) __sfr PIR3; 455 __at(0x0FA4) volatile __PIR3bits_t PIR3bits; 456 457 __at(0x0FA5) __sfr IPR3; 458 __at(0x0FA5) volatile __IPR3bits_t IPR3bits; 459 460 __at(0x0FA6) __sfr EECON1; 461 __at(0x0FA6) volatile __EECON1bits_t EECON1bits; 462 463 __at(0x0FA7) __sfr EECON2; 464 465 __at(0x0FAB) __sfr RCSTA; 466 __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits; 467 468 __at(0x0FAB) __sfr RCSTA1; 469 __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits; 470 471 __at(0x0FAC) __sfr TXSTA; 472 __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits; 473 474 __at(0x0FAC) __sfr TXSTA1; 475 __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits; 476 477 __at(0x0FAD) __sfr TXREG; 478 479 __at(0x0FAD) __sfr TXREG1; 480 481 __at(0x0FAE) __sfr RCREG; 482 483 __at(0x0FAE) __sfr RCREG1; 484 485 __at(0x0FAF) __sfr SPBRG; 486 487 __at(0x0FAF) __sfr SPBRG1; 488 489 __at(0x0FB0) __sfr PSPCON; 490 __at(0x0FB0) volatile __PSPCONbits_t PSPCONbits; 491 492 __at(0x0FB1) __sfr T3CON; 493 __at(0x0FB1) volatile __T3CONbits_t T3CONbits; 494 495 __at(0x0FB2) __sfr TMR3; 496 497 __at(0x0FB2) __sfr TMR3L; 498 499 __at(0x0FB3) __sfr TMR3H; 500 501 __at(0x0FB4) __sfr CMCON; 502 __at(0x0FB4) volatile __CMCONbits_t CMCONbits; 503 504 __at(0x0FB5) __sfr CVRCON; 505 __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits; 506 507 __at(0x0FB6) __sfr ECCP1AS; 508 __at(0x0FB6) volatile __ECCP1ASbits_t ECCP1ASbits; 509 510 __at(0x0FB7) __sfr CCP3CON; 511 __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits; 512 513 __at(0x0FB7) __sfr ECCP3CON; 514 __at(0x0FB7) volatile __ECCP3CONbits_t ECCP3CONbits; 515 516 __at(0x0FB8) __sfr CCPR3; 517 518 __at(0x0FB8) __sfr CCPR3L; 519 520 __at(0x0FB9) __sfr CCPR3H; 521 522 __at(0x0FBA) __sfr CCP2CON; 523 __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits; 524 525 __at(0x0FBA) __sfr ECCP2CON; 526 __at(0x0FBA) volatile __ECCP2CONbits_t ECCP2CONbits; 527 528 __at(0x0FBB) __sfr CCPR2; 529 530 __at(0x0FBB) __sfr CCPR2L; 531 532 __at(0x0FBC) __sfr CCPR2H; 533 534 __at(0x0FBD) __sfr CCP1CON; 535 __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits; 536 537 __at(0x0FBD) __sfr ECCP1CON; 538 __at(0x0FBD) volatile __ECCP1CONbits_t ECCP1CONbits; 539 540 __at(0x0FBE) __sfr CCPR1; 541 542 __at(0x0FBE) __sfr CCPR1L; 543 544 __at(0x0FBF) __sfr CCPR1H; 545 546 __at(0x0FC0) __sfr ADCON2; 547 __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits; 548 549 __at(0x0FC1) __sfr ADCON1; 550 __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits; 551 552 __at(0x0FC2) __sfr ADCON0; 553 __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits; 554 555 __at(0x0FC3) __sfr ADRES; 556 557 __at(0x0FC3) __sfr ADRESL; 558 559 __at(0x0FC4) __sfr ADRESH; 560 561 __at(0x0FC5) __sfr SSP1CON2; 562 __at(0x0FC5) volatile __SSP1CON2bits_t SSP1CON2bits; 563 564 __at(0x0FC5) __sfr SSPCON2; 565 __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits; 566 567 __at(0x0FC6) __sfr SSP1CON1; 568 __at(0x0FC6) volatile __SSP1CON1bits_t SSP1CON1bits; 569 570 __at(0x0FC6) __sfr SSPCON1; 571 __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits; 572 573 __at(0x0FC7) __sfr SSP1STAT; 574 __at(0x0FC7) volatile __SSP1STATbits_t SSP1STATbits; 575 576 __at(0x0FC7) __sfr SSPSTAT; 577 __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits; 578 579 __at(0x0FC8) __sfr SSP1ADD; 580 581 __at(0x0FC8) __sfr SSPADD; 582 583 __at(0x0FC9) __sfr SSP1BUF; 584 585 __at(0x0FC9) __sfr SSPBUF; 586 587 __at(0x0FCA) __sfr T2CON; 588 __at(0x0FCA) volatile __T2CONbits_t T2CONbits; 589 590 __at(0x0FCB) __sfr PR2; 591 592 __at(0x0FCC) __sfr TMR2; 593 594 __at(0x0FCD) __sfr T1CON; 595 __at(0x0FCD) volatile __T1CONbits_t T1CONbits; 596 597 __at(0x0FCE) __sfr TMR1; 598 599 __at(0x0FCE) __sfr TMR1L; 600 601 __at(0x0FCF) __sfr TMR1H; 602 603 __at(0x0FD0) __sfr RCON; 604 __at(0x0FD0) volatile __RCONbits_t RCONbits; 605 606 __at(0x0FD1) __sfr WDTCON; 607 __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits; 608 609 __at(0x0FD2) __sfr ECON1; 610 __at(0x0FD2) volatile __ECON1bits_t ECON1bits; 611 612 __at(0x0FD3) __sfr OSCCON; 613 __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits; 614 615 __at(0x0FD5) __sfr T0CON; 616 __at(0x0FD5) volatile __T0CONbits_t T0CONbits; 617 618 __at(0x0FD6) __sfr TMR0; 619 620 __at(0x0FD6) __sfr TMR0L; 621 622 __at(0x0FD7) __sfr TMR0H; 623 624 __at(0x0FD8) __sfr STATUS; 625 __at(0x0FD8) volatile __STATUSbits_t STATUSbits; 626 627 __at(0x0FD9) __sfr FSR2L; 628 629 __at(0x0FDA) __sfr FSR2H; 630 631 __at(0x0FDB) __sfr PLUSW2; 632 633 __at(0x0FDC) __sfr PREINC2; 634 635 __at(0x0FDD) __sfr POSTDEC2; 636 637 __at(0x0FDE) __sfr POSTINC2; 638 639 __at(0x0FDF) __sfr INDF2; 640 641 __at(0x0FE0) __sfr BSR; 642 643 __at(0x0FE1) __sfr FSR1L; 644 645 __at(0x0FE2) __sfr FSR1H; 646 647 __at(0x0FE3) __sfr PLUSW1; 648 649 __at(0x0FE4) __sfr PREINC1; 650 651 __at(0x0FE5) __sfr POSTDEC1; 652 653 __at(0x0FE6) __sfr POSTINC1; 654 655 __at(0x0FE7) __sfr INDF1; 656 657 __at(0x0FE8) __sfr WREG; 658 659 __at(0x0FE9) __sfr FSR0L; 660 661 __at(0x0FEA) __sfr FSR0H; 662 663 __at(0x0FEB) __sfr PLUSW0; 664 665 __at(0x0FEC) __sfr PREINC0; 666 667 __at(0x0FED) __sfr POSTDEC0; 668 669 __at(0x0FEE) __sfr POSTINC0; 670 671 __at(0x0FEF) __sfr INDF0; 672 673 __at(0x0FF0) __sfr INTCON3; 674 __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits; 675 676 __at(0x0FF1) __sfr INTCON2; 677 __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits; 678 679 __at(0x0FF2) __sfr INTCON; 680 __at(0x0FF2) volatile __INTCONbits_t INTCONbits; 681 682 __at(0x0FF3) __sfr PROD; 683 684 __at(0x0FF3) __sfr PRODL; 685 686 __at(0x0FF4) __sfr PRODH; 687 688 __at(0x0FF5) __sfr TABLAT; 689 690 __at(0x0FF6) __sfr TBLPTR; 691 692 __at(0x0FF6) __sfr TBLPTRL; 693 694 __at(0x0FF7) __sfr TBLPTRH; 695 696 __at(0x0FF8) __sfr TBLPTRU; 697 698 __at(0x0FF9) __sfr PC; 699 700 __at(0x0FF9) __sfr PCL; 701 702 __at(0x0FFA) __sfr PCLATH; 703 704 __at(0x0FFB) __sfr PCLATU; 705 706 __at(0x0FFC) __sfr STKPTR; 707 __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits; 708 709 __at(0x0FFD) __sfr TOS; 710 711 __at(0x0FFD) __sfr TOSL; 712 713 __at(0x0FFE) __sfr TOSH; 714 715 __at(0x0FFF) __sfr TOSU; 716