1 /* 2 * Simulator of microcontrollers (glob.h) 3 * 4 * Copyright (C) 1999,99 Drotos Daniel, Talker Bt. 5 * 6 * To contact author send email to drdani@mazsola.iit.uni-miskolc.hu 7 * Other contributors include: 8 * Karl Bongers karl@turbobit.com, 9 * Johan Knol johan.knol@iduna.nl 10 * 11 */ 12 13 /* This file is part of microcontroller simulator: ucsim. 14 15 UCSIM is free software; you can redistribute it and/or modify 16 it under the terms of the GNU General Public License as published by 17 the Free Software Foundation; either version 2 of the License, or 18 (at your option) any later version. 19 20 UCSIM is distributed in the hope that it will be useful, 21 but WITHOUT ANY WARRANTY; without even the implied warranty of 22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 GNU General Public License for more details. 24 25 You should have received a copy of the GNU General Public License 26 along with UCSIM; see the file COPYING. If not, write to the Free 27 Software Foundation, 59 Temple Place - Suite 330, Boston, MA 28 02111-1307, USA. */ 29 /*@1@*/ 30 31 #ifndef GLOB_HEADER 32 #define GLOB_HEADER 33 34 #include "stypes.h" 35 36 /* this needs to match char *op_mnemonic_str[] definition in glob.cc */ 37 enum { 38 BAD_OPCODE=0, 39 ADD, 40 ADDC, 41 ADDS, 42 AND, 43 ANL, 44 ASL, 45 ASR, 46 BCC, 47 BCS, 48 BEQ, 49 BG, 50 BGE, 51 BGT, 52 BKPT, 53 BL, 54 BLE, 55 BLT, 56 BMI, 57 BNE, 58 BNV, 59 BOV, 60 BPL, 61 BR, 62 CALL, 63 CJNE, 64 CLR, 65 CMP, 66 CPL, 67 DA, 68 DIV_w, 69 DIV_d, 70 DIVU_b, 71 DIVU_w, 72 DIVU_d, 73 DJNZ, 74 FCALL, 75 FJMP, 76 JB, 77 JBC, 78 JMP, 79 JNB, 80 JNZ, 81 JZ, 82 LEA, 83 LSR, 84 MOV, 85 MOVC, 86 MOVS, 87 MOVX, 88 MUL_w, 89 MULU_b, 90 MULU_w, 91 NEG, 92 NOP, 93 NORM, 94 OR, 95 ORL, 96 POP, 97 POPU, 98 PUSH, 99 PUSHU, 100 RESET, 101 RET, 102 RETI, 103 RL, 104 RLC, 105 RR, 106 RRC, 107 SETB, 108 SEXT, 109 SUB, 110 SUBB, 111 TRAP, 112 XCH, 113 XOR, 114 }; 115 116 extern const char *op_mnemonic_str[]; 117 118 /* this classifies the operands and is used in the dissassembly 119 to print the operands. Its also used in the simulation to characterize 120 the op-code function. 121 */ 122 enum op_operands { 123 // the repeating parameter encoding for ADD, ADDC, SUB, SUBB, AND, XOR, ... 124 REG_REG , 125 REG_IREG , 126 IREG_REG , 127 REG_IREGOFF8 , 128 IREGOFF8_REG , 129 REG_IREGOFF16 , 130 IREGOFF16_REG , 131 REG_IREGINC , 132 IREGINC_REG , 133 DIRECT_REG , 134 REG_DIRECT , 135 REG_DATA8 , 136 REG_DATA16 , 137 IREG_DATA8 , 138 IREG_DATA16 , 139 IREGINC_DATA8 , 140 IREGINC_DATA16 , 141 IREGOFF8_DATA8 , 142 IREGOFF8_DATA16 , 143 IREGOFF16_DATA8 , 144 IREGOFF16_DATA16, 145 DIRECT_DATA8 , 146 DIRECT_DATA16 , 147 148 // odd-ball ones 149 NO_OPERANDS, // for NOP 150 CY_BIT, 151 BIT_CY, 152 CY_NOTBIT, 153 DATA4, 154 REG_DATA4, 155 REG_DATA5, 156 IREG_DATA4, 157 IREGINC_DATA4, 158 IREGOFF8_DATA4, 159 IREGOFF16_DATA4, 160 DIRECT_DATA4, 161 162 REG, 163 IREG, 164 BIT_ALONE, 165 DIRECT, 166 DIRECT_DIRECT, 167 RLIST, 168 ADDR24, 169 BIT_REL8, 170 REG_REL8, 171 DIRECT_REL8, 172 REG_REGOFF8, 173 REG_REGOFF16, 174 175 REG_USP, 176 USP_REG, 177 178 REL8, 179 REL16, 180 181 REG_DIRECT_REL8, 182 REG_DATA8_REL8, 183 REG_DATA16_REL8, 184 IREG_DATA8_REL8, 185 IREG_DATA16_REL8, 186 187 A_APLUSDPTR, 188 A_APLUSPC, 189 A_PLUSDPTR, 190 IIREG 191 }; 192 193 // table of dissassembled instructions 194 struct xa_dis_entry 195 { 196 uint is1byte; /* only grab 1 byte for table lookup(most are 2 bytes) */ 197 uint code; /* bits in opcode used to match table entry(with mask) */ 198 uint mask; /* mask used on .code to match up a common opcode */ 199 char branch; /* used by main app to implement "next" around calls */ 200 uchar length; /* total length of opcode, used by dissasembler and main app */ 201 int mnemonic; /* type of opcode(ADD, ADDC...) */ 202 int operands; /* unique classification of operands: Rd,Rs = REG_REG,... */ 203 }; 204 205 extern struct dis_entry glob_disass_xa[]; 206 207 extern struct xa_dis_entry disass_xa[]; 208 209 210 #endif 211 212 /* End of xa.src/glob.h */ 213