1 /* ppc.h -- Header file for PowerPC opcode table 2 Copyright 1994, 1995 Free Software Foundation, Inc. 3 Written by Ian Lance Taylor, Cygnus Support 4 5 This file is part of GDB, GAS, and the GNU binutils. 6 7 GDB, GAS, and the GNU binutils are free software; you can redistribute 8 them and/or modify them under the terms of the GNU General Public 9 License as published by the Free Software Foundation; either version 10 1, or (at your option) any later version. 11 12 GDB, GAS, and the GNU binutils are distributed in the hope that they 13 will be useful, but WITHOUT ANY WARRANTY; without even the implied 14 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See 15 the GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this file; see the file COPYING. If not, write to the Free 19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ 20 21 #ifndef PPC_H 22 #define PPC_H 23 24 /* The opcode table is an array of struct powerpc_opcode. */ 25 26 struct powerpc_opcode 27 { 28 /* The opcode name. */ 29 const char *name; 30 31 /* The opcode itself. Those bits which will be filled in with 32 operands are zeroes. */ 33 unsigned long opcode; 34 35 /* The opcode mask. This is used by the disassembler. This is a 36 mask containing ones indicating those bits which must match the 37 opcode field, and zeroes indicating those bits which need not 38 match (and are presumably filled in by operands). */ 39 unsigned long mask; 40 41 /* One bit flags for the opcode. These are used to indicate which 42 specific processors support the instructions. The defined values 43 are listed below. */ 44 unsigned long flags; 45 46 /* An array of operand codes. Each code is an index into the 47 operand table. They appear in the order which the operands must 48 appear in assembly code, and are terminated by a zero. */ 49 unsigned char operands[8]; 50 }; 51 52 /* The table itself is sorted by major opcode number, and is otherwise 53 in the order in which the disassembler should consider 54 instructions. */ 55 extern const struct powerpc_opcode powerpc_opcodes[]; 56 extern const int powerpc_num_opcodes; 57 58 /* Values defined for the flags field of a struct powerpc_opcode. */ 59 60 /* Opcode is defined for the PowerPC architecture. */ 61 #define PPC_OPCODE_PPC (01) 62 63 /* Opcode is defined for the POWER (RS/6000) architecture. */ 64 #define PPC_OPCODE_POWER (02) 65 66 /* Opcode is defined for the POWER2 (Rios 2) architecture. */ 67 #define PPC_OPCODE_POWER2 (04) 68 69 /* Opcode is only defined on 32 bit architectures. */ 70 #define PPC_OPCODE_32 (010) 71 72 /* Opcode is only defined on 64 bit architectures. */ 73 #define PPC_OPCODE_64 (020) 74 75 /* Opcode is supported by the Motorola PowerPC 601 processor. The 601 76 is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions, 77 but it also supports many additional POWER instructions. */ 78 #define PPC_OPCODE_601 (040) 79 80 /* Opcode is supported in both the Power and PowerPC architectures 81 (ie, compiler's -mcpu=common or assembler's -mcom). */ 82 #define PPC_OPCODE_COMMON (0100) 83 84 /* Opcode is supported for any Power or PowerPC platform (this is 85 for the assembler's -many option, and it eliminates duplicates). */ 86 #define PPC_OPCODE_ANY (0200) 87 88 /* A macro to extract the major opcode from an instruction. */ 89 #define PPC_OP(i) (((i) >> 26) & 0x3f) 90 91 /* The operands table is an array of struct powerpc_operand. */ 92 93 struct powerpc_operand 94 { 95 /* The number of bits in the operand. */ 96 int bits; 97 98 /* How far the operand is left shifted in the instruction. */ 99 int shift; 100 101 /* Insertion function. This is used by the assembler. To insert an 102 operand value into an instruction, check this field. 103 104 If it is NULL, execute 105 i |= (op & ((1 << o->bits) - 1)) << o->shift; 106 (i is the instruction which we are filling in, o is a pointer to 107 this structure, and op is the opcode value; this assumes twos 108 complement arithmetic). 109 110 If this field is not NULL, then simply call it with the 111 instruction and the operand value. It will return the new value 112 of the instruction. If the ERRMSG argument is not NULL, then if 113 the operand value is illegal, *ERRMSG will be set to a warning 114 string (the operand will be inserted in any case). If the 115 operand value is legal, *ERRMSG will be unchanged (most operands 116 can accept any value). */ 117 unsigned long (*insert) PARAMS ((unsigned long instruction, long op, 118 const char **errmsg)); 119 120 /* Extraction function. This is used by the disassembler. To 121 extract this operand type from an instruction, check this field. 122 123 If it is NULL, compute 124 op = ((i) >> o->shift) & ((1 << o->bits) - 1); 125 if ((o->flags & PPC_OPERAND_SIGNED) != 0 126 && (op & (1 << (o->bits - 1))) != 0) 127 op -= 1 << o->bits; 128 (i is the instruction, o is a pointer to this structure, and op 129 is the result; this assumes twos complement arithmetic). 130 131 If this field is not NULL, then simply call it with the 132 instruction value. It will return the value of the operand. If 133 the INVALID argument is not NULL, *INVALID will be set to 134 non-zero if this operand type can not actually be extracted from 135 this operand (i.e., the instruction does not match). If the 136 operand is valid, *INVALID will not be changed. */ 137 long (*extract) PARAMS ((unsigned long instruction, int *invalid)); 138 139 /* One bit syntax flags. */ 140 unsigned long flags; 141 }; 142 143 /* Elements in the table are retrieved by indexing with values from 144 the operands field of the powerpc_opcodes table. */ 145 146 extern const struct powerpc_operand powerpc_operands[]; 147 148 /* Values defined for the flags field of a struct powerpc_operand. */ 149 150 /* This operand takes signed values. */ 151 #define PPC_OPERAND_SIGNED (01) 152 153 /* This operand takes signed values, but also accepts a full positive 154 range of values when running in 32 bit mode. That is, if bits is 155 16, it takes any value from -0x8000 to 0xffff. In 64 bit mode, 156 this flag is ignored. */ 157 #define PPC_OPERAND_SIGNOPT (02) 158 159 /* This operand does not actually exist in the assembler input. This 160 is used to support extended mnemonics such as mr, for which two 161 operands fields are identical. The assembler should call the 162 insert function with any op value. The disassembler should call 163 the extract function, ignore the return value, and check the value 164 placed in the valid argument. */ 165 #define PPC_OPERAND_FAKE (04) 166 167 /* The next operand should be wrapped in parentheses rather than 168 separated from this one by a comma. This is used for the load and 169 store instructions which want their operands to look like 170 reg,displacement(reg) 171 */ 172 #define PPC_OPERAND_PARENS (010) 173 174 /* This operand may use the symbolic names for the CR fields, which 175 are 176 lt 0 gt 1 eq 2 so 3 un 3 177 cr0 0 cr1 1 cr2 2 cr3 3 178 cr4 4 cr5 5 cr6 6 cr7 7 179 These may be combined arithmetically, as in cr2*4+gt. These are 180 only supported on the PowerPC, not the POWER. */ 181 #define PPC_OPERAND_CR (020) 182 183 /* This operand names a register. The disassembler uses this to print 184 register names with a leading 'r'. */ 185 #define PPC_OPERAND_GPR (040) 186 187 /* This operand names a floating point register. The disassembler 188 prints these with a leading 'f'. */ 189 #define PPC_OPERAND_FPR (0100) 190 191 /* This operand is a relative branch displacement. The disassembler 192 prints these symbolically if possible. */ 193 #define PPC_OPERAND_RELATIVE (0200) 194 195 /* This operand is an absolute branch address. The disassembler 196 prints these symbolically if possible. */ 197 #define PPC_OPERAND_ABSOLUTE (0400) 198 199 /* This operand is optional, and is zero if omitted. This is used for 200 the optional BF and L fields in the comparison instructions. The 201 assembler must count the number of operands remaining on the line, 202 and the number of operands remaining for the opcode, and decide 203 whether this operand is present or not. The disassembler should 204 print this operand out only if it is not zero. */ 205 #define PPC_OPERAND_OPTIONAL (01000) 206 207 /* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand 208 is omitted, then for the next operand use this operand value plus 209 1, ignoring the next operand field for the opcode. This wretched 210 hack is needed because the Power rotate instructions can take 211 either 4 or 5 operands. The disassembler should print this operand 212 out regardless of the PPC_OPERAND_OPTIONAL field. */ 213 #define PPC_OPERAND_NEXT (02000) 214 215 /* This operand should be regarded as a negative number for the 216 purposes of overflow checking (i.e., the normal most negative 217 number is disallowed and one more than the normal most positive 218 number is allowed). This flag will only be set for a signed 219 operand. */ 220 #define PPC_OPERAND_NEGATIVE (04000) 221 222 /* The POWER and PowerPC assemblers use a few macros. We keep them 223 with the operands table for simplicity. The macro table is an 224 array of struct powerpc_macro. */ 225 226 struct powerpc_macro 227 { 228 /* The macro name. */ 229 const char *name; 230 231 /* The number of operands the macro takes. */ 232 unsigned int operands; 233 234 /* One bit flags for the opcode. These are used to indicate which 235 specific processors support the instructions. The values are the 236 same as those for the struct powerpc_opcode flags field. */ 237 unsigned long flags; 238 239 /* A format string to turn the macro into a normal instruction. 240 Each %N in the string is replaced with operand number N (zero 241 based). */ 242 const char *format; 243 }; 244 245 extern const struct powerpc_macro powerpc_macros[]; 246 extern const int powerpc_num_macros; 247 248 #endif /* PPC_H */ 249