1 // Copyright 2012 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef V8_CODEGEN_IA32_SSE_INSTR_H_ 6 #define V8_CODEGEN_IA32_SSE_INSTR_H_ 7 8 // SSE/SSE2 instructions whose AVX version has two operands. 9 #define SSE_UNOP_INSTRUCTION_LIST(V) \ 10 V(sqrtps, 0F, 51) \ 11 V(rsqrtps, 0F, 52) \ 12 V(rcpps, 0F, 53) \ 13 V(cvtps2pd, 0F, 5A) \ 14 V(cvtdq2ps, 0F, 5B) 15 16 #define SSE2_INSTRUCTION_LIST(V) \ 17 V(packsswb, 66, 0F, 63) \ 18 V(packssdw, 66, 0F, 6B) \ 19 V(packuswb, 66, 0F, 67) \ 20 V(pmaddwd, 66, 0F, F5) \ 21 V(paddb, 66, 0F, FC) \ 22 V(paddw, 66, 0F, FD) \ 23 V(paddd, 66, 0F, FE) \ 24 V(paddq, 66, 0F, D4) \ 25 V(paddsb, 66, 0F, EC) \ 26 V(paddsw, 66, 0F, ED) \ 27 V(paddusb, 66, 0F, DC) \ 28 V(paddusw, 66, 0F, DD) \ 29 V(pand, 66, 0F, DB) \ 30 V(pandn, 66, 0F, DF) \ 31 V(pcmpeqb, 66, 0F, 74) \ 32 V(pcmpeqw, 66, 0F, 75) \ 33 V(pcmpeqd, 66, 0F, 76) \ 34 V(pcmpgtb, 66, 0F, 64) \ 35 V(pcmpgtw, 66, 0F, 65) \ 36 V(pcmpgtd, 66, 0F, 66) \ 37 V(pmaxsw, 66, 0F, EE) \ 38 V(pmaxub, 66, 0F, DE) \ 39 V(pminsw, 66, 0F, EA) \ 40 V(pminub, 66, 0F, DA) \ 41 V(pmullw, 66, 0F, D5) \ 42 V(por, 66, 0F, EB) \ 43 V(psllw, 66, 0F, F1) \ 44 V(pslld, 66, 0F, F2) \ 45 V(psllq, 66, 0F, F3) \ 46 V(pmuludq, 66, 0F, F4) \ 47 V(pavgb, 66, 0F, E0) \ 48 V(psraw, 66, 0F, E1) \ 49 V(psrad, 66, 0F, E2) \ 50 V(pavgw, 66, 0F, E3) \ 51 V(pmulhuw, 66, 0F, E4) \ 52 V(pmulhw, 66, 0F, E5) \ 53 V(psrlw, 66, 0F, D1) \ 54 V(psrld, 66, 0F, D2) \ 55 V(psrlq, 66, 0F, D3) \ 56 V(psubb, 66, 0F, F8) \ 57 V(psubw, 66, 0F, F9) \ 58 V(psubd, 66, 0F, FA) \ 59 V(psubq, 66, 0F, FB) \ 60 V(psubsb, 66, 0F, E8) \ 61 V(psubsw, 66, 0F, E9) \ 62 V(psubusb, 66, 0F, D8) \ 63 V(psubusw, 66, 0F, D9) \ 64 V(punpcklbw, 66, 0F, 60) \ 65 V(punpcklwd, 66, 0F, 61) \ 66 V(punpckldq, 66, 0F, 62) \ 67 V(punpcklqdq, 66, 0F, 6C) \ 68 V(punpckhbw, 66, 0F, 68) \ 69 V(punpckhwd, 66, 0F, 69) \ 70 V(punpckhdq, 66, 0F, 6A) \ 71 V(punpckhqdq, 66, 0F, 6D) \ 72 V(pxor, 66, 0F, EF) 73 74 // Instructions dealing with scalar double-precision values. 75 #define SSE2_INSTRUCTION_LIST_SD(V) \ 76 V(sqrtsd, F2, 0F, 51) \ 77 V(addsd, F2, 0F, 58) \ 78 V(mulsd, F2, 0F, 59) \ 79 V(cvtsd2ss, F2, 0F, 5A) \ 80 V(subsd, F2, 0F, 5C) \ 81 V(minsd, F2, 0F, 5D) \ 82 V(divsd, F2, 0F, 5E) \ 83 V(maxsd, F2, 0F, 5F) 84 85 #define SSSE3_INSTRUCTION_LIST(V) \ 86 V(pshufb, 66, 0F, 38, 00) \ 87 V(phaddw, 66, 0F, 38, 01) \ 88 V(phaddd, 66, 0F, 38, 02) \ 89 V(pmaddubsw, 66, 0F, 38, 04) \ 90 V(psignb, 66, 0F, 38, 08) \ 91 V(psignw, 66, 0F, 38, 09) \ 92 V(psignd, 66, 0F, 38, 0A) \ 93 V(pmulhrsw, 66, 0F, 38, 0B) 94 95 // SSSE3 instructions whose AVX version has two operands. 96 #define SSSE3_UNOP_INSTRUCTION_LIST(V) \ 97 V(pabsb, 66, 0F, 38, 1C) \ 98 V(pabsw, 66, 0F, 38, 1D) \ 99 V(pabsd, 66, 0F, 38, 1E) 100 101 #define SSE4_INSTRUCTION_LIST(V) \ 102 V(pmuldq, 66, 0F, 38, 28) \ 103 V(pcmpeqq, 66, 0F, 38, 29) \ 104 V(packusdw, 66, 0F, 38, 2B) \ 105 V(pminsb, 66, 0F, 38, 38) \ 106 V(pminsd, 66, 0F, 38, 39) \ 107 V(pminuw, 66, 0F, 38, 3A) \ 108 V(pminud, 66, 0F, 38, 3B) \ 109 V(pmaxsb, 66, 0F, 38, 3C) \ 110 V(pmaxsd, 66, 0F, 38, 3D) \ 111 V(pmaxuw, 66, 0F, 38, 3E) \ 112 V(pmaxud, 66, 0F, 38, 3F) \ 113 V(pmulld, 66, 0F, 38, 40) 114 115 #define SSE4_RM_INSTRUCTION_LIST(V) \ 116 V(pmovsxbw, 66, 0F, 38, 20) \ 117 V(pmovsxwd, 66, 0F, 38, 23) \ 118 V(pmovsxdq, 66, 0F, 38, 25) \ 119 V(pmovzxbw, 66, 0F, 38, 30) \ 120 V(pmovzxwd, 66, 0F, 38, 33) \ 121 V(pmovzxdq, 66, 0F, 38, 35) \ 122 V(ptest, 66, 0F, 38, 17) 123 124 // These require AVX2, and we only define the VEX-128 versions. 125 #define AVX2_BROADCAST_LIST(V) \ 126 V(vpbroadcastd, 66, 0F, 38, 58) \ 127 V(vpbroadcastb, 66, 0F, 38, 78) \ 128 V(vpbroadcastw, 66, 0F, 38, 79) 129 130 #endif // V8_CODEGEN_IA32_SSE_INSTR_H_ 131