1 /* Definitions of target machine for GNU compiler, for Sun SPARC. 2 Copyright (C) 1987-2021 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com). 4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #include "config/vxworks-dummy.h" 24 25 /* Note that some other tm.h files include this one and then override 26 whatever definitions are necessary. */ 27 28 #define TARGET_CPU_CPP_BUILTINS() sparc_target_macros () 29 30 /* Target hooks for D language. */ 31 #define TARGET_D_CPU_VERSIONS sparc_d_target_versions 32 #define TARGET_D_REGISTER_CPU_TARGET_INFO sparc_d_register_target_info 33 34 /* Specify this in a cover file to provide bi-architecture (32/64) support. */ 35 /* #define SPARC_BI_ARCH */ 36 37 /* Macro used later in this file to determine default architecture. */ 38 #define DEFAULT_ARCH32_P ((TARGET_DEFAULT & MASK_64BIT) == 0) 39 40 /* TARGET_ARCH{32,64} are the main macros to decide which of the two 41 architectures to compile for. We allow targets to choose compile time or 42 runtime selection. */ 43 #ifdef IN_LIBGCC2 44 #if defined(__sparcv9) || defined(__arch64__) 45 #define TARGET_ARCH32 0 46 #else 47 #define TARGET_ARCH32 1 48 #endif /* sparc64 */ 49 #else 50 #ifdef SPARC_BI_ARCH 51 #define TARGET_ARCH32 (!TARGET_64BIT) 52 #else 53 #define TARGET_ARCH32 (DEFAULT_ARCH32_P) 54 #endif /* SPARC_BI_ARCH */ 55 #endif /* IN_LIBGCC2 */ 56 #define TARGET_ARCH64 (!TARGET_ARCH32) 57 58 /* Code model selection in 64-bit environment. 59 60 The machine mode used for addresses is 32-bit wide: 61 62 TARGET_CM_32: 32-bit address space. 63 It is the code model used when generating 32-bit code. 64 65 The machine mode used for addresses is 64-bit wide: 66 67 TARGET_CM_MEDLOW: 32-bit address space. 68 The executable must be in the low 32 bits of memory. 69 This avoids generating %uhi and %ulo terms. Programs 70 can be statically or dynamically linked. 71 72 TARGET_CM_MEDMID: 44-bit address space. 73 The executable must be in the low 44 bits of memory, 74 and the %[hml]44 terms are used. The text and data 75 segments have a maximum size of 2GB (31-bit span). 76 The maximum offset from any instruction to the label 77 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 78 79 TARGET_CM_MEDANY: 64-bit address space. 80 The text and data segments have a maximum size of 2GB 81 (31-bit span) and may be located anywhere in memory. 82 The maximum offset from any instruction to the label 83 _GLOBAL_OFFSET_TABLE_ is 2GB (31-bit span). 84 85 TARGET_CM_EMBMEDANY: 64-bit address space. 86 The text and data segments have a maximum size of 2GB 87 (31-bit span) and may be located anywhere in memory. 88 The global register %g4 contains the start address of 89 the data segment. Programs are statically linked and 90 PIC is not supported. 91 92 Different code models are not supported in 32-bit environment. */ 93 94 #define TARGET_CM_MEDLOW (sparc_code_model == CM_MEDLOW) 95 #define TARGET_CM_MEDMID (sparc_code_model == CM_MEDMID) 96 #define TARGET_CM_MEDANY (sparc_code_model == CM_MEDANY) 97 #define TARGET_CM_EMBMEDANY (sparc_code_model == CM_EMBMEDANY) 98 99 /* Default code model to be overridden in 64-bit environment. */ 100 #define SPARC_DEFAULT_CMODEL CM_32 101 102 /* Do not use the .note.GNU-stack convention by default. */ 103 #define NEED_INDICATE_EXEC_STACK 0 104 105 /* This is call-clobbered in the normal ABI, but is reserved in the 106 home grown (aka upward compatible) embedded ABI. */ 107 #define EMBMEDANY_BASE_REG "%g4" 108 109 /* Values of TARGET_CPU_DEFAULT, set via -D in the Makefile, 110 and specified by the user via --with-cpu=foo. 111 This specifies the cpu implementation, not the architecture size. */ 112 /* Note that TARGET_CPU_v9 is assumed to start the list of 64-bit 113 capable cpu's. */ 114 #define TARGET_CPU_sparc 0 115 #define TARGET_CPU_v7 0 /* alias */ 116 #define TARGET_CPU_cypress 0 /* alias */ 117 #define TARGET_CPU_v8 1 /* generic v8 implementation */ 118 #define TARGET_CPU_supersparc 2 119 #define TARGET_CPU_hypersparc 3 120 #define TARGET_CPU_leon 4 121 #define TARGET_CPU_leon3 5 122 #define TARGET_CPU_leon3v7 6 123 #define TARGET_CPU_sparclite 7 124 #define TARGET_CPU_f930 7 /* alias */ 125 #define TARGET_CPU_f934 7 /* alias */ 126 #define TARGET_CPU_sparclite86x 8 127 #define TARGET_CPU_sparclet 9 128 #define TARGET_CPU_tsc701 9 /* alias */ 129 #define TARGET_CPU_v9 10 /* generic v9 implementation */ 130 #define TARGET_CPU_sparcv9 10 /* alias */ 131 #define TARGET_CPU_sparc64 10 /* alias */ 132 #define TARGET_CPU_ultrasparc 11 133 #define TARGET_CPU_ultrasparc3 12 134 #define TARGET_CPU_niagara 13 135 #define TARGET_CPU_niagara2 14 136 #define TARGET_CPU_niagara3 15 137 #define TARGET_CPU_niagara4 16 138 #define TARGET_CPU_niagara7 19 139 #define TARGET_CPU_m8 20 140 141 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \ 142 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \ 143 || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \ 144 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara \ 145 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 \ 146 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 \ 147 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 \ 148 || TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 \ 149 || TARGET_CPU_DEFAULT == TARGET_CPU_m8 150 151 #define CPP_CPU32_DEFAULT_SPEC "" 152 #define ASM_CPU32_DEFAULT_SPEC "" 153 154 #if TARGET_CPU_DEFAULT == TARGET_CPU_v9 155 /* ??? What does Sun's CC pass? */ 156 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 157 /* ??? It's not clear how other assemblers will handle this, so by default 158 use GAS. Sun's Solaris assembler recognizes -xarch=v8plus, but this case 159 is handled in sol2.h. */ 160 #define ASM_CPU64_DEFAULT_SPEC "-Av9" 161 #endif 162 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc 163 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 164 #define ASM_CPU64_DEFAULT_SPEC "-Av9a" 165 #endif 166 #if TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 167 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 168 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 169 #endif 170 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara 171 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 172 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 173 #endif 174 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara2 175 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 176 #define ASM_CPU64_DEFAULT_SPEC "-Av9b" 177 #endif 178 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara3 179 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 180 #define ASM_CPU64_DEFAULT_SPEC "-Av9" AS_NIAGARA3_FLAG 181 #endif 182 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara4 183 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 184 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA4_FLAG 185 #endif 186 #if TARGET_CPU_DEFAULT == TARGET_CPU_niagara7 187 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 188 #define ASM_CPU64_DEFAULT_SPEC AS_NIAGARA7_FLAG 189 #endif 190 #if TARGET_CPU_DEFAULT == TARGET_CPU_m8 191 #define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__" 192 #define ASM_CPU64_DEFAULT_SPEC AS_M8_FLAG 193 #endif 194 195 #else 196 197 #define CPP_CPU64_DEFAULT_SPEC "" 198 #define ASM_CPU64_DEFAULT_SPEC "" 199 200 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparc \ 201 || TARGET_CPU_DEFAULT == TARGET_CPU_v8 202 #define CPP_CPU32_DEFAULT_SPEC "" 203 #define ASM_CPU32_DEFAULT_SPEC "" 204 #endif 205 206 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclet 207 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclet__" 208 #define ASM_CPU32_DEFAULT_SPEC "-Asparclet" 209 #endif 210 211 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite 212 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite__" 213 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 214 #endif 215 216 #if TARGET_CPU_DEFAULT == TARGET_CPU_sparclite86x 217 #define CPP_CPU32_DEFAULT_SPEC "-D__sparclite86x__" 218 #define ASM_CPU32_DEFAULT_SPEC "-Asparclite" 219 #endif 220 221 #if TARGET_CPU_DEFAULT == TARGET_CPU_supersparc 222 #define CPP_CPU32_DEFAULT_SPEC "-D__supersparc__ -D__sparc_v8__" 223 #define ASM_CPU32_DEFAULT_SPEC "" 224 #endif 225 226 #if TARGET_CPU_DEFAULT == TARGET_CPU_hypersparc 227 #define CPP_CPU32_DEFAULT_SPEC "-D__hypersparc__ -D__sparc_v8__" 228 #define ASM_CPU32_DEFAULT_SPEC "" 229 #endif 230 231 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon \ 232 || TARGET_CPU_DEFAULT == TARGET_CPU_leon3 233 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__ -D__sparc_v8__" 234 #define ASM_CPU32_DEFAULT_SPEC AS_LEON_FLAG 235 #endif 236 237 #if TARGET_CPU_DEFAULT == TARGET_CPU_leon3v7 238 #define CPP_CPU32_DEFAULT_SPEC "-D__leon__" 239 #define ASM_CPU32_DEFAULT_SPEC AS_LEONV7_FLAG 240 #endif 241 242 #endif 243 244 #if !defined(CPP_CPU32_DEFAULT_SPEC) || !defined(CPP_CPU64_DEFAULT_SPEC) 245 #error Unrecognized value in TARGET_CPU_DEFAULT. 246 #endif 247 248 #ifdef SPARC_BI_ARCH 249 250 #define CPP_CPU_DEFAULT_SPEC \ 251 (DEFAULT_ARCH32_P ? "\ 252 %{m64:" CPP_CPU64_DEFAULT_SPEC "} \ 253 %{!m64:" CPP_CPU32_DEFAULT_SPEC "} \ 254 " : "\ 255 %{m32:" CPP_CPU32_DEFAULT_SPEC "} \ 256 %{!m32:" CPP_CPU64_DEFAULT_SPEC "} \ 257 ") 258 #define ASM_CPU_DEFAULT_SPEC \ 259 (DEFAULT_ARCH32_P ? "\ 260 %{m64:" ASM_CPU64_DEFAULT_SPEC "} \ 261 %{!m64:" ASM_CPU32_DEFAULT_SPEC "} \ 262 " : "\ 263 %{m32:" ASM_CPU32_DEFAULT_SPEC "} \ 264 %{!m32:" ASM_CPU64_DEFAULT_SPEC "} \ 265 ") 266 267 #else /* !SPARC_BI_ARCH */ 268 269 #define CPP_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? CPP_CPU32_DEFAULT_SPEC : CPP_CPU64_DEFAULT_SPEC) 270 #define ASM_CPU_DEFAULT_SPEC (DEFAULT_ARCH32_P ? ASM_CPU32_DEFAULT_SPEC : ASM_CPU64_DEFAULT_SPEC) 271 272 #endif /* !SPARC_BI_ARCH */ 273 274 /* Define macros to distinguish architectures. */ 275 276 /* Common CPP definitions used by CPP_SPEC amongst the various targets 277 for handling -mcpu=xxx switches. */ 278 #define CPP_CPU_SPEC "\ 279 %{mcpu=sparclet:-D__sparclet__} %{mcpu=tsc701:-D__sparclet__} \ 280 %{mcpu=sparclite:-D__sparclite__} \ 281 %{mcpu=f930:-D__sparclite__} %{mcpu=f934:-D__sparclite__} \ 282 %{mcpu=sparclite86x:-D__sparclite86x__} \ 283 %{mcpu=v8:-D__sparc_v8__} \ 284 %{mcpu=supersparc:-D__supersparc__ -D__sparc_v8__} \ 285 %{mcpu=hypersparc:-D__hypersparc__ -D__sparc_v8__} \ 286 %{mcpu=leon:-D__leon__ -D__sparc_v8__} \ 287 %{mcpu=leon3:-D__leon__ -D__sparc_v8__} \ 288 %{mcpu=leon3v7:-D__leon__} \ 289 %{mcpu=v9:-D__sparc_v9__} \ 290 %{mcpu=ultrasparc:-D__sparc_v9__} \ 291 %{mcpu=ultrasparc3:-D__sparc_v9__} \ 292 %{mcpu=niagara:-D__sparc_v9__} \ 293 %{mcpu=niagara2:-D__sparc_v9__} \ 294 %{mcpu=niagara3:-D__sparc_v9__} \ 295 %{mcpu=niagara4:-D__sparc_v9__} \ 296 %{mcpu=niagara7:-D__sparc_v9__} \ 297 %{mcpu=m8:-D__sparc_v9__} \ 298 %{!mcpu*:%(cpp_cpu_default)} \ 299 " 300 #define CPP_ARCH32_SPEC "" 301 #define CPP_ARCH64_SPEC "-D__arch64__" 302 303 #define CPP_ARCH_DEFAULT_SPEC \ 304 (DEFAULT_ARCH32_P ? CPP_ARCH32_SPEC : CPP_ARCH64_SPEC) 305 306 #define CPP_ARCH_SPEC "\ 307 %{m32:%(cpp_arch32)} \ 308 %{m64:%(cpp_arch64)} \ 309 %{!m32:%{!m64:%(cpp_arch_default)}} \ 310 " 311 312 /* Macros to distinguish the endianness, window model and FP support. */ 313 #define CPP_OTHER_SPEC "\ 314 %{mflat:-D_FLAT} \ 315 %{msoft-float:-D_SOFT_FLOAT} \ 316 " 317 318 /* Macros to distinguish the particular subtarget. */ 319 #define CPP_SUBTARGET_SPEC "" 320 321 #define CPP_SPEC \ 322 "%(cpp_cpu) %(cpp_arch) %(cpp_endian) %(cpp_other) %(cpp_subtarget)" 323 324 /* This used to translate -dalign to -malign, but that is no good 325 because it can't turn off the usual meaning of making debugging dumps. */ 326 327 #define CC1_SPEC "" 328 329 /* Override in target specific files. */ 330 #define ASM_CPU_SPEC "\ 331 %{mcpu=sparclet:-Asparclet} %{mcpu=tsc701:-Asparclet} \ 332 %{mcpu=sparclite:-Asparclite} \ 333 %{mcpu=sparclite86x:-Asparclite} \ 334 %{mcpu=f930:-Asparclite} %{mcpu=f934:-Asparclite} \ 335 %{mcpu=v8:-Av8} \ 336 %{mcpu=supersparc:-Av8} \ 337 %{mcpu=hypersparc:-Av8} \ 338 %{mcpu=leon:" AS_LEON_FLAG "} \ 339 %{mcpu=leon3:" AS_LEON_FLAG "} \ 340 %{mcpu=leon3v7:" AS_LEONV7_FLAG "} \ 341 %{mv8plus:-Av8plus} \ 342 %{mcpu=v9:-Av9} \ 343 %{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \ 344 %{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \ 345 %{mcpu=niagara:%{!mv8plus:-Av9b}} \ 346 %{mcpu=niagara2:%{!mv8plus:-Av9b}} \ 347 %{mcpu=niagara3:%{!mv8plus:-Av9" AS_NIAGARA3_FLAG "}} \ 348 %{mcpu=niagara4:%{!mv8plus:" AS_NIAGARA4_FLAG "}} \ 349 %{mcpu=niagara7:%{!mv8plus:" AS_NIAGARA7_FLAG "}} \ 350 %{mcpu=m8:%{!mv8plus:" AS_M8_FLAG "}} \ 351 %{!mcpu*:%(asm_cpu_default)} \ 352 " 353 354 /* Word size selection, among other things. 355 This is what GAS uses. Add %(asm_arch) to ASM_SPEC to enable. */ 356 357 #define ASM_ARCH32_SPEC "-32" 358 #define ASM_ARCH64_SPEC "-64 -no-undeclared-regs" 359 #define ASM_ARCH_DEFAULT_SPEC \ 360 (DEFAULT_ARCH32_P ? ASM_ARCH32_SPEC : ASM_ARCH64_SPEC) 361 362 #define ASM_ARCH_SPEC "\ 363 %{m32:%(asm_arch32)} \ 364 %{m64:%(asm_arch64)} \ 365 %{!m32:%{!m64:%(asm_arch_default)}} \ 366 " 367 368 #ifdef HAVE_AS_RELAX_OPTION 369 #define ASM_RELAX_SPEC "%{!mno-relax:-relax}" 370 #else 371 #define ASM_RELAX_SPEC "" 372 #endif 373 374 /* Special flags to the Sun-4 assembler when using pipe for input. */ 375 376 #define ASM_SPEC "\ 377 %{!pg:%{!p:%{" FPIE_OR_FPIC_SPEC ":-k}}} %{keep-local-as-symbols:-L} \ 378 %(asm_cpu) %(asm_relax)" 379 380 /* This macro defines names of additional specifications to put in the specs 381 that can be used in various specifications like CC1_SPEC. Its definition 382 is an initializer with a subgrouping for each command option. 383 384 Each subgrouping contains a string constant, that defines the 385 specification name, and a string constant that used by the GCC driver 386 program. 387 388 Do not define this macro if it does not need to do anything. */ 389 390 #define EXTRA_SPECS \ 391 { "cpp_cpu", CPP_CPU_SPEC }, \ 392 { "cpp_cpu_default", CPP_CPU_DEFAULT_SPEC }, \ 393 { "cpp_arch32", CPP_ARCH32_SPEC }, \ 394 { "cpp_arch64", CPP_ARCH64_SPEC }, \ 395 { "cpp_arch_default", CPP_ARCH_DEFAULT_SPEC },\ 396 { "cpp_arch", CPP_ARCH_SPEC }, \ 397 { "cpp_other", CPP_OTHER_SPEC }, \ 398 { "cpp_subtarget", CPP_SUBTARGET_SPEC }, \ 399 { "asm_cpu", ASM_CPU_SPEC }, \ 400 { "asm_cpu_default", ASM_CPU_DEFAULT_SPEC }, \ 401 { "asm_arch32", ASM_ARCH32_SPEC }, \ 402 { "asm_arch64", ASM_ARCH64_SPEC }, \ 403 { "asm_relax", ASM_RELAX_SPEC }, \ 404 { "asm_arch_default", ASM_ARCH_DEFAULT_SPEC },\ 405 { "asm_arch", ASM_ARCH_SPEC }, \ 406 SUBTARGET_EXTRA_SPECS 407 408 #define SUBTARGET_EXTRA_SPECS 409 410 /* Because libgcc can generate references back to libc (via .umul etc.) we have 411 to list libc again after the second libgcc. */ 412 #define LINK_GCC_C_SEQUENCE_SPEC "%G %{!nolibc:%L} %G %{!nolibc:%L}" 413 414 415 #define PTRDIFF_TYPE (TARGET_ARCH64 ? "long int" : "int") 416 #define SIZE_TYPE (TARGET_ARCH64 ? "long unsigned int" : "unsigned int") 417 418 /* ??? This should be 32 bits for v9 but what can we do? */ 419 #define WCHAR_TYPE "short unsigned int" 420 #define WCHAR_TYPE_SIZE 16 421 422 /* Mask of all CPU selection flags. */ 423 #define MASK_ISA \ 424 (MASK_SPARCLITE + MASK_SPARCLET + MASK_LEON + MASK_LEON3 \ 425 + MASK_V8 + MASK_V9 + MASK_DEPRECATED_V8_INSNS) 426 427 /* Mask of all CPU feature flags. */ 428 #define MASK_FEATURES \ 429 (MASK_FPU + MASK_HARD_QUAD + MASK_VIS + MASK_VIS2 + MASK_VIS3 \ 430 + MASK_VIS4 + MASK_CBCOND + MASK_FMAF + MASK_FSMULD \ 431 + MASK_POPC + MASK_SUBXC) 432 433 /* TARGET_HARD_MUL: Use 32-bit hardware multiply instructions but not %y. */ 434 #define TARGET_HARD_MUL \ 435 (TARGET_SPARCLITE || TARGET_SPARCLET \ 436 || TARGET_V8 || TARGET_DEPRECATED_V8_INSNS) 437 438 /* TARGET_HARD_MUL32: Use 32-bit hardware multiply instructions with %y 439 to get high 32 bits. False in 64-bit or V8+ because multiply stores 440 a 64-bit result in a register. */ 441 #define TARGET_HARD_MUL32 \ 442 (TARGET_HARD_MUL && TARGET_ARCH32 && !TARGET_V8PLUS) 443 444 /* MASK_APP_REGS must always be the default because that's what 445 FIXED_REGISTERS is set to and -ffixed- is processed before 446 TARGET_CONDITIONAL_REGISTER_USAGE is called (where we process 447 -mno-app-regs). */ 448 #define TARGET_DEFAULT (MASK_APP_REGS + MASK_FPU) 449 450 /* Recast the cpu class to be the cpu attribute. 451 Every file includes us, but not every file includes insn-attr.h. */ 452 #define sparc_cpu_attr ((enum attr_cpu) sparc_cpu) 453 454 /* Support for a compile-time default CPU, et cetera. The rules are: 455 --with-cpu is ignored if -mcpu is specified. 456 --with-tune is ignored if -mtune is specified. 457 --with-float is ignored if -mhard-float, -msoft-float, -mfpu, or -mno-fpu 458 are specified. */ 459 #define OPTION_DEFAULT_SPECS \ 460 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 461 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" }, \ 462 {"float", "%{!msoft-float:%{!mhard-float:%{!mfpu:%{!mno-fpu:-m%(VALUE)-float}}}}" } 463 464 /* target machine storage layout */ 465 466 /* Define this if most significant bit is lowest numbered 467 in instructions that operate on numbered bit-fields. */ 468 #define BITS_BIG_ENDIAN 1 469 470 /* Define this if most significant byte of a word is the lowest numbered. */ 471 #define BYTES_BIG_ENDIAN 1 472 473 /* Define this if most significant word of a multiword number is the lowest 474 numbered. */ 475 #define WORDS_BIG_ENDIAN 1 476 477 #define MAX_BITS_PER_WORD 64 478 479 /* Width of a word, in units (bytes). */ 480 #define UNITS_PER_WORD (TARGET_ARCH64 ? 8 : 4) 481 #ifdef IN_LIBGCC2 482 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 483 #else 484 #define MIN_UNITS_PER_WORD 4 485 #endif 486 487 /* Now define the sizes of the C data types. */ 488 #define SHORT_TYPE_SIZE 16 489 #define INT_TYPE_SIZE 32 490 #define LONG_TYPE_SIZE (TARGET_ARCH64 ? 64 : 32) 491 #define LONG_LONG_TYPE_SIZE 64 492 #define FLOAT_TYPE_SIZE 32 493 #define DOUBLE_TYPE_SIZE 64 494 495 /* LONG_DOUBLE_TYPE_SIZE is defined per OS even though the 496 SPARC ABI says that it is 128-bit wide. */ 497 /* #define LONG_DOUBLE_TYPE_SIZE 128 */ 498 499 /* The widest floating-point format really supported by the hardware. */ 500 #define WIDEST_HARDWARE_FP_SIZE 64 501 502 /* Width in bits of a pointer. This is the size of ptr_mode. */ 503 #define POINTER_SIZE (TARGET_PTR64 ? 64 : 32) 504 505 /* This is the machine mode used for addresses. */ 506 #define Pmode (TARGET_ARCH64 ? DImode : SImode) 507 508 /* If we have to extend pointers (only when TARGET_ARCH64 and not 509 TARGET_PTR64), we want to do it unsigned. This macro does nothing 510 if ptr_mode and Pmode are the same. */ 511 #define POINTERS_EXTEND_UNSIGNED 1 512 513 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 514 #define PARM_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 515 516 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 517 /* FIXME, this is wrong when TARGET_ARCH64 and TARGET_STACK_BIAS, because 518 then %sp+2047 is 128-bit aligned so %sp is really only byte-aligned. */ 519 #define STACK_BOUNDARY (TARGET_ARCH64 ? 128 : 64) 520 521 /* Temporary hack until the FIXME above is fixed. */ 522 #define SPARC_STACK_BOUNDARY_HACK (TARGET_ARCH64 && TARGET_STACK_BIAS) 523 524 /* ALIGN FRAMES on double word boundaries */ 525 #define SPARC_STACK_ALIGN(LOC) ROUND_UP ((LOC), UNITS_PER_WORD * 2) 526 527 /* Allocation boundary (in *bits*) for the code of a function. */ 528 #define FUNCTION_BOUNDARY 32 529 530 /* Alignment of field after `int : 0' in a structure. */ 531 #define EMPTY_FIELD_BOUNDARY (TARGET_ARCH64 ? 64 : 32) 532 533 /* Every structure's size must be a multiple of this. */ 534 #define STRUCTURE_SIZE_BOUNDARY 8 535 536 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 537 #define PCC_BITFIELD_TYPE_MATTERS 1 538 539 /* No data type wants to be aligned rounder than this. */ 540 #define BIGGEST_ALIGNMENT (TARGET_ARCH64 ? 128 : 64) 541 542 /* The best alignment to use in cases where we have a choice. */ 543 #define FASTEST_ALIGNMENT 64 544 545 /* Define this macro as an expression for the alignment of a structure 546 (given by STRUCT as a tree node) if the alignment computed in the 547 usual way is COMPUTED and the alignment explicitly specified was 548 SPECIFIED. 549 550 The default is to use SPECIFIED if it is larger; otherwise, use 551 the smaller of COMPUTED and `BIGGEST_ALIGNMENT' */ 552 #define ROUND_TYPE_ALIGN(STRUCT, COMPUTED, SPECIFIED) \ 553 (TARGET_FASTER_STRUCTS ? \ 554 ((TREE_CODE (STRUCT) == RECORD_TYPE \ 555 || TREE_CODE (STRUCT) == UNION_TYPE \ 556 || TREE_CODE (STRUCT) == QUAL_UNION_TYPE) \ 557 && TYPE_FIELDS (STRUCT) != 0 \ 558 ? MAX (MAX ((COMPUTED), (SPECIFIED)), BIGGEST_ALIGNMENT) \ 559 : MAX ((COMPUTED), (SPECIFIED))) \ 560 : MAX ((COMPUTED), (SPECIFIED))) 561 562 /* An integer expression for the size in bits of the largest integer machine 563 mode that should actually be used. We allow pairs of registers. */ 564 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_ARCH64 ? TImode : DImode) 565 566 /* We need 2 words, so we can save the stack pointer and the return register 567 of the function containing a non-local goto target. */ 568 #define STACK_SAVEAREA_MODE(LEVEL) \ 569 ((LEVEL) == SAVE_NONLOCAL ? (TARGET_ARCH64 ? TImode : DImode) : Pmode) 570 571 /* Make arrays of chars word-aligned for the same reasons. */ 572 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 573 (TREE_CODE (TYPE) == ARRAY_TYPE \ 574 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 575 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 576 577 /* Make local arrays of chars word-aligned for the same reasons. */ 578 #define LOCAL_ALIGNMENT(TYPE, ALIGN) DATA_ALIGNMENT (TYPE, ALIGN) 579 580 /* Set this nonzero if move instructions will actually fail to work 581 when given unaligned data. */ 582 #define STRICT_ALIGNMENT 1 583 584 /* Things that must be doubleword aligned cannot go in the text section, 585 because the linker fails to align the text section enough! 586 Put them in the data section. This macro is only used in this file. */ 587 #define MAX_TEXT_ALIGN 32 588 589 /* Standard register usage. */ 590 591 /* Number of actual hardware registers. 592 The hardware registers are assigned numbers for the compiler 593 from 0 to just below FIRST_PSEUDO_REGISTER. 594 All registers that the compiler knows about must be given numbers, 595 even those that are not normally considered general registers. 596 597 SPARC has 32 integer registers and 32 floating point registers. 598 64-bit SPARC has 32 additional fp regs, but the odd numbered ones are not 599 accessible. We still account for them to simplify register computations 600 (e.g.: in CLASS_MAX_NREGS). There are also 4 fp condition code registers, so 601 32+32+32+4 == 100. 602 Register 100 is used as the integer condition code register. 603 Register 101 is used as the soft frame pointer register. 604 Register 102 is used as the general status register by VIS instructions. */ 605 606 #define FIRST_PSEUDO_REGISTER 103 607 608 #define SPARC_FIRST_INT_REG 0 609 #define SPARC_LAST_INT_REG 31 610 #define SPARC_FIRST_FP_REG 32 611 /* Additional V9 fp regs. */ 612 #define SPARC_FIRST_V9_FP_REG 64 613 #define SPARC_LAST_V9_FP_REG 95 614 /* V9 %fcc[0123]. V8 uses (figuratively) %fcc0. */ 615 #define SPARC_FIRST_V9_FCC_REG 96 616 #define SPARC_LAST_V9_FCC_REG 99 617 /* V8 fcc reg. */ 618 #define SPARC_FCC_REG 96 619 /* Integer CC reg. We don't distinguish %icc from %xcc. */ 620 #define SPARC_ICC_REG 100 621 #define SPARC_GSR_REG 102 622 623 /* Nonzero if REGNO is an fp reg. */ 624 #define SPARC_FP_REG_P(REGNO) \ 625 ((REGNO) >= SPARC_FIRST_FP_REG && (REGNO) <= SPARC_LAST_V9_FP_REG) 626 627 /* Nonzero if REGNO is an int reg. */ 628 #define SPARC_INT_REG_P(REGNO) \ 629 (((unsigned) (REGNO)) <= SPARC_LAST_INT_REG) 630 631 /* Argument passing regs. */ 632 #define SPARC_OUTGOING_INT_ARG_FIRST 8 633 #define SPARC_INCOMING_INT_ARG_FIRST (TARGET_FLAT ? 8 : 24) 634 #define SPARC_FP_ARG_FIRST 32 635 636 /* 1 for registers that have pervasive standard uses 637 and are not available for the register allocator. 638 639 On non-v9 systems: 640 g1 is free to use as temporary. 641 g2-g4 are reserved for applications. Gcc normally uses them as 642 temporaries, but this can be disabled via the -mno-app-regs option. 643 g5 through g7 are reserved for the operating system. 644 645 On v9 systems: 646 g1,g5 are free to use as temporaries, and are free to use between calls 647 if the call is to an external function via the PLT. 648 g4 is free to use as a temporary in the non-embedded case. 649 g4 is reserved in the embedded case. 650 g2-g3 are reserved for applications. Gcc normally uses them as 651 temporaries, but this can be disabled via the -mno-app-regs option. 652 g6-g7 are reserved for the operating system (or application in 653 embedded case). 654 ??? Register 1 is used as a temporary by the 64 bit sethi pattern, so must 655 currently be a fixed register until this pattern is rewritten. 656 Register 1 is also used when restoring call-preserved registers in large 657 stack frames. 658 659 Registers fixed in arch32 and not arch64 (or vice-versa) are marked in 660 TARGET_CONDITIONAL_REGISTER_USAGE in order to properly handle -ffixed-. 661 */ 662 663 #define FIXED_REGISTERS \ 664 {1, 0, 2, 2, 2, 2, 1, 1, \ 665 0, 0, 0, 0, 0, 0, 1, 0, \ 666 0, 0, 0, 0, 0, 0, 0, 0, \ 667 0, 0, 0, 0, 0, 0, 0, 1, \ 668 \ 669 0, 0, 0, 0, 0, 0, 0, 0, \ 670 0, 0, 0, 0, 0, 0, 0, 0, \ 671 0, 0, 0, 0, 0, 0, 0, 0, \ 672 0, 0, 0, 0, 0, 0, 0, 0, \ 673 \ 674 0, 0, 0, 0, 0, 0, 0, 0, \ 675 0, 0, 0, 0, 0, 0, 0, 0, \ 676 0, 0, 0, 0, 0, 0, 0, 0, \ 677 0, 0, 0, 0, 0, 0, 0, 0, \ 678 \ 679 0, 0, 0, 0, 1, 1, 1} 680 681 /* 1 for registers not available across function calls. 682 Unlike the above, this need not include the FIXED_REGISTERS, but any 683 registers that can be used without being saved. 684 The latter must include the registers where values are returned 685 and the register where structure-value addresses are passed. 686 Aside from that, you can include as many other registers as you like. */ 687 688 #define CALL_REALLY_USED_REGISTERS \ 689 {1, 1, 1, 1, 1, 1, 1, 1, \ 690 1, 1, 1, 1, 1, 1, 1, 1, \ 691 0, 0, 0, 0, 0, 0, 0, 0, \ 692 0, 0, 0, 0, 0, 0, 0, 0, \ 693 \ 694 1, 1, 1, 1, 1, 1, 1, 1, \ 695 1, 1, 1, 1, 1, 1, 1, 1, \ 696 1, 1, 1, 1, 1, 1, 1, 1, \ 697 1, 1, 1, 1, 1, 1, 1, 1, \ 698 \ 699 1, 1, 1, 1, 1, 1, 1, 1, \ 700 1, 1, 1, 1, 1, 1, 1, 1, \ 701 1, 1, 1, 1, 1, 1, 1, 1, \ 702 1, 1, 1, 1, 1, 1, 1, 1, \ 703 \ 704 1, 1, 1, 1, 1, 1, 1} 705 706 /* Due to the ARCH64 discrepancy above we must override this next 707 macro too. */ 708 #define REGMODE_NATURAL_SIZE(MODE) sparc_regmode_natural_size (MODE) 709 710 /* Value is 1 if it is OK to rename a hard register FROM to another hard 711 register TO. We cannot rename %g1 as it may be used before the save 712 register window instruction in the prologue. */ 713 #define HARD_REGNO_RENAME_OK(FROM, TO) ((FROM) != 1) 714 715 /* Select a register mode required for caller save of hard regno REGNO. 716 Contrary to what is documented, the default is not the smallest suitable 717 mode but the largest suitable mode for the given (REGNO, NREGS) pair and 718 it quickly creates paradoxical subregs that can be problematic. */ 719 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 720 ((MODE) == VOIDmode ? choose_hard_reg_mode (REGNO, NREGS, NULL) : (MODE)) 721 722 /* Specify the registers used for certain standard purposes. 723 The values of these macros are register numbers. */ 724 725 /* Register to use for pushing function arguments. */ 726 #define STACK_POINTER_REGNUM 14 727 728 /* The stack bias (amount by which the hardware register is offset by). */ 729 #define SPARC_STACK_BIAS ((TARGET_ARCH64 && TARGET_STACK_BIAS) ? 2047 : 0) 730 731 /* Actual top-of-stack address is 92/176 greater than the contents of the 732 stack pointer register for !v9/v9. That is: 733 - !v9: 64 bytes for the in and local registers, 4 bytes for structure return 734 address, and 6*4 bytes for the 6 register parameters. 735 - v9: 128 bytes for the in and local registers + 6*8 bytes for the integer 736 parameter regs. */ 737 #define STACK_POINTER_OFFSET (FIRST_PARM_OFFSET(0) + SPARC_STACK_BIAS) 738 739 /* Base register for access to local variables of the function. */ 740 #define HARD_FRAME_POINTER_REGNUM 30 741 742 /* The soft frame pointer does not have the stack bias applied. */ 743 #define FRAME_POINTER_REGNUM 101 744 745 #define INIT_EXPANDERS \ 746 do { \ 747 if (crtl->emit.regno_pointer_align) \ 748 { \ 749 /* The biased stack pointer is only aligned on BITS_PER_UNIT. */\ 750 if (SPARC_STACK_BIAS) \ 751 { \ 752 REGNO_POINTER_ALIGN (STACK_POINTER_REGNUM) \ 753 = BITS_PER_UNIT; \ 754 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) \ 755 = BITS_PER_UNIT; \ 756 } \ 757 \ 758 /* In 32-bit mode, not everything is double-word aligned. */ \ 759 if (TARGET_ARCH32) \ 760 { \ 761 REGNO_POINTER_ALIGN (VIRTUAL_INCOMING_ARGS_REGNUM) \ 762 = BITS_PER_WORD; \ 763 REGNO_POINTER_ALIGN (VIRTUAL_STACK_DYNAMIC_REGNUM) \ 764 = BITS_PER_WORD; \ 765 REGNO_POINTER_ALIGN (VIRTUAL_OUTGOING_ARGS_REGNUM) \ 766 = BITS_PER_WORD; \ 767 } \ 768 } \ 769 } while (0) 770 771 /* Base register for access to arguments of the function. */ 772 #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM 773 774 /* Register in which static-chain is passed to a function. This must 775 not be a register used by the prologue. */ 776 #define STATIC_CHAIN_REGNUM (TARGET_ARCH64 ? 5 : 2) 777 778 /* Register which holds the global offset table, if any. */ 779 #define GLOBAL_OFFSET_TABLE_REGNUM 23 780 781 /* Register which holds offset table for position-independent data references. 782 The original SPARC ABI imposes no requirement on the choice of the register 783 so we use a pseudo-register to make sure it is properly saved and restored 784 around calls to setjmp. Now the ABI of VxWorks RTP makes it live on entry 785 to PLT entries so we use the canonical GOT register in this case. */ 786 #define PIC_OFFSET_TABLE_REGNUM \ 787 (TARGET_VXWORKS_RTP && flag_pic ? GLOBAL_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 788 789 /* Pick a default value we can notice from override_options: 790 !v9: Default is on. 791 v9: Default is off. 792 Originally it was -1, but later on the container of options changed to 793 unsigned byte, so we decided to pick 127 as default value, which does 794 reflect an undefined default value in case of 0/1. */ 795 #define DEFAULT_PCC_STRUCT_RETURN 127 796 797 /* Functions which return large structures get the address 798 to place the wanted value at offset 64 from the frame. 799 Must reserve 64 bytes for the in and local registers. 800 v9: Functions which return large structures get the address to place the 801 wanted value from an invisible first argument. */ 802 #define STRUCT_VALUE_OFFSET 64 803 804 /* Define the classes of registers for register constraints in the 805 machine description. Also define ranges of constants. 806 807 One of the classes must always be named ALL_REGS and include all hard regs. 808 If there is more than one class, another class must be named NO_REGS 809 and contain no registers. 810 811 The name GENERAL_REGS must be the name of a class (or an alias for 812 another name such as ALL_REGS). This is the class of registers 813 that is allowed by "g" or "r" in a register constraint. 814 Also, registers outside this class are allocated only when 815 instructions express preferences for them. 816 817 The classes must be numbered in nondecreasing order; that is, 818 a larger-numbered class must never be contained completely 819 in a smaller-numbered class. 820 821 For any two classes, it is very desirable that there be another 822 class that represents their union. */ 823 824 /* The SPARC has various kinds of registers: general, floating point, 825 and condition codes [well, it has others as well, but none that we 826 care directly about]. 827 828 For v9 we must distinguish between the upper and lower floating point 829 registers because the upper ones can't hold SFmode values. 830 TARGET_HARD_REGNO_MODE_OK won't help here because reload assumes that 831 register(s) satisfying a group need for a class will also satisfy a 832 single need for that class. EXTRA_FP_REGS is a bit of a misnomer as 833 it covers all 64 fp regs. 834 835 It is important that one class contains all the general and all the standard 836 fp regs. Otherwise find_reg() won't properly allocate int regs for moves, 837 because reg_class_record() will bias the selection in favor of fp regs, 838 because reg_class_subunion[GENERAL_REGS][FP_REGS] will yield FP_REGS, 839 because FP_REGS > GENERAL_REGS. 840 841 It is also important that one class contain all the general and all 842 the fp regs. Otherwise when spilling a DFmode reg, it may be from 843 EXTRA_FP_REGS but find_reloads() may use class 844 GENERAL_OR_FP_REGS. This will cause allocate_reload_reg() to die 845 because the compiler thinks it doesn't have a spill reg when in 846 fact it does. 847 848 v9 also has 4 floating point condition code registers. Since we don't 849 have a class that is the union of FPCC_REGS with either of the others, 850 it is important that it appear first. Otherwise the compiler will die 851 trying to compile _fixunsdfsi because fix_truncdfsi2 won't match its 852 constraints. */ 853 854 enum reg_class { NO_REGS, FPCC_REGS, I64_REGS, GENERAL_REGS, FP_REGS, 855 EXTRA_FP_REGS, GENERAL_OR_FP_REGS, GENERAL_OR_EXTRA_FP_REGS, 856 ALL_REGS, LIM_REG_CLASSES }; 857 858 #define N_REG_CLASSES (int) LIM_REG_CLASSES 859 860 /* Give names of register classes as strings for dump file. */ 861 862 #define REG_CLASS_NAMES \ 863 { "NO_REGS", "FPCC_REGS", "I64_REGS", "GENERAL_REGS", "FP_REGS", \ 864 "EXTRA_FP_REGS", "GENERAL_OR_FP_REGS", "GENERAL_OR_EXTRA_FP_REGS", \ 865 "ALL_REGS" } 866 867 /* Define which registers fit in which classes. 868 This is an initializer for a vector of HARD_REG_SET 869 of length N_REG_CLASSES. */ 870 871 #define REG_CLASS_CONTENTS \ 872 {{0, 0, 0, 0}, /* NO_REGS */ \ 873 {0, 0, 0, 0xf}, /* FPCC_REGS */ \ 874 {0xffff, 0, 0, 0}, /* I64_REGS */ \ 875 {-1, 0, 0, 0x20}, /* GENERAL_REGS */ \ 876 {0, -1, 0, 0}, /* FP_REGS */ \ 877 {0, -1, -1, 0}, /* EXTRA_FP_REGS */ \ 878 {-1, -1, 0, 0x20}, /* GENERAL_OR_FP_REGS */ \ 879 {-1, -1, -1, 0x20}, /* GENERAL_OR_EXTRA_FP_REGS */ \ 880 {-1, -1, -1, 0x7f}} /* ALL_REGS */ 881 882 /* The same information, inverted: 883 Return the class number of the smallest class containing 884 reg number REGNO. This could be a conditional expression 885 or could index an array. */ 886 887 extern enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 888 889 #define REGNO_REG_CLASS(REGNO) sparc_regno_reg_class[(REGNO)] 890 891 /* This is the order in which to allocate registers normally. 892 893 We put %f0-%f7 last among the float registers, so as to make it more 894 likely that a pseudo-register which dies in the float return register 895 area will get allocated to the float return register, thus saving a move 896 instruction at the end of the function. 897 898 Similarly for integer return value registers. 899 900 We know in this case that we will not end up with a leaf function. 901 902 The register allocator is given the global and out registers first 903 because these registers are call clobbered and thus less useful to 904 global register allocation. 905 906 Next we list the local and in registers. They are not call clobbered 907 and thus very useful for global register allocation. We list the input 908 registers before the locals so that it is more likely the incoming 909 arguments received in those registers can just stay there and not be 910 reloaded. */ 911 912 #define REG_ALLOC_ORDER \ 913 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 914 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 915 15, /* %o7 */ \ 916 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 917 29, 28, 27, 26, 25, 24, 31, /* %i5-%i0,%i7 */\ 918 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 919 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 920 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 921 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 922 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 923 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 924 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 925 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 926 96, 97, 98, 99, /* %fcc0-3 */ \ 927 100, 0, 14, 30, 101, 102 } /* %icc, %g0, %o6, %i6, %sfp, %gsr */ 928 929 /* This is the order in which to allocate registers for 930 leaf functions. If all registers can fit in the global and 931 output registers, then we have the possibility of having a leaf 932 function. 933 934 The macro actually mentioned the input registers first, 935 because they get renumbered into the output registers once 936 we know really do have a leaf function. 937 938 To be more precise, this register allocation order is used 939 when %o7 is found to not be clobbered right before register 940 allocation. Normally, the reason %o7 would be clobbered is 941 due to a call which could not be transformed into a sibling 942 call. 943 944 As a consequence, it is possible to use the leaf register 945 allocation order and not end up with a leaf function. We will 946 not get suboptimal register allocation in that case because by 947 definition of being potentially leaf, there were no function 948 calls. Therefore, allocation order within the local register 949 window is not critical like it is when we do have function calls. */ 950 951 #define REG_LEAF_ALLOC_ORDER \ 952 { 1, 2, 3, 4, 5, 6, 7, /* %g1-%g7 */ \ 953 29, 28, 27, 26, 25, 24, /* %i5-%i0 */ \ 954 15, /* %o7 */ \ 955 13, 12, 11, 10, 9, 8, /* %o5-%o0 */ \ 956 16, 17, 18, 19, 20, 21, 22, 23, /* %l0-%l7 */ \ 957 40, 41, 42, 43, 44, 45, 46, 47, /* %f8-%f15 */ \ 958 48, 49, 50, 51, 52, 53, 54, 55, /* %f16-%f23 */ \ 959 56, 57, 58, 59, 60, 61, 62, 63, /* %f24-%f31 */ \ 960 64, 65, 66, 67, 68, 69, 70, 71, /* %f32-%f39 */ \ 961 72, 73, 74, 75, 76, 77, 78, 79, /* %f40-%f47 */ \ 962 80, 81, 82, 83, 84, 85, 86, 87, /* %f48-%f55 */ \ 963 88, 89, 90, 91, 92, 93, 94, 95, /* %f56-%f63 */ \ 964 39, 38, 37, 36, 35, 34, 33, 32, /* %f7-%f0 */ \ 965 96, 97, 98, 99, /* %fcc0-3 */ \ 966 100, 0, 14, 30, 31, 101, 102 } /* %icc, %g0, %o6, %i6, %i7, %sfp, %gsr */ 967 968 #define ADJUST_REG_ALLOC_ORDER order_regs_for_local_alloc () 969 970 extern char sparc_leaf_regs[]; 971 #define LEAF_REGISTERS sparc_leaf_regs 972 973 extern char leaf_reg_remap[]; 974 #define LEAF_REG_REMAP(REGNO) (leaf_reg_remap[REGNO]) 975 976 /* The class value for index registers, and the one for base regs. */ 977 #define INDEX_REG_CLASS GENERAL_REGS 978 #define BASE_REG_CLASS GENERAL_REGS 979 980 /* Local macro to handle the two v9 classes of FP regs. */ 981 #define FP_REG_CLASS_P(CLASS) ((CLASS) == FP_REGS || (CLASS) == EXTRA_FP_REGS) 982 983 /* Predicate for 2-bit and 5-bit unsigned constants. */ 984 #define SPARC_IMM2_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x3) == 0) 985 #define SPARC_IMM5_P(X) (((unsigned HOST_WIDE_INT) (X) & ~0x1F) == 0) 986 987 /* Predicates for 5-bit, 10-bit, 11-bit and 13-bit signed constants. */ 988 #define SPARC_SIMM5_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x10 < 0x20) 989 #define SPARC_SIMM10_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x200 < 0x400) 990 #define SPARC_SIMM11_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x400 < 0x800) 991 #define SPARC_SIMM13_P(X) ((unsigned HOST_WIDE_INT) (X) + 0x1000 < 0x2000) 992 993 /* 10- and 11-bit immediates are only used for a few specific insns. 994 SMALL_INT is used throughout the port so we continue to use it. */ 995 #define SMALL_INT(X) (SPARC_SIMM13_P (INTVAL (X))) 996 997 /* Predicate for constants that can be loaded with a sethi instruction. 998 This is the general, 64-bit aware, bitwise version that ensures that 999 only constants whose representation fits in the mask 1000 1001 0x00000000fffffc00 1002 1003 are accepted. It will reject, for example, negative SImode constants 1004 on 64-bit hosts, so correct handling is to mask the value beforehand 1005 according to the mode of the instruction. */ 1006 #define SPARC_SETHI_P(X) \ 1007 (((unsigned HOST_WIDE_INT) (X) \ 1008 & ((unsigned HOST_WIDE_INT) 0x3ff - GET_MODE_MASK (SImode) - 1)) == 0) 1009 1010 /* Version of the above predicate for SImode constants and below. */ 1011 #define SPARC_SETHI32_P(X) \ 1012 (SPARC_SETHI_P ((unsigned HOST_WIDE_INT) (X) & GET_MODE_MASK (SImode))) 1013 1014 /* Return the maximum number of consecutive registers 1015 needed to represent mode MODE in a register of class CLASS. */ 1016 /* On SPARC, this is the size of MODE in words. */ 1017 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1018 (FP_REG_CLASS_P (CLASS) ? (GET_MODE_SIZE (MODE) + 3) / 4 \ 1019 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1020 1021 /* Stack layout; function entry, exit and calling. */ 1022 1023 /* Define this if pushing a word on the stack 1024 makes the stack pointer a smaller address. */ 1025 #define STACK_GROWS_DOWNWARD 1 1026 1027 /* Define this to nonzero if the nominal address of the stack frame 1028 is at the high-address end of the local variables; 1029 that is, each additional local variable allocated 1030 goes at a more negative offset in the frame. */ 1031 #define FRAME_GROWS_DOWNWARD 1 1032 1033 /* Offset of first parameter from the argument pointer register value. 1034 !v9: This is 64 for the ins and locals, plus 4 for the struct-return reg 1035 even if this function isn't going to use it. 1036 v9: This is 128 for the ins and locals. */ 1037 #define FIRST_PARM_OFFSET(FNDECL) \ 1038 (TARGET_ARCH64 ? 16 * UNITS_PER_WORD : STRUCT_VALUE_OFFSET + UNITS_PER_WORD) 1039 1040 /* Offset from the argument pointer register value to the CFA. 1041 This is different from FIRST_PARM_OFFSET because the register window 1042 comes between the CFA and the arguments. */ 1043 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1044 1045 /* When a parameter is passed in a register, stack space is still 1046 allocated for it. 1047 !v9: All 6 possible integer registers have backing store allocated. 1048 v9: Only space for the arguments passed is allocated. */ 1049 /* ??? Ideally, we'd use zero here (as the minimum), but zero has special 1050 meaning to the backend. Further, we need to be able to detect if a 1051 varargs/unprototyped function is called, as they may want to spill more 1052 registers than we've provided space. Ugly, ugly. So for now we retain 1053 all 6 slots even for v9. */ 1054 #define REG_PARM_STACK_SPACE(DECL) (6 * UNITS_PER_WORD) 1055 1056 /* Definitions for register elimination. */ 1057 1058 #define ELIMINABLE_REGS \ 1059 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1060 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} } 1061 1062 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1063 do \ 1064 { \ 1065 (OFFSET) = sparc_initial_elimination_offset ((TO)); \ 1066 } \ 1067 while (0) 1068 1069 /* Keep the stack pointer constant throughout the function. 1070 This is both an optimization and a necessity: longjmp 1071 doesn't behave itself when the stack pointer moves within 1072 the function! */ 1073 #define ACCUMULATE_OUTGOING_ARGS 1 1074 1075 /* Define this macro if the target machine has "register windows". This 1076 C expression returns the register number as seen by the called function 1077 corresponding to register number OUT as seen by the calling function. 1078 Return OUT if register number OUT is not an outbound register. */ 1079 1080 #define INCOMING_REGNO(OUT) \ 1081 ((TARGET_FLAT || (OUT) < 8 || (OUT) > 15) ? (OUT) : (OUT) + 16) 1082 1083 /* Define this macro if the target machine has "register windows". This 1084 C expression returns the register number as seen by the calling function 1085 corresponding to register number IN as seen by the called function. 1086 Return IN if register number IN is not an inbound register. */ 1087 1088 #define OUTGOING_REGNO(IN) \ 1089 ((TARGET_FLAT || (IN) < 24 || (IN) > 31) ? (IN) : (IN) - 16) 1090 1091 /* Define this macro if the target machine has register windows. This 1092 C expression returns true if the register is call-saved but is in the 1093 register window. */ 1094 1095 #define LOCAL_REGNO(REGNO) \ 1096 (!TARGET_FLAT && (REGNO) >= 16 && (REGNO) <= 31) 1097 1098 /* Define the size of space to allocate for the return value of an 1099 untyped_call. */ 1100 1101 #define APPLY_RESULT_SIZE (TARGET_ARCH64 ? 24 : 16) 1102 1103 /* 1 if N is a possible register number for function argument passing. 1104 On SPARC, these are the "output" registers. v9 also uses %f0-%f31. */ 1105 1106 #define FUNCTION_ARG_REGNO_P(N) \ 1107 (((N) >= 8 && (N) <= 13) \ 1108 || (TARGET_ARCH64 && TARGET_FPU && (N) >= 32 && (N) <= 63)) 1109 1110 /* Define a data type for recording info about an argument list 1111 during the scan of that argument list. This data type should 1112 hold all necessary information about the function itself 1113 and about the args processed so far, enough to enable macros 1114 such as FUNCTION_ARG to determine where the next arg should go. 1115 1116 On SPARC (!v9), this is a single integer, which is a number of words 1117 of arguments scanned so far (including the invisible argument, 1118 if any, which holds the structure-value-address). 1119 Thus 7 or more means all following args should go on the stack. 1120 1121 For v9, we also need to know whether a prototype is present. */ 1122 1123 struct sparc_args { 1124 int words; /* number of words passed so far */ 1125 int prototype_p; /* nonzero if a prototype is present */ 1126 int libcall_p; /* nonzero if a library call */ 1127 }; 1128 #define CUMULATIVE_ARGS struct sparc_args 1129 1130 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1131 for a call to a function whose data type is FNTYPE. 1132 For a library call, FNTYPE is 0. */ 1133 1134 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1135 init_cumulative_args (& (CUM), (FNTYPE), (LIBNAME), (FNDECL)); 1136 1137 1138 /* Generate the special assembly code needed to tell the assembler whatever 1139 it might need to know about the return value of a function. 1140 1141 For SPARC assemblers, we need to output a .proc pseudo-op which conveys 1142 information to the assembler relating to peephole optimization (done in 1143 the assembler). */ 1144 1145 #define ASM_DECLARE_RESULT(FILE, RESULT) \ 1146 fprintf ((FILE), "\t.proc\t0%lo\n", sparc_type_code (TREE_TYPE (RESULT))) 1147 1148 /* Output the special assembly code needed to tell the assembler some 1149 register is used as global register variable. 1150 1151 SPARC 64bit psABI declares registers %g2 and %g3 as application 1152 registers and %g6 and %g7 as OS registers. Any object using them 1153 should declare (for %g2/%g3 has to, for %g6/%g7 can) that it uses them 1154 and how they are used (scratch or some global variable). 1155 Linker will then refuse to link together objects which use those 1156 registers incompatibly. 1157 1158 Unless the registers are used for scratch, two different global 1159 registers cannot be declared to the same name, so in the unlikely 1160 case of a global register variable occupying more than one register 1161 we prefix the second and following registers with .gnu.part1. etc. */ 1162 1163 extern GTY(()) char sparc_hard_reg_printed[8]; 1164 1165 #define ASM_DECLARE_REGISTER_GLOBAL(FILE, DECL, REGNO, NAME) \ 1166 do { \ 1167 if (TARGET_ARCH64) \ 1168 { \ 1169 int end = end_hard_regno (DECL_MODE (decl), REGNO); \ 1170 int reg; \ 1171 for (reg = (REGNO); reg < 8 && reg < end; reg++) \ 1172 if ((reg & ~1) == 2 || (reg & ~1) == 6) \ 1173 { \ 1174 if (reg == (REGNO)) \ 1175 fprintf ((FILE), "\t.register\t%%g%d, %s\n", reg, (NAME)); \ 1176 else \ 1177 fprintf ((FILE), "\t.register\t%%g%d, .gnu.part%d.%s\n", \ 1178 reg, reg - (REGNO), (NAME)); \ 1179 sparc_hard_reg_printed[reg] = 1; \ 1180 } \ 1181 } \ 1182 } while (0) 1183 1184 /* Emit rtl for profiling. */ 1185 #define PROFILE_HOOK(LABEL) sparc_profile_hook (LABEL) 1186 1187 /* All the work done in PROFILE_HOOK, but still required. */ 1188 #define FUNCTION_PROFILER(FILE, LABELNO) do { } while (0) 1189 1190 /* Set the name of the mcount function for the system. */ 1191 #define MCOUNT_FUNCTION "*mcount" 1192 1193 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1194 the stack pointer does not matter. The value is tested only in 1195 functions that have frame pointers. */ 1196 #define EXIT_IGNORE_STACK 1 1197 1198 /* Length in units of the trampoline for entering a nested function. */ 1199 #define TRAMPOLINE_SIZE (TARGET_ARCH64 ? 32 : 16) 1200 1201 /* Alignment required for trampolines, in bits. */ 1202 #define TRAMPOLINE_ALIGNMENT 128 1203 1204 /* Generate RTL to flush the register windows so as to make arbitrary frames 1205 available. */ 1206 #define SETUP_FRAME_ADDRESSES() \ 1207 do { \ 1208 if (!TARGET_FLAT) \ 1209 emit_insn (gen_flush_register_windows ());\ 1210 } while (0) 1211 1212 /* Given an rtx for the address of a frame, 1213 return an rtx for the address of the word in the frame 1214 that holds the dynamic chain--the previous frame's address. */ 1215 #define DYNAMIC_CHAIN_ADDRESS(frame) \ 1216 plus_constant (Pmode, frame, 14 * UNITS_PER_WORD + SPARC_STACK_BIAS) 1217 1218 /* Given an rtx for the frame pointer, 1219 return an rtx for the address of the frame. */ 1220 #define FRAME_ADDR_RTX(frame) plus_constant (Pmode, frame, SPARC_STACK_BIAS) 1221 1222 /* The return address isn't on the stack, it is in a register, so we can't 1223 access it from the current frame pointer. We can access it from the 1224 previous frame pointer though by reading a value from the register window 1225 save area. */ 1226 #define RETURN_ADDR_IN_PREVIOUS_FRAME 1 1227 1228 /* This is the offset of the return address to the true next instruction to be 1229 executed for the current function. */ 1230 #define RETURN_ADDR_OFFSET \ 1231 (8 + 4 * (! TARGET_ARCH64 && cfun->returns_struct)) 1232 1233 /* The current return address is in %i7. The return address of anything 1234 farther back is in the register window save area at [%fp+60]. */ 1235 /* ??? This ignores the fact that the actual return address is +8 for normal 1236 returns, and +12 for structure returns. */ 1237 #define RETURN_ADDR_REGNUM 31 1238 #define RETURN_ADDR_RTX(count, frame) \ 1239 ((count == -1) \ 1240 ? gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) \ 1241 : gen_rtx_MEM (Pmode, \ 1242 memory_address (Pmode, plus_constant (Pmode, frame, \ 1243 15 * UNITS_PER_WORD \ 1244 + SPARC_STACK_BIAS)))) 1245 1246 /* Before the prologue, the return address is %o7 + 8. OK, sometimes it's 1247 +12, but always using +8 is close enough for frame unwind purposes. 1248 Actually, just using %o7 is close enough for unwinding, but %o7+8 1249 is something you can return to. */ 1250 #define INCOMING_RETURN_ADDR_REGNUM 15 1251 #define INCOMING_RETURN_ADDR_RTX \ 1252 plus_constant (word_mode, \ 1253 gen_rtx_REG (word_mode, INCOMING_RETURN_ADDR_REGNUM), 8) 1254 #define DWARF_FRAME_RETURN_COLUMN \ 1255 DWARF_FRAME_REGNUM (INCOMING_RETURN_ADDR_REGNUM) 1256 1257 /* The offset from the incoming value of %sp to the top of the stack frame 1258 for the current function. On sparc64, we have to account for the stack 1259 bias if present. */ 1260 #define INCOMING_FRAME_SP_OFFSET SPARC_STACK_BIAS 1261 1262 /* Describe how we implement __builtin_eh_return. */ 1263 #define EH_RETURN_REGNUM 1 1264 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 24 : INVALID_REGNUM) 1265 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, EH_RETURN_REGNUM) 1266 1267 /* Define registers used by the epilogue and return instruction. */ 1268 #define EPILOGUE_USES(REGNO) \ 1269 ((REGNO) == RETURN_ADDR_REGNUM \ 1270 || (TARGET_FLAT \ 1271 && epilogue_completed \ 1272 && (REGNO) == INCOMING_RETURN_ADDR_REGNUM) \ 1273 || (crtl->calls_eh_return && (REGNO) == EH_RETURN_REGNUM)) 1274 1275 /* Select a format to encode pointers in exception handling data. CODE 1276 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1277 true if the symbol may be affected by dynamic relocations. 1278 1279 If assembler and linker properly support .uaword %r_disp32(foo), 1280 then use PC relative 32-bit relocations instead of absolute relocs 1281 for shared libraries. On sparc64, use pc relative 32-bit relocs even 1282 for binaries, to save memory. 1283 1284 binutils 2.12 would emit a R_SPARC_DISP32 dynamic relocation if the 1285 symbol %r_disp32() is against was not local, but .hidden. In that 1286 case, we have to use DW_EH_PE_absptr for pic personality. */ 1287 #ifdef HAVE_AS_SPARC_UA_PCREL 1288 #ifdef HAVE_AS_SPARC_UA_PCREL_HIDDEN 1289 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1290 (flag_pic \ 1291 ? (GLOBAL ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4\ 1292 : ((TARGET_ARCH64 && ! GLOBAL) \ 1293 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1294 : DW_EH_PE_absptr)) 1295 #else 1296 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 1297 (flag_pic \ 1298 ? (GLOBAL ? DW_EH_PE_absptr : (DW_EH_PE_pcrel | DW_EH_PE_sdata4)) \ 1299 : ((TARGET_ARCH64 && ! GLOBAL) \ 1300 ? (DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 1301 : DW_EH_PE_absptr)) 1302 #endif 1303 1304 /* Emit a PC-relative relocation. */ 1305 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 1306 do { \ 1307 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 1308 fprintf (FILE, "%%r_disp%d(", SIZE * 8); \ 1309 assemble_name (FILE, LABEL); \ 1310 fputc (')', FILE); \ 1311 } while (0) 1312 #endif 1313 1314 /* Addressing modes, and classification of registers for them. */ 1315 1316 /* Macros to check register numbers against specific register classes. */ 1317 1318 /* These assume that REGNO is a hard or pseudo reg number. 1319 They give nonzero only if REGNO is a hard reg of the suitable class 1320 or a pseudo reg currently allocated to a suitable hard reg. 1321 Since they use reg_renumber, they are safe only once reg_renumber 1322 has been allocated, which happens in reginfo.c during register 1323 allocation. */ 1324 1325 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1326 (SPARC_INT_REG_P (REGNO) || SPARC_INT_REG_P (reg_renumber[REGNO]) \ 1327 || (REGNO) == FRAME_POINTER_REGNUM \ 1328 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM) 1329 1330 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 1331 1332 #define REGNO_OK_FOR_FP_P(REGNO) \ 1333 (((unsigned) (REGNO) - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32)) \ 1334 || ((unsigned) reg_renumber[REGNO] - 32 < (TARGET_V9 ? (unsigned)64 : (unsigned)32))) 1335 1336 #define REGNO_OK_FOR_CCFP_P(REGNO) \ 1337 (TARGET_V9 \ 1338 && (((unsigned) (REGNO) - 96 < (unsigned)4) \ 1339 || ((unsigned) reg_renumber[REGNO] - 96 < (unsigned)4))) 1340 1341 /* Maximum number of registers that can appear in a valid memory address. */ 1342 1343 #define MAX_REGS_PER_ADDRESS 2 1344 1345 /* Recognize any constant value that is a valid address. 1346 When PIC, we do not accept an address that would require a scratch reg 1347 to load into a register. */ 1348 1349 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1350 1351 /* Define this, so that when PIC, reload won't try to reload invalid 1352 addresses which require two reload registers. */ 1353 1354 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1355 1356 /* Should gcc use [%reg+%lo(xx)+offset] addresses? */ 1357 1358 #ifdef HAVE_AS_OFFSETABLE_LO10 1359 #define USE_AS_OFFSETABLE_LO10 1 1360 #else 1361 #define USE_AS_OFFSETABLE_LO10 0 1362 #endif 1363 1364 /* Try a machine-dependent way of reloading an illegitimate address 1365 operand. If we find one, push the reload and jump to WIN. This 1366 macro is used in only one place: `find_reloads_address' in reload.c. */ 1367 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1368 do { \ 1369 int win; \ 1370 (X) = sparc_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1371 (int)(TYPE), (IND_LEVELS), &win); \ 1372 if (win) \ 1373 goto WIN; \ 1374 } while (0) 1375 1376 /* Specify the machine mode that this machine uses 1377 for the index in the tablejump instruction. */ 1378 /* If we ever implement any of the full models (such as CM_FULLANY), 1379 this has to be DImode in that case */ 1380 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1381 #define CASE_VECTOR_MODE \ 1382 (! TARGET_PTR64 ? SImode : flag_pic ? SImode : TARGET_CM_MEDLOW ? SImode : DImode) 1383 #else 1384 /* If assembler does not have working .subsection -1, we use DImode for pic, as otherwise 1385 we have to sign extend which slows things down. */ 1386 #define CASE_VECTOR_MODE \ 1387 (! TARGET_PTR64 ? SImode : flag_pic ? DImode : TARGET_CM_MEDLOW ? SImode : DImode) 1388 #endif 1389 1390 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1391 #define DEFAULT_SIGNED_CHAR 1 1392 1393 /* Max number of bytes we can move from memory to memory 1394 in one reasonably fast instruction. */ 1395 #define MOVE_MAX 8 1396 1397 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1398 move-instruction pairs, we will do a cpymem or libcall instead. */ 1399 1400 #define MOVE_RATIO(speed) ((speed) ? 8 : 3) 1401 1402 /* Define if operations between registers always perform the operation 1403 on the full register even if a narrower mode is specified. */ 1404 #define WORD_REGISTER_OPERATIONS 1 1405 1406 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1407 will either zero-extend or sign-extend. The value of this macro should 1408 be the code that says which one of the two operations is implicitly 1409 done, UNKNOWN if none. */ 1410 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1411 1412 /* Nonzero if access to memory by bytes is slow and undesirable. 1413 For RISC chips, it means that access to memory by bytes is no 1414 better than access by words when possible, so grab a whole word 1415 and maybe make use of that. */ 1416 #define SLOW_BYTE_ACCESS 1 1417 1418 /* Define this to be nonzero if shift instructions ignore all but the low-order 1419 few bits. */ 1420 #define SHIFT_COUNT_TRUNCATED 1 1421 1422 /* For SImode, we make sure the top 32-bits of the register are clear and 1423 then we subtract 32 from the lzd instruction result. */ 1424 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1425 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1426 1427 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1428 return the mode to be used for the comparison. For floating-point, 1429 CCFP[E]mode is used. CCNZmode should be used when the first operand 1430 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 1431 processing is needed. */ 1432 #define SELECT_CC_MODE(OP,X,Y) select_cc_mode ((OP), (X), (Y)) 1433 1434 /* Return nonzero if MODE implies a floating point inequality can be 1435 reversed. For SPARC this is always true because we have a full 1436 compliment of ordered and unordered comparisons, but until generic 1437 code knows how to reverse it correctly we keep the old definition. */ 1438 #define REVERSIBLE_CC_MODE(MODE) ((MODE) != CCFPEmode && (MODE) != CCFPmode) 1439 1440 /* A function address in a call instruction for indexing purposes. */ 1441 #define FUNCTION_MODE Pmode 1442 1443 /* Define this if addresses of constant functions 1444 shouldn't be put through pseudo regs where they can be cse'd. 1445 Desirable on machines where ordinary constants are expensive 1446 but a CALL with constant address is cheap. */ 1447 #define NO_FUNCTION_CSE 1 1448 1449 /* The _Q_* comparison libcalls return booleans. */ 1450 #define FLOAT_LIB_COMPARE_RETURNS_BOOL(MODE, COMPARISON) ((MODE) == TFmode) 1451 1452 /* Assume by default that the _Qp_* 64-bit libcalls are implemented such 1453 that the inputs are fully consumed before the output memory is clobbered. */ 1454 1455 #define TARGET_BUGGY_QP_LIB 0 1456 1457 /* Assume by default that we do not have the Solaris-specific conversion 1458 routines nor 64-bit integer multiply and divide routines. */ 1459 1460 #define SUN_CONVERSION_LIBFUNCS 0 1461 #define DITF_CONVERSION_LIBFUNCS 0 1462 #define SUN_INTEGER_MULTIPLY_64 0 1463 1464 /* A C expression for the cost of a branch instruction. A value of 1 1465 is the default; other values are interpreted relative to that. */ 1466 #define BRANCH_COST(SPEED_P, PREDICTABLE_P) \ 1467 (sparc_branch_cost (SPEED_P, PREDICTABLE_P)) 1468 1469 /* Control the assembler format that we output. */ 1470 1471 /* A C string constant describing how to begin a comment in the target 1472 assembler language. The compiler assumes that the comment will end at 1473 the end of the line. */ 1474 1475 #define ASM_COMMENT_START "!" 1476 1477 /* Output to assembler file text saying following lines 1478 may contain character constants, extra white space, comments, etc. */ 1479 1480 #define ASM_APP_ON "" 1481 1482 /* Output to assembler file text saying following lines 1483 no longer contain unusual constructs. */ 1484 1485 #define ASM_APP_OFF "" 1486 1487 /* How to refer to registers in assembler output. 1488 This sequence is indexed by compiler's hard-register-number (see above). */ 1489 1490 #define REGISTER_NAMES \ 1491 {"%g0", "%g1", "%g2", "%g3", "%g4", "%g5", "%g6", "%g7", \ 1492 "%o0", "%o1", "%o2", "%o3", "%o4", "%o5", "%sp", "%o7", \ 1493 "%l0", "%l1", "%l2", "%l3", "%l4", "%l5", "%l6", "%l7", \ 1494 "%i0", "%i1", "%i2", "%i3", "%i4", "%i5", "%fp", "%i7", \ 1495 "%f0", "%f1", "%f2", "%f3", "%f4", "%f5", "%f6", "%f7", \ 1496 "%f8", "%f9", "%f10", "%f11", "%f12", "%f13", "%f14", "%f15", \ 1497 "%f16", "%f17", "%f18", "%f19", "%f20", "%f21", "%f22", "%f23", \ 1498 "%f24", "%f25", "%f26", "%f27", "%f28", "%f29", "%f30", "%f31", \ 1499 "%f32", "%f33", "%f34", "%f35", "%f36", "%f37", "%f38", "%f39", \ 1500 "%f40", "%f41", "%f42", "%f43", "%f44", "%f45", "%f46", "%f47", \ 1501 "%f48", "%f49", "%f50", "%f51", "%f52", "%f53", "%f54", "%f55", \ 1502 "%f56", "%f57", "%f58", "%f59", "%f60", "%f61", "%f62", "%f63", \ 1503 "%fcc0", "%fcc1", "%fcc2", "%fcc3", "%icc", "%sfp", "%gsr" } 1504 1505 /* Define additional names for use in asm clobbers and asm declarations. */ 1506 1507 #define ADDITIONAL_REGISTER_NAMES \ 1508 {{"ccr", SPARC_ICC_REG}, {"cc", SPARC_ICC_REG}} 1509 1510 /* On Sun 4, this limit is 2048. We use 1000 to be safe, since the length 1511 can run past this up to a continuation point. Once we used 1500, but 1512 a single entry in C++ can run more than 500 bytes, due to the length of 1513 mangled symbol names. dbxout.c should really be fixed to do 1514 continuations when they are actually needed instead of trying to 1515 guess... */ 1516 #define DBX_CONTIN_LENGTH 1000 1517 1518 /* This is how to output a command to make the user-level label named NAME 1519 defined for reference from other files. */ 1520 1521 /* Globalizing directive for a label. */ 1522 #define GLOBAL_ASM_OP "\t.global " 1523 1524 /* The prefix to add to user-visible assembler symbols. */ 1525 1526 #define USER_LABEL_PREFIX "_" 1527 1528 /* This is how to store into the string LABEL 1529 the symbol_ref name of an internal numbered label where 1530 PREFIX is the class of label and NUM is the number within the class. 1531 This is suitable for output with `assemble_name'. */ 1532 1533 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1534 sprintf ((LABEL), "*%s%ld", (PREFIX), (long)(NUM)) 1535 1536 /* This is how we hook in and defer the case-vector until the end of 1537 the function. */ 1538 #define ASM_OUTPUT_ADDR_VEC(LAB,VEC) \ 1539 sparc_defer_case_vector ((LAB),(VEC), 0) 1540 1541 #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,VEC) \ 1542 sparc_defer_case_vector ((LAB),(VEC), 1) 1543 1544 /* This is how to output an element of a case-vector that is absolute. */ 1545 1546 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1547 do { \ 1548 char label[30]; \ 1549 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1550 if (CASE_VECTOR_MODE == SImode) \ 1551 fprintf (FILE, "\t.word\t"); \ 1552 else \ 1553 fprintf (FILE, "\t.xword\t"); \ 1554 assemble_name (FILE, label); \ 1555 fputc ('\n', FILE); \ 1556 } while (0) 1557 1558 /* This is how to output an element of a case-vector that is relative. 1559 (SPARC uses such vectors only when generating PIC.) */ 1560 1561 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1562 do { \ 1563 char label[30]; \ 1564 ASM_GENERATE_INTERNAL_LABEL (label, "L", (VALUE)); \ 1565 if (CASE_VECTOR_MODE == SImode) \ 1566 fprintf (FILE, "\t.word\t"); \ 1567 else \ 1568 fprintf (FILE, "\t.xword\t"); \ 1569 assemble_name (FILE, label); \ 1570 ASM_GENERATE_INTERNAL_LABEL (label, "L", (REL)); \ 1571 fputc ('-', FILE); \ 1572 assemble_name (FILE, label); \ 1573 fputc ('\n', FILE); \ 1574 } while (0) 1575 1576 /* This is what to output before and after case-vector (both 1577 relative and absolute). If .subsection -1 works, we put case-vectors 1578 at the beginning of the current section. */ 1579 1580 #ifdef HAVE_GAS_SUBSECTION_ORDERING 1581 1582 #define ASM_OUTPUT_ADDR_VEC_START(FILE) \ 1583 fprintf(FILE, "\t.subsection\t-1\n") 1584 1585 #define ASM_OUTPUT_ADDR_VEC_END(FILE) \ 1586 fprintf(FILE, "\t.previous\n") 1587 1588 #endif 1589 1590 /* This is how to output an assembler line 1591 that says to advance the location counter 1592 to a multiple of 2**LOG bytes. */ 1593 1594 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1595 if ((LOG) != 0) \ 1596 fprintf (FILE, "\t.align %d\n", (1 << (LOG))) 1597 1598 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1599 fprintf (FILE, "\t.skip " HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 1600 1601 /* This says how to output an assembler line 1602 to define a global common symbol. */ 1603 1604 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1605 ( fputs ("\t.common ", (FILE)), \ 1606 assemble_name ((FILE), (NAME)), \ 1607 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\"\n", (SIZE))) 1608 1609 /* This says how to output an assembler line to define a local common 1610 symbol. */ 1611 1612 #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ 1613 ( fputs ("\t.reserve ", (FILE)), \ 1614 assemble_name ((FILE), (NAME)), \ 1615 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",\"bss\",%u\n", \ 1616 (SIZE), ((ALIGNED) / BITS_PER_UNIT))) 1617 1618 /* A C statement (sans semicolon) to output to the stdio stream 1619 FILE the assembler definition of uninitialized global DECL named 1620 NAME whose size is SIZE bytes and alignment is ALIGN bytes. 1621 Try to use asm_output_aligned_bss to implement this macro. */ 1622 1623 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1624 do { \ 1625 ASM_OUTPUT_ALIGNED_LOCAL (FILE, NAME, SIZE, ALIGN); \ 1626 } while (0) 1627 1628 /* Output #ident as a .ident. */ 1629 1630 #undef TARGET_ASM_OUTPUT_IDENT 1631 #define TARGET_ASM_OUTPUT_IDENT default_asm_output_ident_directive 1632 1633 /* Prettify the assembly. */ 1634 1635 extern int sparc_indent_opcode; 1636 1637 #define ASM_OUTPUT_OPCODE(FILE, PTR) \ 1638 do { \ 1639 if (sparc_indent_opcode) \ 1640 { \ 1641 putc (' ', FILE); \ 1642 sparc_indent_opcode = 0; \ 1643 } \ 1644 } while (0) 1645 1646 /* TLS support defaulting to original Sun flavor. GNU extensions 1647 must be activated in separate configuration files. */ 1648 #ifdef HAVE_AS_TLS 1649 #define TARGET_TLS 1 1650 #else 1651 #define TARGET_TLS 0 1652 #endif 1653 1654 #define TARGET_SUN_TLS TARGET_TLS 1655 #define TARGET_GNU_TLS 0 1656 1657 #ifdef HAVE_AS_FMAF_HPC_VIS3 1658 #define AS_NIAGARA3_FLAG "d" 1659 #else 1660 #define AS_NIAGARA3_FLAG "b" 1661 #endif 1662 1663 #ifdef HAVE_AS_SPARC4 1664 #define AS_NIAGARA4_FLAG "-xarch=sparc4" 1665 #else 1666 #define AS_NIAGARA4_FLAG "-Av9" AS_NIAGARA3_FLAG 1667 #endif 1668 1669 #ifdef HAVE_AS_SPARC5_VIS4 1670 #define AS_NIAGARA7_FLAG "-xarch=sparc5" 1671 #else 1672 #define AS_NIAGARA7_FLAG AS_NIAGARA4_FLAG 1673 #endif 1674 1675 #ifdef HAVE_AS_SPARC6 1676 #define AS_M8_FLAG "-xarch=sparc6" 1677 #else 1678 #define AS_M8_FLAG AS_NIAGARA7_FLAG 1679 #endif 1680 1681 #ifdef HAVE_AS_LEON 1682 #define AS_LEON_FLAG "-Aleon" 1683 #define AS_LEONV7_FLAG "-Aleon" 1684 #else 1685 #define AS_LEON_FLAG "-Av8" 1686 #define AS_LEONV7_FLAG "-Av7" 1687 #endif 1688 1689 /* We use gcc _mcount for profiling. */ 1690 #define NO_PROFILE_COUNTERS 0 1691 1692 /* Debug support */ 1693 #define MASK_DEBUG_OPTIONS 0x01 /* debug option handling */ 1694 #define MASK_DEBUG_ALL MASK_DEBUG_OPTIONS 1695 1696 #define TARGET_DEBUG_OPTIONS (sparc_debug & MASK_DEBUG_OPTIONS) 1697 1698 /* By default, use the weakest memory model for the cpu. */ 1699 #ifndef SUBTARGET_DEFAULT_MEMORY_MODEL 1700 #define SUBTARGET_DEFAULT_MEMORY_MODEL SMM_DEFAULT 1701 #endif 1702 1703 /* Define this to 1 if the FE_EXCEPT values defined in fenv.h start at 1. */ 1704 #define SPARC_LOW_FE_EXCEPT_VALUES 0 1705 1706 #define TARGET_SUPPORTS_WIDE_INT 1 1707