1; 2; 3; Copyright (c) 2016 Roy Rankin 4; 5; This file is part of the gpsim regression tests 6; 7; This library is free software; you can redistribute it and/or 8; modify it under the terms of the GNU Lesser General Public 9; License as published by the Free Software Foundation; either 10; version 2.1 of the License, or (at your option) any later version. 11; 12; This library is distributed in the hope that it will be useful, 13; but WITHOUT ANY WARRANTY; without even the implied warranty of 14; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15; Lesser General Public License for more details. 16; 17; You should have received a copy of the GNU Lesser General Public 18; License along with this library; if not, see 19; <http://www.gnu.org/licenses/lgpl-2.1.html>. 20 21 22 list p=18f26k22 23 include <p18f26k22.inc> 24 include <coff.inc> 25 26 CONFIG WDTEN=ON 27 CONFIG WDTPS=128 28 CONFIG MCLRE = INTMCLR 29 CONFIG FOSC = INTIO67 30 31 32 33 errorlevel -302 34 radix dec 35 36;---------------------------------------------------------------------- 37;---------------------------------------------------------------------- 38GPR_DATA UDATA_SHR 0 39 40temp RES 1 41txif_int RES 1 42tx2if_int RES 1 43rcif_int RES 1 44rc2if_int RES 1 45 46;---------------------------------------------------------------------- 47; ********************* RESET VECTOR LOCATION ******************** 48;---------------------------------------------------------------------- 49RESET_VECTOR CODE 0x000 ; processor reset vector 50 bra start ; go to beginning of program 51 52 ;; 53 ;; Interrupt 54 ;; 55INTERRUPT_VECTOR CODE 0X008 56 57 goto interrupt 58 59;SPBRG : 3 : 1 Mbits/se 60;TXSTA : 10110000 (B0h) : 8-bit tran 61;RCSTA : 10010000 (90h) : 8-bit rece 62 63 64;******************************************* 65; Sample Code For Synchronous Mode 66;******************************************* 67 68#define ClkFreq 16000000 69#define baud(X) ((10*ClkFreq/(4*X))+5)/10 - 1 70#define TXSTA_INIT 0xB0 71#define RCTSA_INIT 0x90 72 73MAIN CODE 74 .sim "scope.ch0 = 'portc6'" 75 .sim "scope.ch1 = 'portc7'" 76 .sim "node clock data" 77 .sim "attach clock portc6 portb6" 78 .sim "attach data portc7 portb7" 79start 80 ;set clock to 16 Mhz 81 82 BANKSEL OSCCON 83 bsf OSCCON,6 84 85 clrf STATUS 86 BANKSEL ANSELA 87 clrf ANSELA ; set port to digital 88 clrf ANSELC 89 bsf TRISC,7 90 bsf TRISC,6 91 bsf TRISB,7 92 bsf TRISB,6 93 call RC_CREN_Master 94 call TXEN_Master 95 call RC_Master 96 call TX_Master 97 clrf RCSTA 98 clrf RCSTA2 99 100 .assert "'*** PASSED 18f26k22 synchronous euart'" 101 nop 102 103TXEN_Master: 104 call Setup_Sync_TXEN_Master_Mode 105 call Setup_Sync_RC_Slave_Mode 106 bsf RCSTA2,RX9 107 movlw 0x55 108 movwf TXREG 109 .assert("(txsta1 & 2) == 0, '*** FAILED p18f26k22 TXMT=0 after TXREG loaded and TXEN==0'" ) 110 nop 111 ; delay to check data not sent yet 112 decfsz WREG,W 113 goto $-1 114 .assert("(txsta1 & 2) == 0, '*** FAILED p18f26k22 TXMT=0 before TXEN==1'" ) 115 nop 116 .assert("(pir3 & 0x20) == 0, '*** FAILED p18f26k22 rc2if=0 before TXEN==1'" ) 117 nop 118 bsf TXSTA,TXEN 119 btfss TXSTA,TRMT 120 goto $-1 121 .assert("(pir3 & 0x20) == 0x20, '*** FAILED p18f26k22 rc2if=1 after TXEN==1'" ) 122 nop 123 .assert("(rcsta2 & 0x01) == 0x01, '*** FAILED p18f26k22 RX9D=1 after transfer'") 124 nop 125 movf RCREG2,W 126 .assert ("W == 0x55, '*** FAILED p18f26k22 rcreg 9 bit transfer'") 127 nop 128 return 129 130TX_Master: 131 call Setup_Sync_TX_Master_Mode 132 call Setup_Sync_RC_Slave_Mode 133 movlw (1<<CKTXP) 134 movwf BAUDCON 135 movwf BAUDCON2 136 movlw 0x55 137 movwf TXREG 138 btfss PIR1,TXIF 139 goto $-1 140 movlw 0xaa 141 movwf TXREG 142 btfss PIR1,TXIF 143 goto $-1 144 btfss PIR3,RC2IF 145 goto $-1 146 movf RCREG2,W 147 .assert "W == 0x55, 'p18f26k22 Sync M=tx S=rx clk invert char 1'" 148 nop 149 150 btfss TXSTA,TRMT 151 goto $-1 152 btfss PIR3,RC2IF 153 goto $-1 154 movf RCREG2,W 155 .assert "W == 0xaa, 'p18f26k22 Sync M=tx S=rx clk invert char 2'" 156 nop 157 return 158 159 160 161RC_Master: 162 call Setup_Sync_RC_Master_Mode 163 call Setup_Sync_TX_Slave_Mode 164 clrf BAUDCON 165 clrf BAUDCON2 166 movlw 0x55 167 movwf TXREG2 168 bsf RCSTA,SREN ;Start single character read 169 btfss PIR1,RC1IF 170 goto $-1 171 movf RCREG1,W 172 .assert "W == 0x55, 'p18f26k22 Sync M=rx S=tx char 1'" 173 nop 174 return 175 176RC_CREN_Master: 177 call Setup_Sync_RC_Master_Mode 178 call Setup_Sync_TX_Slave_Mode 179 clrf BAUDCON 180 clrf BAUDCON2 181 bsf INTCON,GIE 182 bsf INTCON,PEIE 183 movlw 0x55 184 movwf TXREG2 185 movlw (1<<SPEN) | (1<<CREN) ;Start continuous character read 186 movwf RCSTA 187 clrf rcif_int 188 bsf PIE1,RC1IE 189 btfss rcif_int,0 190 goto $-1 191 movf RCREG1,W 192 .assert "W == 0x55, 'p18f26k22 Sync M=rx(CREN) S=tx char 1'" 193 nop 194 btfss RCSTA,OERR 195 goto $-1 196 movf RCREG1,W ; this should not clear OERR, because CREN is set 197 .assert "(rcsta1 & 0x02) == 0x02,'p18f26k22 Sync M=rx(CREN) RCREG does not clean OERR'" 198 nop 199 bcf RCSTA,CREN 200 .assert "(rcsta1 & 0x02) == 0x00,'p18f26k22 Sync M=rx(CREN) CREN=0 does clean OERR'" 201 nop 202 bcf RCSTA,SPEN 203 .assert "(pir1 & 0x20) == 0x00,'p18f26k22 Sync M=rx(CREN) SPEN=0 does clean RCIF'" 204 nop 205 return 206 207Setup_Sync_TX_Master_Mode 208 movlb 0 209 movlw baud(1000000) 210 BANKSEL SPBRG 211 movwf SPBRG 212 movlw (1<<CSRC) | (1<<SYNC) 213 movwf TXSTA 214 movlw (1<<SPEN) 215 movwf RCSTA 216 bsf TXSTA,TXEN 217 return 218 219; Setup synchronous master mode 9 bits TXEN trigger output 220Setup_Sync_TXEN_Master_Mode 221 movlb 0 222 movlw baud(1000000) 223 BANKSEL SPBRG 224 movwf SPBRG 225 ; send 9 bits bit9=1 226 movlw (1<<CSRC) | (1<<SYNC) | (1<<TX9) | (1<<TX9D) 227 movwf TXSTA 228 movlw (1<<SPEN) 229 movwf RCSTA 230 return 231 232Setup_Sync_RC_Master_Mode 233 movlb 0 234 movlw baud(1000000) 235 BANKSEL SPBRG 236 movwf SPBRG 237 movlw (1<<CSRC) | (1<<SYNC) 238 movwf TXSTA 239 movlw (1<<SPEN) 240 movwf RCSTA 241 return 242 243Setup_Sync_RC_Slave_Mode: 244 movlb 0 245 movlw baud(1000000) 246 BANKSEL SPBRG 247 movwf SPBRG 248 movlw (1<<SYNC) 249 movwf TXSTA2 250 movlw (1<<SPEN) 251 movwf RCSTA2 252 bsf RCSTA2,CREN 253 return 254 255Setup_Sync_TX_Slave_Mode: 256 movlw (1<<SYNC) 257 movwf TXSTA2 258 movlw (1<<SPEN) ;RCSTA_INIT 259 movwf RCSTA2 260 bsf TXSTA2,TXEN 261 return 262 263interrupt: 264 265 movlb 0 ; BSR=0 266 267 movf PIR1,W 268 andwf PIE1,W 269 movwf temp 270 btfsc temp,TXIF 271 goto int_txif 272 btfsc temp,RCIF 273 goto int_rcif 274 movf PIR3,W 275 andwf PIE3,W 276 movwf temp 277 btfsc temp,TX2IF 278 goto int_tx2if 279 btfsc temp,RC2IF 280 goto int_rc2if 281 282 283 .assert "'FAILED 18F26k22 unexpected interrupt'" 284 nop 285 286back_interrupt: 287 retfie 1 288 289int_txif: 290 bsf txif_int,0 291 bcf PIE1,TX1IE 292 goto back_interrupt 293 294int_tx2if: 295 bsf tx2if_int,0 296 bcf PIE3,TX2IE 297 goto back_interrupt 298 299int_rcif: 300 bsf rcif_int,0 301 bcf PIE1,RC1IE 302 goto back_interrupt 303 304int_rc2if: 305 bsf rc2if_int,0 306 bcf PIE3,RC2IE 307 goto back_interrupt 308 309 end 310