1        ;; tmr3_16bit.asm
2        ;;
3        ;; The purpose of this program is to test how well gpsim can simulate
4        ;; TMR1 for a 16bit-core pic (like the 18fxxx family) although
5	;; most of the functionality is generic to all processors where
6	;; t1mer1 supports an external clock source.
7	;;
8        ;; Here are the tests performed:
9	;;
10	;; -- TMR3 count seconds when driven by simulated external crystal
11	;; -- TMR3 driven Fosc/4 with prescale of 8
12	;; -- TMR3 count seconds when driven by external stimuli
13	;; -- TMR3L and TMR3H can be read and written
14
15	list    p=18f452                ; list directive to define processor
16	include <p18f452.inc>           ; processor specific variable definitions
17        include <coff.inc>              ; Grab some useful macros
18        radix   dec                     ; Numbers are assumed to be decimal
19
20
21
22;----------------------------------------------------------------------
23
24; Printf Command
25.command macro x
26  .direct "C", x
27  endm
28
29;----------------------------------------------------------------------
30GPR_DATA                UDATA
31temp            RES     1
32temp1           RES     1
33temp2           RES     1
34failures        RES     1
35
36TMR0_RollOver	RES	1
37TMR3_RollOver	RES	1
38countLo		RES	1
39countHi		RES	1
40TMR3H_Sampled	RES	1
41TMR3H_Last	RES	1
42SecondsLo	RES	1
43SecondsHi	RES	1
44
45  GLOBAL countLo, countHi
46  GLOBAL SecondsLo, SecondsHi
47
48;----------------------------------------------------------------------
49;   ******************* MAIN CODE START LOCATION  ******************
50;----------------------------------------------------------------------
51STARTUP    CODE	0
52
53	bra	Start
54
55
56;------------------------------------------------------------------------
57;
58;  Interrupt Vector
59;
60;------------------------------------------------------------------------
61
62INT_VECTOR   CODE    0x008               ; interrupt vector location
63
64
65check_TMR0_interrupt:
66
67
68    ;;==================
69    ;; TMR3 Interrupt
70    ;;==================
71
72	BTFSC	INTCON,T0IF		;If the roll over flag is not set
73	 BTFSS	INTCON,T0IE		;or the interrupt is not enabled
74	  bra   checkTMR0IntEnd         ;
75
76    ;; TMR0 has rolled over. Clear the pending interrupt and notify
77    ;; the foreground code by incrementing the "roll over" counter
78    ;; Notice that the increment operation is atomic - this means
79    ;; we won't have to worry about the foreground code and interrupt
80    ;; code clashing over accesses to this variable.
81
82        BCF     INTCON,T0IF,0           ; Clear the pending interrupt
83        INCF    TMR0_RollOver,F         ; Set a flag to indicate rollover
84
85checkTMR0IntEnd:
86
87    ;;==================
88    ;; TMR3 Interrupt
89    ;;==================
90	BTFSC	PIR2,TMR3IF
91	 BTFSS	PIE2,TMR3IE
92	  BRA	checkTMR3IntEnd
93
94	BCF	PIR2,TMR3IF		;Clear the interrupt
95	INCF	TMR3_RollOver,F		;Set a flag
96	BSF     TMR3H, 7     		; Preload for 1 sec overflow
97
98   ; Note, since we have a 32768 Hz crystal tied to TMR3 and we have the timer
99   ; configured as a 16-bit timer TMR3H loaded with 0x80, then this interrupt
100   ; will happen once every second.
101
102	INFSNZ	SecondsLo,F		;Update the system time.
103	 INCF	SecondsHi,F
104
105
106	CLRF	TMR3H_Sampled
107	CLRF	TMR3H_Last
108checkTMR3IntEnd:
109
110ExitInterrupt:
111	RETFIE	1
112
113
114MAIN	CODE
115
116Start:
117
118  ;------------------------------------------------------------------------
119  ;
120  ; Embedded simulation scripts
121  ;
122  ; Set the clock frequency to 10MHz
123
124  .sim "frequency 10e6"
125
126
127  ; define a stimulus to generate a 32kHz clock. This will be tied
128  ; to TMR3's input and is used to simulate an external drive.
129  ;
130  ; 40MHz
131  ;   Instruction Rate = (4 clks/instruction) / (10e6 clks/second)
132  ;                    = 400nS per instruction
133  ;  32.768kHz ==> 30.517uS period
134  ;  Instruction Cycles/32.768kHz cycle = 30.517uS / .4uS
135  ;                                     = 76.2925 instructions
136  ;
137
138  .sim "stimulus asynchronous_stimulus "
139  .sim "initial_state 0"
140  .sim "start_cycle 0x2008130"
141  .sim "period 305"
142  .sim "{ 38,1 ,  76,0 , 114,1 , 152,0 , 190,1 , 228,0 , 266,1}"
143  .sim "name Clk32kHz"
144  .sim "end"
145
146  ; Create a node
147
148  .sim "node clk_node"
149
150  ; attach the clock
151
152  .sim "attach clk_node  Clk32kHz portc0"
153
154
155
156  ; At reset, all bits of t1Con should be clear.
157  .assert "t1con == 0x00"
158
159	MOVLW	(1<<RC0)|(1<<RC1)  ;The lower two bits of PORTC are for
160	IORWF	TRISC,F		   ;the 32kHz oscillator and should be inputs
161
162	; Load TMR3H, TMR3L with 0x8000 for one second interupts
163	CLRF	TMR3L
164	MOVLW	0x80
165	MOVWF	TMR3H
166
167	BCF	PIR1,TMR3IF	;Clear any TMR3 pending interrupt
168	BSF	PIE2,TMR3IE	;Enable TMR3 interrupts
169	BSF	INTCON,PEIE	;Enable Peripheral interrupts
170	BSF	INTCON,GIE	;Enable Global interrupts
171
172  ; TMR3 not running yet, TMR3H and TMR3L should be unchanged
173	MOVF	TMR3L,W		; test read
174   .assert "W==0, '*** FAILED 16bit-core TMR3 test TMR3L read'"
175	nop
176	MOVF	TMR3H,W
177   .assert "W==0x80, '*** FAILED 16bit-core TMR3 test TMR3H read'"
178	nop
179
180  ; Simulate crystal oscillator for TMR1 external source
181  ;
182	MOVLW	( (1<<T1OSCEN) | (1<<TMR1CS) )
183	MOVWF	T1CON
184        MOVLW   (1<<TMR3CS) | (1<<TMR3ON)
185        MOVWF	T3CON
186
187	; Delay 16,793,733 about 6.7 seconds with TMR3 counting seconds
188	clrf	countLo
189	MOVLW	0x10
190	MOVWF	countHi
191L1:	clrwdt
192	rcall	d1
193	decfsz	countLo,F
194	 bra	L1
195	decfsz	countHi,F
196	 bra	L1
197
198   .assert "(SecondsLo==6), '*** FAILED 16bit-core TMR3 test bad count with crystal'"
199	nop
200test2:
201	nop
202
203  ; TMR3 on Fosc/4 with prescale of 8
204  ;
205	; Load TMR3H, TMR3L with 0x8000 for one second interupts
206;	BCF	T1CON,TMR3ON ; Microchip recommend stopping couter for writes
207	CLRF	TMR3L
208	MOVLW	0x80
209	MOVWF	TMR3H
210	CLRF	SecondsLo
211
212	CLRF	T1CON
213        MOVLW	(1<<T3CKPS1) | (1<<T3CKPS0) | (1<<TMR3ON)
214	MOVWF	T3CON
215
216	; Delay 16,793,733 cycles period 32768 * 8 gives 64 counts
217	clrf	countLo
218	MOVLW	0x10
219	MOVWF	countHi
220L2:	clrwdt
221	rcall	d1
222	decfsz	countLo,F
223	 bra	L2
224	decfsz	countHi,F
225	 bra	L2
226
227   .assert "(SecondsLo==64), '*** FAILED 16bit-core TMR3 test bad count with crystal'"
228	nop
229
230test3:
231	nop
232	CLRF	SecondsLo
233  ; External Stimulus for TMR3
234	MOVLW	((1<<TMR1CS) | (1<<TMR3ON))
235	MOVWF	T3CON
236	nop
237
238	; Delay 33587476 cycles, 13.4 seconds with TMR3 counting seconds
239	MOVLW	0x20
240	MOVWF	countHi
241L3:	clrwdt
242	rcall	d1
243	decfsz	countLo,F
244	 bra	L3
245	decfsz	countHi,F
246	 bra	L3
247
248   .assert "SecondsLo == 13, '*** FAILED 16bit-core TMR3 test bad count with stimuli'"
249	nop
250done:
251  .assert  "'*** PASSED 16bit-core TMR3 test'"
252        bra     $
253
254failed:
255        movlw   1
256        movwf   failures
257  .assert  "'*** FAILED 16bit-core TMR3 test'"
258        bra     done
259
260d1	RCALL	d2
261d2	RCALL	d3
262d3	RCALL	d4
263d4	RCALL	d5
264d5	RCALL	d6
265d6	RCALL	d7
266d7	RCALL	d8
267d8	RCALL	d9
268d9	RCALL	d10
269d10	RCALL	d11
270d11	RETURN
271
272 end
273