1 /* $NetBSD: ninjascsi32.c,v 1.24 2013/09/14 21:52:49 martin Exp $ */
2
3 /*-
4 * Copyright (c) 2004, 2006, 2007 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by ITOH Yasufumi.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #include <sys/cdefs.h>
33 __KERNEL_RCSID(0, "$NetBSD: ninjascsi32.c,v 1.24 2013/09/14 21:52:49 martin Exp $");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/callout.h>
38 #include <sys/device.h>
39 #include <sys/kernel.h>
40 #include <sys/buf.h>
41 #include <sys/scsiio.h>
42 #include <sys/proc.h>
43
44 #include <sys/bus.h>
45 #include <sys/intr.h>
46
47 #include <dev/scsipi/scsi_all.h>
48 #include <dev/scsipi/scsipi_all.h>
49 #include <dev/scsipi/scsiconf.h>
50 #include <dev/scsipi/scsi_message.h>
51
52 /*
53 * DualEdge transfer support
54 */
55 /* #define NJSC32_DUALEDGE */ /* XXX untested */
56
57 /*
58 * Auto param loading does not work properly (it partially works (works on
59 * start, doesn't on restart) on rev 0x54, it doesn't work at all on rev 0x51),
60 * and it doesn't improve the performance so much,
61 * forget about it.
62 */
63 #undef NJSC32_AUTOPARAM
64
65 #include <dev/ic/ninjascsi32reg.h>
66 #include <dev/ic/ninjascsi32var.h>
67
68 /* #define NJSC32_DEBUG */
69 /* #define NJSC32_TRACE */
70
71 #ifdef NJSC32_DEBUG
72 #define DPRINTF(x) printf x
73 #define DPRINTC(cmd, x) PRINTC(cmd, x)
74 #else
75 #define DPRINTF(x)
76 #define DPRINTC(cmd, x)
77 #endif
78 #ifdef NJSC32_TRACE
79 #define TPRINTF(x) printf x
80 #define TPRINTC(cmd, x) PRINTC(cmd, x)
81 #else
82 #define TPRINTF(x)
83 #define TPRINTC(cmd, x)
84 #endif
85
86 #define PRINTC(cmd, x) do { \
87 scsi_print_addr((cmd)->c_xs->xs_periph); \
88 printf x; \
89 } while (/* CONSTCOND */ 0)
90
91 static void njsc32_scsipi_request(struct scsipi_channel *,
92 scsipi_adapter_req_t, void *);
93 static void njsc32_scsipi_minphys(struct buf *);
94 static int njsc32_scsipi_ioctl(struct scsipi_channel *, u_long, void *,
95 int, struct proc *);
96
97 static void njsc32_init(struct njsc32_softc *, int nosleep);
98 static int njsc32_init_cmds(struct njsc32_softc *);
99 static void njsc32_target_async(struct njsc32_softc *,
100 struct njsc32_target *);
101 static void njsc32_init_targets(struct njsc32_softc *);
102 static void njsc32_add_msgout(struct njsc32_softc *, int);
103 static u_int32_t njsc32_get_auto_msgout(struct njsc32_softc *);
104 #ifdef NJSC32_DUALEDGE
105 static void njsc32_msgout_wdtr(struct njsc32_softc *, int);
106 #endif
107 static void njsc32_msgout_sdtr(struct njsc32_softc *, int period,
108 int offset);
109 static void njsc32_negotiate_xfer(struct njsc32_softc *,
110 struct njsc32_target *);
111 static void njsc32_arbitration_failed(struct njsc32_softc *);
112 static void njsc32_start(struct njsc32_softc *);
113 static void njsc32_run_xfer(struct njsc32_softc *, struct scsipi_xfer *);
114 static void njsc32_end_cmd(struct njsc32_softc *, struct njsc32_cmd *,
115 scsipi_xfer_result_t);
116 static void njsc32_wait_reset_release(void *);
117 static void njsc32_reset_bus(struct njsc32_softc *);
118 static void njsc32_clear_cmds(struct njsc32_softc *,
119 scsipi_xfer_result_t);
120 static void njsc32_set_ptr(struct njsc32_softc *, struct njsc32_cmd *,
121 u_int32_t);
122 static void njsc32_assert_ack(struct njsc32_softc *);
123 static void njsc32_negate_ack(struct njsc32_softc *);
124 static void njsc32_wait_req_negate(struct njsc32_softc *);
125 static void njsc32_reconnect(struct njsc32_softc *, struct njsc32_cmd *);
126 enum njsc32_reselstat {
127 NJSC32_RESEL_ERROR, /* to be rejected */
128 NJSC32_RESEL_COMPLETE, /* reselection is just complete */
129 NJSC32_RESEL_THROUGH /* this message is OK (no reply) */
130 };
131 static enum njsc32_reselstat njsc32_resel_identify(struct njsc32_softc *,
132 int lun, struct njsc32_cmd **);
133 static enum njsc32_reselstat njsc32_resel_tag(struct njsc32_softc *,
134 int tag, struct njsc32_cmd **);
135 static void njsc32_cmd_reload(struct njsc32_softc *, struct njsc32_cmd *,
136 int);
137 static void njsc32_update_xfer_mode(struct njsc32_softc *,
138 struct njsc32_target *);
139 static void njsc32_msgin(struct njsc32_softc *);
140 static void njsc32_msgout(struct njsc32_softc *);
141 static void njsc32_cmdtimeout(void *);
142 static void njsc32_reseltimeout(void *);
143
144 static inline unsigned
njsc32_read_1(struct njsc32_softc * sc,int no)145 njsc32_read_1(struct njsc32_softc *sc, int no)
146 {
147
148 return bus_space_read_1(sc->sc_regt, sc->sc_regh, no);
149 }
150
151 static inline unsigned
njsc32_read_2(struct njsc32_softc * sc,int no)152 njsc32_read_2(struct njsc32_softc *sc, int no)
153 {
154
155 return bus_space_read_2(sc->sc_regt, sc->sc_regh, no);
156 }
157
158 static inline u_int32_t
njsc32_read_4(struct njsc32_softc * sc,int no)159 njsc32_read_4(struct njsc32_softc *sc, int no)
160 {
161
162 return bus_space_read_4(sc->sc_regt, sc->sc_regh, no);
163 }
164
165 static inline void
njsc32_write_1(struct njsc32_softc * sc,int no,int val)166 njsc32_write_1(struct njsc32_softc *sc, int no, int val)
167 {
168
169 bus_space_write_1(sc->sc_regt, sc->sc_regh, no, val);
170 }
171
172 static inline void
njsc32_write_2(struct njsc32_softc * sc,int no,int val)173 njsc32_write_2(struct njsc32_softc *sc, int no, int val)
174 {
175
176 bus_space_write_2(sc->sc_regt, sc->sc_regh, no, val);
177 }
178
179 static inline void
njsc32_write_4(struct njsc32_softc * sc,int no,u_int32_t val)180 njsc32_write_4(struct njsc32_softc *sc, int no, u_int32_t val)
181 {
182
183 bus_space_write_4(sc->sc_regt, sc->sc_regh, no, val);
184 }
185
186 static inline unsigned
njsc32_ireg_read_1(struct njsc32_softc * sc,int no)187 njsc32_ireg_read_1(struct njsc32_softc *sc, int no)
188 {
189
190 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
191 return bus_space_read_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW);
192 }
193
194 static inline void
njsc32_ireg_write_1(struct njsc32_softc * sc,int no,int val)195 njsc32_ireg_write_1(struct njsc32_softc *sc, int no, int val)
196 {
197
198 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
199 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val);
200 }
201
202 static inline void
njsc32_ireg_write_2(struct njsc32_softc * sc,int no,int val)203 njsc32_ireg_write_2(struct njsc32_softc *sc, int no, int val)
204 {
205
206 bus_space_write_1(sc->sc_regt, sc->sc_regh, NJSC32_REG_INDEX, no);
207 bus_space_write_2(sc->sc_regt, sc->sc_regh, NJSC32_REG_DATA_LOW, val);
208 }
209
210 #define NS(ns) ((ns) / 4) /* nanosecond (>= 50) -> sync value */
211 #ifdef __STDC__
212 # define ACKW(n) NJSC32_ACK_WIDTH_ ## n ## CLK
213 # define SMPL(n) (NJSC32_SREQ_SAMPLING_ ## n ## CLK | \
214 NJSC32_SREQ_SAMPLING_ENABLE)
215 #else
216 # define ACKW(n) NJSC32_ACK_WIDTH_/**/n/**/CLK
217 # define SMPL(n) (NJSC32_SREQ_SAMPLING_/**/n/**/CLK | \
218 NJSC32_SREQ_SAMPLING_ENABLE)
219 #endif
220
221 #define NJSC32_NSYNCT_MAXSYNC 1
222 #define NJSC32_NSYNCT 16
223
224 /* 40MHz (25ns) */
225 static const struct njsc32_sync_param njsc32_synct_40M[NJSC32_NSYNCT] = {
226 { 0, 0, 0 }, /* dummy for async */
227 { NS( 50), ACKW(1), 0 }, /* 20.0 : 50ns, 25ns */
228 { NS( 75), ACKW(1), SMPL(1) }, /* 13.3 : 75ns, 25ns */
229 { NS(100), ACKW(2), SMPL(1) }, /* 10.0 : 100ns, 50ns */
230 { NS(125), ACKW(2), SMPL(2) }, /* 8.0 : 125ns, 50ns */
231 { NS(150), ACKW(3), SMPL(2) }, /* 6.7 : 150ns, 75ns */
232 { NS(175), ACKW(3), SMPL(2) }, /* 5.7 : 175ns, 75ns */
233 { NS(200), ACKW(4), SMPL(2) }, /* 5.0 : 200ns, 100ns */
234 { NS(225), ACKW(4), SMPL(4) }, /* 4.4 : 225ns, 100ns */
235 { NS(250), ACKW(4), SMPL(4) }, /* 4.0 : 250ns, 100ns */
236 { NS(275), ACKW(4), SMPL(4) }, /* 3.64: 275ns, 100ns */
237 { NS(300), ACKW(4), SMPL(4) }, /* 3.33: 300ns, 100ns */
238 { NS(325), ACKW(4), SMPL(4) }, /* 3.01: 325ns, 100ns */
239 { NS(350), ACKW(4), SMPL(4) }, /* 2.86: 350ns, 100ns */
240 { NS(375), ACKW(4), SMPL(4) }, /* 2.67: 375ns, 100ns */
241 { NS(400), ACKW(4), SMPL(4) } /* 2.50: 400ns, 100ns */
242 };
243
244 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS
245 /* 20MHz (50ns) */
246 static const struct njsc32_sync_param njsc32_synct_20M[NJSC32_NSYNCT] = {
247 { 0, 0, 0 }, /* dummy for async */
248 { NS(100), ACKW(1), 0 }, /* 10.0 : 100ns, 50ns */
249 { NS(150), ACKW(1), SMPL(2) }, /* 6.7 : 150ns, 50ns */
250 { NS(200), ACKW(2), SMPL(2) }, /* 5.0 : 200ns, 100ns */
251 { NS(250), ACKW(2), SMPL(4) }, /* 4.0 : 250ns, 100ns */
252 { NS(300), ACKW(3), SMPL(4) }, /* 3.3 : 300ns, 150ns */
253 { NS(350), ACKW(3), SMPL(4) }, /* 2.8 : 350ns, 150ns */
254 { NS(400), ACKW(4), SMPL(4) }, /* 2.5 : 400ns, 200ns */
255 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 200ns */
256 { NS(500), ACKW(4), SMPL(4) }, /* 2.0 : 500ns, 200ns */
257 { NS(550), ACKW(4), SMPL(4) }, /* 1.82: 550ns, 200ns */
258 { NS(600), ACKW(4), SMPL(4) }, /* 1.67: 600ns, 200ns */
259 { NS(650), ACKW(4), SMPL(4) }, /* 1.54: 650ns, 200ns */
260 { NS(700), ACKW(4), SMPL(4) }, /* 1.43: 700ns, 200ns */
261 { NS(750), ACKW(4), SMPL(4) }, /* 1.33: 750ns, 200ns */
262 { NS(800), ACKW(4), SMPL(4) } /* 1.25: 800ns, 200ns */
263 };
264
265 /* 33.3MHz (30ns) */
266 static const struct njsc32_sync_param njsc32_synct_pci[NJSC32_NSYNCT] = {
267 { 0, 0, 0 }, /* dummy for async */
268 { NS( 60), ACKW(1), 0 }, /* 16.6 : 60ns, 30ns */
269 { NS( 90), ACKW(1), SMPL(1) }, /* 11.1 : 90ns, 30ns */
270 { NS(120), ACKW(2), SMPL(2) }, /* 8.3 : 120ns, 60ns */
271 { NS(150), ACKW(2), SMPL(2) }, /* 6.7 : 150ns, 60ns */
272 { NS(180), ACKW(3), SMPL(2) }, /* 5.6 : 180ns, 90ns */
273 { NS(210), ACKW(3), SMPL(4) }, /* 4.8 : 210ns, 90ns */
274 { NS(240), ACKW(4), SMPL(4) }, /* 4.2 : 240ns, 120ns */
275 { NS(270), ACKW(4), SMPL(4) }, /* 3.7 : 270ns, 120ns */
276 { NS(300), ACKW(4), SMPL(4) }, /* 3.3 : 300ns, 120ns */
277 { NS(330), ACKW(4), SMPL(4) }, /* 3.0 : 330ns, 120ns */
278 { NS(360), ACKW(4), SMPL(4) }, /* 2.8 : 360ns, 120ns */
279 { NS(390), ACKW(4), SMPL(4) }, /* 2.6 : 390ns, 120ns */
280 { NS(420), ACKW(4), SMPL(4) }, /* 2.4 : 420ns, 120ns */
281 { NS(450), ACKW(4), SMPL(4) }, /* 2.2 : 450ns, 120ns */
282 { NS(480), ACKW(4), SMPL(4) } /* 2.1 : 480ns, 120ns */
283 };
284 #endif /* NJSC32_SUPPORT_OTHER_CLOCKS */
285
286 #undef NS
287 #undef ACKW
288 #undef SMPL
289
290 /* initialize device */
291 static void
njsc32_init(struct njsc32_softc * sc,int nosleep)292 njsc32_init(struct njsc32_softc *sc, int nosleep)
293 {
294 u_int16_t intstat;
295 int i;
296
297 /* block all interrupts */
298 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
299
300 /* clear transfer */
301 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
302 njsc32_write_4(sc, NJSC32_REG_BM_CNT, 0);
303
304 /* make sure interrupts are cleared */
305 for (i = 0; ((intstat = njsc32_read_2(sc, NJSC32_REG_IRQ))
306 & NJSC32_IRQ_INTR_PENDING) && i < 5 /* just not forever */; i++) {
307 DPRINTF(("%s: njsc32_init: intr pending: %#x\n",
308 device_xname(sc->sc_dev), intstat));
309 }
310
311 /* FIFO threshold */
312 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_FULL,
313 NJSC32_FIFO_FULL_BUSMASTER);
314 njsc32_ireg_write_1(sc, NJSC32_IREG_FIFO_THRESHOLD_EMPTY,
315 NJSC32_FIFO_EMPTY_BUSMASTER);
316
317 /* clock source */
318 njsc32_ireg_write_1(sc, NJSC32_IREG_CLOCK, sc->sc_clk);
319
320 /* memory read multiple */
321 njsc32_ireg_write_1(sc, NJSC32_IREG_BM,
322 NJSC32_BM_MEMRD_CMD1 | NJSC32_BM_SGT_AUTO_PARA_MEMRD_CMD);
323
324 /* clear parity error and enable parity detection */
325 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
326 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR);
327
328 /* misc configuration */
329 njsc32_ireg_write_2(sc, NJSC32_IREG_MISC,
330 NJSC32_MISC_SCSI_DIRECTION_DETECTOR_SELECT |
331 NJSC32_MISC_DELAYED_BMSTART |
332 NJSC32_MISC_MASTER_TERMINATION_SELECT |
333 NJSC32_MISC_BMREQ_NEGATE_TIMING_SEL |
334 NJSC32_MISC_AUTOSEL_TIMING_SEL |
335 NJSC32_MISC_BMSTOP_CHANGE2_NONDATA_PHASE);
336
337 /*
338 * Check for termination power (32Bi and some versions of 32UDE).
339 */
340 if (!nosleep || cold) {
341 DPRINTF(("%s: njsc32_init: checking TERMPWR\n",
342 device_xname(sc->sc_dev)));
343
344 /* First, turn termination power off */
345 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR, 0);
346
347 /* give 0.5s to settle */
348 if (nosleep)
349 delay(500000);
350 else
351 tsleep(sc, PWAIT, "njs_t1", hz / 2);
352 }
353
354 /* supply termination power if not supplied by other devices */
355 if ((njsc32_ireg_read_1(sc, NJSC32_IREG_TERM_PWR) &
356 NJSC32_TERMPWR_SENSE) == 0) {
357 /* termination power is not present on the bus */
358 if (sc->sc_flags & NJSC32_CANNOT_SUPPLY_TERMPWR) {
359 /*
360 * CardBus device must not supply termination power
361 * to avoid excessive power consumption.
362 */
363 printf("%s: no termination power present\n",
364 device_xname(sc->sc_dev));
365 } else {
366 /* supply termination power */
367 njsc32_ireg_write_1(sc, NJSC32_IREG_TERM_PWR,
368 NJSC32_TERMPWR_BPWR);
369
370 DPRINTF(("%s: supplying termination power\n",
371 device_xname(sc->sc_dev)));
372
373 /* give 0.5s to settle */
374 if (!nosleep)
375 tsleep(sc, PWAIT, "njs_t2", hz / 2);
376 }
377 }
378
379 /* stop timer */
380 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
381 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
382
383 /* default transfer parameter */
384 njsc32_write_1(sc, NJSC32_REG_SYNC, 0);
385 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, NJSC32_ACK_WIDTH_1CLK);
386 njsc32_write_2(sc, NJSC32_REG_SEL_TIMEOUT,
387 NJSC32_SEL_TIMEOUT_TIME);
388
389 /* select interrupt source */
390 njsc32_ireg_write_2(sc, NJSC32_IREG_IRQ_SELECT,
391 NJSC32_IRQSEL_RESELECT |
392 NJSC32_IRQSEL_PHASE_CHANGE |
393 NJSC32_IRQSEL_SCSIRESET |
394 NJSC32_IRQSEL_TIMER |
395 NJSC32_IRQSEL_FIFO_THRESHOLD |
396 NJSC32_IRQSEL_TARGET_ABORT |
397 NJSC32_IRQSEL_MASTER_ABORT |
398 /* XXX not yet
399 NJSC32_IRQSEL_SERR |
400 NJSC32_IRQSEL_PERR |
401 NJSC32_IRQSEL_BMCNTERR |
402 */
403 NJSC32_IRQSEL_AUTO_SCSI_SEQ);
404
405 /* interrupts will be unblocked later after bus reset */
406
407 /* turn LED off */
408 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT_DDR,
409 NJSC32_EXTPORT_LED_OFF);
410 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT,
411 NJSC32_EXTPORT_LED_OFF);
412
413 /* reset SCSI bus so the targets become known state */
414 njsc32_reset_bus(sc);
415 }
416
417 static int
njsc32_init_cmds(struct njsc32_softc * sc)418 njsc32_init_cmds(struct njsc32_softc *sc)
419 {
420 struct njsc32_cmd *cmd;
421 bus_addr_t dmaaddr;
422 int i, error;
423
424 /*
425 * allocate DMA area for command
426 */
427 if ((error = bus_dmamem_alloc(sc->sc_dmat,
428 sizeof(struct njsc32_dma_page), PAGE_SIZE, 0,
429 &sc->sc_cmdpg_seg, 1, &sc->sc_cmdpg_nsegs, BUS_DMA_NOWAIT)) != 0) {
430 aprint_error_dev(sc->sc_dev,
431 "unable to allocate cmd page, error = %d\n",
432 error);
433 return 0;
434 }
435 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_cmdpg_seg,
436 sc->sc_cmdpg_nsegs, sizeof(struct njsc32_dma_page),
437 (void **)&sc->sc_cmdpg,
438 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) {
439 aprint_error_dev(sc->sc_dev,
440 "unable to map cmd page, error = %d\n",
441 error);
442 goto fail1;
443 }
444 if ((error = bus_dmamap_create(sc->sc_dmat,
445 sizeof(struct njsc32_dma_page), 1,
446 sizeof(struct njsc32_dma_page), 0, BUS_DMA_NOWAIT,
447 &sc->sc_dmamap_cmdpg)) != 0) {
448 aprint_error_dev(sc->sc_dev,
449 "unable to create cmd DMA map, error = %d\n",
450 error);
451 goto fail2;
452 }
453 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap_cmdpg,
454 sc->sc_cmdpg, sizeof(struct njsc32_dma_page),
455 NULL, BUS_DMA_NOWAIT)) != 0) {
456 aprint_error_dev(sc->sc_dev,
457 "unable to load cmd DMA map, error = %d\n",
458 error);
459 goto fail3;
460 }
461
462 memset(sc->sc_cmdpg, 0, sizeof(struct njsc32_dma_page));
463 dmaaddr = sc->sc_dmamap_cmdpg->dm_segs[0].ds_addr;
464
465 #ifdef NJSC32_AUTOPARAM
466 sc->sc_ap_dma = dmaaddr + offsetof(struct njsc32_dma_page, dp_ap);
467 #endif
468
469 for (i = 0; i < NJSC32_NUM_CMD; i++) {
470 cmd = &sc->sc_cmds[i];
471 cmd->c_sc = sc;
472 cmd->c_sgt = sc->sc_cmdpg->dp_sg[i];
473 cmd->c_sgt_dma = dmaaddr +
474 offsetof(struct njsc32_dma_page, dp_sg[i]);
475 cmd->c_flags = 0;
476
477 error = bus_dmamap_create(sc->sc_dmat,
478 NJSC32_MAX_XFER, /* max total map size */
479 NJSC32_NUM_SG, /* max number of segments */
480 NJSC32_SGT_MAXSEGLEN, /* max size of a segment */
481 0, /* boundary */
482 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &cmd->c_dmamap_xfer);
483 if (error) {
484 aprint_error_dev(sc->sc_dev,
485 "only %d cmd descs available (error = %d)\n",
486 i, error);
487 break;
488 }
489 TAILQ_INSERT_TAIL(&sc->sc_freecmd, cmd, c_q);
490 }
491
492 if (i > 0)
493 return i;
494
495 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg);
496 fail3: bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg);
497 fail2: bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg,
498 sizeof(struct njsc32_dma_page));
499 fail1: bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg, sc->sc_cmdpg_nsegs);
500
501 return 0;
502 }
503
504 static void
njsc32_target_async(struct njsc32_softc * sc,struct njsc32_target * target)505 njsc32_target_async(struct njsc32_softc *sc, struct njsc32_target *target)
506 {
507
508 target->t_sync =
509 NJSC32_SYNC_VAL(sc->sc_sync_max, NJSC32_SYNCOFFSET_ASYNC);
510 target->t_ackwidth = NJSC32_ACK_WIDTH_1CLK;
511 target->t_sample = 0; /* disable */
512 target->t_syncoffset = NJSC32_SYNCOFFSET_ASYNC;
513 target->t_syncperiod = NJSC32_SYNCPERIOD_ASYNC;
514 }
515
516 static void
njsc32_init_targets(struct njsc32_softc * sc)517 njsc32_init_targets(struct njsc32_softc *sc)
518 {
519 int id, lun;
520 struct njsc32_lu *lu;
521
522 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) {
523 /* cancel negotiation status */
524 sc->sc_targets[id].t_state = NJSC32_TARST_INIT;
525
526 /* default to async mode */
527 njsc32_target_async(sc, &sc->sc_targets[id]);
528
529 #ifdef NJSC32_DUALEDGE
530 sc->sc_targets[id].t_xferctl = 0;
531 #endif
532
533 sc->sc_targets[id].t_targetid =
534 (1 << id) | (1 << NJSC32_INITIATOR_ID);
535
536 /* init logical units */
537 for (lun = 0; lun < NJSC32_NLU; lun++) {
538 lu = &sc->sc_targets[id].t_lus[lun];
539 lu->lu_cmd = NULL;
540 TAILQ_INIT(&lu->lu_q);
541 }
542 }
543 }
544
545 void
njsc32_attach(struct njsc32_softc * sc)546 njsc32_attach(struct njsc32_softc *sc)
547 {
548 const char *str;
549 #if 1 /* test */
550 int reg;
551 njsc32_model_t detected_model;
552 #endif
553
554 /* init */
555 TAILQ_INIT(&sc->sc_freecmd);
556 TAILQ_INIT(&sc->sc_reqcmd);
557 callout_init(&sc->sc_callout, 0);
558
559 #if 1 /* test */
560 /*
561 * try to distinguish 32Bi and 32UDE
562 */
563 /* try to set DualEdge bit (exists on 32UDE only) and read it back */
564 njsc32_write_2(sc, NJSC32_REG_TRANSFER, NJSC32_XFR_DUALEDGE_ENABLE);
565 if ((reg = njsc32_read_2(sc, NJSC32_REG_TRANSFER)) == 0xffff) {
566 /* device was removed? */
567 aprint_error_dev(sc->sc_dev, "attach failed\n");
568 return;
569 } else if (reg & NJSC32_XFR_DUALEDGE_ENABLE) {
570 detected_model = NJSC32_MODEL_32UDE | NJSC32_FLAG_DUALEDGE;
571 } else {
572 detected_model = NJSC32_MODEL_32BI;
573 }
574 njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0); /* restore */
575
576 #if 1/*def DIAGNOSTIC*/
577 /* compare what is configured with what is detected */
578 if ((sc->sc_model & NJSC32_MODEL_MASK) !=
579 (detected_model & NJSC32_MODEL_MASK)) {
580 /*
581 * Please report this error if it happens.
582 */
583 aprint_error_dev(sc->sc_dev, "model mismatch: %#x vs %#x\n",
584 sc->sc_model, detected_model);
585 return;
586 }
587 #endif
588 #endif
589
590 /* check model */
591 switch (sc->sc_model & NJSC32_MODEL_MASK) {
592 case NJSC32_MODEL_32BI:
593 str = "Bi";
594 /* 32Bi doesn't support DualEdge transfer */
595 KASSERT((sc->sc_model & NJSC32_FLAG_DUALEDGE) == 0);
596 break;
597 case NJSC32_MODEL_32UDE:
598 str = "UDE";
599 break;
600 default:
601 aprint_error_dev(sc->sc_dev, "unknown model!\n");
602 return;
603 }
604 aprint_normal_dev(sc->sc_dev, "NJSC-32%s", str);
605
606 switch (sc->sc_clk) {
607 default:
608 #ifdef DIAGNOSTIC
609 panic("njsc32_attach: unknown clk %d", sc->sc_clk);
610 #endif
611 case NJSC32_CLOCK_DIV_4:
612 sc->sc_synct = njsc32_synct_40M;
613 str = "40MHz";
614 break;
615 #ifdef NJSC32_SUPPORT_OTHER_CLOCKS
616 case NJSC32_CLOCK_DIV_2:
617 sc->sc_synct = njsc32_synct_20M;
618 str = "20MHz";
619 break;
620 case NJSC32_CLOCK_PCICLK:
621 sc->sc_synct = njsc32_synct_pci;
622 str = "PCI";
623 break;
624 #endif
625 }
626 aprint_normal(", G/A rev %#x, clk %s%s\n",
627 NJSC32_INDEX_GAREV(njsc32_read_2(sc, NJSC32_REG_INDEX)), str,
628 (sc->sc_model & NJSC32_FLAG_DUALEDGE) ?
629 #ifdef NJSC32_DUALEDGE
630 ", DualEdge"
631 #else
632 ", DualEdge (no driver support)"
633 #endif
634 : "");
635
636 /* allocate DMA resource */
637 if ((sc->sc_ncmd = njsc32_init_cmds(sc)) == 0) {
638 aprint_error_dev(sc->sc_dev, "no usable DMA map\n");
639 return;
640 }
641 sc->sc_flags |= NJSC32_CMDPG_MAPPED;
642
643 sc->sc_curcmd = NULL;
644 sc->sc_nusedcmds = 0;
645
646 sc->sc_sync_max = 1; /* XXX look up EEPROM configuration? */
647
648 /* initialize hardware and target structure */
649 njsc32_init(sc, cold);
650
651 /* setup adapter */
652 sc->sc_adapter.adapt_dev = sc->sc_dev;
653 sc->sc_adapter.adapt_nchannels = 1;
654 sc->sc_adapter.adapt_request = njsc32_scsipi_request;
655 sc->sc_adapter.adapt_minphys = njsc32_scsipi_minphys;
656 sc->sc_adapter.adapt_ioctl = njsc32_scsipi_ioctl;
657
658 sc->sc_adapter.adapt_max_periph = sc->sc_adapter.adapt_openings =
659 sc->sc_ncmd;
660
661 /* setup channel */
662 sc->sc_channel.chan_adapter = &sc->sc_adapter;
663 sc->sc_channel.chan_bustype = &scsi_bustype;
664 sc->sc_channel.chan_channel = 0;
665 sc->sc_channel.chan_ntargets = NJSC32_NTARGET;
666 sc->sc_channel.chan_nluns = NJSC32_NLU;
667 sc->sc_channel.chan_id = NJSC32_INITIATOR_ID;
668
669 sc->sc_scsi = config_found(sc->sc_dev, &sc->sc_channel, scsiprint);
670 }
671
672 int
njsc32_detach(struct njsc32_softc * sc,int flags)673 njsc32_detach(struct njsc32_softc *sc, int flags)
674 {
675 int rv = 0;
676 int i, s;
677 struct njsc32_cmd *cmd;
678
679 callout_stop(&sc->sc_callout);
680
681 s = splbio();
682
683 /* clear running/disconnected commands */
684 njsc32_clear_cmds(sc, XS_DRIVER_STUFFUP);
685
686 sc->sc_stat = NJSC32_STAT_DETACH;
687
688 /* clear pending commands */
689 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) {
690 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q);
691 njsc32_end_cmd(sc, cmd, XS_RESET);
692 }
693
694 if (sc->sc_scsi != NULL)
695 rv = config_detach(sc->sc_scsi, flags);
696
697 splx(s);
698
699 /* free DMA resource */
700 if (sc->sc_flags & NJSC32_CMDPG_MAPPED) {
701 for (i = 0; i < sc->sc_ncmd; i++) {
702 cmd = &sc->sc_cmds[i];
703 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED)
704 bus_dmamap_unload(sc->sc_dmat,
705 cmd->c_dmamap_xfer);
706 bus_dmamap_destroy(sc->sc_dmat, cmd->c_dmamap_xfer);
707 }
708
709 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap_cmdpg);
710 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap_cmdpg);
711 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_cmdpg,
712 sizeof(struct njsc32_dma_page));
713 bus_dmamem_free(sc->sc_dmat, &sc->sc_cmdpg_seg,
714 sc->sc_cmdpg_nsegs);
715 }
716
717 return rv;
718 }
719
720 static inline void
njsc32_cmd_init(struct njsc32_cmd * cmd)721 njsc32_cmd_init(struct njsc32_cmd *cmd)
722 {
723
724 cmd->c_flags = 0;
725
726 /* scatter/gather table */
727 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, 0);
728 cmd->c_sgoffset = 0;
729 cmd->c_sgfixcnt = 0;
730
731 /* data pointer */
732 cmd->c_dp_cur = cmd->c_dp_saved = cmd->c_dp_max = 0;
733 }
734
735 static inline void
njsc32_init_msgout(struct njsc32_softc * sc)736 njsc32_init_msgout(struct njsc32_softc *sc)
737 {
738
739 sc->sc_msgoutlen = 0;
740 sc->sc_msgoutidx = 0;
741 }
742
743 static void
njsc32_add_msgout(struct njsc32_softc * sc,int byte)744 njsc32_add_msgout(struct njsc32_softc *sc, int byte)
745 {
746
747 if (sc->sc_msgoutlen >= NJSC32_MSGOUT_LEN) {
748 printf("njsc32_add_msgout: too many\n");
749 return;
750 }
751 sc->sc_msgout[sc->sc_msgoutlen++] = byte;
752 }
753
754 static u_int32_t
njsc32_get_auto_msgout(struct njsc32_softc * sc)755 njsc32_get_auto_msgout(struct njsc32_softc *sc)
756 {
757 u_int32_t val;
758 u_int8_t *p;
759
760 val = 0;
761 p = sc->sc_msgout;
762 switch (sc->sc_msgoutlen) {
763 /* 31-24 23-16 15-8 7 ... 1 0 */
764 case 3: /* MSG3 MSG2 MSG1 V --- cnt */
765 val |= *p++ << NJSC32_MSGOUT_MSG1_SHIFT;
766 /* FALLTHROUGH */
767
768 case 2: /* MSG2 MSG1 --- V --- cnt */
769 val |= *p++ << NJSC32_MSGOUT_MSG2_SHIFT;
770 /* FALLTHROUGH */
771
772 case 1: /* MSG1 --- --- V --- cnt */
773 val |= *p++ << NJSC32_MSGOUT_MSG3_SHIFT;
774 val |= NJSC32_MSGOUT_VALID | sc->sc_msgoutlen;
775 break;
776
777 default:
778 break;
779 }
780 return val;
781 }
782
783 #ifdef NJSC32_DUALEDGE
784 /* add Wide Data Transfer Request to the next Message Out */
785 static void
njsc32_msgout_wdtr(struct njsc32_softc * sc,int width)786 njsc32_msgout_wdtr(struct njsc32_softc *sc, int width)
787 {
788
789 njsc32_add_msgout(sc, MSG_EXTENDED);
790 njsc32_add_msgout(sc, MSG_EXT_WDTR_LEN);
791 njsc32_add_msgout(sc, MSG_EXT_WDTR);
792 njsc32_add_msgout(sc, width);
793 }
794 #endif
795
796 /* add Synchronous Data Transfer Request to the next Message Out */
797 static void
njsc32_msgout_sdtr(struct njsc32_softc * sc,int period,int offset)798 njsc32_msgout_sdtr(struct njsc32_softc *sc, int period, int offset)
799 {
800
801 njsc32_add_msgout(sc, MSG_EXTENDED);
802 njsc32_add_msgout(sc, MSG_EXT_SDTR_LEN);
803 njsc32_add_msgout(sc, MSG_EXT_SDTR);
804 njsc32_add_msgout(sc, period);
805 njsc32_add_msgout(sc, offset);
806 }
807
808 static void
njsc32_negotiate_xfer(struct njsc32_softc * sc,struct njsc32_target * target)809 njsc32_negotiate_xfer(struct njsc32_softc *sc, struct njsc32_target *target)
810 {
811
812 /* initial negotiation state */
813 if (target->t_state == NJSC32_TARST_INIT) {
814 #ifdef NJSC32_DUALEDGE
815 if (target->t_flags & NJSC32_TARF_DE)
816 target->t_state = NJSC32_TARST_DE;
817 else
818 #endif
819 if (target->t_flags & NJSC32_TARF_SYNC)
820 target->t_state = NJSC32_TARST_SDTR;
821 else
822 target->t_state = NJSC32_TARST_DONE;
823 }
824
825 switch (target->t_state) {
826 default:
827 case NJSC32_TARST_INIT:
828 #ifdef DIAGNOSTIC
829 panic("njsc32_negotiate_xfer");
830 /* NOTREACHED */
831 #endif
832 /* FALLTHROUGH */
833 case NJSC32_TARST_DONE:
834 /* no more work */
835 break;
836
837 #ifdef NJSC32_DUALEDGE
838 case NJSC32_TARST_DE:
839 njsc32_msgout_wdtr(sc, 0xde /* XXX? */);
840 break;
841
842 case NJSC32_TARST_WDTR:
843 njsc32_msgout_wdtr(sc, MSG_EXT_WDTR_BUS_8_BIT);
844 break;
845 #endif
846
847 case NJSC32_TARST_SDTR:
848 njsc32_msgout_sdtr(sc, sc->sc_synct[sc->sc_sync_max].sp_period,
849 NJSC32_SYNCOFFSET_MAX);
850 break;
851
852 case NJSC32_TARST_ASYNC:
853 njsc32_msgout_sdtr(sc, NJSC32_SYNCPERIOD_ASYNC,
854 NJSC32_SYNCOFFSET_ASYNC);
855 break;
856 }
857 }
858
859 /* turn LED on */
860 static inline void
njsc32_led_on(struct njsc32_softc * sc)861 njsc32_led_on(struct njsc32_softc *sc)
862 {
863
864 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_ON);
865 }
866
867 /* turn LED off */
868 static inline void
njsc32_led_off(struct njsc32_softc * sc)869 njsc32_led_off(struct njsc32_softc *sc)
870 {
871
872 njsc32_ireg_write_1(sc, NJSC32_IREG_EXT_PORT, NJSC32_EXTPORT_LED_OFF);
873 }
874
875 static void
njsc32_arbitration_failed(struct njsc32_softc * sc)876 njsc32_arbitration_failed(struct njsc32_softc *sc)
877 {
878 struct njsc32_cmd *cmd;
879
880 if ((cmd = sc->sc_curcmd) == NULL || sc->sc_stat != NJSC32_STAT_ARBIT)
881 return;
882
883 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0)
884 callout_stop(&cmd->c_xs->xs_callout);
885
886 sc->sc_stat = NJSC32_STAT_IDLE;
887 sc->sc_curcmd = NULL;
888
889 /* the command is no longer active */
890 if (--sc->sc_nusedcmds == 0)
891 njsc32_led_off(sc);
892 }
893
894 static inline void
njsc32_cmd_load(struct njsc32_softc * sc,struct njsc32_cmd * cmd)895 njsc32_cmd_load(struct njsc32_softc *sc, struct njsc32_cmd *cmd)
896 {
897 struct njsc32_target *target;
898 struct scsipi_xfer *xs;
899 int i, control, lun;
900 u_int32_t msgoutreg;
901 #ifdef NJSC32_AUTOPARAM
902 struct njsc32_autoparam *ap;
903 #endif
904
905 xs = cmd->c_xs;
906 #ifdef NJSC32_AUTOPARAM
907 ap = &sc->sc_cmdpg->dp_ap;
908 #else
909 /* reset CDB pointer */
910 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, NJSC32_CMD_CLEAR_CDB_FIFO_PTR);
911 #endif
912
913 /* CDB */
914 TPRINTC(cmd, ("njsc32_cmd_load: CDB"));
915 for (i = 0; i < xs->cmdlen; i++) {
916 #ifdef NJSC32_AUTOPARAM
917 ap->ap_cdb[i].cdb_data = ((u_int8_t *)xs->cmd)[i];
918 #else
919 njsc32_write_1(sc, NJSC32_REG_COMMAND_DATA,
920 ((u_int8_t *)xs->cmd)[i]);
921 #endif
922 TPRINTF((" %02x", ((u_int8_t *)cmd->c_xs->cmd)[i]));
923 }
924 #ifdef NJSC32_AUTOPARAM /* XXX needed? */
925 for ( ; i < NJSC32_AUTOPARAM_CDBLEN; i++)
926 ap->ap_cdb[i].cdb_data = 0;
927 #endif
928
929 control = xs->xs_control;
930
931 /*
932 * Message Out
933 */
934 njsc32_init_msgout(sc);
935
936 /* Identify */
937 lun = xs->xs_periph->periph_lun;
938 njsc32_add_msgout(sc, (control & XS_CTL_REQSENSE) ?
939 MSG_IDENTIFY(lun, 0) : MSG_IDENTIFY(lun, 1));
940
941 /* tagged queueing */
942 if (control & XS_CTL_TAGMASK) {
943 njsc32_add_msgout(sc, xs->xs_tag_type);
944 njsc32_add_msgout(sc, xs->xs_tag_id);
945 TPRINTF((" (tag %#x %#x)\n", xs->xs_tag_type, xs->xs_tag_id));
946 }
947 TPRINTF(("\n"));
948
949 target = cmd->c_target;
950
951 /* transfer negotiation */
952 if (control & XS_CTL_REQSENSE)
953 target->t_state = NJSC32_TARST_INIT;
954 njsc32_negotiate_xfer(sc, target);
955
956 msgoutreg = njsc32_get_auto_msgout(sc);
957
958 #ifdef NJSC32_AUTOPARAM
959 ap->ap_msgout = htole32(msgoutreg);
960
961 ap->ap_sync = target->t_sync;
962 ap->ap_ackwidth = target->t_ackwidth;
963 ap->ap_targetid = target->t_targetid;
964 ap->ap_sample = target->t_sample;
965
966 ap->ap_cmdctl = htole16(NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
967 NJSC32_CMD_AUTO_COMMAND_PHASE |
968 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN |
969 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02);
970 #ifdef NJSC32_DUALEDGE
971 ap->ap_xferctl = htole16(cmd->c_xferctl | target->t_xferctl);
972 #else
973 ap->ap_xferctl = htole16(cmd->c_xferctl);
974 #endif
975 ap->ap_sgtdmaaddr = htole32(cmd->c_sgtdmaaddr);
976
977 /* sync njsc32_autoparam */
978 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
979 offsetof(struct njsc32_dma_page, dp_ap), /* offset */
980 sizeof(struct njsc32_autoparam),
981 BUS_DMASYNC_PREWRITE);
982
983 /* autoparam DMA address */
984 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, sc->sc_ap_dma);
985
986 /* start command (autoparam) */
987 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,
988 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_PARAMETER);
989
990 #else /* not NJSC32_AUTOPARAM */
991
992 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgoutreg);
993
994 /* load parameters */
995 njsc32_write_1(sc, NJSC32_REG_TARGET_ID, target->t_targetid);
996 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync);
997 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth);
998 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample);
999 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr);
1000 #ifdef NJSC32_DUALEDGE
1001 njsc32_write_2(sc, NJSC32_REG_TRANSFER,
1002 cmd->c_xferctl | target->t_xferctl);
1003 #else
1004 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
1005 #endif
1006 /* start AutoSCSI */
1007 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL,
1008 NJSC32_CMD_CLEAR_CDB_FIFO_PTR | NJSC32_CMD_AUTO_COMMAND_PHASE |
1009 NJSC32_CMD_AUTO_SCSI_START | NJSC32_CMD_AUTO_ATN |
1010 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02);
1011 #endif /* not NJSC32_AUTOPARAM */
1012 }
1013
1014 /* Note: must be called at splbio() */
1015 static void
njsc32_start(struct njsc32_softc * sc)1016 njsc32_start(struct njsc32_softc *sc)
1017 {
1018 struct njsc32_cmd *cmd;
1019
1020 /* get a command to issue */
1021 TAILQ_FOREACH(cmd, &sc->sc_reqcmd, c_q) {
1022 if (cmd->c_lu->lu_cmd == NULL &&
1023 ((cmd->c_flags & NJSC32_CMD_TAGGED) ||
1024 TAILQ_EMPTY(&cmd->c_lu->lu_q)))
1025 break; /* OK, the logical unit is free */
1026 }
1027 if (!cmd)
1028 goto out; /* no work to do */
1029
1030 /* request will always fail if not in bus free phase */
1031 if (njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) !=
1032 NJSC32_BUSMON_BUSFREE)
1033 goto busy;
1034
1035 /* clear parity error and enable parity detection */
1036 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
1037 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR);
1038
1039 njsc32_cmd_load(sc, cmd);
1040
1041 if (sc->sc_nusedcmds++ == 0)
1042 njsc32_led_on(sc);
1043
1044 sc->sc_curcmd = cmd;
1045 sc->sc_stat = NJSC32_STAT_ARBIT;
1046
1047 if ((cmd->c_xs->xs_control & XS_CTL_POLL) == 0) {
1048 callout_reset(&cmd->c_xs->xs_callout,
1049 mstohz(cmd->c_xs->timeout),
1050 njsc32_cmdtimeout, cmd);
1051 }
1052
1053 return;
1054
1055 busy: /* XXX retry counter */
1056 TPRINTF(("%s: njsc32_start: busy\n", device_xname(sc->sc_dev)));
1057 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_ARBITRATION_RETRY_TIME);
1058 out: njsc32_write_2(sc, NJSC32_REG_TRANSFER, 0);
1059 }
1060
1061 static void
njsc32_run_xfer(struct njsc32_softc * sc,struct scsipi_xfer * xs)1062 njsc32_run_xfer(struct njsc32_softc *sc, struct scsipi_xfer *xs)
1063 {
1064 struct scsipi_periph *periph;
1065 int control;
1066 int lun;
1067 struct njsc32_cmd *cmd;
1068 int s, i, error;
1069
1070 periph = xs->xs_periph;
1071 KASSERT((unsigned)periph->periph_target <= NJSC32_MAX_TARGET_ID);
1072
1073 control = xs->xs_control;
1074 lun = periph->periph_lun;
1075
1076 /*
1077 * get a free cmd
1078 * (scsipi layer knows the number of cmds, so this shall never fail)
1079 */
1080 s = splbio();
1081 cmd = TAILQ_FIRST(&sc->sc_freecmd);
1082 KASSERT(cmd);
1083 TAILQ_REMOVE(&sc->sc_freecmd, cmd, c_q);
1084 splx(s);
1085
1086 /*
1087 * build a request
1088 */
1089 njsc32_cmd_init(cmd);
1090 cmd->c_xs = xs;
1091 cmd->c_target = &sc->sc_targets[periph->periph_target];
1092 cmd->c_lu = &cmd->c_target->t_lus[lun];
1093
1094 /* tagged queueing */
1095 if (control & XS_CTL_TAGMASK) {
1096 cmd->c_flags |= NJSC32_CMD_TAGGED;
1097 if (control & XS_CTL_HEAD_TAG)
1098 cmd->c_flags |= NJSC32_CMD_TAGGED_HEAD;
1099 }
1100
1101 /* map DMA buffer */
1102 cmd->c_datacnt = xs->datalen;
1103 if (xs->datalen) {
1104 /* Is XS_CTL_DATA_UIO ever used anywhere? */
1105 KASSERT((control & XS_CTL_DATA_UIO) == 0);
1106
1107 error = bus_dmamap_load(sc->sc_dmat, cmd->c_dmamap_xfer,
1108 xs->data, xs->datalen, NULL,
1109 ((control & XS_CTL_NOSLEEP) ?
1110 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) |
1111 BUS_DMA_STREAMING |
1112 ((control & XS_CTL_DATA_IN) ?
1113 BUS_DMA_READ : BUS_DMA_WRITE));
1114
1115 switch (error) {
1116 case 0:
1117 break;
1118 case ENOMEM:
1119 case EAGAIN:
1120 xs->error = XS_RESOURCE_SHORTAGE;
1121 goto map_failed;
1122 default:
1123 xs->error = XS_DRIVER_STUFFUP;
1124 map_failed:
1125 printf("%s: njsc32_run_xfer: map failed, error %d\n",
1126 device_xname(sc->sc_dev), error);
1127 /* put it back to free command list */
1128 s = splbio();
1129 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q);
1130 splx(s);
1131 /* abort this transfer */
1132 scsipi_done(xs);
1133 return;
1134 }
1135
1136 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer,
1137 0, cmd->c_dmamap_xfer->dm_mapsize,
1138 (control & XS_CTL_DATA_IN) ?
1139 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
1140
1141 for (i = 0; i < cmd->c_dmamap_xfer->dm_nsegs; i++) {
1142 cmd->c_sgt[i].sg_addr =
1143 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_addr);
1144 cmd->c_sgt[i].sg_len =
1145 htole32(cmd->c_dmamap_xfer->dm_segs[i].ds_len);
1146 }
1147 /* end mark */
1148 cmd->c_sgt[i - 1].sg_len |= htole32(NJSC32_SGT_ENDMARK);
1149
1150 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
1151 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */
1152 NJSC32_SIZE_SGT,
1153 BUS_DMASYNC_PREWRITE);
1154
1155 cmd->c_flags |= NJSC32_CMD_DMA_MAPPED;
1156
1157 /* enable transfer */
1158 cmd->c_xferctl =
1159 NJSC32_XFR_TRANSFER_GO | NJSC32_XFR_BM_START |
1160 NJSC32_XFR_ALL_COUNT_CLR;
1161
1162 /* XXX How can we specify the DMA direction? */
1163
1164 #if 0 /* faster write mode? (doesn't work) */
1165 if ((control & XS_CTL_DATA_IN) == 0)
1166 cmd->c_xferctl |= NJSC32_XFR_ADVANCED_BM_WRITE;
1167 #endif
1168 } else {
1169 /* no data transfer */
1170 cmd->c_xferctl = 0;
1171 }
1172
1173 /* queue request */
1174 s = splbio();
1175 TAILQ_INSERT_TAIL(&sc->sc_reqcmd, cmd, c_q);
1176
1177 /* start the controller if idle */
1178 if (sc->sc_stat == NJSC32_STAT_IDLE)
1179 njsc32_start(sc);
1180
1181 splx(s);
1182
1183 if (control & XS_CTL_POLL) {
1184 /* wait for completion */
1185 /* XXX should handle timeout? */
1186 while ((xs->xs_status & XS_STS_DONE) == 0) {
1187 delay(1000);
1188 njsc32_intr(sc);
1189 }
1190 }
1191 }
1192
1193 static void
njsc32_end_cmd(struct njsc32_softc * sc,struct njsc32_cmd * cmd,scsipi_xfer_result_t result)1194 njsc32_end_cmd(struct njsc32_softc *sc, struct njsc32_cmd *cmd,
1195 scsipi_xfer_result_t result)
1196 {
1197 struct scsipi_xfer *xs;
1198 int s;
1199 #ifdef DIAGNOSTIC
1200 struct njsc32_cmd *c;
1201 #endif
1202
1203 KASSERT(cmd);
1204
1205 #ifdef DIAGNOSTIC
1206 s = splbio();
1207 TAILQ_FOREACH(c, &sc->sc_freecmd, c_q) {
1208 if (cmd == c)
1209 panic("njsc32_end_cmd: already in free list");
1210 }
1211 splx(s);
1212 #endif
1213 xs = cmd->c_xs;
1214
1215 if (cmd->c_flags & NJSC32_CMD_DMA_MAPPED) {
1216 if (cmd->c_datacnt) {
1217 bus_dmamap_sync(sc->sc_dmat, cmd->c_dmamap_xfer,
1218 0, cmd->c_dmamap_xfer->dm_mapsize,
1219 (xs->xs_control & XS_CTL_DATA_IN) ?
1220 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1221
1222 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
1223 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg,
1224 NJSC32_SIZE_SGT, BUS_DMASYNC_POSTWRITE);
1225 }
1226
1227 bus_dmamap_unload(sc->sc_dmat, cmd->c_dmamap_xfer);
1228 cmd->c_flags &= ~NJSC32_CMD_DMA_MAPPED;
1229 }
1230
1231 s = splbio();
1232 if ((xs->xs_control & XS_CTL_POLL) == 0)
1233 callout_stop(&xs->xs_callout);
1234
1235 TAILQ_INSERT_HEAD(&sc->sc_freecmd, cmd, c_q);
1236 splx(s);
1237
1238 xs->error = result;
1239 scsipi_done(xs);
1240
1241 if (--sc->sc_nusedcmds == 0)
1242 njsc32_led_off(sc);
1243 }
1244
1245 /*
1246 * request from scsipi layer
1247 */
1248 static void
njsc32_scsipi_request(struct scsipi_channel * chan,scsipi_adapter_req_t req,void * arg)1249 njsc32_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req,
1250 void *arg)
1251 {
1252 struct njsc32_softc *sc;
1253 struct scsipi_xfer_mode *xm;
1254 struct njsc32_target *target;
1255
1256 sc = device_private(chan->chan_adapter->adapt_dev);
1257
1258 switch (req) {
1259 case ADAPTER_REQ_RUN_XFER:
1260 njsc32_run_xfer(sc, arg);
1261 break;
1262
1263 case ADAPTER_REQ_GROW_RESOURCES:
1264 /* not supported */
1265 break;
1266
1267 case ADAPTER_REQ_SET_XFER_MODE:
1268 xm = arg;
1269 target = &sc->sc_targets[xm->xm_target];
1270
1271 target->t_flags = 0;
1272 if (xm->xm_mode & PERIPH_CAP_TQING)
1273 target->t_flags |= NJSC32_TARF_TAG;
1274 if (xm->xm_mode & PERIPH_CAP_SYNC) {
1275 target->t_flags |= NJSC32_TARF_SYNC;
1276 #ifdef NJSC32_DUALEDGE
1277 if (sc->sc_model & NJSC32_FLAG_DUALEDGE)
1278 target->t_flags |= NJSC32_TARF_DE;
1279 #endif
1280 }
1281 #ifdef NJSC32_DUALEDGE
1282 target->t_xferctl = 0;
1283 #endif
1284 target->t_state = NJSC32_TARST_INIT;
1285 njsc32_target_async(sc, target);
1286
1287 break;
1288 default:
1289 break;
1290 }
1291 }
1292
1293 static void
njsc32_scsipi_minphys(struct buf * bp)1294 njsc32_scsipi_minphys(struct buf *bp)
1295 {
1296
1297 if (bp->b_bcount > NJSC32_MAX_XFER)
1298 bp->b_bcount = NJSC32_MAX_XFER;
1299 minphys(bp);
1300 }
1301
1302 /*
1303 * On some versions of 32UDE (probably the earlier ones), the controller
1304 * detects continuous bus reset when the termination power is absent.
1305 * Make sure the system won't hang on such situation.
1306 */
1307 static void
njsc32_wait_reset_release(void * arg)1308 njsc32_wait_reset_release(void *arg)
1309 {
1310 struct njsc32_softc *sc = arg;
1311 struct njsc32_cmd *cmd;
1312
1313 /* clear pending commands */
1314 while ((cmd = TAILQ_FIRST(&sc->sc_reqcmd)) != NULL) {
1315 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q);
1316 njsc32_end_cmd(sc, cmd, XS_RESET);
1317 }
1318
1319 /* If Bus Reset is not released yet, schedule recheck. */
1320 if (njsc32_read_2(sc, NJSC32_REG_IRQ) & NJSC32_IRQ_SCSIRESET) {
1321 switch (sc->sc_stat) {
1322 case NJSC32_STAT_RESET:
1323 sc->sc_stat = NJSC32_STAT_RESET1;
1324 break;
1325 case NJSC32_STAT_RESET1:
1326 /* print message if Bus Reset is detected twice */
1327 sc->sc_stat = NJSC32_STAT_RESET2;
1328 printf("%s: detected excessive bus reset "
1329 "--- missing termination power?\n",
1330 device_xname(sc->sc_dev));
1331 break;
1332 default:
1333 break;
1334 }
1335 callout_reset(&sc->sc_callout,
1336 hz * 2 /* poll every 2s */,
1337 njsc32_wait_reset_release, sc);
1338 return;
1339 }
1340
1341 if (sc->sc_stat == NJSC32_STAT_RESET2)
1342 printf("%s: bus reset is released\n", device_xname(sc->sc_dev));
1343
1344 /* unblock interrupts */
1345 njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
1346
1347 sc->sc_stat = NJSC32_STAT_IDLE;
1348 }
1349
1350 static void
njsc32_reset_bus(struct njsc32_softc * sc)1351 njsc32_reset_bus(struct njsc32_softc *sc)
1352 {
1353 int s;
1354
1355 DPRINTF(("%s: njsc32_reset_bus:\n", device_xname(sc->sc_dev)));
1356
1357 /* block interrupts */
1358 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
1359
1360 sc->sc_stat = NJSC32_STAT_RESET;
1361
1362 /* hold SCSI bus reset */
1363 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, NJSC32_SBCTL_RST);
1364 delay(NJSC32_RESET_HOLD_TIME);
1365
1366 /* clear transfer */
1367 njsc32_clear_cmds(sc, XS_RESET);
1368
1369 /* initialize target structure */
1370 njsc32_init_targets(sc);
1371
1372 /* XXXSMP scsipi */
1373 KERNEL_LOCK(1, curlwp);
1374 s = splbio();
1375 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_RESET, NULL);
1376 splx(s);
1377 /* XXXSMP scsipi */
1378 KERNEL_UNLOCK_ONE(curlwp);
1379
1380 /* release SCSI bus reset */
1381 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, 0);
1382
1383 njsc32_wait_reset_release(sc);
1384 }
1385
1386 /*
1387 * clear running/disconnected commands
1388 */
1389 static void
njsc32_clear_cmds(struct njsc32_softc * sc,scsipi_xfer_result_t cmdresult)1390 njsc32_clear_cmds(struct njsc32_softc *sc, scsipi_xfer_result_t cmdresult)
1391 {
1392 struct njsc32_cmd *cmd;
1393 int id, lun;
1394 struct njsc32_lu *lu;
1395
1396 njsc32_arbitration_failed(sc);
1397
1398 /* clear current transfer */
1399 if ((cmd = sc->sc_curcmd) != NULL) {
1400 sc->sc_curcmd = NULL;
1401 njsc32_end_cmd(sc, cmd, cmdresult);
1402 }
1403
1404 /* clear disconnected transfers */
1405 for (id = 0; id <= NJSC32_MAX_TARGET_ID; id++) {
1406 for (lun = 0; lun < NJSC32_NLU; lun++) {
1407 lu = &sc->sc_targets[id].t_lus[lun];
1408
1409 if ((cmd = lu->lu_cmd) != NULL) {
1410 lu->lu_cmd = NULL;
1411 njsc32_end_cmd(sc, cmd, cmdresult);
1412 }
1413 while ((cmd = TAILQ_FIRST(&lu->lu_q)) != NULL) {
1414 TAILQ_REMOVE(&lu->lu_q, cmd, c_q);
1415 njsc32_end_cmd(sc, cmd, cmdresult);
1416 }
1417 }
1418 }
1419 }
1420
1421 static int
njsc32_scsipi_ioctl(struct scsipi_channel * chan,u_long cmd,void * addr,int flag,struct proc * p)1422 njsc32_scsipi_ioctl(struct scsipi_channel *chan, u_long cmd,
1423 void *addr, int flag, struct proc *p)
1424 {
1425 struct njsc32_softc *sc;
1426
1427 sc = device_private(chan->chan_adapter->adapt_dev);
1428
1429 switch (cmd) {
1430 case SCBUSIORESET:
1431 njsc32_init(sc, 0);
1432 return 0;
1433 default:
1434 break;
1435 }
1436
1437 return ENOTTY;
1438 }
1439
1440 /*
1441 * set current data pointer
1442 */
1443 static inline void
njsc32_set_cur_ptr(struct njsc32_cmd * cmd,u_int32_t pos)1444 njsc32_set_cur_ptr(struct njsc32_cmd *cmd, u_int32_t pos)
1445 {
1446
1447 /* new current data pointer */
1448 cmd->c_dp_cur = pos;
1449
1450 /* update number of bytes transferred */
1451 if (pos > cmd->c_dp_max)
1452 cmd->c_dp_max = pos;
1453 }
1454
1455 /*
1456 * set data pointer for the next transfer
1457 */
1458 static void
njsc32_set_ptr(struct njsc32_softc * sc,struct njsc32_cmd * cmd,u_int32_t pos)1459 njsc32_set_ptr(struct njsc32_softc *sc, struct njsc32_cmd *cmd, u_int32_t pos)
1460 {
1461 struct njsc32_sgtable *sg;
1462 unsigned sgte;
1463 u_int32_t len;
1464
1465 /* set current pointer */
1466 njsc32_set_cur_ptr(cmd, pos);
1467
1468 /* undo previous fix if any */
1469 if (cmd->c_sgfixcnt != 0) {
1470 sg = &cmd->c_sgt[cmd->c_sgoffset];
1471 sg->sg_addr = htole32(le32toh(sg->sg_addr) - cmd->c_sgfixcnt);
1472 sg->sg_len = htole32(le32toh(sg->sg_len) + cmd->c_sgfixcnt);
1473 cmd->c_sgfixcnt = 0;
1474 }
1475
1476 if (pos >= cmd->c_datacnt) {
1477 /* transfer done */
1478 #if 1 /*def DIAGNOSTIC*/
1479 if (pos > cmd->c_datacnt)
1480 printf("%s: pos %u too large\n",
1481 device_xname(sc->sc_dev), pos - cmd->c_datacnt);
1482 #endif
1483 cmd->c_xferctl = 0; /* XXX correct? */
1484
1485 return;
1486 }
1487
1488 for (sgte = 0, sg = cmd->c_sgt;
1489 sgte < NJSC32_NUM_SG && pos > 0; sgte++, sg++) {
1490 len = le32toh(sg->sg_len) & ~NJSC32_SGT_ENDMARK;
1491 if (pos < len) {
1492 sg->sg_addr = htole32(le32toh(sg->sg_addr) + pos);
1493 sg->sg_len = htole32(le32toh(sg->sg_len) - pos);
1494 cmd->c_sgfixcnt = pos;
1495 break;
1496 }
1497 pos -= len;
1498 #ifdef DIAGNOSTIC
1499 if (sg->sg_len & htole32(NJSC32_SGT_ENDMARK)) {
1500 panic("njsc32_set_ptr: bad pos");
1501 }
1502 #endif
1503 }
1504 #ifdef DIAGNOSTIC
1505 if (sgte >= NJSC32_NUM_SG)
1506 panic("njsc32_set_ptr: bad sg");
1507 #endif
1508 if (cmd->c_sgoffset != sgte) {
1509 cmd->c_sgoffset = sgte;
1510 cmd->c_sgtdmaaddr = NJSC32_CMD_DMAADDR_SGT(cmd, sgte);
1511 }
1512
1513 /* XXX overkill */
1514 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap_cmdpg,
1515 (char *)cmd->c_sgt - (char *)sc->sc_cmdpg, /* offset */
1516 NJSC32_SIZE_SGT,
1517 BUS_DMASYNC_PREWRITE);
1518 }
1519
1520 /*
1521 * save data pointer
1522 */
1523 static inline void
njsc32_save_ptr(struct njsc32_cmd * cmd)1524 njsc32_save_ptr(struct njsc32_cmd *cmd)
1525 {
1526
1527 cmd->c_dp_saved = cmd->c_dp_cur;
1528 }
1529
1530 static void
njsc32_assert_ack(struct njsc32_softc * sc)1531 njsc32_assert_ack(struct njsc32_softc *sc)
1532 {
1533 u_int8_t reg;
1534
1535 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL);
1536 reg |= NJSC32_SBCTL_ACK | NJSC32_SBCTL_ACK_ENABLE;
1537 #if 0 /* needed? */
1538 reg |= NJSC32_SBCTL_AUTODIRECTION;
1539 #endif
1540 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg);
1541 }
1542
1543 static void
njsc32_negate_ack(struct njsc32_softc * sc)1544 njsc32_negate_ack(struct njsc32_softc *sc)
1545 {
1546 u_int8_t reg;
1547
1548 reg = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_CONTROL);
1549 #if 0 /* needed? */
1550 reg |= NJSC32_SBCTL_ACK_ENABLE;
1551 reg |= NJSC32_SBCTL_AUTODIRECTION;
1552 #endif
1553 reg &= ~NJSC32_SBCTL_ACK;
1554 njsc32_write_1(sc, NJSC32_REG_SCSI_BUS_CONTROL, reg);
1555 }
1556
1557 static void
njsc32_wait_req_negate(struct njsc32_softc * sc)1558 njsc32_wait_req_negate(struct njsc32_softc *sc)
1559 {
1560 int cnt;
1561
1562 for (cnt = 0; cnt < NJSC32_REQ_TIMEOUT; cnt++) {
1563 if ((njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) &
1564 NJSC32_BUSMON_REQ) == 0)
1565 return;
1566 delay(1);
1567 }
1568 printf("%s: njsc32_wait_req_negate: timed out\n",
1569 device_xname(sc->sc_dev));
1570 }
1571
1572 static void
njsc32_reconnect(struct njsc32_softc * sc,struct njsc32_cmd * cmd)1573 njsc32_reconnect(struct njsc32_softc *sc, struct njsc32_cmd *cmd)
1574 {
1575 struct scsipi_xfer *xs;
1576
1577 xs = cmd->c_xs;
1578 if ((xs->xs_control & XS_CTL_POLL) == 0) {
1579 callout_stop(&xs->xs_callout);
1580 callout_reset(&xs->xs_callout,
1581 mstohz(xs->timeout),
1582 njsc32_cmdtimeout, cmd);
1583 }
1584
1585 /* Reconnection implies Restore Pointers */
1586 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved);
1587 }
1588
1589 static enum njsc32_reselstat
njsc32_resel_identify(struct njsc32_softc * sc,int lun,struct njsc32_cmd ** pcmd)1590 njsc32_resel_identify(struct njsc32_softc *sc, int lun,
1591 struct njsc32_cmd **pcmd)
1592 {
1593 int targetid;
1594 struct njsc32_lu *plu;
1595 struct njsc32_cmd *cmd;
1596
1597 switch (sc->sc_stat) {
1598 case NJSC32_STAT_RESEL:
1599 break; /* OK */
1600
1601 case NJSC32_STAT_RESEL_LUN:
1602 case NJSC32_STAT_RECONNECT:
1603 /*
1604 * accept and ignore if the LUN is the same as the current one,
1605 * reject otherwise.
1606 */
1607 return sc->sc_resellun == lun ?
1608 NJSC32_RESEL_THROUGH : NJSC32_RESEL_ERROR;
1609
1610 default:
1611 printf("%s: njsc32_resel_identify: not in reselection\n",
1612 device_xname(sc->sc_dev));
1613 return NJSC32_RESEL_ERROR;
1614 }
1615
1616 targetid = sc->sc_reselid;
1617 TPRINTF(("%s: njsc32_resel_identify: reselection lun %d\n",
1618 device_xname(sc->sc_dev), lun));
1619
1620 if (targetid > NJSC32_MAX_TARGET_ID || lun >= NJSC32_NLU)
1621 return NJSC32_RESEL_ERROR;
1622
1623 sc->sc_resellun = lun;
1624 plu = &sc->sc_targets[targetid].t_lus[lun];
1625
1626 if ((cmd = plu->lu_cmd) != NULL) {
1627 sc->sc_stat = NJSC32_STAT_RECONNECT;
1628 plu->lu_cmd = NULL;
1629 *pcmd = cmd;
1630 TPRINTC(cmd, ("njsc32_resel_identify: I_T_L nexus\n"));
1631 njsc32_reconnect(sc, cmd);
1632 return NJSC32_RESEL_COMPLETE;
1633 } else if (!TAILQ_EMPTY(&plu->lu_q)) {
1634 /* wait for tag */
1635 sc->sc_stat = NJSC32_STAT_RESEL_LUN;
1636 return NJSC32_RESEL_THROUGH;
1637 }
1638
1639 /* no disconnected commands */
1640 return NJSC32_RESEL_ERROR;
1641 }
1642
1643 static enum njsc32_reselstat
njsc32_resel_tag(struct njsc32_softc * sc,int tag,struct njsc32_cmd ** pcmd)1644 njsc32_resel_tag(struct njsc32_softc *sc, int tag, struct njsc32_cmd **pcmd)
1645 {
1646 struct njsc32_cmd_head *head;
1647 struct njsc32_cmd *cmd;
1648
1649 TPRINTF(("%s: njsc32_resel_tag: reselection tag %d\n",
1650 device_xname(sc->sc_dev), tag));
1651 if (sc->sc_stat != NJSC32_STAT_RESEL_LUN)
1652 return NJSC32_RESEL_ERROR;
1653
1654 head = &sc->sc_targets[sc->sc_reselid].t_lus[sc->sc_resellun].lu_q;
1655
1656 /* XXX slow? */
1657 /* search for the command of the tag */
1658 TAILQ_FOREACH(cmd, head, c_q) {
1659 if (cmd->c_xs->xs_tag_id == tag) {
1660 sc->sc_stat = NJSC32_STAT_RECONNECT;
1661 TAILQ_REMOVE(head, cmd, c_q);
1662 *pcmd = cmd;
1663 TPRINTC(cmd, ("njsc32_resel_tag: I_T_L_Q nexus\n"));
1664 njsc32_reconnect(sc, cmd);
1665 return NJSC32_RESEL_COMPLETE;
1666 }
1667 }
1668
1669 /* no disconnected commands */
1670 return NJSC32_RESEL_ERROR;
1671 }
1672
1673 /*
1674 * Reload parameters and restart AutoSCSI.
1675 *
1676 * XXX autoparam doesn't work as expected and we can't use it here.
1677 */
1678 static void
njsc32_cmd_reload(struct njsc32_softc * sc,struct njsc32_cmd * cmd,int cctl)1679 njsc32_cmd_reload(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int cctl)
1680 {
1681 struct njsc32_target *target;
1682
1683 target = cmd->c_target;
1684
1685 /* clear parity error and enable parity detection */
1686 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
1687 NJSC32_PARITYCTL_CHECK_ENABLE | NJSC32_PARITYCTL_CLEAR_ERROR);
1688
1689 /* load parameters */
1690 njsc32_write_1(sc, NJSC32_REG_SYNC, target->t_sync);
1691 njsc32_write_1(sc, NJSC32_REG_ACK_WIDTH, target->t_ackwidth);
1692 njsc32_write_1(sc, NJSC32_REG_SREQ_SAMPLING, target->t_sample);
1693 njsc32_write_4(sc, NJSC32_REG_SGT_ADR, cmd->c_sgtdmaaddr);
1694 #ifdef NJSC32_DUALEDGE
1695 njsc32_write_2(sc, NJSC32_REG_TRANSFER,
1696 cmd->c_xferctl | target->t_xferctl);
1697 #else
1698 njsc32_write_2(sc, NJSC32_REG_TRANSFER, cmd->c_xferctl);
1699 #endif
1700 /* start AutoSCSI */
1701 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
1702
1703 sc->sc_curcmd = cmd;
1704 }
1705
1706 static void
njsc32_update_xfer_mode(struct njsc32_softc * sc,struct njsc32_target * target)1707 njsc32_update_xfer_mode(struct njsc32_softc *sc, struct njsc32_target *target)
1708 {
1709 struct scsipi_xfer_mode xm;
1710
1711 xm.xm_target = target - sc->sc_targets; /* target ID */
1712 xm.xm_mode = 0;
1713 xm.xm_period = target->t_syncperiod;
1714 xm.xm_offset = target->t_syncoffset;
1715 if (xm.xm_offset != 0)
1716 xm.xm_mode |= PERIPH_CAP_SYNC;
1717 if (target->t_flags & NJSC32_TARF_TAG)
1718 xm.xm_mode |= PERIPH_CAP_TQING;
1719
1720 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm);
1721 }
1722
1723 static void
njsc32_msgin(struct njsc32_softc * sc)1724 njsc32_msgin(struct njsc32_softc *sc)
1725 {
1726 u_int8_t msg0, msg;
1727 int msgcnt;
1728 struct njsc32_cmd *cmd;
1729 enum njsc32_reselstat rstat;
1730 int cctl = 0;
1731 u_int32_t ptr; /* unsigned type ensures 2-complement calculation */
1732 u_int32_t msgout = 0;
1733 bool reload_params = FALSE;
1734 struct njsc32_target *target;
1735 int idx, period, offset;
1736
1737 /*
1738 * we are in Message In, so the previous Message Out should have
1739 * been done.
1740 */
1741 njsc32_init_msgout(sc);
1742
1743 /* get a byte of Message In */
1744 msg = njsc32_read_1(sc, NJSC32_REG_DATA_IN);
1745 TPRINTF(("%s: njsc32_msgin: got %#x\n", device_xname(sc->sc_dev), msg));
1746 if ((msgcnt = sc->sc_msgincnt) < NJSC32_MSGIN_LEN)
1747 sc->sc_msginbuf[sc->sc_msgincnt] = msg;
1748
1749 njsc32_assert_ack(sc);
1750
1751 msg0 = sc->sc_msginbuf[0];
1752 cmd = sc->sc_curcmd;
1753
1754 /* check for parity error */
1755 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) &
1756 NJSC32_PARITYSTATUS_ERROR_LSB) {
1757
1758 printf("%s: msgin: parity error\n", device_xname(sc->sc_dev));
1759
1760 /* clear parity error */
1761 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
1762 NJSC32_PARITYCTL_CHECK_ENABLE |
1763 NJSC32_PARITYCTL_CLEAR_ERROR);
1764
1765 /* respond as Message Parity Error */
1766 njsc32_add_msgout(sc, MSG_PARITY_ERROR);
1767
1768 /* clear Message In */
1769 sc->sc_msgincnt = 0;
1770 goto reply;
1771 }
1772
1773 #define WAITNEXTMSG do { sc->sc_msgincnt++; goto restart; } while (0)
1774 #define MSGCOMPLETE do { sc->sc_msgincnt = 0; goto restart; } while (0)
1775 if (MSG_ISIDENTIFY(msg0)) {
1776 /*
1777 * Got Identify message from target.
1778 */
1779 if ((msg0 & ~MSG_IDENTIFY_LUNMASK) != MSG_IDENTIFYFLAG ||
1780 (rstat = njsc32_resel_identify(sc, msg0 &
1781 MSG_IDENTIFY_LUNMASK, &cmd)) == NJSC32_RESEL_ERROR) {
1782 /*
1783 * invalid Identify -> Reject
1784 */
1785 goto reject;
1786 }
1787 if (rstat == NJSC32_RESEL_COMPLETE)
1788 reload_params = TRUE;
1789 MSGCOMPLETE;
1790 }
1791
1792 if (msg0 == MSG_SIMPLE_Q_TAG) {
1793 if (msgcnt == 0)
1794 WAITNEXTMSG;
1795
1796 /* got whole message */
1797 sc->sc_msgincnt = 0;
1798
1799 if ((rstat = njsc32_resel_tag(sc, sc->sc_msginbuf[1], &cmd))
1800 == NJSC32_RESEL_ERROR) {
1801 /*
1802 * invalid Simple Queue Tag -> Abort Tag
1803 */
1804 printf("%s: msgin: invalid tag\n",
1805 device_xname(sc->sc_dev));
1806 njsc32_add_msgout(sc, MSG_ABORT_TAG);
1807 goto reply;
1808 }
1809 if (rstat == NJSC32_RESEL_COMPLETE)
1810 reload_params = TRUE;
1811 MSGCOMPLETE;
1812 }
1813
1814 /* I_T_L or I_T_L_Q nexus should be established now */
1815 if (cmd == NULL) {
1816 printf("%s: msgin %#x without nexus -- sending abort\n",
1817 device_xname(sc->sc_dev), msg0);
1818 njsc32_add_msgout(sc, MSG_ABORT);
1819 goto reply;
1820 }
1821
1822 /*
1823 * extended message
1824 * 0x01 <length (0 stands for 256)> <length bytes>
1825 * (<code> [<parameter> ...])
1826 */
1827 #define EXTLENOFF 1
1828 #define EXTCODEOFF 2
1829 if (msg0 == MSG_EXTENDED) {
1830 if (msgcnt < EXTLENOFF ||
1831 msgcnt < EXTLENOFF + 1 +
1832 (u_int8_t)(sc->sc_msginbuf[EXTLENOFF] - 1))
1833 WAITNEXTMSG;
1834
1835 /* got whole message */
1836 sc->sc_msgincnt = 0;
1837
1838 switch (sc->sc_msginbuf[EXTCODEOFF]) {
1839 case 0: /* Modify Data Pointer */
1840 if (msgcnt != 5 + EXTCODEOFF - 1)
1841 break;
1842 /*
1843 * parameter is 32bit big-endian signed (2-complement)
1844 * value
1845 */
1846 ptr = (sc->sc_msginbuf[EXTCODEOFF + 1] << 24) |
1847 (sc->sc_msginbuf[EXTCODEOFF + 2] << 16) |
1848 (sc->sc_msginbuf[EXTCODEOFF + 3] << 8) |
1849 sc->sc_msginbuf[EXTCODEOFF + 4];
1850
1851 /* new pointer */
1852 ptr += cmd->c_dp_cur; /* ignore overflow */
1853
1854 /* reject if ptr is not in data buffer */
1855 if (ptr > cmd->c_datacnt)
1856 break;
1857
1858 njsc32_set_ptr(sc, cmd, ptr);
1859 goto restart;
1860
1861 case MSG_EXT_SDTR: /* Synchronous Data Transfer Request */
1862 DPRINTC(cmd, ("SDTR %#x %#x\n",
1863 sc->sc_msginbuf[EXTCODEOFF + 1],
1864 sc->sc_msginbuf[EXTCODEOFF + 2]));
1865 if (msgcnt != MSG_EXT_SDTR_LEN + EXTCODEOFF-1)
1866 break; /* reject */
1867
1868 target = cmd->c_target;
1869
1870 /* lookup sync period parameters */
1871 period = sc->sc_msginbuf[EXTCODEOFF + 1];
1872 for (idx = sc->sc_sync_max; idx < NJSC32_NSYNCT; idx++)
1873 if (sc->sc_synct[idx].sp_period >= period) {
1874 period = sc->sc_synct[idx].sp_period;
1875 break;
1876 }
1877 if (idx >= NJSC32_NSYNCT) {
1878 /*
1879 * We can't meet the timing condition that
1880 * the target requests -- use async.
1881 */
1882 njsc32_target_async(sc, target);
1883 njsc32_update_xfer_mode(sc, target);
1884 if (target->t_state == NJSC32_TARST_SDTR) {
1885 /*
1886 * We started SDTR exchange -- start
1887 * negotiation again and request async.
1888 */
1889 target->t_state = NJSC32_TARST_ASYNC;
1890 njsc32_negotiate_xfer(sc, target);
1891 goto reply;
1892 } else {
1893 /*
1894 * The target started SDTR exchange
1895 * -- just reject and fallback
1896 * to async.
1897 */
1898 goto reject;
1899 }
1900 }
1901
1902 /* check sync offset */
1903 offset = sc->sc_msginbuf[EXTCODEOFF + 2];
1904 if (offset > NJSC32_SYNCOFFSET_MAX) {
1905 if (target->t_state == NJSC32_TARST_SDTR) {
1906 printf("%s: wrong sync offset: %d\n",
1907 device_xname(sc->sc_dev), offset);
1908 /* XXX what to do? */
1909 }
1910 offset = NJSC32_SYNCOFFSET_MAX;
1911 }
1912
1913 target->t_ackwidth = sc->sc_synct[idx].sp_ackw;
1914 target->t_sample = sc->sc_synct[idx].sp_sample;
1915 target->t_syncperiod = period;
1916 target->t_syncoffset = offset;
1917 target->t_sync = NJSC32_SYNC_VAL(idx, offset);
1918 njsc32_update_xfer_mode(sc, target);
1919
1920 if (target->t_state == NJSC32_TARST_SDTR) {
1921 target->t_state = NJSC32_TARST_DONE;
1922 } else {
1923 njsc32_msgout_sdtr(sc, period, offset);
1924 goto reply;
1925 }
1926 goto restart;
1927
1928 case MSG_EXT_WDTR: /* Wide Data Transfer Request */
1929 DPRINTC(cmd,
1930 ("WDTR %#x\n", sc->sc_msginbuf[EXTCODEOFF + 1]));
1931 #ifdef NJSC32_DUALEDGE
1932 if (msgcnt != MSG_EXT_WDTR_LEN + EXTCODEOFF-1)
1933 break; /* reject */
1934
1935 /*
1936 * T->I of this message is not used for
1937 * DualEdge negotiation, so the device
1938 * must not be a DualEdge device.
1939 *
1940 * XXX correct?
1941 */
1942 target = cmd->c_target;
1943 target->t_xferctl = 0;
1944
1945 switch (target->t_state) {
1946 case NJSC32_TARST_DE:
1947 if (sc->sc_msginbuf[EXTCODEOFF + 1] !=
1948 MSG_EXT_WDTR_BUS_8_BIT) {
1949 /*
1950 * Oops, we got unexpected WDTR.
1951 * Negotiate for 8bit.
1952 */
1953 target->t_state = NJSC32_TARST_WDTR;
1954 } else {
1955 target->t_state = NJSC32_TARST_SDTR;
1956 }
1957 njsc32_negotiate_xfer(sc, target);
1958 goto reply;
1959
1960 case NJSC32_TARST_WDTR:
1961 if (sc->sc_msginbuf[EXTCODEOFF + 1] !=
1962 MSG_EXT_WDTR_BUS_8_BIT) {
1963 printf("%s: unexpected transfer width:"
1964 " %#x\n", device_xname(sc->sc_dev),
1965 sc->sc_msginbuf[EXTCODEOFF + 1]);
1966 /* XXX what to do? */
1967 }
1968 target->t_state = NJSC32_TARST_SDTR;
1969 njsc32_negotiate_xfer(sc, target);
1970 goto reply;
1971
1972 default:
1973 /* the target started WDTR exchange */
1974 DPRINTC(cmd, ("WDTR from target\n"));
1975
1976 target->t_state = NJSC32_TARST_SDTR;
1977 njsc32_target_async(sc, target);
1978
1979 break; /* reject the WDTR (8bit transfer) */
1980 }
1981 #endif /* NJSC32_DUALEDGE */
1982 break; /* reject */
1983 }
1984 DPRINTC(cmd, ("njsc32_msgin: reject ext msg %#x msgincnt %d\n",
1985 sc->sc_msginbuf[EXTCODEOFF], msgcnt));
1986 goto reject;
1987 }
1988
1989 /* 2byte messages */
1990 if (MSG_IS2BYTE(msg0)) {
1991 if (msgcnt == 0)
1992 WAITNEXTMSG;
1993
1994 /* got whole message */
1995 sc->sc_msgincnt = 0;
1996 }
1997
1998 switch (msg0) {
1999 case MSG_CMDCOMPLETE: /* 0x00 */
2000 case MSG_SAVEDATAPOINTER: /* 0x02 */
2001 case MSG_DISCONNECT: /* 0x04 */
2002 /* handled by AutoSCSI */
2003 PRINTC(cmd, ("msgin: unexpected msg: %#x\n", msg0));
2004 break;
2005
2006 case MSG_RESTOREPOINTERS: /* 0x03 */
2007 /* restore data pointer to what was saved */
2008 DPRINTC(cmd, ("njsc32_msgin: Restore Pointers\n"));
2009 njsc32_set_ptr(sc, cmd, cmd->c_dp_saved);
2010 reload_params = TRUE;
2011 MSGCOMPLETE;
2012 /* NOTREACHED */
2013 break;
2014
2015 #if 0 /* handled above */
2016 case MSG_EXTENDED: /* 0x01 */
2017 #endif
2018 case MSG_MESSAGE_REJECT: /* 0x07 */
2019 target = cmd->c_target;
2020 DPRINTC(cmd, ("Reject tarst %d\n", target->t_state));
2021 switch (target->t_state) {
2022 #ifdef NJSC32_DUALEDGE
2023 case NJSC32_TARST_WDTR:
2024 case NJSC32_TARST_DE:
2025 target->t_xferctl = 0;
2026 target->t_state = NJSC32_TARST_SDTR;
2027 njsc32_negotiate_xfer(sc, target);
2028 goto reply;
2029 #endif
2030 case NJSC32_TARST_SDTR:
2031 case NJSC32_TARST_ASYNC:
2032 njsc32_target_async(sc, target);
2033 target->t_state = NJSC32_TARST_DONE;
2034 njsc32_update_xfer_mode(sc, target);
2035 break;
2036 default:
2037 break;
2038 }
2039 goto restart;
2040
2041 case MSG_NOOP: /* 0x08 */
2042 #ifdef NJSC32_DUALEDGE
2043 target = cmd->c_target;
2044 if (target->t_state == NJSC32_TARST_DE) {
2045 printf("%s: DualEdge transfer\n",
2046 device_xname(sc->sc_dev));
2047 target->t_xferctl = NJSC32_XFR_DUALEDGE_ENABLE;
2048 /* go to next negotiation */
2049 target->t_state = NJSC32_TARST_SDTR;
2050 njsc32_negotiate_xfer(sc, target);
2051 goto reply;
2052 }
2053 #endif
2054 goto restart;
2055
2056 case MSG_INITIATOR_DET_ERR: /* 0x05 I->T only */
2057 case MSG_ABORT: /* 0x06 I->T only */
2058 case MSG_PARITY_ERROR: /* 0x09 I->T only */
2059 case MSG_LINK_CMD_COMPLETE: /* 0x0a */
2060 case MSG_LINK_CMD_COMPLETEF: /* 0x0b */
2061 case MSG_BUS_DEV_RESET: /* 0x0c I->T only */
2062 case MSG_ABORT_TAG: /* 0x0d I->T only */
2063 case MSG_CLEAR_QUEUE: /* 0x0e I->T only */
2064
2065 #if 0 /* handled above */
2066 case MSG_SIMPLE_Q_TAG: /* 0x20 */
2067 #endif
2068 case MSG_HEAD_OF_Q_TAG: /* 0x21 I->T only */
2069 case MSG_ORDERED_Q_TAG: /* 0x22 I->T only */
2070 case MSG_IGN_WIDE_RESIDUE: /* 0x23 */
2071
2072 default:
2073 #ifdef NJSC32_DEBUG
2074 PRINTC(cmd, ("msgin: unsupported msg: %#x", msg0));
2075 if (MSG_IS2BYTE(msg0))
2076 printf(" %#x", msg);
2077 printf("\n");
2078 #endif
2079 break;
2080 }
2081
2082 reject:
2083 njsc32_add_msgout(sc, MSG_MESSAGE_REJECT);
2084
2085 reply:
2086 msgout = njsc32_get_auto_msgout(sc);
2087
2088 restart:
2089 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
2090 NJSC32_CMD_AUTO_COMMAND_PHASE |
2091 NJSC32_CMD_AUTO_SCSI_RESTART;
2092
2093 /*
2094 * Be careful the second and latter bytes of Message In
2095 * shall not be absorbed by AutoSCSI.
2096 */
2097 if (sc->sc_msgincnt == 0)
2098 cctl |= NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02;
2099
2100 if (sc->sc_msgoutlen != 0)
2101 cctl |= NJSC32_CMD_AUTO_ATN;
2102
2103 njsc32_write_4(sc, NJSC32_REG_SCSI_MSG_OUT, msgout);
2104
2105 /* (re)start AutoSCSI (may assert ATN) */
2106 if (reload_params) {
2107 njsc32_cmd_reload(sc, cmd, cctl);
2108 } else {
2109 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2110 }
2111
2112 /* +ATN -> -REQ: need 90ns delay? */
2113
2114 njsc32_wait_req_negate(sc); /* wait for REQ negation */
2115
2116 njsc32_negate_ack(sc);
2117
2118 return;
2119 }
2120
2121 static void
njsc32_msgout(struct njsc32_softc * sc)2122 njsc32_msgout(struct njsc32_softc *sc)
2123 {
2124 int cctl;
2125 u_int8_t bus;
2126 unsigned n;
2127
2128 if (sc->sc_msgoutlen == 0) {
2129 /* target entered to Message Out on unexpected timing */
2130 njsc32_add_msgout(sc, MSG_NOOP);
2131 }
2132
2133 cctl = NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
2134 NJSC32_CMD_AUTO_COMMAND_PHASE | NJSC32_CMD_AUTO_SCSI_RESTART |
2135 NJSC32_CMD_AUTO_MSGIN_00_04 | NJSC32_CMD_AUTO_MSGIN_02;
2136
2137 /* make sure target is in Message Out phase */
2138 bus = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR);
2139 if ((bus & NJSC32_BUSMON_PHASE_MASK) != NJSC32_PHASE_MESSAGE_OUT) {
2140 /*
2141 * Message Out is aborted by target.
2142 */
2143 printf("%s: njsc32_msgout: phase change %#x\n",
2144 device_xname(sc->sc_dev), bus);
2145
2146 /* XXX what to do? */
2147
2148 /* restart AutoSCSI (negate ATN) */
2149 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2150
2151 sc->sc_msgoutidx = 0;
2152 return;
2153 }
2154
2155 n = sc->sc_msgoutidx;
2156 if (n == sc->sc_msgoutlen - 1) {
2157 /*
2158 * negate ATN before sending ACK
2159 */
2160 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, 0);
2161
2162 sc->sc_msgoutidx = 0; /* target may retry Message Out */
2163 } else {
2164 cctl |= NJSC32_CMD_AUTO_ATN;
2165 sc->sc_msgoutidx++;
2166 }
2167
2168 /* Send Message Out */
2169 njsc32_write_1(sc, NJSC32_REG_SCSI_OUT_LATCH, sc->sc_msgout[n]);
2170
2171 /* DBn -> +ACK: need 55ns delay? */
2172
2173 njsc32_assert_ack(sc);
2174 njsc32_wait_req_negate(sc); /* wait for REQ negation */
2175
2176 /* restart AutoSCSI */
2177 njsc32_write_2(sc, NJSC32_REG_COMMAND_CONTROL, cctl);
2178
2179 njsc32_negate_ack(sc);
2180
2181 /*
2182 * do not reset sc->sc_msgoutlen so the target
2183 * can retry Message Out phase
2184 */
2185 }
2186
2187 static void
njsc32_cmdtimeout(void * arg)2188 njsc32_cmdtimeout(void *arg)
2189 {
2190 struct njsc32_cmd *cmd = arg;
2191 struct njsc32_softc *sc;
2192 int s;
2193
2194 PRINTC(cmd, ("command timeout\n"));
2195
2196 sc = cmd->c_sc;
2197
2198 s = splbio();
2199
2200 if (sc->sc_stat == NJSC32_STAT_ARBIT)
2201 njsc32_arbitration_failed(sc);
2202 else {
2203 sc->sc_curcmd = NULL;
2204 sc->sc_stat = NJSC32_STAT_IDLE;
2205 njsc32_end_cmd(sc, cmd, XS_TIMEOUT);
2206 }
2207
2208 /* XXX? */
2209 njsc32_init(sc, 1); /* bus reset */
2210
2211 splx(s);
2212 }
2213
2214 static void
njsc32_reseltimeout(void * arg)2215 njsc32_reseltimeout(void *arg)
2216 {
2217 struct njsc32_cmd *cmd = arg;
2218 struct njsc32_softc *sc;
2219 int s;
2220
2221 PRINTC(cmd, ("reselection timeout\n"));
2222
2223 sc = cmd->c_sc;
2224
2225 s = splbio();
2226
2227 /* remove from disconnected list */
2228 if (cmd->c_flags & NJSC32_CMD_TAGGED) {
2229 /* I_T_L_Q */
2230 KASSERT(cmd->c_lu->lu_cmd == NULL);
2231 TAILQ_REMOVE(&cmd->c_lu->lu_q, cmd, c_q);
2232 } else {
2233 /* I_T_L */
2234 KASSERT(cmd->c_lu->lu_cmd == cmd);
2235 cmd->c_lu->lu_cmd = NULL;
2236 }
2237
2238 njsc32_end_cmd(sc, cmd, XS_TIMEOUT);
2239
2240 /* XXX? */
2241 njsc32_init(sc, 1); /* bus reset */
2242
2243 splx(s);
2244 }
2245
2246 static inline void
njsc32_end_auto(struct njsc32_softc * sc,struct njsc32_cmd * cmd,int auto_phase)2247 njsc32_end_auto(struct njsc32_softc *sc, struct njsc32_cmd *cmd, int auto_phase)
2248 {
2249 struct scsipi_xfer *xs;
2250
2251 if (auto_phase & NJSC32_XPHASE_MSGIN_02) {
2252 /* Message In: 0x02 Save Data Pointer */
2253
2254 /*
2255 * Adjust saved data pointer
2256 * if the command is not completed yet.
2257 */
2258 if ((auto_phase & NJSC32_XPHASE_MSGIN_00) == 0 &&
2259 (auto_phase &
2260 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) != 0) {
2261 njsc32_save_ptr(cmd);
2262 }
2263 TPRINTF(("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n",
2264 njsc32_read_4(sc, NJSC32_REG_BM_CNT),
2265 njsc32_read_4(sc, NJSC32_REG_SGT_ADR),
2266 njsc32_read_4(sc, NJSC32_REG_SACK_CNT),
2267 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT)));
2268 }
2269
2270 xs = cmd->c_xs;
2271
2272 if (auto_phase & NJSC32_XPHASE_MSGIN_00) {
2273 /* Command Complete */
2274 TPRINTC(cmd, ("njsc32_intr: Command Complete\n"));
2275 switch (xs->status) {
2276 case SCSI_CHECK: case SCSI_QUEUE_FULL: case SCSI_BUSY:
2277 /*
2278 * scsipi layer will automatically handle the error
2279 */
2280 njsc32_end_cmd(sc, cmd, XS_BUSY);
2281 break;
2282 default:
2283 xs->resid -= cmd->c_dp_max;
2284 njsc32_end_cmd(sc, cmd, XS_NOERROR);
2285 break;
2286 }
2287 } else if (auto_phase & NJSC32_XPHASE_MSGIN_04) {
2288 /* Disconnect */
2289 TPRINTC(cmd, ("njsc32_intr: Disconnect\n"));
2290
2291 /* for ill-designed devices */
2292 if ((xs->xs_periph->periph_quirks & PQUIRK_AUTOSAVE) != 0)
2293 njsc32_save_ptr(cmd);
2294
2295 /*
2296 * move current cmd to disconnected list
2297 */
2298 if (cmd->c_flags & NJSC32_CMD_TAGGED) {
2299 /* I_T_L_Q */
2300 if (cmd->c_flags & NJSC32_CMD_TAGGED_HEAD)
2301 TAILQ_INSERT_HEAD(&cmd->c_lu->lu_q, cmd, c_q);
2302 else
2303 TAILQ_INSERT_TAIL(&cmd->c_lu->lu_q, cmd, c_q);
2304 } else {
2305 /* I_T_L */
2306 cmd->c_lu->lu_cmd = cmd;
2307 }
2308
2309 /*
2310 * schedule timeout -- avoid being
2311 * disconnected forever
2312 */
2313 if ((xs->xs_control & XS_CTL_POLL) == 0) {
2314 callout_stop(&xs->xs_callout);
2315 callout_reset(&xs->xs_callout, mstohz(xs->timeout),
2316 njsc32_reseltimeout, cmd);
2317 }
2318
2319 } else {
2320 /*
2321 * target has come to Bus Free phase
2322 * probably to notify an error
2323 */
2324 PRINTC(cmd, ("njsc32_intr: unexpected bus free\n"));
2325 /* try Request Sense */
2326 xs->status = SCSI_CHECK;
2327 njsc32_end_cmd(sc, cmd, XS_BUSY);
2328 }
2329 }
2330
2331 int
njsc32_intr(void * arg)2332 njsc32_intr(void *arg)
2333 {
2334 struct njsc32_softc *sc = arg;
2335 u_int16_t intr;
2336 u_int8_t arbstat, bus_phase;
2337 int auto_phase;
2338 int idbit;
2339 struct njsc32_cmd *cmd;
2340
2341 intr = njsc32_read_2(sc, NJSC32_REG_IRQ);
2342 if ((intr & NJSC32_IRQ_INTR_PENDING) == 0)
2343 return 0; /* not mine */
2344
2345 TPRINTF(("%s: njsc32_intr: %#x\n", device_xname(sc->sc_dev), intr));
2346
2347 #if 0 /* I don't think this is required */
2348 /* mask interrupts */
2349 njsc32_write_2(sc, NJSC32_REG_IRQ, NJSC32_IRQ_MASK_ALL);
2350 #endif
2351
2352 /* we got an interrupt, so stop the timer */
2353 njsc32_write_2(sc, NJSC32_REG_TIMER, NJSC32_TIMER_STOP);
2354
2355 if (intr & NJSC32_IRQ_SCSIRESET) {
2356 printf("%s: detected bus reset\n", device_xname(sc->sc_dev));
2357 /* make sure all devices on the bus are certainly reset */
2358 njsc32_reset_bus(sc);
2359 goto out;
2360 }
2361
2362 if (sc->sc_stat == NJSC32_STAT_ARBIT) {
2363 cmd = sc->sc_curcmd;
2364 KASSERT(cmd);
2365 arbstat = njsc32_read_1(sc, NJSC32_REG_ARBITRATION_STAT);
2366 if (arbstat & (NJSC32_ARBSTAT_WIN | NJSC32_ARBSTAT_FAIL)) {
2367 /*
2368 * arbitration done
2369 */
2370 /* clear arbitration status */
2371 njsc32_write_1(sc, NJSC32_REG_SET_ARBITRATION,
2372 NJSC32_SETARB_CLEAR);
2373
2374 if (arbstat & NJSC32_ARBSTAT_WIN) {
2375 TPRINTC(cmd,
2376 ("njsc32_intr: arbitration won\n"));
2377
2378 TAILQ_REMOVE(&sc->sc_reqcmd, cmd, c_q);
2379
2380 sc->sc_stat = NJSC32_STAT_CONNECT;
2381 } else {
2382 TPRINTC(cmd,
2383 ("njsc32_intr: arbitration failed\n"));
2384
2385 njsc32_arbitration_failed(sc);
2386
2387 /* XXX delay */
2388 /* XXX retry counter */
2389 }
2390 }
2391 }
2392
2393 if (intr & NJSC32_IRQ_TIMER) {
2394 TPRINTF(("%s: njsc32_intr: timer interrupt\n",
2395 device_xname(sc->sc_dev)));
2396 }
2397
2398 if (intr & NJSC32_IRQ_RESELECT) {
2399 /* Reselection from a target */
2400 njsc32_arbitration_failed(sc); /* just in case */
2401 if ((cmd = sc->sc_curcmd) != NULL) {
2402 /* ? */
2403 printf("%s: unexpected reselection\n",
2404 device_xname(sc->sc_dev));
2405 sc->sc_curcmd = NULL;
2406 sc->sc_stat = NJSC32_STAT_IDLE;
2407 njsc32_end_cmd(sc, cmd, XS_DRIVER_STUFFUP);
2408 }
2409
2410 idbit = njsc32_read_1(sc, NJSC32_REG_RESELECT_ID);
2411 if ((idbit & (1 << NJSC32_INITIATOR_ID)) == 0 ||
2412 (sc->sc_reselid =
2413 ffs(idbit & ~(1 << NJSC32_INITIATOR_ID)) - 1) < 0) {
2414 printf("%s: invalid reselection (id: %#x)\n",
2415 device_xname(sc->sc_dev), idbit);
2416 sc->sc_stat = NJSC32_STAT_IDLE; /* XXX ? */
2417 } else {
2418 sc->sc_stat = NJSC32_STAT_RESEL;
2419 TPRINTF(("%s: njsc32_intr: reselection from %d\n",
2420 device_xname(sc->sc_dev), sc->sc_reselid));
2421 }
2422 }
2423
2424 if (intr & NJSC32_IRQ_PHASE_CHANGE) {
2425 #if 1 /* XXX probably not needed */
2426 if (sc->sc_stat == NJSC32_STAT_ARBIT)
2427 PRINTC(sc->sc_curcmd,
2428 ("njsc32_intr: cancel arbitration phase\n"));
2429 njsc32_arbitration_failed(sc);
2430 #endif
2431 /* current bus phase */
2432 bus_phase = njsc32_read_1(sc, NJSC32_REG_SCSI_BUS_MONITOR) &
2433 NJSC32_BUSMON_PHASE_MASK;
2434
2435 switch (bus_phase) {
2436 case NJSC32_PHASE_MESSAGE_IN:
2437 njsc32_msgin(sc);
2438 break;
2439
2440 /*
2441 * target may suddenly become Status / Bus Free phase
2442 * to notify an error condition
2443 */
2444 case NJSC32_PHASE_STATUS:
2445 printf("%s: unexpected bus phase: Status\n",
2446 device_xname(sc->sc_dev));
2447 if ((cmd = sc->sc_curcmd) != NULL) {
2448 cmd->c_xs->status =
2449 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN);
2450 TPRINTC(cmd, ("njsc32_intr: Status %d\n",
2451 cmd->c_xs->status));
2452 }
2453 break;
2454 case NJSC32_PHASE_BUSFREE:
2455 printf("%s: unexpected bus phase: Bus Free\n",
2456 device_xname(sc->sc_dev));
2457 if ((cmd = sc->sc_curcmd) != NULL) {
2458 sc->sc_curcmd = NULL;
2459 sc->sc_stat = NJSC32_STAT_IDLE;
2460 if (cmd->c_xs->status != SCSI_QUEUE_FULL &&
2461 cmd->c_xs->status != SCSI_BUSY)
2462 cmd->c_xs->status = SCSI_CHECK;/* XXX */
2463 njsc32_end_cmd(sc, cmd, XS_BUSY);
2464 }
2465 goto out;
2466 default:
2467 #ifdef NJSC32_DEBUG
2468 printf("%s: unexpected bus phase: ",
2469 device_xname(sc->sc_dev));
2470 switch (bus_phase) {
2471 case NJSC32_PHASE_COMMAND:
2472 printf("Command\n");
2473 break;
2474 case NJSC32_PHASE_MESSAGE_OUT:
2475 printf("Message Out\n");
2476 break;
2477 case NJSC32_PHASE_DATA_IN:
2478 printf("Data In\n");
2479 break;
2480 case NJSC32_PHASE_DATA_OUT:
2481 printf("Data Out\n");
2482 break;
2483 case NJSC32_PHASE_RESELECT:
2484 printf("Reselect\n");
2485 break;
2486 default:
2487 printf("%#x\n", bus_phase);
2488 break;
2489 }
2490 #else
2491 printf("%s: unexpected bus phase: %#x",
2492 device_xname(sc->sc_dev), bus_phase);
2493 #endif
2494 break;
2495 }
2496 }
2497
2498 if (intr & NJSC32_IRQ_AUTOSCSI) {
2499 /*
2500 * AutoSCSI interrupt
2501 */
2502 auto_phase = njsc32_read_2(sc, NJSC32_REG_EXECUTE_PHASE);
2503 TPRINTF(("%s: njsc32_intr: AutoSCSI: %#x\n",
2504 device_xname(sc->sc_dev), auto_phase));
2505 njsc32_write_2(sc, NJSC32_REG_EXECUTE_PHASE, 0);
2506
2507 if (auto_phase & NJSC32_XPHASE_SEL_TIMEOUT) {
2508 cmd = sc->sc_curcmd;
2509 if (cmd == NULL) {
2510 printf("%s: sel no cmd\n",
2511 device_xname(sc->sc_dev));
2512 goto out;
2513 }
2514 DPRINTC(cmd, ("njsc32_intr: selection timeout\n"));
2515
2516 sc->sc_curcmd = NULL;
2517 sc->sc_stat = NJSC32_STAT_IDLE;
2518 njsc32_end_cmd(sc, cmd, XS_SELTIMEOUT);
2519
2520 goto out;
2521 }
2522
2523 #ifdef NJSC32_TRACE
2524 if (auto_phase & NJSC32_XPHASE_COMMAND) {
2525 /* Command phase has been automatically processed */
2526 TPRINTF(("%s: njsc32_intr: Command\n",
2527 device_xname(sc->sc_dev)));
2528 }
2529 #endif
2530 #ifdef NJSC32_DEBUG
2531 if (auto_phase & NJSC32_XPHASE_ILLEGAL) {
2532 printf("%s: njsc32_intr: Illegal phase\n",
2533 device_xname(sc->sc_dev));
2534 }
2535 #endif
2536
2537 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) {
2538 TPRINTF(("%s: njsc32_intr: Process Message In\n",
2539 device_xname(sc->sc_dev)));
2540 njsc32_msgin(sc);
2541 }
2542
2543 if (auto_phase & NJSC32_XPHASE_PAUSED_MSG_OUT) {
2544 TPRINTF(("%s: njsc32_intr: Process Message Out\n",
2545 device_xname(sc->sc_dev)));
2546 njsc32_msgout(sc);
2547 }
2548
2549 cmd = sc->sc_curcmd;
2550 if (cmd == NULL) {
2551 TPRINTF(("%s: njsc32_intr: no cmd\n",
2552 device_xname(sc->sc_dev)));
2553 goto out;
2554 }
2555
2556 if (auto_phase &
2557 (NJSC32_XPHASE_DATA_IN | NJSC32_XPHASE_DATA_OUT)) {
2558 u_int32_t sackcnt, cntoffset;
2559
2560 #ifdef NJSC32_TRACE
2561 if (auto_phase & NJSC32_XPHASE_DATA_IN)
2562 PRINTC(cmd, ("njsc32_intr: data in done\n"));
2563 if (auto_phase & NJSC32_XPHASE_DATA_OUT)
2564 PRINTC(cmd, ("njsc32_intr: data out done\n"));
2565 printf("BM %u, SGT %u, SACK %u, SAVED_ACK %u\n",
2566 njsc32_read_4(sc, NJSC32_REG_BM_CNT),
2567 njsc32_read_4(sc, NJSC32_REG_SGT_ADR),
2568 njsc32_read_4(sc, NJSC32_REG_SACK_CNT),
2569 njsc32_read_4(sc, NJSC32_REG_SAVED_ACK_CNT));
2570 #endif
2571
2572 /*
2573 * detected parity error on data transfer?
2574 */
2575 if (njsc32_read_1(sc, NJSC32_REG_PARITY_STATUS) &
2576 (NJSC32_PARITYSTATUS_ERROR_LSB|
2577 NJSC32_PARITYSTATUS_ERROR_MSB)) {
2578
2579 PRINTC(cmd, ("datain: parity error\n"));
2580
2581 /* clear parity error */
2582 njsc32_write_1(sc, NJSC32_REG_PARITY_CONTROL,
2583 NJSC32_PARITYCTL_CHECK_ENABLE |
2584 NJSC32_PARITYCTL_CLEAR_ERROR);
2585
2586 if (auto_phase & NJSC32_XPHASE_BUS_FREE) {
2587 /*
2588 * XXX command has already finished
2589 * -- what can we do?
2590 *
2591 * It is not clear current command
2592 * caused the error -- reset everything.
2593 */
2594 njsc32_init(sc, 1); /* XXX */
2595 } else {
2596 /* XXX does this case occur? */
2597 #if 1
2598 printf("%s: datain: parity error\n",
2599 device_xname(sc->sc_dev));
2600 #endif
2601 /*
2602 * Make attention condition and try
2603 * to send Initiator Detected Error
2604 * message.
2605 */
2606 njsc32_init_msgout(sc);
2607 njsc32_add_msgout(sc,
2608 MSG_INITIATOR_DET_ERR);
2609 njsc32_write_4(sc,
2610 NJSC32_REG_SCSI_MSG_OUT,
2611 njsc32_get_auto_msgout(sc));
2612 /* restart autoscsi with ATN */
2613 njsc32_write_2(sc,
2614 NJSC32_REG_COMMAND_CONTROL,
2615 NJSC32_CMD_CLEAR_CDB_FIFO_PTR |
2616 NJSC32_CMD_AUTO_COMMAND_PHASE |
2617 NJSC32_CMD_AUTO_SCSI_RESTART |
2618 NJSC32_CMD_AUTO_MSGIN_00_04 |
2619 NJSC32_CMD_AUTO_MSGIN_02 |
2620 NJSC32_CMD_AUTO_ATN);
2621 }
2622 goto out;
2623 }
2624
2625 /*
2626 * data has been transferred, and current pointer
2627 * is changed
2628 */
2629 sackcnt = njsc32_read_4(sc, NJSC32_REG_SACK_CNT);
2630
2631 /*
2632 * The controller returns extra ACK count
2633 * if the DMA buffer is not 4byte aligned.
2634 */
2635 cntoffset = le32toh(cmd->c_sgt[0].sg_addr) & 3;
2636 #ifdef NJSC32_DEBUG
2637 if (cntoffset != 0) {
2638 printf("sackcnt %u, cntoffset %u\n",
2639 sackcnt, cntoffset);
2640 }
2641 #endif
2642 /* advance SCSI pointer */
2643 njsc32_set_cur_ptr(cmd,
2644 cmd->c_dp_cur + sackcnt - cntoffset);
2645 }
2646
2647 if (auto_phase & NJSC32_XPHASE_MSGOUT) {
2648 /* Message Out phase has been automatically processed */
2649 TPRINTC(cmd, ("njsc32_intr: Message Out\n"));
2650 if ((auto_phase & NJSC32_XPHASE_PAUSED_MSG_IN) == 0 &&
2651 sc->sc_msgoutlen <= NJSC32_MSGOUT_MAX_AUTO) {
2652 njsc32_init_msgout(sc);
2653 }
2654 }
2655
2656 if (auto_phase & NJSC32_XPHASE_STATUS) {
2657 /* Status phase has been automatically processed */
2658 cmd->c_xs->status =
2659 njsc32_read_1(sc, NJSC32_REG_SCSI_CSB_IN);
2660 TPRINTC(cmd, ("njsc32_intr: Status %#x\n",
2661 cmd->c_xs->status));
2662 }
2663
2664 if (auto_phase & NJSC32_XPHASE_BUS_FREE) {
2665 /* AutoSCSI is finished */
2666
2667 TPRINTC(cmd, ("njsc32_intr: Bus Free\n"));
2668
2669 sc->sc_stat = NJSC32_STAT_IDLE;
2670 sc->sc_curcmd = NULL;
2671
2672 njsc32_end_auto(sc, cmd, auto_phase);
2673 }
2674 goto out;
2675 }
2676
2677 if (intr & NJSC32_IRQ_FIFO_THRESHOLD) {
2678 /* XXX We use DMA, and this shouldn't happen */
2679 printf("%s: njsc32_intr: FIFO\n", device_xname(sc->sc_dev));
2680 njsc32_init(sc, 1);
2681 goto out;
2682 }
2683 if (intr & NJSC32_IRQ_PCI) {
2684 /* XXX? */
2685 printf("%s: njsc32_intr: PCI\n", device_xname(sc->sc_dev));
2686 }
2687 if (intr & NJSC32_IRQ_BMCNTERR) {
2688 /* XXX? */
2689 printf("%s: njsc32_intr: BM\n", device_xname(sc->sc_dev));
2690 }
2691
2692 out:
2693 /* go next command if controller is idle */
2694 if (sc->sc_stat == NJSC32_STAT_IDLE)
2695 njsc32_start(sc);
2696
2697 #if 0
2698 /* enable interrupts */
2699 njsc32_write_2(sc, NJSC32_REG_IRQ, 0);
2700 #endif
2701
2702 return 1; /* processed */
2703 }
2704