1 /* savage_drm.h -- Public header for the savage driver
2  *
3  * Copyright 2004  Felix Kuehling
4  * All Rights Reserved.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sub license,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial portions
15  * of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20  * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22  * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  */
25 
26 #ifndef __SAVAGE_DRM_H__
27 #define __SAVAGE_DRM_H__
28 
29 #ifndef __SAVAGE_SAREA_DEFINES__
30 #define __SAVAGE_SAREA_DEFINES__
31 
32 /* 2 heaps (1 for card, 1 for agp), each divided into upto 128
33  * regions, subject to a minimum region size of (1<<16) == 64k.
34  *
35  * Clients may subdivide regions internally, but when sharing between
36  * clients, the region size is the minimum granularity.
37  */
38 
39 #define SAVAGE_CARD_HEAP		0
40 #define SAVAGE_AGP_HEAP			1
41 #define SAVAGE_NR_TEX_HEAPS		2
42 #define SAVAGE_NR_TEX_REGIONS		16
43 #define SAVAGE_LOG_MIN_TEX_REGION_SIZE	16
44 
45 #endif /* __SAVAGE_SAREA_DEFINES__ */
46 
47 typedef struct _drm_savage_sarea {
48 	/* LRU lists for texture memory in agp space and on the card.
49 	 */
50 	struct drm_tex_region texList[SAVAGE_NR_TEX_HEAPS][SAVAGE_NR_TEX_REGIONS+1];
51 	unsigned int texAge[SAVAGE_NR_TEX_HEAPS];
52 
53 	/* Mechanism to validate card state.
54 	 */
55 	int ctxOwner;
56 } drm_savage_sarea_t, *drm_savage_sarea_ptr;
57 
58 /* Savage-specific ioctls
59  */
60 #define DRM_SAVAGE_BCI_INIT		0x00
61 #define DRM_SAVAGE_BCI_CMDBUF           0x01
62 #define DRM_SAVAGE_BCI_EVENT_EMIT	0x02
63 #define DRM_SAVAGE_BCI_EVENT_WAIT	0x03
64 
65 #define DRM_IOCTL_SAVAGE_INIT		DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_INIT, drm_savage_init_t)
66 #define DRM_IOCTL_SAVAGE_CMDBUF		DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_CMDBUF, drm_savage_cmdbuf_t)
67 #define DRM_IOCTL_SAVAGE_EVENT_EMIT	DRM_IOWR(DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_EMIT, drm_savage_event_emit_t)
68 #define DRM_IOCTL_SAVAGE_EVENT_WAIT	DRM_IOW( DRM_COMMAND_BASE + DRM_SAVAGE_BCI_EVENT_WAIT, drm_savage_event_wait_t)
69 
70 #define SAVAGE_DMA_PCI	1
71 #define SAVAGE_DMA_AGP	3
72 typedef struct drm_savage_init {
73 	enum {
74 		SAVAGE_INIT_BCI = 1,
75 		SAVAGE_CLEANUP_BCI = 2
76 	} func;
77 	unsigned int sarea_priv_offset;
78 
79 	/* some parameters */
80 	unsigned int cob_size;
81 	unsigned int bci_threshold_lo, bci_threshold_hi;
82 	unsigned int dma_type;
83 
84 	/* frame buffer layout */
85 	unsigned int fb_bpp;
86 	unsigned int front_offset, front_pitch;
87 	unsigned int back_offset, back_pitch;
88 	unsigned int depth_bpp;
89 	unsigned int depth_offset, depth_pitch;
90 
91 	/* local textures */
92 	unsigned int texture_offset;
93 	unsigned int texture_size;
94 
95 	/* physical locations of non-permanent maps */
96 	unsigned long status_offset;
97 	unsigned long buffers_offset;
98 	unsigned long agp_textures_offset;
99 	unsigned long cmd_dma_offset;
100 } drm_savage_init_t;
101 
102 typedef union drm_savage_cmd_header drm_savage_cmd_header_t;
103 typedef struct drm_savage_cmdbuf {
104 				/* command buffer in client's address space */
105 	drm_savage_cmd_header_t __user *cmd_addr;
106 	unsigned int size;	/* size of the command buffer in 64bit units */
107 
108 	unsigned int dma_idx;	/* DMA buffer index to use */
109 	int discard;		/* discard DMA buffer when done */
110 				/* vertex buffer in client's address space */
111 	unsigned int __user *vb_addr;
112 	unsigned int vb_size;	/* size of client vertex buffer in bytes */
113 	unsigned int vb_stride;	/* stride of vertices in 32bit words */
114 				/* boxes in client's address space */
115 	struct drm_clip_rect __user *box_addr;
116 	unsigned int nbox;	/* number of clipping boxes */
117 } drm_savage_cmdbuf_t;
118 
119 #define SAVAGE_WAIT_2D  0x1 /* wait for 2D idle before updating event tag */
120 #define SAVAGE_WAIT_3D  0x2 /* wait for 3D idle before updating event tag */
121 #define SAVAGE_WAIT_IRQ 0x4 /* emit or wait for IRQ, not implemented yet */
122 typedef struct drm_savage_event {
123 	unsigned int count;
124 	unsigned int flags;
125 } drm_savage_event_emit_t, drm_savage_event_wait_t;
126 
127 /* Commands for the cmdbuf ioctl
128  */
129 #define SAVAGE_CMD_STATE	0  /* a range of state registers */
130 #define SAVAGE_CMD_DMA_PRIM	1  /* vertices from DMA buffer */
131 #define SAVAGE_CMD_VB_PRIM	2  /* vertices from client vertex buffer */
132 #define SAVAGE_CMD_DMA_IDX	3  /* indexed vertices from DMA buffer */
133 #define SAVAGE_CMD_VB_IDX	4  /* indexed vertices client vertex buffer */
134 #define SAVAGE_CMD_CLEAR	5  /* clear buffers */
135 #define SAVAGE_CMD_SWAP		6  /* swap buffers */
136 
137 /* Primitive types
138 */
139 #define SAVAGE_PRIM_TRILIST	0  /* triangle list */
140 #define SAVAGE_PRIM_TRISTRIP	1  /* triangle strip */
141 #define SAVAGE_PRIM_TRIFAN	2  /* triangle fan */
142 #define SAVAGE_PRIM_TRILIST_201	3  /* reorder verts for correct flat
143 				    * shading on s3d */
144 
145 /* Skip flags (vertex format)
146  */
147 #define SAVAGE_SKIP_Z		0x01
148 #define SAVAGE_SKIP_W		0x02
149 #define SAVAGE_SKIP_C0		0x04
150 #define SAVAGE_SKIP_C1		0x08
151 #define SAVAGE_SKIP_S0		0x10
152 #define SAVAGE_SKIP_T0		0x20
153 #define SAVAGE_SKIP_ST0		0x30
154 #define SAVAGE_SKIP_S1		0x40
155 #define SAVAGE_SKIP_T1		0x80
156 #define SAVAGE_SKIP_ST1		0xc0
157 #define SAVAGE_SKIP_ALL_S3D	0x3f
158 #define SAVAGE_SKIP_ALL_S4	0xff
159 
160 /* Buffer names for clear command
161  */
162 #define SAVAGE_FRONT		0x1
163 #define SAVAGE_BACK		0x2
164 #define SAVAGE_DEPTH		0x4
165 
166 /* 64-bit command header
167  */
168 union drm_savage_cmd_header {
169 	struct {
170 		unsigned char cmd;	/* command */
171 		unsigned char pad0;
172 		unsigned short pad1;
173 		unsigned short pad2;
174 		unsigned short pad3;
175 	} cmd; /* generic */
176 	struct {
177 		unsigned char cmd;
178 		unsigned char global;	/* need idle engine? */
179 		unsigned short count;	/* number of consecutive registers */
180 		unsigned short start;	/* first register */
181 		unsigned short pad3;
182 	} state; /* SAVAGE_CMD_STATE */
183 	struct {
184 		unsigned char cmd;
185 		unsigned char prim;	/* primitive type */
186 		unsigned short skip;	/* vertex format (skip flags) */
187 		unsigned short count;	/* number of vertices */
188 		unsigned short start;	/* first vertex in DMA/vertex buffer */
189 	} prim; /* SAVAGE_CMD_DMA_PRIM, SAVAGE_CMD_VB_PRIM */
190 	struct {
191 		unsigned char cmd;
192 		unsigned char prim;
193 		unsigned short skip;
194 		unsigned short count;	/* number of indices that follow */
195 		unsigned short pad3;
196 	} idx; /* SAVAGE_CMD_DMA_IDX, SAVAGE_CMD_VB_IDX */
197 	struct {
198 		unsigned char cmd;
199 		unsigned char pad0;
200 		unsigned short pad1;
201 		unsigned int flags;
202 	} clear0; /* SAVAGE_CMD_CLEAR */
203 	struct {
204 		unsigned int mask;
205 		unsigned int value;
206 	} clear1; /* SAVAGE_CMD_CLEAR data */
207 };
208 
209 #endif
210