1 /* $NetBSD: nouveau_subdev_bar_nvc0.c,v 1.2 2015/10/18 15:42:00 jmcneill Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_bar_nvc0.c,v 1.2 2015/10/18 15:42:00 jmcneill Exp $");
29
30 #include <core/gpuobj.h>
31
32 #include <subdev/timer.h>
33 #include <subdev/fb.h>
34 #include <subdev/vm.h>
35
36 #include "priv.h"
37
38 struct nvc0_bar_priv_vm {
39 struct nouveau_gpuobj *mem;
40 struct nouveau_gpuobj *pgd;
41 struct nouveau_vm *vm;
42 };
43
44 struct nvc0_bar_priv {
45 struct nouveau_bar base;
46 spinlock_t lock;
47 struct nvc0_bar_priv_vm bar[2];
48 };
49
50 static int
nvc0_bar_kmap(struct nouveau_bar * bar,struct nouveau_mem * mem,u32 flags,struct nouveau_vma * vma)51 nvc0_bar_kmap(struct nouveau_bar *bar, struct nouveau_mem *mem,
52 u32 flags, struct nouveau_vma *vma)
53 {
54 struct nvc0_bar_priv *priv = (void *)bar;
55 int ret;
56
57 ret = nouveau_vm_get(priv->bar[0].vm, mem->size << 12, 12, flags, vma);
58 if (ret)
59 return ret;
60
61 nouveau_vm_map(vma, mem);
62 return 0;
63 }
64
65 static int
nvc0_bar_umap(struct nouveau_bar * bar,struct nouveau_mem * mem,u32 flags,struct nouveau_vma * vma)66 nvc0_bar_umap(struct nouveau_bar *bar, struct nouveau_mem *mem,
67 u32 flags, struct nouveau_vma *vma)
68 {
69 struct nvc0_bar_priv *priv = (void *)bar;
70 int ret;
71
72 ret = nouveau_vm_get(priv->bar[1].vm, mem->size << 12,
73 mem->page_shift, flags, vma);
74 if (ret)
75 return ret;
76
77 nouveau_vm_map(vma, mem);
78 return 0;
79 }
80
81 static void
nvc0_bar_unmap(struct nouveau_bar * bar,struct nouveau_vma * vma)82 nvc0_bar_unmap(struct nouveau_bar *bar, struct nouveau_vma *vma)
83 {
84 nouveau_vm_unmap(vma);
85 nouveau_vm_put(vma);
86 }
87
88 static int
nvc0_bar_init_vm(struct nvc0_bar_priv * priv,struct nvc0_bar_priv_vm * bar_vm,int bar_nr)89 nvc0_bar_init_vm(struct nvc0_bar_priv *priv, struct nvc0_bar_priv_vm *bar_vm,
90 int bar_nr)
91 {
92 struct nouveau_device *device = nv_device(&priv->base);
93 struct nouveau_vm *vm;
94 resource_size_t bar_len;
95 int ret;
96
97 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x1000, 0, 0,
98 &bar_vm->mem);
99 if (ret)
100 return ret;
101
102 ret = nouveau_gpuobj_new(nv_object(priv), NULL, 0x8000, 0, 0,
103 &bar_vm->pgd);
104 if (ret)
105 return ret;
106
107 bar_len = nv_device_resource_len(device, bar_nr);
108
109 ret = nouveau_vm_new(device, 0, bar_len, 0, &vm);
110 if (ret)
111 return ret;
112
113 atomic_inc(&vm->engref[NVDEV_SUBDEV_BAR]);
114
115 /*
116 * Bootstrap page table lookup.
117 */
118 if (bar_nr == 3) {
119 ret = nouveau_gpuobj_new(nv_object(priv), NULL,
120 (bar_len >> 12) * 8, 0x1000,
121 NVOBJ_FLAG_ZERO_ALLOC,
122 &vm->pgt[0].obj[0]);
123 vm->pgt[0].refcount[0] = 1;
124 if (ret)
125 return ret;
126 }
127
128 ret = nouveau_vm_ref(vm, &bar_vm->vm, bar_vm->pgd);
129 nouveau_vm_ref(NULL, &vm, NULL);
130 if (ret)
131 return ret;
132
133 nv_wo32(bar_vm->mem, 0x0200, lower_32_bits(bar_vm->pgd->addr));
134 nv_wo32(bar_vm->mem, 0x0204, upper_32_bits(bar_vm->pgd->addr));
135 nv_wo32(bar_vm->mem, 0x0208, lower_32_bits(bar_len - 1));
136 nv_wo32(bar_vm->mem, 0x020c, upper_32_bits(bar_len - 1));
137
138 return 0;
139 }
140
141 static int
nvc0_bar_ctor(struct nouveau_object * parent,struct nouveau_object * engine,struct nouveau_oclass * oclass,void * data,u32 size,struct nouveau_object ** pobject)142 nvc0_bar_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
143 struct nouveau_oclass *oclass, void *data, u32 size,
144 struct nouveau_object **pobject)
145 {
146 struct nouveau_device *device = nv_device(parent);
147 struct nvc0_bar_priv *priv;
148 bool has_bar3 = nv_device_resource_len(device, 3) != 0;
149 int ret;
150
151 ret = nouveau_bar_create(parent, engine, oclass, &priv);
152 *pobject = nv_object(priv);
153 if (ret)
154 return ret;
155
156 /* BAR3 */
157 if (has_bar3) {
158 ret = nvc0_bar_init_vm(priv, &priv->bar[0], 3);
159 if (ret)
160 return ret;
161 priv->base.alloc = nouveau_bar_alloc;
162 priv->base.kmap = nvc0_bar_kmap;
163 }
164
165 /* BAR1 */
166 ret = nvc0_bar_init_vm(priv, &priv->bar[1], 1);
167 if (ret)
168 return ret;
169
170 priv->base.umap = nvc0_bar_umap;
171 priv->base.unmap = nvc0_bar_unmap;
172 priv->base.flush = nv84_bar_flush;
173 spin_lock_init(&priv->lock);
174 return 0;
175 }
176
177 static void
nvc0_bar_dtor(struct nouveau_object * object)178 nvc0_bar_dtor(struct nouveau_object *object)
179 {
180 struct nvc0_bar_priv *priv = (void *)object;
181
182 nouveau_vm_ref(NULL, &priv->bar[1].vm, priv->bar[1].pgd);
183 nouveau_gpuobj_ref(NULL, &priv->bar[1].pgd);
184 nouveau_gpuobj_ref(NULL, &priv->bar[1].mem);
185
186 if (priv->bar[0].vm) {
187 nouveau_gpuobj_ref(NULL, &priv->bar[0].vm->pgt[0].obj[0]);
188 nouveau_vm_ref(NULL, &priv->bar[0].vm, priv->bar[0].pgd);
189 }
190 nouveau_gpuobj_ref(NULL, &priv->bar[0].pgd);
191 nouveau_gpuobj_ref(NULL, &priv->bar[0].mem);
192
193 nouveau_bar_destroy(&priv->base);
194 }
195
196 static int
nvc0_bar_init(struct nouveau_object * object)197 nvc0_bar_init(struct nouveau_object *object)
198 {
199 struct nvc0_bar_priv *priv = (void *)object;
200 int ret;
201
202 ret = nouveau_bar_init(&priv->base);
203 if (ret)
204 return ret;
205
206 nv_mask(priv, 0x000200, 0x00000100, 0x00000000);
207 nv_mask(priv, 0x000200, 0x00000100, 0x00000100);
208 nv_mask(priv, 0x100c80, 0x00000001, 0x00000000);
209
210 nv_wr32(priv, 0x001704, 0x80000000 | priv->bar[1].mem->addr >> 12);
211 if (priv->bar[0].mem)
212 nv_wr32(priv, 0x001714,
213 0xc0000000 | priv->bar[0].mem->addr >> 12);
214 return 0;
215 }
216
217 struct nouveau_oclass
218 nvc0_bar_oclass = {
219 .handle = NV_SUBDEV(BAR, 0xc0),
220 .ofuncs = &(struct nouveau_ofuncs) {
221 .ctor = nvc0_bar_ctor,
222 .dtor = nvc0_bar_dtor,
223 .init = nvc0_bar_init,
224 .fini = _nouveau_bar_fini,
225 },
226 };
227