1 /* $NetBSD: nouveau_subdev_mc_nvc0.c,v 1.1.1.1 2014/08/06 12:36:31 riastradh Exp $ */
2
3 /*
4 * Copyright 2012 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Ben Skeggs
25 */
26
27 #include <sys/cdefs.h>
28 __KERNEL_RCSID(0, "$NetBSD: nouveau_subdev_mc_nvc0.c,v 1.1.1.1 2014/08/06 12:36:31 riastradh Exp $");
29
30 #include "nv04.h"
31
32 const struct nouveau_mc_intr
33 nvc0_mc_intr[] = {
34 { 0x00000001, NVDEV_ENGINE_PPP },
35 { 0x00000020, NVDEV_ENGINE_COPY0 },
36 { 0x00000040, NVDEV_ENGINE_COPY1 },
37 { 0x00000080, NVDEV_ENGINE_COPY2 },
38 { 0x00000100, NVDEV_ENGINE_FIFO },
39 { 0x00001000, NVDEV_ENGINE_GR },
40 { 0x00002000, NVDEV_SUBDEV_FB },
41 { 0x00008000, NVDEV_ENGINE_BSP },
42 { 0x00040000, NVDEV_SUBDEV_THERM },
43 { 0x00020000, NVDEV_ENGINE_VP },
44 { 0x00100000, NVDEV_SUBDEV_TIMER },
45 { 0x00200000, NVDEV_SUBDEV_GPIO },
46 { 0x01000000, NVDEV_SUBDEV_PWR },
47 { 0x02000000, NVDEV_SUBDEV_LTCG },
48 { 0x04000000, NVDEV_ENGINE_DISP },
49 { 0x08000000, NVDEV_SUBDEV_FB },
50 { 0x10000000, NVDEV_SUBDEV_BUS },
51 { 0x40000000, NVDEV_SUBDEV_IBUS },
52 { 0x80000000, NVDEV_ENGINE_SW },
53 {},
54 };
55
56 static void
nvc0_mc_msi_rearm(struct nouveau_mc * pmc)57 nvc0_mc_msi_rearm(struct nouveau_mc *pmc)
58 {
59 struct nv04_mc_priv *priv = (void *)pmc;
60 nv_wr32(priv, 0x088704, 0x00000000);
61 }
62
63 struct nouveau_oclass *
64 nvc0_mc_oclass = &(struct nouveau_mc_oclass) {
65 .base.handle = NV_SUBDEV(MC, 0xc0),
66 .base.ofuncs = &(struct nouveau_ofuncs) {
67 .ctor = nv04_mc_ctor,
68 .dtor = _nouveau_mc_dtor,
69 .init = nv50_mc_init,
70 .fini = _nouveau_mc_fini,
71 },
72 .intr = nvc0_mc_intr,
73 .msi_rearm = nvc0_mc_msi_rearm,
74 }.base;
75