1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file cm_common.h 24 //! \brief Contains CM definitions 25 //! 26 27 #ifndef MEDIADRIVER_AGNOSTIC_COMMON_CM_CMCOMMON_H_ 28 #define MEDIADRIVER_AGNOSTIC_COMMON_CM_CMCOMMON_H_ 29 30 #include "mhw_mi.h" 31 #include "cm_innerdef_os.h" 32 #include <list> 33 34 // this marco is used to remove warning from clang to unused parameters 35 // which is harmless and useless but to make clang happy 36 #ifndef UNUSED 37 #define UNUSED(x) (void)(x) 38 #endif // UNUSED 39 40 //======<Feature List>====================================================================== 41 42 #define MDF_HW_KERNEL_DEBUG_SUPPORT 1 //avaliable by default, will be excluded in Open source media. 43 44 #if (_DEBUG || _RELEASE_INTERNAL) 45 #define MDF_COMMAND_BUFFER_DUMP 1 //avaliable in Debug/Release-internal 46 #define MDF_CURBE_DATA_DUMP 1 47 #define MDF_SURFACE_CONTENT_DUMP 1 48 #define MDF_SURFACE_STATE_DUMP 1 49 #define MDF_INTERFACE_DESCRIPTOR_DATA_DUMP 1 50 #endif 51 52 //===============<Definitions>================================================== 53 54 // Definition for return code 55 typedef enum _CM_RETURN_CODE 56 { 57 CM_SUCCESS = 0, 58 /* 59 * RANGE -1 ~ -9999 FOR EXTERNAL ERROR CODE 60 */ 61 CM_FAILURE = -1, 62 CM_NOT_IMPLEMENTED = -2, 63 CM_SURFACE_ALLOCATION_FAILURE = -3, 64 CM_OUT_OF_HOST_MEMORY = -4, 65 CM_SURFACE_FORMAT_NOT_SUPPORTED = -5, 66 CM_EXCEED_SURFACE_AMOUNT = -6, 67 CM_EXCEED_KERNEL_ARG_AMOUNT = -7, 68 CM_EXCEED_KERNEL_ARG_SIZE_IN_BYTE = -8, 69 CM_INVALID_ARG_INDEX = -9, 70 CM_INVALID_ARG_VALUE = -10, 71 CM_INVALID_ARG_SIZE = -11, 72 CM_INVALID_THREAD_INDEX = -12, 73 CM_INVALID_WIDTH = -13, 74 CM_INVALID_HEIGHT = -14, 75 CM_INVALID_DEPTH = -15, 76 CM_INVALID_COMMON_ISA = -16, 77 CM_OPEN_VIDEO_DEVICE_HANDLE_FAILURE = -17, 78 CM_VIDEO_DEVICE_LOCKED = -18, // Video device is already locked. 79 CM_LOCK_VIDEO_DEVICE_FAILURE = -19, // Video device is not locked but can't be locked. 80 CM_EXCEED_SAMPLER_AMOUNT = -20, 81 CM_EXCEED_MAX_KERNEL_PER_ENQUEUE = -21, 82 CM_EXCEED_MAX_KERNEL_SIZE_IN_BYTE = -22, 83 CM_EXCEED_MAX_THREAD_AMOUNT_PER_ENQUEUE = -23, 84 CM_EXCEED_VME_STATE_G6_AMOUNT = -24, 85 CM_INVALID_THREAD_SPACE = -25, 86 CM_EXCEED_MAX_TIMEOUT = -26, 87 CM_JITDLL_LOAD_FAILURE = -27, 88 CM_JIT_COMPILE_FAILURE = -28, 89 CM_JIT_COMPILESIM_FAILURE = -29, 90 CM_INVALID_THREAD_GROUP_SPACE = -30, 91 CM_THREAD_ARG_NOT_ALLOWED = -31, 92 CM_INVALID_GLOBAL_BUFFER_INDEX = -32, 93 CM_INVALID_BUFFER_HANDLER = -33, 94 CM_EXCEED_MAX_SLM_SIZE = -34, 95 CM_JITDLL_OLDER_THAN_ISA = -35, 96 CM_INVALID_HARDWARE_THREAD_NUMBER = -36, 97 CM_GTPIN_INVOKE_FAILURE = -37, 98 CM_INVALIDE_L3_CONFIGURATION = -38, 99 CM_INVALID_TEXTURE2D_USAGE = -39, 100 CM_INTEL_GFX_NOTFOUND = -40, 101 CM_GPUCOPY_INVALID_SYSMEM = -41, 102 CM_GPUCOPY_INVALID_WIDTH = -42, 103 CM_GPUCOPY_INVALID_STRIDE = -43, 104 CM_EVENT_DRIVEN_FAILURE = -44, 105 CM_LOCK_SURFACE_FAIL = -45, // Lock surface failed 106 CM_INVALID_GENX_BINARY = -46, 107 CM_FEATURE_NOT_SUPPORTED_IN_DRIVER = -47, // driver out-of-sync 108 CM_QUERY_DLL_VERSION_FAILURE = -48, //Fail in getting DLL file version 109 CM_KERNELPAYLOAD_PERTHREADARG_MUTEX_FAIL = -49, 110 CM_KERNELPAYLOAD_PERKERNELARG_MUTEX_FAIL = -50, 111 CM_KERNELPAYLOAD_SETTING_FAILURE = -51, 112 CM_KERNELPAYLOAD_SURFACE_INVALID_BTINDEX = -52, 113 CM_NOT_SET_KERNEL_ARGUMENT = -53, 114 CM_GPUCOPY_INVALID_SURFACES = -54, 115 CM_GPUCOPY_INVALID_SIZE = -55, 116 CM_GPUCOPY_OUT_OF_RESOURCE = -56, 117 CM_INVALID_VIDEO_DEVICE = -57, 118 CM_SURFACE_DELAY_DESTROY = -58, 119 CM_INVALID_VEBOX_STATE = -59, 120 CM_INVALID_VEBOX_SURFACE = -60, 121 CM_FEATURE_NOT_SUPPORTED_BY_HARDWARE = -61, 122 CM_RESOURCE_USAGE_NOT_SUPPORT_READWRITE = -62, 123 CM_MULTIPLE_MIPLEVELS_NOT_SUPPORTED = -63, 124 CM_INVALID_UMD_CONTEXT = -64, 125 CM_INVALID_LIBVA_SURFACE = -65, 126 CM_INVALID_LIBVA_INITIALIZE = -66, 127 CM_KERNEL_THREADSPACE_NOT_SET = -67, 128 CM_INVALID_KERNEL_THREADSPACE = -68, 129 CM_KERNEL_THREADSPACE_THREADS_NOT_ASSOCIATED= -69, 130 CM_KERNEL_THREADSPACE_INTEGRITY_FAILED = -70, 131 CM_INVALID_USERPROVIDED_GENBINARY = -71, 132 CM_INVALID_PRIVATE_DATA = -72, 133 CM_INVALID_MOS_RESOURCE_HANDLE = -73, 134 CM_SURFACE_CACHED = -74, 135 CM_SURFACE_IN_USE = -75, 136 CM_INVALID_GPUCOPY_KERNEL = -76, 137 CM_INVALID_DEPENDENCY_WITH_WALKING_PATTERN = -77, 138 CM_INVALID_MEDIA_WALKING_PATTERN = -78, 139 CM_FAILED_TO_ALLOCATE_SVM_BUFFER = -79, 140 CM_EXCEED_MAX_POWER_OPTION_FOR_PLATFORM = -80, 141 CM_INVALID_KERNEL_THREADGROUPSPACE = -81, 142 CM_INVALID_KERNEL_SPILL_CODE = -82, 143 CM_UMD_DRIVER_NOT_SUPPORTED = -83, 144 CM_INVALID_GPU_FREQUENCY_VALUE = -84, 145 CM_SYSTEM_MEMORY_NOT_4KPAGE_ALIGNED = -85, 146 CM_KERNEL_ARG_SETTING_FAILED = -86, 147 CM_NO_AVAILABLE_SURFACE = -87, 148 CM_VA_SURFACE_NOT_SUPPORTED = -88, 149 CM_TOO_MUCH_THREADS = -89, 150 CM_NULL_POINTER = -90, 151 CM_EXCEED_MAX_NUM_2D_ALIASES = -91, 152 CM_INVALID_PARAM_SIZE = -92, 153 CM_GT_UNSUPPORTED = -93, 154 CM_GTPIN_FLAG_NO_LONGER_SUPPORTED = -94, 155 CM_PLATFORM_UNSUPPORTED_FOR_API = -95, 156 CM_TASK_MEDIA_RESET = -96, 157 CM_KERNELPAYLOAD_SAMPLER_INVALID_BTINDEX = -97, 158 CM_EXCEED_MAX_NUM_BUFFER_ALIASES = -98, 159 CM_SYSTEM_MEMORY_NOT_4PIXELS_ALIGNED = -99, 160 CM_FAILED_TO_CREATE_CURBE_SURFACE = -100, 161 CM_INVALID_CAP_NAME = -101, 162 CM_INVALID_USER_GPU_CONTEXT_FOR_QUEUE_EX = -102, 163 CM_INVALID_CREATE_OPTION_FOR_BUFFER_STATELESS = -103, 164 CM_INVALID_KERNEL_ARG_POINTER = -104, 165 CM_SYSTEM_MEMORY_NOT_2PIXELS_ALIGNED = -105, 166 CM_NO_SUPPORTED_ADAPTER = -106, 167 /* 168 * RANGE -10000 ~ -19999 FOR INTERNAL ERROR CODE 169 */ 170 CM_INTERNAL_ERROR_CODE_OFFSET = -10000, 171 172 /* 173 * RANGE <=-20000 AREAD FOR MOST STATUS CONVERSION 174 */ 175 CM_MOS_STATUS_CONVERTED_CODE_OFFSET = -20000 176 } CM_RETURN_CODE; 177 178 //------------------------------------------------------------------------------ 179 //| Lock flags 180 //------------------------------------------------------------------------------ 181 #define CM_HAL_LOCKFLAG_READONLY 0x00000001 182 #define CM_HAL_LOCKFLAG_WRITEONLY 0x00000002 183 184 #define CM_BATCH_BUFFER_REUSE_ENABLE 1 185 #define CM_MAX_TASKS_DEFAULT 4 186 #define CM_MAXIMUM_TASKS 64 // used for VTune time collection static arrays 187 #define CM_MAX_TASKS_EU_SATURATION 4 188 189 #define CM_KERNEL_BINARY_BLOCK_SIZE 65536 // 64 KB 190 #define CM_KERNEL_BINARY_PADDING_SIZE 128 // Padding after kernel binary to WA page fault issue. 191 #define CM_MAX_KERNELS_PER_TASK 16 192 #define CM_MAX_SPILL_SIZE_PER_THREAD_IVB 11264 // 11 KB 193 #define CM_MAX_SPILL_SIZE_PER_THREAD_HSW_BDW 131072 // 128 KB 194 #define CM_MAX_SPILL_SIZE_PER_THREAD_HEVC 16384 // 16 KB 195 #define CM_MAX_SPILL_SIZE_PER_THREAD_DEFAULT CM_MAX_SPILL_SIZE_PER_THREAD // 196 #define CM_MAX_SAMPLER_TABLE_SIZE 512 197 #define CM_MAX_SAMPLER_8X8_TABLE_SIZE 2 198 #define CM_MAX_AVS_SAMPLER_SIZE 16 199 #define CM_MAX_3D_SAMPLER_SIZE 16 200 #define CM_MAX_VME_BINDING_INDEX 3 // base + forward + backward 201 #define CM_MAX_VME_BINDING_INDEX_1 33 // base + forward + backward when >= HSW 202 #define CM_MAX_BUFFER_SURFACE_TABLE_SIZE 256 203 #define CM_MAX_2D_SURFACE_UP_TABLE_SIZE 512 204 #define CM_MAX_2D_SURFACE_TABLE_SIZE 256 205 #define CM_MAX_3D_SURFACE_TABLE_SIZE 64 206 #define CM_MAX_USER_THREADS 262144 // 512x512 (max TS size) * 64 bytes (sizeof(MO cmd) + 10DW) = 16 MB (max allocated for BB) 207 #define CM_MAX_USER_THREADS_NO_THREADARG 262144 // 512x512 (max TS size) * 64 bytes (sizeof(MO cmd) + 10DW) = 16 MB (max allocated for BB) 208 #define MAX_THREAD_SPACE_WIDTH_PERGROUP 64 209 #define MAX_THREAD_SPACE_HEIGHT_PERGROUP 64 210 #define MAX_THREAD_SPACE_DEPTH_PERGROUP 64 211 #define CM_MAX_BB_SIZE 16777216 // 16 MB - Maximum Space allocated for Batch Buffer 212 #define CM_MAX_ARGS_PER_KERNEL 255 // compiler only supports up to 255 arguments 213 #define CM_MAX_THREAD_PAYLOAD_SIZE 2016 // 63 GRF 214 #define CM_MAX_ARG_BYTE_PER_KERNEL CM_MAX_THREAD_PAYLOAD_SIZE 215 #define CM_EXTRA_BB_SPACE (256 + 8*64) // Additional Space in BB for commands other than MEDIA_OBJECT, 8 addtional cachelines to avoid page fault 216 #define CM_MAX_STATIC_SURFACE_STATES_PER_BT 256 // Max possible surface state per binding table 217 #define CM_MAX_SURFACE_STATES_PER_BT 64 // Pre-set Max Surface state per binding table 218 #define CM_MAX_SURFACE_STATES 256 // Max Surface states 219 #define CM_PAYLOAD_OFFSET 32 // CM Compiler generates offset by 32 bytes. This need to be subtracted from kernel data offset. 220 #define CM_PER_KERNEL_ARG_VAL 1 // Per Kernel Indication 221 #define CM_MAX_CURBE_SIZE_PER_TASK 8192 // 256 GRF 222 #define CM_MAX_CURBE_SIZE_PER_KERNEL CM_MAX_THREAD_PAYLOAD_SIZE // 63 GRF 223 #define CM_MAX_THREAD_WIDTH_FOR_MW 511 224 #define CM_MAX_INDIRECT_DATA_SIZE_PER_KERNEL 1984 // 496 x 4 225 #define CM_HAL_MAX_DEPENDENCY_COUNT 8 226 #define CM_HAL_MAX_NUM_2D_ALIASES 10 // maximum number of aliases for one 2D surface. Arbitrary - can be increased 227 #define CM_HAL_MAX_NUM_BUFFER_ALIASES 10 // maximum number of aliases for one Buffer. Arbitrary - can be increased 228 229 #define CM_MAX_SIP_SIZE 0x4000 // 16k system routine size 230 #define CM_DEBUG_SURFACE_INDEX 252 // reserved for tools 231 #define CM_DEBUG_SURFACE_SIZE 0x10000 // 64k for all threads 232 #define CM_CSR_SURFACE_SIZE 0x800000 // 8 M Bytes for CSR surface 233 #define CM_SYNC_QWORD_PER_TASK 2 // 2 time stamps are record for a task. 1 for GPU start time stamp, 1 for GPU end time stamp. 234 235 #define CM_NULL_SURFACE 0xFFFF 236 #define CM_SURFACE_MASK 0xFFFF 237 #define CM_DEFAULT_CACHE_TYPE 0xFF00 238 239 #define CM_NULL_SURFACE_BINDING_INDEX 0 // Reserve 0 for NULL surface 240 #define CM_MAX_GLOBAL_SURFACE_NUMBER 7 241 242 #define CM_RESERVED_SURFACE_NUMBER_FOR_KERNEL_DEBUG 1 //debug surface 243 #define CM_GPUWALKER_IMPLICIT_ARG_NUM 6 //thread and group spaces plus thread id in two dimentions. 244 #define CM_HAL_MAX_VEBOX_SURF_NUM 16 245 246 #define __CM_SIP_FILE_PATH_GT1 "c:\\sip\\SIP_BTI_252_GT1.dat" 247 #define __CM_SIP_FILE_PATH_GT2 "c:\\sip\\SIP_BTI_252_GT2.dat" 248 #define __CM_SIP_FILE_PATH_GT3 "c:\\sip\\SIP_BTI_252_GT3.dat" 249 #define __CM_SIP_FILE_PATH_GT4 "c:\\sip\\SIP_BTI_252_GT4.dat" 250 251 #define CM_HAL_GPU_CONTEXT_COUNT 2 // MOS_GPU_CONTEXT_RENDER4 and MOS_GPU_CONTEXT_RENDER3 252 253 #define CM_INVALID_INDEX -1 254 255 #define CM_KERNEL_FLAGS_CURBE 0x00000001 256 #define CM_KERNEL_FLAGS_NONSTALLING_SCOREBOARD 0x00000002 //bit 1 257 258 #define ADDRESS_PAGE_ALIGNMENT_MASK_X64 0xFFFFFFFFFFFFF000ULL 259 #define ADDRESS_PAGE_ALIGNMENT_MASK_X86 0xFFFFF000 260 261 //CM MemObjCtl associated 262 #define CM_INVALID_MEMOBJCTL 0xFF 263 #define CM_MEMOBJCTL_CACHE_MASK 0xFF00 264 265 //Enqueue with Sync 266 #define CM_NO_KERNEL_SYNC 0 267 268 //Conditional batch buffer end 269 #define CM_NO_CONDITIONAL_END 0 270 #define CM_DEFAULT_COMPARISON_VALUE 0 271 #define CM_MAX_CONDITIONAL_END_CMDS 64 272 273 // CM masks used to decode hints for EnqueueWithHints 274 #define CM_HINTS_MASK_MEDIAOBJECT 0x1 275 #define CM_HINTS_MASK_KERNEL_GROUPS 0xE 276 #define CM_HINTS_NUM_BITS_WALK_OBJ 0x1 277 #define CM_HINTS_LEASTBIT_MASK 1 278 #define CM_HINTS_DEFAULT_NUM_KERNEL_GRP 1 279 #define CM_DEFAULT_THREAD_DEPENDENCY_MASK 0xFF 280 #define CM_REUSE_DEPENDENCY_MASK 0x1 281 #define CM_RESET_DEPENDENCY_MASK 0x2 282 #define CM_NO_BATCH_BUFFER_REUSE 0x4 283 #define CM_NO_BATCH_BUFFER_REUSE_BIT_POS 0x2 284 #define CM_SCOREBOARD_MASK_POS_IN_MEDIA_OBJECT_CMD 0x5 285 #define CM_HINTS_MASK_NUM_TASKS 0x70 286 #define CM_HINTS_NUM_BITS_TASK_POS 0x4 287 288 // CM device creation with different options 289 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_ENABLE 0 290 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_DISABLE 1 291 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_MASK 1 292 293 #define CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_ENABLE_HEVC 2 294 #define CM_DEVICE_CREATE_OPTION_MAX_TASKS_HEVC_MASK 4 295 296 #define CM_DEVICE_CREATE_OPTION_TDR_DISABLE 64 //Reserved, used only in CMRT Thin 297 298 #define CM_DEVICE_CREATE_OPTION_DEFAULT CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_ENABLE 299 300 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_OFFSET 1 301 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_MASK (7 << CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_OFFSET) 302 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_16K_STEP 16384 //16K 303 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_16K 1 304 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_32K 2 305 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_48K 3 306 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_64K 4 307 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_80K 5 308 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_96K 6 309 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_112K 7 310 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_128K 0 // 128K By default 311 #define CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_DEFAULT CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_128K 312 313 #define CM_DEVICE_CONFIG_TASK_NUM_OFFSET 4 314 #define CM_DEVICE_CONFIG_TASK_NUM_MASK (3 << CM_DEVICE_CONFIG_TASK_NUM_OFFSET) 315 #define CM_DEVICE_CONFIG_TASK_NUM_DEFAULT 0 316 #define CM_DEVICE_CONFIG_TASK_NUM_8 1 317 #define CM_DEVICE_CONFIG_TASK_NUM_12 2 318 #define CM_DEVICE_CONFIG_TASK_NUM_16 3 319 #define CM_DEVICE_CONFIG_TASK_NUM_STEP 4 320 321 #define CM_DEVICE_CONFIG_MEDIA_RESET_OFFSET 7 322 #define CM_DEVICE_CONFIG_MEDIA_RESET_ENABLE (1 << CM_DEVICE_CONFIG_MEDIA_RESET_OFFSET) 323 324 #define CM_DEVICE_CONFIG_EXTRA_TASK_NUM_OFFSET 8 325 #define CM_DEVICE_CONFIG_EXTRA_TASK_NUM_MASK (3 << CM_DEVICE_CONFIG_EXTRA_TASK_NUM_OFFSET) 326 #define CM_DEVICE_CONFIG_EXTRA_TASK_NUM_4 3 327 328 #define CM_DEVICE_CONFIG_SLICESHUTDOWN_OFFSET 10 329 #define CM_DEVICE_CONFIG_SLICESHUTDOWN_ENABLE (1 << CM_DEVICE_CONFIG_SLICESHUTDOWN_OFFSET) 330 331 #define CM_DEVICE_CONFIG_GPUCONTEXT_OFFSET 12 332 #define CM_DEVICE_CONFIG_GPUCONTEXT_ENABLE (1 << CM_DEVICE_CONFIG_GPUCONTEXT_OFFSET) 333 334 #define CM_DEVICE_CONFIG_KERNELBINARYGSH_OFFSET 13 335 #define CM_DEVICE_CONFIG_KERNELBINARYGSH_MASK (255 << CM_DEVICE_CONFIG_KERNELBINARYGSH_OFFSET ) 336 337 #define CM_DEVICE_CONFIG_DSH_DISABLE_OFFSET 21 338 #define CM_DEVICE_CONFIG_DSH_DISABLE_MASK (1 << CM_DEVICE_CONFIG_DSH_DISABLE_OFFSET) 339 340 #define CM_DEVICE_CONFIG_MIDTHREADPREEMPTION_OFFSET 22 341 #define CM_DEVICE_CONFIG_MIDTHREADPREEMPTION_DISENABLE (1 << CM_DEVICE_CONFIG_MIDTHREADPREEMPTION_OFFSET) 342 343 #define CM_DEVICE_CONFIG_KERNEL_DEBUG_OFFSET 23 344 #define CM_DEVICE_CONFIG_KERNEL_DEBUG_ENABLE (1 << CM_DEVICE_CONFIG_KERNEL_DEBUG_OFFSET) 345 346 #define CM_DEVICE_CONFIG_VEBOX_OFFSET 28 347 #define CM_DEVICE_CONFIG_VEBOX_DISABLE (1 << CM_DEVICE_CONFIG_VEBOX_OFFSET) 348 349 #define CM_DEVICE_CONFIG_GPUCOPY_OFFSET 29 350 #define CM_DEVICE_CONFIG_GPUCOPY_DISABLE (1 << CM_DEVICE_CONFIG_GPUCOPY_OFFSET) 351 352 #define CM_DEVICE_CONFIG_FAST_PATH_OFFSET 30 353 #define CM_DEVICE_CONFIG_FAST_PATH_ENABLE (1 << CM_DEVICE_CONFIG_FAST_PATH_OFFSET) 354 355 #define CM_DEVICE_CONFIG_MOCK_RUNTIME_OFFSET 31 356 #define CM_DEVICE_CONFIG_MOCK_RUNTIME_ENABLE (1 << CM_DEVICE_CONFIG_MOCK_RUNTIME_OFFSET) 357 358 // HEVC config : 359 // Scratch space size :16k 360 // Number of task: 16 361 // Media Reset Option : true 362 // Extra task num: 4 363 #define CM_DEVICE_CREATE_OPTION_FOR_HEVC ((CM_DEVICE_CREATE_OPTION_SCRATCH_SPACE_ENABLE) \ 364 | (CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_16K << CM_DEVICE_CONFIG_SCRATCH_SPACE_SIZE_OFFSET) \ 365 | (CM_DEVICE_CONFIG_TASK_NUM_16 << CM_DEVICE_CONFIG_TASK_NUM_OFFSET) \ 366 | (CM_DEVICE_CONFIG_MEDIA_RESET_ENABLE) \ 367 | (CM_DEVICE_CONFIG_EXTRA_TASK_NUM_4 << CM_DEVICE_CONFIG_EXTRA_TASK_NUM_OFFSET)\ 368 | (CM_DEVICE_CONFIG_GPUCONTEXT_ENABLE)) 369 370 // HEVC config with slice shutdown enabled 371 #define CM_DEVICE_CREATE_OPTION_FOR_HEVC_SSD ((CM_DEVICE_CREATE_OPTION_FOR_HEVC) | (CM_DEVICE_CONFIG_SLICESHUTDOWN_ENABLE)) 372 373 #define CM_ARGUMENT_SURFACE_SIZE 4 374 375 #define MAX_STEPPING_NUM 10 376 377 #define CM_26ZI_BLOCK_WIDTH 16 378 #define CM_26ZI_BLOCK_HEIGHT 8 379 380 #define CM_NUM_DWORD_FOR_MW_PARAM 16 381 382 #define CM_MAX_KERNEL_NAME_SIZE_IN_BYTE 256 383 #define CM_EXTRA_STRING_LENGTH_FOR_MWMO_DUMP 50 384 385 #define CM_KERNELBINARY_BLOCKSIZE_2MB (1024 * 1024 * 2) 386 #define CM_64BYTE (64) 387 388 #define CM_DDI_1_0 100 389 #define CM_DDI_1_1 101 390 #define CM_DDI_1_2 102 391 #define CM_DDI_1_3 103 392 #define CM_DDI_1_4 104 393 #define CM_DDI_2_0 200 394 #define CM_DDI_2_1 201 395 #define CM_DDI_2_2 202 396 #define CM_DDI_2_3 203 397 #define CM_DDI_2_4 204 398 #define CM_DDI_3_0 300 399 #define CM_DDI_4_0 400 400 #define CM_DDI_5_0 500 401 #define CM_DDI_6_0 600 402 #define CM_DDI_7_0 700 403 #define CM_DDI_7_2 702 //for MDFRT API refreshment. 404 405 #define CM_VERSION (CM_DDI_7_2) 406 407 #define CM_BUFFER_STATELESS_CREATE_OPTION_GFX_MEM 0 408 #define CM_BUFFER_STATELESS_CREATE_OPTION_SYS_MEM 1 409 #define CM_BUFFER_STATELESS_CREATE_OPTION_DEFAULT CM_BUFFER_STATELESS_CREATE_OPTION_GFX_MEM 410 411 //------------------------------------------------------------------------------ 412 //| Forward declarations 413 //------------------------------------------------------------------------------ 414 typedef struct _CM_HAL_STATE *PCM_HAL_STATE; 415 416 struct CM_HAL_KERNEL_PARAM; 417 typedef CM_HAL_KERNEL_PARAM *PCM_HAL_KERNEL_PARAM; 418 419 // Queue option used by multiple context queues 420 enum CM_QUEUE_TYPE 421 { 422 CM_QUEUE_TYPE_NONE = 0, 423 CM_QUEUE_TYPE_RENDER = 1, 424 CM_QUEUE_TYPE_COMPUTE = 2 425 }; 426 427 enum CM_QUEUE_SSEU_USAGE_HINT_TYPE 428 { 429 CM_QUEUE_SSEU_USAGE_HINT_DEFAULT = 0, 430 CM_QUEUE_SSEU_USAGE_HINT_VME = 1 431 }; 432 433 struct _CM_QUEUE_CREATE_OPTION 434 { 435 CM_QUEUE_TYPE QueueType : 3; 436 bool RAMode : 1; 437 unsigned int Reserved0 : 3; 438 bool UserGPUContext : 1; // Is the user-provided GPU Context already created externally 439 unsigned int GPUContext : 8; // user-provided GPU Context ordinal 440 CM_QUEUE_SSEU_USAGE_HINT_TYPE SseuUsageHint : 3; 441 unsigned int Reserved1 : 1; 442 unsigned int Reserved2 : 12; 443 }; 444 #define CM_QUEUE_CREATE_OPTION _CM_QUEUE_CREATE_OPTION 445 446 const CM_QUEUE_CREATE_OPTION CM_DEFAULT_QUEUE_CREATE_OPTION = { CM_QUEUE_TYPE_RENDER, false, 0, false, 0, CM_QUEUE_SSEU_USAGE_HINT_DEFAULT, 0, 0 }; 447 448 //------------------------------------------------------------------------------ 449 //|GT-PIN 450 typedef struct _CM_SURFACE_DETAILS 451 { 452 uint32_t width; //width of surface 453 uint32_t height; //height of surface, 0 if surface is CmBuffer 454 uint32_t depth; //depth of surface, 0 if surface is CmBuffer or CmSurface2D 455 456 DdiSurfaceFormat format; //format of surface, UNKNOWN if surface is CmBuffer 457 uint32_t planeIndex; //plane Index for this BTI, 0 if surface is not planar surface 458 459 uint32_t pitch; //pitch of suface, 0 if surface is CmBuffer 460 uint32_t slicePitch; //pitch of a slice in CmSurface3D, 0 if surface is CmBuffer or CmSurface2D 461 uint32_t surfaceBaseAddress; 462 uint8_t tiledSurface; //bool 463 uint8_t tileWalk; //bool 464 uint32_t xOffset; 465 uint32_t yOffset; 466 }CM_SURFACE_DETAILS,*PCM_SURFACE_DETAILS; 467 468 //------------------------------------------------------------------------------ 469 //| CM dependency pattern 470 //------------------------------------------------------------------------------ 471 typedef enum _CM_DEPENDENCY_PATTERN 472 { 473 CM_NONE_DEPENDENCY = 0, //All threads run parallel, scanline dispatch 474 CM_WAVEFRONT = 1, 475 CM_WAVEFRONT26 = 2, 476 CM_VERTICAL_WAVE = 3, 477 CM_HORIZONTAL_WAVE = 4, 478 CM_WAVEFRONT26Z = 5, 479 CM_WAVEFRONT26X = 6, 480 CM_WAVEFRONT26ZIG = 7, 481 CM_WAVEFRONT26ZI = 8 482 } CM_DEPENDENCY_PATTERN; 483 484 //------------------------------------------------------------------------------ 485 //| CM media walking pattern (used with no dependency) 486 //------------------------------------------------------------------------------ 487 typedef enum _CM_WALKING_PATTERN 488 { 489 CM_WALK_DEFAULT = 0, 490 CM_WALK_WAVEFRONT = 1, 491 CM_WALK_WAVEFRONT26 = 2, 492 CM_WALK_VERTICAL = 3, 493 CM_WALK_HORIZONTAL = 4, 494 CM_WALK_WAVEFRONT26X = 5, 495 CM_WALK_WAVEFRONT26ZIG = 6, 496 CM_WALK_WAVEFRONT45D = 7, 497 CM_WALK_WAVEFRONT45XD_2 = 8, 498 CM_WALK_WAVEFRONT26XALT = 9, 499 CM_WALK_WAVEFRONT26D = 10, 500 CM_WALK_WAVEFRONT26XD = 11 501 } CM_WALKING_PATTERN; 502 503 //------------------------------------------------------------------------------ 504 //| CM MEDIA_OBJECT_WALKER GroupID Select 505 //------------------------------------------------------------------------------ 506 typedef enum _CM_MW_GROUP_SELECT 507 { 508 CM_MW_GROUP_NONE = 0, 509 CM_MW_GROUP_COLORLOOP = 1, 510 CM_MW_GROUP_INNERLOCAL = 2, 511 CM_MW_GROUP_MIDLOCAL = 3, 512 CM_MW_GROUP_OUTERLOCAL = 4, 513 CM_MW_GROUP_INNERGLOBAL = 5, 514 } CM_MW_GROUP_SELECT; 515 516 //------------------------------------------------------------------------------ 517 //| CM media walking parameters (used for engineering build) 518 //------------------------------------------------------------------------------ 519 typedef struct _CM_WALKING_PARAMETERS 520 { 521 uint32_t Value[CM_NUM_DWORD_FOR_MW_PARAM]; 522 } CM_WALKING_PARAMETERS, *PCM_WALKING_PARAMETERS; 523 524 #define CM_FUSED_EU_DISABLE 0 525 #define CM_FUSED_EU_ENABLE 1 526 #define CM_FUSED_EU_DEFAULT CM_FUSED_EU_DISABLE 527 528 #define CM_TURBO_BOOST_DISABLE 0 529 #define CM_TURBO_BOOST_ENABLE 1 530 #define CM_TURBO_BOOST_DEFAULT CM_TURBO_BOOST_ENABLE 531 532 typedef struct _CM_TASK_CONFIG 533 { 534 bool turboBoostFlag : 1; 535 bool fusedEuDispatchFlag : 1; 536 uint32_t reserved_bits :30; 537 uint32_t reserved0; 538 uint32_t reserved1; 539 uint32_t reserved2; 540 }CM_TASK_CONFIG, *PCM_TASK_CONFIG; 541 542 typedef enum _CM_KERNEL_EXEC_MODE 543 { 544 CM_KERNEL_EXECUTION_MODE_MONOPOLIZED = 0, // Kernel need occupy all DSS for execution. 545 CM_KERNEL_EXECUTION_MODE_CONCURRENT, // Kernel can occupy part of DSS and concurrently execute together with other workloads. 546 } CM_KERNEL_EXEC_MODE; 547 548 struct CM_EXECUTION_CONFIG 549 { 550 CM_KERNEL_EXEC_MODE kernelExecutionMode = CM_KERNEL_EXECUTION_MODE_MONOPOLIZED; 551 int concurrentPolicy = 0; //Reserve for future extension. 552 }; 553 554 struct CM_KERNEL_SYNC_CONFIG { 555 bool dataCacheFlush : 1; // true: cache will be flushed; 556 uint32_t reserved : 31; 557 }; 558 559 struct L3ConfigRegisterValues 560 { 561 unsigned int config_register0; 562 unsigned int config_register1; 563 unsigned int config_register2; 564 unsigned int config_register3; 565 }; 566 567 //*----------------------------------------------------------------------------- 568 //| Execute Vebox data params 569 //*----------------------------------------------------------------------------- 570 typedef struct _CM_VEBOX_STATE 571 { 572 573 uint32_t ColorGamutExpansionEnable : 1; 574 uint32_t ColorGamutCompressionEnable : 1; 575 uint32_t GlobalIECPEnable : 1; 576 uint32_t DNEnable : 1; 577 uint32_t DIEnable : 1; 578 uint32_t DNDIFirstFrame : 1; 579 uint32_t DownsampleMethod422to420 : 1; 580 uint32_t DownsampleMethod444to422 : 1; 581 uint32_t DIOutputFrames : 2; 582 uint32_t DemosaicEnable : 1; 583 uint32_t VignetteEnable : 1; 584 uint32_t AlphaPlaneEnable : 1; 585 uint32_t HotPixelFilteringEnable : 1; 586 uint32_t SingleSliceVeboxEnable : 1; 587 uint32_t LaceCorrectionEnable : BITFIELD_BIT(16); 588 uint32_t DisableEncoderStatistics : BITFIELD_BIT(17); 589 uint32_t DisableTemporalDenoiseFilter : BITFIELD_BIT(18); 590 uint32_t SinglePipeEnable : BITFIELD_BIT(19); 591 uint32_t __CODEGEN_UNIQUE(Reserved) : BITFIELD_BIT(20); 592 uint32_t ForwardGammaCorrectionEnable : BITFIELD_BIT(21); 593 uint32_t __CODEGEN_UNIQUE(Reserved) : BITFIELD_RANGE(22, 24); 594 uint32_t StateSurfaceControlBits : BITFIELD_RANGE(25, 31); 595 596 } CM_VEBOX_STATE, *PCM_VEBOX_STATE; 597 598 //------------------------------------------------------------------------------ 599 //| HAL Sampler 8x8 State Param for Sampler 8x8 Entry in the array 600 //------------------------------------------------------------------------------ 601 typedef enum _CM_HAL_SAMPLER_8X8_TYPE 602 { 603 CM_SAMPLER8X8_AVS = 0, // AVS sampler8x8 type 604 CM_SAMPLER8X8_CONV = 1, // CONV sampler8x type 605 CM_SAMPLER8X8_MISC = 3, // MISC sampler8x8 type 606 CM_SAMPLER8X8_NONE 607 }CM_HAL_SAMPLER_8X8_TYPE; 608 609 typedef struct _CM_AVS_COEFF_TABLE{ 610 float FilterCoeff_0_0; 611 float FilterCoeff_0_1; 612 float FilterCoeff_0_2; 613 float FilterCoeff_0_3; 614 float FilterCoeff_0_4; 615 float FilterCoeff_0_5; 616 float FilterCoeff_0_6; 617 float FilterCoeff_0_7; 618 }CM_AVS_COEFF_TABLE; 619 620 typedef enum _CM_GPUCOPY_KERNEL_ID 621 { 622 GPU_COPY_KERNEL_UNKNOWN = 0x0, 623 624 //cpu -> gpu 625 GPU_COPY_KERNEL_GPU2CPU_UNALIGNED_NV12_ID = 0x1, 626 GPU_COPY_KERNEL_GPU2CPU_ALIGNED_NV12_ID = 0x2, 627 GPU_COPY_KERNEL_GPU2CPU_UNALIGNED_ID = 0x3, 628 GPU_COPY_KERNEL_GPU2CPU_ALIGNED_ID = 0x4, 629 630 //gpu -> cpu 631 GPU_COPY_KERNEL_CPU2GPU_NV12_ID = 0x5, 632 GPU_COPY_KERNEL_CPU2GPU_ID = 0x6, 633 634 //gpu -> gpu 635 GPU_COPY_KERNEL_GPU2GPU_NV12_ID = 0x7, 636 GPU_COPY_KERNEL_GPU2GPU_ID = 0x8, 637 638 //cpu -> cpu 639 GPU_COPY_KERNEL_CPU2CPU_ID = 0x9 640 } CM_GPUCOPY_KERNEL_ID; 641 642 // referenced in both g9 and g10. 643 typedef enum _CM_HAL_MEMORY_OBJECT_CONTROL_G9 644 { 645 CM_MEMORY_OBJECT_CONTROL_SKL_DEFAULT = 0x0, 646 CM_MEMORY_OBJECT_CONTROL_SKL_NO_L3 = 0x1, 647 CM_MEMORY_OBJECT_CONTROL_SKL_NO_LLC_ELLC = 0x2, 648 CM_MEMORY_OBJECT_CONTROL_SKL_NO_LLC = 0x3, 649 CM_MEMORY_OBJECT_CONTROL_SKL_NO_ELLC = 0x4, 650 CM_MEMORY_OBJECT_CONTROL_SKL_NO_LLC_L3 = 0x5, 651 CM_MEMORY_OBJECT_CONTROL_SKL_NO_ELLC_L3 = 0x6, 652 CM_MEMORY_OBJECT_CONTROL_SKL_NO_CACHE = 0x7 653 }CM_HAL_MEMORY_OBJECT_CONTROL_G9; 654 655 // Unified CM_MEMORY_OBJECT_CONTROL enumeration 656 typedef enum _CM_HAL_MEMORY_OBJECT_CONTROL 657 { 658 CM_MEMORY_OBJECT_CONTROL_DEFAULT = 0x0, 659 CM_MEMORY_OBJECT_CONTROL_NO_L3 = 0x1, 660 CM_MEMORY_OBJECT_CONTROL_NO_LLC_ELLC = 0x2, 661 CM_MEMORY_OBJECT_CONTROL_NO_LLC = 0x3, 662 CM_MEMORY_OBJECT_CONTROL_NO_ELLC = 0x4, 663 CM_MEMORY_OBJECT_CONTROL_NO_LLC_L3 = 0x5, 664 CM_MEMORY_OBJECT_CONTROL_NO_ELLC_L3 = 0x6, 665 CM_MEMORY_OBJECT_CONTROL_NO_CACHE = 0x7, 666 CM_MEMORY_OBJECT_CONTROL_L1_ENABLED = 0x8 667 }CM_HAL_MEMORY_OBJECT_CONTROL; 668 669 670 typedef struct _CM_POWER_OPTION 671 { 672 uint16_t nSlice; // set number of slice to use: 0(default number), 1, 2... 673 uint16_t nSubSlice; // set number of subslice to use: 0(default number), 1, 2... 674 uint16_t nEU; // set number of EU to use: 0(default number), 1, 2... 675 } CM_POWER_OPTION, *PCM_POWER_OPTION; 676 677 //*----------------------------------------------------------------------------- 678 //| CM Convolve type for SKL+ 679 //*----------------------------------------------------------------------------- 680 typedef enum _CM_CONVOLVE_SKL_TYPE 681 { 682 CM_CONVOLVE_SKL_TYPE_2D = 0, 683 CM_CONVOLVE_SKL_TYPE_1D = 1, 684 CM_CONVOLVE_SKL_TYPE_1P = 2 685 } CM_CONVOLVE_SKL_TYPE; 686 687 // to define frame type for interlace frame support 688 typedef enum _CM_FRAME_TYPE 689 { 690 CM_FRAME, // singe frame, not interlaced 691 CM_TOP_FIELD, 692 CM_BOTTOM_FIELD, 693 MAX_FRAME_TYPE 694 } CM_FRAME_TYPE; 695 696 //L3 Configurations 697 typedef struct _L3_CONFIG { 698 uint32_t slm; //sharedlocalmemory 699 uint32_t urb; //unified return buffer 700 uint32_t rest; //rest 701 uint32_t datacluster; //data cluster 702 uint32_t readonly; //read only 703 uint32_t instruction; //instruction/state cache 704 uint32_t constant; //constant cache 705 uint32_t texture; //texture cache 706 uint32_t sum; //sum 707 } L3_CONFIG; 708 709 typedef enum _L3_SUGGEST_CONFIG 710 { 711 CM_L3_PLANE_DEFAULT = 0, 712 CM_L3_PLANE_1, 713 CM_L3_PLANE_2, 714 CM_L3_PLANE_3, 715 CM_L3_PLANE_4, 716 CM_L3_PLANE_5, 717 CM_L3_PLANE_6, 718 CM_L3_PLANE_7, 719 CM_L3_PLANE_8, 720 } L3_SUGGEST_CONFIG; 721 722 enum SURFACE_DESTROY_KIND{ 723 APP_DESTROY = 0, 724 DELAYED_DESTROY = 1, 725 FORCE_DESTROY = 2 726 }; 727 728 // Need to consistant with compiler 729 enum CM_ARG_KIND 730 { 731 // compiler-defined kind 732 ARG_KIND_GENERAL = 0x0, 733 ARG_KIND_SAMPLER = 0x1, 734 //ARG_KIND_SURFACE = 0x2, compiler value for surface 735 // runtime classify further surface to 1D/2D/3D 736 ARG_KIND_SURFACE_2D = 0x2, 737 ARG_KIND_SURFACE_1D = 0x3, 738 ARG_KIND_SURFACE_3D = 0x4, 739 ARG_KIND_SURFACE_VME = 0x5, 740 ARG_KIND_VME_INDEX = 0x6, 741 ARG_KIND_SURFACE_2D_UP = 0x7, 742 ARG_KIND_SURFACE_SAMPLER8X8_AVS = 0x8, 743 ARG_KIND_SURFACE_SAMPLER8X8_VA = 0x9, //get compiler update before checking this in 744 ARG_KIND_SURFACE_SAMPLER = 0xb, 745 ARG_KIND_SURFACE = 0xc, 746 ARG_KIND_SURFACE2DUP_SAMPLER = 0xd, 747 ARG_KIND_IMPLICT_LOCALSIZE = 0xe, 748 ARG_KIND_IMPLICT_GROUPSIZE = 0xf, 749 ARG_KIND_IMPLICIT_LOCALID = 0x10, 750 ARG_KIND_STATE_BUFFER = 0x11, 751 ARG_KIND_GENERAL_DEPVEC = 0x20, 752 ARG_KIND_SURFACE_2D_SCOREBOARD = 0x2A, //used for SW scoreboarding 753 ARG_KIND_GENERAL_DEPCNT = 0x30 //dependency count, used for SW scoreboarding 754 }; 755 756 //non-depend on rtti::dynamic_cast 757 enum CM_ENUM_CLASS_TYPE 758 { 759 CM_ENUM_CLASS_TYPE_CMBUFFER_RT = 0, 760 CM_ENUM_CLASS_TYPE_CMSURFACE2D = 1, 761 CM_ENUM_CLASS_TYPE_CMSURFACE2DUP = 2, 762 CM_ENUM_CLASS_TYPE_CMSURFACE3D = 3, 763 CM_ENUM_CLASS_TYPE_CMSURFACESAMPLER = 4, 764 CM_ENUM_CLASS_TYPE_CMSURFACESAMPLER8X8 = 5, 765 CM_ENUM_CLASS_TYPE_CMSURFACEVME = 6, 766 CM_ENUM_CLASS_TYPE_CMSAMPLER_RT = 7, 767 CM_ENUM_CLASS_TYPE_CMSAMPLER8X8STATE_RT = 8, 768 CM_ENUM_CLASS_TYPE_CM_STATE_BUFFER = 9 769 }; 770 771 #endif // #ifndef MEDIADRIVER_AGNOSTIC_COMMON_CM_CMCOMMON_H_ 772