1 /* 2 * Copyright (c) 2017-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file codec_def_common_encode.h 24 //! \brief Defines common types and macros shared by CodecHal, MHW, and DDI layer for encode. 25 //! \details All codec_def_encode may include this file which should not contain any DDI specific code. 26 //! 27 #ifndef __CODEC_DEF_COMMON_ENCODE_H__ 28 #define __CODEC_DEF_COMMON_ENCODE_H__ 29 30 #include "mos_defs.h" 31 32 #define CODEC_NUM_REF_BUFFERS (CODEC_MAX_NUM_REF_FRAME + 1) // Max 16 references (for AVC) + 1 for the current frame 33 #define CODEC_NUM_NON_REF_BUFFERS 3 34 #define CODEC_NUM_TRACKED_BUFFERS (CODEC_NUM_REF_BUFFERS + CODEC_NUM_NON_REF_BUFFERS) 35 #define CODEC_CURR_TRACKED_BUFFER CODEC_NUM_TRACKED_BUFFERS 36 37 //BRC 38 #define BRC_IMG_STATE_SIZE_PER_PASS 128 39 #define BRC_IMG_STATE_SIZE_PER_PASS_G10 144 40 #define BRC_IMG_STATE_SIZE_PER_PASS_G11 192 41 42 // Quality/Performance differentiators for HSW AVC Encode 43 #define NUM_TARGET_USAGE_MODES 8 44 #define NUM_VDENC_TARGET_USAGE_MODES 8 45 46 //weighted prediction 47 #define CODEC_NUM_WP_FRAME 8 48 #define CODEC_MAX_FORWARD_WP_FRAME 6 49 #define CODEC_MAX_BACKWARD_WP_FRAME 2 50 #define CODEC_WP_OUTPUT_L0_START 0 51 #define CODEC_WP_OUTPUT_L1_START 6 52 53 #define CODEC_720P_MAX_PIC_WIDTH 1280 54 #define CODEC_720P_MAX_PIC_HEIGHT 1280 55 56 #define CODEC_MAX_PIC_WIDTH 1920 57 #define CODEC_MAX_PIC_HEIGHT 1920 // Tablet usage in portrait mode, image resolution = 1200x1920, so change MAX_HEIGHT to 1920 58 59 #define CODEC_2K_MAX_PIC_WIDTH 2048 60 #define CODEC_2K_MAX_PIC_HEIGHT 2048 61 62 #define CODEC_4K_MAX_PIC_WIDTH 4096 63 #define CODEC_4K_MAX_PIC_HEIGHT 4096 64 65 #define CODEC_8K_MAX_PIC_WIDTH 8192 66 #define CODEC_8K_MAX_PIC_HEIGHT 8192 67 68 #define CODEC_16K_MAX_PIC_WIDTH 16384 69 #define CODEC_12K_MAX_PIC_HEIGHT 12288 70 #define CODEC_16K_MAX_PIC_HEIGHT 16384 71 72 #define CODECHAL_MAD_BUFFER_SIZE 4 // buffer size is 4 bytes 73 74 // HME 75 #define SCALE_FACTOR_2x 2 76 #define SCALE_FACTOR_4x 4 77 #define SCALE_FACTOR_16x 16 78 #define SCALE_FACTOR_32x 32 79 80 #define CODECHAL_VP9_MB_CODE_SIZE 204 81 82 typedef struct tagENCODE_RECT 83 { 84 uint16_t Top; // [0..(FrameHeight+ M-1)/M -1] 85 uint16_t Bottom; // [0..(FrameHeight+ M-1)/M -1] 86 uint16_t Left; // [0..(FrameWidth+15)/16-1] 87 uint16_t Right; // [0..(FrameWidth+15)/16-1] 88 } ENCODE_RECT; 89 90 typedef struct tagMOVE_RECT 91 { 92 uint32_t SourcePointX; 93 uint32_t SourcePointY; 94 uint32_t DestRectTop; 95 uint32_t DestRectBottom; 96 uint32_t DestRectLeft; 97 uint32_t DestRectRight; 98 } MOVE_RECT; 99 100 /*! \brief Defines ROI settings. 101 * 102 * {Top, Bottom, Left, Right} defines the ROI boundary. The values are in unit of blocks. The block size M should use LCU size (e.g. sif LCU size is 32x32, M is 32). And its range should be within the frame boundary, so that: 103 * 0 <= Top <= Bottom <= (FrameHeight+ M-1)/M -1 104 * 0 <= Left <= Right <= (FrameWidth+M-1)/M-1 105 * If input range is out of frame boundary, driver should trim it. 106 * ROI alignes with LCU based rectangular blocks and cannot have arbitrary pixel-based location. 107 * Region overlapping is allowed. For MBs reside within more than one ROIs, parameters from ROI with smaller index rules. For example, when ROI[0] and ROI[1] overlap on a certain area, the QP value for the overlapped area will be determined by value of ROI[0]. The order of ROI[] reflects objects’ relative relationship of depth. Foreground objects should have ROI index smaller than background objects. 108 */ 109 typedef struct _CODEC_ROI 110 { 111 uint16_t Top; //!< [0..(FrameHeight+15)/16-1] 112 uint16_t Bottom; //!< [0..(FrameHeight+15)/16-1] 113 uint16_t Left; //!< [0..(FrameWidth+15)/16-1] 114 uint16_t Right; //!< [0..(FrameWidth+15)/16-1] 115 /*! \brief For ROIValueInDeltaQP equals CQP case, this parameter gives explicit delta QP value of ROI regional QP vs. frame QP. 116 * 117 * Value range [-51..51]. If regional QP PriorityLevelOfDQp + QpY is out of range of [0..51], driver should crop it. It could be applied on both CQP and BRC cases. For ROIValueInDeltaQP equals 0BRC cases, this parameter describes the priority level of the ROI region. Value range [-3..3]. The higher the absolute value, the bigger range of delta QP is allowed. And it is usually applies on BRC case. BRC will decide the actual delta QP value. Positive priority level means negative delta QP should be applied. And negative priority level means positive delta QP which implies the region should be intentionally blurred. In either case, value Priority level 0 means same as non-ROI region. It is suggested that application does not set value 0. But if it happens, driver will treat that ROI as part of non-ROI background. 118 */ 119 char PriorityLevelOrDQp; 120 } CODEC_ROI, *PCODEC_ROI; 121 122 /*! \brief Indicates the uncompressed input color space 123 * 124 * Valid only when input is ARGB format. 125 */ 126 typedef enum _CODEC_INPUT_COLORSPACE 127 { 128 ECOLORSPACE_P709 = 0, 129 ECOLORSPACE_P601 = 1, 130 ECOLORSPACE_P2020 = 2 131 } CODEC_INPUT_COLORSPACE, ENCODE_INPUT_COLORSPACE; 132 133 /*! \brief Indicates the tolerance the application has to variations in the frame size. 134 * 135 * For example, wireless display scenarios may require very steady bitrate to reduce buffering time. It affects the BRC algorithm used, but may or may not have an effect based on the combination of other BRC parameters. Only valid when the driver reports support for FrameSizeToleranceSupport. 136 */ 137 typedef enum _CODEC_FRAMESIZE_TOLERANCE 138 { 139 EFRAMESIZETOL_NORMAL = 0, 140 EFRAMESIZETOL_LOW = 1, //!< Maps to "sliding window" 141 EFRAMESIZETOL_EXTREMELY_LOW = 2 //!< Maps to "low delay" 142 } CODEC_FRAMESIZE_TOLERANCE, ENCODE_FRAMESIZE_TOLERANCE; 143 144 /*! \brief Provides a hint to encoder about the scenario for the encoding session. 145 * 146 * BRC algorithm may tune differently based on this info. 147 */ 148 typedef enum _CODEC_SCENARIO 149 { 150 ESCENARIO_UNKNOWN = 0, 151 ESCENARIO_DISPLAYREMOTING = 1, 152 ESCENARIO_VIDEOCONFERENCE = 2, 153 ESCENARIO_ARCHIVE = 3, 154 ESCENARIO_LIVESTREAMING = 4, 155 ESCENARIO_VIDEOCAPTURE = 5, 156 ESCENARIO_VIDEOSURVEILLANCE = 6, 157 ESCENARIO_GAMESTREAMING = 7, 158 ESCENARIO_REMOTEGAMING = 8 159 } CODEC_SCENARIO, ENCODE_SCENARIO; 160 161 /*! \brief Provides a hint to encoder about the content for the encoding session. 162 */ 163 typedef enum _CODEC_CONTENT 164 { 165 ECONTENT_UNKNOWN = 0, 166 ECONTENT_FULLSCREENVIDEO = 1, 167 ECONTENT_NONVIDEOSCREEN = 2 168 } CODEC_CONTENT, ENCODE_CONTENT; 169 170 typedef enum 171 { 172 RATECONTROL_CBR = 1, 173 RATECONTROL_VBR = 2, 174 RATECONTROL_CQP = 3, 175 RATECONTROL_AVBR = 4, 176 RATECONTROL_RESERVED0 = 8, // This is used by MSDK for Lookahead and hence not used here 177 RATECONTROL_ICQ = 9, 178 RATECONTROL_VCM = 10, 179 RATECONTROL_QVBR = 14, 180 RATECONTROL_CQL = 15, 181 RATECONTROL_IWD_VBR = 100 182 } RATE_CONTROL_METHOD; 183 184 typedef enum 185 { 186 DEFAULT_WEIGHTED_INTER_PRED_MODE = 0, 187 EXPLICIT_WEIGHTED_INTER_PRED_MODE = 1, 188 IMPLICIT_WEIGHTED_INTER_PRED_MODE = 2, 189 INVALID_WEIGHTED_INTER_PRED_MODE = -1 190 } WEIGHTED_INTER_PRED_MODE; 191 192 // used from MHW & DDI 193 typedef enum 194 { 195 ROLLING_I_DISABLED = 0, 196 ROLLING_I_COLUMN = 1, 197 ROLLING_I_ROW = 2, 198 ROLLING_I_SQUARE = 3 199 } ROLLING_I_SETTING; 200 201 typedef enum 202 { 203 BRC_ROLLING_I_DISABLED = 0, 204 BRC_ROLLING_I_COLUMN = 4, 205 BRC_ROLLING_I_ROW = 8, 206 BRC_ROLLING_I_SQUARE = 12, 207 BRC_ROLLING_I_QP = 13 208 }BRC_ROLLING_I_SETTING; 209 210 typedef enum _CODECHAL_MFX_SURFACE_ID 211 { 212 CODECHAL_MFX_REF_SURFACE_ID = 0, 213 CODECHAL_MFX_SRC_SURFACE_ID = 4, 214 CODECHAL_MFX_DSRECON_SURFACE_ID = 5 215 } CODECHAL_MFX_SURFACE_ID; 216 217 typedef enum _CODECHAL_HCP_SURFACE_ID 218 { 219 CODECHAL_HCP_DECODED_SURFACE_ID = 0, 220 CODECHAL_HCP_SRC_SURFACE_ID = 1, // Encode 221 CODECHAL_HCP_LAST_SURFACE_ID = 2, // VP9 222 CODECHAL_HCP_GOLDEN_SURFACE_ID = 3, // VP9 223 CODECHAL_HCP_ALTREF_SURFACE_ID = 4, // VP9 224 CODECHAL_HCP_REF_SURFACE_ID = 5 225 } CODECHAL_HCP_SURFACE_ID; 226 227 // --------------------------- 228 // Structures 229 // --------------------------- 230 // used from MHW & DDI 231 typedef struct _BSBuffer 232 { 233 uint8_t *pBase; 234 uint8_t *pCurrent; 235 uint32_t SliceOffset; // Slice offset, always byte aligned 236 uint8_t BitOffset; // bit offset for pCurrent. 237 uint32_t BitSize; // bit size per slice, first slice may include SPS & PPS 238 uint32_t BufferSize; // buffer size 239 } BSBuffer, *PBSBuffer; 240 241 typedef struct _CODEC_ENCODER_SLCDATA 242 { 243 uint32_t SliceOffset; 244 uint32_t BitSize; 245 uint32_t CmdOffset; 246 uint32_t SkipEmulationByteCount; 247 248 // MPEG2 only 249 struct 250 { 251 uint8_t SliceGroup; 252 uint16_t NextSgMbXCnt; 253 uint16_t NextSgMbYCnt; 254 }; 255 } CODEC_ENCODER_SLCDATA, *PCODEC_ENCODER_SLCDATA; 256 257 typedef struct _CODECHAL_NAL_UNIT_PARAMS 258 { 259 uint32_t uiNalUnitType; 260 uint32_t uiOffset; 261 uint32_t uiSize; 262 bool bInsertEmulationBytes; 263 uint32_t uiSkipEmulationCheckCount; 264 } CODECHAL_NAL_UNIT_PARAMS, *PCODECHAL_NAL_UNIT_PARAMS; 265 266 typedef struct tagFRAMERATE 267 { 268 uint32_t Numerator; 269 uint32_t Denominator; 270 } FRAMERATE; 271 272 /*********************************************************************************\ 273 Constants for VDENC costing look-up-tables 274 \*********************************************************************************/ 275 typedef enum _CODEC_VDENC_LUTMODE 276 { 277 CODEC_VDENC_LUTMODE_INTRA_SADMPM = 0x00, 278 CODEC_VDENC_LUTMODE_INTRA_32x32 = 0x01, 279 CODEC_VDENC_LUTMODE_INTRA_16x16 = 0x02, 280 CODEC_VDENC_LUTMODE_INTRA_8x8 = 0x03, 281 CODEC_VDENC_LUTMODE_INTER_32x16 = 0x04, 282 CODEC_VDENC_LUTMODE_INTER_16x32 = 0x04, 283 CODEC_VDENC_LUTMODE_INTER_AMP = 0x04, //All asymmetrical shapes 284 CODEC_VDENC_LUTMODE_INTER_16x16 = 0x05, 285 CODEC_VDENC_LUTMODE_INTER_16x8 = 0x06, 286 CODEC_VDENC_LUTMODE_INTER_8x16 = 0x06, 287 CODEC_VDENC_LUTMODE_INTER_8x8 = 0x07, 288 CODEC_VDENC_LUTMODE_INTER_32x32 = 0x08, 289 CODEC_VDENC_LUTMODE_INTER_BIDIR = 0x09, 290 CODEC_VDENC_LUTMODE_REF_ID = 0x0A, 291 CODEC_VDENC_LUTMODE_INTRA_CHROMA = 0x0B, 292 CODEC_VDENC_LUTMODE_INTRA_NxN = 0x0C, 293 CODEC_VDENC_LUTMODE_INTRA_RDEMPM = 0x0D, 294 CODEC_VDENC_LUTMODE_MERGE_32X32 = 0x0E, 295 CODEC_VDENC_LUTMODE_MERGE_16x16 = 0x0F, 296 CODEC_VDENC_LUTMODE_MERGE_8x8 = 0x10, 297 CODEC_VDENC_LUTMODE_SKIP_32X32 = 0x11, 298 CODEC_VDENC_LUTMODE_SKIP_16x16 = 0x12, 299 CODEC_VDENC_LUTMODE_SKIP_8x8 = 0x13, 300 CODEC_VDENC_LUTMODE_INTRA_DC_32x32_SAD = 0x14, 301 CODEC_VDENC_LUTMODE_INTRA_DC_16x16_SAD = 0x15, 302 CODEC_VDENC_LUTMODE_INTRA_DC_8x8_SAD = 0x16, 303 CODEC_VDENC_LUTMODE_INTRA_DC_4x4_SAD = 0x17, 304 CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_SAD = 0x18, 305 CODEC_VDENC_LUTMODE_INTRA_NONDC_16x16_SAD = 0x19, 306 CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_SAD = 0x1A, 307 CODEC_VDENC_LUTMODE_INTRA_NONDC_4x4_SAD = 0x1B, 308 CODEC_VDENC_LUTMODE_INTRA_DC_32x32_RD = 0x1C, 309 CODEC_VDENC_LUTMODE_INTRA_DC_8x8_RD = 0x1D, 310 CODEC_VDENC_LUTMODE_INTRA_NONDC_32x32_RD = 0x1E, 311 CODEC_VDENC_LUTMODE_INTRA_NONDC_8x8_RD = 0x1F, 312 CODEC_VDENC_LUTMODE_INTRA_LEFT_BOUNDARY_SAD = 0x20, 313 CODEC_VDENC_LUTMODE_INTRA_TOP_BOUNDARY_SAD = 0x21, 314 CODEC_VDENC_LUTMODE_INTRA_TU_SPLIT = 0x22, 315 CODEC_VDENC_LUTMODE_INTER_TU_SPLIT = 0x23, 316 CODEC_VDENC_LUTMODE_TU_CBF_FLAG = 0x24, 317 CODEC_VDENC_LUTMODE_INTRA_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 0, 318 CODEC_VDENC_LUTMODE_INTRA_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 1, 319 CODEC_VDENC_LUTMODE_INTRA_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 2, 320 CODEC_VDENC_LUTMODE_INTRA_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 3, 321 CODEC_VDENC_LUTMODE_INTER_TU_32_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 4, 322 CODEC_VDENC_LUTMODE_INTER_TU_16_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 5, 323 CODEC_VDENC_LUTMODE_INTER_TU_8_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 6, 324 CODEC_VDENC_LUTMODE_INTER_TU_4_CBF_FLAG = CODEC_VDENC_LUTMODE_TU_CBF_FLAG + 7, 325 326 CODEC_VDENC_LUTMODE_TU_COEF_EST = 0x2C, 327 CODEC_VDENC_LUTMODE_INTRA_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 0, 328 CODEC_VDENC_LUTMODE_INTRA_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 1, 329 CODEC_VDENC_LUTMODE_INTRA_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 2, 330 CODEC_VDENC_LUTMODE_INTRA_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 3, 331 CODEC_VDENC_LUTMODE_INTER_TU_32_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 4, 332 CODEC_VDENC_LUTMODE_INTER_TU_16_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 5, 333 CODEC_VDENC_LUTMODE_INTER_TU_8_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 6, 334 CODEC_VDENC_LUTMODE_INTER_TU_4_NZC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 7, 335 336 CODEC_VDENC_LUTMODE_INTRA_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 8, 337 CODEC_VDENC_LUTMODE_INTRA_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 9, 338 CODEC_VDENC_LUTMODE_INTRA_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 10, 339 CODEC_VDENC_LUTMODE_INTRA_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 11, 340 CODEC_VDENC_LUTMODE_INTER_TU_32_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 12, 341 CODEC_VDENC_LUTMODE_INTER_TU_16_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 13, 342 CODEC_VDENC_LUTMODE_INTER_TU_8_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 14, 343 CODEC_VDENC_LUTMODE_INTER_TU_4_NSIGC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 15, 344 345 CODEC_VDENC_LUTMODE_INTRA_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 16, 346 CODEC_VDENC_LUTMODE_INTRA_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 17, 347 CODEC_VDENC_LUTMODE_INTRA_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 18, 348 CODEC_VDENC_LUTMODE_INTRA_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 19, 349 CODEC_VDENC_LUTMODE_INTER_TU_32_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 20, 350 CODEC_VDENC_LUTMODE_INTER_TU_16_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 21, 351 CODEC_VDENC_LUTMODE_INTER_TU_8_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 22, 352 CODEC_VDENC_LUTMODE_INTER_TU_4_NSUBSETC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 23, 353 354 CODEC_VDENC_LUTMODE_INTRA_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 24, 355 CODEC_VDENC_LUTMODE_INTRA_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 25, 356 CODEC_VDENC_LUTMODE_INTRA_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 26, 357 CODEC_VDENC_LUTMODE_INTRA_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 27, 358 CODEC_VDENC_LUTMODE_INTER_TU_32_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 28, 359 CODEC_VDENC_LUTMODE_INTER_TU_16_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 29, 360 CODEC_VDENC_LUTMODE_INTER_TU_8_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 30, 361 CODEC_VDENC_LUTMODE_INTER_TU_4_NLEVELC = CODEC_VDENC_LUTMODE_TU_COEF_EST + 31, 362 363 // VP9 specific cost 364 CODEC_VDENC_LUTMODE_INTRA_32x16 = 0x4C, 365 CODEC_VDENC_LUTMODE_INTRA_16x8 = 0x4D, 366 CODEC_VDENC_LUTMODE_INTER_NEARESTMV = 0x4E, 367 CODEC_VDENC_LUTMODE_INTER_NEARMV = 0x4F, 368 CODEC_VDENC_LUTMODE_INTER_ZEROMV = 0x50, 369 CODEC_VDENC_LUTMODE_TU_DEPTH0 = 0x51, 370 CODEC_VDENC_LUTMODE_TU_DEPTH1 = 0x52, 371 CODEC_VDENC_LUTMODE_TU_DEPTH2 = 0x53, 372 373 CODEC_VDENC_LUTMODE_INTRA_64X64DC = 0x54, 374 CODEC_VDENC_LUTMODE_MERGE_64X64 = 0x55, 375 CODEC_VDENC_LUTMODE_SKIP_64X64 = 0x56, 376 377 CODEC_VDENC_NUM_MODE_COST = 0x57 378 } CODEC_VDENC_LUTMODE; 379 380 // Batch buffer type 381 enum 382 { 383 MB_ENC_Frame_BB = 0, 384 MB_ENC_Field_BB, 385 //Add new buffer type here 386 NUM_ENCODE_BB_TYPE 387 }; 388 389 typedef enum 390 { 391 FRAME_NO_SKIP = 0, // encode as normal, no skip frames 392 FRAME_SKIP_NORMAL = 1 // one or more frames were skipped prior to curr frame. Encode curr frame as normal, update BRC 393 } FRAME_SKIP_FLAG; 394 395 typedef enum _CODEC_SLICE_STRUCTS 396 { 397 CODECHAL_SLICE_STRUCT_ONESLICE = 0, // Once slice for the whole frame 398 CODECHAL_SLICE_STRUCT_POW2ROWS = 1, // Slices are power of 2 number of rows, all slices the same 399 CODECHAL_SLICE_STRUCT_ROWSLICE = 2, // Slices are any number of rows, all slices the same 400 CODECHAL_SLICE_STRUCT_ARBITRARYROWSLICE = 3, // Slices are any number of rows, slices can be different 401 CODECHAL_SLICE_STRUCT_ARBITRARYMBSLICE = 4 // Slices are any number of MBs, slices can be different 402 // 5 - 7 are Reserved 403 } CODEC_SLICE_STRUCTS; 404 405 //FEI Encode Macros 406 #define CodecHalIsFeiEncode(codecFunction) \ 407 ( codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \ 408 codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ 409 codecFunction == CODECHAL_FUNCTION_FEI_PAK || \ 410 codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) 411 412 //Encode Macros 413 #define CodecHalIsEncode(codecFunction) \ 414 (codecFunction == CODECHAL_FUNCTION_ENC || \ 415 codecFunction == CODECHAL_FUNCTION_PAK || \ 416 codecFunction == CODECHAL_FUNCTION_ENC_PAK || \ 417 codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK ||\ 418 codecFunction == CODECHAL_FUNCTION_HYBRIDPAK) || \ 419 CodecHalIsFeiEncode(codecFunction) 420 421 #define CodecHalUsesVideoEngine(codecFunction) \ 422 (codecFunction == CODECHAL_FUNCTION_PAK || \ 423 codecFunction == CODECHAL_FUNCTION_ENC_PAK || \ 424 codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \ 425 codecFunction == CODECHAL_FUNCTION_FEI_PAK || \ 426 codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) 427 428 #define CodecHalUsesRenderEngine(codecFunction, standard) \ 429 (codecFunction == CODECHAL_FUNCTION_ENC || \ 430 (codecFunction == CODECHAL_FUNCTION_ENC_PAK) || \ 431 codecFunction == CODECHAL_FUNCTION_HYBRIDPAK || \ 432 ((codecFunction == CODECHAL_FUNCTION_DECODE) && (standard == CODECHAL_VC1)) || \ 433 codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK || \ 434 codecFunction == CODECHAL_FUNCTION_FEI_PRE_ENC || \ 435 codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ 436 codecFunction == CODECHAL_FUNCTION_FEI_ENC_PAK) 437 438 #define CodecHalUsesOnlyRenderEngine(codecFunction) \ 439 (codecFunction == CODECHAL_FUNCTION_ENC || \ 440 codecFunction == CODECHAL_FUNCTION_FEI_ENC || \ 441 codecFunction == CODECHAL_FUNCTION_HYBRIDPAK) 442 443 #define CodecHalUsesVdencEngine(codecFunction) \ 444 (codecFunction == CODECHAL_FUNCTION_ENC_VDENC_PAK) 445 446 #define CodecHalUsesPakEngine(codecFunction) \ 447 (codecFunction == CODECHAL_FUNCTION_PAK || \ 448 codecFunction == CODECHAL_FUNCTION_ENC_PAK) 449 450 #define CodecHalIsRateControlBrc(rateControl, standard) (\ 451 (rateControl == RATECONTROL_CBR) || \ 452 (rateControl == RATECONTROL_VBR) || \ 453 (rateControl == RATECONTROL_AVBR) || \ 454 (rateControl == RATECONTROL_CQL) || \ 455 ((( rateControl == RATECONTROL_VCM) || \ 456 ( rateControl == RATECONTROL_ICQ) || \ 457 ( rateControl == RATECONTROL_QVBR) || \ 458 ( rateControl == RATECONTROL_IWD_VBR)) && \ 459 ( standard == CODECHAL_AVC )) ) 460 461 // The current definition of the first encode mode CODECHAL_ENCODE_MODE_AVC should be used 462 // as a base for subsequent encode modes 463 #define CODECHAL_ENCODE_MODE_BIT_OFFSET ((uint32_t)(log((double)CODECHAL_ENCODE_MODE_AVC)/log(2.))) 464 #define CODECHAL_ENCODE_MODE_BIT_MASK (( 1L << CODECHAL_ENCODE_MODE_BIT_OFFSET) - 1 ) 465 466 #endif // __CODEC_DEF_COMMON_ENCODE_H__ 467