1 /* 2 * Copyright (c) 2017, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_mfx_hwcmd_g10_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g10_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_VDBOX_MFX_HWCMD_G10_X_H__ 29 #define __MHW_VDBOX_MFX_HWCMD_G10_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_vdbox_mfx_g10_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH( x ) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief MFX_QM_STATE 50 //! \details 51 //! This is a common state command for AVC encoder modes. For encoder, it 52 //! represents both the forward QM matrices as well as the decoding QM 53 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 54 //! application are being sent to the hardware. The driver is responsible 55 //! for determining the final set of scaling lists to be used for decoding 56 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 57 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 58 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 59 //! order. But the Forward Q scaling lists are sent in column-wise raster 60 //! order (column-by-column) to simplify the H/W. Driver will perform all 61 //! the scan order conversion for both ForwardQ and IQ. 62 //! 63 struct MFX_QM_STATE_CMD 64 { 65 union 66 { 67 //!< DWORD 0 68 struct 69 { 70 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 71 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 72 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 73 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 74 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 75 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 76 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 77 }; 78 uint32_t Value; 79 } DW0; 80 union 81 { 82 //!< DWORD 1 83 struct 84 { 85 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 86 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 87 } Obj0; 88 struct 89 { 90 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 91 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 92 } Obj1; 93 struct 94 { 95 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 96 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 97 }Obj2; 98 uint32_t Value; 99 } DW1; 100 101 uint32_t ForwardQuantizerMatrix[16]; //!< Forward Quantizer Matrix 102 103 //! \name Local enumerations 104 105 enum SUBOPCODE_B 106 { 107 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 108 }; 109 110 enum SUBOPCODE_A 111 { 112 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 113 }; 114 115 enum MEDIA_COMMAND_OPCODE 116 { 117 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 118 }; 119 120 enum PIPELINE 121 { 122 PIPELINE_MFXMULTIDW = 2, //!< No additional details 123 }; 124 125 enum COMMAND_TYPE 126 { 127 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 128 }; 129 130 //! \brief AVC 131 //! \details 132 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 133 //! loaded. 134 enum AVC 135 { 136 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 137 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 138 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 139 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 140 }; 141 142 //! \brief MPEG2 143 //! \details 144 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 145 //! loaded. 146 enum MPEG2 147 { 148 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 149 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 150 }; 151 152 //! \brief JPEG 153 //! \details 154 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 155 //! loaded. 156 enum JPEG 157 { 158 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 159 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 160 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 161 }; 162 163 //! \name Initializations 164 165 //! \brief Explicit member initialization function 166 MFX_QM_STATE_CMD(); 167 168 static const size_t dwSize = 18; 169 static const size_t byteSize = 72; 170 }; 171 172 //! 173 //! \brief MFX_FQM_STATE 174 //! \details 175 //! This is a common state command for AVC encoder modes. For encoder, it 176 //! represents both the forward QM matrices as well as the decoding QM 177 //! matrices.This is a Frame-level state. Only Scaling Lists specified by an 178 //! application are being sent to the hardware. The driver is responsible 179 //! for determining the final set of scaling lists to be used for decoding 180 //! the current slice, based on the AVC Spec Table 7-2 (Fall-Back Rules A 181 //! and B).In MFX AVC PAK mode, PAK needs both forward Q scaling lists and 182 //! IQ scaling lists. The IQ scaling lists are sent as in MFD in raster scan 183 //! order. But the Forward Q scaling lists are sent in column-wise raster 184 //! order (column-by-column) to simplify the H/W. Driver will perform all 185 //! the scan order conversion for both ForwardQ and IQ. 186 //! 187 struct MFX_FQM_STATE_CMD 188 { 189 union 190 { 191 //!< DWORD 0 192 struct 193 { 194 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 195 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 196 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 197 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 198 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 199 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 200 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 201 }; 202 uint32_t Value; 203 } DW0; 204 union 205 { 206 //!< DWORD 1 207 struct 208 { 209 uint32_t Avc : __CODEGEN_BITFIELD( 0, 1) ; //!< AVC, AVC- Decoder Only 210 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, AVC- Decoder Only 211 } Obj0; 212 struct 213 { 214 uint32_t Mpeg2 : __CODEGEN_BITFIELD( 0, 1) ; //!< MPEG2, MPEG2- Decoder Only 215 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved, MPEG2- Decoder Only 216 } Obj1; 217 struct 218 { 219 uint32_t Jpeg : __CODEGEN_BITFIELD( 0, 1) ; //!< JPEG, JPEG- Encoder Only 220 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 221 }Obj2; 222 uint32_t Value; 223 } DW1; 224 225 uint32_t ForwardQuantizerMatrix[32]; //!< Forward Quantizer Matrix 226 227 //! \name Local enumerations 228 229 enum SUBOPCODE_B 230 { 231 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 232 }; 233 234 enum SUBOPCODE_A 235 { 236 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 237 }; 238 239 enum MEDIA_COMMAND_OPCODE 240 { 241 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 242 }; 243 244 enum PIPELINE 245 { 246 PIPELINE_MFXMULTIDW = 2, //!< No additional details 247 }; 248 249 enum COMMAND_TYPE 250 { 251 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 252 }; 253 254 //! \brief AVC 255 //! \details 256 //! <b>For AVC QM Type</b>: This field specifies which Quantizer Matrix is 257 //! loaded. 258 enum AVC 259 { 260 AVC_AVC_4X_4INTRAMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 0, //!< No additional details 261 AVC_AVC_4X_4INTERMATRIX_Y_4DWS_CB_4DWS_CR_4DWS_RESERVED_4DWS = 1, //!< No additional details 262 AVC_AVC8X8INTRAMATRIX = 2, //!< No additional details 263 AVC_AVC8X8INTERMATRIX = 3, //!< No additional details 264 }; 265 266 //! \brief MPEG2 267 //! \details 268 //! <b>For MPEG2 QM Type</b>: This field specifies which Quantizer Matrix is 269 //! loaded. 270 enum MPEG2 271 { 272 MPEG2_MPEGINTRAQUANTIZERMATRIX = 0, //!< No additional details 273 MPEG2_MPEGNONINTRAQUANTIZERMATRIX = 1, //!< No additional details 274 }; 275 276 //! \brief JPEG 277 //! \details 278 //! <b> For JPEG QM Type</b>:This field specifies which Quantizer Matrix is 279 //! loaded. 280 enum JPEG 281 { 282 JPEG_JPEGLUMAYQUANTIZERMATRIXORR = 0, //!< No additional details 283 JPEG_JPEGCHROMACBQUANTIZERMATRIXORG = 1, //!< No additional details 284 JPEG_JPEGCHROMACRQUANTIZERMATRIXORB = 2, //!< No additional details 285 }; 286 287 //! \name Initializations 288 289 //! \brief Explicit member initialization function 290 MFX_FQM_STATE_CMD(); 291 292 static const size_t dwSize = 34; 293 static const size_t byteSize = 136; 294 }; 295 296 //! 297 //! \brief MFX_PIPE_MODE_SELECT 298 //! \details 299 //! Specifies which codec and hardware module is being used to encode/decode 300 //! the video data, on a per-frame basis. The MFX_PIPE_MODE_SELECT command 301 //! specifies which codec and hardware module is being used to encode/decode 302 //! the video data, on a per-frame basis. It also configures the hardware 303 //! pipeline according to the active encoder/decoder operating mode for 304 //! encoding/decoding the current picture. Commands issued specifically for 305 //! AVC and MPEG2 are ignored when VC1 is the active codec. 306 //! 307 struct MFX_PIPE_MODE_SELECT_CMD 308 { 309 union 310 { 311 //!< DWORD 0 312 struct 313 { 314 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 315 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 316 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 317 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 318 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 319 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 320 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 321 }; 322 uint32_t Value; 323 } DW0; 324 union 325 { 326 //!< DWORD 1 327 struct 328 { 329 uint32_t StandardSelect : __CODEGEN_BITFIELD( 0, 3) ; //!< STANDARD_SELECT 330 uint32_t CodecSelect : __CODEGEN_BITFIELD( 4, 4) ; //!< CODEC_SELECT 331 uint32_t StitchMode : __CODEGEN_BITFIELD( 5, 5) ; //!< STITCH_MODE 332 uint32_t FrameStatisticsStreamoutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< FRAME_STATISTICS_STREAMOUT_ENABLE 333 uint32_t ScaledSurfaceEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SCALED_SURFACE_ENABLE 334 uint32_t PreDeblockingOutputEnablePredeblockoutenable : __CODEGEN_BITFIELD( 8, 8) ; //!< PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 335 uint32_t PostDeblockingOutputEnablePostdeblockoutenable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 336 uint32_t StreamOutEnable : __CODEGEN_BITFIELD(10, 10) ; //!< STREAM_OUT_ENABLE 337 uint32_t PicErrorStatusReportEnable : __CODEGEN_BITFIELD(11, 11) ; //!< PIC_ERRORSTATUS_REPORT_ENABLE 338 uint32_t DeblockerStreamOutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKER_STREAM_OUT_ENABLE 339 uint32_t VdencMode : __CODEGEN_BITFIELD(13, 13) ; //!< VDENC_MODE 340 uint32_t StandaloneVdencModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< STANDALONE_VDENC_MODE_ENABLE 341 uint32_t DecoderModeSelect : __CODEGEN_BITFIELD(15, 16) ; //!< DECODER_MODE_SELECT 342 uint32_t DecoderShortFormatMode : __CODEGEN_BITFIELD(17, 17) ; //!< DECODER_SHORT_FORMAT_MODE 343 uint32_t ExtendedStreamOutEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Extended stream out enable 344 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 31) ; //!< Reserved 345 }; 346 uint32_t Value; 347 } DW1; 348 union 349 { 350 //!< DWORD 2 351 struct 352 { 353 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 354 uint32_t VdsIldbCalculation : __CODEGEN_BITFIELD( 3, 3) ; //!< VDS_ILDB_CALCULATION 355 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 356 uint32_t ClockGateEnableAtSliceLevel : __CODEGEN_BITFIELD( 6, 6) ; //!< CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 357 uint32_t Reserved71 : __CODEGEN_BITFIELD( 7, 9) ; //!< Reserved 358 uint32_t MpcPref08X8DisableFlagDefault0 : __CODEGEN_BITFIELD(10, 10) ; //!< MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 359 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 360 uint32_t Vlf720IOddHeightInVc1Mode : __CODEGEN_BITFIELD(14, 14) ; //!< VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 361 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 362 uint32_t VmbSvcTlbDummyFetchDisableForPerformance : __CODEGEN_BITFIELD(27, 27) ; //!< VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 363 uint32_t VmbSvcMvReplicationFor8X8EnableErrorHandling : __CODEGEN_BITFIELD(28, 28) ; //!< VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 364 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 365 }; 366 uint32_t Value; 367 } DW2; 368 union 369 { 370 //!< DWORD 3 371 struct 372 { 373 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 374 }; 375 uint32_t Value; 376 } DW3; 377 union 378 { 379 //!< DWORD 4 380 struct 381 { 382 uint32_t Reserved128 ; //!< Reserved 383 }; 384 uint32_t Value; 385 } DW4; 386 387 //! \name Local enumerations 388 389 enum SUBOPB 390 { 391 SUBOPB_MFXPIPEMODESELECT = 0, //!< No additional details 392 }; 393 394 enum SUBOPA 395 { 396 SUBOPA_UNNAMED0 = 0, //!< No additional details 397 }; 398 399 enum OPCODE 400 { 401 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 402 }; 403 404 enum PIPELINE 405 { 406 PIPELINE_MFXCOMMON = 2, //!< No additional details 407 }; 408 409 enum COMMAND_TYPE 410 { 411 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 412 }; 413 414 enum STANDARD_SELECT 415 { 416 STANDARD_SELECT_MPEG2 = 0, //!< No additional details 417 STANDARD_SELECT_VC1 = 1, //!< No additional details 418 STANDARD_SELECT_AVC = 2, //!< Covers both AVC and MVC 419 STANDARD_SELECT_JPEG = 3, //!< No additional details 420 STANDARD_SELECT_SVC = 4, //!< No additional details 421 STANDARD_SELECT_VP8 = 5, //!< Decoder starting from BDW, Encoder starting from SKL 422 STANDARD_SELECT_UVLD = 15, //!< SW decoder w/ embedded micro-controller and co-processor 423 }; 424 425 enum CODEC_SELECT 426 { 427 CODEC_SELECT_DECODE = 0, //!< No additional details 428 CODEC_SELECT_ENCODE = 1, //!< Valid only if StandardSel is AVC, MPEG2 and SVC) 429 }; 430 431 enum STITCH_MODE 432 { 433 STITCH_MODE_NOTINSTITCHMODE = 0, //!< No additional details 434 STITCH_MODE_INTHESPECIALSTITCHMODE = 1, //!< This mode can be used for any Codec as long as bitfield conditions are met. 435 }; 436 437 //! \brief FRAME_STATISTICS_STREAMOUT_ENABLE 438 //! \details 439 //! This field controls the frame level statistics streamout from the PAK. 440 //! <p><b>Note</b>: This field needs to be always "Enabled" in VD_Enc 441 //! mode. In case of non-VDEnc mode, 442 //! this can be used to control the frame statistics output from the 443 //! PAK.</p> 444 enum FRAME_STATISTICS_STREAMOUT_ENABLE 445 { 446 FRAME_STATISTICS_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 447 FRAME_STATISTICS_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 448 }; 449 450 //! \brief SCALED_SURFACE_ENABLE 451 //! \details 452 //! This field indicates if the scaled surface is enabled. This field 453 //! enables the 4x HME downscalar of the reconstructed image. Only 454 //! supported for AVC and VP8 formats. 455 enum SCALED_SURFACE_ENABLE 456 { 457 SCALED_SURFACE_ENABLE_DISABLE = 0, //!< No additional details 458 SCALED_SURFACE_ENABLE_ENABLE = 1, //!< No additional details 459 }; 460 461 //! \brief PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 462 //! \details 463 //! This field controls the output write for the reconstructed pixels BEFORE 464 //! the deblocking filter. 465 enum PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE 466 { 467 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 468 PRE_DEBLOCKING_OUTPUT_ENABLE_PREDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 469 }; 470 471 //! \brief POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 472 //! \details 473 //! This field controls the output write for the reconstructed pixels AFTER 474 //! the deblocking filter.In MPEG2 decoding mode, if this is enabled, VC1 475 //! deblocking filter is used. 476 enum POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE 477 { 478 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_DISABLE = 0, //!< No additional details 479 POST_DEBLOCKING_OUTPUT_ENABLE_POSTDEBLOCKOUTENABLE_ENABLE = 1, //!< No additional details 480 }; 481 482 //! \brief STREAM_OUT_ENABLE 483 //! \details 484 //! This field controls whether the macroblock parameter stream-out is 485 //! enabled during VLD decoding for transcoding purpose. 486 enum STREAM_OUT_ENABLE 487 { 488 STREAM_OUT_ENABLE_DISABLE = 0, //!< No additional details 489 STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 490 }; 491 492 //! \brief PIC_ERRORSTATUS_REPORT_ENABLE 493 //! \details 494 //! <p>This field control whether the error/status reporting is enable or 495 //! not.0: Disable1: EnableIn decoder modes: Error reporting is written out 496 //! once per frame. The Error Report frame ID listed in DW3 along with the 497 //! VLD/IT error status bits are packed into one cache and written to the 498 //! "Decoded Picture Error/Status Buffer address" listed in the 499 //! MFX_PIPE_BUF_ADDR_STATE Command. Note: driver shall program different 500 //! error buffer addresses between pictrues; otherwise, hardware might 501 //! overwrite previous written data if driver does not read it fast 502 //! enough.In encoder modes: Not used</p> 503 //! <p>Please refer to "Media VDBOX -> Video Codec -> Other Codec 504 //! Functions -> MFX Error Handling -> Decoder" session for the output 505 //! format.</p> 506 enum PIC_ERRORSTATUS_REPORT_ENABLE 507 { 508 PIC_ERRORSTATUS_REPORT_ENABLE_DISABLE = 0, //!< No additional details 509 PIC_ERRORSTATUS_REPORT_ENABLE_ENABLE = 1, //!< No additional details 510 }; 511 512 //! \brief DEBLOCKER_STREAM_OUT_ENABLE 513 //! \details 514 //! This field indicates if Deblocker information is going to be streamout 515 //! during VLD decoding. 516 //! For AVC, it is needed to enable the deblocker streamout as the AVC 517 //! Disable_DLKFilterIdc is a slice level parameters. Driver needs to 518 //! determine ahead of time if at least one slice of the current frame/ has 519 //! deblocker ON. 520 //! For SVC, there are two deblocking control streamout buffers 521 //! (specified in MFX_BUF_ADDR State Command). This field is still 522 //! associated with the slice level SVC Disable.DLK_Filter_Idc. 523 enum DEBLOCKER_STREAM_OUT_ENABLE 524 { 525 DEBLOCKER_STREAM_OUT_ENABLE_DISABLE = 0, //!< Disable streamout of deblocking control information for standalone deblocker operation.It needs other fields to determine one or two SVC deblocking surface streamout (Post Deblocking Output Enable, Pre Deblocking Output Enable, interlayer idc and regular deblock idc). 526 DEBLOCKER_STREAM_OUT_ENABLE_ENABLE = 1, //!< No additional details 527 }; 528 529 //! \brief VDENC_MODE 530 //! \details 531 //! This field indicates if PAK is working in legacy MBEnc mode or the VDEnc 532 //! mode. 533 enum VDENC_MODE 534 { 535 VDENC_MODE_MBENCMODE = 0, //!< PAK is working in legacy mode 536 VDENC_MODE_VDENCMODE = 1, //!< PAK is working in VDEnc mode 537 }; 538 539 //! \brief STANDALONE_VDENC_MODE_ENABLE 540 //! \details 541 //! This field indicates to PAK if this is standalone VDEnc mode. This is 542 //! primarily a validation mode. 543 enum STANDALONE_VDENC_MODE_ENABLE 544 { 545 STANDALONE_VDENC_MODE_ENABLE_VDENCPAK = 0, //!< No additional details 546 STANDALONE_VDENC_MODE_ENABLE_PAKONLY = 1, //!< No additional details 547 }; 548 549 //! \brief DECODER_MODE_SELECT 550 //! \details 551 //! Each coding standard supports two entry points: VLD entry point and IT 552 //! (IDCT) entry point. This field selects which one is in use.This field is 553 //! only valid if Codec Select is 0 (decoder). 554 enum DECODER_MODE_SELECT 555 { 556 DECODER_MODE_SELECT_VLDMODE = 0, //!< All codec minimum must support this mode Configure the MFD Engine for VLD ModeNote: All codec minimum must support this mode 557 DECODER_MODE_SELECT_ITMODE = 1, //!< Configure the MFD Engine for IT ModeNote: Only VC1 and MPEG2 support this mode 558 DECODER_MODE_SELECT_DEBLOCKERMODE = 2, //!< Configure the MFD Engine for Standalone Deblocker Mode. Require streamout AVC edge control information from preceeding decoding pass.Note: [HSW, EXCLUDE(HSW:GT3:A, HSW:GT3:B, HSW:GT2:B)] Only AVC, MPEG2 and SVC are supported. 559 DECODER_MODE_SELECT_INTERLAYERMODE = 3, //!< Configure the MFX Engine for standalone SVC interlayer upsampling for motion info, residual and reconstructed pixel. Require information being streamout from the preceding encoding and decoding pass of a reference layer.> 560 }; 561 562 //! \brief DECODER_SHORT_FORMAT_MODE 563 //! \details 564 //! For IT mode, this bit must be 0. 565 enum DECODER_SHORT_FORMAT_MODE 566 { 567 DECODER_SHORT_FORMAT_MODE_SHORTFORMATDRIVERINTERFACE = 0, //!< AVC/VC1/MVC/SVC/VP8 Short Format Mode is in useNote: There is no Short Format for SVC and VP8 yet, so this field must be set to 1 for SVC and VP8. 568 DECODER_SHORT_FORMAT_MODE_LONGFORMATDRIVERINTERFACE = 1, //!< AVC/VC1/MVC/SVC/VP8 Long Format Mode is in use. 569 }; 570 571 //! \brief VDS_ILDB_CALCULATION 572 //! \details 573 //! This bit forces all MB into INTRA MBs before doing ILDB control 574 //! generation in VDS. 575 enum VDS_ILDB_CALCULATION 576 { 577 VDS_ILDB_CALCULATION_DISABLE = 0, //!< Use original definition for ILDB calculation. 578 VDS_ILDB_CALCULATION_ENABLE = 1, //!< Force neighbor Intra MB = 1 on ILDB BS calculation. 579 }; 580 581 //! \brief CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 582 //! \details 583 //! BitFieldDesc: 584 enum CLOCK_GATE_ENABLE_AT_SLICE_LEVEL 585 { 586 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_DISABLE = 0, //!< Disable Slice-level Clock gating, Unit-level Clock gating will apply 587 CLOCK_GATE_ENABLE_AT_SLICE_LEVEL_ENABLE = 1, //!< Enable Slice-level Clock gating, overrides any Unit level Clock gating 588 }; 589 590 enum MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0 591 { 592 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_DISABLE = 0, //!< No additional details 593 MPC_PREF08X8_DISABLE_FLAG_DEFAULT_0_ENABLE = 1, //!< No additional details 594 }; 595 596 //! \brief VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 597 //! \details 598 //! This bit indicates VLF write out VC1 picture with odd height (in MBs). 599 enum VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ 600 { 601 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_DISABLE = 0, //!< No additional details 602 VLF_720I_ODD_HEIGHT_IN_VC1_MODE_ENABLE = 1, //!< 720i Enable 603 }; 604 605 //! \brief VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 606 //! \details 607 //! This bit disables TLB dummy fetch in SVC mode in VMB. 608 enum VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE 609 { 610 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_ENABLE = 0, //!< Enable VMB TLB Dummy Fetch for Performance 611 VMB_SVC_TLB_DUMMY_FETCH_DISABLE_FOR_PERFORMANCE_DISABLE = 1, //!< Disable VMB TLB Dummy Fetch 612 }; 613 614 //! \brief VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 615 //! \details 616 //! This bit enables Motion Vector replication on 8x8 level during SVC mode 617 //! for error handling. 618 enum VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING 619 { 620 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_DISABLE = 0, //!< Disable MV 8x8 replication in SVC mode 621 VMB_SVC_MV_REPLICATION_FOR_8X8_ENABLE_ERROR_HANDLING_ENABLE = 1, //!< Enable MV 8x8 Replication in SVC Mode 622 }; 623 624 //! \brief PIC_STATUSERROR_REPORT_ID 625 //! \details 626 //! In decoder modes: Error reporting is written out once per frame. This 627 //! field along with the VLD error status bits are packed into one cache and 628 //! written to the memory location specified by "Decoded Picture 629 //! Error/Status Buffer address" listed in the MFX_PIPE_BUF_ADDR_STATE 630 //! Command. 631 enum PIC_STATUSERROR_REPORT_ID 632 { 633 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 634 }; 635 636 //! \name Initializations 637 638 //! \brief Explicit member initialization function 639 MFX_PIPE_MODE_SELECT_CMD(); 640 641 static const size_t dwSize = 5; 642 static const size_t byteSize = 20; 643 }; 644 645 //! 646 //! \brief MFX_SURFACE_STATE 647 //! \details 648 //! This command is common for all encoding/decoding modes, to specify the 649 //! uncompressed YUV picture (i.e. destination surface) or intermediate 650 //! streamout in/out surface (e.g. coefficient/residual) (field, frame or 651 //! interleaved frame) format for reading and writing: Uncompressed, 652 //! original input picture to be encoded 653 //! Reconstructed non-filtered/filtered display picturec(becoming reference 654 //! pictures as well for subsequent temporal inter-prediction) 655 //! Residual in SVC 656 //! Reconstructed Intra pixel in SVC 657 //! CoeffPred in SVC 658 //! Since there is only one media surface state being active during the 659 //! entire encoding/decoding process, all the uncompressed/reconstructed 660 //! pictures are defined to have the same surface state. For each media 661 //! object call (decoding or encoding), multiple SVC surfaces can be active 662 //! concurrently, to distinguish among them, a surfaceID is added to 663 //! specify for each type of surface. The primary difference among picture 664 //! surface states is their individual programmed base addresses, which are 665 //! provided by other state commands and not included in this command. MFX 666 //! engine is making the association of surface states and corresponding 667 //! buffer base addresses. MFX engine currently supports only one media 668 //! surface type for video and that is the NV12 (Planar YUV420 with 669 //! interleaved U (Cb) and V (Cr). For optimizing memory efficiency based on 670 //! access patterns, only TileY is supported. For JPEG decoder, only IMC1 671 //! and IMC3 are supported. Pitch can be wider than the Picture Width in 672 //! pixels and garbage will be there at the end of each line. The following 673 //! describes all the different formats that are supported and not supported 674 //! in Gen7 MFX : NV12 - 4:2:0 only; UV interleaved; Full Pitch, U and V 675 //! offset is set to 0 (the only format supported for video codec); vertical 676 //! UV offset is MB aligned; UV xoffsets = 0. JPEG does not support NV12 677 //! format because non-interleave JPEG has performance issue with partial 678 //! write (in interleaved UV format) 679 //! IMC 1 & 3 - Full Pitch, U and V are separate plane; (JPEG only; U 680 //! plane + garbage first in full pitch followed by V plane + garbage in 681 //! full pitch). U and V vertical offsets are block aligned; U and V xoffset 682 //! = 0; there is no gap between Y, U and V planes. IMC1 and IMC3 are 683 //! different by a swap of U and V. This is the only format supported in 684 //! JPEG for all video subsampling types (4:4:4, 4:2:2 and 4:2:0) 685 //! We are not supporting IMC 2 & 4 - Full Pitch, U and V are separate 686 //! plane (JPEG only; U plane first in full pitch followed by V plane in 687 //! full pitch - U and V plane are side-by-side). U and V vertical offsets 688 //! are 16-pixel aligned; V xoffset is half-pitch aligned; U xoffset is 0; 689 //! there is no gap between Y, U and V planes. IMC2 and IMC4 are different 690 //! by a swap of U and V. 691 //! We are not supporting YV12 - half pitch for each U and V plane, and 692 //! separate planes for Y, U and V (U plane first in half pitch followed by 693 //! V plane in half pitch). For YV12, U and V vertical offsets are block 694 //! aligned; U and V xoffset = 0; there is no gap between Y, U and V planes 695 //! Note that the following data structures are not specified through the 696 //! media surface state 1D buffers for row-store and other miscellaneous 697 //! information. 698 //! 2D buffers for per-MB data-structures (e.g. DMV biffer, MB info record, 699 //! ILDB Control and Tcoeff/Stocoeff). 700 //! This surface state here is identical to the Surface State for 701 //! deinterlace and sample_8x8 messages described in the Shared Function 702 //! Volume and Sampler Chapter. For non pixel data, such as row stores, 703 //! indirect data (Compressed Slice Data, AVC MV record, Coeff record and 704 //! AVC ILDB record) and streamin/out and output compressed bitstream, a 705 //! linear buffer is employed. For row stores, the H/W is designed to 706 //! guarantee legal memory accesses (read and write). For the remaining 707 //! cases, indirect object base address, indirect object address upper 708 //! bound, object data start address (offset) and object data length are 709 //! used to fully specified their corresponding buffer. This mechanism is 710 //! chosen over the pixel surface type because of their variable record 711 //! sizes. All row store surfaces are linear surface. Their addresses are 712 //! programmed in Pipe_Buf_Base_State or Bsp_Buf_Base_Addr_State 713 //! 714 //! VC1 I picture scaling: Even though VC1 allows I reconstructed picture 715 //! scaling (via RESPIC), as such scaling is only allowed at I picture. All 716 //! subsequent P (and B) pictures must have the same picture dimensions with 717 //! the preceding I picture. Therefore, all reference pictures for P or B 718 //! picture can share the same surface state with the current P and B 719 //! picture. Note : H/W is not processing RESPIC. Application is no longer 720 //! expecting intel decoder pipelineand kernel to perform this function, it 721 //! is going to be done in the video post-processing scaler or display 722 //! controller scale as a separate step and controller. 723 //! 724 //! All video codec surfaces must be NV12 Compliant, except JPEG. U/V 725 //! vertical must be MB aligned for all video codec (further contrained for 726 //! field picture), but JPEG can be block aligned. All video codec and JPEG 727 //! uses Tiled - Y format only, for uncompressed pixel surfaces. 728 //! 729 //! Even for JPEG planar 420 surface, application may provide only 1 730 //! buffers, but there is still only one single surface state for all of 731 //! them. If IMC equal to 1, 2, 3 or 4, U and V have the pitch same as Y. 732 //! And U and V will have different offset, each offset is block aligned. 733 //! 734 struct MFX_SURFACE_STATE_CMD 735 { 736 union 737 { 738 //!< DWORD 0 739 struct 740 { 741 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 742 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 743 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 744 uint32_t Subopa : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPA 745 uint32_t Opcode : __CODEGEN_BITFIELD(24, 26) ; //!< OPCODE 746 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 747 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 748 }; 749 uint32_t Value; 750 } DW0; 751 union 752 { 753 //!< DWORD 1 754 struct 755 { 756 uint32_t SurfaceId : __CODEGEN_BITFIELD( 0, 3) ; //!< SURFACE_ID 757 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 758 }; 759 uint32_t Value; 760 } DW1; 761 union 762 { 763 //!< DWORD 2 764 struct 765 { 766 uint32_t CrVCbUPixelOffsetVDirection : __CODEGEN_BITFIELD( 0, 1) ; //!< Cr(V)/Cb(U) Pixel Offset V Direction 767 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 768 uint32_t Width : __CODEGEN_BITFIELD( 4, 17) ; //!< Width 769 uint32_t Height : __CODEGEN_BITFIELD(18, 31) ; //!< Height 770 }; 771 uint32_t Value; 772 } DW2; 773 union 774 { 775 //!< DWORD 3 776 struct 777 { 778 uint32_t TileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< TILE_WALK 779 uint32_t TiledSurface : __CODEGEN_BITFIELD( 1, 1) ; //!< TILED_SURFACE 780 uint32_t HalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Half Pitch for Chroma 781 uint32_t SurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Surface Pitch 782 uint32_t Reserved116 : __CODEGEN_BITFIELD( 20,26) ; //!< Reserved 783 uint32_t InterleaveChroma : __CODEGEN_BITFIELD(27, 27) ; //!< INTERLEAVE_CHROMA_ 784 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_FORMAT 785 }; 786 uint32_t Value; 787 } DW3; 788 union 789 { 790 //!< DWORD 4 791 struct 792 { 793 uint32_t YOffsetForUCb : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) 794 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 795 uint32_t XOffsetForUCb : __CODEGEN_BITFIELD(16, 30) ; //!< X Offset for U(Cb) 796 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 797 }; 798 uint32_t Value; 799 } DW4; 800 union 801 { 802 //!< DWORD 5 803 struct 804 { 805 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD( 0, 15) ; //!< Y Offset for V(Cr) 806 uint32_t XOffsetForVCr : __CODEGEN_BITFIELD(16, 28) ; //!< X Offset for V(Cr) 807 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 808 }; 809 uint32_t Value; 810 } DW5; 811 812 //! \name Local enumerations 813 814 enum SUBOPB 815 { 816 SUBOPB_UNNAMED1 = 1, //!< No additional details 817 }; 818 819 enum SUBOPA 820 { 821 SUBOPA_UNNAMED0 = 0, //!< No additional details 822 }; 823 824 enum OPCODE 825 { 826 OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 827 }; 828 829 enum PIPELINE 830 { 831 PIPELINE_MFXCOMMON = 2, //!< No additional details 832 }; 833 834 enum COMMAND_TYPE 835 { 836 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 837 }; 838 839 enum SURFACE_ID 840 { 841 SURFACE_ID_DECODEDPICTUREANDREFERENCEPICTURES_SVCUPSAMPLINGSTREAMOUTRECONSTRUCTEDPIXELSCOEFFPREDUPPERLAYERSIZE = 0, //!< 8-bit uncompressed data 842 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMOUTSURFACEUPPERLAYERSIZE = 1, //!< 16-bit uncompressed data 843 SURFACE_ID_SVCRECONSTRUCTEDPIXELANDCOEFFPREDUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 2, //!< 8-bit uncompressed data. 844 SURFACE_ID_SVCRESIDUALUPSAMPLINGSTREAMINSURFACELOWERLAYERSIZE = 3, //!< 16-bit uncompressed data 845 SURFACE_ID_SOURCEINPUTPICTUREENCODER = 4, //!< 8-bit uncompressed data 846 SURFACE_ID_RECONSTRUCTEDSCALEDREFERENCEPICTURE = 5, //!< 8-bit data 847 }; 848 849 //! \brief TILE_WALK 850 //! \details 851 //! (This field must be set to 1: TILEWALK_YMAJOR)This field specifies the 852 //! type of memory tiling (XMajor or YMajor) employed to tile this surface. 853 //! See Memory Interface Functions for details on memory tiling and 854 //! restrictions.This field is ignored when the surface is linear.This field 855 //! is ignored by MFX. Internally H/W is always treated this set to 1 for 856 //! all video codec and for JPEG. 857 enum TILE_WALK 858 { 859 TILE_WALK_XMAJOR = 0, //!< TILEWALK_XMAJOR 860 TILE_WALK_YMAJOR = 1, //!< TILEWALK_YMAJOR 861 }; 862 863 //! \brief TILED_SURFACE 864 //! \details 865 //! (This field must be set to TRUE: Tiled)This field specifies whether the 866 //! surface is tiled.This field is ignored by MFX 867 enum TILED_SURFACE 868 { 869 TILED_SURFACE_FALSE = 0, //!< Linear 870 TILED_SURFACE_TRUE = 1, //!< Tiled 871 }; 872 873 //! \brief INTERLEAVE_CHROMA_ 874 //! \details 875 //! This field indicates that the chroma fields are interleaved in a single 876 //! plane rather than stored as two separate planes. This field is only used 877 //! for PLANAR surface formats.For AVC/VC1/MPEG VLD and IT modes : set to 878 //! Enable to support interleave U/V only.For JPEG : set to Disable for all 879 //! formats (including 4:2:0) - because JPEG does not support NV12. (This 880 //! field is needed only if JPEG will support NV12; otherwise is ignored.) 881 enum INTERLEAVE_CHROMA_ 882 { 883 INTERLEAVE_CHROMA_DISABLE = 0, //!< No additional details 884 INTERLEAVE_CHROMA_ENABLE = 1, //!< No additional details 885 }; 886 887 //! \brief SURFACE_FORMAT 888 //! \details 889 //! Specifies the format of the surface. All of the Y and G channels will 890 //! use table 0 and all of the Cr/Cb/R/B channels will use table 1.Usage: 891 //! For 420 planar YUV surface, use 4; for monochrome surfaces, use 12. For 892 //! monochrome surfaces, hardware ignores control fields for Chroma 893 //! planes.This field must be set to 4 - PLANAR_420_8, or 12 - Y8_UNORMNot 894 //! used for MFX, and is ignored. But for JPEG decoding, this field should 895 //! be programmed to the same format as JPEG_PIC_STATE. For video codec, it 896 //! should set to 4 always. 897 enum SURFACE_FORMAT 898 { 899 SURFACE_FORMAT_YCRCBNORMAL = 0, //!< No additional details 900 SURFACE_FORMAT_YCRCBSWAPUVY = 1, //!< No additional details 901 SURFACE_FORMAT_YCRCBSWAPUV = 2, //!< No additional details 902 SURFACE_FORMAT_YCRCBSWAPY = 3, //!< No additional details 903 SURFACE_FORMAT_PLANAR_4208 = 4, //!< (NV12, IMC1,2,3,4, YV12) 904 SURFACE_FORMAT_PLANAR_4118 = 5, //!< Deinterlace Only 905 SURFACE_FORMAT_PLANAR_4228 = 6, //!< Deinterlace Only 906 SURFACE_FORMAT_STMMDNSTATISTICS = 7, //!< Deinterlace Only 907 SURFACE_FORMAT_R10G10B10A2UNORM = 8, //!< Sample_8x8 Only 908 SURFACE_FORMAT_R8G8B8A8UNORM = 9, //!< Sample_8x8 Only 909 SURFACE_FORMAT_R8B8UNORMCRCB = 10, //!< Sample_8x8 Only 910 SURFACE_FORMAT_R8UNORMCRCB = 11, //!< Sample_8x8 Only 911 SURFACE_FORMAT_Y8UNORM = 12, //!< Sample_8x8 Only 912 }; 913 914 //! \name Initializations 915 916 //! \brief Explicit member initialization function 917 MFX_SURFACE_STATE_CMD(); 918 919 static const size_t dwSize = 6; 920 static const size_t byteSize = 24; 921 }; 922 923 //! 924 //! \brief MFX_IND_OBJ_BASE_ADDR_STATE 925 //! \details 926 //! This state command provides the memory base addresses for all row 927 //! stores, StreamOut buffer and reconstructed picture output buffers 928 //! required by the MFD or MFC Engine (that are in addition to the row 929 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 930 //! reference picture buffers). This is a picture level state command and is 931 //! common among all codec standards and for both encoder and decoder 932 //! operating modes. However, some fields may only applicable to a specific 933 //! codec standard. All Pixel Surfaces (original, reference frame and 934 //! reconstructed frame) in the Encoder are programmed with the same surface 935 //! state (NV12 and TileY format), except each has its own frame buffer base 936 //! address. In the tile format, there is no need to provide buffer offset 937 //! for each slice; since from each MB address, the hardware can calculated 938 //! the corresponding memory location within the frame buffer directly. 939 //! 940 //! The MFX_IND_OBJ_BASE_ADDR command sets the memory base address pointers 941 //! for the corresponding Indirect Object Data Start Addresses (Offsets) 942 //! specified in each OBJECT commands. The characteristic of these indirect 943 //! object data is their variable size (per MB or per Slice). Hence, each 944 //! OBJECT command must specify the indirect object data offset from the 945 //! base address to start fetching or writing object data. 946 //! 947 //! While the use of base address is unconditional, the indirection can be 948 //! effectively disabled by setting the base address to zero. For decoder, 949 //! there are: 1 read-only per-slice indirect object in the BSD_OBJECT 950 //! Command, and 951 //! 2 read-only per-MB indirect objects in the IT_OBJECT Command. 952 //! For decoder: the Video Command Streamer (VCS) will perform the memory 953 //! access bound check automatically using the corresponding MFC Indirect 954 //! Object Access Upper Bound specification. If any access is at or beyond 955 //! the upper bound, zero value is returned. The request to memory is still 956 //! being sent, but the corresponding codec's BSD unit will detect this 957 //! condition and perform the zeroing return. If the Upper Bound is turned 958 //! off, the beyond bound request will return whatever on the bus (invalid 959 //! data). For encoder, there are: 1 read-only per-MB indirect object in 960 //! the PAK_OBJECT Command, and 961 //! 1 write-only per-slice indirect object in the PAK Slice_State Command 962 //! For encoder: whenever an out of bound address accessing request is 963 //! generated, VMX will detect such requests and snap the address to the 964 //! corresponding [indirect object base address + indirect data start 965 //! address]. VMX will return all 0s as the data to the requestor. 966 //! NotationDefinitionPhysicalAddress[n:m] Corresponding bits of a physical 967 //! graphics memory byte address (not mapped by a GTT) GraphicsAddress[n:m] 968 //! Corresponding bits of an absolute, virtual graphics memory byte address 969 //! (mapped by a GTT). 970 //! 971 struct MFX_IND_OBJ_BASE_ADDR_STATE_CMD 972 { 973 union 974 { 975 //!< DWORD 0 976 struct 977 { 978 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 979 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 980 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 981 uint32_t SubOpcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODEA 982 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 983 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 984 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 985 }; 986 uint32_t Value; 987 } DW0; 988 union 989 { 990 //!< DWORD 1 991 struct 992 { 993 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 994 uint32_t MfxIndirectBitstreamObjectBaseAddressDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Base Address (Decoder and Stitch Modes) 995 }; 996 uint32_t Value; 997 } DW1; 998 union 999 { 1000 //!< DWORD 2 1001 struct 1002 { 1003 uint32_t MfxIndirectBitstreamObjectDestinationAddressDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object - Destination Address (Decoder and Stitch Modes)[47:32] 1004 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1005 }; 1006 uint32_t Value; 1007 } DW2; 1008 union 1009 { 1010 //!< DWORD 3 1011 struct 1012 { 1013 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1014 uint32_t MfxIndirectBitstreamObjectbaseArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1015 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1016 uint32_t MfxIndirectBitstreamObjectTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1017 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1018 }; 1019 uint32_t Value; 1020 } DW3; 1021 union 1022 { 1023 //!< DWORD 4 1024 struct 1025 { 1026 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1027 uint32_t MfxIndirectBitstreamObjectAccessUpperBoundDecoderAndStitchModes : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect Bitstream Object - Access Upper Bound (Decoder and Stitch Modes) 1028 }; 1029 uint32_t Value; 1030 } DW4; 1031 union 1032 { 1033 //!< DWORD 5 1034 struct 1035 { 1036 uint32_t MfxIndirectBitstreamObjectUpperboundDecoderAndStitchModes4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect Bitstream Object UpperBound (Decoder and Stitch Modes)[47:32] 1037 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1038 }; 1039 uint32_t Value; 1040 } DW5; 1041 union 1042 { 1043 //!< DWORD 6 1044 struct 1045 { 1046 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1047 uint32_t MfxIndirectMvObjectBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object - Base Address 1048 }; 1049 uint32_t Value; 1050 } DW6; 1051 union 1052 { 1053 //!< DWORD 7 1054 struct 1055 { 1056 uint32_t MfxIndirectMvObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object Base Address [47:32] 1057 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1058 }; 1059 uint32_t Value; 1060 } DW7; 1061 union 1062 { 1063 //!< DWORD 8 1064 struct 1065 { 1066 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1067 uint32_t MfxIndirectMvObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1068 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1069 uint32_t MfxIndirectMvObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1070 uint32_t Reserved271 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1071 }; 1072 uint32_t Value; 1073 } DW8; 1074 union 1075 { 1076 //!< DWORD 9 1077 struct 1078 { 1079 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1080 uint32_t MfxIndirectMvObjectAccessUpperBound : __CODEGEN_BITFIELD(12, 31) ; //!< MFX Indirect MV Object Access Upper Bound 1081 }; 1082 uint32_t Value; 1083 } DW9; 1084 union 1085 { 1086 //!< DWORD 10 1087 struct 1088 { 1089 uint32_t MfxIndirectMvObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFX Indirect MV Object UpperBound [47:32] 1090 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1091 }; 1092 uint32_t Value; 1093 } DW10; 1094 union 1095 { 1096 //!< DWORD 11 1097 struct 1098 { 1099 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1100 uint32_t MfdIndirectItCoeffObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Base Address (Decoder Only) 1101 }; 1102 uint32_t Value; 1103 } DW11; 1104 union 1105 { 1106 //!< DWORD 12 1107 struct 1108 { 1109 uint32_t MfdIndirectItCoeffObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object Base Address [47:32] 1110 uint32_t Reserved400 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1111 }; 1112 uint32_t Value; 1113 } DW12; 1114 union 1115 { 1116 //!< DWORD 13 1117 struct 1118 { 1119 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1120 uint32_t MfdIndirectItCoeffObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1121 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1122 uint32_t MfdIndirectItCoeffTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1123 uint32_t Reserved431 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1124 }; 1125 uint32_t Value; 1126 } DW13; 1127 union 1128 { 1129 //!< DWORD 14 1130 struct 1131 { 1132 uint32_t Reserved448 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1133 uint32_t MfdIndirectItCoeffObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-COEFF Object - Access Upper Bound (Decoder Only) 1134 }; 1135 uint32_t Value; 1136 } DW14; 1137 union 1138 { 1139 //!< DWORD 15 1140 struct 1141 { 1142 uint32_t MfdIndirectItCoeffObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-COEFF Object UpperBound [47:32] 1143 uint32_t Reserved496 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1144 }; 1145 uint32_t Value; 1146 } DW15; 1147 union 1148 { 1149 //!< DWORD 16 1150 struct 1151 { 1152 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1153 uint32_t MfdIndirectItDblkObjectBaseAddressDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Base Address (Decoder Only) 1154 }; 1155 uint32_t Value; 1156 } DW16; 1157 union 1158 { 1159 //!< DWORD 17 1160 struct 1161 { 1162 uint32_t MfdIndirectItDblkObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object Base Address [47:32] 1163 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1164 }; 1165 uint32_t Value; 1166 } DW17; 1167 union 1168 { 1169 //!< DWORD 18 1170 struct 1171 { 1172 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1173 uint32_t MfdIndirectItDblkObjectArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1174 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1175 uint32_t MfdIndirectItDblkObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1176 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1177 }; 1178 uint32_t Value; 1179 } DW18; 1180 union 1181 { 1182 //!< DWORD 19 1183 struct 1184 { 1185 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1186 uint32_t MfdIndirectItDblkObjectAccessUpperBoundDecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFD Indirect IT-DBLK Object - Access Upper Bound (Decoder Only) 1187 }; 1188 uint32_t Value; 1189 } DW19; 1190 union 1191 { 1192 //!< DWORD 20 1193 struct 1194 { 1195 uint32_t MfdIndirectItDblkObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFD Indirect IT-DBLK Object UpperBound [47:32] 1196 uint32_t Reserved656 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1197 }; 1198 uint32_t Value; 1199 } DW20; 1200 union 1201 { 1202 //!< DWORD 21 1203 struct 1204 { 1205 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1206 uint32_t MfcIndirectPakBseObjectBaseAddressEncoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Base Address (Encoder Only) 1207 }; 1208 uint32_t Value; 1209 } DW21; 1210 union 1211 { 1212 //!< DWORD 22 1213 struct 1214 { 1215 uint32_t MfcIndirectPakBseObjectBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object Base Address [47:32] 1216 uint32_t Reserved720 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1217 }; 1218 uint32_t Value; 1219 } DW22; 1220 union 1221 { 1222 //!< DWORD 23 1223 struct 1224 { 1225 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1226 uint32_t MfcIndirectPakBseObjectDesitnationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1227 uint32_t Reserved745 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1228 uint32_t MfcIndirectPakBseObjectDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1229 uint32_t Reserved751 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1230 }; 1231 uint32_t Value; 1232 } DW23; 1233 union 1234 { 1235 //!< DWORD 24 1236 struct 1237 { 1238 uint32_t Reserved768 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1239 uint32_t MfcIndirectPakBseObjectAccessUpperBoundEecoderOnly : __CODEGEN_BITFIELD(12, 31) ; //!< MFC Indirect PAK-BSE Object - Access Upper Bound (Eecoder Only) 1240 }; 1241 uint32_t Value; 1242 } DW24; 1243 union 1244 { 1245 //!< DWORD 25 1246 struct 1247 { 1248 uint32_t MfcIndirectPakBseObjectUpperbound4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MFC Indirect PAK-BSE Object UpperBound [47:32] 1249 uint32_t Reserved816 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1250 }; 1251 uint32_t Value; 1252 } DW25; 1253 1254 //! \name Local enumerations 1255 1256 enum SUBOPCODEB 1257 { 1258 SUBOPCODEB_MFXINDOBJBASEADDRSTATE = 3, //!< No additional details 1259 }; 1260 1261 enum SUB_OPCODEA 1262 { 1263 SUB_OPCODEA_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1264 }; 1265 1266 enum COMMON_OPCODE 1267 { 1268 COMMON_OPCODE_MFXINDOBJBASEADDRSTATE = 0, //!< No additional details 1269 }; 1270 1271 enum PIPELINE 1272 { 1273 PIPELINE_MFXINDOBJBASEADDRSTATE = 2, //!< No additional details 1274 }; 1275 1276 enum COMMAND_TYPE 1277 { 1278 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1279 }; 1280 1281 //! \brief MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1282 //! \details 1283 //! This field controls the priority of arbitration used in the GAC/GAM 1284 //! pipeline for this surface. 1285 enum MFX_INDIRECT_BITSTREAM_OBJECTBASE__ARBITRATION_PRIORITY_CONTROL 1286 { 1287 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1288 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1289 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1290 MFX_INDIRECT_BITSTREAM_OBJECTBASE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1291 }; 1292 1293 //! \brief MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1294 //! \details 1295 //! <b>For Media Surfaces:</b> 1296 //! This field specifies the tiled resource mode. 1297 enum MFX_INDIRECT_BITSTREAM_OBJECT__TILED_RESOURCE_MODE 1298 { 1299 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1300 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1301 MFX_INDIRECT_BITSTREAM_OBJECT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1302 }; 1303 1304 //! \brief MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1305 //! \details 1306 //! This field controls the priority of arbitration used in the GAC/GAM 1307 //! pipeline for this surface. 1308 enum MFX_INDIRECT_MV_OBJECT__ARBITRATION_PRIORITY_CONTROL 1309 { 1310 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1311 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1312 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1313 MFX_INDIRECT_MV_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1314 }; 1315 1316 //! \brief MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1317 //! \details 1318 //! <b>For Media Surfaces:</b> 1319 //! This field specifies the tiled resource mode. 1320 enum MFX_INDIRECT_MV_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1321 { 1322 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1323 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1324 MFX_INDIRECT_MV_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1325 }; 1326 1327 //! \brief MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1328 //! \details 1329 //! This field controls the priority of arbitration used in the GAC/GAM 1330 //! pipeline for this surface. 1331 enum MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1332 { 1333 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1334 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1335 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1336 MFD_INDIRECT_IT_COEFF_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1337 }; 1338 1339 //! \brief MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1340 //! \details 1341 //! <b>For Media Surfaces:</b> 1342 //! This field specifies the tiled resource mode. 1343 enum MFD_INDIRECT_IT_COEFF__TILED_RESOURCE_MODE 1344 { 1345 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1346 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1347 MFD_INDIRECT_IT_COEFF_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1348 }; 1349 1350 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1351 //! \details 1352 //! This field controls the priority of arbitration used in the GAC/GAM 1353 //! pipeline for this surface. 1354 enum MFD_INDIRECT_IT_DBLK_OBJECT__ARBITRATION_PRIORITY_CONTROL 1355 { 1356 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1357 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1358 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1359 MFD_INDIRECT_IT_DBLK_OBJECT_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1360 }; 1361 1362 //! \brief MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1363 //! \details 1364 //! <b>For Media Surfaces:</b> 1365 //! This field specifies the tiled resource mode. 1366 enum MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1367 { 1368 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1369 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1370 MFD_INDIRECT_IT_DBLK_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1371 }; 1372 1373 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1374 //! \details 1375 //! This field controls the priority of arbitration used in the GAC/GAM 1376 //! pipeline for this surface. 1377 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION__ARBITRATION_PRIORITY_CONTROL 1378 { 1379 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1380 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1381 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1382 MFC_INDIRECT_PAK_BSE_OBJECT_DESITNATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1383 }; 1384 1385 //! \brief MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1386 //! \details 1387 //! <b>For Media Surfaces:</b> 1388 //! This field specifies the tiled resource mode. 1389 enum MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION__TILED_RESOURCE_MODE 1390 { 1391 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1392 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1393 MFC_INDIRECT_PAK_BSE_OBJECT_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1394 }; 1395 1396 //! \name Initializations 1397 1398 //! \brief Explicit member initialization function 1399 MFX_IND_OBJ_BASE_ADDR_STATE_CMD(); 1400 1401 static const size_t dwSize = 26; 1402 static const size_t byteSize = 104; 1403 }; 1404 1405 //! 1406 //! \brief MFX_BSP_BUF_BASE_ADDR_STATE 1407 //! \details 1408 //! This frame-level state command is used to specify all the buffer base 1409 //! addresses needed for the operation of the AVC Bit Stream Processing 1410 //! Units (for decoder, it is BSD Unit; for encoder, it is BSE Unit) For 1411 //! both encoder and decoder, currently it is assumed that all codec 1412 //! standards can share the same BSP_BUF_BASE_STATE. The simplicity of this 1413 //! command is the result of moving all the direct MV related processing 1414 //! into the ENC Subsystem. Since all implicit weight calculations and 1415 //! directMV calculations are done in ENC and all picture buffer management 1416 //! are done in the Host, there is no need to provide POC (POC List - 1417 //! FieldOrderCntList, CurrPic POC - CurrFieldOrderCnt) information to PAK. 1418 //! For decoder, all the direct mode information are sent in a separate 1419 //! slice-level command (AVC_DIRECTMODE_STATE command). In addition, in 1420 //! Encoder, the row stores for CABAC encoding and MB Parameters 1421 //! Construction (MPC) are combined into one single row store. The row 1422 //! stores specified in this command do not combine with those specified in 1423 //! the MFC_PIPE_BUF_ADDR_STATE command for hardware simplification reason. 1424 //! 1425 struct MFX_BSP_BUF_BASE_ADDR_STATE_CMD 1426 { 1427 union 1428 { 1429 //!< DWORD 0 1430 struct 1431 { 1432 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1433 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1434 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1435 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1436 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1437 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1438 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1439 }; 1440 uint32_t Value; 1441 } DW0; 1442 union 1443 { 1444 //!< DWORD 1 1445 struct 1446 { 1447 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1448 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite : __CODEGEN_BITFIELD( 6, 31) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write 1449 }; 1450 uint32_t Value; 1451 } DW1; 1452 union 1453 { 1454 //!< DWORD 2 1455 struct 1456 { 1457 uint32_t BsdMpcRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< BSD/MPC Row Store Scratch Buffer Base Address - Read/Write [47:32] 1458 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1459 }; 1460 uint32_t Value; 1461 } DW2; 1462 union 1463 { 1464 //!< DWORD 3 1465 struct 1466 { 1467 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1468 uint32_t BsdMpcRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1469 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1470 uint32_t BsdMpcRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1471 uint32_t BsdMpcRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1472 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1473 }; 1474 uint32_t Value; 1475 } DW3; 1476 union 1477 { 1478 //!< DWORD 4 1479 struct 1480 { 1481 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1482 uint32_t MprRowStoreScratchBufferBaseAddressReadWriteDecoderOnly : __CODEGEN_BITFIELD( 6, 31) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write (Decoder Only) 1483 }; 1484 uint32_t Value; 1485 } DW4; 1486 union 1487 { 1488 //!< DWORD 5 1489 struct 1490 { 1491 uint32_t MprRowStoreScratchBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< MPR Row Store Scratch Buffer Base Address - Read/Write [47:32] 1492 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1493 }; 1494 uint32_t Value; 1495 } DW5; 1496 union 1497 { 1498 //!< DWORD 6 1499 struct 1500 { 1501 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1502 uint32_t MprRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1503 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 11) ; //!< Reserved 1504 uint32_t MprRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1505 uint32_t MprRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1506 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1507 }; 1508 uint32_t Value; 1509 } DW6; 1510 union 1511 { 1512 //!< DWORD 7 1513 struct 1514 { 1515 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1516 uint32_t BitplaneReadBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitplane Read Buffer Base Address 1517 }; 1518 uint32_t Value; 1519 } DW7; 1520 union 1521 { 1522 //!< DWORD 8 1523 struct 1524 { 1525 uint32_t BitplaneReadBufferBaseAddressReadWrite4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Bitplane Read Buffer Base Address - Read/Write [47:32] 1526 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1527 }; 1528 uint32_t Value; 1529 } DW8; 1530 union 1531 { 1532 //!< DWORD 9 1533 struct 1534 { 1535 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 1536 uint32_t BitplaneReadBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1537 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 1538 uint32_t BitplaneReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1539 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1540 }; 1541 uint32_t Value; 1542 } DW9; 1543 1544 //! \name Local enumerations 1545 1546 enum SUBOPCODE_B 1547 { 1548 SUBOPCODE_B_UNNAMED_4 = 4, //!< No additional details 1549 }; 1550 1551 enum SUBOPCODE_A 1552 { 1553 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 1554 }; 1555 1556 enum MEDIA_COMMAND_OPCODE 1557 { 1558 MEDIA_COMMAND_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 1559 }; 1560 1561 enum PIPELINE 1562 { 1563 PIPELINE_PIPELINE = 2, //!< No additional details 1564 }; 1565 1566 enum COMMAND_TYPE 1567 { 1568 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1569 }; 1570 1571 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1572 //! \details 1573 //! This field controls the priority of arbitration used in the GAC/GAM 1574 //! pipeline for this surface. 1575 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1576 { 1577 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1578 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1579 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1580 BSDMPC_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1581 }; 1582 1583 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1584 //! \details 1585 //! This field controls if Intra Row Store is going to store inside Media 1586 //! Internal Storage or to LLC. 1587 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1588 { 1589 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1590 BSDMPC_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1591 }; 1592 1593 //! \brief BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1594 //! \details 1595 //! <b>For Media Surfaces:</b> 1596 //! This field specifies the tiled resource mode. 1597 enum BSDMPC_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1598 { 1599 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1600 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1601 BSDMPC_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1602 }; 1603 1604 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1605 //! \details 1606 //! This field controls the priority of arbitration used in the GAC/GAM 1607 //! pipeline for this surface. 1608 enum MPR_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 1609 { 1610 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1611 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1612 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1613 MPR_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1614 }; 1615 1616 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1617 //! \details 1618 //! This field controls if Intra Row Store is going to store inside Media 1619 //! Internal Storage or to LLC. 1620 enum MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1621 { 1622 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 1623 MPR_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 1624 }; 1625 1626 //! \brief MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1627 //! \details 1628 //! <b>For Media Surfaces:</b> 1629 //! This field specifies the tiled resource mode. 1630 enum MPR_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 1631 { 1632 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1633 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1634 MPR_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1635 }; 1636 1637 //! \brief BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1638 //! \details 1639 //! This field controls the priority of arbitration used in the GAC/GAM 1640 //! pipeline for this surface. 1641 enum BITPLANE_READ_BUFFER__ARBITRATION_PRIORITY_CONTROL 1642 { 1643 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 1644 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 1645 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 1646 BITPLANE_READ_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 1647 }; 1648 1649 //! \brief BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1650 //! \details 1651 //! <b>For Media Surfaces:</b> 1652 //! This field specifies the tiled resource mode. 1653 enum BITPLANE_READ_BUFFER__TILED_RESOURCE_MODE 1654 { 1655 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 1656 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 1657 BITPLANE_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 1658 }; 1659 1660 //! \name Initializations 1661 1662 //! \brief Explicit member initialization function 1663 MFX_BSP_BUF_BASE_ADDR_STATE_CMD(); 1664 1665 static const size_t dwSize = 10; 1666 static const size_t byteSize = 40; 1667 }; 1668 1669 //! 1670 //! \brief MFD_AVC_PICID_STATE 1671 //! \details 1672 //! This is a frame level state command used for both AVC Long and Short 1673 //! Format in VLD mode.PictureID[16] contains the pictureID of each 1674 //! reference picture (16 maximum) so hardware can uniquely identify the 1675 //! reference picture across frames (this will be used for DMV 1676 //! operation).This command will be needed for both short and long format. 1677 //! 1678 struct MFD_AVC_PICID_STATE_CMD 1679 { 1680 union 1681 { 1682 //!< DWORD 0 1683 struct 1684 { 1685 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1686 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1687 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1688 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1689 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1690 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1691 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1692 }; 1693 uint32_t Value; 1694 } DW0; 1695 union 1696 { 1697 //!< DWORD 1 1698 struct 1699 { 1700 uint32_t PictureidRemappingDisable : __CODEGEN_BITFIELD( 0, 0) ; //!< PICTUREID_REMAPPING_DISABLE 1701 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 1702 }; 1703 uint32_t Value; 1704 } DW1; 1705 1706 uint32_t Pictureidlist1616Bits[8]; //!< PictureIDList[16][16 bits] 1707 1708 //! \name Local enumerations 1709 1710 enum SUBOPCODE_B 1711 { 1712 SUBOPCODE_B_MEDIA = 5, //!< No additional details 1713 }; 1714 1715 enum SUBOPCODE_A 1716 { 1717 SUBOPCODE_A_DEC = 1, //!< No additional details 1718 }; 1719 1720 enum MEDIA_COMMAND_OPCODE 1721 { 1722 MEDIA_COMMAND_OPCODE_MFDAVCDPBSTATE = 1, //!< No additional details 1723 }; 1724 1725 enum PIPELINE 1726 { 1727 PIPELINE_MFXMULTIDW = 2, //!< No additional details 1728 }; 1729 1730 enum COMMAND_TYPE 1731 { 1732 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1733 }; 1734 1735 //! \brief PICTUREID_REMAPPING_DISABLE 1736 //! \details 1737 //! If Picture ID Remapping Disable is "1", PictureIDList will not be used. 1738 enum PICTUREID_REMAPPING_DISABLE 1739 { 1740 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE16BITSPICTUREIDTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURE = 0, //!< Desc 1741 PICTUREID_REMAPPING_DISABLE_AVCDECODERWILLUSE_4BITSFRAMESTOREIDINDEXTOREFFRAMELISTTOHANDLEDMVANDIDENTIFYTHEREFERENCEPICTURETHISCAUSESDMVLOGICTOFUNCTIONTHESAMEINPROJECTIVBANDBEFORE = 1, //!< Desc 1742 }; 1743 1744 //! \name Initializations 1745 1746 //! \brief Explicit member initialization function 1747 MFD_AVC_PICID_STATE_CMD(); 1748 1749 static const size_t dwSize = 10; 1750 static const size_t byteSize = 40; 1751 }; 1752 1753 //! 1754 //! \brief MFX_AVC_IMG_STATE 1755 //! \details 1756 //! This must be the very first command to issue after the surface state, 1757 //! the pipe select and base address setting commands. This command supports 1758 //! both Long and Short VLD and IT AVC Decoding Interface. 1759 //! 1760 struct MFX_AVC_IMG_STATE_CMD 1761 { 1762 union 1763 { 1764 //!< DWORD 0 1765 struct 1766 { 1767 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1768 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1769 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 1770 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 1771 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 1772 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1773 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1774 }; 1775 uint32_t Value; 1776 } DW0; 1777 union 1778 { 1779 //!< DWORD 1 1780 struct 1781 { 1782 uint32_t FrameSize : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Size 1783 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1784 }; 1785 uint32_t Value; 1786 } DW1; 1787 union 1788 { 1789 //!< DWORD 2 1790 struct 1791 { 1792 uint32_t FrameWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width 1793 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 1794 uint32_t FrameHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height 1795 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1796 }; 1797 uint32_t Value; 1798 } DW2; 1799 union 1800 { 1801 //!< DWORD 3 1802 struct 1803 { 1804 uint32_t Reserved96 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 1805 uint32_t ImgstructImageStructureImgStructure10 : __CODEGEN_BITFIELD( 8, 9) ; //!< IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 1806 uint32_t WeightedBipredIdc : __CODEGEN_BITFIELD(10, 11) ; //!< WEIGHTED_BIPRED_IDC 1807 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(12, 12) ; //!< WEIGHTED_PRED_FLAG 1808 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD(13, 13) ; //!< RHODOMAIN_RATE_CONTROL_ENABLE 1809 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1810 uint32_t FirstChromaQpOffset : __CODEGEN_BITFIELD(16, 20) ; //!< First Chroma QP Offset 1811 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 1812 uint32_t SecondChromaQpOffset : __CODEGEN_BITFIELD(24, 28) ; //!< Second Chroma QP Offset 1813 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1814 }; 1815 uint32_t Value; 1816 } DW3; 1817 union 1818 { 1819 //!< DWORD 4 1820 struct 1821 { 1822 uint32_t Fieldpicflag : __CODEGEN_BITFIELD( 0, 0) ; //!< FIELDPICFLAG 1823 uint32_t Mbaffflameflag : __CODEGEN_BITFIELD( 1, 1) ; //!< MBAFFFLAMEFLAG 1824 uint32_t Framembonlyflag : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEMBONLYFLAG 1825 uint32_t Transform8X8Flag : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSFORM8X8FLAG 1826 uint32_t Direct8X8Infflag : __CODEGEN_BITFIELD( 4, 4) ; //!< DIRECT8X8INFFLAG 1827 uint32_t Constrainedipredflag : __CODEGEN_BITFIELD( 5, 5) ; //!< CONSTRAINEDIPREDFLAG 1828 uint32_t Imgdisposableflag : __CODEGEN_BITFIELD( 6, 6) ; //!< IMGDISPOSABLEFLAG 1829 uint32_t Entropycodingflag : __CODEGEN_BITFIELD( 7, 7) ; //!< ENTROPYCODINGFLAG 1830 uint32_t Mbmvformatflag : __CODEGEN_BITFIELD( 8, 8) ; //!< MBMVFORMATFLAG 1831 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 1832 uint32_t Chromaformatidc : __CODEGEN_BITFIELD(10, 11) ; //!< CHROMAFORMATIDC 1833 uint32_t Mvunpackedflag : __CODEGEN_BITFIELD(12, 12) ; //!< MVUNPACKEDFLAG 1834 uint32_t Reserved141 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 1835 uint32_t Loadslicepointerflag : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG 1836 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 1837 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 1838 }; 1839 uint32_t Value; 1840 } DW4; 1841 union 1842 { 1843 //!< DWORD 5 1844 struct 1845 { 1846 uint32_t IntrambmaxbitflagIntrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 1847 uint32_t IntermbmaxbitflagIntermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 1848 uint32_t FrameszoverflagFramebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 1849 uint32_t FrameszunderflagFramebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 1850 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 6) ; //!< Reserved 1851 uint32_t IntraIntermbipcmflagForceipcmcontrolmask : __CODEGEN_BITFIELD( 7, 7) ; //!< INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 1852 uint32_t Reserved168 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 1853 uint32_t MbratectrlflagMbLevelRateControlEnablingFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 1854 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 1855 uint32_t Reserved172 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1856 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 1857 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 26) ; //!< Reserved 1858 uint32_t TrellisQuantizationChromaDisableTqchromadisable : __CODEGEN_BITFIELD(27, 27) ; //!< TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 1859 uint32_t TrellisQuantizationRoundingTqr : __CODEGEN_BITFIELD(28, 30) ; //!< TRELLIS_QUANTIZATION_ROUNDING_TQR 1860 uint32_t TrellisQuantizationEnabledTqenb : __CODEGEN_BITFIELD(31, 31) ; //!< TRELLIS_QUANTIZATION_ENABLED_TQENB 1861 }; 1862 uint32_t Value; 1863 } DW5; 1864 union 1865 { 1866 //!< DWORD 6 1867 struct 1868 { 1869 uint32_t Intrambmaxsz : __CODEGEN_BITFIELD( 0, 11) ; //!< IntraMbMaxSz 1870 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1871 uint32_t Intermbmaxsz : __CODEGEN_BITFIELD(16, 27) ; //!< InterMbMaxSz 1872 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1873 }; 1874 uint32_t Value; 1875 } DW6; 1876 union 1877 { 1878 //!< DWORD 7 1879 struct 1880 { 1881 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 1882 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 15) ; //!< Reserved 1883 uint32_t BspEncoderEcoEnable : __CODEGEN_BITFIELD(16, 16) ; //!< BSP_ENCODER_ECO_ENABLE 1884 uint32_t Reserved241 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1885 }; 1886 uint32_t Value; 1887 } DW7; 1888 union 1889 { 1890 //!< DWORD 8 1891 struct 1892 { 1893 uint32_t Slicedeltaqppmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpPMax[0] 1894 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMax[1] 1895 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMax[2] 1896 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMax[3] 1897 }; 1898 uint32_t Value; 1899 } DW8; 1900 union 1901 { 1902 //!< DWORD 9 1903 struct 1904 { 1905 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQpMin[0] 1906 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQpMin[1] 1907 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQpMin[2] 1908 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQpMin[3] 1909 }; 1910 uint32_t Value; 1911 } DW9; 1912 union 1913 { 1914 //!< DWORD 10 1915 struct 1916 { 1917 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1918 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 1919 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 1920 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 1921 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 1922 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 1923 }; 1924 uint32_t Value; 1925 } DW10; 1926 union 1927 { 1928 //!< DWORD 11 1929 struct 1930 { 1931 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 1932 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1933 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1934 uint32_t SliceStatsStreamoutEnable : __CODEGEN_BITFIELD(31, 31) ; //!< Slice Stats Streamout Enable 1935 }; 1936 uint32_t Value; 1937 } DW11; 1938 union 1939 { 1940 //!< DWORD 12 1941 struct 1942 { 1943 uint32_t Reserved384 ; //!< Reserved 1944 }; 1945 uint32_t Value; 1946 } DW12; 1947 union 1948 { 1949 //!< DWORD 13 1950 struct 1951 { 1952 uint32_t InitialQpValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Initial QP Value 1953 uint32_t NumberOfActiveReferencePicturesFromL0 : __CODEGEN_BITFIELD( 8, 13) ; //!< Number of Active Reference Pictures from L0 1954 uint32_t Reserved430 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1955 uint32_t NumberOfActiveReferencePicturesFromL1 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Active Reference Pictures from L1 1956 uint32_t Reserved438 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 1957 uint32_t NumberOfReferenceFrames : __CODEGEN_BITFIELD(24, 28) ; //!< Number of Reference Frames 1958 uint32_t CurrentPictureHasPerformedMmco5 : __CODEGEN_BITFIELD(29, 29) ; //!< Current Picture Has Performed MMCO5 1959 uint32_t Reserved446 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1960 }; 1961 uint32_t Value; 1962 } DW13; 1963 union 1964 { 1965 //!< DWORD 14 1966 struct 1967 { 1968 uint32_t PicOrderPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< Pic_order_present_flag 1969 uint32_t DeltaPicOrderAlwaysZeroFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< Delta_pic_order_always_zero_flag 1970 uint32_t PicOrderCntType : __CODEGEN_BITFIELD( 2, 3) ; //!< Pic_order_cnt_type 1971 uint32_t Reserved452 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 1972 uint32_t SliceGroupMapType : __CODEGEN_BITFIELD( 8, 10) ; //!< slice_group_map_type 1973 uint32_t RedundantPicCntPresentFlag : __CODEGEN_BITFIELD(11, 11) ; //!< redundant_pic_cnt_present_flag 1974 uint32_t NumSliceGroupsMinus1 : __CODEGEN_BITFIELD(12, 14) ; //!< num_slice_groups_minus1 1975 uint32_t DeblockingFilterControlPresentFlag : __CODEGEN_BITFIELD(15, 15) ; //!< deblocking_filter_control_present_flag 1976 uint32_t Log2MaxFrameNumMinus4 : __CODEGEN_BITFIELD(16, 23) ; //!< Log2_max_frame_num_minus4 1977 uint32_t Log2MaxPicOrderCntLsbMinus4 : __CODEGEN_BITFIELD(24, 31) ; //!< Log2_max_pic_order_cnt_lsb_minus4 1978 }; 1979 uint32_t Value; 1980 } DW14; 1981 union 1982 { 1983 //!< DWORD 15 1984 struct 1985 { 1986 uint32_t SliceGroupChangeRate : __CODEGEN_BITFIELD( 0, 15) ; //!< Slice Group Change Rate 1987 uint32_t CurrPicFrameNum : __CODEGEN_BITFIELD(16, 31) ; //!< Curr Pic Frame Num 1988 }; 1989 uint32_t Value; 1990 } DW15; 1991 union 1992 { 1993 //!< DWORD 16 1994 struct 1995 { 1996 uint32_t CurrentFrameViewId : __CODEGEN_BITFIELD( 0, 9) ; //!< Current Frame View ID 1997 uint32_t Reserved522 : __CODEGEN_BITFIELD(10, 11) ; //!< Reserved 1998 uint32_t MaxViewIdxl0 : __CODEGEN_BITFIELD(12, 15) ; //!< Max View IDXL0 1999 uint32_t Reserved528 : __CODEGEN_BITFIELD(16, 17) ; //!< Reserved 2000 uint32_t MaxViewIdxl1 : __CODEGEN_BITFIELD(18, 21) ; //!< Max View IDXL1 2001 uint32_t Reserved534 : __CODEGEN_BITFIELD(22, 30) ; //!< Reserved 2002 uint32_t InterViewOrderDisable : __CODEGEN_BITFIELD(31, 31) ; //!< INTER_VIEW_ORDER_DISABLE 2003 }; 2004 uint32_t Value; 2005 } DW16; 2006 union 2007 { 2008 //!< DWORD 17 2009 struct 2010 { 2011 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP input 2012 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP offset 2013 uint32_t Reserved550 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2014 uint32_t ExtendedRhodomainStatisticsEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Extended RhoDomain Statistics Enable 2015 uint32_t Reserved553 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2016 uint32_t RhodomainAveragemacroblockqp : __CODEGEN_BITFIELD(16, 21) ; //!< RhoDomain AverageMacroblockQP 2017 uint32_t Reserved566 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 2018 }; 2019 uint32_t Value; 2020 } DW17; 2021 union 2022 { 2023 //!< DWORD 18 2024 struct 2025 { 2026 uint32_t Reserved576 ; //!< Reserved 2027 }; 2028 uint32_t Value; 2029 } DW18; 2030 union 2031 { 2032 //!< DWORD 19 2033 struct 2034 { 2035 uint32_t ThresholdSizeInBytes ; //!< Threshold Size in Bytes 2036 }; 2037 uint32_t Value; 2038 } DW19; 2039 union 2040 { 2041 //!< DWORD 20 2042 struct 2043 { 2044 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 2045 }; 2046 uint32_t Value; 2047 } DW20; 2048 2049 //! \name Local enumerations 2050 2051 enum SUBOPCODE_B 2052 { 2053 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 2054 }; 2055 2056 enum SUBOPCODE_A 2057 { 2058 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2059 }; 2060 2061 enum MEDIA_COMMAND_OPCODE 2062 { 2063 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2064 }; 2065 2066 enum PIPELINE 2067 { 2068 PIPELINE_MFXAVCIMGSTATE = 2, //!< No additional details 2069 }; 2070 2071 enum COMMAND_TYPE 2072 { 2073 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2074 }; 2075 2076 //! \brief IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2077 //! \details 2078 //! The current encoding picture structure can only takes on 3 possible 2079 //! values 2080 enum IMGSTRUCT__IMAGE_STRUCTURE_IMG_STRUCTURE10 2081 { 2082 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_FRAMEPICTURE = 0, //!< No additional details 2083 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_TOPFIELDPICTURE = 1, //!< No additional details 2084 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_INVALID_NOTALLOWED = 2, //!< No additional details 2085 IMGSTRUCT_IMAGE_STRUCTURE_IMG_STRUCTURE10_BOTTOMFIELDPICTURE = 3, //!< No additional details 2086 }; 2087 2088 //! \brief WEIGHTED_BIPRED_IDC 2089 //! \details 2090 //! (This field is defined differently from DevSNB; DevIVB follows strictly AVC interface.) 2091 enum WEIGHTED_BIPRED_IDC 2092 { 2093 WEIGHTED_BIPRED_IDC_DEFAULT = 0, //!< Specifies that the default weighted prediction is used for B slices 2094 WEIGHTED_BIPRED_IDC_EXPLICIT = 1, //!< Specifies that explicit weighted prediction is used for B slices 2095 WEIGHTED_BIPRED_IDC_IMPLICIT = 2, //!< Specifies that implicit weighted prediction is used for B slices. 2096 }; 2097 2098 //! \brief WEIGHTED_PRED_FLAG 2099 //! \details 2100 //! (This field is defined differently from Gen6, Gen7 follows strictly AVC interface.) 2101 enum WEIGHTED_PRED_FLAG 2102 { 2103 WEIGHTED_PRED_FLAG_DISABLE = 0, //!< specifies that weighted prediction is not used for P and SP slices 2104 WEIGHTED_PRED_FLAG_ENABLE = 1, //!< specifies that weighted prediction is used for P and SP slices 2105 }; 2106 2107 //! \brief RHODOMAIN_RATE_CONTROL_ENABLE 2108 //! \details 2109 //! This field indicates if RhoDomain related parameters are present in the 2110 //! MFX_AVC_IMAGE_STATE. (AverageMacroblockQP). It enables the Rho Domain 2111 //! statistics collection. 2112 enum RHODOMAIN_RATE_CONTROL_ENABLE 2113 { 2114 RHODOMAIN_RATE_CONTROL_ENABLE_DISABLE = 0, //!< RhoDomain rate control parameters are not present in MFX_AVC_IMAGE_STATE 2115 RHODOMAIN_RATE_CONTROL_ENABLE_ENABLE = 1, //!< RhoDomain rate control parameters are present in MFX_AVC_IMAGE_STATE. 2116 }; 2117 2118 //! \brief FIELDPICFLAG 2119 //! \details 2120 //! Field picture flag, field_pic_flag, specifies the current slice is a 2121 //! coded field or not.It is set to the same value as the syntax element in 2122 //! the Slice Header. It must be consistent with the img_structure[1:0] and 2123 //! the frame_mbs_only_flag settings.Although field_pic_flag is a Slice 2124 //! Header parameter, its value is expected to be the same for all the 2125 //! slices of a picture. 2126 enum FIELDPICFLAG 2127 { 2128 FIELDPICFLAG_FRAME = 0, //!< a slice of a coded frame 2129 FIELDPICFLAG_FIELD = 1, //!< a slice of a coded field 2130 }; 2131 2132 //! \brief MBAFFFLAMEFLAG 2133 //! \details 2134 //! MBAFF mode is active, mbaff_frame_flag.It is derived from MbaffFrameFlag 2135 //! = (mb_adaptive_frame_field_flag && ! field_pic_flag ). 2136 //! mb_adaptive_frame_field_flag is a syntax element in the current active 2137 //! SPS and field_pic_flag is a syntax element in the current Slice Header. 2138 //! They both are present only if frame_mbs_only_flag is 0. Although 2139 //! mbaff_frame_flag is a Slice Header parameter, its value is expected to 2140 //! be the same for all the slices of a picture.It must be consistent with 2141 //! the mb_adaptive_frame_field_flag, the field_pic_flag and the 2142 //! frame_mbs_only_flag settings.This bit is valid only when the 2143 //! img_structure[1:0] indicates the current picture is a frame. 2144 enum MBAFFFLAMEFLAG 2145 { 2146 MBAFFFLAMEFLAG_FALSE = 0, //!< not in MBAFF mode 2147 MBAFFFLAMEFLAG_TRUE = 1, //!< in MBAFF mode 2148 }; 2149 2150 //! \brief FRAMEMBONLYFLAG 2151 //! \details 2152 //! Frame MB only flag, frame_mbs_only_flagIt is set to the value of the 2153 //! syntax element in the current active SPS. 2154 enum FRAMEMBONLYFLAG 2155 { 2156 FRAMEMBONLYFLAG_FALSE = 0, //!< not true ; effectively enables the possibility of MBAFF mode. 2157 FRAMEMBONLYFLAG_TRUE = 1, //!< true, only frame MBs can occur in this sequence, hence disallows the MBAFF mode and field picture. 2158 }; 2159 2160 //! \brief TRANSFORM8X8FLAG 2161 //! \details 2162 //! 8x8 IDCT Transform Mode Flag, trans8x8_mode_flagSpecifies 8x8 IDCT 2163 //! transform may be used in this pictureIt is set to the value of the 2164 //! syntax element in the current active PPS. 2165 enum TRANSFORM8X8FLAG 2166 { 2167 TRANSFORM8X8FLAG_4X_4 = 0, //!< no 8x8 IDCT Transform, only 4x4 IDCT transform blocks are present 2168 TRANSFORM8X8FLAG_8X8 = 1, //!< 8x8 Transform is allowed 2169 }; 2170 2171 //! \brief DIRECT8X8INFFLAG 2172 //! \details 2173 //! Direct 8x8 Inference Flag, direct_8x8_inference_flagIt is set to the 2174 //! value of the syntax element in the current active SPS.It specifies the 2175 //! derivation process for luma motion vectors in the Direct MV coding modes 2176 //! (B_Skip, B_Direct_16x16 and B_Direct_8x8). When frame_mbs_only_flag is 2177 //! equal to 0, direct_8x8_inference_flag shall be equal to 1.It must be 2178 //! consistent with the frame_mbs_only_flag and transform_8x8_mode_flag 2179 //! settings. 2180 enum DIRECT8X8INFFLAG 2181 { 2182 DIRECT8X8INFFLAG_SUBBLOCK = 0, //!< allows subpartitioning to go below 8x8 block size (i.e. 4x4, 8x4 or 4x8) 2183 DIRECT8X8INFFLAG_BLOCK = 1, //!< allows processing only at 8x8 block size. MB Info is stored for 8x8 block size. 2184 }; 2185 2186 //! \brief CONSTRAINEDIPREDFLAG 2187 //! \details 2188 //! Constrained Intra Prediction Flag, constrained_ipred_flagIt is set to 2189 //! the value of the syntax element in the current active PPS. 2190 enum CONSTRAINEDIPREDFLAG 2191 { 2192 CONSTRAINEDIPREDFLAG_INTRAANDINTER = 0, //!< allows both intra and inter neighboring MB to be used in the intra-prediction encoding of the current MB. 2193 CONSTRAINEDIPREDFLAG_INTRAONLY = 1, //!< allows only to use neighboring Intra MBs in the intra-prediction encoding of the current MB. If the neighbor is an inter MB, it is considered as not available. 2194 }; 2195 2196 //! \brief IMGDISPOSABLEFLAG 2197 //! \details 2198 //! Current Img Disposable Flag or Non-Reference Picture Flag 2199 enum IMGDISPOSABLEFLAG 2200 { 2201 IMGDISPOSABLEFLAG_REFERENCE = 0, //!< the current decoding picture may be used as a reference picture for others 2202 IMGDISPOSABLEFLAG_DISPOSABLE = 1, //!< the current decoding picture is not used as a reference picture (e.g. a B-picture cannot be a reference picture for any subsequent decoding) 2203 }; 2204 2205 //! \brief ENTROPYCODINGFLAG 2206 //! \details 2207 //! Entropy Coding Flag, entropy_coding_flag 2208 enum ENTROPYCODINGFLAG 2209 { 2210 ENTROPYCODINGFLAG_CAVLCBIT_SERIALENCODINGMODE = 0, //!< Desc 2211 ENTROPYCODINGFLAG_CABACBIT_SERIALENCODINGMODE = 1, //!< Desc 2212 }; 2213 2214 //! \brief MBMVFORMATFLAG 2215 //! \details 2216 //! Use MB level MvFormat flag (Encoder Only)(This bit must be set to zero 2217 //! in IVB:GT2:A0) 2218 enum MBMVFORMATFLAG 2219 { 2220 MBMVFORMATFLAG_IGNORE = 0, //!< HW PAK ignore MvFormat in the MB data. When bit 12 == 0, all MBs use packed MV formatWhen bit 12 == 1, each MB data must use unpacked MV format, 8MV when there is no minor MV involved, and 32MV if there are some minor MVs. 2221 MBMVFORMATFLAG_FOLLOW = 1, //!< HW PAK will follow MvFormat value set within each MB data. 2222 }; 2223 2224 //! \brief CHROMAFORMATIDC 2225 //! \details 2226 //! Chroma Format IDC, ChromaFormatIdc[1:0]It specifies the sampling of 2227 //! chroma component (Cb, Cr) in the current picture as follows : 2228 enum CHROMAFORMATIDC 2229 { 2230 CHROMAFORMATIDC_MONOCHROMEPICTURE = 0, //!< Desc 2231 CHROMAFORMATIDC_420PICTURE = 1, //!< Desc 2232 CHROMAFORMATIDC_422PICTURENOTSUPPORTED = 2, //!< No additional details 2233 CHROMAFORMATIDC_4_4_4PICTURENOTSUPPORTED = 3, //!< No additional details 2234 }; 2235 2236 //! \brief MVUNPACKEDFLAG 2237 //! \details 2238 //! MVUnPackedEnable (Encoder Only)This field is reserved in Decode mode. 2239 enum MVUNPACKEDFLAG 2240 { 2241 MVUNPACKEDFLAG_PACKED = 0, //!< use packed MV format 2242 MVUNPACKEDFLAG_UNPACKED = 1, //!< use unpacked 8MV/32MV format only 2243 }; 2244 2245 //! \brief LOADSLICEPOINTERFLAG 2246 //! \details 2247 //! LoadBitStreamPointerPerSlice (Encoder-only)To support multiple slice 2248 //! picture and additional header/data insertion before and after an encoded 2249 //! slice.When this field is set to 0, bitstream pointer is only loaded once 2250 //! for the first slice of a frame. For subsequent slices in the frame, 2251 //! bitstream data are stitched together to form a single output data 2252 //! stream.When this field is set to 1, bitstream pointer is loaded for each 2253 //! slice of a frame. Basically bitstream data for different slices of a 2254 //! frame will be written to different memory locations. 2255 enum LOADSLICEPOINTERFLAG 2256 { 2257 LOADSLICEPOINTERFLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame 2258 LOADSLICEPOINTERFLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 2259 }; 2260 2261 //! \brief MBSTATENABLED 2262 //! \details 2263 //! <p>Enable reading in MB status buffer (a.k.a. encoding stream-out 2264 //! buffer) Note: For multi-pass encoder, all passes except the first one 2265 //! need to set this value to 1. By setting the first pass to 0, it does 2266 //! save some memory bandwidth.</p> 2267 //! <p><span style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 2268 //! line-height: normal;">In VDenc mode this must be set to zero as no MB 2269 //! level rate control is used. </span></p> 2270 enum MBSTATENABLED 2271 { 2272 MBSTATENABLED_DISABLE = 0, //!< Disable Reading of Macroblock Status Buffer 2273 MBSTATENABLED_ENABLE = 1, //!< Enable Reading of Macroblock Status Buffer 2274 }; 2275 2276 //! \brief MINFRAMEWSIZE 2277 //! \details 2278 //! <p><b>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</b> 2279 //! Mininum Frame Size is specified to compensate for intel Rate 2280 //! Control Currently zero fill (no need to perform emulation byte 2281 //! insertion) is done 2282 //! only to the end of the CABAC_ZERO_WORD insertion (if any) at the 2283 //! last slice of a 2284 //! picture. Intel encoder parameter. The caller 2285 //! should always make 2286 //! sure that the value, represented by Mininum Frame Size, is always 2287 //! less than maximum 2288 //! frame size <b>FrameBitRateMax (DWORD 10 bits</b> 29:16).This field 2289 //! is reserved in 2290 //! Decode mode.</p> 2291 //! <p>The programmable range 0…2^18-1</p> 2292 //! <p>When MinFrameWSizeUnits is 00.</p> 2293 //! <p>Programmable range is 0…2^20-1 when MinFrameWSizeUnits is 2294 //! 01.</p> 2295 //! <p>Programmable range is 0…2^26-1 when MinFrameWSizeUnits is 2296 //! 10.</p> 2297 //! <p>Programmable range is 0…2^32-1 when MinFrameWSizeUnits is 2298 //! 11.</p> 2299 enum MINFRAMEWSIZE 2300 { 2301 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 2302 }; 2303 2304 //! \brief INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2305 //! \details 2306 //! This is a mask bit controlling if the condition of any intra MB in the 2307 //! frame exceeds IntraMBMaxSize. 2308 enum INTRAMBMAXBITFLAG__INTRAMBMAXSIZEREPORTMASK 2309 { 2310 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2311 INTRAMBMAXBITFLAG_INTRAMBMAXSIZEREPORTMASK_ENABLE = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 2312 }; 2313 2314 //! \brief INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2315 //! \details 2316 //! This is a mask bit controlling if the condition of any inter MB in the 2317 //! frame exceeds InterMBMaxSize. 2318 enum INTERMBMAXBITFLAG__INTERMBMAXSIZEREPORTMASK 2319 { 2320 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2321 INTERMBMAXBITFLAG_INTERMBMAXSIZEREPORTMASK_ENABLE = 1, //!< Set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 2322 }; 2323 2324 //! \brief FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2325 //! \details 2326 //! This is a mask bit controlling if the condition of frame level bit count 2327 //! exceeds FrameBitRateMax. 2328 enum FRAMESZOVERFLAG__FRAMEBITRATEMAXREPORTMASK 2329 { 2330 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2331 FRAMESZOVERFLAG_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 2332 }; 2333 2334 //! \brief FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2335 //! \details 2336 //! This is a mask bit controlling if the condition of frame level bit count 2337 //! is less than FrameBitRateMin 2338 enum FRAMESZUNDERFLAG__FRAMEBITRATEMINREPORTMASK 2339 { 2340 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 2341 FRAMESZUNDERFLAG_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 2342 }; 2343 2344 //! \brief INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2345 //! \details 2346 //! This field is to Force <b>IPCM</b> for Intra or Inter Macroblock size 2347 //! conformance mask. 2348 enum INTRAINTERMBIPCMFLAG__FORCEIPCMCONTROLMASK 2349 { 2350 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_DISABLE = 0, //!< Do not change intra or Inter macroblocks even 2351 INTRAINTERMBIPCMFLAG_FORCEIPCMCONTROLMASK_ENABLE = 1, //!< Change intra or Inter macroblocks MB_type to IPCM 2352 }; 2353 2354 //! \brief MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2355 //! \details 2356 //! <p>MB Rate Control conformance mask</p> 2357 //! <p>In VDenc mode, this field must be zero as frame level rate control is 2358 //! used.</p> 2359 enum MBRATECTRLFLAG__MB_LEVEL_RATE_CONTROL_ENABLING_FLAG 2360 { 2361 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_DISABLE = 0, //!< Apply accumulative delta QP for consecutive passes on top of the macroblock QP values in inline data 2362 MBRATECTRLFLAG_MB_LEVEL_RATE_CONTROL_ENABLING_FLAG_ENABLE = 1, //!< Apply RC QP delta to suggested QP values in Macroblock Status Buffer except the first pass. 2363 }; 2364 2365 //! \brief MINFRAMEWSIZEUNITS 2366 //! \details 2367 //! This field is the Minimum Frame Size Units 2368 enum MINFRAMEWSIZEUNITS 2369 { 2370 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 2371 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 2372 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 2373 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 2374 }; 2375 2376 //! \brief NONFIRSTPASSFLAG 2377 //! \details 2378 //! This signals the current pass is not the first pass. It will imply 2379 //! designate HW behavior: e.g 2380 enum NONFIRSTPASSFLAG 2381 { 2382 NONFIRSTPASSFLAG_DISABLE = 0, //!< Always use the MbQpY from initial PAK inline object for all passes of PAK 2383 NONFIRSTPASSFLAG_ENABLE = 1, //!< Use MbQpY from stream-out buffer if MbRateCtrlFlag is set to 1 2384 }; 2385 2386 //! \brief TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2387 //! \details 2388 //! This signal is used to disable chroma TQ. To enable TQ for both luma and 2389 //! chroma, TQEnb=1, TQChromaDisable=0. To enable TQ only for luma, TQEnb=1, 2390 //! TQChromaDisable=1. 2391 enum TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE 2392 { 2393 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_UNNAMED0 = 0, //!< Enable Trellis Quantization chroma 2394 TRELLIS_QUANTIZATION_CHROMA_DISABLE_TQCHROMADISABLE_DEFAULT = 1, //!< Disable Trellis Quantization chroma 2395 }; 2396 2397 //! \brief TRELLIS_QUANTIZATION_ROUNDING_TQR 2398 //! \details 2399 //! This rounding scheme is only applied to the quantized coefficients 2400 //! ranging from 0 to 1 when TQEnb is set to 1 in AVC CABAC mode. One of the 2401 //! following values is added to quantized coefficients before truncating 2402 //! fractional part. 2403 enum TRELLIS_QUANTIZATION_ROUNDING_TQR 2404 { 2405 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED0 = 0, //!< Add 1/8 2406 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED1 = 1, //!< Add 2/8 2407 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED2 = 2, //!< Add 3/8 2408 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED3 = 3, //!< Add 4/8 (rounding 0.5) 2409 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED_4 = 4, //!< Add 5/8 2410 TRELLIS_QUANTIZATION_ROUNDING_TQR_UNNAMED5 = 5, //!< Add 6/8 2411 TRELLIS_QUANTIZATION_ROUNDING_TQR_DEFAULT = 6, //!< Add 7/8 (Default rounding 0.875) 2412 }; 2413 2414 //! \brief TRELLIS_QUANTIZATION_ENABLED_TQENB 2415 //! \details 2416 //! The TQ improves output video quality of AVC CABAC encoder by selecting 2417 //! quantized values for each non-zero coefficient so as to minimize the 2418 //! total R-D cost.This flag is only valid AVC CABAC mode. Otherwise, this 2419 //! flag should be disabled. 2420 enum TRELLIS_QUANTIZATION_ENABLED_TQENB 2421 { 2422 TRELLIS_QUANTIZATION_ENABLED_TQENB_DISABLE = 0, //!< Use Normal 2423 TRELLIS_QUANTIZATION_ENABLED_TQENB_ENABLE = 1, //!< Use Trellis quantization 2424 }; 2425 2426 enum VSL_TOP_MB_TRANS8X8FLAG 2427 { 2428 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 2429 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 2430 }; 2431 2432 //! \brief BSP_ENCODER_ECO_ENABLE 2433 //! \details 2434 //! <p>This is to Enable AVC Encoder BSP Bit Outstanding ECO fix.</p> 2435 //! <p>This bit must be same as bit9 of Dword2 of MFX_PIPE_MODE_SELECT</p> 2436 enum BSP_ENCODER_ECO_ENABLE 2437 { 2438 BSP_ENCODER_ECO_ENABLE_DISABLE = 0, //!< No additional details 2439 BSP_ENCODER_ECO_ENABLE_ENABLE = 1, //!< No additional details 2440 }; 2441 2442 //! \brief FRAMEBITRATEMINUNITMODE 2443 //! \details 2444 //! This field is the Frame Bitrate Minimum Limit Units. 2445 enum FRAMEBITRATEMINUNITMODE 2446 { 2447 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2448 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2449 }; 2450 2451 //! \brief FRAMEBITRATEMINUNIT 2452 //! \details 2453 //! This field is the Frame Bitrate Minimum Limit Units. 2454 enum FRAMEBITRATEMINUNIT 2455 { 2456 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 2457 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2458 }; 2459 2460 //! \brief FRAMEBITRATEMAXUNITMODE 2461 //! \details 2462 //! This field is the Frame Bitrate Maximum Limit Units. 2463 enum FRAMEBITRATEMAXUNITMODE 2464 { 2465 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 2466 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 2467 }; 2468 2469 //! \brief FRAMEBITRATEMAXUNIT_ 2470 //! \details 2471 //! This field is the Frame Bitrate Maximum Limit Units. 2472 enum FRAMEBITRATEMAXUNIT_ 2473 { 2474 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 2475 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 2476 }; 2477 2478 //! \brief FRAMEBITRATEMAXDELTA 2479 //! \details 2480 //! This field is used to select the slice delta QP when FrameBitRateMax Is 2481 //! exceeded. It shares the same FrameBitrateMaxUnit. When 2482 //! FrameBitrateMaxUnitMode is 0(compatibility mode) bits 16:27 should be 2483 //! used, bits 28, 29 and 30 should be 0. 2484 enum FRAMEBITRATEMAXDELTA 2485 { 2486 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 2487 }; 2488 2489 enum VAD_ERROR_LOGIC 2490 { 2491 VAD_ERROR_LOGIC_ENABLE = 0, //!< Error reporting ON in case of premature Slice done 2492 VAD_ERROR_LOGIC_DISABLE = 1, //!< CABAC Engine will auto decode the bitstream in case of premature slice done. 2493 }; 2494 2495 //! \brief INTER_VIEW_ORDER_DISABLE 2496 //! \details 2497 //! It indicates how to append inter-view picture into initial sorted 2498 //! reference list. (due to ambiguity in the MVC Spec) 2499 enum INTER_VIEW_ORDER_DISABLE 2500 { 2501 INTER_VIEW_ORDER_DISABLE_DEFAULT = 0, //!< View Order Ascending 2502 INTER_VIEW_ORDER_DISABLE_DISABLE = 1, //!< View ID Ascending 2503 }; 2504 2505 //! \name Initializations 2506 2507 //! \brief Explicit member initialization function 2508 MFX_AVC_IMG_STATE_CMD(); 2509 2510 static const size_t dwSize = 21; 2511 static const size_t byteSize = 84; 2512 }; 2513 2514 //! 2515 //! \brief MFX_AVC_REF_IDX_STATE 2516 //! \details 2517 //! This is a slice level command and can be issued multiple times within a 2518 //! picture that is comprised of multiple slices. The same command is used 2519 //! for AVC encoder (PAK mode) and decoder (VLD mode); it is not need in 2520 //! decoder IT mode. The inline data of this command is interpreted 2521 //! differently for encoder as for decoder. For decoder, it is interpreted 2522 //! as RefIdx List L0/L1 as in AVC spec., and it matches with the AVC 2523 //! API data structure for decoder in VLD mode : RefPicList[2][32] (L0:L1, 2524 //! 0:31 RefPic). But for encoder, it is interpreted as a Reference Index 2525 //! Mapping Table for L0 and L1 reference pictures. For packing the bits at 2526 //! the output of PAK, the syntax elements must follow the definition of 2527 //! RefIdxL0/L1 list according to the AVC spec. However, the decoder 2528 //! pipeline was designed to use a variation of that standard definition, as 2529 //! such a conversion (mapping) is needed to support the hardware design. 2530 //! The Reference lists are needed in processing both P and B slice in AVC 2531 //! codec. For P-MB, only L0 list is used; for B-MB both L0 and L1 lists are 2532 //! needed. For a B-MB that is coded in L1-only Prediction, only L1 list is 2533 //! used. 2534 //! 2535 //! An application will create the RefPicList L0 and L1 2536 //! and pass onto the driver. The content of each entry of RefPicList 2537 //! L0/L1[ ] is a 7-bit picture index. This picture index is the same as 2538 //! that of RefFrameList[ ] content. This picture index, however, is not 2539 //! defined the same as the frame store ID (0 to 16, 5-bits) we have 2540 //! implemented in H/W. Hence, driver is required to manage a table to 2541 //! convert between picture index and intel frame store ID. As such, 2542 //! the final RefPicList L0/L1[ ] that the driver passes onto the H/W is not 2543 //! the same as that defined. 2544 //! 2545 struct MFX_AVC_REF_IDX_STATE_CMD 2546 { 2547 union 2548 { 2549 //!< DWORD 0 2550 struct 2551 { 2552 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2553 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2554 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2555 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2556 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2557 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2558 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2559 }; 2560 uint32_t Value; 2561 } DW0; 2562 union 2563 { 2564 //!< DWORD 1 2565 struct 2566 { 2567 uint32_t RefpiclistSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLIST_SELECT 2568 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2569 }; 2570 uint32_t Value; 2571 } DW1; 2572 2573 uint32_t ReferenceListEntry[8]; //!< Reference List Entry 2574 2575 //! \name Local enumerations 2576 2577 enum SUBOPCODEB 2578 { 2579 SUBOPCODEB_MFXAVCREFIDXSTATE = 4, //!< No additional details 2580 }; 2581 2582 enum SUBOPCODEA 2583 { 2584 SUBOPCODEA_MFXAVCREFIDXSTATE = 0, //!< No additional details 2585 }; 2586 2587 enum COMMAND_OPCODE 2588 { 2589 COMMAND_OPCODE_AVC = 1, //!< No additional details 2590 }; 2591 2592 enum PIPELINE 2593 { 2594 PIPELINE_MFXAVCREFIDXSTATE = 2, //!< No additional details 2595 }; 2596 2597 enum COMMAND_TYPE 2598 { 2599 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2600 }; 2601 2602 //! \brief REFPICLIST_SELECT 2603 //! \details 2604 //! <p>Num_ref_idx_l1_active is resulted from the specifications in both PPS 2605 //! and Slice Header for the current slice. However, since the full 2606 //! reference list L0 and/or L1 are always sent, only present flags are 2607 //! specified instead.</p> 2608 //! <p>This parameter is specified for Intel interface only.</p> 2609 enum REFPICLIST_SELECT 2610 { 2611 REFPICLIST_SELECT_REFPICLIST0 = 0, //!< The list that followed represents RefList L0 (Decoder VLD mode) or Ref Idx Mapping Table L0 (Encoder PAK mode) 2612 REFPICLIST_SELECT_REFPICLIST1 = 1, //!< The list that followed represents RefList L1 (Decoder VLD mode) or Ref Idx Mapping Table L1 (Encoder PAK mode) 2613 }; 2614 2615 //! \name Initializations 2616 2617 //! \brief Explicit member initialization function 2618 MFX_AVC_REF_IDX_STATE_CMD(); 2619 2620 static const size_t dwSize = 10; 2621 static const size_t byteSize = 40; 2622 }; 2623 2624 //! 2625 //! \brief MFX_AVC_WEIGHTOFFSET_STATE 2626 //! \details 2627 //! This is a slice level command and can be issued multiple times within a 2628 //! picture that is comprised of multiple slices. The same command is used 2629 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). However, 2630 //! since for AVC decoder VLD and IT modes, and AVC encoder mode, the 2631 //! implicit weights are computed in hardware, this command is not issued. 2632 //! For encoder, regardless of the type of weight calculation is active for 2633 //! the current slice (default, implicit or explicit), they are all sent to 2634 //! the PAK as if they were all in explicit mode. However, for implicit 2635 //! weight and offset, each entry contains only a 16-bit weight and no 2636 //! offset (offset = 0 always in implicit mode and can be hard-coded inside 2637 //! the hardware).The weights (and offsets) are needed in processing both P 2638 //! and B slice in AVC codec. For P-MB, at most only L0 list is used; for 2639 //! B-MB both L0 and L1 lists may be needed. For a B-MB that is coded in 2640 //! L1-only Prediction, only L1 list is sent.The content of this command 2641 //! matches with the AVC API data structure for explicit prediction 2642 //! mode only : Weights[2][32][3][2] (L0:L1, 0:31 RefPic, Y:Cb:Cr, W:0) 2643 //! 2644 struct MFX_AVC_WEIGHTOFFSET_STATE_CMD 2645 { 2646 union 2647 { 2648 //!< DWORD 0 2649 struct 2650 { 2651 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2652 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2653 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 2654 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 2655 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 2656 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2657 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2658 }; 2659 uint32_t Value; 2660 } DW0; 2661 union 2662 { 2663 //!< DWORD 1 2664 struct 2665 { 2666 uint32_t WeightAndOffsetSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< WEIGHT_AND_OFFSET_SELECT 2667 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2668 }; 2669 uint32_t Value; 2670 } DW1; 2671 2672 uint32_t Weightoffset[96]; //!< WeightOffset 2673 2674 //! \name Local enumerations 2675 2676 enum SUBOPCODE_B 2677 { 2678 SUBOPCODE_B_UNNAMED5 = 5, //!< No additional details 2679 }; 2680 2681 enum SUBOPCODE_A 2682 { 2683 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 2684 }; 2685 2686 enum MEDIA_COMMAND_OPCODE 2687 { 2688 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 2689 }; 2690 2691 enum PIPELINE 2692 { 2693 PIPELINE_MFXAVCWEIGHTOFFSETSTATE = 2, //!< No additional details 2694 }; 2695 2696 enum COMMAND_TYPE 2697 { 2698 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2699 }; 2700 2701 //! \brief WEIGHT_AND_OFFSET_SELECT 2702 //! \details 2703 //! It must be set in consistent with the WeightedPredFlag and 2704 //! WeightedBiPredIdc in the Img_State command. 2705 //! This parameter is specified for Intel interface only. 2706 //! For implicit even though only one entry may be used, still loading 2707 //! the whole 32-entry table. 2708 enum WEIGHT_AND_OFFSET_SELECT 2709 { 2710 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL0TABLE = 0, //!< The list that followed is associated with the weight and offset for RefPicList L0 2711 WEIGHT_AND_OFFSET_SELECT_WEIGHTANDOFFSETL1TABLE = 1, //!< The list that followed is associated with the weight and offset for RefPicList L1 2712 }; 2713 2714 //! \name Initializations 2715 2716 //! \brief Explicit member initialization function 2717 MFX_AVC_WEIGHTOFFSET_STATE_CMD(); 2718 2719 static const size_t dwSize = 98; 2720 static const size_t byteSize = 392; 2721 }; 2722 2723 //! 2724 //! \brief MFX_AVC_SLICE_STATE 2725 //! \details 2726 //! This is a slice level command and can be issued multiple times within a 2727 //! picture that is comprised of multiple slices. The same command is used 2728 //! for AVC encoder (PAK mode) and decoder (VLD and IT modes). 2729 //! 2730 //! In VDEnc mode, this command is programmed for every super-slice. However 2731 //! not all parameters are allowed to change across super-slices. 2732 //! 2733 //! MFX_AVC_SLICE_STATE command is not issued for AVC Short Format 2734 //! Bitstream decode, instead MFD_AVC_SLICEADDR command is executed to 2735 //! retrieve the next slice MB Start Address X and Y by H/W itself. 2736 //! 2737 struct MFX_AVC_SLICE_STATE_CMD 2738 { 2739 union 2740 { 2741 //!< DWORD 0 2742 struct 2743 { 2744 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2745 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2746 uint32_t CommandSubopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< COMMAND_SUBOPCODEB 2747 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 2748 uint32_t CommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMAND_OPCODE 2749 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2750 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2751 }; 2752 uint32_t Value; 2753 } DW0; 2754 union 2755 { 2756 //!< DWORD 1 2757 struct 2758 { 2759 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 3) ; //!< SLICE_TYPE 2760 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 2761 }; 2762 uint32_t Value; 2763 } DW1; 2764 union 2765 { 2766 //!< DWORD 2 2767 struct 2768 { 2769 uint32_t Log2WeightDenomLuma : __CODEGEN_BITFIELD( 0, 2) ; //!< Log 2 Weight Denom Luma 2770 uint32_t Reserved67 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2771 uint32_t Log2WeightDenomChroma : __CODEGEN_BITFIELD( 8, 10) ; //!< Log 2 Weight Denom Chroma 2772 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 2773 uint32_t NumberOfReferencePicturesInInterPredictionList0 : __CODEGEN_BITFIELD(16, 21) ; //!< Number of Reference Pictures in Inter-prediction List 0 2774 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2775 uint32_t NumberOfReferencePicturesInInterPredictionList1 : __CODEGEN_BITFIELD(24, 29) ; //!< Number of Reference Pictures in Inter-prediction List 1 2776 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2777 }; 2778 uint32_t Value; 2779 } DW2; 2780 union 2781 { 2782 //!< DWORD 3 2783 struct 2784 { 2785 uint32_t SliceAlphaC0OffsetDiv2 : __CODEGEN_BITFIELD( 0, 3) ; //!< Slice Alpha C0 Offset Div2 2786 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 2787 uint32_t SliceBetaOffsetDiv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< Slice Beta Offset Div2 2788 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2789 uint32_t SliceQuantizationParameter : __CODEGEN_BITFIELD(16, 21) ; //!< Slice Quantization Parameter 2790 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2791 uint32_t CabacInitIdc10 : __CODEGEN_BITFIELD(24, 25) ; //!< Cabac Init Idc[1:0] 2792 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 2793 uint32_t DisableDeblockingFilterIndicator : __CODEGEN_BITFIELD(27, 28) ; //!< DISABLE_DEBLOCKING_FILTER_INDICATOR 2794 uint32_t DirectPredictionType : __CODEGEN_BITFIELD(29, 29) ; //!< DIRECT_PREDICTION_TYPE 2795 uint32_t WeightedPredictionIndicator : __CODEGEN_BITFIELD(30, 31) ; //!< Weighted Prediction Indicator 2796 }; 2797 uint32_t Value; 2798 } DW3; 2799 union 2800 { 2801 //!< DWORD 4 2802 struct 2803 { 2804 uint32_t SliceStartMbNum : __CODEGEN_BITFIELD( 0, 14) ; //!< Slice Start Mb Num 2805 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 2806 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Horizontal Position 2807 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Vertical Position 2808 }; 2809 uint32_t Value; 2810 } DW4; 2811 union 2812 { 2813 //!< DWORD 5 2814 struct 2815 { 2816 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Horizontal Position 2817 uint32_t Reserved168 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2818 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD(16, 24) ; //!< Next Slice Vertical Position 2819 uint32_t Reserved184 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 2820 }; 2821 uint32_t Value; 2822 } DW5; 2823 union 2824 { 2825 //!< DWORD 6 2826 struct 2827 { 2828 uint32_t StreamId10 : __CODEGEN_BITFIELD( 0, 1) ; //!< Stream ID [1:0] 2829 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 2830 uint32_t SliceId30 : __CODEGEN_BITFIELD( 4, 7) ; //!< Slice ID [3:0] 2831 uint32_t Reserved200 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 2832 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD(12, 12) ; //!< CABACZEROWORDINSERTIONENABLE 2833 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD(13, 13) ; //!< EMULATIONBYTESLICEINSERTENABLE 2834 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 2835 uint32_t TailInsertionPresentInBitstream : __CODEGEN_BITFIELD(15, 15) ; //!< TAIL_INSERTION_PRESENT_IN_BITSTREAM 2836 uint32_t SlicedataInsertionPresentInBitstream : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 2837 uint32_t HeaderInsertionPresentInBitstream : __CODEGEN_BITFIELD(17, 17) ; //!< HEADER_INSERTION_PRESENT_IN_BITSTREAM 2838 uint32_t Reserved210 : __CODEGEN_BITFIELD(18, 18) ; //!< Reserved 2839 uint32_t IsLastSlice : __CODEGEN_BITFIELD(19, 19) ; //!< IS_LAST_SLICE 2840 uint32_t MbTypeSkipConversionDisable : __CODEGEN_BITFIELD(20, 20) ; //!< MB_TYPE_SKIP_CONVERSION_DISABLE 2841 uint32_t MbTypeDirectConversionDisable : __CODEGEN_BITFIELD(21, 21) ; //!< MB_TYPE_DIRECT_CONVERSION_DISABLE 2842 uint32_t RcPanicType : __CODEGEN_BITFIELD(22, 22) ; //!< RC_PANIC_TYPE 2843 uint32_t RcPanicEnable : __CODEGEN_BITFIELD(23, 23) ; //!< RC_PANIC_ENABLE 2844 uint32_t RcStableTolerance : __CODEGEN_BITFIELD(24, 27) ; //!< RC Stable Tolerance 2845 uint32_t RcTriggleMode : __CODEGEN_BITFIELD(28, 29) ; //!< RC_TRIGGLE_MODE 2846 uint32_t Resetratecontrolcounter : __CODEGEN_BITFIELD(30, 30) ; //!< RESETRATECONTROLCOUNTER 2847 uint32_t RateControlCounterEnable : __CODEGEN_BITFIELD(31, 31) ; //!< RATE_CONTROL_COUNTER_ENABLE 2848 }; 2849 uint32_t Value; 2850 } DW6; 2851 union 2852 { 2853 //!< DWORD 7 2854 struct 2855 { 2856 uint32_t IndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect PAK-BSE Data Start Address (Write) 2857 uint32_t Reserved253 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2858 }; 2859 uint32_t Value; 2860 } DW7; 2861 union 2862 { 2863 //!< DWORD 8 2864 struct 2865 { 2866 uint32_t GrowParamGrowInit : __CODEGEN_BITFIELD( 0, 3) ; //!< Grow Param - Grow Init 2867 uint32_t GrowParamGrowResistance : __CODEGEN_BITFIELD( 4, 7) ; //!< Grow Param - Grow Resistance 2868 uint32_t ShrinkParamShrinkInit : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrink Param - Shrink Init 2869 uint32_t ShrinkParamShrinkResistance : __CODEGEN_BITFIELD(12, 15) ; //!< Shrink Param - Shrink Resistance 2870 uint32_t MagnitudeOfQpMaxPositiveModifier : __CODEGEN_BITFIELD(16, 23) ; //!< Magnitude of QP Max Positive Modifier 2871 uint32_t MagnitudeOfQpMaxNegativeModifier : __CODEGEN_BITFIELD(24, 31) ; //!< Magnitude of QP Max Negative Modifier 2872 }; 2873 uint32_t Value; 2874 } DW8; 2875 union 2876 { 2877 //!< DWORD 9 2878 struct 2879 { 2880 uint32_t Correct1 : __CODEGEN_BITFIELD( 0, 3) ; //!< Correct 1 2881 uint32_t Correct2 : __CODEGEN_BITFIELD( 4, 7) ; //!< Correct 2 2882 uint32_t Correct3 : __CODEGEN_BITFIELD( 8, 11) ; //!< Correct 3 2883 uint32_t Correct4 : __CODEGEN_BITFIELD(12, 15) ; //!< Correct 4 2884 uint32_t Correct5 : __CODEGEN_BITFIELD(16, 19) ; //!< Correct 5 2885 uint32_t Correct6 : __CODEGEN_BITFIELD(20, 23) ; //!< Correct 6 2886 uint32_t Roundintra : __CODEGEN_BITFIELD(24, 26) ; //!< ROUNDINTRA 2887 uint32_t Roundintraenable : __CODEGEN_BITFIELD(27, 27) ; //!< RoundIntraEnable 2888 uint32_t Roundinter : __CODEGEN_BITFIELD(28, 30) ; //!< ROUNDINTER 2889 uint32_t Roundinterenable : __CODEGEN_BITFIELD(31, 31) ; //!< RoundInterEnable 2890 }; 2891 uint32_t Value; 2892 } DW9; 2893 union 2894 { 2895 //!< DWORD 10 2896 struct 2897 { 2898 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 2899 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 2900 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 2901 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 2902 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 2903 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 2904 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 2905 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 2906 }; 2907 uint32_t Value; 2908 } DW10; 2909 2910 //! \name Local enumerations 2911 2912 enum COMMAND_SUBOPCODEB 2913 { 2914 COMMAND_SUBOPCODEB_MFXAVCSLICESTATE = 3, //!< No additional details 2915 }; 2916 2917 enum SUBOPCODEA 2918 { 2919 SUBOPCODEA_MFXAVCSLICESTATE = 0, //!< No additional details 2920 }; 2921 2922 enum COMMAND_OPCODE 2923 { 2924 COMMAND_OPCODE_AVC = 1, //!< No additional details 2925 }; 2926 2927 enum PIPELINE 2928 { 2929 PIPELINE_MFXAVCSLICESTATE = 2, //!< No additional details 2930 }; 2931 2932 enum COMMAND_TYPE 2933 { 2934 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2935 }; 2936 2937 //! \brief SLICE_TYPE 2938 //! \details 2939 //! It is set to the value of the syntax element read from the Slice Header. 2940 enum SLICE_TYPE 2941 { 2942 SLICE_TYPE_PSLICE = 0, //!< No additional details 2943 SLICE_TYPE_BSLICE = 1, //!< No additional details 2944 SLICE_TYPE_ISLICE = 2, //!< No additional details 2945 }; 2946 2947 enum DISABLE_DEBLOCKING_FILTER_INDICATOR 2948 { 2949 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED0 = 0, //!< FilterInternalEdgesFlag is set equal to 1 2950 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED1 = 1, //!< Disable all deblocking operation, no deblocking parameter syntax element is read; filterInternalEdgesFlag is set equal to 0 2951 DISABLE_DEBLOCKING_FILTER_INDICATOR_UNNAMED2 = 2, //!< Macroblocks in different slices are considered not available; filterInternalEdgesFlag is set equal to 1 2952 }; 2953 2954 //! \brief DIRECT_PREDICTION_TYPE 2955 //! \details 2956 //! Type of direct prediction used for B Slices. This field is valid only 2957 //! for Slice_Type = B Slice; otherwise, it must be set to 0. 2958 enum DIRECT_PREDICTION_TYPE 2959 { 2960 DIRECT_PREDICTION_TYPE_TEMPORAL = 0, //!< No additional details 2961 DIRECT_PREDICTION_TYPE_SPATIAL = 1, //!< No additional details 2962 }; 2963 2964 //! \brief CABACZEROWORDINSERTIONENABLE 2965 //! \details 2966 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2967 //! requirement. 2968 enum CABACZEROWORDINSERTIONENABLE 2969 { 2970 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion 2971 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP(effectively can be used as an indicator for last slice of a picture, if the assumption is only the last slice of a picture needs to insert CABAC_ZERO_WORDs. 2972 }; 2973 2974 //! \brief EMULATIONBYTESLICEINSERTENABLE 2975 //! \details 2976 //! To have PAK outputting SODB or EBSP to the output bitstream buffer 2977 enum EMULATIONBYTESLICEINSERTENABLE 2978 { 2979 EMULATIONBYTESLICEINSERTENABLE_UNNAMED0 = 0, //!< outputting RBSP 2980 EMULATIONBYTESLICEINSERTENABLE_UNNAMED1 = 1, //!< outputting EBSP 2981 }; 2982 2983 //! \brief TAIL_INSERTION_PRESENT_IN_BITSTREAM 2984 //! \details 2985 //! <p>This bit should only be set for the last super slice.</p> 2986 //! <p><span style="color: rgb(0, 0, 0); font-family: Arial, sans-serif; 2987 //! line-height: normal;">SKL Restriction: In VDENC mode, SW should insert 2988 //! 1000 </span><b style="color: rgb(0, 0, 0); font-family: Arial, 2989 //! sans-serif; line-height: normal;">VD_PIPELINE_FLUSH commands with 2990 //! VDENC_pipeline_Done set to 1 before inserting tail command. This is for 2991 //! delaying the tail insertion in HW. The HW recommendation is to insert 2992 //! tail only at the end of sequence to avoid performance loss since this 2993 //! restriction potentially cause performance degradation.</b></p> 2994 enum TAIL_INSERTION_PRESENT_IN_BITSTREAM 2995 { 2996 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits 2997 TAIL_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 2998 }; 2999 3000 //! \brief SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 3001 //! \details 3002 //! <p>This bit should be set for all super-slices.</p> 3003 enum SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM 3004 { 3005 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No Slice Data insertion into the output bitstream buffer 3006 SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Slice Data insertion into the output bitstream buffer is present. 3007 }; 3008 3009 //! \brief HEADER_INSERTION_PRESENT_IN_BITSTREAM 3010 //! \details 3011 //! Note: In VDEnc mode, the slice header PAK object maximum size is 25 DWs. 3012 enum HEADER_INSERTION_PRESENT_IN_BITSTREAM 3013 { 3014 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, in front of the current slice encoded bits. 3015 HEADER_INSERTION_PRESENT_IN_BITSTREAM_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 3016 }; 3017 3018 //! \brief IS_LAST_SLICE 3019 //! \details 3020 //! It is used by the zero filling in the Minimum Frame Size test. 3021 enum IS_LAST_SLICE 3022 { 3023 IS_LAST_SLICE_UNNAMED0 = 0, //!< Current slice is NOT the last slice of a picture 3024 IS_LAST_SLICE_UNNAMED1 = 1, //!< Current slice is the last slice of a picture 3025 }; 3026 3027 //! \brief MB_TYPE_SKIP_CONVERSION_DISABLE 3028 //! \details 3029 //! For all Macroblock type conversions in different slices, refer to 3030 //! Section "Macroblock Type Conversion Rules" in the same volume. 3031 enum MB_TYPE_SKIP_CONVERSION_DISABLE 3032 { 3033 MB_TYPE_SKIP_CONVERSION_DISABLE_ENABLESKIPTYPECONVERSION = 0, //!< No additional details 3034 MB_TYPE_SKIP_CONVERSION_DISABLE_DISABLESKIPTYPECONVERSION = 1, //!< No additional details 3035 }; 3036 3037 //! \brief MB_TYPE_DIRECT_CONVERSION_DISABLE 3038 //! \details 3039 //! For all Macroblock type conversions in different slices, refer to 3040 //! Section "Macroblock Type Conversion Rules" in the same volume. 3041 enum MB_TYPE_DIRECT_CONVERSION_DISABLE 3042 { 3043 MB_TYPE_DIRECT_CONVERSION_DISABLE_ENABLEDIRECTMODECONVERSION = 0, //!< No additional details 3044 MB_TYPE_DIRECT_CONVERSION_DISABLE_DISABLEDIRECTMODECONVERSION = 1, //!< No additional details 3045 }; 3046 3047 //! \brief RC_PANIC_TYPE 3048 //! \details 3049 //! This field selects between two RC Panic methods 3050 enum RC_PANIC_TYPE 3051 { 3052 RC_PANIC_TYPE_QPPANIC = 0, //!< No additional details 3053 RC_PANIC_TYPE_CBPPANIC = 1, //!< No additional details 3054 }; 3055 3056 //! \brief RC_PANIC_ENABLE 3057 //! \details 3058 //! If this field is set to 1, RC enters panic mode when sum_act > 3059 //! sum_max. RC Panic Type field controls what type of panic behavior is 3060 //! invoked. 3061 enum RC_PANIC_ENABLE 3062 { 3063 RC_PANIC_ENABLE_DISABLE = 0, //!< No additional details 3064 RC_PANIC_ENABLE_ENABLE = 1, //!< No additional details 3065 }; 3066 3067 enum RC_TRIGGLE_MODE 3068 { 3069 RC_TRIGGLE_MODE_ALWAYSRATECONTROL = 0, //!< Whereas RC becomes active if sum_act > sum_target or sum_act < sum_target 3070 RC_TRIGGLE_MODE_GENTLERATECONTROL = 1, //!< whereas RC becomes active if sum_act > upper_midpt or sum_act < lower_midpt 3071 RC_TRIGGLE_MODE_LOOSERATECONTROL = 2, //!< whereas RC becomes active if sum_act > sum_max or sum_act < sum_min 3072 }; 3073 3074 //! \brief RESETRATECONTROLCOUNTER 3075 //! \details 3076 //! To reset the bit allocation accumulation counter to 0 to restart the 3077 //! rate control. 3078 enum RESETRATECONTROLCOUNTER 3079 { 3080 RESETRATECONTROLCOUNTER_NOTRESET = 0, //!< No additional details 3081 RESETRATECONTROLCOUNTER_RESET = 1, //!< No additional details 3082 }; 3083 3084 //! \brief RATE_CONTROL_COUNTER_ENABLE 3085 //! \details 3086 //! To enable the accumulation of bit allocation for rate control 3087 //! This field enables hardware Rate Control logic. The rest of the RC 3088 //! control fields are only valid when this field is set to 1. Otherwise, 3089 //! hardware ignores these fields. 3090 enum RATE_CONTROL_COUNTER_ENABLE 3091 { 3092 RATE_CONTROL_COUNTER_ENABLE_DISABLE = 0, //!< No additional details 3093 RATE_CONTROL_COUNTER_ENABLE_ENABLE = 1, //!< No additional details 3094 }; 3095 3096 //! \brief ROUNDINTRA 3097 //! \details 3098 //! Rounding precision for Intra quantized coefficients 3099 enum ROUNDINTRA 3100 { 3101 ROUNDINTRA_116 = 0, //!< No additional details 3102 ROUNDINTRA_216 = 1, //!< No additional details 3103 ROUNDINTRA_316 = 2, //!< No additional details 3104 ROUNDINTRA_416 = 3, //!< No additional details 3105 ROUNDINTRA_516 = 4, //!< No additional details 3106 ROUNDINTRA_616 = 5, //!< No additional details 3107 ROUNDINTRA_716 = 6, //!< No additional details 3108 ROUNDINTRA_816 = 7, //!< No additional details 3109 }; 3110 3111 //! \brief ROUNDINTER 3112 //! \details 3113 //! Rounding precision for Inter quantized coefficients 3114 enum ROUNDINTER 3115 { 3116 ROUNDINTER_116 = 0, //!< No additional details 3117 ROUNDINTER_216 = 1, //!< No additional details 3118 ROUNDINTER_316 = 2, //!< No additional details 3119 ROUNDINTER_416 = 3, //!< No additional details 3120 ROUNDINTER_516 = 4, //!< No additional details 3121 ROUNDINTER_616 = 5, //!< No additional details 3122 ROUNDINTER_716 = 6, //!< No additional details 3123 ROUNDINTER_816 = 7, //!< No additional details 3124 }; 3125 3126 //! \name Initializations 3127 3128 //! \brief Explicit member initialization function 3129 MFX_AVC_SLICE_STATE_CMD(); 3130 3131 static const size_t dwSize = 11; 3132 static const size_t byteSize = 44; 3133 }; 3134 3135 //! 3136 //! \brief MFD_AVC_DPB_STATE 3137 //! \details 3138 //! This is a frame level state command used only in AVC Short Slice 3139 //! Bitstream Format VLD mode. RefFrameList[16] of interface is 3140 //! replaced with intel Reference Picture Addresses[16] of 3141 //! MFX_PIPE_BUF_ADDR_STATE command. The LongTerm Picture flag indicator of 3142 //! all reference pictures are collected into LongTermPic_Flag[16]. 3143 //! FieldOrderCntList[16][2] and CurrFieldOrderCnt[2] of interface are 3144 //! replaced with intel POCList[34] of MFX_AVC_DIRECTMODE_STATE command. 3145 //! 3146 struct MFD_AVC_DPB_STATE_CMD 3147 { 3148 union 3149 { 3150 //!< DWORD 0 3151 struct 3152 { 3153 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3154 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3155 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3156 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3157 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3158 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3159 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3160 }; 3161 uint32_t Value; 3162 } DW0; 3163 union 3164 { 3165 //!< DWORD 1 3166 struct 3167 { 3168 uint32_t NonExistingframeFlag161Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< NON_EXISTINGFRAME_FLAG161_BIT 3169 uint32_t LongtermframeFlag161Bit : __CODEGEN_BITFIELD(16, 31) ; //!< LONGTERMFRAME_FLAG161_BIT 3170 }; 3171 uint32_t Value; 3172 } DW1; 3173 union 3174 { 3175 //!< DWORD 2 3176 struct 3177 { 3178 uint32_t UsedforreferenceFlag162Bits ; //!< USEDFORREFERENCE_FLAG162_BITS 3179 }; 3180 uint32_t Value; 3181 } DW2; 3182 3183 uint32_t Ltstframenumlist1616Bits[8]; //!< LTSTFRAMENUMLIST1616_BITS 3184 3185 uint32_t Viewidlist1616Bits[8]; //!< ViewIDList[16][16 bits] 3186 3187 uint32_t Vieworderlistl0168Bits[4]; //!< ViewOrderListL0[16][8 bits] 3188 3189 uint32_t Vieworderlistl1168Bits[4]; //!< ViewOrderListL1[16][8 bits] 3190 3191 //! \name Local enumerations 3192 3193 enum SUBOPCODE_B 3194 { 3195 SUBOPCODE_B_UNNAMED6 = 6, //!< No additional details 3196 }; 3197 3198 enum SUBOPCODE_A 3199 { 3200 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3201 }; 3202 3203 enum MEDIA_COMMAND_OPCODE 3204 { 3205 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3206 }; 3207 3208 enum PIPELINE 3209 { 3210 PIPELINE_MFXMULTIDW = 2, //!< No additional details 3211 }; 3212 3213 enum COMMAND_TYPE 3214 { 3215 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3216 }; 3217 3218 //! \brief NON_EXISTINGFRAME_FLAG161_BIT 3219 //! \details 3220 //! One-to-one correspondence with the entries of the Intel 3221 //! RefFrameList[16]. 1 bit per reference frame. 3222 enum NON_EXISTINGFRAME_FLAG161_BIT 3223 { 3224 NON_EXISTINGFRAME_FLAG161_BIT_VALID = 0, //!< the reference picture in that entry of RefFrameList[] is a valid reference 3225 NON_EXISTINGFRAME_FLAG161_BIT_INVALID = 1, //!< the reference picture in that entry of RefFrameList[] does not exist anymore. 3226 }; 3227 3228 //! \brief LONGTERMFRAME_FLAG161_BIT 3229 //! \details 3230 //! One-to-one correspondence with the entries of the Intel 3231 //! RefFrameList[16]. 1 bit per reference frame. 3232 enum LONGTERMFRAME_FLAG161_BIT 3233 { 3234 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISASHORTTERMREFERENCEPICTURE = 0, //!< No additional details 3235 LONGTERMFRAME_FLAG161_BIT_THEPICTUREISALONGTERMREFERENCEPICTURE = 1, //!< No additional details 3236 }; 3237 3238 //! \brief USEDFORREFERENCE_FLAG162_BITS 3239 //! \details 3240 //! One-to-one correspondence with the entries of the Intel 3241 //! RefFrameList[16]. 2 bits per reference frame. 3242 enum USEDFORREFERENCE_FLAG162_BITS 3243 { 3244 USEDFORREFERENCE_FLAG162_BITS_NOTREFERENCE = 0, //!< indicates a frame is "not used for reference". 3245 USEDFORREFERENCE_FLAG162_BITS_TOPFIELD = 1, //!< bit[0] indicates that the top field of a frame is marked as "used for reference". 3246 USEDFORREFERENCE_FLAG162_BITS_BOTTOMFIELD = 2, //!< bit[1] indicates that the bottom field of a frame is marked as "used for reference". 3247 USEDFORREFERENCE_FLAG162_BITS_FRAME = 3, //!< bit[1:0] indicates that a frame (or field pair) is marked as "used for reference". 3248 }; 3249 3250 //! \brief LTSTFRAMENUMLIST1616_BITS 3251 //! \details 3252 //! One-to-one correspondence with the entries of the Intel 3253 //! RefFrameList[16]. 16 bits per reference frame.Depending on the 3254 //! corresponding LongTermFrame_Flag[], the content of this field is 3255 //! interpreted differently. 3256 enum LTSTFRAMENUMLIST1616_BITS 3257 { 3258 LTSTFRAMENUMLIST1616_BITS_SHORTTERMFRAMEFLAGI = 0, //!< LTSTFrameNumList[i]represent Short Term Picture FrameNum. 3259 LTSTFRAMENUMLIST1616_BITS_LONGTERMFRAMEFLAGI = 1, //!< LTSTFrameNumList[i] represent LongTermFrameIdx. 3260 }; 3261 3262 //! \name Initializations 3263 3264 //! \brief Explicit member initialization function 3265 MFD_AVC_DPB_STATE_CMD(); 3266 3267 static const size_t dwSize = 27; 3268 static const size_t byteSize = 108; 3269 }; 3270 3271 //! 3272 //! \brief MFD_AVC_SLICEADDR 3273 //! \details 3274 //! This is a Slice level command used only for AVC Short Slice 3275 //! Bitstream Format VLD mode.When decoding a slice, H/W needs to know the 3276 //! last MB of the slice has reached in order to start decoding the next 3277 //! slice. It also needs to know if a slice is terminated but the last MB 3278 //! has not reached, error conealment should be invoked to generate those 3279 //! missing MBs. For AVC Short Format, the only way to know the last 3280 //! MB position of the current slice, H/W needs to snoop into the next 3281 //! slice's start MB address (a linear address encoded in the Slice Header). 3282 //! Since each BSD Object command can have only one indirect bitstream 3283 //! buffer address, this command is added to help H/W to snoop into the next 3284 //! slice's slice header and retrieve its Start MB Address. This command 3285 //! will take the next slice's bitstream buffer address as input (exactly 3286 //! the same way as a BSD Object command), and parse only the 3287 //! first_mb_in_slice syntax element. The result will stored inside the H/W, 3288 //! and will be used to decode the current slice specified in the BSD Object 3289 //! command.Only the very first few bytes (max 5 bytes for a max 4K picture) 3290 //! of the Slice Header will be decoded, the rest of the bitstream are don't 3291 //! care. This is because the first_mb_in_slice is encoded in Exponential 3292 //! Golomb, and will take 33 bits to represent the max 256 x 256 = 64K-1 3293 //! value. The indirect data of MFD_AVC_SLICEADDR is a valid BSD object and 3294 //! is decoded as in BSD OBJECT command.The next Slice Start MB Address is 3295 //! also exposed to the MMIO interface.The Slice Start MB Address 3296 //! (first_mb_in_slice) is a linear MB address count; but it is translated 3297 //! into the corresponding 2D MB X and Y raster position, and are stored 3298 //! internally as NextSliceMbY and NextSliceMbX. 3299 //! 3300 struct MFD_AVC_SLICEADDR_CMD 3301 { 3302 union 3303 { 3304 //!< DWORD 0 3305 struct 3306 { 3307 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3308 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3309 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3310 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3311 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3312 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3313 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3314 }; 3315 uint32_t Value; 3316 } DW0; 3317 union 3318 { 3319 //!< DWORD 1 3320 struct 3321 { 3322 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3323 }; 3324 uint32_t Value; 3325 } DW1; 3326 union 3327 { 3328 //!< DWORD 2 3329 struct 3330 { 3331 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3332 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3333 }; 3334 uint32_t Value; 3335 } DW2; 3336 union 3337 { 3338 //!< DWORD 3 3339 struct 3340 { 3341 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Driver Provided NAL Type Value 3342 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD( 8, 8) ; //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3343 uint32_t Reserved105 : __CODEGEN_BITFIELD(9, 31) ; //!< Reserved 3344 }; 3345 uint32_t Value; 3346 } DW3; 3347 3348 //! \name Local enumerations 3349 3350 enum SUBOPCODE_B 3351 { 3352 SUBOPCODE_B_UNNAMED7 = 7, //!< No additional details 3353 }; 3354 3355 enum SUBOPCODE_A 3356 { 3357 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3358 }; 3359 3360 enum MEDIA_COMMAND_OPCODE 3361 { 3362 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3363 }; 3364 3365 enum PIPELINE 3366 { 3367 PIPELINE_MFDAVCSLICEADDR = 2, //!< No additional details 3368 }; 3369 3370 enum COMMAND_TYPE 3371 { 3372 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3373 }; 3374 3375 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3376 //! \details 3377 //! <p>This bit indicates hardware should use the NAL Type (provided below) 3378 //! programmed by driver instead of using the one from bitstream. The NAL 3379 //! byte from bitstream will not be correct.</p> 3380 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3381 { 3382 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from first byte of decoded bitstream. 3383 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided NAL Type Values" programmed by driver. 3384 }; 3385 3386 //! \name Initializations 3387 3388 //! \brief Explicit member initialization function 3389 MFD_AVC_SLICEADDR_CMD(); 3390 3391 static const size_t dwSize = 4; 3392 static const size_t byteSize = 16; 3393 }; 3394 3395 //! 3396 //! \brief MFD_AVC_BSD_OBJECT 3397 //! \details 3398 //! The MFD_AVC_BSD_OBJECT command is the only primitive command for the AVC 3399 //! Decoding Pipeline. The same command is used for both CABAC and CAVLD 3400 //! modes. The Slice Data portion of the bitstream is loaded as indirect 3401 //! data object.Before issuing a MFD_AVC_BSD_OBJECT command, all AVC states 3402 //! of the MFD Engine need to be valid. Therefore the commands used to set 3403 //! these states need to have been issued prior to the issue of a 3404 //! MFD_AVC_BSD_OBJECT command. 3405 //! 3406 //! Context switch interrupt is not supported by this command. 3407 //! 3408 struct MFD_AVC_BSD_OBJECT_CMD 3409 { 3410 union 3411 { 3412 //!< DWORD 0 3413 struct 3414 { 3415 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3416 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3417 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3418 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3419 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3420 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3421 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3422 }; 3423 uint32_t Value; 3424 } DW0; 3425 union 3426 { 3427 //!< DWORD 1 3428 struct 3429 { 3430 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 3431 }; 3432 uint32_t Value; 3433 } DW1; 3434 union 3435 { 3436 //!< DWORD 2 3437 struct 3438 { 3439 uint32_t IndirectBsdDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect BSD Data Start Address 3440 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 3441 }; 3442 uint32_t Value; 3443 } DW2; 3444 union 3445 { 3446 //!< DWORD 3 3447 struct 3448 { 3449 uint32_t MbErrorConcealmentPSliceWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3450 uint32_t MbErrorConcealmentPSliceMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3451 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 3452 uint32_t MbErrorConcealmentBSpatialWeightPredictionDisableFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3453 uint32_t MbErrorConcealmentBSpatialMotionVectorsOverrideDisableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3454 uint32_t Reserved101 : __CODEGEN_BITFIELD( 5, 5) ; //!< Reserved 3455 uint32_t MbErrorConcealmentBSpatialPredictionMode : __CODEGEN_BITFIELD( 6, 7) ; //!< MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3456 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING_ 3457 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 3458 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 3459 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3460 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3461 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 3462 uint32_t BsdPrematureCompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3463 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3464 uint32_t ConcealmentPictureId : __CODEGEN_BITFIELD(16, 21) ; //!< Concealment Picture ID 3465 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 3466 uint32_t MbErrorConcealmentBTemporalWeightPredictionDisableFlag : __CODEGEN_BITFIELD(24, 24) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3467 uint32_t MbErrorConcealmentBTemporalMotionVectorsOverrideEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3468 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 3469 uint32_t MbErrorConcealmentBTemporalPredictionMode : __CODEGEN_BITFIELD(27, 28) ; //!< MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3470 uint32_t IntraPredmode4X48X8LumaErrorControlBit : __CODEGEN_BITFIELD(29, 29) ; //!< INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3471 uint32_t InitCurrentMbNumber : __CODEGEN_BITFIELD(30, 30) ; //!< Init Current MB Number 3472 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 3473 }; 3474 uint32_t Value; 3475 } DW3; 3476 union 3477 { 3478 //!< DWORD 4 3479 struct 3480 { 3481 uint32_t FirstMacroblockMbBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock (MB)Bit Offset 3482 uint32_t LastsliceFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< LASTSLICE_FLAG 3483 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 3484 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 6) ; //!< Reserved 3485 uint32_t FixPrevMbSkipped : __CODEGEN_BITFIELD( 7, 7) ; //!< Fix Prev Mb Skipped 3486 uint32_t Reserved136 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3487 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First MB Byte Offset of Slice Data or Slice Header 3488 }; 3489 uint32_t Value; 3490 } DW4; 3491 union 3492 { 3493 //!< DWORD 5 3494 struct 3495 { 3496 uint32_t IntraPredictionErrorControlBitAppliedToIntra16X16Intra8X8Intra4X4LumaAndChroma : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3497 uint32_t Intra8X84X4PredictionErrorConcealmentControlBit : __CODEGEN_BITFIELD( 1, 1) ; //!< INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3498 uint32_t Reserved162 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 3499 uint32_t BSliceTemporalInterConcealmentMode : __CODEGEN_BITFIELD( 4, 6) ; //!< B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3500 uint32_t Reserved167 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3501 uint32_t BSliceSpatialInterConcealmentMode : __CODEGEN_BITFIELD( 8, 10) ; //!< B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3502 uint32_t Reserved171 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 3503 uint32_t BSliceInterDirectTypeConcealmentMode : __CODEGEN_BITFIELD(12, 13) ; //!< B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3504 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 3505 uint32_t BSliceConcealmentMode : __CODEGEN_BITFIELD(15, 15) ; //!< B_SLICE_CONCEALMENT_MODE 3506 uint32_t PSliceInterConcealmentMode : __CODEGEN_BITFIELD(16, 18) ; //!< P_SLICE_INTER_CONCEALMENT_MODE 3507 uint32_t Reserved179 : __CODEGEN_BITFIELD(19, 22) ; //!< Reserved 3508 uint32_t PSliceConcealmentMode : __CODEGEN_BITFIELD(23, 23) ; //!< P_SLICE_CONCEALMENT_MODE 3509 uint32_t ConcealmentReferencePictureFieldBit : __CODEGEN_BITFIELD(24, 29) ; //!< Concealment Reference Picture + Field Bit 3510 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 3511 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE 3512 }; 3513 uint32_t Value; 3514 } DW5; 3515 union 3516 { 3517 //!< DWORD 6 3518 struct 3519 { 3520 uint32_t DriverProvidedNalTypeValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Driver Provided Nal Type Value 3521 uint32_t AvcNalTypeFirstByteOverrideBit : __CODEGEN_BITFIELD( 8, 8) ; //!< AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3522 uint32_t Reserved2051 : __CODEGEN_BITFIELD(9, 31) ; //!< Reserved 3523 }; 3524 uint32_t Value; 3525 } DW6; 3526 3527 //! \name Local enumerations 3528 3529 enum SUBOPCODE_B 3530 { 3531 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3532 }; 3533 3534 enum SUBOPCODE_A 3535 { 3536 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 3537 }; 3538 3539 enum MEDIA_COMMAND_OPCODE 3540 { 3541 MEDIA_COMMAND_OPCODE_AVCDEC = 1, //!< No additional details 3542 }; 3543 3544 enum PIPELINE 3545 { 3546 PIPELINE_MFDAVCBSDOBJECT = 2, //!< No additional details 3547 }; 3548 3549 enum COMMAND_TYPE 3550 { 3551 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3552 }; 3553 3554 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3555 //! \details 3556 //! During MB Error Concealment on P slice, weight prediction is disabled to 3557 //! improve image quality. 3558 //! This bit can be set to preserve the original weight prediction. 3559 //! This bit does not affect normal decoded MB. 3560 enum MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG 3561 { 3562 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3563 MB_ERROR_CONCEALMENT_P_SLICE_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3564 }; 3565 3566 //! \brief MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3567 //! \details 3568 //! During MB Error Concealment on P slice, motion vectors are forced to 0 3569 //! to improve image quality. 3570 //! This bit can be set to use the predicted motion vectors instead. 3571 //! This bit does not affect normal decoded MB. 3572 enum MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3573 { 3574 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3575 MB_ERROR_CONCEALMENT_P_SLICE_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3576 }; 3577 3578 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3579 //! \details 3580 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3581 //! weight prediction is disabled to improve image quality. 3582 //! This bit can be set to preserve the original weight prediction. 3583 //! This bit does not affect normal decoded MB. 3584 enum MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG 3585 { 3586 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment. 3587 MB_ERROR_CONCEALMENT_B_SPATIAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment. 3588 }; 3589 3590 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3591 //! \details 3592 //! During MB Error Concealment on B slice with Spatial Direct Prediction, 3593 //! motion vectors are forced to 0 to improve image quality. 3594 //! This bit can be set to use the predicted motion vectors instead. 3595 //! This bit does not affect normal decoded MB. 3596 enum MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG 3597 { 3598 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED0 = 0, //!< Motion Vectors are Overridden to 0 during MB Concealment 3599 MB_ERROR_CONCEALMENT_B_SPATIAL_MOTION_VECTORS_OVERRIDE_DISABLE_FLAG_UNNAMED1 = 1, //!< Predicted Motion Vectors are used during MB Concealment 3600 }; 3601 3602 //! \brief MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3603 //! \details 3604 //! These two bits control how the reference L0/L1 are overridden in B 3605 //! spatial slice. 3606 enum MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_ 3607 { 3608 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3609 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3610 MB_ERROR_CONCEALMENT_B_SPATIAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3611 }; 3612 3613 //! \brief MB_HEADER_ERROR_HANDLING_ 3614 //! \details 3615 //! Software must follow the action for each Value as follow: 3616 enum MB_HEADER_ERROR_HANDLING_ 3617 { 3618 MB_HEADER_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error concealment. 3619 MB_HEADER_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3620 }; 3621 3622 //! \brief ENTROPY_ERROR_HANDLING 3623 //! \details 3624 //! Software must follow the action for each Value as follow: 3625 enum ENTROPY_ERROR_HANDLING 3626 { 3627 ENTROPY_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically perform the error handling. 3628 ENTROPY_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W). 3629 }; 3630 3631 //! \brief MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3632 //! \details 3633 //! Software must follow the action for each Value as follow: 3634 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 3635 { 3636 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3637 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3638 }; 3639 3640 //! \brief BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3641 //! \details 3642 //! BSD Premature Complete Error occurs in situation where the Slice decode 3643 //! is completed but there are still data in the bitstream. 3644 enum BSD_PREMATURE_COMPLETE_ERROR_HANDLING 3645 { 3646 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED0 = 0, //!< Ignore the error and continue (masked the interrupt), assume the hardware automatically performs the error handling 3647 BSD_PREMATURE_COMPLETE_ERROR_HANDLING_UNNAMED1 = 1, //!< Set the interrupt to the driver (provide MMIO registers for MB address R/W) 3648 }; 3649 3650 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3651 //! \details 3652 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3653 //! weight prediction is disabled to improve image quality. 3654 //! This bit can be set to preserve the original weight prediction. 3655 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG 3656 { 3657 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED0 = 0, //!< Weight Prediction is Disabled during MB Concealment 3658 MB_ERROR_CONCEALMENT_B_TEMPORAL_WEIGHT_PREDICTION_DISABLE_FLAG_UNNAMED1 = 1, //!< Weight Prediction will not be overridden during MB Concealment 3659 }; 3660 3661 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3662 //! \details 3663 //! During MB Error Concealment on B slice with Temporal Direct Prediction, 3664 //! motion vectors are forced to 0 to improve image quality. 3665 //! This bit can be set to preserve the original weight prediction. 3666 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG 3667 { 3668 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED0 = 0, //!< Predicted Motion Vectors are used during MB Concealment 3669 MB_ERROR_CONCEALMENT_B_TEMPORAL_MOTION_VECTORS_OVERRIDE_ENABLE_FLAG_UNNAMED1 = 1, //!< Motion Vectors are Overridden to 0 during MB Concealment 3670 }; 3671 3672 //! \brief MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3673 //! \details 3674 //! These two bits control how the reference L0/L1 are overridden in B 3675 //! temporal slice. 3676 enum MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE 3677 { 3678 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED0 = 0, //!< Both Reference Indexes L0/L1 are forced to 0 during Concealment 3679 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED1 = 1, //!< Only Reference Index L1 is forced to 0; Reference Index L0 is forced to -1 3680 MB_ERROR_CONCEALMENT_B_TEMPORAL_PREDICTION_MODE_UNNAMED2 = 2, //!< Only Reference Index L0 is forced to 0; Reference Index L1 is forced to -1 3681 }; 3682 3683 //! \brief INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3684 //! \details 3685 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3686 //! decoded value is incorrect according to MB position 3687 enum INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT 3688 { 3689 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will detect and fix IntraPredMode (4x4/8x8 Luma) Errors. 3690 INTRA_PREDMODE_4X48X8_LUMA_ERROR_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will NOT detect IntraPredMode (4x4/8x8 Luma) Errors. The wrong IntraPredMode value will be retaind. 3691 }; 3692 3693 //! \brief CONCEALMENT_METHOD 3694 //! \details 3695 //! This field specifies the method used for concealment when error is 3696 //! detected. If set, a copy from collocated macroblock location is 3697 //! performed from the concealment reference indicated by the ConCeal_Pic_Id 3698 //! field. If it is not set, a copy from the current picture is performed 3699 //! using Intra 16x16 Prediction method. 3700 enum CONCEALMENT_METHOD 3701 { 3702 CONCEALMENT_METHOD_UNNAMED0 = 0, //!< Intra 16x16 Prediction 3703 CONCEALMENT_METHOD_UNNAMED1 = 1, //!< Inter P Copy 3704 }; 3705 3706 //! \brief LASTSLICE_FLAG 3707 //! \details 3708 //! It is needed for both error concealment at the end of a picture (so, no 3709 //! more phantom slice as in DevSNB). It is also needed to know to set the 3710 //! last MB in a picture correctly. 3711 enum LASTSLICE_FLAG 3712 { 3713 LASTSLICE_FLAG_UNNAMED0 = 0, //!< If the current Slice to be decoded is any slice other than the very last slice of the current picture 3714 LASTSLICE_FLAG_UNNAMED1 = 1, //!< If the current Slice to be decoded is the very last slice of the current picture. 3715 }; 3716 3717 enum EMULATION_PREVENTION_BYTE_PRESENT 3718 { 3719 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 3720 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 3721 }; 3722 3723 //! \brief INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3724 //! \details 3725 //! This field controls if AVC decoder will fix Intra Prediction Mode if the 3726 //! decoded value is incorrect according to MB position. 3727 enum INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA 3728 { 3729 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED0 = 0, //!< AVC decoder will detect and fix Intra Prediction Mode Errors. 3730 INTRA_PREDICTION_ERROR_CONTROL_BIT_APPLIED_TO_INTRA16X16INTRA8X8INTRA4X4_LUMA_AND_CHROMA_UNNAMED1 = 1, //!< AVC decoder will retain the Intra Prediction value decoded from bitstream. 3731 }; 3732 3733 //! \brief INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3734 //! \details 3735 //! This field controls if AVC goes into MB concealment mode (next MB) when 3736 //! an error is detected on Intra8x8/4x4 Prediction Mode (these 2 modes have 3737 //! fixed coding so it may not affect the bitstream. 3738 enum INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT 3739 { 3740 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED0 = 0, //!< AVC decoder will NOT go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3741 INTRA_8X84X4_PREDICTION_ERROR_CONCEALMENT_CONTROL_BIT_UNNAMED1 = 1, //!< AVC decoder will go into MB concealment when Intra8x8/4x4 Prediction mode is incorrect. 3742 }; 3743 3744 //! \brief B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3745 //! \details 3746 //! This field controls how AVC decoder select reference picture for 3747 //! Temporal Inter Concealment in B Slice 3748 enum B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE 3749 { 3750 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1) 3751 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3752 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using B-Skip Algorithm) 3753 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< " Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3754 B_SLICE_TEMPORAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0/L1(If no long term picture available, use Temporal Closest Picture) 3755 }; 3756 3757 //! \brief B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3758 //! \details 3759 //! This field controls how AVC decoder select reference picture for Spatial 3760 //! Inter Concealment in B Slice. 3761 enum B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE 3762 { 3763 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0/L1 (Use top entry of Reference List L0/L1). 3764 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3765 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC][For L1: Closest POC larger than current POC] 3766 B_SLICE_SPATIAL_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< " First Long Term Picture in Reference List L0/L1 (If no long term picture available, use Temporal Closest Picture) 3767 }; 3768 3769 //! \brief B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3770 //! \details 3771 //! AVC decoder can use Spatial or Temporal Direct for B Skip/Direct. 3772 //! This field determine can override the mode on how AVC decoder 3773 //! handles MB concealment in B slice. 3774 enum B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE 3775 { 3776 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Use Default Direct Type (slice programmed direct type) 3777 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Forced to Spatial Direct Only 3778 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Forced to Temporal Direct Only 3779 B_SLICE_INTER_DIRECT_TYPE_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Spatial Direct without Temporal Componenet (MovingBlock information) 3780 }; 3781 3782 //! \brief B_SLICE_CONCEALMENT_MODE 3783 //! \details 3784 //! This field controls how AVC decoder handle MB concealment in B Slice 3785 enum B_SLICE_CONCEALMENT_MODE 3786 { 3787 B_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3788 B_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3789 }; 3790 3791 //! \brief P_SLICE_INTER_CONCEALMENT_MODE 3792 //! \details 3793 //! This field controls how AVC decoder select reference picture for 3794 //! Concealment in P Slice. 3795 enum P_SLICE_INTER_CONCEALMENT_MODE 3796 { 3797 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED0 = 0, //!< Top of Reference List L0 (Use top entry of Reference List L0) 3798 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED1 = 1, //!< Driver Specified Concealment Reference 3799 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED2 = 2, //!< Predicted Reference (Use reference picture predicted using P-Skip Algorithm) 3800 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED3 = 3, //!< Temporal Closest (Using POC to select the closest forward picture)[For L0: Closest POC smaller than current POC] 3801 P_SLICE_INTER_CONCEALMENT_MODE_UNNAMED_4 = 4, //!< First Long Term Picture in Reference List L0 (If no long term picture available, use Temporal Closest Picture) 3802 }; 3803 3804 //! \brief P_SLICE_CONCEALMENT_MODE 3805 //! \details 3806 //! This field controls how AVC decoder handle MB concealment in P Slice 3807 enum P_SLICE_CONCEALMENT_MODE 3808 { 3809 P_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 0, //!< No additional details 3810 P_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 1, //!< No additional details 3811 }; 3812 3813 //! \brief I_SLICE_CONCEALMENT_MODE 3814 //! \details 3815 //! This field controls how AVC decoder handle MB concealment in I Slice 3816 enum I_SLICE_CONCEALMENT_MODE 3817 { 3818 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< No additional details 3819 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< No additional details 3820 }; 3821 3822 //! \brief AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3823 //! \details 3824 //! <p>This bit indicates hardware should use the NAL Type (provided below) 3825 //! programmed by driver instead of using the one from bitstream. The NAL 3826 //! byte from bitstream will not be correct.</p> 3827 enum AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT 3828 { 3829 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEBITSTREAMDECODEDNALTYPE = 0, //!< NAL Type should come from the first byte of Decoded Bitstream 3830 AVC_NAL_TYPE_FIRST_BYTE_OVERRIDE_BIT_USEDRIVERPROGRAMMEDNALTYPE = 1, //!< NAL Type should come from "Driver Provided Nal Type" programmed by driver. 3831 }; 3832 3833 //! \name Initializations 3834 3835 //! \brief Explicit member initialization function 3836 MFD_AVC_BSD_OBJECT_CMD(); 3837 3838 static const size_t dwSize = 7; 3839 static const size_t byteSize = 28; 3840 }; 3841 3842 //! 3843 //! \brief MFX_PAK_INSERT_OBJECT 3844 //! \details 3845 //! The MFX_PAK_INSERT_OBJECT command is the first primitive command for the 3846 //! AVC, MPEG2, JPEG, SVC and VP8 Encoding Pipeline. 3847 //! 3848 //! This command is issued to setup the control and parameters of inserting 3849 //! a chunk of compressed/encoded bits into the current bitstream output 3850 //! buffer starting at the specified bit locationto perform the actual 3851 //! insertion by transferring the command inline data to the output buffer 3852 //! max, 32 bits at a time. It is a variable length command as the data to 3853 //! be inserted are presented as inline data of this command. It is a 3854 //! multiple of 32-bit (1 DW), as the data bus to the bitstream buffer is 3855 //! 32-bit wide. Multiple insertion commands can be issued back to back in a 3856 //! series. It is host software's responsibility to make sure their 3857 //! corresponding data will properly stitch together to form a valid H.264 3858 //! bitstream. Internally, MFX hardware will keep track of the very last two 3859 //! bytes' (the very last byte can be a partial byte) values of the previous 3860 //! insertion. It is required that the next Insertion Object Command or the 3861 //! next PAK Object Command to perform the start code emulation sequence 3862 //! check and prevention 0x03 byte insertion with this end condition of the 3863 //! previous insertion. Hardware will keep track of an output bitstream 3864 //! buffer current byte position and the associated next bit insertion 3865 //! position index. Data to be inserted can be a valid H.264 NAL units or a 3866 //! partial NAL unit. Certain NAL unit has a minimum byte size requirement. 3867 //! As such the hardware will optionally (enabled by STATE Command) 3868 //! determines the number of CABAC_ZERO_WORD to be inserted to the end of 3869 //! the current NAL, based on the minimum byte size of a NAL and the actual 3870 //! bin count of the encoded Slice. Since prior to the CABAC_ZERO_WORD 3871 //! insertion, the RBSP or EBSP is already byte-aligned, so each 3872 //! CABAC_ZERO_WORD insertion is actually a 3-byte sequence 0x00 00 03. The 3873 //! inline data may have already been processed for start code emulation 3874 //! byte insertion, except the possibility of the last 2 bytes plus the very 3875 //! last partial byte (if any). Hence, when hardware performing the 3876 //! concatenation of multiple consecutive insertion commands, or 3877 //! concatenation of an insertion command and a PAK object command, it must 3878 //! check and perform the necessary start code emulation byte insert at the 3879 //! junction.The inline data is required to be byte aligned on the left 3880 //! (first transmitted bit order) and may or may not be byte aligned on the 3881 //! right (last transmitted bits). The command will specify the bit offset 3882 //! of the last valid DW.Each insertion state command defines a chunk of 3883 //! bits (compressed data) to be inserted at a specific location of the 3884 //! output compressed bitstream in the output buffer.Depend on CABAC or 3885 //! CAVLC encoding mode (from Slice State), PAK Object Command is always 3886 //! ended in byte aligned output bitstream except for CABAC header insertion 3887 //! which is bit aligned. In the aligned cases, PAK will perform 0 filling 3888 //! in CAVLC mode, and 1 filling in CABAC mode. Insertion data can 3889 //! include:any encoded syntax elements bit data before the encoded Slice 3890 //! Data (PAK Object Command) of the current SliceSPS NALPPS NALSEI NALOther 3891 //! Non-Slice NALLeading_Zero_8_bits (as many bytes as there is)Start Code 3892 //! PrefixNAL Header ByteSlice HeaderAny encoded syntax elements bit data 3893 //! after the encoded Slice Data (PAK Object Command) of the current Slice 3894 //! and prior to the next encoded Slice Data of the next Slice or prior to 3895 //! the end of the bistream, whichever comes firstCabac_Zero_Word or 3896 //! Trailing_Zero_8bits (as many bytes as there is). Anything listed above 3897 //! before a Slice DataContext switch interrupt is not supported by this 3898 //! command. 3899 //! 3900 struct MFX_PAK_INSERT_OBJECT_CMD 3901 { 3902 union 3903 { 3904 //!< DWORD 0 3905 struct 3906 { 3907 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3908 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3909 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 3910 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 3911 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 3912 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3913 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3914 }; 3915 uint32_t Value; 3916 } DW0; 3917 union 3918 { 3919 //!< DWORD 1 3920 struct 3921 { 3922 uint32_t BitstreamstartresetResetbitstreamstartingpos : __CODEGEN_BITFIELD( 0, 0) ; //!< BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3923 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 3924 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 3925 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3926 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 3927 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 3928 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< SLICE_HEADER_INDICATOR 3929 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 3930 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 3931 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 31) ; //!< Reserved 3932 }; 3933 uint32_t Value; 3934 } DW1; 3935 3936 //! \name Local enumerations 3937 3938 enum SUBOPCODE_B 3939 { 3940 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 3941 }; 3942 3943 enum SUBOPCODE_A 3944 { 3945 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 3946 }; 3947 3948 enum MEDIA_COMMAND_OPCODE 3949 { 3950 MEDIA_COMMAND_OPCODE_MFXCOMMON = 0, //!< No additional details 3951 }; 3952 3953 enum PIPELINE 3954 { 3955 PIPELINE_MFXPAKINSERTOBJECT = 2, //!< No additional details 3956 }; 3957 3958 enum COMMAND_TYPE 3959 { 3960 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3961 }; 3962 3963 //! \brief BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3964 //! \details 3965 //! Must be set to 1 for JPEG encoder 3966 enum BITSTREAMSTARTRESET__RESETBITSTREAMSTARTINGPOS 3967 { 3968 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_INSERT = 0, //!< Insert the current command inline data starting at the current bitstream buffer insertion position 3969 BITSTREAMSTARTRESET_RESETBITSTREAMSTARTINGPOS_RESET = 1, //!< Reset the bitstream buffer insertion position to the bitstream buffer starting position. 3970 }; 3971 3972 //! \brief EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3973 //! \details 3974 //! Must be set to 0 for JPEG encoder 3975 enum EMULATIONFLAG__EMULATIONBYTEBITSINSERTENABLE 3976 { 3977 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_NONE = 0, //!< No emulation 3978 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_EMULATE = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between insertion commands, or an insertion command followed by a PAK Object command. 3979 }; 3980 3981 //! \brief SLICE_HEADER_INDICATOR 3982 //! \details 3983 //! This bit indicates if the insert object is a slice header. In the VDEnc 3984 //! mode, PAK only gets this command at the beginning of the frame for slice 3985 //! position X=0, Y=0. It internally generates the header that needs to be 3986 //! inserted per slice. For VDEnc mode, this bit should always be set. 3987 enum SLICE_HEADER_INDICATOR 3988 { 3989 SLICE_HEADER_INDICATOR_LEGACY = 0, //!< Legacy Insertion Object command. The PAK Insertion Object command is not stored in HW. 3990 SLICE_HEADER_INDICATOR_SLICEHEADER = 1, //!< Insertion Object is a Slice Header. The command is stored internally by HW and is used for inserting slice headers. 3991 }; 3992 3993 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 3994 //! \details 3995 //! In case this flag is on, bits are NOT accumulated during current access 3996 //! unit coding neither for Cabac Zero Word insertion bits counting or for 3997 //! output in MMIO register MFC_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER. 3998 //! When using HeaderLenghtExcludeFrmSize for header insertion, the 3999 //! software needs to make sure that data comes already with inserted start 4000 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 4001 //! DWORD1 of MFX_PAK_INSERT_OBJECT). 4002 enum HEADERLENGTHEXCLUDEFRMSIZE_ 4003 { 4004 HEADERLENGTHEXCLUDEFRMSIZE_ACCUMULATE = 0, //!< All bits accumulated 4005 HEADERLENGTHEXCLUDEFRMSIZE_NOACCUMULATION = 1, //!< Bits during current call are not accumulated 4006 }; 4007 4008 //! \name Initializations 4009 4010 //! \brief Explicit member initialization function 4011 MFX_PAK_INSERT_OBJECT_CMD(); 4012 4013 static const size_t dwSize = 2; 4014 static const size_t byteSize = 8; 4015 }; 4016 4017 //! 4018 //! \brief MFX_MPEG2_PIC_STATE 4019 //! \details 4020 //! This must be the very first command to issue after the surface state, 4021 //! the pipe select and base address setting commands. For MPEG-2 the 4022 //! encoder is called per slice-group, however the picture state is called 4023 //! per picture.Notice that a slice-group is a group of consecutive slices 4024 //! that no non-trivial slice headers are inserted in between. 4025 //! 4026 struct MFX_MPEG2_PIC_STATE_CMD 4027 { 4028 union 4029 { 4030 //!< DWORD 0 4031 struct 4032 { 4033 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4034 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4035 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4036 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4037 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4038 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4039 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4040 }; 4041 uint32_t Value; 4042 } DW0; 4043 union 4044 { 4045 //!< DWORD 1 4046 struct 4047 { 4048 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 4049 uint32_t ScanOrder : __CODEGEN_BITFIELD( 6, 6) ; //!< SCAN_ORDER 4050 uint32_t IntraVlcFormat : __CODEGEN_BITFIELD( 7, 7) ; //!< Intra VLC Format 4051 uint32_t QuantizerScaleType : __CODEGEN_BITFIELD( 8, 8) ; //!< QUANTIZER_SCALE_TYPE 4052 uint32_t ConcealmentMotionVectorFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< Concealment Motion Vector Flag 4053 uint32_t FramePredictionFrameDct : __CODEGEN_BITFIELD(10, 10) ; //!< Frame Prediction Frame DCT 4054 uint32_t TffTopFieldFirst : __CODEGEN_BITFIELD(11, 11) ; //!< TFF (Top Field First) 4055 uint32_t PictureStructure : __CODEGEN_BITFIELD(12, 13) ; //!< Picture Structure 4056 uint32_t IntraDcPrecision : __CODEGEN_BITFIELD(14, 15) ; //!< Intra DC Precision 4057 uint32_t FCode00 : __CODEGEN_BITFIELD(16, 19) ; //!< f_code[0][0] 4058 uint32_t FCode01 : __CODEGEN_BITFIELD(20, 23) ; //!< f_code[0][1] 4059 uint32_t FCode10 : __CODEGEN_BITFIELD(24, 27) ; //!< f_code[1][0]. 4060 uint32_t FCode11 : __CODEGEN_BITFIELD(28, 31) ; //!< f_code[1][1]. 4061 }; 4062 uint32_t Value; 4063 } DW1; 4064 union 4065 { 4066 //!< DWORD 2 4067 struct 4068 { 4069 uint32_t DisableMismatch : __CODEGEN_BITFIELD( 0, 0) ; //!< Disable Mismatch 4070 uint32_t Mismatchcontroldisabled : __CODEGEN_BITFIELD( 1, 1) ; //!< MISMATCHCONTROLDISABLED 4071 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 8) ; //!< Reserved 4072 uint32_t PictureCodingType : __CODEGEN_BITFIELD( 9, 10) ; //!< PICTURE_CODING_TYPE 4073 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 13) ; //!< Reserved 4074 uint32_t LoadslicepointerflagLoadbitstreampointerperslice : __CODEGEN_BITFIELD(14, 14) ; //!< LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4075 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 23) ; //!< Reserved 4076 uint32_t PBSlicePredictedMotionVectorOverrideFinalMvValueOverride : __CODEGEN_BITFIELD(24, 24) ; //!< PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4077 uint32_t PBSlicePredictedBidirMotionTypeOverrideBiDirectionMvTypeOverride : __CODEGEN_BITFIELD(25, 26) ; //!< PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4078 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 4079 uint32_t PBSliceConcealmentMode : __CODEGEN_BITFIELD(28, 29) ; //!< PB_SLICE_CONCEALMENT_MODE_ 4080 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 30) ; //!< Reserved 4081 uint32_t ISliceConcealmentMode : __CODEGEN_BITFIELD(31, 31) ; //!< I_SLICE_CONCEALMENT_MODE_ 4082 }; 4083 uint32_t Value; 4084 } DW2; 4085 union 4086 { 4087 //!< DWORD 3 4088 struct 4089 { 4090 uint32_t Framewidthinmbsminus170PictureWidthInMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< FrameWidthInMBsMinus1[7:0] (Picture Width in Macroblocks) 4091 uint32_t Reserved104 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 4092 uint32_t Frameheightinmbsminus170PictureHeightInMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< FrameHeightInMBsMinus1[7:0] (Picture Height in Macroblocks) 4093 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 30) ; //!< Reserved 4094 uint32_t SliceConcealmentDisableBit : __CODEGEN_BITFIELD(31, 31) ; //!< SLICE_CONCEALMENT_DISABLE_BIT 4095 }; 4096 uint32_t Value; 4097 } DW3; 4098 union 4099 { 4100 //!< DWORD 4 4101 struct 4102 { 4103 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 4104 uint32_t Roundintradc : __CODEGEN_BITFIELD( 1, 2) ; //!< RoundIntraDC 4105 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 4106 uint32_t Roundinterdc : __CODEGEN_BITFIELD( 4, 6) ; //!< RoundInterDC 4107 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 4108 uint32_t Roundintraac : __CODEGEN_BITFIELD( 8, 10) ; //!< RoundIntraAC 4109 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 4110 uint32_t Roundinterac : __CODEGEN_BITFIELD(12, 14) ; //!< RoundInterAC, 4111 uint32_t Mbstatenabled : __CODEGEN_BITFIELD(15, 15) ; //!< MBSTATENABLED 4112 uint32_t Minframewsize : __CODEGEN_BITFIELD(16, 31) ; //!< MINFRAMEWSIZE 4113 }; 4114 uint32_t Value; 4115 } DW4; 4116 union 4117 { 4118 //!< DWORD 5 4119 struct 4120 { 4121 uint32_t Intrambmaxsizereportmask : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAMBMAXSIZEREPORTMASK 4122 uint32_t Intermbmaxsizereportmask : __CODEGEN_BITFIELD( 1, 1) ; //!< INTERMBMAXSIZEREPORTMASK 4123 uint32_t Framebitratemaxreportmask : __CODEGEN_BITFIELD( 2, 2) ; //!< FRAMEBITRATEMAXREPORTMASK_ 4124 uint32_t Framebitrateminreportmask : __CODEGEN_BITFIELD( 3, 3) ; //!< FRAMEBITRATEMINREPORTMASK 4125 uint32_t Reserved164 : __CODEGEN_BITFIELD( 4, 8) ; //!< Reserved 4126 uint32_t Mbratecontrolmask : __CODEGEN_BITFIELD( 9, 9) ; //!< MBRATECONTROLMASK 4127 uint32_t Minframewsizeunits : __CODEGEN_BITFIELD(10, 11) ; //!< MINFRAMEWSIZEUNITS 4128 uint32_t Intermbforcecbpzerocontrolmask : __CODEGEN_BITFIELD(12, 12) ; //!< INTERMBFORCECBPZEROCONTROLMASK 4129 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 4130 uint32_t Framesizecontrolmask : __CODEGEN_BITFIELD(16, 16) ; //!< FRAMESIZECONTROLMASK 4131 uint32_t Reserved177 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 4132 }; 4133 uint32_t Value; 4134 } DW5; 4135 union 4136 { 4137 //!< DWORD 6 4138 struct 4139 { 4140 uint32_t Intrambmaxsize : __CODEGEN_BITFIELD( 0, 11) ; //!< INTRAMBMAXSIZE 4141 uint32_t Reserved204 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4142 uint32_t Intermbmaxsize : __CODEGEN_BITFIELD(16, 27) ; //!< INTERMBMAXSIZE 4143 uint32_t Reserved220 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 4144 }; 4145 uint32_t Value; 4146 } DW6; 4147 union 4148 { 4149 //!< DWORD 7 4150 struct 4151 { 4152 uint32_t VslTopMbTrans8X8Flag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSL_TOP_MB_TRANS8X8FLAG 4153 uint32_t Reserved225 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 4154 }; 4155 uint32_t Value; 4156 } DW7; 4157 union 4158 { 4159 //!< DWORD 8 4160 struct 4161 { 4162 uint32_t Slicedeltaqpmax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMax[0] 4163 uint32_t Slicedeltaqpmax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMax[1] 4164 uint32_t Slicedeltaqpmax2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMax[2] 4165 uint32_t Slicedeltaqpmax3 : __CODEGEN_BITFIELD(24, 31) ; //!< SLICEDELTAQPMAX3 4166 }; 4167 uint32_t Value; 4168 } DW8; 4169 union 4170 { 4171 //!< DWORD 9 4172 struct 4173 { 4174 uint32_t Slicedeltaqpmin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< SliceDeltaQPMin[0] 4175 uint32_t Slicedeltaqpmin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< SliceDeltaQPMin[1] 4176 uint32_t Slicedeltaqpmin2 : __CODEGEN_BITFIELD(16, 23) ; //!< SliceDeltaQPMin[2] 4177 uint32_t Slicedeltaqpmin3 : __CODEGEN_BITFIELD(24, 31) ; //!< SliceDeltaQPMin[3] 4178 }; 4179 uint32_t Value; 4180 } DW9; 4181 union 4182 { 4183 //!< DWORD 10 4184 struct 4185 { 4186 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 4187 uint32_t Framebitrateminunitmode : __CODEGEN_BITFIELD(14, 14) ; //!< FRAMEBITRATEMINUNITMODE 4188 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(15, 15) ; //!< FRAMEBITRATEMINUNIT 4189 uint32_t Framebitratemax : __CODEGEN_BITFIELD(16, 29) ; //!< FrameBitRateMax 4190 uint32_t Framebitratemaxunitmode : __CODEGEN_BITFIELD(30, 30) ; //!< FRAMEBITRATEMAXUNITMODE 4191 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT_ 4192 }; 4193 uint32_t Value; 4194 } DW10; 4195 union 4196 { 4197 //!< DWORD 11 4198 struct 4199 { 4200 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FrameBitRateMinDelta 4201 uint32_t Reserved367 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 4202 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 4203 uint32_t Reserved383 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 4204 }; 4205 uint32_t Value; 4206 } DW11; 4207 union 4208 { 4209 //!< DWORD 12 4210 struct 4211 { 4212 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 31) ; //!< Reserved 4213 }; 4214 uint32_t Value; 4215 } DW12; 4216 4217 //! \name Local enumerations 4218 4219 enum SUBOPCODE_B 4220 { 4221 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 4222 }; 4223 4224 enum SUBOPCODE_A 4225 { 4226 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 4227 }; 4228 4229 enum MEDIA_COMMAND_OPCODE 4230 { 4231 MEDIA_COMMAND_OPCODE_MPEG2COMMON = 3, //!< No additional details 4232 }; 4233 4234 enum PIPELINE 4235 { 4236 PIPELINE_MFXMPEG2PICSTATE = 2, //!< No additional details 4237 }; 4238 4239 enum COMMAND_TYPE 4240 { 4241 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4242 }; 4243 4244 //! \brief SCAN_ORDER 4245 //! \details 4246 //! This field specifies the Inverse Scan method for the DCT-domain 4247 //! coefficients in the blocks of the current picture. 4248 enum SCAN_ORDER 4249 { 4250 SCAN_ORDER_UNNAMED0 = 0, //!< MPEG_ZIGZAG_SCAN 4251 SCAN_ORDER_UNNAMED1 = 1, //!< MPEG_ALTERNATE_VERTICAL_SCAN 4252 }; 4253 4254 //! \brief QUANTIZER_SCALE_TYPE 4255 //! \details 4256 //! This field specifies the quantizer scaling type. 4257 enum QUANTIZER_SCALE_TYPE 4258 { 4259 QUANTIZER_SCALE_TYPE_UNNAMED0 = 0, //!< MPEG_QSCALE_LINEAR 4260 QUANTIZER_SCALE_TYPE_UNNAMED1 = 1, //!< D MPEG_QSCALE_NONLINEAR esc 4261 }; 4262 4263 //! \brief MISMATCHCONTROLDISABLED 4264 //! \details 4265 //! These 2 bits flag disables mismatch control of the inverse 4266 //! transformation for some specific cases during reference reconstruction. 4267 enum MISMATCHCONTROLDISABLED 4268 { 4269 MISMATCHCONTROLDISABLED_UNNAMED0 = 0, //!< Mismatch control applies to all MBs 4270 MISMATCHCONTROLDISABLED_UNNAMED1 = 1, //!< Disable mismatch control to all intra MBs whose all AC-coefficients are zero. 4271 MISMATCHCONTROLDISABLED_UNNAMED2 = 2, //!< Disable mismatch control to all MBs whose all AC-coefficients are zero. 4272 MISMATCHCONTROLDISABLED_UNNAMED3 = 3, //!< Disable mismatch control to all MBs. 4273 }; 4274 4275 //! \brief PICTURE_CODING_TYPE 4276 //! \details 4277 //! This field identifies whether the picture is an intra-coded picture (I), 4278 //! predictive-coded picture (P) or bi-directionally predictive-coded 4279 //! picture (B). See ISO/IEC 13818-2 6.3.9 for details. 4280 enum PICTURE_CODING_TYPE 4281 { 4282 PICTURE_CODING_TYPE_MPEGIPICTURE = 1, //!< No additional details 4283 PICTURE_CODING_TYPE_10MPEGPPICTURE = 2, //!< No additional details 4284 PICTURE_CODING_TYPE_MPEGBPICTURE = 3, //!< No additional details 4285 }; 4286 4287 //! \brief LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4288 //! \details 4289 //! To support multiple slice picture and additional header/data insertion 4290 //! before and after an encoded slice.When this field is set to 0, bitstream 4291 //! pointer is only loaded once for the first slice of a frame. For 4292 //! subsequent slices in the frame, bitstream data are stitched together to 4293 //! form a single output data stream.When this field is set to 1, bitstream 4294 //! pointer is loaded for each slice of a frame. Basically bitstream data 4295 //! for different slices of a frame will be written to different memory 4296 //! locations. 4297 enum LOADSLICEPOINTERFLAG__LOADBITSTREAMPOINTERPERSLICE 4298 { 4299 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED0 = 0, //!< Load BitStream Pointer only once for the first slice of a frame 4300 LOADSLICEPOINTERFLAG_LOADBITSTREAMPOINTERPERSLICE_UNNAMED1 = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of the bitstream buffer from the Indirect PAK-BSE Object Data Start Address field 4301 }; 4302 4303 //! \brief PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4304 //! \details 4305 //! This field is only applicable if the Concealment Motion Vectors are 4306 //! non-zero. 4307 //! It is only possible if "P/B Slice Concealment Mode" is set to "00" 4308 //! or "01" and left MB has non-zero motion vectors). 4309 enum PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE 4310 { 4311 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_PREDICTED = 0, //!< Motion Vectors use predicted values 4312 PB_SLICE_PREDICTED_MOTION_VECTOR_OVERRIDE_FINAL_MV_VALUE_OVERRIDE_ZERO = 1, //!< Motion Vectors force to 0 4313 }; 4314 4315 //! \brief PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4316 //! \details 4317 //! This field is only applicable if the Concealment Motion Type is 4318 //! predicted to be Bi-directional. 4319 //! (It is only possible if "P/B Slice Concealment Mode" is set to "00" 4320 //! or "01" and left MB is a bi-directional MB). 4321 enum PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE__BI_DIRECTION_MV_TYPE_OVERRIDE 4322 { 4323 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BID = 0, //!< Keep Bi-direction Prediction 4324 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_FWD = 2, //!< Only use Forward Prediction (Backward MV is forced to invalid 4325 PB_SLICE_PREDICTED_BIDIR_MOTION_TYPE_OVERRIDE_BI_DIRECTION_MV_TYPE_OVERRIDE_BWD = 3, //!< Only use Backward Prediction (Forward MV is forced to invalid) 4326 }; 4327 4328 //! \brief PB_SLICE_CONCEALMENT_MODE_ 4329 //! \details 4330 //! This field controls how MPEG decoder handles MB concealment in P/B 4331 //! Slice. 4332 enum PB_SLICE_CONCEALMENT_MODE_ 4333 { 4334 PB_SLICE_CONCEALMENT_MODE_INTER = 0, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use forward reference (same polarity for field pic) with MV final values set to 0. 4335 PB_SLICE_CONCEALMENT_MODE_LEFT = 1, //!< If left MB is NOT Intra MB type (including skipMB), use left MB inter prediction mode [frame/field or forward/backward/bi] and MV final values as concealment.Otherwise (left MB is Intra MB), use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data) 4336 PB_SLICE_CONCEALMENT_MODE_ZERO = 2, //!< Always use forward reference (same polarity for field pic) with MV final values set to 0 (Macroblock is concealed as INTER coded) 4337 PB_SLICE_CONCEALMENT_MODE_INTRA = 3, //!< Use left MB dct_dc_pred[cc] values for concealment (Macroblock is concealed as INTRA MB and dct_dc_pred[cc] are DC predictor for Luma, Cr, Cb data 4338 }; 4339 4340 //! \brief I_SLICE_CONCEALMENT_MODE_ 4341 //! \details 4342 //! This field controls how MPEG decoder handles MB concealment in I Slice 4343 enum I_SLICE_CONCEALMENT_MODE_ 4344 { 4345 I_SLICE_CONCEALMENT_MODE_INTRACONCEALMENT = 0, //!< Using Coefficient values to handle MB concealment 4346 I_SLICE_CONCEALMENT_MODE_INTERCONCEALMENT = 1, //!< Using Motion Vectors to handle MB concealment 4347 }; 4348 4349 //! \brief SLICE_CONCEALMENT_DISABLE_BIT 4350 //! \details 4351 //! If VINunit detects the next slice starting position is either 4352 //! out-of-bound or smaller than or equal to the current slice starting 4353 //! position, VIN will set the current slice to be 1 MB and force VMDunit to 4354 //! do slice concealment on the next slice. 4355 //! This bit will disable this feature and the MB data from the next 4356 //! slice will be decoded from bitstream. 4357 enum SLICE_CONCEALMENT_DISABLE_BIT 4358 { 4359 SLICE_CONCEALMENT_DISABLE_BIT_ENABLE = 0, //!< VIN will force next slice to be concealment if detects slice boundary error 4360 SLICE_CONCEALMENT_DISABLE_BIT_DISABLE = 1, //!< VIN will not force next slice to be in concealment 4361 }; 4362 4363 //! \brief MINFRAMEWSIZE 4364 //! \details 4365 //! - Minimum Frame Size [15:0] (16-bit) (Encoder Only)Mininum Frame Size is 4366 //! specified to compensate for intel Rate ControlCurrently zero fill (no 4367 //! need to perform emulation byte insertion) is done only to the end of the 4368 //! CABAC_ZERO_WORD insertion (if any) at the last slice of a picture. Intel 4369 //! encoder parameter. The caller should always make sure 4370 //! that the value, represented by Mininum Frame Size, is always less than 4371 //! maximum frame size FrameBitRateMax (DWORD 10 bits 29:16). This field is 4372 //! reserved in Decode mode. 4373 enum MINFRAMEWSIZE 4374 { 4375 MINFRAMEWSIZE_UNNAMED0 = 0, //!< No additional details 4376 }; 4377 4378 //! \brief INTRAMBMAXSIZEREPORTMASK 4379 //! \details 4380 //! This is a mask bit controlling if the condition of any intra MB in the 4381 //! frame exceeds IntraMBMaxSize. 4382 enum INTRAMBMAXSIZEREPORTMASK 4383 { 4384 INTRAMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4385 INTRAMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Intra MB Conformance Max size limit. 4386 }; 4387 4388 //! \brief INTERMBMAXSIZEREPORTMASK 4389 //! \details 4390 //! This is a mask bit controlling if the condition of any inter MB in the 4391 //! frame exceeds InterMBMaxSize. 4392 enum INTERMBMAXSIZEREPORTMASK 4393 { 4394 INTERMBMAXSIZEREPORTMASK_UNNAMED0 = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4395 INTERMBMAXSIZEREPORTMASK_UNNAMED1 = 1, //!< set bit0 of MFC_IMAGE_STATUS control register if the total bit counter for the current MB is greater than the Inter MB Conformance Max size limit. 4396 }; 4397 4398 //! \brief FRAMEBITRATEMAXREPORTMASK_ 4399 //! \details 4400 //! This is a mask bit controlling if the condition of frame level bit count 4401 //! exceeds FrameBitRateMax. 4402 enum FRAMEBITRATEMAXREPORTMASK_ 4403 { 4404 FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4405 FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1 of MFC_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit rate Maximum limit. 4406 }; 4407 4408 //! \brief FRAMEBITRATEMINREPORTMASK 4409 //! \details 4410 //! This is a mask bit controlling if the condition of frame level bit count 4411 //! is less than FrameBitRateMin. 4412 enum FRAMEBITRATEMINREPORTMASK 4413 { 4414 FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit0 of MFC_IMAGE_STATUS control register. 4415 FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< set bit0 and bit 1of MFC_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit rate Minimum limit. 4416 }; 4417 4418 //! \brief MBRATECONTROLMASK 4419 //! \details 4420 //! MB Rate Control conformance maskThis field is ignored when 4421 //! MacroblockStatEnable is disabled or MB level Rate control flag for the 4422 //! current MB is disable in Macroblock Status Buffer. 4423 enum MBRATECONTROLMASK 4424 { 4425 MBRATECONTROLMASK_UNNAMED0 = 0, //!< Do not change QP values of inter macroblock with suggested QP values in Macroblock Status Buffer 4426 MBRATECONTROLMASK_UNNAMED1 = 1, //!< Apply RC QP delta for all macroblock 4427 }; 4428 4429 //! \brief MINFRAMEWSIZEUNITS 4430 //! \details 4431 //! This field is the Minimum Frame Size Units 4432 enum MINFRAMEWSIZEUNITS 4433 { 4434 MINFRAMEWSIZEUNITS_COMPATIBILITYMODE = 0, //!< Minimum Frame Size is in old mode (words, 2bytes) 4435 MINFRAMEWSIZEUNITS_16BYTE = 1, //!< Minimum Frame Size is in 16bytes 4436 MINFRAMEWSIZEUNITS_4KB = 2, //!< Minimum Frame Size is in 4Kbytes 4437 MINFRAMEWSIZEUNITS_16KB = 3, //!< Minimum Frame Size is in 16Kbytes 4438 }; 4439 4440 //! \brief INTERMBFORCECBPZEROCONTROLMASK 4441 //! \details 4442 //! Inter MB Force CBP ZERO mask. 4443 enum INTERMBFORCECBPZEROCONTROLMASK 4444 { 4445 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED0 = 0, //!< No effect 4446 INTERMBFORCECBPZEROCONTROLMASK_UNNAMED1 = 1, //!< Zero out all A/C coefficients for the inter MB violating Inter Confirmance 4447 }; 4448 4449 //! \brief FRAMESIZECONTROLMASK 4450 //! \details 4451 //! Frame size conformance maskThis field is used when MacroblockStatEnable 4452 //! is set to 1. 4453 enum FRAMESIZECONTROLMASK 4454 { 4455 FRAMESIZECONTROLMASK_UNNAMED0 = 0, //!< Do not change Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control 4456 FRAMESIZECONTROLMASK_UNNAMED1 = 1, //!< Replace Slice Quantization Parameter values in MFC_MPEG2_SLICEGROUP_STATE with suggested slice QP value for frame level Rate control values in MFC_IMAGE_STATUS control register. 4457 }; 4458 4459 //! \brief INTRAMBMAXSIZE 4460 //! \details 4461 //! This field, Intra MB Conformance Max size limit,indicates the allowed 4462 //! max bit count size for Intra MB 4463 enum INTRAMBMAXSIZE 4464 { 4465 INTRAMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4466 }; 4467 4468 //! \brief INTERMBMAXSIZE 4469 //! \details 4470 //! This field, Inter MB Conformance Max size limit,indicates the allowed 4471 //! max bit count size for Inter MB 4472 enum INTERMBMAXSIZE 4473 { 4474 INTERMBMAXSIZE_UNNAMED_4095 = 4095, //!< No additional details 4475 }; 4476 4477 enum VSL_TOP_MB_TRANS8X8FLAG 4478 { 4479 VSL_TOP_MB_TRANS8X8FLAG_DISABLE = 0, //!< VSL will only fetch the current MB data. 4480 VSL_TOP_MB_TRANS8X8FLAG_ENABLE = 1, //!< When this bit is set VSL will make extra fetch to memory to fetch the MB data for top MB. 4481 }; 4482 4483 //! \brief SLICEDELTAQPMAX3 4484 //! \details 4485 //! This field is the Slice level delta QP for total 4486 //! bit-count above FrameBitRateMax - first 1/8 regionThis field is 4487 //! used to 4488 //! calculate the suggested slice QP into the MFC_IMAGE_STATUS control 4489 //! register when 4490 //! total bit count for the entire frame exceeds FrameBitRateMax but is 4491 //! within 1/8 4492 //! of FrameBitRateMaxDelta above FrameBitRateMax, i.e., in the range 4493 //! of 4494 //! (FrameBitRateMax, (FrameBitRateMax+ 4495 //! FrameBitRateMaxDelta>>3). 4496 enum SLICEDELTAQPMAX3 4497 { 4498 SLICEDELTAQPMAX3_DISABLE = 0, //!< No additional details 4499 SLICEDELTAQPMAX3_ENABLE = 1, //!< No additional details 4500 }; 4501 4502 //! \brief FRAMEBITRATEMINUNITMODE 4503 //! \details 4504 //! This field is the Frame Bitrate Minimum Limit 4505 //! Units.ValueNameDescriptionProject 4506 enum FRAMEBITRATEMINUNITMODE 4507 { 4508 FRAMEBITRATEMINUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4509 FRAMEBITRATEMINUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4510 }; 4511 4512 //! \brief FRAMEBITRATEMINUNIT 4513 //! \details 4514 //! This field is the Frame Bitrate Minimum Limit Units. 4515 enum FRAMEBITRATEMINUNIT 4516 { 4517 FRAMEBITRATEMINUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMinUnitMode is 1 and in units of 128 Bytes if FrameBitrateMinUnitMode is 0 4518 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4519 }; 4520 4521 //! \brief FRAMEBITRATEMAXUNITMODE 4522 //! \details 4523 //! BitFiel This field is the Frame Bitrate Maximum Limit Units.dDesc 4524 enum FRAMEBITRATEMAXUNITMODE 4525 { 4526 FRAMEBITRATEMAXUNITMODE_COMPATIBILITYMODE = 0, //!< FrameBitRateMaxUnit is in old mode (128b/16Kb) 4527 FRAMEBITRATEMAXUNITMODE_NEWMODE = 1, //!< FrameBitRateMaxUnit is in new mode (32byte/4Kb) 4528 }; 4529 4530 //! \brief FRAMEBITRATEMAXUNIT_ 4531 //! \details 4532 //! This field is the Frame Bitrate Maximum Limit Units. 4533 enum FRAMEBITRATEMAXUNIT_ 4534 { 4535 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< FrameBitRateMax is in units of 32 Bytes when FrameBitrateMaxUnitMode is 1 and in units of 128 Bytes if FrameBitrateMaxUnitMode is 0 4536 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< FrameBitRateMax is in units of 4KBytes Bytes when FrameBitrateMaxUnitMode is 1 and in units of 16KBytes if FrameBitrateMaxUnitMode is 0 4537 }; 4538 4539 //! \brief FRAMEBITRATEMAXDELTA 4540 //! \details 4541 //! This field is used to select the slice delta QP when FrameBitRateMax Is 4542 //! exceeded. It shares the same FrameBitrateMaxUnit. 4543 //! The programmable range is either 0- 512KB or 4MBB in 4544 //! FrameBitrateMaxUnit of 128 Bytes or 16KB respectively. 4545 enum FRAMEBITRATEMAXDELTA 4546 { 4547 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 4548 }; 4549 4550 //! \name Initializations 4551 4552 //! \brief Explicit member initialization function 4553 MFX_MPEG2_PIC_STATE_CMD(); 4554 4555 static const size_t dwSize = 13; 4556 static const size_t byteSize = 52; 4557 }; 4558 4559 //! 4560 //! \brief MFD_MPEG2_BSD_OBJECT 4561 //! \details 4562 //! Different from AVC and VC1, MFD_MPEG2_BSD_OBJECT command is pipelinable. 4563 //! This is for performance purpose as in MPEG2 a slice is defined as a 4564 //! group of MBs of any size that must be within a macroblock row.Slice 4565 //! header parameters are passed in as inline data and the bitstream data 4566 //! for the slice is passed in as indirect data. Of the inline data, 4567 //! slice_horizontal_position and slice_vertical_position determines the 4568 //! location within the destination picture of the first macroblock in the 4569 //! slice. The content in this command is identical to that in the 4570 //! MEDIA_OBJECT command in VLD mode described in the Media Chapter. 4571 //! 4572 struct MFD_MPEG2_BSD_OBJECT_CMD 4573 { 4574 union 4575 { 4576 //!< DWORD 0 4577 struct 4578 { 4579 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 4580 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4581 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 4582 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 4583 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 4584 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 4585 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 4586 }; 4587 uint32_t Value; 4588 } DW0; 4589 union 4590 { 4591 //!< DWORD 1 4592 struct 4593 { 4594 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 4595 }; 4596 uint32_t Value; 4597 } DW1; 4598 union 4599 { 4600 //!< DWORD 2 4601 struct 4602 { 4603 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 4604 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4605 }; 4606 uint32_t Value; 4607 } DW2; 4608 union 4609 { 4610 //!< DWORD 3 4611 struct 4612 { 4613 uint32_t FirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< First Macroblock Bit Offset 4614 uint32_t IsLastMb : __CODEGEN_BITFIELD( 3, 3) ; //!< IS_LAST_MB 4615 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 4616 uint32_t LastPicSlice : __CODEGEN_BITFIELD( 5, 5) ; //!< LAST_PIC_SLICE 4617 uint32_t SliceConcealmentTypeBit : __CODEGEN_BITFIELD( 6, 6) ; //!< SLICE_CONCEALMENT_TYPE_BIT 4618 uint32_t SliceConcealmentOverrideBit : __CODEGEN_BITFIELD( 7, 7) ; //!< SLICE_CONCEALMENT_OVERRIDE_BIT 4619 uint32_t MacroblockCount : __CODEGEN_BITFIELD( 8, 15) ; //!< Macroblock Count 4620 uint32_t SliceVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Vertical Position 4621 uint32_t SliceHorizontalPosition : __CODEGEN_BITFIELD(24, 31) ; //!< Slice Horizontal Position 4622 }; 4623 uint32_t Value; 4624 } DW3; 4625 union 4626 { 4627 //!< DWORD 4 4628 struct 4629 { 4630 uint32_t NextSliceHorizontalPosition : __CODEGEN_BITFIELD( 0, 7) ; //!< Next Slice Horizontal Position 4631 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 8, 16) ; //!< Next Slice Vertical Position 4632 uint32_t Reserved145 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 4633 uint32_t QuantizerScaleCode : __CODEGEN_BITFIELD(24, 28) ; //!< Quantizer Scale Code 4634 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 4635 }; 4636 uint32_t Value; 4637 } DW4; 4638 4639 //! \name Local enumerations 4640 4641 enum SUBOPCODE_B 4642 { 4643 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 4644 }; 4645 4646 enum SUBOPCODE_A 4647 { 4648 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 4649 }; 4650 4651 enum MEDIA_COMMAND_OPCODE 4652 { 4653 MEDIA_COMMAND_OPCODE_MPEG2DEC = 3, //!< No additional details 4654 }; 4655 4656 enum PIPELINE 4657 { 4658 PIPELINE_MFDMPEG2BSDOBJECT = 2, //!< No additional details 4659 }; 4660 4661 enum COMMAND_TYPE 4662 { 4663 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 4664 }; 4665 4666 enum IS_LAST_MB 4667 { 4668 IS_LAST_MB_UNNAMED0 = 0, //!< The current MB is not the last MB in the current Slice 4669 IS_LAST_MB_UNNAMED1 = 1, //!< The current MB is the last MB in the current Slice 4670 }; 4671 4672 //! \brief LAST_PIC_SLICE 4673 //! \details 4674 //! This bit is added to support error concealment at the end of a picture. 4675 enum LAST_PIC_SLICE 4676 { 4677 LAST_PIC_SLICE_UNNAMED0 = 0, //!< The current Slice is not the last Slice of current picture 4678 LAST_PIC_SLICE_UNNAMED1 = 1, //!< The current Slice is the last Slice of the entire picture 4679 }; 4680 4681 //! \brief SLICE_CONCEALMENT_TYPE_BIT 4682 //! \details 4683 //! This bit can be forced by driver ("Slice Concealment Override Bit") or 4684 //! set by VINunit depending on slice boundary errors. 4685 enum SLICE_CONCEALMENT_TYPE_BIT 4686 { 4687 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED0 = 0, //!< VMD will decode MBs from the bitstream until the bitstream is run-out. Then VMD will conceal the remaining MBs. 4688 SLICE_CONCEALMENT_TYPE_BIT_UNNAMED1 = 1, //!< VMD will conceal all MBs of the slice regardless of bitstream. (If driver does not force the value of this bit, VIN will set this bit depending on slice boundary error. If the next slice position of the current slice is out-of-bound or the same or earlier than the current slice start position, VIN will set this bit for the next slice) 4689 }; 4690 4691 //! \brief SLICE_CONCEALMENT_OVERRIDE_BIT 4692 //! \details 4693 //! This bit forces hardware to handle the current slice in Conceal or 4694 //! Deocde Mode. If this bit is set to one, VIN will force the current 4695 //! slice to do concealment or to decode from bitstream regardless if the 4696 //! slice boundary has errors or not. 4697 enum SLICE_CONCEALMENT_OVERRIDE_BIT 4698 { 4699 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED0 = 0, //!< Driver must program "Slice Concealment Type" to '0'. VIN will set "Slice Concealment Type" depending if the slice boundary has error or not 4700 SLICE_CONCEALMENT_OVERRIDE_BIT_UNNAMED1 = 1, //!< VIN will use driver-provided "Slice Concealment Type" regardless of valid slice boundary 4701 }; 4702 4703 //! \name Initializations 4704 4705 //! \brief Explicit member initialization function 4706 MFD_MPEG2_BSD_OBJECT_CMD(); 4707 4708 static const size_t dwSize = 5; 4709 static const size_t byteSize = 20; 4710 }; 4711 4712 //! 4713 //! \brief MFD_IT_OBJECT_MPEG2_INLINE_DATA 4714 //! \details 4715 //! The content in this command is similar to that in the MEDIA_OBJECT 4716 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4717 //! command corresponds to the processing of one macroblock. Macroblock 4718 //! parameters are passed in as inline data and the non-zero DCT coefficient 4719 //! data for the macroblock is passed in as indirect data. Inline data 4720 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4721 //! 4722 struct MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD 4723 { 4724 union 4725 { 4726 //!< DWORD 0 4727 struct 4728 { 4729 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 4730 uint32_t Lastmbinrow : __CODEGEN_BITFIELD( 3, 3) ; //!< LastMBInRow 4731 uint32_t Reserved4 : __CODEGEN_BITFIELD( 4, 5) ; //!< Reserved 4732 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD( 6, 11) ; //!< Coded Block Pattern 4733 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 4734 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16) ; //!< MACROBLOCK_INTRA_TYPE 4735 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17) ; //!< MACROBLOCK_MOTION_FORWARD 4736 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18) ; //!< MACROBLOCK_MOTION_BACKWARD 4737 uint32_t Reserved19 : __CODEGEN_BITFIELD(19, 20) ; //!< Reserved 4738 uint32_t DctType : __CODEGEN_BITFIELD(21, 21) ; //!< DCT_TYPE 4739 uint32_t Reserved22 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 4740 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25) ; //!< Motion Type 4741 uint32_t Reserved26 : __CODEGEN_BITFIELD(26, 27) ; //!< Reserved 4742 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31) ; //!< MOTION_VERTICAL_FIELD_SELECT 4743 }; 4744 uint32_t Value; 4745 } DW0; 4746 union 4747 { 4748 //!< DWORD 1 4749 struct 4750 { 4751 uint32_t Horzorigin : __CODEGEN_BITFIELD( 0, 7) ; //!< HorzOrigin 4752 uint32_t Vertorigin : __CODEGEN_BITFIELD( 8, 15) ; //!< VertOrigin 4753 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4754 }; 4755 uint32_t Value; 4756 } DW1; 4757 union 4758 { 4759 //!< DWORD 2 4760 struct 4761 { 4762 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 0, Forward, Horizontal Component 4763 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 0, Forward, Vertical Component 4764 }; 4765 uint32_t Value; 4766 } DW2; 4767 union 4768 { 4769 //!< DWORD 3 4770 struct 4771 { 4772 uint32_t MotionVectorsField0BackwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 0, Backward, Horizontal Component 4773 uint32_t MotionVectorsField0BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 0, Backward, Vertical Component 4774 }; 4775 uint32_t Value; 4776 } DW3; 4777 union 4778 { 4779 //!< DWORD 4 4780 struct 4781 { 4782 uint32_t MotionVectorsField1ForwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 1, Forward, Horizontal Component 4783 uint32_t MotionVectorsField1ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 1, Forward, Vertical Component 4784 }; 4785 uint32_t Value; 4786 } DW4; 4787 union 4788 { 4789 //!< DWORD 5 4790 struct 4791 { 4792 uint32_t MotionVectorsField1BackwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 1, Backward, Horizontal Component 4793 uint32_t MotionVectorsField1BackwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 1, Backward, Vertical Component 4794 }; 4795 uint32_t Value; 4796 } DW5; 4797 4798 //! \name Local enumerations 4799 4800 //! \brief MACROBLOCK_INTRA_TYPE 4801 //! \details 4802 //! This field specifies if the current macroblock is intra-coded. When set, 4803 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 4804 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 4805 enum MACROBLOCK_INTRA_TYPE 4806 { 4807 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 4808 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 4809 }; 4810 4811 //! \brief MACROBLOCK_MOTION_FORWARD 4812 //! \details 4813 //! This field specifies if the forward motion vector is active. See ISO/IEC 4814 //! 13818-2 Tables B-2 through B-4. 4815 enum MACROBLOCK_MOTION_FORWARD 4816 { 4817 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 4818 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 4819 }; 4820 4821 //! \brief MACROBLOCK_MOTION_BACKWARD 4822 //! \details 4823 //! This field specifies if the backward motion vector is active. See 4824 //! ISO/IEC 13818-2 Tables B-2 through B-4. 4825 enum MACROBLOCK_MOTION_BACKWARD 4826 { 4827 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 4828 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 4829 }; 4830 4831 //! \brief DCT_TYPE 4832 //! \details 4833 //! This field specifies the DCT type of the current macroblock. The kernel 4834 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 4835 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 4836 //! (no coded blocks present). 4837 enum DCT_TYPE 4838 { 4839 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 4840 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 4841 }; 4842 4843 //! \brief MOTION_VERTICAL_FIELD_SELECT 4844 //! \details 4845 //! A bit-wise representation of a long [2][2] array as defined in 4846 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 4847 //! <table> 4848 //! <thead> 4849 //! 4850 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 4851 //! Index</td></tr> 4852 //! </thead> 4853 //! <tbody> 4854 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 4855 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 4856 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 4857 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 4858 //! </tbody> 4859 //! </table> 4860 enum MOTION_VERTICAL_FIELD_SELECT 4861 { 4862 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 4863 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 4864 }; 4865 4866 //! \name Initializations 4867 4868 //! \brief Explicit member initialization function 4869 MFD_IT_OBJECT_MPEG2_INLINE_DATA_CMD(); 4870 4871 static const size_t dwSize = 6; 4872 static const size_t byteSize = 24; 4873 }; 4874 4875 //! 4876 //! \brief MFD_IT_OBJECT_VC1_INLINE_DATA 4877 //! \details 4878 //! The content in this command is similar to that in the MEDIA_OBJECT 4879 //! command in IS mode described in the Media Chapter. Each MFD_IT_OBJECT 4880 //! command corresponds to the processing of one macroblock. Macroblock 4881 //! parameters are passed in as inline data and the non-zero DCT coefficient 4882 //! data for the macroblock is passed in as indirect data. Inline data 4883 //! starts at dword 7 of MFD_IT_OBJECT command. There are 7 dwords total. 4884 //! 4885 struct MFD_IT_OBJECT_VC1_INLINE_DATA_CMD 4886 { 4887 union 4888 { 4889 //!< DWORD 0 4890 struct 4891 { 4892 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 4893 uint32_t Lastmbinrow : __CODEGEN_BITFIELD( 3, 3) ; //!< LastMBInRow 4894 uint32_t LastRowFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< Last Row Flag 4895 uint32_t ChromaIntraFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< Chroma Intra Flag 4896 uint32_t CodedBlockPattern : __CODEGEN_BITFIELD( 6, 11) ; //!< Coded Block Pattern 4897 uint32_t LumaIntra8X8Flag : __CODEGEN_BITFIELD(12, 15) ; //!< Luma Intra 8x8 Flag 4898 uint32_t MacroblockIntraType : __CODEGEN_BITFIELD(16, 16) ; //!< MACROBLOCK_INTRA_TYPE 4899 uint32_t MacroblockMotionForward : __CODEGEN_BITFIELD(17, 17) ; //!< MACROBLOCK_MOTION_FORWARD 4900 uint32_t MacroblockMotionBackward : __CODEGEN_BITFIELD(18, 18) ; //!< MACROBLOCK_MOTION_BACKWARD 4901 uint32_t Motion4Mv : __CODEGEN_BITFIELD(19, 19) ; //!< MOTION4MV 4902 uint32_t Overlaptransform : __CODEGEN_BITFIELD(20, 20) ; //!< OVERLAPTRANSFORM 4903 uint32_t DctType : __CODEGEN_BITFIELD(21, 21) ; //!< DCT_TYPE 4904 uint32_t Mvswitch : __CODEGEN_BITFIELD(22, 22) ; //!< MvSwitch 4905 uint32_t Reserved23 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 4906 uint32_t MotionType : __CODEGEN_BITFIELD(24, 25) ; //!< Motion Type 4907 uint32_t Mvfieldselectchroma : __CODEGEN_BITFIELD(26, 26) ; //!< MvFieldSelectChroma 4908 uint32_t Reserved27 : __CODEGEN_BITFIELD(27, 27) ; //!< Reserved 4909 uint32_t MotionVerticalFieldSelect : __CODEGEN_BITFIELD(28, 31) ; //!< MOTION_VERTICAL_FIELD_SELECT 4910 }; 4911 uint32_t Value; 4912 } DW0; 4913 union 4914 { 4915 //!< DWORD 1 4916 struct 4917 { 4918 uint32_t Horzorigin : __CODEGEN_BITFIELD( 0, 7) ; //!< HorzOrigin 4919 uint32_t Vertorigin : __CODEGEN_BITFIELD( 8, 15) ; //!< VertOrigin 4920 uint32_t Osedgemaskluma : __CODEGEN_BITFIELD(16, 23) ; //!< OSEdgeMaskLuma 4921 uint32_t Osedgemaskchroma : __CODEGEN_BITFIELD(24, 25) ; //!< OSEdgeMaskChroma 4922 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 4923 }; 4924 uint32_t Value; 4925 } DW1; 4926 union 4927 { 4928 //!< DWORD 2 4929 struct 4930 { 4931 uint32_t MotionVectorsField0ForwardHorizontalComponent : __CODEGEN_BITFIELD( 0, 15) ; //!< Motion Vectors - Field 0, Forward, Horizontal Component 4932 uint32_t MotionVectorsField0ForwardVerticalComponent : __CODEGEN_BITFIELD(16, 31) ; //!< Motion Vectors - Field 0, Forward, Vertical Component 4933 }; 4934 uint32_t Value; 4935 } DW2; 4936 union 4937 { 4938 //!< DWORD 3 4939 struct 4940 { 4941 uint32_t Motionvector1 ; //!< MotionVector1 4942 }; 4943 uint32_t Value; 4944 } DW3; 4945 union 4946 { 4947 //!< DWORD 4 4948 struct 4949 { 4950 uint32_t Motionvector2 ; //!< MotionVector2 4951 }; 4952 uint32_t Value; 4953 } DW4; 4954 union 4955 { 4956 //!< DWORD 5 4957 struct 4958 { 4959 uint32_t Motionvector3 ; //!< MotionVector3 4960 }; 4961 uint32_t Value; 4962 } DW5; 4963 union 4964 { 4965 //!< DWORD 6 4966 struct 4967 { 4968 uint32_t Motionvectorchroma ; //!< MotionVectorChroma 4969 }; 4970 uint32_t Value; 4971 } DW6; 4972 union 4973 { 4974 //!< DWORD 7 4975 struct 4976 { 4977 uint32_t SubblockCodeForY0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Subblock Code for Y0 4978 uint32_t SubblockCodeForY1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Subblock Code for Y1 4979 uint32_t SubblockCodeForY2 : __CODEGEN_BITFIELD(16, 23) ; //!< Subblock Code for Y2 4980 uint32_t SubblockCodeForY3 : __CODEGEN_BITFIELD(24, 31) ; //!< Subblock Code for Y3 4981 }; 4982 uint32_t Value; 4983 } DW7; 4984 union 4985 { 4986 //!< DWORD 8 4987 struct 4988 { 4989 uint32_t SubblockCodeForCb : __CODEGEN_BITFIELD( 0, 7) ; //!< Subblock Code for Cb 4990 uint32_t SubblockCodeForCr : __CODEGEN_BITFIELD( 8, 15) ; //!< Subblock Code for Cr 4991 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 4992 }; 4993 uint32_t Value; 4994 } DW8; 4995 union 4996 { 4997 //!< DWORD 9 4998 struct 4999 { 5000 uint32_t IldbControlDataForBlockY0 : __CODEGEN_BITFIELD( 0, 7) ; //!< ILDB control data for block Y0 5001 uint32_t IldbControlDataForBlockY1 : __CODEGEN_BITFIELD( 8, 15) ; //!< ILDB control data for block Y1 5002 uint32_t IldbControlDataForBlockY2 : __CODEGEN_BITFIELD(16, 23) ; //!< ILDB control data for block Y2 5003 uint32_t IldbControlDataForBlockY3 : __CODEGEN_BITFIELD(24, 31) ; //!< ILDB control data for block Y3 5004 }; 5005 uint32_t Value; 5006 } DW9; 5007 union 5008 { 5009 //!< DWORD 10 5010 struct 5011 { 5012 uint32_t IldbControlDataForCbBlock : __CODEGEN_BITFIELD( 0, 7) ; //!< ILDB control data for Cb block 5013 uint32_t IldbControlDataForCrBlock : __CODEGEN_BITFIELD( 8, 15) ; //!< ILDB control data for Cr block 5014 uint32_t Reserved336 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 5015 }; 5016 uint32_t Value; 5017 } DW10; 5018 5019 //! \name Local enumerations 5020 5021 //! \brief MACROBLOCK_INTRA_TYPE 5022 //! \details 5023 //! This field specifies if the current macroblock is intra-coded. When set, 5024 //! Coded Block Pattern is ignored and no prediction is performed (i.e., no 5025 //! motion vectors are used). See ISO/IEC 13818-2 Tables B-2 through B-4. 5026 enum MACROBLOCK_INTRA_TYPE 5027 { 5028 MACROBLOCK_INTRA_TYPE_NON_INTRAMACROBLOCK = 0, //!< No additional details 5029 MACROBLOCK_INTRA_TYPE_INTRAMACROBLOCK = 1, //!< No additional details 5030 }; 5031 5032 //! \brief MACROBLOCK_MOTION_FORWARD 5033 //! \details 5034 //! This field specifies if the forward motion vector is active. See ISO/IEC 5035 //! 13818-2 Tables B-2 through B-4. 5036 enum MACROBLOCK_MOTION_FORWARD 5037 { 5038 MACROBLOCK_MOTION_FORWARD_NOFORWARDMOTIONVECTOR = 0, //!< No additional details 5039 MACROBLOCK_MOTION_FORWARD_USEFORWARDMOTIONVECTORS = 1, //!< No additional details 5040 }; 5041 5042 //! \brief MACROBLOCK_MOTION_BACKWARD 5043 //! \details 5044 //! This field specifies if the backward motion vector is active. See 5045 //! ISO/IEC 13818-2 Tables B-2 through B-4. 5046 enum MACROBLOCK_MOTION_BACKWARD 5047 { 5048 MACROBLOCK_MOTION_BACKWARD_NOBACKWARDMOTIONVECTOR = 0, //!< No additional details 5049 MACROBLOCK_MOTION_BACKWARD_USEBACKWARDMOTIONVECTORS = 1, //!< No additional details 5050 }; 5051 5052 enum MOTION4MV 5053 { 5054 MOTION4MV_1MV_MODE = 0, //!< No additional details 5055 MOTION4MV_4MV_MODE = 1, //!< No additional details 5056 }; 5057 5058 //! \brief OVERLAPTRANSFORM 5059 //! \details 5060 //! Was Overlap Transform - H261 Loop Filter 5061 enum OVERLAPTRANSFORM 5062 { 5063 OVERLAPTRANSFORM_NOOVERLAPSMOOTHINGFILTER = 0, //!< This field indicates whether overlap smoothing filter should be performed on I-block boundaries. 5064 OVERLAPTRANSFORM_OVERLAPSMOOTHINGFILTERPERFORMED = 1, //!< Macroblock is field DCT coded 5065 }; 5066 5067 //! \brief DCT_TYPE 5068 //! \details 5069 //! This field specifies the DCT type of the current macroblock. The kernel 5070 //! should ignore this field when processing Cb/Cr data. See ISO/IEC 13818-2 5071 //! #167;6.3.17.1. This field is zero if Coded Block Pattern is also zero 5072 //! (no coded blocks present). 5073 enum DCT_TYPE 5074 { 5075 DCT_TYPE_MCFRAMEDCT = 0, //!< Macroblock is frame DCT coded 5076 DCT_TYPE_MCFIELDDCT = 1, //!< Macroblock is field DCT coded 5077 }; 5078 5079 //! \brief MOTION_VERTICAL_FIELD_SELECT 5080 //! \details 5081 //! A bit-wise representation of a long [2][2] array as defined in 5082 //! #167;6.3.17.2 of the ISO/IEC 13818-2 (see also #167;7.6.4). 5083 //! <table> 5084 //! <thead> 5085 //! 5086 //! <tr><td>Bit</td><td>MVector[r]</td><td>MVector[s]</td><td>MotionVerticalFieldSelect 5087 //! Index</td></tr> 5088 //! </thead> 5089 //! <tbody> 5090 //! <tr><td>28</td><td>0</td><td>0</td><td>0</td></tr> 5091 //! <tr><td>29</td><td>0</td><td>1</td><td>1</td></tr> 5092 //! <tr><td>30</td><td>1</td><td>0</td><td>2</td></tr> 5093 //! <tr><td>31</td><td>1</td><td>1</td><td>3</td></tr> 5094 //! </tbody> 5095 //! </table> 5096 enum MOTION_VERTICAL_FIELD_SELECT 5097 { 5098 MOTION_VERTICAL_FIELD_SELECT_TOPFIELD = 0, //!< The prediction is taken from the top reference field. 5099 MOTION_VERTICAL_FIELD_SELECT_BOTTOMFIELD = 1, //!< The prediction is taken from the bottom reference field. 5100 }; 5101 5102 //! \name Initializations 5103 5104 //! \brief Explicit member initialization function 5105 MFD_IT_OBJECT_VC1_INLINE_DATA_CMD(); 5106 5107 static const size_t dwSize = 11; 5108 static const size_t byteSize = 44; 5109 }; 5110 5111 //! 5112 //! \brief MFD_IT_OBJECT 5113 //! \details 5114 //! All weight mode (default and implicit) are mapped to explicit mode. But 5115 //! the weights come in either as explicit or implicit. 5116 //! 5117 struct MFD_IT_OBJECT_CMD 5118 { 5119 union 5120 { 5121 //!< DWORD 0 5122 struct 5123 { 5124 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5125 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5126 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5127 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5128 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5129 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5130 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5131 }; 5132 uint32_t Value; 5133 } DW0; 5134 union 5135 { 5136 //!< DWORD 1 5137 struct 5138 { 5139 uint32_t IndirectItMvDataLength : __CODEGEN_BITFIELD( 0, 9) ; //!< Indirect IT-MV Data Length 5140 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 5141 }; 5142 uint32_t Value; 5143 } DW1; 5144 union 5145 { 5146 //!< DWORD 2 5147 struct 5148 { 5149 uint32_t IndirectItMvDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-MV Data Start Address Offset 5150 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5151 }; 5152 uint32_t Value; 5153 } DW2; 5154 union 5155 { 5156 //!< DWORD 3 5157 struct 5158 { 5159 uint32_t IndirectItCoeffDataLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Indirect IT-COEFF Data Length 5160 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 5161 }; 5162 uint32_t Value; 5163 } DW3; 5164 union 5165 { 5166 //!< DWORD 4 5167 struct 5168 { 5169 uint32_t IndirectItCoeffDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-COEFF Data Start Address Offset 5170 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5171 }; 5172 uint32_t Value; 5173 } DW4; 5174 union 5175 { 5176 //!< DWORD 5 5177 struct 5178 { 5179 uint32_t IndirectItDblkControlDataLength : __CODEGEN_BITFIELD( 0, 5) ; //!< Indirect IT-DBLK Control Data Length 5180 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 5181 }; 5182 uint32_t Value; 5183 } DW5; 5184 union 5185 { 5186 //!< DWORD 6 5187 struct 5188 { 5189 uint32_t IndirectItDblkControlDataStartAddressOffset : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect IT-DBLK Control Data Start Address Offset 5190 uint32_t Reserved221 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5191 }; 5192 uint32_t Value; 5193 } DW6; 5194 5195 //! \name Local enumerations 5196 5197 enum SUBOPCODE_B 5198 { 5199 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 5200 }; 5201 5202 enum SUBOPCODE_A 5203 { 5204 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5205 }; 5206 5207 enum MEDIA_COMMAND_OPCODE 5208 { 5209 MEDIA_COMMAND_OPCODE_MFXCOMMONDEC = 0, //!< No additional details 5210 }; 5211 5212 enum PIPELINE 5213 { 5214 PIPELINE_MFDITOBJECT = 2, //!< No additional details 5215 }; 5216 5217 enum COMMAND_TYPE 5218 { 5219 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5220 }; 5221 5222 //! \name Initializations 5223 5224 //! \brief Explicit member initialization function 5225 MFD_IT_OBJECT_CMD(); 5226 5227 static const size_t dwSize = 7; 5228 static const size_t byteSize = 28; 5229 }; 5230 5231 //! 5232 //! \brief MFC_MPEG2_SLICEGROUP_STATE 5233 //! \details 5234 //! This is a slice group level command and can be issued multiple times 5235 //! within a picture that is comprised of multiple slice groups. The same 5236 //! command is used for AVC encoder (PAK mode) and decoder (VLD and IT 5237 //! modes). 5238 //! 5239 struct MFC_MPEG2_SLICEGROUP_STATE_CMD 5240 { 5241 union 5242 { 5243 //!< DWORD 0 5244 struct 5245 { 5246 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5247 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5248 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5249 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5250 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5251 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5252 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5253 }; 5254 uint32_t Value; 5255 } DW0; 5256 union 5257 { 5258 //!< DWORD 1 5259 struct 5260 { 5261 uint32_t Streamid10EncoderOnly : __CODEGEN_BITFIELD( 0, 1) ; //!< StreamID[1:0] (Encoder-only) 5262 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved 5263 uint32_t Sliceid30EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< SliceID[3:0] (Encoder-only) 5264 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 11) ; //!< Reserved 5265 uint32_t Intrasliceflag : __CODEGEN_BITFIELD(12, 12) ; //!< IntraSliceFlag 5266 uint32_t Intraslice : __CODEGEN_BITFIELD(13, 13) ; //!< IntraSlice 5267 uint32_t Firstslicehdrdisabled : __CODEGEN_BITFIELD(14, 14) ; //!< FirstSliceHdrDisabled 5268 uint32_t TailpresentflagTailInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(15, 15) ; //!< TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5269 uint32_t SlicedataPresentflagSlicedataInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(16, 16) ; //!< SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5270 uint32_t HeaderpresentflagHeaderInsertionPresentInBitstreamEncoderOnly : __CODEGEN_BITFIELD(17, 17) ; //!< HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5271 uint32_t BitstreamoutputflagCompressedBitstreamOutputDisableFlagEncoderOnly : __CODEGEN_BITFIELD(18, 18) ; //!< BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5272 uint32_t Islastslicegrp : __CODEGEN_BITFIELD(19, 19) ; //!< IsLastSliceGrp 5273 uint32_t SkipconvdisabledMbTypeSkipConversionDisableEncoderOnly : __CODEGEN_BITFIELD(20, 20) ; //!< SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5274 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 5275 uint32_t RatectrlpanictypeRcPanicTypeEncoderOnly : __CODEGEN_BITFIELD(22, 22) ; //!< RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5276 uint32_t RatectrlpanicflagRcPanicEnableEncoderOnly : __CODEGEN_BITFIELD(23, 23) ; //!< RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5277 uint32_t MbratectrlparamRcStableToleranceEncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< MbRateCtrlParam- RC Stable Tolerance (Encoder-only) 5278 uint32_t MbratectrlmodeRcTriggleModeEncoderOnly : __CODEGEN_BITFIELD(28, 29) ; //!< MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5279 uint32_t MbratectrlresetResetratecontrolcounterEncoderOnly : __CODEGEN_BITFIELD(30, 30) ; //!< MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5280 uint32_t MbratectrlflagRatecontrolcounterenableEncoderOnly : __CODEGEN_BITFIELD(31, 31) ; //!< MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5281 }; 5282 uint32_t Value; 5283 } DW1; 5284 union 5285 { 5286 //!< DWORD 2 5287 struct 5288 { 5289 uint32_t FirstmbxcntAlsoCurrstarthorzpos : __CODEGEN_BITFIELD( 0, 7) ; //!< FirstMbXcnt - also CurrStartHorzPos 5290 uint32_t FirstmbycntAlsoCurrstartvertpos : __CODEGEN_BITFIELD( 8, 15) ; //!< FirstMbYcnt - also CurrStartVertPos 5291 uint32_t NextsgmbxcntAlsoNextstarthorzpos : __CODEGEN_BITFIELD(16, 23) ; //!< NextSgMbXcnt - also NextStartHorzPos 5292 uint32_t NextsgmbycntAlsoNextstartvertpos : __CODEGEN_BITFIELD(24, 31) ; //!< NextSgMbYcnt - also NextStartVertPos 5293 }; 5294 uint32_t Value; 5295 } DW2; 5296 union 5297 { 5298 //!< DWORD 3 5299 struct 5300 { 5301 uint32_t Slicegroupqp : __CODEGEN_BITFIELD( 0, 5) ; //!< SliceGroupQp 5302 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5303 uint32_t Slicegroupskip : __CODEGEN_BITFIELD( 8, 8) ; //!< SliceGroupSkip 5304 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 5305 }; 5306 uint32_t Value; 5307 } DW3; 5308 union 5309 { 5310 //!< DWORD 4 5311 struct 5312 { 5313 uint32_t BitstreamoffsetIndirectPakBseDataStartAddressWrite : __CODEGEN_BITFIELD( 0, 28) ; //!< BitstreamOffset - Indirect PAK-BSE Data Start Address (Write) 5314 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 5315 }; 5316 uint32_t Value; 5317 } DW4; 5318 union 5319 { 5320 //!< DWORD 5 5321 struct 5322 { 5323 uint32_t GrowparamGrowInitEncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< GrowParam - Grow Init (Encoder-only) 5324 uint32_t GrowparamGrowResistanceEncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< GrowParam - Grow Resistance (Encoder-only) 5325 uint32_t ShrinkaramShrinkInitEncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< Shrinkaram - Shrink Init (Encoder-only) 5326 uint32_t ShrinkparamShrinkResistanceEncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< ShrinkParam - Shrink Resistance (Encoder-only) 5327 uint32_t MaxqpposmodifierMagnitudeOfQpMaxPositiveModifierEncoderOnly : __CODEGEN_BITFIELD(16, 23) ; //!< MaxQpPosModifier - Magnitude of QP Max Positive Modifier (Encoder-only) 5328 uint32_t MaxqpnegmodifierMagnitudeOfQpMaxNegativeModifierEncoderOnly : __CODEGEN_BITFIELD(24, 31) ; //!< MaxQpNegModifier - Magnitude of QP Max Negative Modifier (Encoder-only) 5329 }; 5330 uint32_t Value; 5331 } DW5; 5332 union 5333 { 5334 //!< DWORD 6 5335 struct 5336 { 5337 uint32_t CorrectpointsCorrect1EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CorrectPoints - Correct 1 (Encoder-only) 5338 uint32_t CorrectpointsCorrect2EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CorrectPoints - Correct 2 (Encoder-only) 5339 uint32_t CorrectpointsCorrect3EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CorrectPoints - Correct 3 (Encoder-only) 5340 uint32_t CorrectpointsCorrect4EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CorrectPoints - Correct 4 (Encoder-only) 5341 uint32_t CorrectpointsCorrect5EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CorrectPoints - Correct 5 (Encoder-only) 5342 uint32_t CorrectpointsCorrect6EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CorrectPoints - Correct 6 (Encoder-only) 5343 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5344 }; 5345 uint32_t Value; 5346 } DW6; 5347 union 5348 { 5349 //!< DWORD 7 5350 struct 5351 { 5352 uint32_t Cv0ClampValue0EncoderOnly : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 (Encoder-only) 5353 uint32_t Cv1ClampValue1EncoderOnly : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 - Clamp Value 1 (Encoder-only) 5354 uint32_t Cv2ClampValue2EncoderOnly : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 - Clamp Value 2 (Encoder-only) 5355 uint32_t Cv3ClampValue3EncoderOnly : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 - Clamp Value 3 (Encoder-only) 5356 uint32_t Cv4ClampValue4EncoderOnly : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 - Clamp Value 4 (Encoder-only) 5357 uint32_t Cv5ClampValue5EncoderOnly : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 - Clamp Value 5 (Encoder-only) 5358 uint32_t Cv6ClampValue6EncoderOnly : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 - Clamp Value 6 (Encoder-only) 5359 uint32_t Cv7ClampValue7EncoderOnly : __CODEGEN_BITFIELD(28, 31) ; //!< CV7 - Clamp Value 7 (Encoder-only) 5360 }; 5361 uint32_t Value; 5362 } DW7; 5363 5364 //! \name Local enumerations 5365 5366 enum SUBOPCODE_B 5367 { 5368 SUBOPCODE_B_MEDIA = 3, //!< No additional details 5369 }; 5370 5371 enum SUBOPCODE_A 5372 { 5373 SUBOPCODE_A_MEDIA = 2, //!< No additional details 5374 }; 5375 5376 enum MEDIA_COMMAND_OPCODE 5377 { 5378 MEDIA_COMMAND_OPCODE_MPEG2 = 3, //!< No additional details 5379 }; 5380 5381 enum PIPELINE 5382 { 5383 PIPELINE_MFXMPEG2SLICEGROUPSTATE = 2, //!< No additional details 5384 }; 5385 5386 enum COMMAND_TYPE 5387 { 5388 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5389 }; 5390 5391 enum TAILPRESENTFLAG__TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5392 { 5393 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED0 = 0, //!< no tail insertion into the output bitstream buffer, after the current slice encoded bits 5394 TAILPRESENTFLAG_TAIL_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_UNNAMED1 = 1, //!< tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits. 5395 }; 5396 5397 enum SLICEDATA_PRESENTFLAG__SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5398 { 5399 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no Slice Data insertion into the output bitstream buffer 5400 SLICEDATA_PRESENTFLAG_SLICEDATA_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< Slice Data insertion into the output bitstream buffer is present. 5401 }; 5402 5403 enum HEADERPRESENTFLAG__HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY 5404 { 5405 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_DISABLE = 0, //!< no header insertion into the output bitstream buffer, in front of the current slice encoded bits 5406 HEADERPRESENTFLAG_HEADER_INSERTION_PRESENT_IN_BITSTREAM_ENCODER_ONLY_ENABLE = 1, //!< header insertion into the output bitstream buffer is present, and is in front of the current slice encoded bits. 5407 }; 5408 5409 enum BITSTREAMOUTPUTFLAG__COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY 5410 { 5411 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_ENABLE = 0, //!< enable the writing of the output compressed bitstream 5412 BITSTREAMOUTPUTFLAG_COMPRESSED_BITSTREAM_OUTPUT_DISABLE_FLAG_ENCODER_ONLY_DISABLE = 1, //!< disable the writing of the output compressed bitstream 5413 }; 5414 5415 //! \brief SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5416 //! \details 5417 //! This field is only valid for a P or B slice. It must be zero for other 5418 //! slice types. Rules are provided in Section 2.3.3.1.6 5419 enum SKIPCONVDISABLED__MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY 5420 { 5421 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_ENABLE = 0, //!< Enable skip type conversion 5422 SKIPCONVDISABLED_MB_TYPE_SKIP_CONVERSION_DISABLE_ENCODER_ONLY_DISABLE = 1, //!< Disable skip type conversion 5423 }; 5424 5425 //! \brief RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5426 //! \details 5427 //! This field selects between two RC Panic methods. If it is set to 0, in 5428 //! panic mode, the macroblock QP is maxed out, setting to requested QP + 5429 //! QP_max_pos_mod. If it is set to 1, for an intra macroblock, AC CBPs are 5430 //! set to zero (note that DC CBPs are not modified). For inter macroblocks, 5431 //! AC and DC CBPs are forced to zero. 5432 enum RATECTRLPANICTYPE__RC_PANIC_TYPE_ENCODER_ONLY 5433 { 5434 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED0 = 0, //!< QP Panic 5435 RATECTRLPANICTYPE_RC_PANIC_TYPE_ENCODER_ONLY_UNNAMED1 = 1, //!< CBP Panic 5436 }; 5437 5438 //! \brief RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5439 //! \details 5440 //! If this field is set to 1, RC enters panic mode 5441 //! when sum_act > sum_max. RC Panic Type field controls what type 5442 //! of panic 5443 //! behavior is invoked. 5444 enum RATECTRLPANICFLAG__RC_PANIC_ENABLE_ENCODER_ONLY 5445 { 5446 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5447 RATECTRLPANICFLAG_RC_PANIC_ENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5448 }; 5449 5450 enum MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY 5451 { 5452 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED0 = 0, //!< Always Rate Control, whereas RC becomes activeif sum_act > sum_target or sum_act < sum_target 5453 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED1 = 1, //!< Gentle Rate Control, whereas RC becomes activeif sum_act > upper_midpt or sum_act < lower_midpt 5454 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED2 = 2, //!< Loose Rate Control, whereas RC becomes activeif sum_act > sum_max or sum_act < sum_min 5455 MBRATECTRLMODE_RC_TRIGGLE_MODE_ENCODER_ONLY_UNNAMED3 = 3, //!< Reserved 5456 }; 5457 5458 //! \brief MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5459 //! \details 5460 //! To reset the bit allocation accumulation counter to 0 to restart the 5461 //! rate control. 5462 enum MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY 5463 { 5464 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_DISABLE = 0, //!< Not reset 5465 MBRATECTRLRESET_RESETRATECONTROLCOUNTER_ENCODER_ONLY_ENABLE = 1, //!< reset 5466 }; 5467 5468 //! \brief MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5469 //! \details 5470 //! To enable the accumulation of bit allocation for rate controlThis field 5471 //! enables hardware Rate Control logic. The rest of the RC control fields 5472 //! are only valid when this field is set to 1. Otherwise, hardware ignores 5473 //! these fields.Note: To reset MB level rate control (QRC), we need to set 5474 //! both bits MbRateCtrlFlag and MbRateCtrlReset to 1 in the new slice 5475 enum MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY 5476 { 5477 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_DISABLE = 0, //!< No additional details 5478 MBRATECTRLFLAG_RATECONTROLCOUNTERENABLE_ENCODER_ONLY_ENABLE = 1, //!< No additional details 5479 }; 5480 5481 //! \name Initializations 5482 5483 //! \brief Explicit member initialization function 5484 MFC_MPEG2_SLICEGROUP_STATE_CMD(); 5485 5486 static const size_t dwSize = 8; 5487 static const size_t byteSize = 32; 5488 }; 5489 5490 //! 5491 //! \brief MFX_VC1_PRED_PIPE_STATE 5492 //! \details 5493 //! This command is used to set the operating states of the MFD Engine 5494 //! beyond the BSD unit. It is used with both VC1 Long and Short 5495 //! format.Driver is responsible to take the intensity compensation enable 5496 //! signal, the LumScale and the LumShift provided from the VC1 5497 //! interface, and maintain a history of these values for reference 5498 //! pictures. Together with these three parameters specified for the current 5499 //! picture being decoded, driver will derive and supply the above sets of 5500 //! LumScaleX, LumShiftX and intensity compensation enable (single or 5501 //! double, forward or backward) signals. H/W is responsible to take these 5502 //! state values, and use them to build the lookup table (including the 5503 //! derivation of iScale and iShift) for remapping the reference frame 5504 //! pixels, as well as perfoming the actual pixel remapping 5505 //! calculations/process. 5506 //! 5507 struct MFX_VC1_PRED_PIPE_STATE_CMD 5508 { 5509 union 5510 { 5511 //!< DWORD 0 5512 struct 5513 { 5514 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5515 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5516 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5517 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5518 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5519 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5520 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5521 }; 5522 uint32_t Value; 5523 } DW0; 5524 union 5525 { 5526 //!< DWORD 1 5527 struct 5528 { 5529 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 3) ; //!< Reserved 5530 uint32_t ReferenceFrameBoundaryReplicationMode : __CODEGEN_BITFIELD( 4, 7) ; //!< Reference Frame Boundary Replication Mode 5531 uint32_t VinIntensitycompSingleBwden : __CODEGEN_BITFIELD( 8, 9) ; //!< vin_intensitycomp_Single_BWDen 5532 uint32_t VinIntensitycompSingleFwden : __CODEGEN_BITFIELD(10, 11) ; //!< vin_intensitycomp_Single_FWDen 5533 uint32_t VinIntensitycompDoubleBwden : __CODEGEN_BITFIELD(12, 13) ; //!< vin_intensitycomp_Double_BWDen 5534 uint32_t VinIntensitycompDoubleFwden : __CODEGEN_BITFIELD(14, 15) ; //!< vin_intensitycomp_Double_FWDen 5535 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 5536 }; 5537 uint32_t Value; 5538 } DW1; 5539 union 5540 { 5541 //!< DWORD 2 5542 struct 5543 { 5544 uint32_t Lumscale1SingleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - FWD 5545 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5546 uint32_t Lumscale2SingleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - FWD 5547 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5548 uint32_t Lumshift1SingleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - FWD 5549 uint32_t Reserved86 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5550 uint32_t Lumshift2SingleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - FWD 5551 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5552 }; 5553 uint32_t Value; 5554 } DW2; 5555 union 5556 { 5557 //!< DWORD 3 5558 struct 5559 { 5560 uint32_t Lumscale1DoubleFwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - FWD 5561 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5562 uint32_t Lumscale2DoubleFwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - FWD 5563 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5564 uint32_t Lumshift1DoubleFwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -FWD 5565 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5566 uint32_t Lumshift2DoubleFwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - FWD 5567 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5568 }; 5569 uint32_t Value; 5570 } DW3; 5571 union 5572 { 5573 //!< DWORD 4 5574 struct 5575 { 5576 uint32_t Lumscale1SingleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - Single - BWD 5577 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5578 uint32_t Lumscale2SingleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - single - BWD 5579 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5580 uint32_t Lumshift1SingleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - single - BWD 5581 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5582 uint32_t Lumshift2SingleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- single - BWD 5583 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5584 }; 5585 uint32_t Value; 5586 } DW4; 5587 union 5588 { 5589 //!< DWORD 5 5590 struct 5591 { 5592 uint32_t Lumscale1DoubleBwd : __CODEGEN_BITFIELD( 0, 5) ; //!< LumScale1 - double - BWD 5593 uint32_t Reserved166 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 5594 uint32_t Lumscale2DoubleBwd : __CODEGEN_BITFIELD( 8, 13) ; //!< LumScale2 - double - BWD 5595 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5596 uint32_t Lumshift1DoubleBwd : __CODEGEN_BITFIELD(16, 21) ; //!< LumShift1 - double -BWD 5597 uint32_t Reserved182 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 5598 uint32_t Lumshift2DoubleBwd : __CODEGEN_BITFIELD(24, 29) ; //!< LumShift2- double - BWD 5599 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5600 }; 5601 uint32_t Value; 5602 } DW5; 5603 5604 //! \name Local enumerations 5605 5606 enum SUBOPCODE_B 5607 { 5608 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5609 }; 5610 5611 enum SUBOPCODE_A 5612 { 5613 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 5614 }; 5615 5616 enum MEDIA_COMMAND_OPCODE 5617 { 5618 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 5619 }; 5620 5621 enum PIPELINE 5622 { 5623 PIPELINE_MFXVC1PREDPIPESTATE = 2, //!< No additional details 5624 }; 5625 5626 enum COMMAND_TYPE 5627 { 5628 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5629 }; 5630 5631 //! \name Initializations 5632 5633 //! \brief Explicit member initialization function 5634 MFX_VC1_PRED_PIPE_STATE_CMD(); 5635 5636 static const size_t dwSize = 6; 5637 static const size_t byteSize = 24; 5638 }; 5639 5640 //! 5641 //! \brief MFD_VC1_LONG_PIC_STATE 5642 //! \details 5643 //! MFX_VC1_LONG PIC_STATE command encapsulates the decoding parameters that 5644 //! are read or derived from bitstream syntax elements above (inclusive) 5645 //! picture header layer. These parameters are static for a picture and when 5646 //! slice structure is present, these parameters are not changed from slice 5647 //! to slice of the same picture. Hence, this command is only issued at the 5648 //! beginning of processing a new picture and prior to the VC1_*_OBJECT 5649 //! command. The values set for these state variables are retained 5650 //! internally across slices.Only the parameters needed by hardware (BSD 5651 //! unit) to decode bit sequence for the macroblocks in a picture layer or a 5652 //! slice layer are presented in this command. Other parameters such as the 5653 //! ones used for inverse transform or motion compensation are provided in 5654 //! MFX_VC1_PRED_PIPE_STATE command.This Long interface format is intel 5655 //! proprietary interface. Driver will need to perform addition operations 5656 //! to generate all the fields in this command. 5657 //! 5658 struct MFD_VC1_LONG_PIC_STATE_CMD 5659 { 5660 union 5661 { 5662 //!< DWORD 0 5663 struct 5664 { 5665 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 5666 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5667 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 5668 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 5669 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 5670 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 5671 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 5672 }; 5673 uint32_t Value; 5674 } DW0; 5675 union 5676 { 5677 //!< DWORD 1 5678 struct 5679 { 5680 uint32_t Picturewidthinmbsminus1PictureWidthMinus1InMacroblocks : __CODEGEN_BITFIELD( 0, 7) ; //!< PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5681 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 5682 uint32_t Pictureheightinmbsminus1PictureHeightMinus1InMacroblocks : __CODEGEN_BITFIELD(16, 23) ; //!< PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5683 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 5684 }; 5685 uint32_t Value; 5686 } DW1; 5687 union 5688 { 5689 //!< DWORD 2 5690 struct 5691 { 5692 uint32_t Vc1Profile : __CODEGEN_BITFIELD( 0, 0) ; //!< VC1_PROFILE 5693 uint32_t Reserved65 : __CODEGEN_BITFIELD( 1, 2) ; //!< Reserved 5694 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< Secondfield 5695 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 5696 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 5697 uint32_t RangereductionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RANGEREDUCTION_ENABLE 5698 uint32_t Rangereductionscale : __CODEGEN_BITFIELD( 7, 7) ; //!< RANGEREDUCTIONSCALE 5699 uint32_t MotionVectorMode : __CODEGEN_BITFIELD( 8, 11) ; //!< MOTION_VECTOR_MODE 5700 uint32_t Syncmarker : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER 5701 uint32_t InterpolationRounderContro : __CODEGEN_BITFIELD(13, 13) ; //!< Interpolation Rounder Contro 5702 uint32_t Implicitquantizer : __CODEGEN_BITFIELD(14, 14) ; //!< ImplicitQuantizer 5703 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 5704 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 5705 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 5706 }; 5707 uint32_t Value; 5708 } DW2; 5709 union 5710 { 5711 //!< DWORD 3 5712 struct 5713 { 5714 uint32_t Bscalefactor : __CODEGEN_BITFIELD( 0, 7) ; //!< BScaleFactor 5715 uint32_t PquantPictureQuantizationValue : __CODEGEN_BITFIELD( 8, 12) ; //!< PQuant (Picture Quantization Value) 5716 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 5717 uint32_t AltpquantAlternativePictureQuantizationValue : __CODEGEN_BITFIELD(16, 20) ; //!< AltPQuant (Alternative Picture Quantization Value) 5718 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved 5719 uint32_t FcmFrameCodingMode : __CODEGEN_BITFIELD(24, 25) ; //!< FCM_FRAME_CODING_MODE 5720 uint32_t PictypePictureType : __CODEGEN_BITFIELD(26, 28) ; //!< PicType (Picture Type) 5721 uint32_t Condover : __CODEGEN_BITFIELD(29, 30) ; //!< CONDOVER 5722 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 5723 }; 5724 uint32_t Value; 5725 } DW3; 5726 union 5727 { 5728 //!< DWORD 4 5729 struct 5730 { 5731 uint32_t Pquantuniform : __CODEGEN_BITFIELD( 0, 0) ; //!< PQUANTUNIFORM 5732 uint32_t Halfqp : __CODEGEN_BITFIELD( 1, 1) ; //!< HalfQP 5733 uint32_t AltpquantconfigAlternativePictureQuantizationConfiguration : __CODEGEN_BITFIELD( 2, 3) ; //!< ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5734 uint32_t AltpquantedgemaskAlternativePictureQuantizationEdgeMask : __CODEGEN_BITFIELD( 4, 7) ; //!< AltPQuantEdgeMask (Alternative Picture Quantization Edge Mask) 5735 uint32_t ExtendedmvrangeExtendedMotionVectorRangeFlag : __CODEGEN_BITFIELD( 8, 9) ; //!< EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5736 uint32_t ExtendeddmvrangeExtendedDifferentialMotionVectorRangeFlag : __CODEGEN_BITFIELD(10, 11) ; //!< EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 5737 uint32_t Reserved140 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 5738 uint32_t FwdrefdistReferenceDistance : __CODEGEN_BITFIELD(16, 19) ; //!< FwdRefDist (Reference Distance) 5739 uint32_t BwdrefdistReferenceDistance : __CODEGEN_BITFIELD(20, 23) ; //!< BwdRefDist (Reference Distance) 5740 uint32_t NumrefNumberOfReferences : __CODEGEN_BITFIELD(24, 24) ; //!< NUMREF_NUMBER_OF_REFERENCES 5741 uint32_t ReffieldpicpolarityReferenceFieldPicturePolarity : __CODEGEN_BITFIELD(25, 25) ; //!< REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 5742 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD(26, 26) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 5743 uint32_t FourmvswitchFourMotionVectorSwitch : __CODEGEN_BITFIELD(27, 27) ; //!< FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 5744 uint32_t UnifiedmvmodeUnifiedMotionVectorMode : __CODEGEN_BITFIELD(28, 29) ; //!< UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 5745 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 5746 }; 5747 uint32_t Value; 5748 } DW4; 5749 union 5750 { 5751 //!< DWORD 5 5752 struct 5753 { 5754 uint32_t CbptabCodedBlockPatternTable : __CODEGEN_BITFIELD( 0, 2) ; //!< CbpTab (Coded Block Pattern Table) 5755 uint32_t TransdctabIntraTransformDcTable : __CODEGEN_BITFIELD( 3, 3) ; //!< TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 5756 uint32_t TransacuvPictureLevelTransformChromaAcCodingSetIndexTransactable : __CODEGEN_BITFIELD( 4, 5) ; //!< TransAcUV (Picture-level Transform Chroma AC Coding Set Index, TRANSACTABLE) 5757 uint32_t TransacyPictureLevelTransformLumaAcCodingSetIndexTransactable2 : __CODEGEN_BITFIELD( 6, 7) ; //!< TransAcY (Picture-level Transform Luma AC Coding Set Index, TRANSACTABLE2 5758 uint32_t MbmodetabMacroblockModeTable : __CODEGEN_BITFIELD( 8, 10) ; //!< MbModeTab (Macroblock Mode Table) 5759 uint32_t TranstypembflagMacroblockTransformTypeFlag : __CODEGEN_BITFIELD(11, 11) ; //!< TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 5760 uint32_t TranstypePictureLevelTransformType : __CODEGEN_BITFIELD(12, 13) ; //!< TransType (Picture-level Transform Type) 5761 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 5762 uint32_t Twomvbptab2MvBlockPatternTable : __CODEGEN_BITFIELD(16, 17) ; //!< TwoMvBpTab (2MV Block Pattern Table) 5763 uint32_t Fourmvbptab4MvBlockPatternTable : __CODEGEN_BITFIELD(18, 19) ; //!< FourMvBpTab (4-MV Block Pattern Table) 5764 uint32_t MvtabMotionVectorTable : __CODEGEN_BITFIELD(20, 22) ; //!< MvTab (Motion Vector Table) 5765 uint32_t Reserved183 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 5766 uint32_t Fieldtxraw : __CODEGEN_BITFIELD(24, 24) ; //!< FIELDTXRAW 5767 uint32_t Acpredraw : __CODEGEN_BITFIELD(25, 25) ; //!< ACPREDRAW 5768 uint32_t Overflagsraw : __CODEGEN_BITFIELD(26, 26) ; //!< OVERFLAGSRAW 5769 uint32_t Directmbraw : __CODEGEN_BITFIELD(27, 27) ; //!< DIRECTMBRAW 5770 uint32_t Skipmbraw : __CODEGEN_BITFIELD(28, 28) ; //!< SKIPMBRAW 5771 uint32_t Mvtypembraw : __CODEGEN_BITFIELD(29, 29) ; //!< MVTYPEMBRAW 5772 uint32_t Forwardmbraw : __CODEGEN_BITFIELD(30, 30) ; //!< FORWARDMBRAW 5773 uint32_t BitplanepresentflagBitplaneBufferPresentFlag : __CODEGEN_BITFIELD(31, 31) ; //!< BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 5774 }; 5775 uint32_t Value; 5776 } DW5; 5777 5778 //! \name Local enumerations 5779 5780 enum SUBOPCODE_B 5781 { 5782 SUBOPCODE_B_UNNAMED1 = 1, //!< No additional details 5783 }; 5784 5785 enum SUBOPCODE_A 5786 { 5787 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 5788 }; 5789 5790 enum MEDIA_COMMAND_OPCODE 5791 { 5792 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 5793 }; 5794 5795 enum PIPELINE 5796 { 5797 PIPELINE_MFDVC1LONGPICSTATE = 2, //!< No additional details 5798 }; 5799 5800 enum COMMAND_TYPE 5801 { 5802 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 5803 }; 5804 5805 //! \brief PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5806 //! \details 5807 //! This field indicates the width of the picture in unit of macroblocks. 5808 //! For example, for a 1920x1080 frame picture, PictureWidthInMBs equals 120 5809 //! (1920 divided by 16).This field is used in VLD and IT modes 5810 enum PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS 5811 { 5812 PICTUREWIDTHINMBSMINUS1_PICTURE_WIDTH_MINUS_1_IN_MACROBLOCKS_VALUE255 = 255, //!< No additional details 5813 }; 5814 5815 //! \brief PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5816 //! \details 5817 //! This field indicates the height of the picture in unit of macroblocks. 5818 //! For example, for a 1920x1080 frame picture, PictureHeightInMBs equals 68 5819 //! (1080 divided by 16, and rounded up, i.e. effectively specified as 1088 5820 //! instead).This field is used in VLD and IT modes. 5821 enum PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_ 5822 { 5823 PICTUREHEIGHTINMBSMINUS1_PICTURE_HEIGHT_MINUS_1_IN_MACROBLOCKS_VALUE255 = 255, //!< No additional details 5824 }; 5825 5826 //! \brief VC1_PROFILE 5827 //! \details 5828 //! specifies the bitstream profile.This field is used in both VLD and IT 5829 //! modes. 5830 enum VC1_PROFILE 5831 { 5832 VC1_PROFILE_DISABLE = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 5833 VC1_PROFILE_ENABLE = 1, //!< current picture is in Advanced Profile 5834 }; 5835 5836 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 5837 //! \details 5838 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 5839 //! if Overlap smoothing is ON at the picture levelThis field is used in 5840 //! both VLD and IT modes. 5841 enum OVERLAP_SMOOTHING_ENABLE_FLAG 5842 { 5843 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 5844 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 5845 }; 5846 5847 //! \brief LOOPFILTER_ENABLE_FLAG 5848 //! \details 5849 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 5850 //! indicates if In-loop Deblocking is ON according to picture level 5851 //! bitstream syntax control. This bit affects BSD unit and also the loop 5852 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 5853 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 5854 //! in-loop deblocking operation follows the VC1 standard - deblocking 5855 //! doesn't cross slice boundary.When this bit is set to 0, but 5856 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 5857 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 5858 //! this case, deblocking operation does cross slice boundary.This field is 5859 //! used in VLD mode only, not in IT mode. 5860 enum LOOPFILTER_ENABLE_FLAG 5861 { 5862 LOOPFILTER_ENABLE_FLAG_DISABLE = 0, //!< Disables loop filter 5863 LOOPFILTER_ENABLE_FLAG_ENABLE = 1, //!< Enables loop filter 5864 }; 5865 5866 //! \brief RANGEREDUCTION_ENABLE 5867 //! \details 5868 //! This field specifies whether on-the-fly pixel value range reduction 5869 //! should be performed for the preceding (or forward) reference picture. 5870 //! Along with RangeReductionScale to specify whether scale up or down 5871 //! should be performed. It is not the same value as RANGEREDFRM Syntax 5872 //! Element (PictureParameters bPicDeblocked bit 5) in the Picture 5873 //! Header. 5874 enum RANGEREDUCTION_ENABLE 5875 { 5876 RANGEREDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 5877 RANGEREDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 5878 }; 5879 5880 //! \brief RANGEREDUCTIONSCALE 5881 //! \details 5882 //! This field specifies whether the reference picture pixel values should 5883 //! be scaled up or scaled down on-the-fly, if RangeReduction is Enabled. 5884 enum RANGEREDUCTIONSCALE 5885 { 5886 RANGEREDUCTIONSCALE_UNNAMED0 = 0, //!< Scale down reference picture by factor of 2 5887 RANGEREDUCTIONSCALE_UNNAMED1 = 1, //!< Scale up reference picture by factor of 2 5888 }; 5889 5890 //! \brief MOTION_VECTOR_MODE 5891 //! \details 5892 //! This field indicates one of the following motion compensation 5893 //! interpolation modes for P and B pictures. The MC interpolation modes 5894 //! apply to prediction values of luminance blocks and are always in 5895 //! quarter-sample. For chrominance blocks, it always performs bilinear 5896 //! interpolation with either half-pel or quarter-pel precision.Before the 5897 //! polarity of Chroma Half-pel or Q-pel is reversed, now I 5898 //! have fixed it to match with VC1 Spec. 5899 enum MOTION_VECTOR_MODE 5900 { 5901 MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Chroma Quarter -pel + Luma bicubic. (can only be 1MV) 5902 MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< Chroma Half-pel + Luma bicubic. (can be 1MV or 4MV) 5903 MOTION_VECTOR_MODE_UNNAMED8 = 8, //!< Chroma Quarter -pel + Luma bilinear. (can only be 1MV) 5904 MOTION_VECTOR_MODE_UNNAMED9 = 9, //!< Chroma Half-pel + Luma bilinear 5905 }; 5906 5907 //! \brief SYNCMARKER 5908 //! \details 5909 //! Indicates whether sync markers are enabled/disabled. If enable, sync 5910 //! markers "may be" present in the current video sequence being decoded. It 5911 //! is a sequence level syntax element and is valid only for Simple and Main 5912 //! Profiles. 5913 enum SYNCMARKER 5914 { 5915 SYNCMARKER_NOTPRESENT = 0, //!< Sync Marker is not present in the bitstream 5916 SYNCMARKER_MAYBEPRESENT = 1, //!< Sync Marker maybe present in the bitstream 5917 }; 5918 5919 //! \brief FCM_FRAME_CODING_MODE 5920 //! \details 5921 //! This is the same as the variable FCM defined in VC1.This field must be 5922 //! set to 0 for Simple and Main ProfilesThis field is unique to intel VC1 5923 //! VLD Long format, and is used in IT mode as well. For VC1 IT mode, 5924 //! driver needs to convert the interface to intel HW VLD Long Format 5925 //! interface. 5926 enum FCM_FRAME_CODING_MODE 5927 { 5928 FCM_FRAME_CODING_MODE_DISABLE = 0, //!< Progressive Frame Picture 5929 FCM_FRAME_CODING_MODE_ENABLE = 1, //!< Interlaced Frame Picture 5930 FCM_FRAME_CODING_MODE_UNNAMED2 = 2, //!< Field Picture with Top Field First 5931 FCM_FRAME_CODING_MODE_UNNAMED3 = 3, //!< Field Picture with Bottom Field First 5932 }; 5933 5934 //! \brief CONDOVER 5935 //! \details 5936 //! This field is the decoded syntax element CONDOVER in a bitstream of 5937 //! advanced profile. It controls the overlap smoothing filter operation for 5938 //! an I frame or an BI frame when the picture level qualization step size 5939 //! PQUANT is 8 or lower.This field is used in intel VC1 VLD mode only, not 5940 //! in VC1 and IT modes. 5941 enum CONDOVER 5942 { 5943 CONDOVER_UNNAMED0 = 0, //!< No overlap smoothing 5944 CONDOVER_UNNAMED1 = 1, //!< Reserved 5945 CONDOVER_UNNAMED2 = 2, //!< Always perform overlap smoothing filter 5946 CONDOVER_UNNAMED3 = 3, //!< Overlap smoothing on a per macroblock basis based on OVERFLAGS 5947 }; 5948 5949 //! \brief PQUANTUNIFORM 5950 //! \details 5951 //! Indicating if uniform quantization applies to the 5952 //! picture. It is used for inverse quantization of the AC 5953 //! coefficients.QUANTIZER 5954 //! 001123PQUANTIZER - 5955 //! -01--PQINDEX>=9<=8----PQuantUniform010201ImplicitQuantizer = 5956 //! 0, and 5957 //! PQuantUniform = 0 is used to represent 2 cases : 1) QUANTIZER=01 5958 //! and 5959 //! PQUANTIZER=0; and 2) QUANTIZER = 10b.ImplicitQuantizer = 0, and 5960 //! PQuantUniform = 5961 //! 1 is used to represent 2 cases : 1) QUANTIZER=01 and PQUANTIZER=1; 5962 //! and 2) 5963 //! QUANTIZER = 11bThis field is unique to intel VC1 VLD Long format 5964 //! mode, and is 5965 //! not used in IT and VC1 modes. 5966 enum PQUANTUNIFORM 5967 { 5968 PQUANTUNIFORM_UNNAMED0 = 0, //!< Non-uniform 5969 PQUANTUNIFORM_UNNAMED1 = 1, //!< Uniform 5970 }; 5971 5972 //! \brief ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5973 //! \details 5974 //! This field specifies the way AltPQuant is used in the picture. It 5975 //! determines how to compute the macroblock quantizer step size, MQUANT. It 5976 //! is derived based on the following variables DQUANT, DQUANTFRM, 5977 //! DQPROFILE, DQSBEDGE, DQDBEDGE, and DQBILEVEL defined in the VC1 5978 //! standard, as shown in Error! Reference source not found..This field is 5979 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 5980 //! VC1 modes. 5981 enum ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION 5982 { 5983 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED0 = 0, //!< AltPQuant not used 5984 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED1 = 1, //!< AltPQuant is used and applied to edge macroblocks only 5985 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED2 = 2, //!< MQUANT is encoded in macroblock layer 5986 ALTPQUANTCONFIG_ALTERNATIVE_PICTURE_QUANTIZATION_CONFIGURATION_UNNAMED3 = 3, //!< AltPQuant and PQuant are selected on macroblock basis 5987 }; 5988 5989 //! \brief EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5990 //! \details 5991 //! This field specifies the motion vector range in quarter-pel or half-pel 5992 //! modes. It is equivalent to the variable MVRANGE in the VC1 standard. 5993 //! This field is unique to intel VC1 VLD Long format mode, and is not used 5994 //! in IT and VC1 modes 5995 enum EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG 5996 { 5997 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< [-256, 255] x [-128, 127] 5998 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< 512, 511] x [-256, 255] 5999 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< [-2048, 2047] x [-1024, 1023] 6000 EXTENDEDMVRANGE_EXTENDED_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< [-4096, 4095] x [-2048, 2047] 6001 }; 6002 6003 //! \brief EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 6004 //! \details 6005 //! This field specifies the differential motion vector range in interlaced 6006 //! pictures. It is equivalent to the variable DMVRANGE in the VC1 standard. 6007 //! This field is unique to intel VC1 VLD Long format mode, and is not used 6008 //! in IT and VC1 modes. 6009 enum EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG 6010 { 6011 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED0 = 0, //!< No extended range 6012 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED1 = 1, //!< Extended horizontally 6013 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED2 = 2, //!< Extended vertically 6014 EXTENDEDDMVRANGE_EXTENDED_DIFFERENTIAL_MOTION_VECTOR_RANGE_FLAG_UNNAMED3 = 3, //!< Extended in both directions 6015 }; 6016 6017 //! \brief NUMREF_NUMBER_OF_REFERENCES 6018 //! \details 6019 //! This field indicates how many reference fields are referenced by the 6020 //! current (field) picture. It is identical to the variable NUMREF in the 6021 //! VC1 standard. This field is only valid for field P picture (FCM = 10 | 6022 //! 11).This field is unique to intel VC1 VLD Long format mode, and is not 6023 //! used in IT and VC1 modes. 6024 enum NUMREF_NUMBER_OF_REFERENCES 6025 { 6026 NUMREF_NUMBER_OF_REFERENCES_UNNAMED0 = 0, //!< One field referenced 6027 NUMREF_NUMBER_OF_REFERENCES_UNNAMED1 = 1, //!< Two fields referenced 6028 }; 6029 6030 //! \brief REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 6031 //! \details 6032 //! This field specifies the polarity of the one reference field picture 6033 //! used for a field P picture. It is derived from the variable REFFIELD 6034 //! defined in VC1 standard and is only valid when one field is referenced 6035 //! (NUMREF = 0) for a field P picture.When NUMREF = 0 and REFFIELD = 0, 6036 //! this field is the polarity of the reference I/P field that is temporally 6037 //! closest; When NUMREF = 0 and REFFIELD = 1, this field is the polarity of 6038 //! the reference I/P field that is the second most temporally closest. The 6039 //! distance is measured based on display order but ignoring the repeated 6040 //! field if present (due to RFF = 1).This field is unique to intel VC1 VLD 6041 //! Long format mode, and is not used in IT and VC1 modes. 6042 enum REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY 6043 { 6044 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED0 = 0, //!< Top (even) field 6045 REFFIELDPICPOLARITY_REFERENCE_FIELD_PICTURE_POLARITY_UNNAMED1 = 1, //!< Bottom (odd) field 6046 }; 6047 6048 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6049 //! \details 6050 //! This field specifies whether the motion vectors for 6051 //! UV is rounded to half or full pel position. It is identical to the 6052 //! variable 6053 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 6054 //! modes.It is 6055 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 6056 //! both VLD and 6057 //! IT modes, and should have the same value as Motion Vector Mode 6058 //! LSBit. 6059 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6060 { 6061 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6062 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6063 }; 6064 6065 //! \brief FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 6066 //! \details 6067 //! This field indicates if 4-MV is present for an interlaced frame P 6068 //! picture. It is identical to the variable 4MVSWITCH (4 Motion Vector 6069 //! Switch) in VC1 standard.This field is used in intel VC1 VLD Long Format 6070 //! mode only, it is not used in VC1 VLD and IT modes. 6071 enum FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH 6072 { 6073 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_DISABLE = 0, //!< only 1-MV 6074 FOURMVSWITCH_FOUR_MOTION_VECTOR_SWITCH_ENABLE = 1, //!< 1, 2, or 4 MVs 6075 }; 6076 6077 //! \brief UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 6078 //! \details 6079 //! This field is a combination of the variables MVMODE and MVMODE2 in the 6080 //! VC1 standard, for parsing Luma MVD from the bitstream. This field is 6081 //! used to signal 1MV vs 4MVallowed (Mixed Mode). This field is also used 6082 //! to signal Q-pel or Half-pel MVD read from the bitstream. The bicubic or 6083 //! bilinear Luma MC interpolation mode is duplicate information from Motion 6084 //! Vector Mode field, and is ignored here.This field is used in intel VC1 6085 //! VLD Long Format mode only, it is not used in VC1 VLD and IT modes. 6086 enum UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE 6087 { 6088 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED0 = 0, //!< Mixed MV, Q-pel bicubic 6089 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED1 = 1, //!< 1-MV, Q-pel bicubic 6090 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED2 = 2, //!< 1-MV half-pel bicubic 6091 UNIFIEDMVMODE_UNIFIED_MOTION_VECTOR_MODE_UNNAMED3 = 3, //!< 1-MV half-pel bilinear 6092 }; 6093 6094 //! \brief TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6095 //! \details 6096 //! This field specifies whether the low motion tables or the high motion 6097 //! tables are used to decode the Transform DC coefficients in intra-coded 6098 //! blocks. This field is identical to the variable TRANSDCTAB in the VC1 6099 //! standard, section 8.1.1.2.This field is valid for all picture types.This 6100 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6101 //! and VC1 modes. 6102 enum TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE 6103 { 6104 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED0 = 0, //!< The high motion tables 6105 TRANSDCTAB_INTRA_TRANSFORM_DC_TABLE_UNNAMED1 = 1, //!< The low motion tables 6106 }; 6107 6108 //! \brief TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6109 //! \details 6110 //! This field indicates whether Transform Type is fixed at picture level or 6111 //! variable at macroblock level. It is identical to the variable TTMBF in 6112 //! the VC1 standard, section 7.1.1.40.This field is set to 1 when 6113 //! VSTRANSFORM is 0 in the entry point layer.This field is unique to intel 6114 //! VC1 VLD Long format mode, and is not used in IT and VC1 modes. 6115 enum TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG 6116 { 6117 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED0 = 0, //!< variable transform type in macroblock layer 6118 TRANSTYPEMBFLAG_MACROBLOCK_TRANSFORM_TYPE_FLAG_UNNAMED1 = 1, //!< use picture level transform type TransType 6119 }; 6120 6121 //! \brief FIELDTXRAW 6122 //! \details 6123 //! This field indicates whether the FIELDTX field is coded in raw or 6124 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6125 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6126 //! and VC1 modes. 6127 enum FIELDTXRAW 6128 { 6129 FIELDTXRAW_DISABLE = 0, //!< Non-Raw Mode 6130 FIELDTXRAW_ENABLE = 1, //!< Raw Mode 6131 }; 6132 6133 //! \brief ACPREDRAW 6134 //! \details 6135 //! This field indicates whether the ACPRED field is coded in raw or non-raw 6136 //! mode.This field is only valid when PictureType is I or BI.This field is 6137 //! unique to intel VC1 VLD Long format mode, and is not used in IT and 6138 //! VC1 modes. 6139 enum ACPREDRAW 6140 { 6141 ACPREDRAW_DISABLE = 0, //!< Non-Raw Mode 6142 ACPREDRAW_ENABLE = 1, //!< Raw Mode 6143 }; 6144 6145 //! \brief OVERFLAGSRAW 6146 //! \details 6147 //! This field indicates whether the OVERFLAGS field is coded in raw or 6148 //! non-raw mode.This field is only valid when PictureType is I or BI.This 6149 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6150 //! and VC1 modes. 6151 enum OVERFLAGSRAW 6152 { 6153 OVERFLAGSRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6154 OVERFLAGSRAW_UNNAMED1 = 1, //!< Raw Mode 6155 }; 6156 6157 //! \brief DIRECTMBRAW 6158 //! \details 6159 //! This field indicates whether the DIRECTMB field is coded in raw or 6160 //! non-raw mode.This field is only valid when PictureType is P or B.This 6161 //! field is unique to intel VC1 VLD Long format mode, and is not used in IT 6162 //! and VC1 modes. 6163 enum DIRECTMBRAW 6164 { 6165 DIRECTMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6166 DIRECTMBRAW_UNNAMED1 = 1, //!< Raw Mode 6167 }; 6168 6169 //! \brief SKIPMBRAW 6170 //! \details 6171 //! This field indicates whether the SKIPMB field is coded in raw or non-raw 6172 //! mode.This field is only valid when PictureType is P or B.0 = non-raw 6173 //! mode1 = raw modeThis field is unique to intel VC1 VLD Long format mode, 6174 //! and is not used in IT and VC1 modes. 6175 enum SKIPMBRAW 6176 { 6177 SKIPMBRAW_DISABLE = 0, //!< Non-Raw Mode 6178 SKIPMBRAW_ENABLE = 1, //!< Raw Mode 6179 }; 6180 6181 //! \brief MVTYPEMBRAW 6182 //! \details 6183 //! This field indicates whether the MVTYPREMB field is coded in raw or 6184 //! non-raw mode.This field is only valid when PictureType is P.This field 6185 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6186 //! VC1 modes. 6187 enum MVTYPEMBRAW 6188 { 6189 MVTYPEMBRAW_UNNAMED0 = 0, //!< Non-Raw Mode 6190 MVTYPEMBRAW_UNNAMED1 = 1, //!< Raw Mode 6191 }; 6192 6193 //! \brief FORWARDMBRAW 6194 //! \details 6195 //! This field indicates whether the FORWARDMB field is coded in raw or 6196 //! non-raw mode.This field is only valid when PictureType is B.This field 6197 //! is unique to intel VC1 VLD Long format mode, and is not used in IT and 6198 //! VC1 modes. 6199 enum FORWARDMBRAW 6200 { 6201 FORWARDMBRAW_UNNAMED0 = 0, //!< non-raw mode 6202 FORWARDMBRAW_UNNAMED1 = 1, //!< raw mode 6203 }; 6204 6205 //! \brief BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6206 //! \details 6207 //! This field indicates whether the bitplane buffer is present for the 6208 //! picture. If set, at least one of the fields listed in bits 22:16 is 6209 //! coded in non-raw mode, and Bitplane Buffer Base Address field in the 6210 //! VC1_BSD_BUF_BASE_STATE command points to the bitplane buffer. Otherwise, 6211 //! all the fields that are applicable for the current picture in bits 22:16 6212 //! must be coded in raw mode.This field is unique to intel VC1 VLD Long 6213 //! format mode, and is not used in IT and VC1 modes. 6214 enum BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG 6215 { 6216 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED0 = 0, //!< bitplane buffer is not present 6217 BITPLANEPRESENTFLAG_BITPLANE_BUFFER_PRESENT_FLAG_UNNAMED1 = 1, //!< bitplane buffer is present 6218 }; 6219 6220 //! \name Initializations 6221 6222 //! \brief Explicit member initialization function 6223 MFD_VC1_LONG_PIC_STATE_CMD(); 6224 6225 static const size_t dwSize = 6; 6226 static const size_t byteSize = 24; 6227 }; 6228 6229 //! 6230 //! \brief MFD_VC1_SHORT_PIC_STATE 6231 //! \details 6232 //! 6233 //! 6234 struct MFD_VC1_SHORT_PIC_STATE_CMD 6235 { 6236 union 6237 { 6238 //!< DWORD 0 6239 struct 6240 { 6241 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6242 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6243 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6244 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6245 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6246 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6247 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6248 }; 6249 uint32_t Value; 6250 } DW0; 6251 union 6252 { 6253 //!< DWORD 1 6254 struct 6255 { 6256 uint32_t PictureWidth : __CODEGEN_BITFIELD( 0, 7) ; //!< Picture Width 6257 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 6258 uint32_t PictureHeight : __CODEGEN_BITFIELD(16, 23) ; //!< Picture Height 6259 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6260 }; 6261 uint32_t Value; 6262 } DW1; 6263 union 6264 { 6265 //!< DWORD 2 6266 struct 6267 { 6268 uint32_t PictureStructure : __CODEGEN_BITFIELD( 0, 1) ; //!< PICTURE_STRUCTURE 6269 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 6270 uint32_t Secondfield : __CODEGEN_BITFIELD( 3, 3) ; //!< SecondField 6271 uint32_t IntraPictureFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< INTRA_PICTURE_FLAG 6272 uint32_t BackwardPredictionPresentFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< Backward Prediction Present Flag 6273 uint32_t Reserved70 : __CODEGEN_BITFIELD( 6, 10) ; //!< Reserved 6274 uint32_t Vc1Profile : __CODEGEN_BITFIELD(11, 11) ; //!< VC1_PROFILE 6275 uint32_t Reserved76 : __CODEGEN_BITFIELD(12, 14) ; //!< Reserved 6276 uint32_t Dmvsurfacevalid : __CODEGEN_BITFIELD(15, 15) ; //!< DmvSurfaceValid 6277 uint32_t MotionVectorMode : __CODEGEN_BITFIELD(16, 19) ; //!< Motion Vector Mode 6278 uint32_t Reserved84 : __CODEGEN_BITFIELD(20, 22) ; //!< Reserved 6279 uint32_t InterpolationRounderControl : __CODEGEN_BITFIELD(23, 23) ; //!< Interpolation Rounder Control 6280 uint32_t BitplaneBufferPitchMinus1 : __CODEGEN_BITFIELD(24, 31) ; //!< Bitplane Buffer Pitch Minus 1 6281 }; 6282 uint32_t Value; 6283 } DW2; 6284 union 6285 { 6286 //!< DWORD 3 6287 struct 6288 { 6289 uint32_t VstransformFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< VSTRANSFORM_FLAG 6290 uint32_t Dquant : __CODEGEN_BITFIELD( 1, 2) ; //!< DQUANT 6291 uint32_t ExtendedMvPresentFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< EXTENDED_MV_PRESENT_FLAG 6292 uint32_t FastuvmcflagFastUvMotionCompensationFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6293 uint32_t LoopfilterEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< LOOPFILTER_ENABLE_FLAG 6294 uint32_t RefdistFlag : __CODEGEN_BITFIELD( 6, 6) ; //!< REFDIST_FLAG 6295 uint32_t PanscanPresentFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< PANSCAN_PRESENT_FLAG 6296 uint32_t Maxbframes : __CODEGEN_BITFIELD( 8, 10) ; //!< MAXBFRAMES 6297 uint32_t RangeredPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(11, 11) ; //!< RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6298 uint32_t SyncmarkerPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(12, 12) ; //!< SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6299 uint32_t MultiresPresentFlagForSimpleMainProfileOnly : __CODEGEN_BITFIELD(13, 13) ; //!< MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6300 uint32_t Quantizer : __CODEGEN_BITFIELD(14, 15) ; //!< QUANTIZER 6301 uint32_t PPicRefDistance : __CODEGEN_BITFIELD(16, 20) ; //!< P_PIC_REF_DISTANCE 6302 uint32_t Reserved117 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 6303 uint32_t ProgressivePicType : __CODEGEN_BITFIELD(22, 23) ; //!< PROGRESSIVE_PIC_TYPE 6304 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 27) ; //!< Reserved 6305 uint32_t RangeReductionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< RANGE_REDUCTION_ENABLE 6306 uint32_t RangeReductionScale : __CODEGEN_BITFIELD(29, 29) ; //!< RANGE_REDUCTION_SCALE 6307 uint32_t OverlapSmoothingEnableFlag : __CODEGEN_BITFIELD(30, 30) ; //!< OVERLAP_SMOOTHING_ENABLE_FLAG 6308 uint32_t Reserved127 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 6309 }; 6310 uint32_t Value; 6311 } DW3; 6312 union 6313 { 6314 //!< DWORD 4 6315 struct 6316 { 6317 uint32_t ExtendedDmvPresentFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< EXTENDED_DMV_PRESENT_FLAG 6318 uint32_t Psf : __CODEGEN_BITFIELD( 1, 1) ; //!< PSF 6319 uint32_t RefpicFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< REFPIC_FLAG 6320 uint32_t Finterflag : __CODEGEN_BITFIELD( 3, 3) ; //!< FINTERFLAG 6321 uint32_t Tfcntrflag : __CODEGEN_BITFIELD( 4, 4) ; //!< TFCNTRFLAG 6322 uint32_t Interlace : __CODEGEN_BITFIELD( 5, 5) ; //!< INTERLACE 6323 uint32_t Pulldown : __CODEGEN_BITFIELD( 6, 6) ; //!< PULLDOWN 6324 uint32_t PostprocFlag : __CODEGEN_BITFIELD( 7, 7) ; //!< POSTPROC Flag 6325 uint32_t _4MvAllowedFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< _4MV Allowed Flag 6326 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 23) ; //!< Reserved 6327 uint32_t BfractionEnumeration : __CODEGEN_BITFIELD(24, 28) ; //!< BFraction Enumeration 6328 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6329 }; 6330 uint32_t Value; 6331 } DW4; 6332 6333 //! \name Local enumerations 6334 6335 enum SUBOPCODE_B 6336 { 6337 SUBOPCODE_B_UNNAMED0 = 0, //!< No additional details 6338 }; 6339 6340 enum SUBOPCODE_A 6341 { 6342 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6343 }; 6344 6345 enum MEDIA_COMMAND_OPCODE 6346 { 6347 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6348 }; 6349 6350 enum PIPELINE 6351 { 6352 PIPELINE_MFDVC1SHORTPICSTATE = 2, //!< No additional details 6353 }; 6354 6355 enum COMMAND_TYPE 6356 { 6357 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6358 }; 6359 6360 //! \brief PICTURE_STRUCTURE 6361 //! \details 6362 //! This field is used in both VC1 VLD mode and IT mode. It is the 6363 //! same parameter as bPicStructure in VC1 spec. 6364 //! The Picture Structure and Progressive Pic Type are used to derive 6365 //! the picture structure as specified in FCM, in VC1 VLD and IT mode. 6366 enum PICTURE_STRUCTURE 6367 { 6368 PICTURE_STRUCTURE_UNNAMED0 = 0, //!< illegal 6369 PICTURE_STRUCTURE_UNNAMED1 = 1, //!< top field (bit 0) 6370 PICTURE_STRUCTURE_UNNAMED2 = 2, //!< bottom field (bit 1) 6371 PICTURE_STRUCTURE_UNNAMED3 = 3, //!< frame (both fields are present) 6372 }; 6373 6374 //! \brief INTRA_PICTURE_FLAG 6375 //! \details 6376 //! This field is used in both VC1 VLD mode and IT mode. It is the 6377 //! same parameter as bPicIntra in VC1 spec. 6378 //! The Intra Picture Flag, Backward Prediction Present Flag and 6379 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6380 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6381 enum INTRA_PICTURE_FLAG 6382 { 6383 INTRA_PICTURE_FLAG_UNNAMED0 = 0, //!< entire picture can have a mixture of intra and inter MB type or just inter MB type. 6384 INTRA_PICTURE_FLAG_UNNAMED1 = 1, //!< entire picture is coded in intra MB type 6385 }; 6386 6387 //! \brief VC1_PROFILE 6388 //! \details 6389 //! specifies the bitstream profile. 6390 //! Note: This is required because 128 is added for intra blocks post 6391 //! inverse transform in advanced profile and also to find out if Motion 6392 //! vectors are adjusted or not. 6393 //! This field is used in both VLD and IT modes. 6394 enum VC1_PROFILE 6395 { 6396 VC1_PROFILE_UNNAMED0 = 0, //!< current picture is in Simple or Main Profile (No need to distinguish Simple and Main Profile) 6397 VC1_PROFILE_UNNAMED1 = 1, //!< current picture is in Advanced Profile 6398 }; 6399 6400 enum VSTRANSFORM_FLAG 6401 { 6402 VSTRANSFORM_FLAG_DISABLE = 0, //!< variable-sized transform coding is not enabled 6403 VSTRANSFORM_FLAG_ENABLE = 1, //!< variable-sized transform coding is enabled 6404 }; 6405 6406 //! \brief DQUANT 6407 //! \details 6408 //! Use for Picture Header Parsing of VOPDUANT elements 6409 enum DQUANT 6410 { 6411 DQUANT_UNNAMED0 = 0, //!< no VOPDQUANT elements; Quantizer cannot vary in frame, same quantization step size PQUANT is used for all MBs in the frame 6412 DQUANT_UNNAMED1 = 1, //!< refer to VC1 Spec. for all the MB position dependent quantizer selection 6413 DQUANT_UNNAMED2 = 2, //!< The macroblocks located on the picture edge boundary shall be quantized with ALTPQUANT while the rest of the macroblocks shall be quantized with PQUANT. 6414 }; 6415 6416 //! \brief EXTENDED_MV_PRESENT_FLAG 6417 //! \details 6418 //! BitFieldDesc 6419 enum EXTENDED_MV_PRESENT_FLAG 6420 { 6421 EXTENDED_MV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_MV is not present in the picture header 6422 EXTENDED_MV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_MV is present in the picture header 6423 }; 6424 6425 //! \brief FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6426 //! \details 6427 //! This field specifies whether the motion vectors for 6428 //! UV is rounded to half or full pel position. It is identical to the 6429 //! variable 6430 //! FASTUVMC in VC1 standard.This field is used in both VLD and IT 6431 //! modes.It is 6432 //! derived from FASTUVMC = (bPicSpatialResid8 >> 4) & 1 in 6433 //! both VLD and 6434 //! IT modes, and should have the same value as Motion Vector Mode 6435 //! LSBit. 6436 enum FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG 6437 { 6438 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED0 = 0, //!< no rounding 6439 FASTUVMCFLAG_FAST_UV_MOTION_COMPENSATION_FLAG_UNNAMED1 = 1, //!< quarter-pel offsets to half/full pel positions 6440 }; 6441 6442 //! \brief LOOPFILTER_ENABLE_FLAG 6443 //! \details 6444 //! This filed is the decoded syntax element LOOPFILTER in bitstream. It 6445 //! indicates if In-loop Deblocking is ON according to picture level 6446 //! bitstream syntax control. This bit affects BSD unit and also the loop 6447 //! filter unit.When this bit is set to 1, PostDeblockOutEnable field in 6448 //! MFX_PIPE_MODE_SELECT command must also be set to 1. In this case, 6449 //! in-loop deblocking operation follows the VC1 standard - deblocking 6450 //! doesn't cross slice boundary.When this bit is set to 0, but 6451 //! PostDeblockOutEnable field in MFX_PIPE_MODE_SELECT command is set to 1. 6452 //! It indicates the loop filter unit is used for out-of-loop deblocking. In 6453 //! this case, deblocking operation does cross slice boundary.This field is 6454 //! used in VLD mode only, not in IT mode. 6455 enum LOOPFILTER_ENABLE_FLAG 6456 { 6457 LOOPFILTER_ENABLE_FLAG_UNNAMED0 = 0, //!< In-Loop-Deblocking-Filter is disabled 6458 LOOPFILTER_ENABLE_FLAG_UNNAMED1 = 1, //!< In-Loop-Deblocking-Filter is enabled 6459 }; 6460 6461 enum PANSCAN_PRESENT_FLAG 6462 { 6463 PANSCAN_PRESENT_FLAG_UNNAMED0 = 0, //!< Pan Scan Parameters are not present in the picture header 6464 PANSCAN_PRESENT_FLAG_UNNAMED1 = 1, //!< Pan Scan Parameters are present in the picture header 6465 }; 6466 6467 //! \brief RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6468 //! \details 6469 //! It is needed for Picture Header Parsing.Driver is responsible to keep 6470 //! RangeReductionScale, RangeReduction Enable and RANGERED Present Flag of 6471 //! current picture coherent. 6472 enum RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6473 { 6474 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Range Reduction Parameter (RANGEREDFRM) is not present in the picture header 6475 RANGERED_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Range Reduction Parameter (RANGEREDFRM) is present in the picture header. 6476 }; 6477 6478 enum SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6479 { 6480 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< Bitstream for Simple and Main Profile has no sync marker 6481 SYNCMARKER_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< Bitstream for Simple and Main Profile may have sync marker(s) 6482 }; 6483 6484 enum MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY 6485 { 6486 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED0 = 0, //!< RESPIC Parameter is present in the picture header 6487 MULTIRES_PRESENT_FLAG_FOR_SIMPLEMAIN_PROFILE_ONLY_UNNAMED1 = 1, //!< RESPIC Parameter is present in the picture header 6488 }; 6489 6490 enum QUANTIZER 6491 { 6492 QUANTIZER_UNNAMED0 = 0, //!< implicit quantizer at frame leve 6493 QUANTIZER_UNNAMED1 = 1, //!< explicit quantizer at frame level, and use PQUANTIZER SE to specify uniform or non-uniform 6494 QUANTIZER_UNNAMED2 = 2, //!< explicit quantizer, and non-uniform quantizer for all frames 6495 QUANTIZER_UNNAMED3 = 3, //!< explicit quantizer, and uniform quantizer for all frames 6496 }; 6497 6498 //! \brief P_PIC_REF_DISTANCE 6499 //! \details 6500 //! This element defines the number of frames between the current frame and 6501 //! the reference frame. It is the same as the REFDIST SE in VC1 interlaced 6502 //! field picture header. It is present if the entry-level flag REFDIST_FLAG 6503 //! == 1, and if the picture type is not one of the following types: B/B, 6504 //! B/BI, BI/B, BI/BI. If the entry level flag REFDIST_FLAG == 0, REFDIST 6505 //! shall be set to the default value of 0.This field is used in VC1 6506 //! VLD mode only, not used in IT and intel VC1 VLD Long Format modes. 6507 enum P_PIC_REF_DISTANCE 6508 { 6509 P_PIC_REF_DISTANCE_UNNAMED0 = 0, //!< No additional details 6510 }; 6511 6512 //! \brief PROGRESSIVE_PIC_TYPE 6513 //! \details 6514 //! This field is used in both VC1 VLD mode and IT mode. It is the 6515 //! same parameter as bPicExtrapolation in VC1 spec.The Picture 6516 //! Structure and Progressive Pic Type are used to derive the picture 6517 //! structure as specified in FCM, in VC1 VLD and IT mode. 6518 enum PROGRESSIVE_PIC_TYPE 6519 { 6520 PROGRESSIVE_PIC_TYPE_UNNAMED0 = 0, //!< progressive only picture 6521 PROGRESSIVE_PIC_TYPE_UNNAMED1 = 1, //!< progressive only picture 6522 PROGRESSIVE_PIC_TYPE_UNNAMED2 = 2, //!< interlace picture (frame-interlace or field-interlace) 6523 PROGRESSIVE_PIC_TYPE_UNNAMED3 = 3, //!< illegal 6524 }; 6525 6526 //! \brief RANGE_REDUCTION_ENABLE 6527 //! \details 6528 //! This field specifies whether on-the-fly pixel value 6529 //! range reduction should be performed for the preceding (or forward) 6530 //! reference 6531 //! picture. Along with RangeReductionScale to specify whether scale up 6532 //! or down 6533 //! should be performed. It is not the same value as RANGEREDFRM Syntax 6534 //! Element 6535 //! (PictureParameters bPicDeblocked bit 5) in the Picture 6536 //! Header.This field is 6537 //! for Main Profile only. Simple Profile is always disable, and not 6538 //! applicable to 6539 //! Advanced Profile. This field is used in both VLD and IT modes.This 6540 //! is derived by 6541 //! driver from the history of RANGERED and RANGEREDFRM syntax elements 6542 //! (i.e. of 6543 //! forward/preceding reference picture) and those of the current 6544 //! picture.RANGERED 6545 //! is the same as (bPicOverflowBlocks >> 3) & 1. RANGEREDFRM 6546 //! is the same 6547 //! as (bPicDeblocked >> 5) & 1.For the current picture is a 6548 //! B picture, 6549 //! this field represents the state of the forward/preceding reference 6550 //! picture 6551 //! onlyDriver is responsible to keep RangeReductionScale, 6552 //! RangeReduction Enable and 6553 //! RANGERED Present Flag of current picture coherent. 6554 enum RANGE_REDUCTION_ENABLE 6555 { 6556 RANGE_REDUCTION_ENABLE_DISABLE = 0, //!< Range reduction is not performed 6557 RANGE_REDUCTION_ENABLE_ENABLE = 1, //!< Range reduction is performed 6558 }; 6559 6560 //! \brief RANGE_REDUCTION_SCALE 6561 //! \details 6562 //! This field specifies whether the reference picture 6563 //! pixel values should be scaled up or scaled down on-the-fly, if 6564 //! RangeReduction is 6565 //! Enabled.NOTE: This bit is derived by driver for Main Profile only. 6566 //! Ignored in 6567 //! Simple and Advanced Profiles. This field is used in both VLD and IT 6568 //! modes.This 6569 //! is derived by driver from the history of RANGERED and RANGEREDFRM 6570 //! syntax 6571 //! elements (i.e. of forward/preceding reference picture) and those of 6572 //! the current 6573 //! picture. RANGERED is the same as (bPicOverflowBlocks >> 3) 6574 //! & 1. 6575 //! RANGEREDFRM is the same as (bPicDeblocked >> 5) & 1. For 6576 //! the current 6577 //! picture is a B picture, this field represents the state of the 6578 //! forward/preceding 6579 //! reference picture onlyDriver is responsible to keep 6580 //! RangeReductionScale, 6581 //! RangeReduction Enable and RANGERED Present Flag of current picture 6582 //! coherent. 6583 enum RANGE_REDUCTION_SCALE 6584 { 6585 RANGE_REDUCTION_SCALE_DISABLE = 0, //!< Scale down reference picture by factor of 2 6586 RANGE_REDUCTION_SCALE_ENABLE = 1, //!< Scale up reference picture by factor of 2 6587 }; 6588 6589 //! \brief OVERLAP_SMOOTHING_ENABLE_FLAG 6590 //! \details 6591 //! This field is the decoded syntax element OVERLAP in bitstreamIndicates 6592 //! if Overlap smoothing is ON at the picture levelThis field is used in 6593 //! both VLD and IT modes 6594 enum OVERLAP_SMOOTHING_ENABLE_FLAG 6595 { 6596 OVERLAP_SMOOTHING_ENABLE_FLAG_DISABLE = 0, //!< to disable overlap smoothing filter 6597 OVERLAP_SMOOTHING_ENABLE_FLAG_ENABLE = 1, //!< to enable overlap smoothing filter 6598 }; 6599 6600 enum EXTENDED_DMV_PRESENT_FLAG 6601 { 6602 EXTENDED_DMV_PRESENT_FLAG_UNNAMED0 = 0, //!< Extended_DMV is not present in the picture header 6603 EXTENDED_DMV_PRESENT_FLAG_UNNAMED1 = 1, //!< Extended_DMV is present in the picture header 6604 }; 6605 6606 //! \brief REFPIC_FLAG 6607 //! \details 6608 //! For a BI picture, REFPIC flag must set to 0For I and P picture, REFPIC 6609 //! flag must set to 0.For a B picture, REFPIC flag must set to 0, except 6610 //! for a B-field in interlaced field mode which can be 0 or 1 (e.g. the top 6611 //! B field can be used as a reference for decoding its corresponding bottom 6612 //! B-field in a field pair).In VLD mode, this flag cannot be used as an 6613 //! optimization signaling for an I or P picture that is not used as a 6614 //! reference picture.This field is used in both VC1 VLD mode and IT 6615 //! mode. It is the same parameter as bPicDeblockConfined[bit2] in VC1 6616 //! spec.The Intra Picture Flag, Backward Prediction Present Flag and 6617 //! RefPicFlag are used to derive the picture type, as specified in PTYPE 6618 //! for a frame, and in FPTYPE for a field, in VC1 VLD and IT mode. 6619 enum REFPIC_FLAG 6620 { 6621 REFPIC_FLAG_UNNAMED0 = 0, //!< the current picture after decoded, will never used as a reference picture 6622 REFPIC_FLAG_UNNAMED1 = 1, //!< the current picture after decoded, will be used as a reference picture later 6623 }; 6624 6625 //! \name Initializations 6626 6627 //! \brief Explicit member initialization function 6628 MFD_VC1_SHORT_PIC_STATE_CMD(); 6629 6630 static const size_t dwSize = 5; 6631 static const size_t byteSize = 20; 6632 }; 6633 6634 //! 6635 //! \brief MFX_VC1_DIRECTMODE_STATE 6636 //! \details 6637 //! This is a picture level command and should be issued only once, even for 6638 //! a multi-slices picture. There is only one DMV buffer for read (when 6639 //! processing a B-picture) and one for write (when processing a P-Picture). 6640 //! Each DMV record is 64 bits per MB, to store the top and bottom field 6641 //! MVs (32-bit MVx,y each). 6642 //! 6643 struct MFX_VC1_DIRECTMODE_STATE_CMD 6644 { 6645 union 6646 { 6647 //!< DWORD 0 6648 struct 6649 { 6650 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6651 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6652 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6653 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6654 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6655 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6656 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6657 }; 6658 uint32_t Value; 6659 } DW0; 6660 union 6661 { 6662 //!< DWORD 1 6663 struct 6664 { 6665 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6666 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Write Buffer Base Address for the Current Picture 6667 }; 6668 uint32_t Value; 6669 } DW1; 6670 union 6671 { 6672 //!< DWORD 2 6673 struct 6674 { 6675 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Write Buffer Base Address for the Current Picture [47:32] 6676 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6677 }; 6678 uint32_t Value; 6679 } DW2; 6680 union 6681 { 6682 //!< DWORD 3 6683 struct 6684 { 6685 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6686 uint32_t DirectMvWriteBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6687 uint32_t DirectMvWriteBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Write Buffer - Memory Compression Enable 6688 uint32_t DirectMvWriteBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6689 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6690 uint32_t DirectMvWriteBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6691 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6692 }; 6693 uint32_t Value; 6694 } DW3; 6695 union 6696 { 6697 //!< DWORD 4 6698 struct 6699 { 6700 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 6701 uint32_t DirectMvReadBufferBaseAddressForTheReferencePicture : __CODEGEN_BITFIELD( 6, 31) ; //!< Direct MV Read Buffer Base Address for the Reference Picture 6702 }; 6703 uint32_t Value; 6704 } DW4; 6705 union 6706 { 6707 //!< DWORD 5 6708 struct 6709 { 6710 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPicture4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Direct MV Read Buffer Base Address for the Current Picture [47:32] 6711 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 6712 }; 6713 uint32_t Value; 6714 } DW5; 6715 union 6716 { 6717 //!< DWORD 6 6718 struct 6719 { 6720 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 6721 uint32_t DirectMvReadBufferBaseAddressForTheCurrentPictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6722 uint32_t DirectMvReadBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Direct MV Read Buffer - Memory Compression Enable 6723 uint32_t DirectMvReadBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6724 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 6725 uint32_t DirectMvReadBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6726 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 6727 }; 6728 uint32_t Value; 6729 } DW6; 6730 6731 //! \name Local enumerations 6732 6733 enum SUBOPCODE_B 6734 { 6735 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 6736 }; 6737 6738 enum SUBOPCODE_A 6739 { 6740 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 6741 }; 6742 6743 enum MEDIA_COMMAND_OPCODE 6744 { 6745 MEDIA_COMMAND_OPCODE_VC1COMMON = 2, //!< No additional details 6746 }; 6747 6748 enum PIPELINE 6749 { 6750 PIPELINE_MFXVC1DIRECTMODESTATE = 2, //!< No additional details 6751 }; 6752 6753 enum COMMAND_TYPE 6754 { 6755 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6756 }; 6757 6758 //! \brief DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6759 //! \details 6760 //! This field controls the priority of arbitration used in the GAC/GAM 6761 //! pipeline for this surface. 6762 enum DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6763 { 6764 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6765 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6766 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6767 DIRECT_MV_WRITE_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6768 }; 6769 6770 //! \brief DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6771 //! \details 6772 //! Distinguishes Vertical from Horizontal compression. Please refer to 6773 //! vol1a 6774 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6775 //! section for more details. 6776 enum DIRECT_MV_WRITE_BUFFER__MEMORY_COMPRESSION_MODE 6777 { 6778 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6779 DIRECT_MV_WRITE_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6780 }; 6781 6782 //! \brief DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6783 //! \details 6784 //! <b>For Media Surfaces:</b> 6785 //! This field specifies the tiled resource mode. 6786 enum DIRECT_MV_WRITE_BUFFER__TILED_RESOURCE_MODE 6787 { 6788 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6789 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6790 DIRECT_MV_WRITE_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6791 }; 6792 6793 //! \brief DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6794 //! \details 6795 //! This field controls the priority of arbitration used in the GAC/GAM 6796 //! pipeline for this surface. 6797 enum DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE__ARBITRATION_PRIORITY_CONTROL 6798 { 6799 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 6800 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 6801 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 6802 DIRECT_MV_READ_BUFFER_BASE_ADDRESS_FOR_THE_CURRENT_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 6803 }; 6804 6805 //! \brief DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6806 //! \details 6807 //! Distinguishes Vertical from Horizontal compression. Please refer to 6808 //! vol1a 6809 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 6810 //! section for more details. 6811 enum DIRECT_MV_READ_BUFFER__MEMORY_COMPRESSION_MODE 6812 { 6813 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 6814 DIRECT_MV_READ_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 6815 }; 6816 6817 //! \brief DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6818 //! \details 6819 //! <b>For Media Surfaces:</b> 6820 //! This field specifies the tiled resource mode. 6821 enum DIRECT_MV_READ_BUFFER__TILED_RESOURCE_MODE 6822 { 6823 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 6824 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 6825 DIRECT_MV_READ_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 6826 }; 6827 6828 //! \name Initializations 6829 6830 //! \brief Explicit member initialization function 6831 MFX_VC1_DIRECTMODE_STATE_CMD(); 6832 6833 static const size_t dwSize = 7; 6834 static const size_t byteSize = 28; 6835 }; 6836 6837 //! 6838 //! \brief MFD_VC1_BSD_OBJECT 6839 //! \details 6840 //! The MFD_VC1_BSD_OBJECT command is the only primitive command for the VC1 6841 //! Decoding Pipeline. The macroblock data portion of the bitstream is 6842 //! loaded as indirect data object.Before issuing a MFD_VC1_BSD_OBJECT 6843 //! command, all VC1 states of the MFD Engine need to be valid. Therefore 6844 //! the commands used to set these states need to have been issued prior to 6845 //! the issue of a MFD_VC1_BSD_OBJECT command.VC1 deblock filter kernel 6846 //! cross the slice boundary if in the last MB row of a slice, so need to 6847 //! know the last MB row of a slice to disable the edge mask. There is why 6848 //! VC1 BSD hardware need to know the end of MB address for the current 6849 //! slice. As such no more phantom slice is needed for VC1, as long as the 6850 //! driver will program both start MB address in the current slice and the 6851 //! start MB address of the next slice. As a result, we can also support 6852 //! multiple picture state commands in between slices. 6853 //! 6854 struct MFD_VC1_BSD_OBJECT_CMD 6855 { 6856 union 6857 { 6858 //!< DWORD 0 6859 struct 6860 { 6861 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6862 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6863 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6864 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6865 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6866 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6867 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6868 }; 6869 uint32_t Value; 6870 } DW0; 6871 union 6872 { 6873 //!< DWORD 1 6874 struct 6875 { 6876 uint32_t IndirectBsdDataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect BSD Data Length 6877 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6878 }; 6879 uint32_t Value; 6880 } DW1; 6881 union 6882 { 6883 //!< DWORD 2 6884 struct 6885 { 6886 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 6887 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 6888 }; 6889 uint32_t Value; 6890 } DW2; 6891 union 6892 { 6893 //!< DWORD 3 6894 struct 6895 { 6896 uint32_t NextSliceVerticalPosition : __CODEGEN_BITFIELD( 0, 8) ; //!< Next Slice Vertical Position 6897 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 6898 uint32_t SliceStartVerticalPosition : __CODEGEN_BITFIELD(16, 23) ; //!< Slice Start Vertical Position 6899 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 6900 }; 6901 uint32_t Value; 6902 } DW3; 6903 union 6904 { 6905 //!< DWORD 4 6906 struct 6907 { 6908 uint32_t FirstmbbitoffsetFirstMacroblockBitOffset : __CODEGEN_BITFIELD( 0, 2) ; //!< FirstMbBitOffset (First Macroblock Bit Offset ) 6909 uint32_t Reserved131 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 6910 uint32_t EmulationPreventionBytePresent : __CODEGEN_BITFIELD( 4, 4) ; //!< EMULATION_PREVENTION_BYTE_PRESENT 6911 uint32_t Reserved133 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 6912 uint32_t FirstMbByteOffsetOfSliceDataOrSliceHeader : __CODEGEN_BITFIELD(16, 31) ; //!< First_MB_Byte_Offset of Slice Data or Slice Header 6913 }; 6914 uint32_t Value; 6915 } DW4; 6916 6917 //! \name Local enumerations 6918 6919 enum SUBOPCODE_B 6920 { 6921 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 6922 }; 6923 6924 enum SUBOPCODE_A 6925 { 6926 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 6927 }; 6928 6929 enum MEDIA_COMMAND_OPCODE 6930 { 6931 MEDIA_COMMAND_OPCODE_VC1DEC = 2, //!< No additional details 6932 }; 6933 6934 enum PIPELINE 6935 { 6936 PIPELINE_MFXMULTIDW = 2, //!< No additional details 6937 }; 6938 6939 enum COMMAND_TYPE 6940 { 6941 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 6942 }; 6943 6944 enum EMULATION_PREVENTION_BYTE_PRESENT 6945 { 6946 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED0 = 0, //!< H/W needs to perform Emulation Byte Removal 6947 EMULATION_PREVENTION_BYTE_PRESENT_UNNAMED1 = 1, //!< H/W does not need to perform Emulation Byte Removal 6948 }; 6949 6950 //! \name Initializations 6951 6952 //! \brief Explicit member initialization function 6953 MFD_VC1_BSD_OBJECT_CMD(); 6954 6955 static const size_t dwSize = 5; 6956 static const size_t byteSize = 20; 6957 }; 6958 6959 //! 6960 //! \brief MFX_JPEG_PIC_STATE 6961 //! \details 6962 //! 6963 //! 6964 struct MFX_JPEG_PIC_STATE_CMD 6965 { 6966 union 6967 { 6968 //!< DWORD 0 6969 struct 6970 { 6971 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 6972 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 6973 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 6974 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 6975 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 6976 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 6977 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 6978 }; 6979 uint32_t Value; 6980 } DW0; 6981 union 6982 { 6983 //!< DWORD 1 6984 struct 6985 { 6986 uint32_t OutputMcuStructure : __CODEGEN_BITFIELD( 0, 2) ; //!< OUTPUT_MCU_STRUCTURE, Encoder Only 6987 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved, Encoder Only 6988 uint32_t InputSurfaceFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< INPUT_SURFACE_FORMAT_YUV, Encoder Only 6989 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 20) ; //!< Reserved, Encoder Only 6990 uint32_t PixelsInVerticalLastMcu : __CODEGEN_BITFIELD(21, 25) ; //!< Pixels In Vertical Last MCU, Encoder Only 6991 uint32_t PixelsInHorizontalLastMcu : __CODEGEN_BITFIELD(26, 30) ; //!< Pixels In Horizontal Last MCU, Encoder Only 6992 uint32_t Reserved63 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved, Encoder Only 6993 } Obj0; 6994 struct 6995 { 6996 uint32_t InputFormatYuv : __CODEGEN_BITFIELD( 0, 2) ; //!< INPUT_FORMAT_YUV, Decoder Only 6997 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved, Decoder Only 6998 uint32_t Rotation : __CODEGEN_BITFIELD( 4, 5) ; //!< ROTATION, Decoder Only 6999 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved, Decoder Only 7000 uint32_t OutputFormatYuv : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_FORMAT_YUV, Decoder Only 7001 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved, Decoder Only 7002 uint32_t AverageDownSampling : __CODEGEN_BITFIELD(16, 16) ; //!< AVERAGE_DOWN_SAMPLING, Decoder Only 7003 uint32_t VerticalDownSamplingEnable : __CODEGEN_BITFIELD(17, 17) ; //!< VERTICAL_DOWN_SAMPLING_ENABLE, Decoder Only 7004 uint32_t HorizontalDownSamplingEnable : __CODEGEN_BITFIELD(18, 18) ; //!< HORIZONTAL_DOWN_SAMPLING_ENABLE, Decoder Only 7005 uint32_t Reserved51 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved, Decoder Only 7006 uint32_t VerticalUpSamplingEnable : __CODEGEN_BITFIELD(20, 20) ; //!< VERTICAL_UP_SAMPLING_ENABLE, Decoder Only 7007 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved, Decoder Only 7008 } Obj1; 7009 uint32_t Value; 7010 } DW1; 7011 union 7012 { 7013 //!< DWORD 2 7014 struct 7015 { 7016 uint32_t FrameWidthInBlocksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blocks Minus 1, Decoder Only 7017 uint32_t Reserved77 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Decoder Only 7018 uint32_t FrameHeightInBlocksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blocks Minus 1, Decoder Only 7019 uint32_t OutputPixelNormalize : __CODEGEN_BITFIELD(29, 29) ; //!< OUTPUT_PIXEL_NORMALIZE, Decoder Only 7020 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved, Decoder Only 7021 } Obj0; 7022 struct 7023 { 7024 uint32_t FrameWidthInBlksMinus1 : __CODEGEN_BITFIELD( 0, 12) ; //!< Frame Width In Blks Minus 1, Encoder Only 7025 uint32_t Roundingquant : __CODEGEN_BITFIELD(13, 15) ; //!< ROUNDINGQUANT, Encoder Only 7026 uint32_t FrameHeightInBlksMinus1 : __CODEGEN_BITFIELD(16, 28) ; //!< Frame Height In Blks Minus 1, Encoder Only 7027 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved, Encoder Only 7028 } Obj1; 7029 uint32_t Value; 7030 } DW2; 7031 7032 //! \name Local enumerations 7033 7034 enum SUBOPCODE_B 7035 { 7036 SUBOPCODE_B_MEDIA = 0, //!< No additional details 7037 }; 7038 7039 enum SUBOPCODE_A 7040 { 7041 SUBOPCODE_A_COMMON = 0, //!< No additional details 7042 }; 7043 7044 enum MEDIA_COMMAND_OPCODE 7045 { 7046 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 7047 }; 7048 7049 enum PIPELINE 7050 { 7051 PIPELINE_MFXMULTIDW = 2, //!< No additional details 7052 }; 7053 7054 enum COMMAND_TYPE 7055 { 7056 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7057 }; 7058 7059 //! \brief OUTPUT_MCU_STRUCTURE 7060 //! \details 7061 //! <p></p> 7062 //! Output MCU Structure(<b>OutputMcuStructure</b>) should be set 7063 //! accordingly for each Input Surface Format 7064 //! YUV(<b>InputSurfaceFormatYUV</b>): 7065 //! <ul> 7066 //! <li>If <b>InputSurfaceFormatYUV</b> is set to NV12, 7067 //! <b>OutputMCUStructure</b> is set to YUV420.</li> 7068 //! <li>If <b>InputSurfaceFormatYUV</b> is set to UYVY or YUY2, 7069 //! <b>OutputMCUStructure</b> is set to YUV422H_2Y.</li> 7070 //! <li>If <b>InputSurfaceFormatYUV</b> is set to Y8, 7071 //! <b>OutputMCuStructure</b> is set to YUV400.</li> 7072 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB (or GBR, BGR, 7073 //! YUV), <b>OutputMCuStructure</b> is set to RGB.</li> 7074 //! <li>If <b>InputSurfaceFormatYUV</b> is set to RGB, the order of 7075 //! encoded blocks in MCU will be same as the order of input image 7076 //! components. 7077 //! If the order of input image components is RGB (or GBR, BGR, YUV), 7078 //! then the order of blocks will be RGB (or GBR, BGR, YUV 7079 //! respectively).</li> 7080 //! </ul> 7081 //! <p></p> 7082 enum OUTPUT_MCU_STRUCTURE 7083 { 7084 OUTPUT_MCU_STRUCTURE_YUV_400 = 0, //!< Grayscale Image 7085 OUTPUT_MCU_STRUCTURE_YUV_420 = 1, //!< Both horizontally and vertically chroma 2:1 subsampled 7086 OUTPUT_MCU_STRUCTURE_YUV_422H2Y = 2, //!< Horizontally chroma 2:1 subsampled - horizontal 2 Y-blocks, 1 U and 1 V block 7087 OUTPUT_MCU_STRUCTURE_RGB = 3, //!< RGB or YUV444: No subsample 7088 OUTPUT_MCU_STRUCTURE_UNNAMED_4 = 4, //!< No additional details 7089 OUTPUT_MCU_STRUCTURE_UNNAMED5 = 5, //!< No additional details 7090 OUTPUT_MCU_STRUCTURE_UNNAMED6 = 6, //!< No additional details 7091 OUTPUT_MCU_STRUCTURE_UNNAMED7 = 7, //!< No additional details 7092 }; 7093 7094 enum INPUT_FORMAT_YUV 7095 { 7096 INPUT_FORMAT_YUV_UNNAMED0 = 0, //!< YUV400 (grayscale image) 7097 INPUT_FORMAT_YUV_UNNAMED1 = 1, //!< YUV420 7098 INPUT_FORMAT_YUV_UNNAMED2 = 2, //!< YUV422H_2Y (Horizontally chroma 2:1 subsampled) - horizontal 2 Y-block, 1U and 1V 7099 INPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUV444 7100 INPUT_FORMAT_YUV_UNNAMED_4 = 4, //!< YUV411 7101 INPUT_FORMAT_YUV_UNNAMED5 = 5, //!< YUV422V_2Y (Vertically chroma 2:1 subsampled) - vertical 2 Y-blocks, 1U and 1V 7102 INPUT_FORMAT_YUV_UNNAMED6 = 6, //!< YUV422H_4Y - 2x2 Y-blocks, vertical 2U and 2V 7103 INPUT_FORMAT_YUV_UNNAMED7 = 7, //!< YUV422V_4Y - 2x2 Y-blocks, horizontal 2U and 2V 7104 }; 7105 7106 //! \brief ROTATION 7107 //! \details 7108 //! Rotation can be set to 01b, 10b, or 11b when OutputFormatYUV is set to 7109 //! 0000b. For other OutputFormatYUV, Rotation is not allowed. 7110 enum ROTATION 7111 { 7112 ROTATION_UNNAMED0 = 0, //!< no rotation 7113 ROTATION_UNNAMED1 = 1, //!< rotate clockwise 90 degree 7114 ROTATION_UNNAMED2 = 2, //!< rotate counter-clockwise 90 degree (same as rotating 270 degree clockwise) 7115 ROTATION_UNNAMED3 = 3, //!< rotate 180 degree (NOT the same as flipped on the x-axis) 7116 }; 7117 7118 //! \brief OUTPUT_FORMAT_YUV 7119 //! \details 7120 //! This field specifies the surface format to write the decoded JPEG 7121 //! image.Note that any non-interleaved JPEG input should be set to "0000". 7122 //! For the interleaved input Scan data, it can be set either "0000" or the 7123 //! corresponding format. 7124 enum OUTPUT_FORMAT_YUV 7125 { 7126 OUTPUT_FORMAT_YUV_UNNAMED0 = 0, //!< 3 separate plane for Y, U, and V respectively 7127 OUTPUT_FORMAT_YUV_UNNAMED1 = 1, //!< NV12 for chroma 4:2:0 7128 OUTPUT_FORMAT_YUV_UNNAMED2 = 2, //!< UYVY for chroma 4:2:2 7129 OUTPUT_FORMAT_YUV_UNNAMED3 = 3, //!< YUY2 for chroma 4:2:2 7130 }; 7131 7132 //! \brief INPUT_SURFACE_FORMAT_YUV 7133 //! \details 7134 //! This field specifies the surface format to read a YUV image data 7135 enum INPUT_SURFACE_FORMAT_YUV 7136 { 7137 INPUT_SURFACE_FORMAT_YUV_UNNAMED0 = 0, //!< Reserved 7138 INPUT_SURFACE_FORMAT_YUV_NV12 = 1, //!< NV12 for chroma 4:2:0 7139 INPUT_SURFACE_FORMAT_YUV_UYVY = 2, //!< UYVY for chroma 4:2:2 7140 INPUT_SURFACE_FORMAT_YUV_YUY2 = 3, //!< YUY2 for chroma 4:2:2 7141 INPUT_SURFACE_FORMAT_YUV_Y8 = 4, //!< Y8 for chroma400 Y-only image 7142 INPUT_SURFACE_FORMAT_YUV_RGB = 5, //!< RGB or YUV for chroma 4:4:4 7143 }; 7144 7145 //! \brief AVERAGE_DOWN_SAMPLING 7146 //! \details 7147 //! This flag is used to select a down-sampling method when 7148 //! <b>VertDownSamplingEnb</b> or <b>HoriDownSamplingEnb</b> is set to 1. 7149 enum AVERAGE_DOWN_SAMPLING 7150 { 7151 AVERAGE_DOWN_SAMPLING_UNNAMED0 = 0, //!< Drop every other line (or column) pixels 7152 AVERAGE_DOWN_SAMPLING_UNNAMED1 = 1, //!< Average neighboring two pixels 7153 }; 7154 7155 //! \brief VERTICAL_DOWN_SAMPLING_ENABLE 7156 //! \details 7157 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7158 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7159 //! enable this flag, the input should be interleaved Scan, 7160 //! <b>InputFormatYUV</b> should be set to YUV422H_2Y or YUV422H_4Y, and 7161 //! <b>OutputFormatYUV</b> should be set to NV12. 7162 enum VERTICAL_DOWN_SAMPLING_ENABLE 7163 { 7164 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7165 VERTICAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical down-sampling 7166 }; 7167 7168 //! \brief HORIZONTAL_DOWN_SAMPLING_ENABLE 7169 //! \details 7170 //! Only applied to chroma blocks. This flag is used for 2:1 horizontal 7171 //! down-sampling for chroma 422 and outputting chroma420 NV21 format. To 7172 //! enable this flag, the input should be interleaved Scan, 7173 //! <b>InputFormatYUV</b> should be set to YUV422V_2Y or YUV422V_4Y, and 7174 //! <b>OutputFormatYUV</b> should be set to NV12. 7175 enum HORIZONTAL_DOWN_SAMPLING_ENABLE 7176 { 7177 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no down-sampling 7178 HORIZONTAL_DOWN_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 horizonatl down-sampling 7179 }; 7180 7181 //! \brief VERTICAL_UP_SAMPLING_ENABLE 7182 //! \details 7183 //! Only applied to chroma blocks. This flag is used for 2:1 vertical 7184 //! up-sampling for chroma 420 and outputting chroma422 YUY2 or UYVY format. 7185 //! To enable this flag, the input should be interleaved Scan, 7186 //! <b>InputFormatYUV</b> should be set to YUV420, and 7187 //! <b>OutputFormatYUV</b> should be set to YUY2 or UYVY. 7188 enum VERTICAL_UP_SAMPLING_ENABLE 7189 { 7190 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED0 = 0, //!< no up-sampling 7191 VERTICAL_UP_SAMPLING_ENABLE_UNNAMED1 = 1, //!< 2:1 vertical up-sampling 7192 }; 7193 7194 //! \brief ROUNDINGQUANT 7195 //! \details 7196 //! Rounding value applied to quantization output 7197 enum ROUNDINGQUANT 7198 { 7199 ROUNDINGQUANT_UNNAMED0 = 0, //!< 1/2 7200 ROUNDINGQUANT_UNNAMED1 = 1, //!< (1/2 - 1/128) 7201 ROUNDINGQUANT_UNNAMED2 = 2, //!< (1/2 + 1/128) 7202 ROUNDINGQUANT_UNNAMED3 = 3, //!< (1/2 - 1/64) 7203 ROUNDINGQUANT_UNNAMED_4 = 4, //!< (1/2 + 1/64) 7204 ROUNDINGQUANT_UNNAMED5 = 5, //!< (1/2 - 1/32) 7205 ROUNDINGQUANT_UNNAMED6 = 6, //!< (1/2 - 1/16) 7206 ROUNDINGQUANT_UNNAMED7 = 7, //!< (1/2 - 1/8) 7207 }; 7208 7209 //! \brief OUTPUT_PIXEL_NORMALIZE 7210 //! \details 7211 //! JPEG decoded output pixels for Y and U/V in order to adjust display YUV 7212 //! range. 7213 enum OUTPUT_PIXEL_NORMALIZE 7214 { 7215 OUTPUT_PIXEL_NORMALIZE_UNNAMED0 = 0, //!< No Normalization 7216 OUTPUT_PIXEL_NORMALIZE_UNNAMED1 = 1, //!< Normalize output pixels from [0,255] to [16,235] 7217 }; 7218 7219 //! \name Initializations 7220 7221 //! \brief Explicit member initialization function 7222 MFX_JPEG_PIC_STATE_CMD(); 7223 7224 static const size_t dwSize = 3; 7225 static const size_t byteSize = 12; 7226 }; 7227 7228 //! 7229 //! \brief MFC_JPEG_HUFF_TABLE_STATE 7230 //! \details 7231 //! This Huffman table commands contains both DC and AC tables for either 7232 //! luma or chroma. Once a Huffman table has been defined for a particular 7233 //! destination, it replaces the previous tables stored in that destination 7234 //! and shall be used in the remaining Scans of the current image. Two 7235 //! Huffman tables for luma and chroma will be sent to H/W, and chroma table 7236 //! is used for both U and V. 7237 //! 7238 struct MFC_JPEG_HUFF_TABLE_STATE_CMD 7239 { 7240 union 7241 { 7242 //!< DWORD 0 7243 struct 7244 { 7245 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7246 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7247 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7248 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7249 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7250 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7251 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7252 }; 7253 uint32_t Value; 7254 } DW0; 7255 union 7256 { 7257 //!< DWORD 1 7258 struct 7259 { 7260 uint32_t HuffTableId : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFF_TABLE_ID 7261 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 7262 }; 7263 uint32_t Value; 7264 } DW1; 7265 7266 uint32_t DcTable[12]; //!< DC_TABLE 7267 7268 uint32_t AcTable[162]; //!< AC_TABLE 7269 7270 //! \name Local enumerations 7271 7272 enum SUBOPCODE_B 7273 { 7274 SUBOPCODE_B_MEDIA = 3, //!< No additional details 7275 }; 7276 7277 enum SUBOPCODE_A 7278 { 7279 SUBOPCODE_A_COMMON = 2, //!< No additional details 7280 }; 7281 7282 enum MEDIA_COMMAND_OPCODE 7283 { 7284 MEDIA_COMMAND_OPCODE_JPEG = 7, //!< No additional details 7285 }; 7286 7287 enum PIPELINE 7288 { 7289 PIPELINE_MFCJPEGHUFFTABLESTATE = 2, //!< No additional details 7290 }; 7291 7292 enum COMMAND_TYPE 7293 { 7294 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7295 }; 7296 7297 //! \brief HUFF_TABLE_ID 7298 //! \details 7299 //! Huffman table destination identifier will specify one of two 7300 //! destinations at the encoder into which the Huffman table must be stored. 7301 enum HUFF_TABLE_ID 7302 { 7303 HUFF_TABLE_ID_UNNAMED0 = 0, //!< Huffman table 0 7304 HUFF_TABLE_ID_UNNAMED1 = 1, //!< Huffman table 1 7305 }; 7306 7307 //! \name Initializations 7308 7309 //! \brief Explicit member initialization function 7310 MFC_JPEG_HUFF_TABLE_STATE_CMD(); 7311 7312 static const size_t dwSize = 176; 7313 static const size_t byteSize = 704; 7314 }; 7315 7316 //! 7317 //! \brief MFD_JPEG_BSD_OBJECT 7318 //! \details 7319 //! 7320 //! 7321 struct MFD_JPEG_BSD_OBJECT_CMD 7322 { 7323 union 7324 { 7325 //!< DWORD 0 7326 struct 7327 { 7328 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7329 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7330 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7331 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7332 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7333 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7334 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7335 }; 7336 uint32_t Value; 7337 } DW0; 7338 union 7339 { 7340 //!< DWORD 1 7341 struct 7342 { 7343 uint32_t IndirectDataLength ; //!< Indirect Data Length 7344 }; 7345 uint32_t Value; 7346 } DW1; 7347 union 7348 { 7349 //!< DWORD 2 7350 struct 7351 { 7352 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 7353 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7354 }; 7355 uint32_t Value; 7356 } DW2; 7357 union 7358 { 7359 //!< DWORD 3 7360 struct 7361 { 7362 uint32_t ScanVerticalPosition : __CODEGEN_BITFIELD( 0, 12) ; //!< Scan Vertical Position 7363 uint32_t Reserved109 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 7364 uint32_t ScanHorizontalPosition : __CODEGEN_BITFIELD(16, 28) ; //!< Scan Horizontal Position 7365 uint32_t Reserved125 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 7366 }; 7367 uint32_t Value; 7368 } DW3; 7369 union 7370 { 7371 //!< DWORD 4 7372 struct 7373 { 7374 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7375 uint32_t Reserved154 : __CODEGEN_BITFIELD(26, 26) ; //!< Reserved 7376 uint32_t ScanComponents : __CODEGEN_BITFIELD(27, 29) ; //!< Scan Components 7377 uint32_t Interleaved : __CODEGEN_BITFIELD(30, 30) ; //!< INTERLEAVED 7378 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7379 }; 7380 uint32_t Value; 7381 } DW4; 7382 union 7383 { 7384 //!< DWORD 5 7385 struct 7386 { 7387 uint32_t Restartinterval16Bit : __CODEGEN_BITFIELD( 0, 15) ; //!< RestartInterval(16 bit) 7388 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 7389 }; 7390 uint32_t Value; 7391 } DW5; 7392 7393 //! \name Local enumerations 7394 7395 enum SUBOPCODE_B 7396 { 7397 SUBOPCODE_B_UNNAMED8 = 8, //!< No additional details 7398 }; 7399 7400 enum SUBOPCODE_A 7401 { 7402 SUBOPCODE_A_UNNAMED1 = 1, //!< No additional details 7403 }; 7404 7405 enum MEDIA_COMMAND_OPCODE 7406 { 7407 MEDIA_COMMAND_OPCODE_JPEGDEC = 7, //!< No additional details 7408 }; 7409 7410 enum PIPELINE 7411 { 7412 PIPELINE_MFDJPEGBSDOBJECT = 2, //!< No additional details 7413 }; 7414 7415 enum COMMAND_TYPE 7416 { 7417 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7418 }; 7419 7420 enum INTERLEAVED 7421 { 7422 INTERLEAVED_NON_INTERLEAVED = 0, //!< one component in the Scan 7423 INTERLEAVED_INTERLEAVED = 1, //!< multiple components in the Scan 7424 }; 7425 7426 //! \name Initializations 7427 7428 //! \brief Explicit member initialization function 7429 MFD_JPEG_BSD_OBJECT_CMD(); 7430 7431 static const size_t dwSize = 6; 7432 static const size_t byteSize = 24; 7433 }; 7434 7435 //! 7436 //! \brief MFC_JPEG_SCAN_OBJECT 7437 //! \details 7438 //! Encoder Only 7439 //! 7440 struct MFC_JPEG_SCAN_OBJECT_CMD 7441 { 7442 union 7443 { 7444 //!< DWORD 0 7445 struct 7446 { 7447 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7448 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7449 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 7450 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 7451 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7452 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7453 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7454 }; 7455 uint32_t Value; 7456 } DW0; 7457 union 7458 { 7459 //!< DWORD 1 7460 struct 7461 { 7462 uint32_t McuCount : __CODEGEN_BITFIELD( 0, 25) ; //!< MCU Count 7463 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 7464 }; 7465 uint32_t Value; 7466 } DW1; 7467 union 7468 { 7469 //!< DWORD 2 7470 struct 7471 { 7472 uint32_t RestartInterval : __CODEGEN_BITFIELD( 0, 15) ; //!< Restart Interval 7473 uint32_t IsLastScan : __CODEGEN_BITFIELD(16, 16) ; //!< IS_LAST_SCAN 7474 uint32_t HeadPresentFlag : __CODEGEN_BITFIELD(17, 17) ; //!< HEAD_PRESENT_FLAG 7475 uint32_t HuffmanDcTable : __CODEGEN_BITFIELD(18, 20) ; //!< HUFFMAN_DC_TABLE 7476 uint32_t Reserved85 : __CODEGEN_BITFIELD(21, 21) ; //!< Reserved 7477 uint32_t HuffmanAcTable : __CODEGEN_BITFIELD(22, 24) ; //!< HUFFMAN_AC_TABLE 7478 uint32_t Reserved89 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 7479 }; 7480 uint32_t Value; 7481 } DW2; 7482 7483 //! \name Local enumerations 7484 7485 enum SUBOPCODE_B 7486 { 7487 SUBOPCODE_B_UNNAMED9 = 9, //!< No additional details 7488 }; 7489 7490 enum SUBOPCODE_A 7491 { 7492 SUBOPCODE_A_UNNAMED2 = 2, //!< No additional details 7493 }; 7494 7495 enum MEDIA_COMMAND_OPCODE 7496 { 7497 MEDIA_COMMAND_OPCODE_JPEGENC = 7, //!< No additional details 7498 }; 7499 7500 enum PIPELINE 7501 { 7502 PIPELINE_MFCJPEGSCANOBJECT = 2, //!< No additional details 7503 }; 7504 7505 enum COMMAND_TYPE 7506 { 7507 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7508 }; 7509 7510 //! \brief IS_LAST_SCAN 7511 //! \details 7512 //! If this flag is set, then HW will insert EOI (0xFFD9) to the end of Scan 7513 //! encoded bitstream. 7514 enum IS_LAST_SCAN 7515 { 7516 IS_LAST_SCAN_UNNAMED0 = 0, //!< Not the last Scan. 7517 IS_LAST_SCAN_UNNAMED1 = 1, //!< Indicates that the current Scan is the last one. 7518 }; 7519 7520 //! \brief HEAD_PRESENT_FLAG 7521 //! \details 7522 //! If this flag is set to 0, then no MFC_JPEG_PAK_INSERT_OBJECT commands 7523 //! will be sent. 7524 //! If this flag is set to 1, then one or more 7525 //! MFC_JPEG_PAK_INSERT_OBJECT commands will be sent after 7526 //! MFC_JPEG_SCAN_OBJECT command. 7527 enum HEAD_PRESENT_FLAG 7528 { 7529 HEAD_PRESENT_FLAG_UNNAMED0 = 0, //!< No insertion into the output bitstream buffer before Scan encoded bitstream 7530 HEAD_PRESENT_FLAG_UNNAMED1 = 1, //!< Headers, tables, App data insertion into the output bitstream buffer. HW will insert the insertion data before the Scan encoded bitstream. 7531 }; 7532 7533 //! \brief HUFFMAN_DC_TABLE 7534 //! \details 7535 //! DC Huffman table destination selector specifies one of two possible DC 7536 //! table destinations for each Y, U, V, or R, G, B. 7537 //! The DC Huffman tables shall have been loaded in destination 0 and 1 7538 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7539 enum HUFFMAN_DC_TABLE 7540 { 7541 HUFFMAN_DC_TABLE_BIT20V0 = 0, //!< The third image component must use the DC table 0. 7542 HUFFMAN_DC_TABLE_BIT19U0 = 0, //!< The second image component must use the DC table 0. 7543 HUFFMAN_DC_TABLE_BIT18Y0 = 0, //!< The first image component must use the DC table 0. 7544 HUFFMAN_DC_TABLE_BIT18Y1 = 1, //!< The first image component must use the DC table 1. 7545 HUFFMAN_DC_TABLE_BIT19U1 = 2, //!< The second image component must use the DC table 1. 7546 HUFFMAN_DC_TABLE_BIT20V1 = 4, //!< The third image component must use the DC table 1. 7547 }; 7548 7549 //! \brief HUFFMAN_AC_TABLE 7550 //! \details 7551 //! AC Huffman table destination selector specifies one of two possible AC 7552 //! table destinations for each Y, U, V, or R, G, B. 7553 //! The AC Huffman tables must have been loaded in destination 0 and 1 7554 //! by the time of issuing MFC_JPEG_HUFF_TABLE_STATE Command. 7555 enum HUFFMAN_AC_TABLE 7556 { 7557 HUFFMAN_AC_TABLE_BIT2_4V0 = 0, //!< The third image component must use the AC table 0. 7558 HUFFMAN_AC_TABLE_BIT23U0 = 0, //!< The second image component must use the AC table 0. 7559 HUFFMAN_AC_TABLE_BIT22Y0 = 0, //!< The first image component must use the AC table 0. 7560 HUFFMAN_AC_TABLE_BIT22Y1 = 1, //!< The first image component must use the AC table 1. 7561 HUFFMAN_AC_TABLE_BIT23U1 = 2, //!< The second image component must use the AC table 1. 7562 HUFFMAN_AC_TABLE_BIT2_4V1 = 4, //!< The third image component must use the AC table 1. 7563 }; 7564 7565 //! \name Initializations 7566 7567 //! \brief Explicit member initialization function 7568 MFC_JPEG_SCAN_OBJECT_CMD(); 7569 7570 static const size_t dwSize = 3; 7571 static const size_t byteSize = 12; 7572 }; 7573 7574 //! 7575 //! \brief MFX_VP8_Encoder_CFG 7576 //! \details 7577 //! This must be the very first command to issue after the surface state, 7578 //! the pipe select and base address setting commands and must be issued 7579 //! before MFX_VP8_PIC_STATE. 7580 //! 7581 struct MFX_VP8_Encoder_CFG_CMD 7582 { 7583 union 7584 { 7585 //!< DWORD 0 7586 struct 7587 { 7588 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 7589 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7590 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 7591 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 7592 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 7593 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 7594 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 7595 }; 7596 uint32_t Value; 7597 } DW0; 7598 union 7599 { 7600 //!< DWORD 1 7601 struct 7602 { 7603 uint32_t PerformanceCounterEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Performance Counter Enable 7604 uint32_t FinalBitstreamOutputDisable : __CODEGEN_BITFIELD( 1, 1) ; //!< Final Bitstream Output Disable 7605 uint32_t TokenStatisticsOutputEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Output Enable 7606 uint32_t BitstreamStatisticsOutputEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< Bitstream Statistics Output Enable 7607 uint32_t UpdateSegmentFeatureDataFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< Update Segment Feature Data Flag 7608 uint32_t SkipFinalBitstreamWhenOverUnderFlow : __CODEGEN_BITFIELD( 5, 5) ; //!< Skip Final Bitstream when Over / Under flow 7609 uint32_t RateControlInitialPass : __CODEGEN_BITFIELD( 6, 6) ; //!< RATE_CONTROL_INITIAL_PASS 7610 uint32_t PerSegmentDeltaQindexLoopfilterDisable : __CODEGEN_BITFIELD( 7, 7) ; //!< Per Segment Delta Qindex / LoopFilter Disable 7611 uint32_t FinerBrcEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< Finer BRC Enable 7612 uint32_t CompressedBitstreamOutputDisable : __CODEGEN_BITFIELD( 9, 9) ; //!< Compressed Bitstream Output Disable 7613 uint32_t VbspunitpowerclockGatingDisable : __CODEGEN_BITFIELD(10, 10) ; //!< VBSPunitPowerClock Gating Disable 7614 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 7615 }; 7616 uint32_t Value; 7617 } DW1; 7618 union 7619 { 7620 //!< DWORD 2 7621 struct 7622 { 7623 uint32_t MaxFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 0, 0) ; //!< MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7624 uint32_t MinFrameBitCountRateControlEnableMask : __CODEGEN_BITFIELD( 1, 1) ; //!< MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7625 uint32_t MaxInterMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 2, 2) ; //!< Max Inter MB Bit Count Check Enable Mask 7626 uint32_t MaxIntraMbBitCountCheckEnableMask : __CODEGEN_BITFIELD( 3, 3) ; //!< Max Intra MB Bit Count Check Enable Mask 7627 uint32_t IntermediateBitBufferOverrunEnableMask : __CODEGEN_BITFIELD( 4, 4) ; //!< Intermediate Bit Buffer Overrun Enable Mask 7628 uint32_t FinalBistreamBufferOverrunEnableMask : __CODEGEN_BITFIELD( 5, 5) ; //!< Final Bistream Buffer Overrun Enable Mask 7629 uint32_t QindexClampHighMaskForUnderflow : __CODEGEN_BITFIELD( 6, 6) ; //!< Qindex_Clamp_High_mask for underflow 7630 uint32_t QindexClampHighMaskForOverflow : __CODEGEN_BITFIELD( 7, 7) ; //!< Qindex_Clamp_High_mask for overflow 7631 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 31) ; //!< Reserved 7632 }; 7633 uint32_t Value; 7634 } DW2; 7635 union 7636 { 7637 //!< DWORD 3 7638 struct 7639 { 7640 uint32_t MaxInterMbBitCount : __CODEGEN_BITFIELD( 0, 11) ; //!< Max Inter MB bit count 7641 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 7642 uint32_t MaxIntraMbBitCountLimit : __CODEGEN_BITFIELD(16, 27) ; //!< Max Intra MB Bit Count Limit 7643 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 7644 }; 7645 uint32_t Value; 7646 } DW3; 7647 union 7648 { 7649 //!< DWORD 4 7650 struct 7651 { 7652 uint32_t FrameBitRateMax : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Bit Rate Max 7653 uint32_t FrameBitRateMaxUnit : __CODEGEN_BITFIELD(14, 14) ; //!< FRAME_BIT_RATE_MAX_UNIT 7654 uint32_t FrameBitrateMaxUnitMode : __CODEGEN_BITFIELD(15, 15) ; //!< FRAME_BITRATE_MAX_UNIT_MODE 7655 uint32_t FrameBitRateMin : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Bit Rate Min 7656 uint32_t FrameBitRateMinUnit : __CODEGEN_BITFIELD(30, 30) ; //!< FRAME_BIT_RATE_MIN_UNIT 7657 uint32_t FrameBitrateMinUnitMode : __CODEGEN_BITFIELD(31, 31) ; //!< FRAME_BITRATE_MIN_UNIT_MODE 7658 }; 7659 uint32_t Value; 7660 } DW4; 7661 union 7662 { 7663 //!< DWORD 5 7664 struct 7665 { 7666 uint32_t FrameDeltaQindexMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Max [0] 7667 uint32_t FrameDeltaQindexMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Max[1] 7668 uint32_t FrameDeltaqIndexMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame DeltaQ Index Max[2] 7669 uint32_t FrameDeltaQindexMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Max[3] 7670 }; 7671 uint32_t Value; 7672 } DW5; 7673 union 7674 { 7675 //!< DWORD 6 7676 struct 7677 { 7678 uint32_t FrameDeltaQindexMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta QIndex Min[0] 7679 uint32_t FrameDeltaQindexMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta QIndex Min[1] 7680 uint32_t FrameDeltaQindexMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta QIndex Min[2] 7681 uint32_t FrameDeltaQindexMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta QIndex Min[3] 7682 }; 7683 uint32_t Value; 7684 } DW6; 7685 union 7686 { 7687 //!< DWORD 7 7688 struct 7689 { 7690 uint32_t PerSegmentFrameDeltaQindexMax1 ; //!< Per Segment Frame Delta QIndex Max[1] 7691 }; 7692 uint32_t Value; 7693 } DW7; 7694 union 7695 { 7696 //!< DWORD 8 7697 struct 7698 { 7699 uint32_t PerSegmentFrameDeltaQindexMin1 ; //!< Per Segment Frame Delta QIndex Min[1] 7700 }; 7701 uint32_t Value; 7702 } DW8; 7703 union 7704 { 7705 //!< DWORD 9 7706 struct 7707 { 7708 uint32_t PerSegmentFrameDeltaQindexMax2 ; //!< Per Segment Frame Delta QIndex Max[2] 7709 }; 7710 uint32_t Value; 7711 } DW9; 7712 union 7713 { 7714 //!< DWORD 10 7715 struct 7716 { 7717 uint32_t PerSegmentFrameDeltaQindexMin2 ; //!< Per Segment Frame Delta QIndex Min[2] 7718 }; 7719 uint32_t Value; 7720 } DW10; 7721 union 7722 { 7723 //!< DWORD 11 7724 struct 7725 { 7726 uint32_t PerSegmentFrameDeltaQindexMax3 ; //!< Per Segment Frame Delta QIndex Max[3] 7727 }; 7728 uint32_t Value; 7729 } DW11; 7730 union 7731 { 7732 //!< DWORD 12 7733 struct 7734 { 7735 uint32_t PerSegmentFrameDeltaQindexMin3 ; //!< Per Segment Frame Delta QIndex Min[3] 7736 }; 7737 uint32_t Value; 7738 } DW12; 7739 union 7740 { 7741 //!< DWORD 13 7742 struct 7743 { 7744 uint32_t FrameDeltaLoopFilterMax0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Max[0] 7745 uint32_t FramEdeltaLoopFilterMax1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Fram eDelta Loop Filter Max[1] 7746 uint32_t FrameDeltaLoopFilterMax2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Max[2] 7747 uint32_t FrameDeltaLoopFilterMax3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Max[3] 7748 }; 7749 uint32_t Value; 7750 } DW13; 7751 union 7752 { 7753 //!< DWORD 14 7754 struct 7755 { 7756 uint32_t FrameDeltaLoopFilterMin0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Delta Loop Filter Min[0] 7757 uint32_t FrameDeltaLoopFilterMin1 : __CODEGEN_BITFIELD( 8, 15) ; //!< Frame Delta Loop Filter Min[1] 7758 uint32_t FrameDeltaLoopFilterMin2 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Delta Loop Filter Min[2] 7759 uint32_t FrameDeltaLoopFilterMin3 : __CODEGEN_BITFIELD(24, 31) ; //!< Frame Delta Loop Filter Min[3] 7760 }; 7761 uint32_t Value; 7762 } DW14; 7763 union 7764 { 7765 //!< DWORD 15 7766 struct 7767 { 7768 uint32_t PerSegmentFrameDeltaLoopfilterMax1 ; //!< Per Segment Frame Delta LoopFilter Max[1] 7769 }; 7770 uint32_t Value; 7771 } DW15; 7772 union 7773 { 7774 //!< DWORD 16 7775 struct 7776 { 7777 uint32_t PerSegmentFrameDeltaLoopfilterMin1 ; //!< Per Segment Frame Delta LoopFilter Min[1] 7778 }; 7779 uint32_t Value; 7780 } DW16; 7781 union 7782 { 7783 //!< DWORD 17 7784 struct 7785 { 7786 uint32_t PerSegmentFrameDeltaLoopfilterMax2 ; //!< Per Segment Frame Delta LoopFilter Max[2] 7787 }; 7788 uint32_t Value; 7789 } DW17; 7790 union 7791 { 7792 //!< DWORD 18 7793 struct 7794 { 7795 uint32_t PerSegmentFrameDeltaLoopfilterMin2 ; //!< Per Segment Frame Delta LoopFilter Min[2] 7796 }; 7797 uint32_t Value; 7798 } DW18; 7799 union 7800 { 7801 //!< DWORD 19 7802 struct 7803 { 7804 uint32_t PerSegmentFrameDeltaLoopfilterMax3 ; //!< Per Segment Frame Delta LoopFilter Max[3] 7805 }; 7806 uint32_t Value; 7807 } DW19; 7808 union 7809 { 7810 //!< DWORD 20 7811 struct 7812 { 7813 uint32_t PerSegmentFrameDeltaLoopfilterMin3 ; //!< Per Segment Frame Delta LoopFilter Min[3] 7814 }; 7815 uint32_t Value; 7816 } DW20; 7817 union 7818 { 7819 //!< DWORD 21 7820 struct 7821 { 7822 uint32_t FrameBitRateMaxDelta : __CODEGEN_BITFIELD( 0, 14) ; //!< Frame Bit Rate Max Delta 7823 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 7824 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD(16, 30) ; //!< FrameBitRateMinDelta 7825 uint32_t Reserved703 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 7826 }; 7827 uint32_t Value; 7828 } DW21; 7829 union 7830 { 7831 //!< DWORD 22 7832 struct 7833 { 7834 uint32_t MinFrameWsize : __CODEGEN_BITFIELD( 0, 15) ; //!< Min Frame WSize 7835 uint32_t MinFrameWsizeUnit : __CODEGEN_BITFIELD(16, 17) ; //!< MIN_FRAME_WSIZE_UNIT 7836 uint32_t Reserved722 : __CODEGEN_BITFIELD(18, 19) ; //!< Reserved 7837 uint32_t BitstreamFormatVersion : __CODEGEN_BITFIELD(20, 22) ; //!< Bitstream Format Version 7838 uint32_t ShowFrame : __CODEGEN_BITFIELD(23, 23) ; //!< Show Frame 7839 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 7840 }; 7841 uint32_t Value; 7842 } DW22; 7843 union 7844 { 7845 //!< DWORD 23 7846 struct 7847 { 7848 uint32_t HorizontalSizeCode : __CODEGEN_BITFIELD( 0, 15) ; //!< Horizontal_Size_Code 7849 uint32_t VerticalSizeCode : __CODEGEN_BITFIELD(16, 31) ; //!< Vertical_Size_Code 7850 }; 7851 uint32_t Value; 7852 } DW23; 7853 union 7854 { 7855 //!< DWORD 24 7856 struct 7857 { 7858 uint32_t FrameHeaderBitCount ; //!< Frame Header Bit Count 7859 }; 7860 uint32_t Value; 7861 } DW24; 7862 union 7863 { 7864 //!< DWORD 25 7865 struct 7866 { 7867 uint32_t FrameHeaderBinBufferQindexUpdatePointer ; //!< Frame Header Bin Buffer Qindex Update Pointer 7868 }; 7869 uint32_t Value; 7870 } DW25; 7871 union 7872 { 7873 //!< DWORD 26 7874 struct 7875 { 7876 uint32_t FrameHeaderBinBufferLoopfilterUpdatePointer ; //!< Frame Header Bin Buffer LoopFilter Update Pointer 7877 }; 7878 uint32_t Value; 7879 } DW26; 7880 union 7881 { 7882 //!< DWORD 27 7883 struct 7884 { 7885 uint32_t FrameHeaderBinBufferTokenUpdatePointer ; //!< Frame Header Bin Buffer Token Update Pointer 7886 }; 7887 uint32_t Value; 7888 } DW27; 7889 union 7890 { 7891 //!< DWORD 28 7892 struct 7893 { 7894 uint32_t FrameHeaderBinBufferMvupdatePointer ; //!< Frame Header Bin Buffer MVUpdate Pointer 7895 }; 7896 uint32_t Value; 7897 } DW28; 7898 union 7899 { 7900 //!< DWORD 29 7901 struct 7902 { 7903 uint32_t Cv0ClampValue0 : __CODEGEN_BITFIELD( 0, 3) ; //!< CV0 - Clamp Value 0 7904 uint32_t Cv1 : __CODEGEN_BITFIELD( 4, 7) ; //!< CV1 7905 uint32_t Cv2 : __CODEGEN_BITFIELD( 8, 11) ; //!< CV2 7906 uint32_t Cv3 : __CODEGEN_BITFIELD(12, 15) ; //!< CV3 7907 uint32_t Cv4 : __CODEGEN_BITFIELD(16, 19) ; //!< CV4 7908 uint32_t Cv5 : __CODEGEN_BITFIELD(20, 23) ; //!< CV5 7909 uint32_t Cv6 : __CODEGEN_BITFIELD(24, 27) ; //!< CV6 7910 uint32_t ClampvaluesCv7 : __CODEGEN_BITFIELD(28, 31) ; //!< ClampValues - CV7 7911 }; 7912 uint32_t Value; 7913 } DW29; 7914 7915 //! \name Local enumerations 7916 7917 enum SUB_OPCODE_B 7918 { 7919 SUB_OPCODE_B_MFXVP8ENCODERCFG = 1, //!< No additional details 7920 }; 7921 7922 enum SUB_OPCODE_A 7923 { 7924 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 7925 }; 7926 7927 enum MEDIA_COMMAND_OPCODE 7928 { 7929 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 7930 }; 7931 7932 enum PIPELINE 7933 { 7934 PIPELINE_VIDEOCODEC = 2, //!< No additional details 7935 }; 7936 7937 enum COMMAND_TYPE 7938 { 7939 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 7940 }; 7941 7942 enum RATE_CONTROL_INITIAL_PASS 7943 { 7944 RATE_CONTROL_INITIAL_PASS_SUBSEQUENCEPASSES = 0, //!< No additional details 7945 RATE_CONTROL_INITIAL_PASS_INITIALPASS = 1, //!< No additional details 7946 }; 7947 7948 //! \brief MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7949 //! \details 7950 //! Enable Max. Frame Rate Control. 7951 //! This is a mask bit controlling if the condition of frame level bit 7952 //! count is greater than or equal to FrameBitRateMax. 7953 enum MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7954 { 7955 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS control register. 7956 MAX_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) >= (Frame Bit Rate Maximum Limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS control register. 7957 }; 7958 7959 //! \brief MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7960 //! \details 7961 //! Enable Min. Frame Rate Control. 7962 //! This is a mask bit controlling if the condition of frame level bit 7963 //! count is less than or equal to FrameBitRateMin. 7964 enum MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK 7965 { 7966 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED0 = 0, //!< Do not update bit[0] of MFX_VP8_IMAGE_STATUS Control Register. 7967 MIN_FRAME_BIT_COUNT_RATE_CONTROL_ENABLE_MASK_UNNAMED1 = 1, //!< If (Total Frame Level Bit Counter) =< (Frame Bit Rate Minimum limit)Set bit[0] and bit[1] of MFX_VP8_IMAGE_STATUS Control Register. 7968 }; 7969 7970 //! \brief FRAME_BIT_RATE_MAX_UNIT 7971 //! \details 7972 //! <i>This field is Frame Bitrate Maximum Mode</i> 7973 enum FRAME_BIT_RATE_MAX_UNIT 7974 { 7975 FRAME_BIT_RATE_MAX_UNIT_32_B = 0, //!< No additional details 7976 FRAME_BIT_RATE_MAX_UNIT_4_KB = 1, //!< No additional details 7977 }; 7978 7979 //! \brief FRAME_BITRATE_MAX_UNIT_MODE 7980 //! \details 7981 //! This field is the Frame Bitrate Maximum Limit Units. 7982 enum FRAME_BITRATE_MAX_UNIT_MODE 7983 { 7984 FRAME_BITRATE_MAX_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Max Unit is in old mode (128b/16Kb) 7985 FRAME_BITRATE_MAX_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Max Unit is in new mode (32byte/4Kb) 7986 }; 7987 7988 //! \brief FRAME_BIT_RATE_MIN_UNIT 7989 //! \details 7990 //! <i>This field is Frame Bitrate Minimum Mode.</i> 7991 enum FRAME_BIT_RATE_MIN_UNIT 7992 { 7993 FRAME_BIT_RATE_MIN_UNIT_32_B = 0, //!< No additional details 7994 FRAME_BIT_RATE_MIN_UNIT_4_KB = 1, //!< No additional details 7995 }; 7996 7997 //! \brief FRAME_BITRATE_MIN_UNIT_MODE 7998 //! \details 7999 //! This field is the Frame Bitrate Minimum Limit Units. 8000 enum FRAME_BITRATE_MIN_UNIT_MODE 8001 { 8002 FRAME_BITRATE_MIN_UNIT_MODE_COMPATIBILITYMODE = 0, //!< Frame BitRate Min Unit is in old mode (128b/16Kb) 8003 FRAME_BITRATE_MIN_UNIT_MODE_NEWMODE = 1, //!< Frame BitRate Min Unit is in new mode (32byte/4Kb) 8004 }; 8005 8006 enum MIN_FRAME_WSIZE_UNIT 8007 { 8008 MIN_FRAME_WSIZE_UNIT_COMPATIBILITYMODE = 0, //!< MinFrameWSizeUnit is in old mode (128b/16Kb) 8009 MIN_FRAME_WSIZE_UNIT_NEWMODE = 1, //!< MinFrameWSizeUnit is in new mode (32byte/4Kb) 8010 }; 8011 8012 //! \name Initializations 8013 8014 //! \brief Explicit member initialization function 8015 MFX_VP8_Encoder_CFG_CMD(); 8016 8017 static const size_t dwSize = 30; 8018 static const size_t byteSize = 120; 8019 }; 8020 8021 //! 8022 //! \brief MFX_VP8_BSP_BUF_BASE_ADDR_STATE 8023 //! \details 8024 //! 8025 //! 8026 struct MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD 8027 { 8028 union 8029 { 8030 //!< DWORD 0 8031 struct 8032 { 8033 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 8034 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 8035 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 8036 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 8037 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 8038 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 8039 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 8040 }; 8041 uint32_t Value; 8042 } DW0; 8043 union 8044 { 8045 //!< DWORD 1 8046 struct 8047 { 8048 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8049 uint32_t FrameHeaderBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Frame Header Base Addr 8050 }; 8051 uint32_t Value; 8052 } DW1; 8053 union 8054 { 8055 //!< DWORD 2 8056 struct 8057 { 8058 uint32_t FrameHeaderBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Frame Header Base Addr - Upper Range 8059 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8060 }; 8061 uint32_t Value; 8062 } DW2; 8063 union 8064 { 8065 //!< DWORD 3 8066 struct 8067 { 8068 uint32_t FrameHeaderBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8069 uint32_t Reserved98 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8070 uint32_t FrameHeaderBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8071 uint32_t ForFrameheaderbaseaddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8072 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8073 uint32_t Reserved105 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8074 }; 8075 uint32_t Value; 8076 } DW3; 8077 union 8078 { 8079 //!< DWORD 4 8080 struct 8081 { 8082 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8083 uint32_t IntermediateBufferBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Intermediate Buffer Base Addr 8084 }; 8085 uint32_t Value; 8086 } DW4; 8087 union 8088 { 8089 //!< DWORD 5 8090 struct 8091 { 8092 uint32_t IntermediateBufferBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Intermediate Buffer Base Addr - Upper Range 8093 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8094 }; 8095 uint32_t Value; 8096 } DW5; 8097 union 8098 { 8099 //!< DWORD 6 8100 struct 8101 { 8102 uint32_t IntermediateBufferBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8103 uint32_t Reserved194 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8104 uint32_t IntermediateBufferBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8105 uint32_t IntermediateBufferBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8106 uint32_t IntermediateBufferBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8107 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8108 }; 8109 uint32_t Value; 8110 } DW6; 8111 union 8112 { 8113 //!< DWORD 7 8114 struct 8115 { 8116 uint32_t IntermediateBufferPartition1Offset ; //!< Intermediate Buffer Partition-1 Offset 8117 }; 8118 uint32_t Value; 8119 } DW7; 8120 union 8121 { 8122 //!< DWORD 8 8123 struct 8124 { 8125 uint32_t IntermediateBufferPartition2Offset ; //!< Intermediate Buffer Partition-2 Offset 8126 }; 8127 uint32_t Value; 8128 } DW8; 8129 union 8130 { 8131 //!< DWORD 9 8132 struct 8133 { 8134 uint32_t IntermediateBufferPartition3Offset ; //!< Intermediate Buffer Partition-3 Offset 8135 }; 8136 uint32_t Value; 8137 } DW9; 8138 union 8139 { 8140 //!< DWORD 10 8141 struct 8142 { 8143 uint32_t IntermediateBufferPartition4Offset ; //!< Intermediate Buffer Partition-4 Offset 8144 }; 8145 uint32_t Value; 8146 } DW10; 8147 union 8148 { 8149 //!< DWORD 11 8150 struct 8151 { 8152 uint32_t IntermediateBufferPartition5Offset ; //!< Intermediate Buffer Partition-5 Offset 8153 }; 8154 uint32_t Value; 8155 } DW11; 8156 union 8157 { 8158 //!< DWORD 12 8159 struct 8160 { 8161 uint32_t IntermediateBufferPartition6Offset ; //!< Intermediate Buffer Partition-6 Offset 8162 }; 8163 uint32_t Value; 8164 } DW12; 8165 union 8166 { 8167 //!< DWORD 13 8168 struct 8169 { 8170 uint32_t IntermediateBufferPartition7Offset ; //!< Intermediate Buffer Partition-7 Offset 8171 }; 8172 uint32_t Value; 8173 } DW13; 8174 union 8175 { 8176 //!< DWORD 14 8177 struct 8178 { 8179 uint32_t IntermediateBufferPartition8Offset ; //!< Intermediate Buffer Partition-8 Offset 8180 }; 8181 uint32_t Value; 8182 } DW14; 8183 union 8184 { 8185 //!< DWORD 15 8186 struct 8187 { 8188 uint32_t IntermediateBufferMaxSize ; //!< Intermediate Buffer Max Size 8189 }; 8190 uint32_t Value; 8191 } DW15; 8192 union 8193 { 8194 //!< DWORD 16 8195 struct 8196 { 8197 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 8198 uint32_t FinalFrameBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Final Frame Base Addr 8199 }; 8200 uint32_t Value; 8201 } DW16; 8202 union 8203 { 8204 //!< DWORD 17 8205 struct 8206 { 8207 uint32_t FinalFrameBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Final Frame Base Addr - Upper Range 8208 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8209 }; 8210 uint32_t Value; 8211 } DW17; 8212 union 8213 { 8214 //!< DWORD 18 8215 struct 8216 { 8217 uint32_t FinalFrameBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8218 uint32_t Reserved578 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8219 uint32_t FinalFrameBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8220 uint32_t FinalFrameBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8221 uint32_t FinalFrameBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8222 uint32_t Reserved585 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8223 }; 8224 uint32_t Value; 8225 } DW18; 8226 union 8227 { 8228 //!< DWORD 19 8229 struct 8230 { 8231 uint32_t Finalframebyteoffset : __CODEGEN_BITFIELD( 0, 5) ; //!< FinalFrameByteOffset 8232 uint32_t Reserved614 : __CODEGEN_BITFIELD( 6, 31) ; //!< Reserved 8233 }; 8234 uint32_t Value; 8235 } DW19; 8236 union 8237 { 8238 //!< DWORD 20 8239 struct 8240 { 8241 uint32_t StreamoutBaseAddrCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8242 uint32_t StreamoutBaseAddrGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Streamout Base Addr - Graphics Data Type (GFDT) 8243 uint32_t Reserved643 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8244 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8245 uint32_t StreamoutBaseAddr : __CODEGEN_BITFIELD( 6, 31) ; //!< Streamout Base Addr 8246 }; 8247 uint32_t Value; 8248 } DW20; 8249 union 8250 { 8251 //!< DWORD 21 8252 struct 8253 { 8254 uint32_t StreamoutBaseAddrUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Streamout Base Addr - Upper Range 8255 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8256 }; 8257 uint32_t Value; 8258 } DW21; 8259 union 8260 { 8261 //!< DWORD 22 8262 struct 8263 { 8264 uint32_t StreamoutBaseAddrAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8265 uint32_t Reserved706 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8266 uint32_t StreamoutBaseAddrTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8267 uint32_t StreamoutBaseAddrLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8268 uint32_t StreamoutBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8269 uint32_t Reserved713 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8270 }; 8271 uint32_t Value; 8272 } DW22; 8273 union 8274 { 8275 //!< DWORD 23 8276 struct 8277 { 8278 uint32_t CoeffProbsStreaminSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8279 uint32_t CoeffProbsStreaminSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Coeff Probs StreamIn Surface - Graphics Data Type (GFDT) 8280 uint32_t Reserved739 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8281 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8282 uint32_t CoeffProbsStreaminSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Coeff Probs StreamIn Surface 8283 }; 8284 uint32_t Value; 8285 } DW23; 8286 union 8287 { 8288 //!< DWORD 24 8289 struct 8290 { 8291 uint32_t CoeffProbsStreaminSurfaceUpperRange : __CODEGEN_BITFIELD( 0, 15) ; //!< Coeff Probs StreamIn Surface - Upper Range 8292 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8293 }; 8294 uint32_t Value; 8295 } DW24; 8296 union 8297 { 8298 //!< DWORD 25 8299 struct 8300 { 8301 uint32_t CoeffProbsStreaminSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8302 uint32_t Reserved802 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 8303 uint32_t CoeffProbsStreaminSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8304 uint32_t CoeffProbsStreaminSurfaceLlcEllcCacheabilityControlLellccc : __CODEGEN_BITFIELD( 5, 6) ; //!< COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8305 uint32_t CoeffProbsStreaminSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL 8306 uint32_t Reserved809 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8307 }; 8308 uint32_t Value; 8309 } DW25; 8310 union 8311 { 8312 //!< DWORD 26 8313 struct 8314 { 8315 uint32_t TokenStatisticsSurfaceCacheabilityControl : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8316 uint32_t TokenStatisticsSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface - Graphics Data Type (GFDT) 8317 uint32_t Reserved835 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8318 uint32_t FrameHeaderBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD( 4, 5) ; //!< FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8319 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 6, 31) ; //!< Token Statistics Surface 8320 }; 8321 uint32_t Value; 8322 } DW26; 8323 union 8324 { 8325 //!< DWORD 27 8326 struct 8327 { 8328 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 0, 15) ; //!< Token Statistics Surface 8329 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 8330 }; 8331 uint32_t Value; 8332 } DW27; 8333 union 8334 { 8335 //!< DWORD 28 8336 struct 8337 { 8338 uint32_t TokenStatisticsSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8339 uint32_t TokenStatisticsSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< Token Statistics Surface 8340 uint32_t TokenStatisticsSurfaceTargetCacheTc : __CODEGEN_BITFIELD( 3, 4) ; //!< TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8341 uint32_t MemoryTypeLlcEllcCacheabilityControlLellcccForCoeffprobsStreaminSurface : __CODEGEN_BITFIELD( 5, 6) ; //!< MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8342 uint32_t TokenStatisticsSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8343 uint32_t Reserved905 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8344 }; 8345 uint32_t Value; 8346 } DW28; 8347 union 8348 { 8349 //!< DWORD 29..30 8350 struct 8351 { 8352 uint64_t MpcRowstoreSurfaceCacheabilityControl : __CODEGEN_BITFIELD(0, 1); //!< MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8353 uint64_t MpcRowstoreSurfaceGraphicsDataTypeGfdt : __CODEGEN_BITFIELD(2, 2); //!< MPC RowStore Surface Graphics Data Type (GFDT) 8354 uint64_t Reserved931 : __CODEGEN_BITFIELD(3, 3); //!< Reserved 8355 uint64_t MpcRowstoreBaseAddrArbitrationPriorityControl : __CODEGEN_BITFIELD(4, 5); //!< MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8356 uint64_t MpcRowstoreSurfaceAddressLow : __CODEGEN_BITFIELD(6, 63); //!< MPC RowStore Surface Address Low 8357 }; 8358 uint32_t Value[2]; 8359 } DW29_30; 8360 union 8361 { 8362 //!< DWORD 31 8363 struct 8364 { 8365 uint32_t MpcRowstoreSurfaceAgeForQuadlruAge : __CODEGEN_BITFIELD( 0, 1) ; //!< MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8366 uint32_t MpcRowstoreSurface : __CODEGEN_BITFIELD( 2, 2) ; //!< MPC RowStore Surface 8367 uint32_t MpcRowstoreTargetCache : __CODEGEN_BITFIELD( 3, 4) ; //!< MPC_ROWSTORE__TARGET_CACHE 8368 uint32_t MpcRowstoreMemoryTypeLlcEllcCacheabilityControl : __CODEGEN_BITFIELD( 5, 6) ; //!< MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8369 uint32_t MpcRowstoreArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8370 uint32_t Reserved1001 : __CODEGEN_BITFIELD( 9, 31) ; //!< Reserved 8371 }; 8372 uint32_t Value; 8373 } DW31; 8374 8375 //! \name Local enumerations 8376 8377 enum SUB_OPCODE_B 8378 { 8379 SUB_OPCODE_B_MFXVP8BSPBUFBASEADDRSTATE = 3, //!< No additional details 8380 }; 8381 8382 enum SUB_OPCODE_A 8383 { 8384 SUB_OPCODE_A_VP8COMMON = 2, //!< No additional details 8385 }; 8386 8387 enum MEDIA_COMMAND_OPCODE 8388 { 8389 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 8390 }; 8391 8392 enum PIPELINE 8393 { 8394 PIPELINE_VIDEOCODEC = 2, //!< No additional details 8395 }; 8396 8397 enum COMMAND_TYPE 8398 { 8399 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 8400 }; 8401 8402 //! \brief FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8403 //! \details 8404 //! This field allows the selection of AGE parameter for a given surface in 8405 //! LLC or eLLC. . 8406 //! If a particular allocation is done at youngest age ("3") it tends 8407 //! to stay longer in the cache as compared to older age allocations ("2", 8408 //! "1", or "0"). 8409 //! This option is given to driver to be able to decide which surfaces 8410 //! are more likely to generate HITs, hence need to be replaced least often 8411 //! in caches. 8412 enum FRAME_HEADER_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8413 { 8414 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8415 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8416 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8417 FRAME_HEADER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8418 }; 8419 8420 //! \brief FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8421 //! \details 8422 //! This field allows the choice of LLC vs eLLC for caching 8423 enum FRAME_HEADER_BASE_ADDR__TARGET_CACHE_TC 8424 { 8425 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8426 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8427 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8428 FRAME_HEADER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8429 }; 8430 8431 //! \brief FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8432 //! \details 8433 //! This is the field used in GT interface block to determine what type of 8434 //! access need to be generated to uncore. 8435 //! For the cases where the LeLLCCC is set, cacheable transaction are 8436 //! generated to enable LLC usage for particular stream. 8437 enum FOR_FRAMEHEADERBASEADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8438 { 8439 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8440 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8441 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8442 FOR_FRAMEHEADERBASEADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8443 }; 8444 8445 //! \brief FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8446 //! \details 8447 //! This field controls the priority of arbitration used in the GAC/GAM 8448 //! pipeline for this surface. 8449 enum FRAME_HEADER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8450 { 8451 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8452 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8453 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8454 FRAME_HEADER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8455 }; 8456 8457 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8458 //! \details 8459 //! This field allows the selection of AGE parameter for a given surface in 8460 //! LLC or eLLC. . 8461 //! If a particular allocation is done at youngest age ("3") it tends 8462 //! to stay longer in the cache as compared to older age allocations ("2", 8463 //! "1", or "0"). 8464 //! This option is given to driver to be able to decide which surfaces 8465 //! are more likely to generate HITs, hence need to be replaced least often 8466 //! in caches. 8467 enum INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE 8468 { 8469 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8470 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8471 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8472 INTERMEDIATE_BUFFER_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8473 }; 8474 8475 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8476 //! \details 8477 //! This field allows the choice of LLC vs. eLLC for caching 8478 enum INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC 8479 { 8480 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8481 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8482 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8483 INTERMEDIATE_BUFFER_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8484 }; 8485 8486 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8487 //! \details 8488 //! This is the field used in GT interface block to determine what type of 8489 //! access need to be generated to uncore. 8490 //! For the cases where the LeLLCCC is set, cacheable transaction are 8491 //! generated to enable LLC usage for particular stream. 8492 enum INTERMEDIATE_BUFFER_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8493 { 8494 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8495 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8496 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8497 INTERMEDIATE_BUFFER_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8498 }; 8499 8500 //! \brief INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8501 //! \details 8502 //! This field controls the priority of arbitration used in the GAC/GAM 8503 //! pipeline for this surface. 8504 enum INTERMEDIATE_BUFFER_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8505 { 8506 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8507 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8508 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8509 INTERMEDIATE_BUFFER_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8510 }; 8511 8512 //! \brief FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8513 //! \details 8514 //! This field allows the selection of AGE parameter for a given surface in 8515 //! LLC or eLLC. . 8516 //! If a particular allocation is done at youngest age ("3") it tends 8517 //! to stay longer in the cache as compared to older age allocations ("2", 8518 //! "1", or "0"). 8519 //! This option is given to driver to be able to decide which surfaces 8520 //! are more likely to generate HITs, hence need to be replaced least often 8521 //! in caches. 8522 enum FINAL_FRAME_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8523 { 8524 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8525 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8526 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8527 FINAL_FRAME_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8528 }; 8529 8530 //! \brief FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8531 //! \details 8532 //! This field allows the choice of LLC vs eLLC for caching 8533 enum FINAL_FRAME_BASE_ADDR__TARGET_CACHE_TC 8534 { 8535 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8536 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8537 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8538 FINAL_FRAME_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8539 }; 8540 8541 //! \brief FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8542 //! \details 8543 //! This is the field used in GT interface block to determine what type of 8544 //! access need to be generated to uncore. 8545 //! For the cases where the LeLLCCC is set, cacheable transaction are 8546 //! generated to enable LLC usage for particular stream. 8547 enum FINAL_FRAME_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8548 { 8549 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8550 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8551 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8552 FINAL_FRAME_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8553 }; 8554 8555 enum FINAL_FRAME_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8556 { 8557 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8558 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8559 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8560 FINAL_FRAME_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8561 }; 8562 8563 //! \brief STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8564 //! \details 8565 //! This field controls cacheability in the mid-level cache (MLC) and 8566 //! last-level cache (LLC) 8567 enum STREAMOUT_BASE_ADDR__CACHEABILITY_CONTROL 8568 { 8569 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8570 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8571 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8572 STREAMOUT_BASE_ADDR_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8573 }; 8574 8575 //! \brief STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8576 //! \details 8577 //! This field controls the priority of arbitration used in the GAC/GAM 8578 //! pipeline for this surface. 8579 enum STREAMOUT_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL_ 8580 { 8581 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8582 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8583 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8584 STREAMOUT_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8585 }; 8586 8587 //! \brief STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8588 //! \details 8589 //! This field allows the selection of AGE parameter for a given surface in 8590 //! LLC or eLLC. . 8591 //! If a particular allocation is done at youngest age ("3") it tends 8592 //! to stay longer in the cache as compared to older age allocations ("2", 8593 //! "1", or "0"). 8594 //! This option is given to driver to be able to decide which surfaces 8595 //! are more likely to generate HITs, hence need to be replaced least often 8596 //! in caches. 8597 enum STREAMOUT_BASE_ADDR__AGE_FOR_QUADLRU_AGE 8598 { 8599 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8600 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8601 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8602 STREAMOUT_BASE_ADDR_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8603 }; 8604 8605 //! \brief STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8606 //! \details 8607 //! This field allows the choice of LLC vs eLLC for caching 8608 enum STREAMOUT_BASE_ADDR__TARGET_CACHE_TC 8609 { 8610 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8611 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8612 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8613 STREAMOUT_BASE_ADDR_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8614 }; 8615 8616 //! \brief STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8617 //! \details 8618 //! This is the field used in GT interface block to determine what type of 8619 //! access need to be generated to uncore. 8620 //! For the cases where the LeLLCCC is set, cacheable transaction are 8621 //! generated to enable LLC usage for particular stream. 8622 enum STREAMOUT_BASE_ADDR__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8623 { 8624 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8625 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8626 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8627 STREAMOUT_BASE_ADDR_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8628 }; 8629 8630 //! \brief COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8631 //! \details 8632 //! This field controls cacheability in the mid-level cache (MLC) and 8633 //! last-level cache (LLC) 8634 enum COEFF_PROBS_STREAMIN_SURFACE__CACHEABILITY_CONTROL 8635 { 8636 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8637 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8638 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8639 COEFF_PROBS_STREAMIN_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8640 }; 8641 8642 //! \brief COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8643 //! \details 8644 //! This field controls the priority of arbitration used in the GAC/GAM 8645 //! pipeline for this surface. 8646 enum COEFF_PROBS_STREAMIN_SURFACE__ARBITRATION_PRIORITY_CONTROL_ 8647 { 8648 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8649 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8650 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8651 COEFF_PROBS_STREAMIN_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8652 }; 8653 8654 //! \brief COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8655 //! \details 8656 //! This field allows the selection of AGE parameter for a given surface in 8657 //! LLC or eLLC. . 8658 //! If a particular allocation is done at youngest age ("3") it tends 8659 //! to stay longer in the cache as compared to older age allocations ("2", 8660 //! "1", or "0"). 8661 //! This option is given to driver to be able to decide which surfaces 8662 //! are more likely to generate HITs, hence need to be replaced least often 8663 //! in caches. 8664 enum COEFF_PROBS_STREAMIN_SURFACE__AGE_FOR_QUADLRU_AGE 8665 { 8666 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 0, //!< No additional details 8667 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 1, //!< No additional details 8668 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 2, //!< No additional details 8669 COEFF_PROBS_STREAMIN_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 3, //!< No additional details 8670 }; 8671 8672 //! \brief COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8673 //! \details 8674 //! This field allows the choice of LLC vs eLLC for caching 8675 enum COEFF_PROBS_STREAMIN_SURFACE__TARGET_CACHE_TC 8676 { 8677 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGT = 0, //!< No additional details 8678 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8679 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8680 COEFF_PROBS_STREAMIN_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8681 }; 8682 8683 //! \brief COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8684 //! \details 8685 //! This is the field used in GT interface block to determine what type of 8686 //! access need to be generated to uncore. 8687 //! For the cases where the LeLLCCC is set, cacheable transaction are 8688 //! generated to enable LLC usage for particular stream. 8689 enum COEFF_PROBS_STREAMIN_SURFACE__LLCELLC_CACHEABILITY_CONTROL_LELLCCC 8690 { 8691 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_CACHEABLE = 0, //!< Use Cacheability Controls from page table / UC with Fence (if coherent cycle) 8692 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_UC = 1, //!< Uncacheable - non-cacheable 8693 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WT = 2, //!< Writethrough 8694 COEFF_PROBS_STREAMIN_SURFACE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_WB = 3, //!< Writeback 8695 }; 8696 8697 //! \brief TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8698 //! \details 8699 //! This field controls cacheability in the mid-level cache (MLC) and 8700 //! last-level cache (LLC). 8701 enum TOKEN_STATISTICS_SURFACE__CACHEABILITY_CONTROL 8702 { 8703 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8704 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8705 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8706 TOKEN_STATISTICS_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8707 }; 8708 8709 //! \brief TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8710 //! \details 8711 //! This field allows the selection of AGE parameter for a given surface in 8712 //! LLC or eLLC. . If a particular allocation is done at youngest age ("3") 8713 //! it tends to stay longer in the cache as compared to older age 8714 //! allocations ("2", "1", or "0"). 8715 //! This option is given to driver to be able to decide which surfaces 8716 //! are more likely to generate HITs, hence need to be replaced least often 8717 //! in caches. 8718 enum TOKEN_STATISTICS_SURFACE__AGE_FOR_QUADLRU_AGE 8719 { 8720 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8721 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8722 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8723 TOKEN_STATISTICS_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8724 }; 8725 8726 //! \brief TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8727 //! \details 8728 //! This field allows the choice of LLC vs eLLC for caching. 8729 enum TOKEN_STATISTICS_SURFACE__TARGET_CACHE_TC 8730 { 8731 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_ELLCONLY_NOTSNOOPEDINGTBDW = 0, //!< No additional details 8732 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCONLY = 1, //!< No additional details 8733 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_LLCELLCALLOWED = 2, //!< No additional details 8734 TOKEN_STATISTICS_SURFACE_TARGET_CACHE_TC_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8735 }; 8736 8737 //! \brief MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8738 //! \details 8739 //! This is the field used in GT interface block to determine what type of 8740 //! access need to be generated to uncore. 8741 //! For the cases where the LeLLCCC is set, cacheable transaction are 8742 //! generated to enable LLC usage for particular stream. 8743 enum MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE 8744 { 8745 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8746 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_UC = 1, //!< Uncacheable - non-cacheable 8747 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WT = 2, //!< Writethrough 8748 MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_LELLCCC_FOR_COEFFPROBS_STREAMIN_SURFACE_WB = 3, //!< Writeback 8749 }; 8750 8751 //! \brief TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8752 //! \details 8753 //! This field controls the priority of arbitration used in the GAC/GAM 8754 //! pipeline for this surface. 8755 enum TOKEN_STATISTICS_SURFACE__ARBITRATION_PRIORITY_CONTROL 8756 { 8757 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8758 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8759 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8760 TOKEN_STATISTICS_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8761 }; 8762 8763 //! \brief MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8764 //! \details 8765 //! <b>This field controls cacheability in the mid-level cache (MLC) and 8766 //! last-level cache (LLC).</b> 8767 enum MPC_ROWSTORE_SURFACE__CACHEABILITY_CONTROL 8768 { 8769 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_GTTENTRY = 0, //!< Use cacheability control bits from GTT entry 8770 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_NOTLLCORMLC = 1, //!< Data is not cached in LLC or MLC 8771 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_LLCBUTNOTMLC = 2, //!< Data is cached in LLC but not MLC 8772 MPC_ROWSTORE_SURFACE_CACHEABILITY_CONTROL_BOTHLLCANDMLC = 3, //!< Data is cached in both LLC and MLC 8773 }; 8774 8775 //! \brief MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8776 //! \details 8777 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8778 //! pipeline for this surface.</b> 8779 enum MPC_ROWSTORE_BASE_ADDR__ARBITRATION_PRIORITY_CONTROL 8780 { 8781 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8782 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8783 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8784 MPC_ROWSTORE_BASE_ADDR_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8785 }; 8786 8787 //! \brief MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8788 //! \details 8789 //! <b>This field allows the selection of AGE parameter for a given surface 8790 //! in LLC or eLLC. . If a particular allocation is done at youngest age 8791 //! ("3") it tends to stay longer in the cache as compared to older age 8792 //! allocations ("2", "1", or "0"). 8793 //! This option is given to driver to be able to decide which surfaces 8794 //! are more likely to generate HITs, hence need to be replaced least often 8795 //! in caches.</b> 8796 enum MPC_ROWSTORE_SURFACE__AGE_FOR_QUADLRU_AGE 8797 { 8798 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_POORCHANCEOFGENERATINGHITS = 0, //!< No additional details 8799 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_DECENTCHANCEOFGENERATINGHITS = 1, //!< No additional details 8800 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_NEXTGOODCHANCEOFGENERATINGHITS = 2, //!< No additional details 8801 MPC_ROWSTORE_SURFACE_AGE_FOR_QUADLRU_AGE_GOODCHANCEOFGENERATINGHITS = 3, //!< No additional details 8802 }; 8803 8804 //! \brief MPC_ROWSTORE__TARGET_CACHE 8805 //! \details 8806 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8807 //! pipeline for this surface.</b> 8808 enum MPC_ROWSTORE__TARGET_CACHE 8809 { 8810 MPC_ROWSTORE_TARGET_CACHE_ELLCONLY = 0, //!< No additional details 8811 MPC_ROWSTORE_TARGET_CACHE_LLCONLY = 1, //!< No additional details 8812 MPC_ROWSTORE_TARGET_CACHE_LLCELLCALLOWED = 2, //!< No additional details 8813 MPC_ROWSTORE_TARGET_CACHE_L3_LLC_ELLCALLOWED = 3, //!< No additional details 8814 }; 8815 8816 //! \brief MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8817 //! \details 8818 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8819 //! pipeline for this surface.</b> 8820 enum MPC_ROWSTORE__MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL 8821 { 8822 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_USECACHEABILITYCONTROLSFROMPAGETABLEUCWITHFENCEIFCOHERENTCYCLE = 0, //!< No additional details 8823 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_UC = 1, //!< Uncacheable - non-cacheable 8824 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WT = 2, //!< Writethrough 8825 MPC_ROWSTORE_MEMORY_TYPE_LLCELLC_CACHEABILITY_CONTROL_WB = 3, //!< Writeback 8826 }; 8827 8828 //! \brief MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8829 //! \details 8830 //! <b>This field controls the priority of arbitration used in the GAC/GAM 8831 //! pipeline for this surface.</b> 8832 enum MPC_ROWSTORE__ARBITRATION_PRIORITY_CONTROL 8833 { 8834 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 8835 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 8836 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 8837 MPC_ROWSTORE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 8838 }; 8839 8840 //! \name Initializations 8841 8842 //! \brief Explicit member initialization function 8843 MFX_VP8_BSP_BUF_BASE_ADDR_STATE_CMD(); 8844 8845 static const size_t dwSize = 32; 8846 static const size_t byteSize = 128; 8847 }; 8848 8849 //! 8850 //! \brief MFD_VP8_BSD_OBJECT 8851 //! \details 8852 //! The MFD_VP8_BSD_OBJECT command is the only primitive command for the VP8 8853 //! Decoding Pipeline. The Partitions of the bitstream is loaded as indirect 8854 //! data object. Before issuing a MFD_VP8_BSD_OBJECT command, all VP8 frame 8855 //! level states of the MFD Engine need to be valid. Therefore the commands 8856 //! used to set these states need to have been issued prior to the issue of 8857 //! a MFD_VP8_BSD_OBJECT command. Context switch interrupt is not supported 8858 //! by this command. 8859 //! 8860 struct MFD_VP8_BSD_OBJECT_CMD 8861 { 8862 union 8863 { 8864 //!< DWORD 0 8865 struct 8866 { 8867 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 8868 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 8869 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 8870 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 8871 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 8872 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 8873 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 8874 }; 8875 uint32_t Value; 8876 } DW0; 8877 union 8878 { 8879 //!< DWORD 1 8880 struct 8881 { 8882 uint32_t Partition0FirstmbbitoffsetFromFrameHeader : __CODEGEN_BITFIELD( 0, 2) ; //!< Partition0 FirstMBBitOffset from Frame Header 8883 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 8884 uint32_t CodedNumOfCoeffTokenPartitions : __CODEGEN_BITFIELD( 4, 5) ; //!< Coded Num of Coeff Token Partitions 8885 uint32_t Reserved38 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 8886 uint32_t Partition0CpbacEntropyRange : __CODEGEN_BITFIELD( 8, 15) ; //!< Partition0 CPBAC Entropy Range 8887 uint32_t Partition0CpbacEntropyCount : __CODEGEN_BITFIELD(16, 20) ; //!< Partition0 CPBAC Entropy Count 8888 uint32_t Reserved53 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 8889 }; 8890 uint32_t Value; 8891 } DW1; 8892 union 8893 { 8894 //!< DWORD 2 8895 struct 8896 { 8897 uint32_t Reserved64 : __CODEGEN_BITFIELD( 0, 23) ; //!< Reserved 8898 uint32_t Partition0CpbacEntropyValue : __CODEGEN_BITFIELD(24, 31) ; //!< Partition0 CPBAC Entropy Value 8899 }; 8900 uint32_t Value; 8901 } DW2; 8902 union 8903 { 8904 //!< DWORD 3 8905 struct 8906 { 8907 uint32_t IndirectPartition0DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition0 Data Length 8908 uint32_t Reserved120 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8909 }; 8910 uint32_t Value; 8911 } DW3; 8912 union 8913 { 8914 //!< DWORD 4 8915 struct 8916 { 8917 uint32_t IndirectPartition0DataStartOffset ; //!< Indirect Partition0 Data Start Offset 8918 }; 8919 uint32_t Value; 8920 } DW4; 8921 union 8922 { 8923 //!< DWORD 5 8924 struct 8925 { 8926 uint32_t IndirectPartition1DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition1 Data Length 8927 uint32_t Reserved184 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8928 }; 8929 uint32_t Value; 8930 } DW5; 8931 union 8932 { 8933 //!< DWORD 6 8934 struct 8935 { 8936 uint32_t IndirectPartition1DataStartOffset ; //!< Indirect Partition1 Data Start Offset 8937 }; 8938 uint32_t Value; 8939 } DW6; 8940 union 8941 { 8942 //!< DWORD 7 8943 struct 8944 { 8945 uint32_t IndirectPartition2DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition2 Data Length 8946 uint32_t Reserved248 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8947 }; 8948 uint32_t Value; 8949 } DW7; 8950 union 8951 { 8952 //!< DWORD 8 8953 struct 8954 { 8955 uint32_t IndirectPartition2DataStartOffset ; //!< Indirect Partition2 Data Start Offset 8956 }; 8957 uint32_t Value; 8958 } DW8; 8959 union 8960 { 8961 //!< DWORD 9 8962 struct 8963 { 8964 uint32_t IndirectPartition3DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition3 Data Length 8965 uint32_t Reserved312 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8966 }; 8967 uint32_t Value; 8968 } DW9; 8969 union 8970 { 8971 //!< DWORD 10 8972 struct 8973 { 8974 uint32_t IndirectPartition3DataStartOffset ; //!< Indirect Partition3 Data Start Offset 8975 }; 8976 uint32_t Value; 8977 } DW10; 8978 union 8979 { 8980 //!< DWORD 11 8981 struct 8982 { 8983 uint32_t IndirectPartition4DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition4 Data Length 8984 uint32_t Reserved376 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 8985 }; 8986 uint32_t Value; 8987 } DW11; 8988 union 8989 { 8990 //!< DWORD 12 8991 struct 8992 { 8993 uint32_t IndirectPartition4DataStartOffset ; //!< Indirect Partition4 Data Start Offset 8994 }; 8995 uint32_t Value; 8996 } DW12; 8997 union 8998 { 8999 //!< DWORD 13 9000 struct 9001 { 9002 uint32_t IndirectPartition5DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition5 Data Length 9003 uint32_t Reserved440 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9004 }; 9005 uint32_t Value; 9006 } DW13; 9007 union 9008 { 9009 //!< DWORD 14 9010 struct 9011 { 9012 uint32_t IndirectPartition5DataStartOffset ; //!< Indirect Partition5 Data Start Offset 9013 }; 9014 uint32_t Value; 9015 } DW14; 9016 union 9017 { 9018 //!< DWORD 15 9019 struct 9020 { 9021 uint32_t IndirectPartition6DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition6 Data Length 9022 uint32_t Reserved504 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9023 }; 9024 uint32_t Value; 9025 } DW15; 9026 union 9027 { 9028 //!< DWORD 16 9029 struct 9030 { 9031 uint32_t IndirectPartition6DataStartOffset ; //!< Indirect Partition6 Data Start Offset 9032 }; 9033 uint32_t Value; 9034 } DW16; 9035 union 9036 { 9037 //!< DWORD 17 9038 struct 9039 { 9040 uint32_t IndirectPartition7DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition7 Data Length 9041 uint32_t Reserved568 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9042 }; 9043 uint32_t Value; 9044 } DW17; 9045 union 9046 { 9047 //!< DWORD 18 9048 struct 9049 { 9050 uint32_t IndirectPartition7DataStartOffset ; //!< Indirect Partition7 Data Start Offset 9051 }; 9052 uint32_t Value; 9053 } DW18; 9054 union 9055 { 9056 //!< DWORD 19 9057 struct 9058 { 9059 uint32_t IndirectPartition8DataLength : __CODEGEN_BITFIELD( 0, 23) ; //!< Indirect Partition8 Data Length 9060 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9061 }; 9062 uint32_t Value; 9063 } DW19; 9064 union 9065 { 9066 //!< DWORD 20 9067 struct 9068 { 9069 uint32_t IndirectPartition8DataStartOffset ; //!< Indirect Partition8 Data Start Offset 9070 }; 9071 uint32_t Value; 9072 } DW20; 9073 union 9074 { 9075 //!< DWORD 21 9076 struct 9077 { 9078 uint32_t Reserved672 : __CODEGEN_BITFIELD( 0, 7) ; //!< Reserved 9079 uint32_t MbHeaderErrorHandling : __CODEGEN_BITFIELD( 8, 8) ; //!< MB_HEADER_ERROR_HANDLING 9080 uint32_t Reserved681 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 9081 uint32_t EntropyErrorHandling : __CODEGEN_BITFIELD(10, 10) ; //!< ENTROPY_ERROR_HANDLING 9082 uint32_t Reserved683 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 9083 uint32_t MprErrorMvOutOfRangeHandling : __CODEGEN_BITFIELD(12, 12) ; //!< MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 9084 uint32_t Reserved685 : __CODEGEN_BITFIELD(13, 13) ; //!< Reserved 9085 uint32_t BsdprematurecompleteErrorHandling : __CODEGEN_BITFIELD(14, 14) ; //!< BSDPREMATURECOMPLETE_ERROR_HANDLING 9086 uint32_t Reserved687 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9087 uint32_t ConcealPicIdConcealmentPictureId : __CODEGEN_BITFIELD(16, 17) ; //!< Conceal_Pic_Id (Concealment Picture ID) 9088 uint32_t Reserved690 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 9089 uint32_t ConcealmentMethod : __CODEGEN_BITFIELD(31, 31) ; //!< CONCEALMENT_METHOD 9090 }; 9091 uint32_t Value; 9092 } DW21; 9093 9094 //! \name Local enumerations 9095 9096 enum SUBOPCODEB 9097 { 9098 SUBOPCODEB_UNNAMED8 = 8, //!< No additional details 9099 }; 9100 9101 enum SUBOPCODEA 9102 { 9103 SUBOPCODEA_UNNAMED1 = 1, //!< No additional details 9104 }; 9105 9106 enum MEDIA_COMMAND_OPCODE 9107 { 9108 MEDIA_COMMAND_OPCODE_VP8DEC = 4, //!< No additional details 9109 }; 9110 9111 enum PIPELINE 9112 { 9113 PIPELINE_MFDVP8BSDOBJECT = 2, //!< No additional details 9114 }; 9115 9116 enum COMMAND_TYPE 9117 { 9118 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9119 }; 9120 9121 enum MB_HEADER_ERROR_HANDLING 9122 { 9123 MB_HEADER_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9124 MB_HEADER_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9125 }; 9126 9127 enum ENTROPY_ERROR_HANDLING 9128 { 9129 ENTROPY_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9130 ENTROPY_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9131 }; 9132 9133 enum MPR_ERROR_MV_OUT_OF_RANGE_HANDLING 9134 { 9135 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9136 MPR_ERROR_MV_OUT_OF_RANGE_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9137 }; 9138 9139 //! \brief BSDPREMATURECOMPLETE_ERROR_HANDLING 9140 //! \details 9141 //! It occurs in situation where the decode is completed but there are still 9142 //! data in the bitstream. 9143 enum BSDPREMATURECOMPLETE_ERROR_HANDLING 9144 { 9145 BSDPREMATURECOMPLETE_ERROR_HANDLING_IGNORETHEERRORANDCONTINUEMASKEDTHEINTERRUPT_ASSUMETHEHARDWAREAUTOMATICALLYPERFORMTHEERRORHANDLING = 0, //!< No additional details 9146 BSDPREMATURECOMPLETE_ERROR_HANDLING_SETTHEINTERRUPTTOTHEDRIVERPROVIDEMMIOREGISTERSFORMBADDRESSRW = 1, //!< No additional details 9147 }; 9148 9149 //! \brief CONCEALMENT_METHOD 9150 //! \details 9151 //! This field specifies the method used for concealment when error is 9152 //! detected. 9153 enum CONCEALMENT_METHOD 9154 { 9155 CONCEALMENT_METHOD_INTRA16X16PREDICTION = 0, //!< A copy from the current picture is performed using Intra 16x16 Prediction method. 9156 CONCEALMENT_METHOD_INTERPCOPY = 1, //!< A copy from collocated macroblock location is performed from the concealment reference indicated by the ConCeal_Pic_Id field. 9157 }; 9158 9159 //! \name Initializations 9160 9161 //! \brief Explicit member initialization function 9162 MFD_VP8_BSD_OBJECT_CMD(); 9163 9164 static const size_t dwSize = 22; 9165 static const size_t byteSize = 88; 9166 }; 9167 9168 //! 9169 //! \brief MFX_VP8_PIC_STATE 9170 //! \details 9171 //! This must be the very first command to issue after the surface state, 9172 //! the pipe select and base address setting commands and must be issued 9173 //! before MFX_VP8_IMG_STATE. 9174 //! 9175 struct MFX_VP8_PIC_STATE_CMD 9176 { 9177 union 9178 { 9179 //!< DWORD 0 9180 struct 9181 { 9182 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9183 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9184 uint32_t SubOpcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUB_OPCODE_B 9185 uint32_t SubOpcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUB_OPCODE_A 9186 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9187 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9188 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9189 }; 9190 uint32_t Value; 9191 } DW0; 9192 union 9193 { 9194 //!< DWORD 1 9195 struct 9196 { 9197 uint32_t FrameWidthMinus1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Frame Width Minus 1 9198 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 9199 uint32_t FrameHeightMinus1 : __CODEGEN_BITFIELD(16, 23) ; //!< Frame Height Minus 1 9200 uint32_t Reserved56 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9201 }; 9202 uint32_t Value; 9203 } DW1; 9204 union 9205 { 9206 //!< DWORD 2 9207 struct 9208 { 9209 uint32_t McFilterSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< MC_FILTER_SELECT, Decoder / Encoder 9210 uint32_t ChromaFullPixelMcFilterMode : __CODEGEN_BITFIELD( 1, 1) ; //!< CHROMA_FULL_PIXEL_MC_FILTER_MODE, Decoder / Encoder 9211 uint32_t Reserved66 : __CODEGEN_BITFIELD( 2, 3) ; //!< Reserved, Decoder / Encoder 9212 uint32_t Dblkfiltertype : __CODEGEN_BITFIELD( 4, 4) ; //!< DBLKFILTERTYPE, Decoder / Encoder 9213 uint32_t Skeyframeflag : __CODEGEN_BITFIELD( 5, 5) ; //!< SKEYFRAMEFLAG, Decoder / Encoder 9214 uint32_t SegmentationIdStreamoutEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< SEGMENTATION_ID_STREAMOUT_ENABLE, Decoder Only 9215 uint32_t SegmentationIdStreaminEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< SEGMENTATION_ID_STREAMIN_ENABLE, Decoder Only 9216 uint32_t SegmentEnableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< SEGMENT_ENABLE_FLAG, Decoder / Encoder 9217 uint32_t UpdateMbsegmentMapFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< UPDATE_MBSEGMENT_MAP_FLAG, Decoder / Encoder 9218 uint32_t MbNocoeffSkipflag : __CODEGEN_BITFIELD(10, 10) ; //!< MB_NOCOEFF_SKIPFLAG, Decoder / Encoder 9219 uint32_t ModeReferenceLoopFilterDeltaEnabled : __CODEGEN_BITFIELD(11, 11) ; //!< MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED, Decoder / Encoder 9220 uint32_t GoldenRefPictureMvSignbiasFlag : __CODEGEN_BITFIELD(12, 12) ; //!< Golden Ref Picture MV SignBias Flag, Decoder / Encoder 9221 uint32_t AlternateRefPicMvSignbiasFlag : __CODEGEN_BITFIELD(13, 13) ; //!< Alternate Ref Pic MV SignBias Flag, Decoder / Encoder 9222 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved, Decoder / Encoder 9223 uint32_t DeblockSharpnessLevel : __CODEGEN_BITFIELD(16, 18) ; //!< Deblock Sharpness Level, Decoder / Encoder 9224 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 23) ; //!< Reserved, Decoder / Encoder 9225 uint32_t Log2NumOfPartition : __CODEGEN_BITFIELD(24, 25) ; //!< LOG2_NUM_OF_PARTITION, Decoder / Encoder 9226 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 9227 }; 9228 uint32_t Value; 9229 } DW2; 9230 union 9231 { 9232 //!< DWORD 3 9233 struct 9234 { 9235 uint32_t DblkfilterlevelForSegment0 : __CODEGEN_BITFIELD( 0, 5) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT0 9236 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 9237 uint32_t DblkfilterlevelForSegment1 : __CODEGEN_BITFIELD( 8, 13) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT1 9238 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 9239 uint32_t DblkfilterlevelForSegment2 : __CODEGEN_BITFIELD(16, 21) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT2 9240 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 9241 uint32_t DblkfilterlevelForSegment3 : __CODEGEN_BITFIELD(24, 29) ; //!< DBLKFILTERLEVEL_FOR_SEGMENT3 9242 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 9243 }; 9244 uint32_t Value; 9245 } DW3; 9246 union 9247 { 9248 //!< DWORD 4 9249 struct 9250 { 9251 uint32_t QuantizerValue0Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType0=Y1DC], Decoder Only 9252 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9253 uint32_t QuantizerValue0Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType1=Y1AC], Decoder Only 9254 uint32_t Reserved153 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9255 } dec; 9256 struct 9257 { 9258 uint32_t Seg0Qindex : __CODEGEN_BITFIELD( 0, 6) ; //!< Seg 0 Qindex, Encoder Only 9259 uint32_t Reserved135 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9260 uint32_t Seg1Qindex : __CODEGEN_BITFIELD( 8, 14) ; //!< Seg 1 Qindex, Encoder Only 9261 uint32_t Reserved143 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved, Encoder Only 9262 uint32_t Seg2Qindex : __CODEGEN_BITFIELD(16, 22) ; //!< Seg 2 Qindex, Encoder Only 9263 uint32_t Reserved151 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved, Encoder Only 9264 uint32_t Seg3Qindex : __CODEGEN_BITFIELD(24, 30) ; //!< Seg 3 Qindex, Encoder Only 9265 uint32_t Reserved159 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9266 } enc; 9267 uint32_t Value; 9268 } DW4; 9269 union 9270 { 9271 //!< DWORD 5 9272 struct 9273 { 9274 uint32_t QuantizerValue0Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType2=UVDC], Decoder Only 9275 uint32_t Reserved169 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9276 uint32_t QuantizerValue0Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType3=UVAC], Decoder Only 9277 uint32_t Reserved185 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9278 } dec; 9279 struct 9280 { 9281 uint32_t Y2DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y2dc Qindex Delta, Encoder Only 9282 uint32_t Y2AcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y2ac Qindex Delta Sign , Encoder Only 9283 uint32_t Reserved165 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved, Encoder Only 9284 uint32_t Y2AcQindexDelta : __CODEGEN_BITFIELD( 8, 11) ; //!< Y2ac Qindex Delta , Encoder Only 9285 uint32_t Y2AcQindexSign : __CODEGEN_BITFIELD(12, 12) ; //!< Y2ac Qindex Sign, Encoder Only 9286 uint32_t Reserved173 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved, Encoder Only 9287 uint32_t UvdcQindexDelta : __CODEGEN_BITFIELD(16, 19) ; //!< UVdc Qindex Delta, Encoder Only 9288 uint32_t UvdcQindexDeltaSign : __CODEGEN_BITFIELD(20, 20) ; //!< UVdc Qindex Delta Sign, Encoder Only 9289 uint32_t Reserved181 : __CODEGEN_BITFIELD(21, 23) ; //!< Reserved, Encoder Only 9290 uint32_t UvacQindexdelta : __CODEGEN_BITFIELD(24, 27) ; //!< UVac QindexDelta, Encoder Only 9291 uint32_t UvacQindexDeltaSign : __CODEGEN_BITFIELD(28, 28) ; //!< UVac Qindex Delta Sign, Encoder Only 9292 uint32_t Reserved189 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 9293 } enc; 9294 uint32_t Value; 9295 } DW5; 9296 union 9297 { 9298 //!< DWORD 6 9299 struct 9300 { 9301 uint32_t QuantizerValue0Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [0][BlockType4=Y2DC], Decoder Only 9302 uint32_t Reserved201 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9303 uint32_t QuantizerValue0Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [0][BlockType5=Y2AC], Decoder Only 9304 uint32_t Reserved217 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9305 } dec; 9306 struct 9307 { 9308 uint32_t Y1DcQindexDelta : __CODEGEN_BITFIELD( 0, 3) ; //!< Y1dc Qindex Delta, Encoder Only 9309 uint32_t Y1DcQindexDeltaSign : __CODEGEN_BITFIELD( 4, 4) ; //!< Y1dc Qindex Delta Sign , Encoder Only 9310 uint32_t Reserved197 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 9311 } enc; 9312 uint32_t Value; 9313 } DW6; 9314 union 9315 { 9316 //!< DWORD 7 9317 struct 9318 { 9319 uint32_t QuantizerValue1Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType0=Y1DC], Decoder Only 9320 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9321 uint32_t QuantizerValue1Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType1=Y1AC], Decoder Only 9322 uint32_t Reserved249 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9323 } dec; 9324 struct 9325 { 9326 uint32_t ClampQindexLow : __CODEGEN_BITFIELD( 0, 6) ; //!< Clamp Qindex Low, Encoder Only 9327 uint32_t Reserved231 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved, Encoder Only 9328 uint32_t ClampQindexHigh : __CODEGEN_BITFIELD( 8, 14) ; //!< Clamp Qindex high, Encoder Only 9329 uint32_t Reserved239 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9330 } enc; 9331 uint32_t Value; 9332 } DW7; 9333 union 9334 { 9335 //!< DWORD 8 9336 struct 9337 { 9338 uint32_t QuantizerValue1Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType2=UVDC], Decoder Only 9339 uint32_t Reserved265 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9340 uint32_t QuantizerValue1Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType3=UVAC], Decoder Only 9341 uint32_t Reserved281 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9342 }; 9343 uint32_t Value; 9344 } DW8; 9345 union 9346 { 9347 //!< DWORD 9 9348 struct 9349 { 9350 uint32_t QuantizerValue1Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [1][BlockType4=Y2DC], Decoder Only 9351 uint32_t Reserved297 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9352 uint32_t QuantizerValue1Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [1][BlockType5=Y2AC], Decoder Only 9353 uint32_t Reserved313 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9354 }; 9355 uint32_t Value; 9356 } DW9; 9357 union 9358 { 9359 //!< DWORD 10 9360 struct 9361 { 9362 uint32_t QuantizerValue2Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType0=Y1DC], Decoder Only 9363 uint32_t Reserved329 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9364 uint32_t QuantizerValue2Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType1=Y1AC], Decoder Only 9365 uint32_t Reserved345 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9366 }; 9367 uint32_t Value; 9368 } DW10; 9369 union 9370 { 9371 //!< DWORD 11 9372 struct 9373 { 9374 uint32_t QuantizerValue2Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType2=UVDC], Decoder Only 9375 uint32_t Reserved361 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9376 uint32_t QuantizerValue2Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType3=UVAC], Decoder Only 9377 uint32_t Reserved377 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9378 }; 9379 uint32_t Value; 9380 } DW11; 9381 union 9382 { 9383 //!< DWORD 12 9384 struct 9385 { 9386 uint32_t QuantizerValue2Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [2][BlockType4=Y2DC], Decoder Only 9387 uint32_t Reserved393 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9388 uint32_t QuantizerValue2Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [2][BlockType5=Y2AC], Decoder Only 9389 uint32_t Reserved409 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9390 }; 9391 uint32_t Value; 9392 } DW12; 9393 union 9394 { 9395 //!< DWORD 13 9396 struct 9397 { 9398 uint32_t QuantizerValue3Blocktype0Y1Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType0=Y1DC], Decoder Only 9399 uint32_t Reserved425 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9400 uint32_t QuantizerValue3Blocktype1Y1Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType1=Y1AC], Decoder Only 9401 uint32_t Reserved441 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9402 }; 9403 uint32_t Value; 9404 } DW13; 9405 union 9406 { 9407 //!< DWORD 14 9408 struct 9409 { 9410 uint32_t QuantizerValue3Blocktype2Uvdc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType2=UVDC], Decoder Only 9411 uint32_t Reserved457 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9412 uint32_t QuantizerValue3Blocktype3Uvac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType3=UVAC], Decoder Only 9413 uint32_t Reserved473 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9414 }; 9415 uint32_t Value; 9416 } DW14; 9417 union 9418 { 9419 //!< DWORD 15 9420 struct 9421 { 9422 uint32_t QuantizerValue3Blocktype4Y2Dc : __CODEGEN_BITFIELD( 0, 8) ; //!< Quantizer Value [3][BlockType4=Y2DC], Decoder Only 9423 uint32_t Reserved489 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved, Decoder Only 9424 uint32_t QuantizerValue3Blocktype5Y2Ac : __CODEGEN_BITFIELD(16, 24) ; //!< Quantizer Value [3][BlockType5=Y2AC], Decoder Only 9425 uint32_t Reserved505 : __CODEGEN_BITFIELD(25, 31) ; //!< Reserved 9426 }; 9427 uint32_t Value; 9428 } DW15; 9429 union 9430 { 9431 //!< DWORD 16 9432 struct 9433 { 9434 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 9435 uint32_t CoeffprobabilityStreaminBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< CoeffProbability StreamIn Base Address, Decoder Only 9436 }; 9437 uint32_t Value; 9438 } DW16; 9439 union 9440 { 9441 //!< DWORD 17 9442 struct 9443 { 9444 uint32_t CoeffprobabilityStreaminAddress : __CODEGEN_BITFIELD( 0, 15) ; //!< CoeffProbability StreamIn Address, Decoder Only 9445 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9446 }; 9447 uint32_t Value; 9448 } DW17; 9449 union 9450 { 9451 //!< DWORD 18 9452 struct 9453 { 9454 uint32_t Reserved576 : __CODEGEN_BITFIELD( 0, 6) ; //!< Reserved 9455 uint32_t CoeffprobabilityStreaminArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL, Decoder Only 9456 uint32_t CoeffprobabilityStreaminMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< CoeffProbability StreamIn - Memory Compression Enable, Decoder Only 9457 uint32_t CoeffprobabilityStreaminMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE, Decoder Only 9458 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved, Decoder Only 9459 uint32_t CoeffprobabilityStreaminTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE, Decoder Only 9460 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9461 }; 9462 uint32_t Value; 9463 } DW18; 9464 union 9465 { 9466 //!< DWORD 19 9467 struct 9468 { 9469 uint32_t Mbsegmentidtreeprobs0 : __CODEGEN_BITFIELD( 0, 7) ; //!< MBSegmentIDTreeProbs[0] 9470 uint32_t Mbsegmentidtreeprobs1 : __CODEGEN_BITFIELD( 8, 15) ; //!< MBSegmentIDTreeProbs[1] 9471 uint32_t Mbsegmentidtreeprobs2 : __CODEGEN_BITFIELD(16, 23) ; //!< MBSegmentIDTreeProbs[2] 9472 uint32_t Reserved632 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9473 }; 9474 uint32_t Value; 9475 } DW19; 9476 union 9477 { 9478 //!< DWORD 20 9479 struct 9480 { 9481 uint32_t Interpredfromgrefrefprob : __CODEGEN_BITFIELD( 0, 7) ; //!< InterPredFromGRefRefProb 9482 uint32_t Interpredfromlastrefprob : __CODEGEN_BITFIELD( 8, 15) ; //!< InterPredFromLastRefProb 9483 uint32_t Intrambprob : __CODEGEN_BITFIELD(16, 23) ; //!< IntraMBProb 9484 uint32_t Mbnocoeffskipfalseprob : __CODEGEN_BITFIELD(24, 31) ; //!< MBNoCoeffSkipFalseProb 9485 }; 9486 uint32_t Value; 9487 } DW20; 9488 union 9489 { 9490 //!< DWORD 21 9491 struct 9492 { 9493 uint32_t Ymodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< YModeProb[0] 9494 uint32_t Ymodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< YModeProb[1] 9495 uint32_t Ymodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< YModeProb[2] 9496 uint32_t Ymodeprob3 : __CODEGEN_BITFIELD(24, 31) ; //!< YModeProb[3] 9497 }; 9498 uint32_t Value; 9499 } DW21; 9500 union 9501 { 9502 //!< DWORD 22 9503 struct 9504 { 9505 uint32_t Uvmodeprob0 : __CODEGEN_BITFIELD( 0, 7) ; //!< UVModeProb[0] 9506 uint32_t Uvmodeprob1 : __CODEGEN_BITFIELD( 8, 15) ; //!< UVModeProb[1] 9507 uint32_t Uvmodeprob2 : __CODEGEN_BITFIELD(16, 23) ; //!< UVModeProb[2] 9508 uint32_t Reserved728 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9509 }; 9510 uint32_t Value; 9511 } DW22; 9512 union 9513 { 9514 //!< DWORD 23 9515 struct 9516 { 9517 uint32_t Mvupdateprobs00 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][0] 9518 uint32_t Mvupdateprobs01 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][1] 9519 uint32_t Mvupdateprobs02 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][2] 9520 uint32_t Mvupdateprobs03 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][3] 9521 }; 9522 uint32_t Value; 9523 } DW23; 9524 union 9525 { 9526 //!< DWORD 24 9527 struct 9528 { 9529 uint32_t Mvupdateprobs04 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][4] 9530 uint32_t Mvupdateprobs05 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][5] 9531 uint32_t Mvupdateprobs06 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][6] 9532 uint32_t Mvupdateprobs07 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][7] 9533 }; 9534 uint32_t Value; 9535 } DW24; 9536 union 9537 { 9538 //!< DWORD 25 9539 struct 9540 { 9541 uint32_t Mvupdateprobs08 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][8] 9542 uint32_t Mvupdateprobs09 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][9] 9543 uint32_t Mvupdateprobs010 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][10] 9544 uint32_t Mvupdateprobs011 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][11] 9545 }; 9546 uint32_t Value; 9547 } DW25; 9548 union 9549 { 9550 //!< DWORD 26 9551 struct 9552 { 9553 uint32_t Mvupdateprobs012 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][12] 9554 uint32_t Mvupdateprobs013 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][13] 9555 uint32_t Mvupdateprobs014 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][14] 9556 uint32_t Mvupdateprobs015 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[0][15] 9557 }; 9558 uint32_t Value; 9559 } DW26; 9560 union 9561 { 9562 //!< DWORD 27 9563 struct 9564 { 9565 uint32_t Mvupdateprobs016 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[0][16] 9566 uint32_t Mvupdateprobs017 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[0][17] 9567 uint32_t Mvupdateprobs018 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[0][18] 9568 uint32_t Reserved888 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9569 }; 9570 uint32_t Value; 9571 } DW27; 9572 union 9573 { 9574 //!< DWORD 28 9575 struct 9576 { 9577 uint32_t Mvupdateprobs10 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][0] 9578 uint32_t Mvupdateprobs11 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][1] 9579 uint32_t Mvupdateprobs12 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][2] 9580 uint32_t Mvupdateprobs13 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][3] 9581 }; 9582 uint32_t Value; 9583 } DW28; 9584 union 9585 { 9586 //!< DWORD 29 9587 struct 9588 { 9589 uint32_t Mvupdateprobs14 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][4] 9590 uint32_t Mvupdateprobs15 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][5] 9591 uint32_t Mvupdateprobs16 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][6] 9592 uint32_t Mvupdateprobs17 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][7] 9593 }; 9594 uint32_t Value; 9595 } DW29; 9596 union 9597 { 9598 //!< DWORD 30 9599 struct 9600 { 9601 uint32_t Mvupdateprobs18 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][8] 9602 uint32_t Mvupdateprobs19 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][9] 9603 uint32_t Mvupdateprobs110 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][10] 9604 uint32_t Mvupdateprobs111 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][11] 9605 }; 9606 uint32_t Value; 9607 } DW30; 9608 union 9609 { 9610 //!< DWORD 31 9611 struct 9612 { 9613 uint32_t Mvupdateprobs112 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][12] 9614 uint32_t Mvupdateprobs113 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][13] 9615 uint32_t Mvupdateprobs114 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][14] 9616 uint32_t Mvupdateprobs115 : __CODEGEN_BITFIELD(24, 31) ; //!< MVUpdateProbs[1][15] 9617 }; 9618 uint32_t Value; 9619 } DW31; 9620 union 9621 { 9622 //!< DWORD 32 9623 struct 9624 { 9625 uint32_t Mvupdateprobs116 : __CODEGEN_BITFIELD( 0, 7) ; //!< MVUpdateProbs[1][16] 9626 uint32_t Mvupdateprobs117 : __CODEGEN_BITFIELD( 8, 15) ; //!< MVUpdateProbs[1][17] 9627 uint32_t Mvupdateprobs118 : __CODEGEN_BITFIELD(16, 23) ; //!< MVUpdateProbs[1][18] 9628 uint32_t Reserved1048 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 9629 }; 9630 uint32_t Value; 9631 } DW32; 9632 union 9633 { 9634 //!< DWORD 33 9635 struct 9636 { 9637 uint32_t Reflfdelta0ForIntraFrame : __CODEGEN_BITFIELD( 0, 6) ; //!< RefLFDelta0 (for INTRA FRAME) 9638 uint32_t Reserved1063 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9639 uint32_t Reflfdelta1ForLastFrame : __CODEGEN_BITFIELD( 8, 14) ; //!< RefLFDelta1 (for LAST FRAME) 9640 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9641 uint32_t Reflfdelta2ForGoldenFrame : __CODEGEN_BITFIELD(16, 22) ; //!< RefLFDelta2 (for GOLDEN FRAME) 9642 uint32_t Reserved1079 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9643 uint32_t Reflfdelta3ForAltrefFrame : __CODEGEN_BITFIELD(24, 30) ; //!< RefLFDelta3 (for ALTREF FRAME) 9644 uint32_t Reserved1087 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9645 }; 9646 uint32_t Value; 9647 } DW33; 9648 union 9649 { 9650 //!< DWORD 34 9651 struct 9652 { 9653 uint32_t Modelfdelta0ForBPredMode : __CODEGEN_BITFIELD( 0, 6) ; //!< ModeLFDelta0 (for B_PRED mode) 9654 uint32_t Reserved1095 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 9655 uint32_t Modelfdelta1ForZeromvMode : __CODEGEN_BITFIELD( 8, 14) ; //!< ModeLFDelta1(for ZEROMV mode) 9656 uint32_t Reserved1103 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 9657 uint32_t Modelfdelta2ForNearestNearAndNewMode : __CODEGEN_BITFIELD(16, 22) ; //!< ModeLFDelta2 (for Nearest, Near and New mode) 9658 uint32_t Reserved1111 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 9659 uint32_t Modelfdelta3ForSplitmvMode : __CODEGEN_BITFIELD(24, 30) ; //!< ModeLFDelta3 (for SPLITMV mode) 9660 uint32_t Reserved1119 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 9661 }; 9662 uint32_t Value; 9663 } DW34; 9664 union 9665 { 9666 //!< DWORD 35 9667 struct 9668 { 9669 uint32_t SegmentationIdStreamBaseAddress ; //!< Segmentation ID Stream Base Address 9670 }; 9671 uint32_t Value; 9672 } DW35; 9673 union 9674 { 9675 //!< DWORD 36 9676 struct 9677 { 9678 uint32_t SegmentationIdStreamBaseAddress4732 : __CODEGEN_BITFIELD( 0, 15) ; //!< Segmentation ID Stream Base Address [47:32] 9679 uint32_t Reserved1168 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9680 }; 9681 uint32_t Value; 9682 } DW36; 9683 union 9684 { 9685 //!< DWORD 37 9686 struct 9687 { 9688 uint32_t Reserved1184 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 9689 uint32_t CoeffprobabilityStreaminAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< CoeffProbability StreamIn Address - Index to Memory Object Control State (MOCS) Tables 9690 uint32_t SegmentationIdStreamArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9691 uint32_t SegmentationIdStreamMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Segmentation ID Stream - Memory Compression Enable 9692 uint32_t SegmentationIdStreamMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9693 uint32_t Reserved1195 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 9694 uint32_t SegmentationIdStreamTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9695 uint32_t Reserved1199 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 9696 }; 9697 uint32_t Value; 9698 } DW37; 9699 9700 //! \name Local enumerations 9701 9702 enum SUB_OPCODE_B 9703 { 9704 SUB_OPCODE_B_MFXVP8PICSTATE = 0, //!< No additional details 9705 }; 9706 9707 enum SUB_OPCODE_A 9708 { 9709 SUB_OPCODE_A_VP8COMMON = 0, //!< No additional details 9710 }; 9711 9712 enum MEDIA_COMMAND_OPCODE 9713 { 9714 MEDIA_COMMAND_OPCODE_VP8 = 4, //!< No additional details 9715 }; 9716 9717 enum PIPELINE 9718 { 9719 PIPELINE_VIDEOCODEC = 2, //!< No additional details 9720 }; 9721 9722 enum COMMAND_TYPE 9723 { 9724 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 9725 }; 9726 9727 //! \brief MC_FILTER_SELECT 9728 //! \details 9729 //! To specify VP8 Profile of operation. 9730 enum MC_FILTER_SELECT 9731 { 9732 MC_FILTER_SELECT_UNNAMED0 = 0, //!< 6-tap filter (regular filter mode) 9733 MC_FILTER_SELECT_UNNAMED1 = 1, //!< 2-tap bilinear filter (simple profile/version mode) 9734 }; 9735 9736 //! \brief CHROMA_FULL_PIXEL_MC_FILTER_MODE 9737 //! \details 9738 //! To specify VP8 Profile of operation. 9739 enum CHROMA_FULL_PIXEL_MC_FILTER_MODE 9740 { 9741 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED0 = 0, //!< Chroma MC filter operates in sub-pixel mode 9742 CHROMA_FULL_PIXEL_MC_FILTER_MODE_UNNAMED1 = 1, //!< Chroma MC filter only operates in full pixel position, i.e. no sub-pixel interpolation. 9743 }; 9744 9745 //! \brief DBLKFILTERTYPE 9746 //! \details 9747 //! To specify VP8 Profile of operation. 9748 enum DBLKFILTERTYPE 9749 { 9750 DBLKFILTERTYPE_UNNAMED0 = 0, //!< Use a full feature normal deblocking filter 9751 DBLKFILTERTYPE_UNNAMED1 = 1, //!< Use a simple filter for deblocking 9752 }; 9753 9754 enum SKEYFRAMEFLAG 9755 { 9756 SKEYFRAMEFLAG_NON_KEYFRAMEP_FRAME = 0, //!< No additional details 9757 SKEYFRAMEFLAG_KEYFRAMEI_FRAME = 1, //!< No additional details 9758 }; 9759 9760 //! \brief SEGMENTATION_ID_STREAMOUT_ENABLE 9761 //! \details 9762 //! When 0, no output needed. 9763 enum SEGMENTATION_ID_STREAMOUT_ENABLE 9764 { 9765 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTDISABLED = 0, //!< No additional details 9766 SEGMENTATION_ID_STREAMOUT_ENABLE_STREAMOUTENABLED = 1, //!< No additional details 9767 }; 9768 9769 //! \brief SEGMENTATION_ID_STREAMIN_ENABLE 9770 //! \details 9771 //! When 0, no input needed. 9772 enum SEGMENTATION_ID_STREAMIN_ENABLE 9773 { 9774 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINDISABLED = 0, //!< No additional details 9775 SEGMENTATION_ID_STREAMIN_ENABLE_STREAMINENABLED = 1, //!< No additional details 9776 }; 9777 9778 enum SEGMENT_ENABLE_FLAG 9779 { 9780 SEGMENT_ENABLE_FLAG_UNNAMED0 = 0, //!< Disable Segmentation processing in the current frame 9781 SEGMENT_ENABLE_FLAG_UNNAMED1 = 1, //!< Enable Segmentation processing in the current frame 9782 }; 9783 9784 enum UPDATE_MBSEGMENT_MAP_FLAG 9785 { 9786 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED0 = 0, //!< Disable segmentation update 9787 UPDATE_MBSEGMENT_MAP_FLAG_UNNAMED1 = 1, //!< Enable segmentation update, and to enable reading segment_id for each MB. 9788 }; 9789 9790 //! \brief MB_NOCOEFF_SKIPFLAG 9791 //! \details 9792 //! Frame level control if Skip MB (with no non-zero coefficient) is allowed 9793 //! or not. 9794 enum MB_NOCOEFF_SKIPFLAG 9795 { 9796 MB_NOCOEFF_SKIPFLAG_UNNAMED0 = 0, //!< All MBs will have its MB level signaling mb_skip_coeff forced to 0. That is, no skip of coefficient record in the bitstream (even their values are all 0s) 9797 MB_NOCOEFF_SKIPFLAG_UNNAMED1 = 1, //!< Skip MB is enabled in the per MB record. 9798 }; 9799 9800 enum MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED 9801 { 9802 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED0 = 0, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is disabled. 9803 MODE_REFERENCE_LOOP_FILTER_DELTA_ENABLED_UNNAMED1 = 1, //!< Mode or Reference Loop Filter Delta Adjustment for current frame is enabled. 9804 }; 9805 9806 enum LOG2_NUM_OF_PARTITION 9807 { 9808 LOG2_NUM_OF_PARTITION_1TOKENPARTITION = 0, //!< No additional details 9809 LOG2_NUM_OF_PARTITION_2TOKENPARTITION = 1, //!< No additional details 9810 LOG2_NUM_OF_PARTITION_4TOKENPARTITION = 2, //!< No additional details 9811 LOG2_NUM_OF_PARTITION_8TOKENPARTITION = 3, //!< No additional details 9812 }; 9813 9814 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT0 9815 //! \details 9816 //! There are max 4 segments per frame, each segment can have its own 9817 //! deblocking filter level. When segmentation is disabled, only segment 0 9818 //! parameter is used for the entire frame. 9819 enum DBLKFILTERLEVEL_FOR_SEGMENT0 9820 { 9821 DBLKFILTERLEVEL_FOR_SEGMENT0_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9822 }; 9823 9824 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT1 9825 //! \details 9826 //! There are max 4 segments per frame, each segment can have its own 9827 //! deblocking filter level. When segmentation is disabled, only segment 0 9828 //! parameter is used for the entire frame. 9829 enum DBLKFILTERLEVEL_FOR_SEGMENT1 9830 { 9831 DBLKFILTERLEVEL_FOR_SEGMENT1_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9832 }; 9833 9834 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT2 9835 //! \details 9836 //! There are max 4 segments per frame, each segment can have its own 9837 //! deblocking filter level. When segmentation is disabled, only segment 0 9838 //! parameter is used for the entire frame. 9839 enum DBLKFILTERLEVEL_FOR_SEGMENT2 9840 { 9841 DBLKFILTERLEVEL_FOR_SEGMENT2_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9842 }; 9843 9844 //! \brief DBLKFILTERLEVEL_FOR_SEGMENT3 9845 //! \details 9846 //! There are max 4 segments per frame, each segment can have its own 9847 //! deblocking filter level. When segmentation is disabled, only segment 0 9848 //! parameter is used for the entire frame. 9849 enum DBLKFILTERLEVEL_FOR_SEGMENT3 9850 { 9851 DBLKFILTERLEVEL_FOR_SEGMENT3_SIGNIFIESDISABLEINLOOPDEBLOCKINGOPERATION = 0, //!< This is used to set a VP8 profile without in loop deblocker. 9852 }; 9853 9854 //! \brief COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9855 //! \details 9856 //! This field controls the priority of arbitration used in the GAC/GAM 9857 //! pipeline for this surface. 9858 enum COEFFPROBABILITY_STREAMIN__ARBITRATION_PRIORITY_CONTROL 9859 { 9860 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9861 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9862 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9863 COEFFPROBABILITY_STREAMIN_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9864 }; 9865 9866 //! \brief COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9867 //! \details 9868 //! Distinguishes Vertical from Horizontal compression. Please refer to 9869 //! vol1a 9870 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9871 //! section for more details. 9872 enum COEFFPROBABILITY_STREAMIN__MEMORY_COMPRESSION_MODE 9873 { 9874 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9875 COEFFPROBABILITY_STREAMIN_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9876 }; 9877 9878 //! \brief COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9879 //! \details 9880 //! <b>For Media Surfaces:</b> 9881 //! This field specifies the tiled resource mode. 9882 enum COEFFPROBABILITY_STREAMIN__TILED_RESOURCE_MODE 9883 { 9884 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9885 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9886 COEFFPROBABILITY_STREAMIN_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9887 }; 9888 9889 //! \brief SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9890 //! \details 9891 //! This field controls the priority of arbitration used in the GAC/GAM 9892 //! pipeline for this surface. 9893 enum SEGMENTATION_ID_STREAM__ARBITRATION_PRIORITY_CONTROL 9894 { 9895 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 9896 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 9897 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 9898 SEGMENTATION_ID_STREAM_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 9899 }; 9900 9901 //! \brief SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9902 //! \details 9903 //! Distinguishes Vertical from Horizontal compression. Please refer to 9904 //! vol1a 9905 //! <b>Memory Data Formats</b> chapter, <b>Media Memory Compression</b> 9906 //! section for more details. 9907 enum SEGMENTATION_ID_STREAM__MEMORY_COMPRESSION_MODE 9908 { 9909 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 9910 SEGMENTATION_ID_STREAM_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 9911 }; 9912 9913 //! \brief SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9914 //! \details 9915 //! <b>For Media Surfaces:</b> 9916 //! This field specifies the tiled resource mode. 9917 enum SEGMENTATION_ID_STREAM__TILED_RESOURCE_MODE 9918 { 9919 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 9920 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 9921 SEGMENTATION_ID_STREAM_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 9922 }; 9923 9924 //! \name Initializations 9925 9926 //! \brief Explicit member initialization function 9927 MFX_VP8_PIC_STATE_CMD(); 9928 9929 static const size_t dwSize = 38; 9930 static const size_t byteSize = 152; 9931 }; 9932 9933 //! 9934 //! \brief MFX_JPEG_HUFF_TABLE_STATE 9935 //! \details 9936 //! This Huffman table commands contains both DC and AC tables for either 9937 //! luma or chroma. Once a Huffman table has been defined for a particular 9938 //! destination, it replaces the previous tables stored in that destination 9939 //! and shall be used in the remaining Scans of the current image. A Huffman 9940 //! table will be sent to H/W only when it is loaded from bitstream. 9941 //! 9942 struct MFX_JPEG_HUFF_TABLE_STATE_CMD 9943 { 9944 union 9945 { 9946 //!< DWORD 0 9947 struct 9948 { 9949 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 9950 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 9951 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 9952 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 9953 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 9954 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 9955 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 9956 }; 9957 uint32_t Value; 9958 } DW0; 9959 union 9960 { 9961 //!< DWORD 1 9962 struct 9963 { 9964 uint32_t Hufftableid1Bit : __CODEGEN_BITFIELD( 0, 0) ; //!< HUFFTABLEID_1_BIT 9965 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 9966 }; 9967 uint32_t Value; 9968 } DW1; 9969 9970 uint32_t DcBits128BitArray[3]; //!< DC_BITS (12 8-bit array) 9971 9972 uint32_t DcHuffval128BitArray[3]; //!< DC_HUFFVAL (12 8-bit array) 9973 9974 uint32_t AcBits168BitArray[4]; //!< AC_BITS (16 8-bit array) 9975 9976 uint32_t AcHuffval1608BitArray[40]; //!< AC_HUFFVAL (160 8-bit array) 9977 9978 union 9979 { 9980 //!< DWORD 52 9981 struct 9982 { 9983 uint32_t AcHuffval28BitArray : __CODEGEN_BITFIELD( 0, 15) ; //!< AC_HUFFVAL(2-8 bit array) 9984 uint32_t Reserved1680 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 9985 }; 9986 uint32_t Value; 9987 } DW52; 9988 9989 //! \name Local enumerations 9990 9991 enum SUBOPCODE_B 9992 { 9993 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 9994 }; 9995 9996 enum SUBOPCODE_A 9997 { 9998 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 9999 }; 10000 10001 enum MEDIA_COMMAND_OPCODE 10002 { 10003 MEDIA_COMMAND_OPCODE_JPEGCOMMON = 7, //!< No additional details 10004 }; 10005 10006 enum PIPELINE 10007 { 10008 PIPELINE_MFXMULTIDW = 2, //!< No additional details 10009 }; 10010 10011 enum COMMAND_TYPE 10012 { 10013 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 10014 }; 10015 10016 //! \brief HUFFTABLEID_1_BIT 10017 //! \details 10018 //! Identifies the huffman table. 10019 enum HUFFTABLEID_1_BIT 10020 { 10021 HUFFTABLEID_1_BIT_Y = 0, //!< Huffman table for Y 10022 }; 10023 10024 //! \name Initializations 10025 10026 //! \brief Explicit member initialization function 10027 MFX_JPEG_HUFF_TABLE_STATE_CMD(); 10028 10029 static const size_t dwSize = 53; 10030 static const size_t byteSize = 212; 10031 }; 10032 10033 //! 10034 //! \brief GRAPHICSADDRESS63_6 10035 //! \details 10036 //! This structure is intended to define the upper bits of the 10037 //! GraphicsAddress, when bits 5:0 are already defined in the referring 10038 //! register. So bit 0 of this structure should correspond to bit 6 of the 10039 //! full GraphicsAddress. 10040 //! 10041 struct GRAPHICSADDRESS63_6_CMD 10042 { 10043 union 10044 { 10045 //!< DWORD 0..1 10046 struct 10047 { 10048 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10049 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 10050 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 10051 }; 10052 uint32_t Value[2]; 10053 } DW0_1; 10054 10055 //! \name Local enumerations 10056 10057 //! \name Initializations 10058 10059 //! \brief Explicit member initialization function 10060 GRAPHICSADDRESS63_6_CMD(); 10061 10062 static const size_t dwSize = 2; 10063 static const size_t byteSize = 8; 10064 }; 10065 10066 //! 10067 //! \brief MFX_PIPE_BUF_ADDR_STATE 10068 //! \details 10069 //! This state command provides the memory base addresses for all row 10070 //! stores, StreamOut buffer and reconstructed picture output buffers 10071 //! required by the MFD or MFC Engine (that are in addition to the row 10072 //! stores of the Bit Stream Decoding/Encoding Unit (BSD/BSE) and the 10073 //! reference picture buffers). 10074 //! This is a picture level state command and is common among all codec 10075 //! standards and for both encoder and decoder operating modes. However, 10076 //! some fields may only applicable to a specific codec standard. All Pixel 10077 //! Surfaces (original, reference frame and reconstructed frame) in the 10078 //! Encoder are programmed with the same surface state (NV12 and TileY 10079 //! format), except each has its own frame buffer base address. In the tile 10080 //! format, there is no need to provide buffer offset for each slice; since 10081 //! from each MB address, the hardware can calculated the corresponding 10082 //! memory location within the frame buffer directly. 10083 //! 10084 struct MFX_PIPE_BUF_ADDR_STATE_CMD 10085 { 10086 union 10087 { 10088 //!< DWORD 0 10089 struct 10090 { 10091 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 10092 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 10093 uint32_t SubopcodeB : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODE_B 10094 uint32_t SubopcodeA : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODE_A 10095 uint32_t CommonOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< COMMON_OPCODE 10096 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 10097 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 10098 }; 10099 uint32_t Value; 10100 } DW0; 10101 union 10102 { 10103 //!< DWORD 1 10104 struct 10105 { 10106 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10107 uint32_t PreDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Pre Deblocking Destination Address 10108 }; 10109 uint32_t Value; 10110 } DW1; 10111 union 10112 { 10113 //!< DWORD 2 10114 struct 10115 { 10116 uint32_t PreDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Pre Deblocking Destination Address High 10117 uint32_t Reserved80 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10118 }; 10119 uint32_t Value; 10120 } DW2; 10121 union 10122 { 10123 //!< DWORD 3 10124 struct 10125 { 10126 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10127 uint32_t PreDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10128 uint32_t PreDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10129 uint32_t PreDeblockingMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< Pre Deblocking - Memory Compression Mode 10130 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10131 uint32_t PreDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< PRE_DEBLOCKING__TILED_RESOURCE_MODE 10132 uint32_t Reserved111 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10133 }; 10134 uint32_t Value; 10135 } DW3; 10136 union 10137 { 10138 //!< DWORD 4 10139 struct 10140 { 10141 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10142 uint32_t PostDeblockingDestinationAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Post Deblocking Destination Address 10143 }; 10144 uint32_t Value; 10145 } DW4; 10146 union 10147 { 10148 //!< DWORD 5 10149 struct 10150 { 10151 uint32_t PostDeblockingDestinationAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Post Deblocking Destination Address High 10152 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10153 }; 10154 uint32_t Value; 10155 } DW5; 10156 union 10157 { 10158 //!< DWORD 6 10159 struct 10160 { 10161 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10162 uint32_t PostDeblockingArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10163 uint32_t PostDeblockingMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10164 uint32_t PostDeblockingMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10165 uint32_t Reserved203 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10166 uint32_t PostDeblockingTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< POST_DEBLOCKING__TILED_RESOURCE_MODE 10167 uint32_t Reserved207 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10168 }; 10169 uint32_t Value; 10170 } DW6; 10171 union 10172 { 10173 //!< DWORD 7 10174 struct 10175 { 10176 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10177 uint32_t OriginalUncompressedPictureSourceAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Original Uncompressed Picture Source Address 10178 }; 10179 uint32_t Value; 10180 } DW7; 10181 union 10182 { 10183 //!< DWORD 8 10184 struct 10185 { 10186 uint32_t OriginalUncompressedPictureSourceAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Original Uncompressed Picture Source Address High 10187 uint32_t Reserved272 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10188 }; 10189 uint32_t Value; 10190 } DW8; 10191 union 10192 { 10193 //!< DWORD 9 10194 struct 10195 { 10196 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10197 uint32_t OriginalUncompressedPictureSourceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10198 uint32_t OriginalUncompressedPictureMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10199 uint32_t OriginalUncompressedPictureMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10200 uint32_t Reserved299 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10201 uint32_t OriginalUncompressedPictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10202 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10203 }; 10204 uint32_t Value; 10205 } DW9; 10206 union 10207 { 10208 //!< DWORD 10 10209 struct 10210 { 10211 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10212 uint32_t StreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< StreamOut Data Destination Base Address 10213 }; 10214 uint32_t Value; 10215 } DW10; 10216 union 10217 { 10218 //!< DWORD 11 10219 struct 10220 { 10221 uint32_t StreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< StreamOut Data Destination Base Address High 10222 uint32_t Reserved368 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10223 }; 10224 uint32_t Value; 10225 } DW11; 10226 union 10227 { 10228 //!< DWORD 12 10229 struct 10230 { 10231 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10232 uint32_t StreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10233 uint32_t StreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10234 uint32_t StreamoutDataDestinationMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10235 uint32_t Reserved395 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10236 uint32_t StreamoutDataDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10237 uint32_t Reserved399 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10238 }; 10239 uint32_t Value; 10240 } DW12; 10241 union 10242 { 10243 //!< DWORD 13 10244 struct 10245 { 10246 uint32_t Reserved416 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10247 uint32_t IntraRowStoreScratchBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Intra Row Store Scratch Buffer Base Address 10248 }; 10249 uint32_t Value; 10250 } DW13; 10251 union 10252 { 10253 //!< DWORD 14 10254 struct 10255 { 10256 uint32_t IntraRowStoreScratchBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Intra Row Store Scratch Buffer Base Address High 10257 uint32_t Reserved464 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10258 }; 10259 uint32_t Value; 10260 } DW14; 10261 union 10262 { 10263 //!< DWORD 15 10264 struct 10265 { 10266 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10267 uint32_t IntraRowStoreScratchBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10268 uint32_t IntraRowStoreScratchBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10269 uint32_t IntraRowStoreScratchBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10270 uint32_t Reserved491 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10271 uint32_t IntraRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10272 uint32_t IntraRowStoreScratchBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10273 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10274 }; 10275 uint32_t Value; 10276 } DW15; 10277 union 10278 { 10279 //!< DWORD 16 10280 struct 10281 { 10282 uint32_t Reserved512 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10283 uint32_t DeblockingFilterRowStoreScratchBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Deblocking Filter Row Store Scratch Base Address 10284 }; 10285 uint32_t Value; 10286 } DW16; 10287 union 10288 { 10289 //!< DWORD 17 10290 struct 10291 { 10292 uint32_t DeblockingFilterRowStoreScratchBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Deblocking Filter Row Store Scratch Base Address High 10293 uint32_t Reserved560 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10294 }; 10295 uint32_t Value; 10296 } DW17; 10297 union 10298 { 10299 //!< DWORD 18 10300 struct 10301 { 10302 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10303 uint32_t DeblockingFilterRowStoreScratchArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10304 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10305 uint32_t DeblockingFilterRowStoreScratchMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10306 uint32_t Reserved587 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 10307 uint32_t DeblockingFilterRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10308 uint32_t DeblockingFilterRowStoreTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10309 uint32_t Reserved591 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10310 }; 10311 uint32_t Value; 10312 } DW18; 10313 10314 mhw_vdbox_mfx_g10_X::GRAPHICSADDRESS63_6_CMD Refpicbaseaddr[16]; //!< RefPicBaseAddr 10315 10316 union 10317 { 10318 //!< DWORD 51 10319 struct 10320 { 10321 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10322 uint32_t ReferencePictureArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10323 uint32_t Reserved1641 : __CODEGEN_BITFIELD( 9, 12) ; //!< Reserved 10324 uint32_t ReferencePictureTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< REFERENCE_PICTURE__TILED_RESOURCE_MODE 10325 uint32_t Reserved1647 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10326 }; 10327 uint32_t Value; 10328 } DW51; 10329 union 10330 { 10331 //!< DWORD 52 10332 struct 10333 { 10334 uint32_t Reserved1664 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10335 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address 10336 }; 10337 uint32_t Value; 10338 } DW52; 10339 union 10340 { 10341 //!< DWORD 53 10342 struct 10343 { 10344 uint32_t MacroblockBufferBaseAddressOrDecodedPictureErrorStatusBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock Buffer Base Address or Decoded Picture Error/Status Buffer Base Address High 10345 uint32_t Reserved1712 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10346 }; 10347 uint32_t Value; 10348 } DW53; 10349 union 10350 { 10351 //!< DWORD 54 10352 struct 10353 { 10354 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10355 uint32_t MacroblockStatusBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10356 uint32_t MacroblockStatusBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10357 uint32_t MacroblockStatusBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10358 uint32_t Reserved1739 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10359 uint32_t MacroblockStatusBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10360 uint32_t Reserved1743 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10361 }; 10362 uint32_t Value; 10363 } DW54; 10364 union 10365 { 10366 //!< DWORD 55 10367 struct 10368 { 10369 uint32_t Reserved1760 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10370 uint32_t MacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Macroblock ILDB StreamOut Buffer Base Address 10371 }; 10372 uint32_t Value; 10373 } DW55; 10374 union 10375 { 10376 //!< DWORD 56 10377 struct 10378 { 10379 uint32_t MacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Macroblock ILDB StreamOut Buffer Base Address High 10380 uint32_t Reserved1808 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10381 }; 10382 uint32_t Value; 10383 } DW56; 10384 union 10385 { 10386 //!< DWORD 57 10387 struct 10388 { 10389 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10390 uint32_t MacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10391 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10392 uint32_t MacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10393 uint32_t Reserved1835 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10394 uint32_t MacroblockIldbStreamoutTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10395 uint32_t Reserved1839 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10396 }; 10397 uint32_t Value; 10398 } DW57; 10399 union 10400 { 10401 //!< DWORD 58 10402 struct 10403 { 10404 uint32_t Reserved1856 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10405 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address 10406 }; 10407 uint32_t Value; 10408 } DW58; 10409 union 10410 { 10411 //!< DWORD 59 10412 struct 10413 { 10414 uint32_t SecondMacroblockIldbStreamoutBufferBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Second Macroblock ILDB StreamOut Buffer Base Address High 10415 uint32_t Reserved1904 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10416 }; 10417 uint32_t Value; 10418 } DW59; 10419 union 10420 { 10421 //!< DWORD 60 10422 struct 10423 { 10424 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 10425 uint32_t SecondMacroblockIldbStreamoutBufferArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Second Macroblock ILDB StreamOut Buffer - Arbitration Priority Control 10426 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10427 uint32_t SecondMacroblockIldbStreamoutBufferMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10428 uint32_t Reserved1931 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10429 uint32_t SecondMacroblockIldbStreamoutBufferTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10430 uint32_t Reserved1935 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10431 }; 10432 uint32_t Value; 10433 } DW60; 10434 union 10435 { 10436 //!< DWORD 61 10437 struct 10438 { 10439 uint32_t ReferencePicture0MemoryCompressionEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 10440 uint32_t ReferencePicture0MemoryCompressionMode : __CODEGEN_BITFIELD( 1, 1) ; //!< REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 10441 uint32_t ReferencePicture1MemoryCompressionEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 10442 uint32_t ReferencePicture1MemoryCompressionMode : __CODEGEN_BITFIELD( 3, 3) ; //!< REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 10443 uint32_t ReferencePicture2MemoryCompressionEnable : __CODEGEN_BITFIELD( 4, 4) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 10444 uint32_t ReferencePicture2MemoryCompressionMode : __CODEGEN_BITFIELD( 5, 5) ; //!< REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 10445 uint32_t ReferencePicture3MemoryCompressionEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 10446 uint32_t ReferencePicture3MemoryCompressionMode : __CODEGEN_BITFIELD( 7, 7) ; //!< REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 10447 uint32_t ReferencePicture4MemoryCompressionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 10448 uint32_t ReferencePicture4MemoryCompressionMode : __CODEGEN_BITFIELD( 9, 9) ; //!< REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 10449 uint32_t ReferencePicture5MemoryCompressionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 10450 uint32_t ReferencePicture5MemoryCompressionMode : __CODEGEN_BITFIELD(11, 11) ; //!< REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 10451 uint32_t ReferencePicture6MemoryCompressionEnable : __CODEGEN_BITFIELD(12, 12) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 10452 uint32_t ReferencePicture6MemoryCompressionMode : __CODEGEN_BITFIELD(13, 13) ; //!< REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 10453 uint32_t ReferencePicture7MemoryCompressionEnable : __CODEGEN_BITFIELD(14, 14) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 10454 uint32_t ReferencePicture7MemoryCompressionMode : __CODEGEN_BITFIELD(15, 15) ; //!< REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 10455 uint32_t ReferencePicture8MemoryCompressionEnable : __CODEGEN_BITFIELD(16, 16) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 10456 uint32_t ReferencePicture8MemoryCompressionMode : __CODEGEN_BITFIELD(17, 17) ; //!< REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 10457 uint32_t ReferencePicture9MemoryCompressionEnable : __CODEGEN_BITFIELD(18, 18) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 10458 uint32_t ReferencePicture9MemoryCompressionMode : __CODEGEN_BITFIELD(19, 19) ; //!< REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 10459 uint32_t ReferencePicture10MemoryCompressionEnable : __CODEGEN_BITFIELD(20, 20) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 10460 uint32_t ReferencePicture10MemoryCompressionMode : __CODEGEN_BITFIELD(21, 21) ; //!< REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 10461 uint32_t ReferencePicture11MemoryCompressionEnable : __CODEGEN_BITFIELD(22, 22) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 10462 uint32_t ReferencePicture11MemoryCompressionMode : __CODEGEN_BITFIELD(23, 23) ; //!< REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 10463 uint32_t ReferencePicture12MemoryCompressionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 10464 uint32_t ReferencePicture12MemoryCompressionMode : __CODEGEN_BITFIELD(25, 25) ; //!< REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 10465 uint32_t ReferencePicture13MemoryCompressionEnable : __CODEGEN_BITFIELD(26, 26) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 10466 uint32_t ReferencePicture13MemoryCompressionMode : __CODEGEN_BITFIELD(27, 27) ; //!< REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 10467 uint32_t ReferencePicture14MemoryCompressionEnable : __CODEGEN_BITFIELD(28, 28) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 10468 uint32_t ReferencePicture14MemoryCompressionMode : __CODEGEN_BITFIELD(29, 29) ; //!< REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 10469 uint32_t ReferencePicture15MemoryCompressionEnable : __CODEGEN_BITFIELD(30, 30) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 10470 uint32_t ReferencePicture15MemoryCompressionMode : __CODEGEN_BITFIELD(31, 31) ; //!< REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 10471 }; 10472 uint32_t Value; 10473 } DW61; 10474 union 10475 { 10476 //!< DWORD 62 10477 struct 10478 { 10479 uint32_t Reserved1984 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10480 uint32_t ScaledReferenceSurfaceBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< Scaled Reference Surface Base Address 10481 }; 10482 uint32_t Value; 10483 } DW62; 10484 union 10485 { 10486 //!< DWORD 63 10487 struct 10488 { 10489 uint32_t ScaledReferenceSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Scaled Reference Surface Base Address High 10490 uint32_t Reserved2032 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10491 }; 10492 uint32_t Value; 10493 } DW63; 10494 union 10495 { 10496 //!< DWORD 64 10497 struct 10498 { 10499 uint32_t Reserved2048 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 10500 uint32_t ScaledReferenceSurfaceIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Scaled Reference Surface - Index to Memory Object Control State (MOCS) Tables 10501 uint32_t ScaleReferenceSurfaceArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 10502 uint32_t ScaledReferenceSurfaceMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Scaled Reference Surface - Memory Compression Enable 10503 uint32_t ScaledReferenceSurfaceMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 10504 uint32_t Reserved2059 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10505 uint32_t ScaledReferenceSurfaceTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 10506 uint32_t Reserved2063 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10507 }; 10508 uint32_t Value; 10509 } DW64; 10510 union 10511 { 10512 //!< DWORD 65 10513 struct 10514 { 10515 uint32_t Reserved2080 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 10516 uint32_t SlicesizeStreamoutDataDestinationBaseAddress : __CODEGEN_BITFIELD( 6, 31) ; //!< SliceSize StreamOut Data Destination Base Address 10517 }; 10518 uint32_t Value; 10519 } DW65; 10520 union 10521 { 10522 //!< DWORD 66 10523 struct 10524 { 10525 uint32_t SlicesizeStreamoutDataDestinationBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceSize StreamOut Data Destination Base Address High 10526 uint32_t Reserved2128 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 10527 }; 10528 uint32_t Value; 10529 } DW66; 10530 union 10531 { 10532 //!< DWORD 67 10533 struct 10534 { 10535 uint32_t Reserved2144 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 10536 uint32_t SlicesizeStreamoutDataDestinationIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SliceSize StreamOut Data Destination - Index to Memory Object Control State (MOCS) Tables 10537 uint32_t SlicesizeStreamoutDataDestinationArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10538 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SliceSize StreamOut Data Destination - Memory Compression Enable 10539 uint32_t SlicesizeStreamoutDataDestinationMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10540 uint32_t Reserved2155 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 10541 uint32_t SlicesizeStreamoutDataDestinationTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10542 uint32_t Reserved2159 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 10543 }; 10544 uint32_t Value; 10545 } DW67; 10546 10547 //! \name Local enumerations 10548 10549 enum SUBOPCODE_B 10550 { 10551 SUBOPCODE_B_UNNAMED2 = 2, //!< No additional details 10552 }; 10553 10554 enum SUBOPCODE_A 10555 { 10556 SUBOPCODE_A_UNNAMED0 = 0, //!< No additional details 10557 }; 10558 10559 enum COMMON_OPCODE 10560 { 10561 COMMON_OPCODE_MFXCOMMONSTATE = 0, //!< No additional details 10562 }; 10563 10564 enum PIPELINE 10565 { 10566 PIPELINE_MFXPIPEBUFADDRSTATE = 2, //!< No additional details 10567 }; 10568 10569 enum COMMAND_TYPE 10570 { 10571 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 10572 }; 10573 10574 //! \brief PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10575 //! \details 10576 //! This field controls the priority of arbitration used in the GAC/GAM 10577 //! pipeline for this surface. 10578 enum PRE_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10579 { 10580 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10581 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10582 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10583 PRE_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10584 }; 10585 10586 //! \brief PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10587 //! \details 10588 //! Memory compression will be attempted for this surface. 10589 enum PRE_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10590 { 10591 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10592 PRE_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10593 }; 10594 10595 //! \brief PRE_DEBLOCKING__TILED_RESOURCE_MODE 10596 //! \details 10597 //! <b>For Media Surfaces:</b> 10598 //! This field specifies the tiled resource mode. 10599 enum PRE_DEBLOCKING__TILED_RESOURCE_MODE 10600 { 10601 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10602 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10603 PRE_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10604 }; 10605 10606 //! \brief POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10607 //! \details 10608 //! This field controls the priority of arbitration used in the GAC/GAM 10609 //! pipeline for this surface. 10610 enum POST_DEBLOCKING__ARBITRATION_PRIORITY_CONTROL 10611 { 10612 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10613 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10614 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10615 POST_DEBLOCKING_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10616 }; 10617 10618 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10619 //! \details 10620 //! Memory compression will be attempted for this surface. 10621 enum POST_DEBLOCKING__MEMORY_COMPRESSION_ENABLE 10622 { 10623 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10624 POST_DEBLOCKING_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10625 }; 10626 10627 //! \brief POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10628 //! \details 10629 //! Distinguishes Vertical from Horizontal compression. Please refer to 10630 //! vol1a <b>Memory Data Formats chapter -section</b> Media Memory 10631 //! Compression <b>for more details.</b> 10632 enum POST_DEBLOCKING__MEMORY_COMPRESSION_MODE 10633 { 10634 POST_DEBLOCKING_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10635 }; 10636 10637 //! \brief POST_DEBLOCKING__TILED_RESOURCE_MODE 10638 //! \details 10639 //! <b>For Media Surfaces:</b> 10640 //! This field specifies the tiled resource mode. 10641 enum POST_DEBLOCKING__TILED_RESOURCE_MODE 10642 { 10643 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10644 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10645 POST_DEBLOCKING_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10646 }; 10647 10648 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10649 //! \details 10650 //! This field controls the priority of arbitration used in the GAC/GAM 10651 //! pipeline for this surface. 10652 enum ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE__ARBITRATION_PRIORITY_CONTROL 10653 { 10654 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10655 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10656 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10657 ORIGINAL_UNCOMPRESSED_PICTURE_SOURCE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10658 }; 10659 10660 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10661 //! \details 10662 //! Note: This is a READ Surface. The setting of this bit should match the 10663 //! settings on how this is written out before. 10664 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_ENABLE 10665 { 10666 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10667 }; 10668 10669 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10670 //! \details 10671 //! Distinguishes Vertical from Horizontal compression. Please refer to 10672 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10673 //! more details. Note: This bit is not used unless Memory Compression 10674 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10675 //! bit should match the settings on how this is written out before 10676 enum ORIGINAL_UNCOMPRESSED_PICTURE__MEMORY_COMPRESSION_MODE 10677 { 10678 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10679 ORIGINAL_UNCOMPRESSED_PICTURE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10680 }; 10681 10682 //! \brief ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10683 //! \details 10684 //! <b>For Media Surfaces:</b> 10685 //! This field specifies the tiled resource mode. 10686 enum ORIGINAL_UNCOMPRESSED_PICTURE__TILED_RESOURCE_MODE 10687 { 10688 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10689 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10690 ORIGINAL_UNCOMPRESSED_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10691 }; 10692 10693 //! \brief STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10694 //! \details 10695 //! This field controls the priority of arbitration used in the GAC/GAM 10696 //! pipeline for this surface. 10697 enum STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 10698 { 10699 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10700 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10701 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10702 STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10703 }; 10704 10705 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10706 //! \details 10707 //! Note: This is a READ Surface. The setting of this bit should match the 10708 //! settings on how this is written out before. 10709 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_ENABLE 10710 { 10711 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10712 }; 10713 10714 //! \brief STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10715 //! \details 10716 //! Distinguishes Vertical from Horizontal compression. Please refer to 10717 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10718 //! more details. Note: This bit is not used unless Memory Compression 10719 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10720 //! bit should match the settings on how this is written out before 10721 enum STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 10722 { 10723 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10724 STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10725 }; 10726 10727 //! \brief STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10728 //! \details 10729 //! <b>For Media Surfaces:</b> 10730 //! This field specifies the tiled resource mode. 10731 enum STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 10732 { 10733 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10734 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10735 STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10736 }; 10737 10738 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10739 //! \details 10740 //! This field controls the priority of arbitration used in the GAC/GAM 10741 //! pipeline for this surface. 10742 enum INTRA_ROW_STORE_SCRATCH_BUFFER__ARBITRATION_PRIORITY_CONTROL 10743 { 10744 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10745 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10746 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10747 INTRA_ROW_STORE_SCRATCH_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10748 }; 10749 10750 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10751 //! \details 10752 //! This surface is linear surface. This bit must be set to "0" since only 10753 //! TileY/TileYf/TileYs surface is allowed to be compressed 10754 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_ENABLE 10755 { 10756 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10757 }; 10758 10759 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10760 //! \details 10761 //! Distinguishes Vertical from Horizontal compression. Please refer to 10762 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10763 //! more details. Note: This bit is not used unless Memory Compression 10764 //! Enable is set to "1" 10765 enum INTRA_ROW_STORE_SCRATCH_BUFFER__MEMORY_COMPRESSION_MODE 10766 { 10767 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10768 INTRA_ROW_STORE_SCRATCH_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10769 }; 10770 10771 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10772 //! \details 10773 //! This field controls if Intra Row Store is going to store inside Media 10774 //! Cache or to LLC. 10775 enum INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10776 { 10777 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 10778 INTRA_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage 10779 }; 10780 10781 //! \brief INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10782 //! \details 10783 //! <b>For Media Surfaces:</b> 10784 //! This field specifies the tiled resource mode. 10785 enum INTRA_ROW_STORE_SCRATCH_BUFFER__TILED_RESOURCE_MODE 10786 { 10787 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10788 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10789 INTRA_ROW_STORE_SCRATCH_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10790 }; 10791 10792 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10793 //! \details 10794 //! This field controls the priority of arbitration used in the GAC/GAM 10795 //! pipeline for this surface. 10796 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__ARBITRATION_PRIORITY_CONTROL 10797 { 10798 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10799 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10800 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10801 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10802 }; 10803 10804 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10805 //! \details 10806 //! This surface is linear surface. This bit must be set to "0" since only 10807 //! TileY/TileYf/TileYs surface is allowed to be compressed 10808 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_ENABLE 10809 { 10810 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10811 }; 10812 10813 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10814 //! \details 10815 //! Distinguishes Vertical from Horizontal compression. Please refer to 10816 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10817 //! more details. Note: This bit is not used unless Memory Compression 10818 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10819 //! bit should match the settings on how this is written out before. 10820 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH__MEMORY_COMPRESSION_MODE 10821 { 10822 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10823 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10824 }; 10825 10826 //! \brief DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10827 //! \details 10828 //! This field controls if Intra Row Store is going to store inside Media 10829 //! Internal Storage or to LLC. 10830 enum DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 10831 { 10832 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC 10833 DEBLOCKING_FILTER_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Media Internal Storage 10834 }; 10835 10836 //! \brief DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10837 //! \details 10838 //! <b>For Media Surfaces:</b> 10839 //! This field specifies the tiled resource mode. 10840 enum DEBLOCKING_FILTER_ROW_STORE__TILED_RESOURCE_MODE 10841 { 10842 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10843 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10844 DEBLOCKING_FILTER_ROW_STORE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10845 }; 10846 10847 //! \brief REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10848 //! \details 10849 //! This field controls the priority of arbitration used in the GAC/GAM 10850 //! pipeline for this surface. 10851 enum REFERENCE_PICTURE__ARBITRATION_PRIORITY_CONTROL 10852 { 10853 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10854 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10855 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10856 REFERENCE_PICTURE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10857 }; 10858 10859 //! \brief REFERENCE_PICTURE__TILED_RESOURCE_MODE 10860 //! \details 10861 //! <b>For Media Surfaces:</b> 10862 //! This field specifies the tiled resource mode. 10863 enum REFERENCE_PICTURE__TILED_RESOURCE_MODE 10864 { 10865 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10866 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10867 REFERENCE_PICTURE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10868 }; 10869 10870 //! \brief MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10871 //! \details 10872 //! This field controls the priority of arbitration used in the GAC/GAM 10873 //! pipeline for this surface. 10874 enum MACROBLOCK_STATUS_BUFFER__ARBITRATION_PRIORITY_CONTROL 10875 { 10876 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10877 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10878 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10879 MACROBLOCK_STATUS_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10880 }; 10881 10882 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10883 //! \details 10884 //! This surface is linear surface. This bit must be set to "0" since only 10885 //! TileY/TileYf/TileYs surface is allowed to be compressed 10886 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_ENABLE 10887 { 10888 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10889 }; 10890 10891 //! \brief MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10892 //! \details 10893 //! Distinguishes Vertical from Horizontal compression. Please refer to 10894 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10895 //! more details. Note: This bit is not used unless Memory Compression 10896 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10897 //! bit should match the settings on how this is written out before. 10898 enum MACROBLOCK_STATUS_BUFFER__MEMORY_COMPRESSION_MODE 10899 { 10900 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10901 MACROBLOCK_STATUS_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10902 }; 10903 10904 //! \brief MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10905 //! \details 10906 //! <b>For Media Surfaces:</b> 10907 //! This field specifies the tiled resource mode. 10908 enum MACROBLOCK_STATUS_BUFFER__TILED_RESOURCE_MODE 10909 { 10910 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10911 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10912 MACROBLOCK_STATUS_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10913 }; 10914 10915 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10916 //! \details 10917 //! This field controls the priority of arbitration used in the GAC/GAM 10918 //! pipeline for this surface. 10919 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__ARBITRATION_PRIORITY_CONTROL 10920 { 10921 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 10922 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 10923 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 10924 MACROBLOCK_ILDB_STREAMOUT_BUFFER_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 10925 }; 10926 10927 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10928 //! \details 10929 //! This surface is linear surface. This bit must be set to "0" since only 10930 //! TileY/TileYf/TileYs surface is allowed to be compressed 10931 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10932 { 10933 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10934 }; 10935 10936 //! \brief MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10937 //! \details 10938 //! Distinguishes Vertical from Horizontal compression. Please refer to 10939 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10940 //! more details. Note: This bit is not used unless Memory Compression 10941 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10942 //! bit should match the settings on how this is written out before. 10943 enum MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10944 { 10945 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10946 MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10947 }; 10948 10949 //! \brief MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10950 //! \details 10951 //! <b>For Media Surfaces:</b> 10952 //! This field specifies the tiled resource mode. 10953 enum MACROBLOCK_ILDB_STREAMOUT__TILED_RESOURCE_MODE 10954 { 10955 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10956 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10957 MACROBLOCK_ILDB_STREAMOUT_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10958 }; 10959 10960 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10961 //! \details 10962 //! This surface is linear surface. This bit must be set to "0" since only 10963 //! TileY/TileYf/TileYs surface is allowed to be compressed 10964 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_ENABLE 10965 { 10966 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10967 }; 10968 10969 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10970 //! \details 10971 //! Distinguishes Vertical from Horizontal compression. Please refer to 10972 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 10973 //! more details. Note: This bit is not used unless Memory Compression 10974 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 10975 //! bit should match the settings on how this is written out before. 10976 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__MEMORY_COMPRESSION_MODE 10977 { 10978 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 10979 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 10980 }; 10981 10982 //! \brief SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10983 //! \details 10984 //! <b>For Media Surfaces:</b> 10985 //! This field specifies the tiled resource mode. 10986 enum SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER__TILED_RESOURCE_MODE 10987 { 10988 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 10989 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 10990 SECOND_MACROBLOCK_ILDB_STREAMOUT_BUFFER_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 10991 }; 10992 10993 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_ENABLE 10994 { 10995 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 10996 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 10997 }; 10998 10999 //! \brief REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 11000 //! \details 11001 //! Distinguishes Vertical from Horizontal compression. Please refer to 11002 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11003 //! more details. Note: This bit is not used unless Memory Compression 11004 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11005 //! bit should match the settings on how this is written out before. 11006 enum REFERENCE_PICTURE_0__MEMORY_COMPRESSION_MODE 11007 { 11008 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11009 REFERENCE_PICTURE_0_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11010 }; 11011 11012 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_ENABLE 11013 { 11014 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11015 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11016 }; 11017 11018 //! \brief REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 11019 //! \details 11020 //! Distinguishes Vertical from Horizontal compression. Please refer to 11021 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11022 //! more details. Note: This bit is not used unless Memory Compression 11023 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11024 //! bit should match the settings on how this is written out before. 11025 enum REFERENCE_PICTURE_1__MEMORY_COMPRESSION_MODE 11026 { 11027 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11028 REFERENCE_PICTURE_1_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11029 }; 11030 11031 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_ENABLE 11032 { 11033 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11034 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11035 }; 11036 11037 //! \brief REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 11038 //! \details 11039 //! Distinguishes Vertical from Horizontal compression. Please refer to 11040 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11041 //! more details. Note: This bit is not used unless Memory Compression 11042 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11043 //! bit should match the settings on how this is written out before. 11044 enum REFERENCE_PICTURE_2__MEMORY_COMPRESSION_MODE 11045 { 11046 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11047 REFERENCE_PICTURE_2_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11048 }; 11049 11050 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_ENABLE 11051 { 11052 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11053 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11054 }; 11055 11056 //! \brief REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 11057 //! \details 11058 //! Distinguishes Vertical from Horizontal compression. Please refer to 11059 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11060 //! more details. Note: This bit is not used unless Memory Compression 11061 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11062 //! bit should match the settings on how this is written out before. 11063 enum REFERENCE_PICTURE_3__MEMORY_COMPRESSION_MODE 11064 { 11065 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11066 REFERENCE_PICTURE_3_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11067 }; 11068 11069 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_ENABLE 11070 { 11071 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11072 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11073 }; 11074 11075 //! \brief REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 11076 //! \details 11077 //! Distinguishes Vertical from Horizontal compression. Please refer to 11078 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11079 //! more details. Note: This bit is not used unless Memory Compression 11080 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11081 //! bit should match the settings on how this is written out before. 11082 enum REFERENCE_PICTURE_4__MEMORY_COMPRESSION_MODE 11083 { 11084 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11085 REFERENCE_PICTURE_4_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11086 }; 11087 11088 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_ENABLE 11089 { 11090 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11091 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11092 }; 11093 11094 //! \brief REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 11095 //! \details 11096 //! Distinguishes Vertical from Horizontal compression. Please refer to 11097 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11098 //! more details. Note: This bit is not used unless Memory Compression 11099 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11100 //! bit should match the settings on how this is written out before. 11101 enum REFERENCE_PICTURE_5__MEMORY_COMPRESSION_MODE 11102 { 11103 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11104 REFERENCE_PICTURE_5_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11105 }; 11106 11107 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_ENABLE 11108 { 11109 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11110 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11111 }; 11112 11113 //! \brief REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 11114 //! \details 11115 //! Distinguishes Vertical from Horizontal compression. Please refer to 11116 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11117 //! more details. Note: This bit is not used unless Memory Compression 11118 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11119 //! bit should match the settings on how this is written out before. 11120 enum REFERENCE_PICTURE_6__MEMORY_COMPRESSION_MODE 11121 { 11122 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11123 REFERENCE_PICTURE_6_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11124 }; 11125 11126 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_ENABLE 11127 { 11128 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11129 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11130 }; 11131 11132 //! \brief REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11133 //! \details 11134 //! Distinguishes Vertical from Horizontal compression. Please refer to 11135 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11136 //! more details. Note: This bit is not used unless Memory Compression 11137 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11138 //! bit should match the settings on how this is written out before. 11139 enum REFERENCE_PICTURE_7__MEMORY_COMPRESSION_MODE 11140 { 11141 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11142 REFERENCE_PICTURE_7_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11143 }; 11144 11145 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_ENABLE 11146 { 11147 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11148 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11149 }; 11150 11151 //! \brief REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11152 //! \details 11153 //! Distinguishes Vertical from Horizontal compression. Please refer to 11154 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11155 //! more details. Note: This bit is not used unless Memory Compression 11156 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11157 //! bit should match the settings on how this is written out before. 11158 enum REFERENCE_PICTURE_8__MEMORY_COMPRESSION_MODE 11159 { 11160 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11161 REFERENCE_PICTURE_8_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11162 }; 11163 11164 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_ENABLE 11165 { 11166 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11167 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11168 }; 11169 11170 //! \brief REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11171 //! \details 11172 //! Distinguishes Vertical from Horizontal compression. Please refer to 11173 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11174 //! more details. Note: This bit is not used unless Memory Compression 11175 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11176 //! bit should match the settings on how this is written out before. 11177 enum REFERENCE_PICTURE_9__MEMORY_COMPRESSION_MODE 11178 { 11179 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11180 REFERENCE_PICTURE_9_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11181 }; 11182 11183 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_ENABLE 11184 { 11185 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11186 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11187 }; 11188 11189 //! \brief REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11190 //! \details 11191 //! Distinguishes Vertical from Horizontal compression. Please refer to 11192 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11193 //! more details. Note: This bit is not used unless Memory Compression 11194 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11195 //! bit should match the settings on how this is written out before. 11196 enum REFERENCE_PICTURE_10__MEMORY_COMPRESSION_MODE 11197 { 11198 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11199 REFERENCE_PICTURE_10_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11200 }; 11201 11202 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_ENABLE 11203 { 11204 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11205 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11206 }; 11207 11208 //! \brief REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11209 //! \details 11210 //! Distinguishes Vertical from Horizontal compression. Please refer to 11211 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11212 //! more details. 11213 //! Note: This bit is not used unless Memory Compression Enable is set 11214 //! to "1" 11215 //! Note: This is a READ Surface. The setting of this bit should 11216 //! match the settings on how this is written out before. 11217 enum REFERENCE_PICTURE_11__MEMORY_COMPRESSION_MODE 11218 { 11219 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11220 REFERENCE_PICTURE_11_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11221 }; 11222 11223 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_ENABLE 11224 { 11225 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11226 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11227 }; 11228 11229 //! \brief REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11230 //! \details 11231 //! Distinguishes Vertical from Horizontal compression. Please refer to 11232 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11233 //! more details. Note: This bit is not used unless Memory Compression 11234 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11235 //! bit should match the settings on how this is written out before. 11236 enum REFERENCE_PICTURE_12__MEMORY_COMPRESSION_MODE 11237 { 11238 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11239 REFERENCE_PICTURE_12_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11240 }; 11241 11242 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_ENABLE 11243 { 11244 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11245 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11246 }; 11247 11248 //! \brief REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11249 //! \details 11250 //! Distinguishes Vertical from Horizontal compression. Please refer to 11251 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11252 //! more details. Note: This bit is not used unless Memory Compression 11253 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11254 //! bit should match the settings on how this is written out before. 11255 enum REFERENCE_PICTURE_13__MEMORY_COMPRESSION_MODE 11256 { 11257 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11258 REFERENCE_PICTURE_13_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11259 }; 11260 11261 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_ENABLE 11262 { 11263 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11264 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11265 }; 11266 11267 //! \brief REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11268 //! \details 11269 //! Distinguishes Vertical from Horizontal compression. Please refer to 11270 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11271 //! more details. Note: This bit is not used unless Memory Compression 11272 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11273 //! bit should match the settings on how this is written out before. 11274 enum REFERENCE_PICTURE_14__MEMORY_COMPRESSION_MODE 11275 { 11276 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11277 REFERENCE_PICTURE_14_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11278 }; 11279 11280 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_ENABLE 11281 { 11282 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11283 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_ENABLE_COMPRESSIONENABLE = 1, //!< No additional details 11284 }; 11285 11286 //! \brief REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11287 //! \details 11288 //! Distinguishes Vertical from Horizontal compression. Please refer to 11289 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11290 //! more details. Note: This bit is not used unless Memory Compression 11291 //! Enable is set to "1" Note: This is a READ Surface. The setting of this 11292 //! bit should match the settings on how this is written out before. 11293 enum REFERENCE_PICTURE_15__MEMORY_COMPRESSION_MODE 11294 { 11295 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11296 REFERENCE_PICTURE_15_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11297 }; 11298 11299 //! \brief SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11300 //! \details 11301 //! This field controls the priority of arbitration used in the GAC/GAM 11302 //! pipeline for this surface. 11303 enum SCALE_REFERENCE_SURFACE__ARBITRATION_PRIORITY_CONTROL 11304 { 11305 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11306 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11307 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11308 SCALE_REFERENCE_SURFACE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11309 }; 11310 11311 //! \brief SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11312 //! \details 11313 //! Distinguishes Vertical from Horizontal compression. Please refer to 11314 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11315 //! more details. 11316 enum SCALED_REFERENCE_SURFACE__MEMORY_COMPRESSION_MODE 11317 { 11318 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11319 SCALED_REFERENCE_SURFACE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11320 }; 11321 11322 //! \brief SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11323 //! \details 11324 //! For Media Surfaces: 11325 //! This field specifies the tiled resource mode 11326 enum SCALED_REFERENCE_SURFACE__TILED_RESOURCE_MODE 11327 { 11328 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11329 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< No tiled resource 11330 SCALED_REFERENCE_SURFACE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< No tiled resource 11331 }; 11332 11333 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 11334 //! \details 11335 //! This field controls the priority of arbitration used in the GAC/GAM 11336 //! pipeline for this surface. 11337 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__ARBITRATION_PRIORITY_CONTROL 11338 { 11339 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11340 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11341 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11342 SLICESIZE_STREAMOUT_DATA_DESTINATION_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11343 }; 11344 11345 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 11346 //! \details 11347 //! Distinguishes Vertical from Horizontal compression. Please refer to 11348 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11349 //! more details. 11350 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__MEMORY_COMPRESSION_MODE 11351 { 11352 SLICESIZE_STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11353 SLICESIZE_STREAMOUT_DATA_DESTINATION_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11354 }; 11355 11356 //! \brief SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 11357 //! \details 11358 //! For Media Surfaces: This Surface is never tiled. 11359 enum SLICESIZE_STREAMOUT_DATA_DESTINATION__TILED_RESOURCE_MODE 11360 { 11361 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11362 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< No tiled resource 11363 SLICESIZE_STREAMOUT_DATA_DESTINATION_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< No tiled resource 11364 }; 11365 11366 //! \name Initializations 11367 11368 //! \brief Explicit member initialization function 11369 MFX_PIPE_BUF_ADDR_STATE_CMD(); 11370 11371 static const size_t dwSize = 68; 11372 static const size_t byteSize = 272; 11373 }; 11374 11375 //! 11376 //! \brief MFX_AVC_DIRECTMODE_STATE 11377 //! \details 11378 //! This is a picture level command and is issued once per picture. All DMV 11379 //! buffers are treated as standard media surfaces, in which the lower 6 11380 //! bits are used for conveying surface states.Current Pic POC number is 11381 //! assumed to be available in POCList[32 and 33] of the 11382 //! MFX_AVC_DIRECTMODE_STATE Command.This command is only valid in the AVC 11383 //! decoding in VLD and IT modes, and AVC encoder mode. The same command 11384 //! supports both Long and Short AVC Interface. The DMV buffers are 11385 //! not required to be programmed for encoder mode. 11386 //! 11387 struct MFX_AVC_DIRECTMODE_STATE_CMD 11388 { 11389 union 11390 { 11391 //!< DWORD 0 11392 struct 11393 { 11394 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 11395 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 11396 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 11397 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 23) ; //!< SUBOPCODEA 11398 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(24, 26) ; //!< MEDIA_COMMAND_OPCODE 11399 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 11400 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 11401 }; 11402 uint32_t Value; 11403 } DW0; 11404 11405 mhw_vdbox_mfx_g10_X::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddress[16]; //!< Direct MV Buffer Base Address 11406 11407 union 11408 { 11409 //!< DWORD 33 11410 struct 11411 { 11412 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11413 uint32_t DirectMvBufferBaseAddressForReferenceFrameArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11414 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11415 uint32_t DirectMvBufferBaseAddressForReferenceFrameMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11416 uint32_t Reserved1067 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11417 uint32_t DirectMvBufferBaseAddressForReferenceFrameTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11418 uint32_t Reserved1071 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11419 }; 11420 uint32_t Value; 11421 } DW33; 11422 11423 mhw_vdbox_mfx_g10_X::GRAPHICSADDRESS63_6_CMD DirectMvBufferBaseAddressForWrite[1]; //!< Direct MV Buffer Base Address for Write 11424 11425 union 11426 { 11427 //!< DWORD 36 11428 struct 11429 { 11430 uint32_t MemoryObjectControlState : __CODEGEN_BITFIELD( 0, 6) ; //!< Memory Object Control State 11431 uint32_t DirectMvBufferBaseAddressForWriteArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11432 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11433 uint32_t DirectMvBufferBaseAddressForWriteMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11434 uint32_t Reserved1163 : __CODEGEN_BITFIELD(11, 12) ; //!< Reserved 11435 uint32_t DirectMvBufferBaseAddressForWriteTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11436 uint32_t Reserved1167 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 11437 }; 11438 uint32_t Value; 11439 } DW36; 11440 11441 uint32_t PocList[34]; //!< POC List 11442 11443 //! \name Local enumerations 11444 11445 enum SUBOPCODEB 11446 { 11447 SUBOPCODEB_UNNAMED2 = 2, //!< No additional details 11448 }; 11449 11450 enum SUBOPCODEA 11451 { 11452 SUBOPCODEA_UNNAMED0 = 0, //!< No additional details 11453 }; 11454 11455 enum MEDIA_COMMAND_OPCODE 11456 { 11457 MEDIA_COMMAND_OPCODE_AVCCOMMON = 1, //!< No additional details 11458 }; 11459 11460 enum PIPELINE 11461 { 11462 PIPELINE_MFXSINGLEDW = 2, //!< No additional details 11463 }; 11464 11465 enum COMMAND_TYPE 11466 { 11467 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 11468 }; 11469 11470 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11471 //! \details 11472 //! This field controls the priority of arbitration used in the GAC/GAM 11473 //! pipeline for this surface. 11474 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__ARBITRATION_PRIORITY_CONTROL 11475 { 11476 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11477 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11478 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11479 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11480 }; 11481 11482 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11483 //! \details 11484 //! This surface is linear surface. This bit must be set to "0" since only 11485 //! TileY/TileYf/TileYs surface is allowed to be compressed 11486 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_ENABLE 11487 { 11488 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11489 }; 11490 11491 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11492 //! \details 11493 //! Distinguishes Vertical from Horizontal compression. Please refer to 11494 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11495 //! more details. 11496 //! Note: This bit is not used unless Memory Compression Enable is set 11497 //! to "1" 11498 //! Note: This is a READ Surface. The setting of this bit should 11499 //! match the settings on how this is written out before. 11500 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__MEMORY_COMPRESSION_MODE 11501 { 11502 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11503 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11504 }; 11505 11506 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11507 //! \details 11508 //! <b>For Media Surfaces:</b> 11509 //! This field specifies the tiled resource mode. 11510 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME__TILED_RESOURCE_MODE 11511 { 11512 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11513 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11514 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_REFERENCE_FRAME_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11515 }; 11516 11517 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11518 //! \details 11519 //! This field controls the priority of arbitration used in the GAC/GAM 11520 //! pipeline for this surface. 11521 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__ARBITRATION_PRIORITY_CONTROL 11522 { 11523 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_HIGHESTPRIORITY = 0, //!< No additional details 11524 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_SECONDHIGHESTPRIORITY = 1, //!< No additional details 11525 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_THIRDHIGHESTPRIORITY = 2, //!< No additional details 11526 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_ARBITRATION_PRIORITY_CONTROL_LOWESTPRIORITY = 3, //!< No additional details 11527 }; 11528 11529 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11530 //! \details 11531 //! This surface is linear surface. This bit must be set to "0" since only 11532 //! TileY/TileYf/TileYs surface is allowed to be compressed 11533 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_ENABLE 11534 { 11535 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_ENABLE_COMPRESSIONDISABLE = 0, //!< No additional details 11536 }; 11537 11538 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11539 //! \details 11540 //! Distinguishes Vertical from Horizontal compression. Please refer to 11541 //! vol1a Memory Data Formats chapter -section Media Memory Compression for 11542 //! more details. 11543 //! Note: This bit is not used unless Memory Compression Enable is set 11544 //! to "1" 11545 //! Note: This is a READ Surface. The setting of this bit should 11546 //! match the settings on how this is written out before. 11547 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__MEMORY_COMPRESSION_MODE 11548 { 11549 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 11550 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSIONMODE = 1, //!< No additional details 11551 }; 11552 11553 //! \brief DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11554 //! \details 11555 //! <b>For Media Surfaces:</b> 11556 //! This field specifies the tiled resource mode. 11557 enum DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE__TILED_RESOURCE_MODE 11558 { 11559 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< No tiled resource 11560 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 11561 DIRECT_MV_BUFFER_BASE_ADDRESS_FOR_WRITE_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 11562 }; 11563 11564 //! \name Initializations 11565 11566 //! \brief Explicit member initialization function 11567 MFX_AVC_DIRECTMODE_STATE_CMD(); 11568 11569 static const size_t dwSize = 71; 11570 static const size_t byteSize = 284; 11571 }; 11572 11573 }; 11574 11575 #pragma pack() 11576 11577 #endif // __MHW_VDBOX_MFX_HWCMD_G10_X_H__ 11578