1 /* 2 * Copyright (c) 2018, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_vdbox_hcp_hwcmd_g11_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g11_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 29 // DO NOT EDIT 30 31 #ifndef __MHW_VDBOX_HCP_HWCMD_G11_X_H__ 32 #define __MHW_VDBOX_HCP_HWCMD_G11_X_H__ 33 34 #pragma once 35 #pragma pack(1) 36 37 #include <cstdint> 38 #include <cstddef> 39 40 class mhw_vdbox_hcp_g11_X 41 { 42 public: 43 // Internal Macros 44 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 45 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 46 #define __CODEGEN_OP_LENGTH_BIAS 2 47 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 48 GetOpLength(uint32_t uiLength)49 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 50 51 //! 52 //! \brief MEMORYADDRESSATTRIBUTES 53 //! \details 54 //! This field controls the priority of arbitration used in the GAC/GAM 55 //! pipeline for this surface. It defines the attributes for VDBOX addresses 56 //! on BDW+. 57 //! 58 struct MEMORYADDRESSATTRIBUTES_CMD 59 { 60 union 61 { 62 struct 63 { 64 uint32_t Reserved0 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 65 uint32_t BaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Base Address - Index to Memory Object Control State (MOCS) Tables 66 uint32_t BaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Base Address - Arbitration Priority Control 67 uint32_t BaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Base Address - Memory Compression Enable 68 uint32_t BaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< BASE_ADDRESS_MEMORY_COMPRESSION_MODE 69 uint32_t Reserved11 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 70 uint32_t BaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 71 uint32_t BaseAddressTiledResourceMode : __CODEGEN_BITFIELD(13, 14) ; //!< BASE_ADDRESS_TILED_RESOURCE_MODE 72 uint32_t Reserved15 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 73 }; 74 uint32_t Value; 75 } DW0; 76 77 //! \name Local enumerations 78 79 //! \brief BASE_ADDRESS_MEMORY_COMPRESSION_MODE 80 //! \details 81 //! Distinguishes vertical from horizontal compression. Please refer to 82 //! vol1a <b>Memory Data Formats chapter - section</b> media Memory 83 //! Compression for more details. 84 enum BASE_ADDRESS_MEMORY_COMPRESSION_MODE 85 { 86 BASE_ADDRESS_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 87 }; 88 89 //! \brief BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 90 //! \details 91 //! This field controls if the Row Store is going to store inside Media 92 //! Cache (rowstore cache) or to LLC. 93 enum BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 94 { 95 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED0 = 0, //!< Buffer going to LLC. 96 BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_UNNAMED1 = 1, //!< Buffer going to Internal Media Storage. 97 }; 98 99 //! \brief BASE_ADDRESS_TILED_RESOURCE_MODE 100 //! \details 101 //! <b>For Media Surfaces:</b> This field specifies the tiled resource mode. 102 enum BASE_ADDRESS_TILED_RESOURCE_MODE 103 { 104 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODENONE = 0, //!< TileY resources 105 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 106 BASE_ADDRESS_TILED_RESOURCE_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 107 }; 108 109 //! \name Initializations 110 111 //! \brief Explicit member initialization function 112 MEMORYADDRESSATTRIBUTES_CMD(); 113 114 static const size_t dwSize = 1; 115 static const size_t byteSize = 4; 116 }; 117 118 //! 119 //! \brief SPLITBASEADDRESS64BYTEALIGNED 120 //! \details 121 //! Specifies a 64-bit (48-bit canonical) 64-byte aligned memory base 122 //! address. 123 //! 124 struct SPLITBASEADDRESS64BYTEALIGNED_CMD 125 { 126 union 127 { 128 struct 129 { 130 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 131 uint64_t Graphicsaddress476 : __CODEGEN_BITFIELD( 6, 47) ; //!< GraphicsAddress47-6 132 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 133 }; 134 uint32_t Value[2]; 135 } DW0_1; 136 137 //! \name Local enumerations 138 139 //! \name Initializations 140 141 //! \brief Explicit member initialization function 142 SPLITBASEADDRESS64BYTEALIGNED_CMD(); 143 144 static const size_t dwSize = 2; 145 static const size_t byteSize = 8; 146 }; 147 148 //! 149 //! \brief SPLITBASEADDRESS4KBYTEALIGNED 150 //! \details 151 //! Specifies a 64-bit (48-bit canonical) 4K-byte aligned memory base 152 //! address. GraphicsAddress is a 64-bit value [63:0], but only a portion of 153 //! it is used by hardware. The upper reserved bits are ignored and MBZ. 154 //! 155 struct SPLITBASEADDRESS4KBYTEALIGNED_CMD 156 { 157 union 158 { 159 struct 160 { 161 uint64_t Reserved0 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 162 uint64_t Graphicsaddress4712 : __CODEGEN_BITFIELD(12, 47) ; //!< GraphicsAddress47-12 163 uint64_t Reserved48 : __CODEGEN_BITFIELD(48, 63) ; //!< Reserved 164 }; 165 uint32_t Value[2]; 166 } DW0_1; 167 168 //! \name Local enumerations 169 170 //! \name Initializations 171 172 //! \brief Explicit member initialization function 173 SPLITBASEADDRESS4KBYTEALIGNED_CMD(); 174 175 static const size_t dwSize = 2; 176 static const size_t byteSize = 8; 177 }; 178 179 //! 180 //! \brief HCP_PIPE_MODE_SELECT 181 //! \details 182 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 183 //! Commands. Each HCP command has assigned a media instruction command as 184 //! defined in DWord 0, BitField 22:16. 185 //! 186 //! The workload for the HCP is based upon a single frame decode. There are 187 //! no states saved between frame decodes in the HCP. Once the bit stream 188 //! DMA is configured with the HCP_BSD_OBJECT command, and the bit stream is 189 //! presented to the HCP, the frame decode will begin. The 190 //! HCP_PIPE_MODE_SELECT command is responsible for general pipeline level 191 //! configuration that would normally be set once for a single stream encode 192 //! or decode and would not be modified on a frame workload basis. This is a 193 //! picture level state command and is shared by both encoding and decoding 194 //! processes. 195 //! 196 struct HCP_PIPE_MODE_SELECT_CMD 197 { 198 union 199 { 200 struct 201 { 202 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 203 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 204 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 205 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 206 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 207 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 208 }; 209 uint32_t Value; 210 } DW0; 211 union 212 { 213 struct 214 { 215 uint32_t CodecSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< CODEC_SELECT 216 uint32_t DeblockerStreamoutEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< DEBLOCKER_STREAMOUT_ENABLE 217 uint32_t PakPipelineStreamoutEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< PAK_PIPELINE_STREAMOUT_ENABLE 218 uint32_t PicStatusErrorReportEnable : __CODEGEN_BITFIELD( 3, 3) ; //!< PIC_STATUSERROR_REPORT_ENABLE 219 uint32_t Reserved36 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 220 uint32_t CodecStandardSelect : __CODEGEN_BITFIELD( 5, 7) ; //!< CODEC_STANDARD_SELECT 221 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 222 uint32_t AdvancedRateControlEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Advanced Rate Control Enable 223 uint32_t VdencMode : __CODEGEN_BITFIELD(10, 10) ; //!< VDEnc_Mode 224 uint32_t RdoqEnabledFlag : __CODEGEN_BITFIELD(11, 11) ; //!< RDOQ_ENABLED_FLAG 225 uint32_t PakFrameLevelStreamoutEnable : __CODEGEN_BITFIELD(12, 12) ; //!< PAK Frame Level StreamOut enable 226 uint32_t MultiEngineMode : __CODEGEN_BITFIELD(13, 14) ; //!< MULTI_ENGINE_MODE 227 uint32_t PipeWorkingMode : __CODEGEN_BITFIELD(15, 16) ; //!< PIPE_WORKING_MODE 228 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 31) ; //!< RESERVED 229 }; 230 uint32_t Value; 231 } DW1; 232 union 233 { 234 struct 235 { 236 uint32_t MediaSoftResetCounterPer1000Clocks ; //!< MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 237 }; 238 uint32_t Value; 239 } DW2; 240 union 241 { 242 struct 243 { 244 uint32_t PicStatusErrorReportId ; //!< PIC_STATUSERROR_REPORT_ID 245 }; 246 uint32_t Value; 247 } DW3; 248 union 249 { 250 struct 251 { 252 uint32_t Reserved128 ; //!< Reserved 253 }; 254 uint32_t Value; 255 } DW4; 256 union 257 { 258 struct 259 { 260 uint32_t Reserved160 ; //!< Reserved 261 }; 262 uint32_t Value; 263 } DW5; 264 265 //! \name Local enumerations 266 267 enum MEDIA_INSTRUCTION_COMMAND 268 { 269 MEDIA_INSTRUCTION_COMMAND_HCPPIPEMODESELECT = 0, //!< No additional details 270 }; 271 272 //! \brief MEDIA_INSTRUCTION_OPCODE 273 //! \details 274 //! Codec/Engine Name = HCP = 7h 275 enum MEDIA_INSTRUCTION_OPCODE 276 { 277 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 278 }; 279 280 enum PIPELINE_TYPE 281 { 282 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 283 }; 284 285 enum COMMAND_TYPE 286 { 287 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 288 }; 289 290 enum CODEC_SELECT 291 { 292 CODEC_SELECT_DECODE = 0, //!< No additional details 293 CODEC_SELECT_ENCODE = 1, //!< No additional details 294 }; 295 296 //! \brief DEBLOCKER_STREAMOUT_ENABLE 297 //! \details 298 //! Deblocker Streamout Enable not currently supported for Encode or Decode 299 enum DEBLOCKER_STREAMOUT_ENABLE 300 { 301 DEBLOCKER_STREAMOUT_ENABLE_DISABLE = 0, //!< Disable deblocker-only parameter streamout 302 DEBLOCKER_STREAMOUT_ENABLE_ENABLE = 1, //!< Enable deblocker-only parameter streamout 303 }; 304 305 //! \brief PAK_PIPELINE_STREAMOUT_ENABLE 306 //! \details 307 //! Pipeline Streamout Enable is only defined for encode. It is ignored for 308 //! decode. 309 enum PAK_PIPELINE_STREAMOUT_ENABLE 310 { 311 PAK_PIPELINE_STREAMOUT_ENABLE_DISABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 0, //!< No additional details 312 PAK_PIPELINE_STREAMOUT_ENABLE_ENABLEPIPELINESTATESANDPARAMETERSSTREAMOUT = 1, //!< No additional details 313 }; 314 315 enum PIC_STATUSERROR_REPORT_ENABLE 316 { 317 PIC_STATUSERROR_REPORT_ENABLE_DISABLE = 0, //!< Disable status/error reporting 318 PIC_STATUSERROR_REPORT_ENABLE_ENABLE = 1, //!< Status/Error reporting is written out once per picture. The Pic Status/Error Report ID in DWord3along with the status/error status bits are packed into one cache line and written to theStatus/Error Buffer address in the HCP_PIPE_BUF_ADDR_STATE command. Must be zero for encoder mode. 319 }; 320 321 enum CODEC_STANDARD_SELECT 322 { 323 CODEC_STANDARD_SELECT_HEVC = 0, //!< No additional details 324 CODEC_STANDARD_SELECT_VP9 = 1, //!< No additional details 325 }; 326 327 enum RDOQ_ENABLED_FLAG 328 { 329 RDOQ_ENABLED_FLAG_DISABLED = 0, //!< No additional details 330 RDOQ_ENABLED_FLAG_ENABLED = 1, //!< No additional details 331 }; 332 333 //! \brief MULTI_ENGINE_MODE 334 //! \details 335 //! <p>This indicates the current pipe is in single pipe mode or if in 336 //! scalable mode is in left/right/middle pipe in multi-engine mode.</p> 337 enum MULTI_ENGINE_MODE 338 { 339 MULTI_ENGINE_MODE_SINGLEENGINEMODEORCABACFEONLYDECODEMODE = 0, //!< This is for single engine mode (legacy) OR CABAC FE only decode mode 340 MULTI_ENGINE_MODE_PIPEISTHELEFTENGINEINAMULTI_ENGINEMODE = 1, //!< Current pipe is the most left engine while running in scalable multi-engine mode 341 MULTI_ENGINE_MODE_PIPEISTHERIGHTENGINEINAMULTI_ENGINEMODE = 2, //!< Current pipe is the most right engine while running in scalable multi-engine mode 342 MULTI_ENGINE_MODE_PIPEISONEOFTHEMIDDLEENGINEINAMULTI_ENGINEMODE = 3, //!< Current pipe is in one of the middle engine while running in scalable multi-engine mode 343 }; 344 345 //! \brief PIPE_WORKING_MODE 346 //! \details 347 //! <p>This programs the working mode for HCP pipe.</p> 348 enum PIPE_WORKING_MODE 349 { 350 PIPE_WORKING_MODE_LEGACYDECODERENCODERMODE_SINGLEPIPE = 0, //!< This is for single pipe mode non-scalable mode. It is used by both decoder and encoder. 351 PIPE_WORKING_MODE_CABACFEONLYDECODEMODE_SINGLECABACPIPE = 1, //!< This is for the single CABAC FE only in decoder mode. This will be only run CABAC and streamout syntax element. 352 PIPE_WORKING_MODE_DECODERBEONLYORENCODERMODE_SCALABLEMULTI_PIPE = 2, //!< This is for multiple-pipe scalable mode. In decoder, it is only on BE reconstruction. In ecoder, it is for PAK. 353 }; 354 355 //! \brief MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 356 //! \details 357 //! In decoder modes, this counter value specifies the number of clocks (per 358 //! 1000) of GAC inactivity 359 //! before a media soft-reset is applied to the HCP and HuC. If counter 360 //! value is set to 0, the media 361 //! soft-reset feature is disabled and no reset will occur. 362 //! <p>In encoder modes, this counter must be set to 0 to disable media 363 //! soft reset. This feature is not 364 //! supported for the encoder.</p> 365 enum MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS 366 { 367 MEDIA_SOFT_RESET_COUNTER_PER_1000_CLOCKS_DISABLE = 0, //!< No additional details 368 }; 369 370 //! \brief PIC_STATUSERROR_REPORT_ID 371 //! \details 372 //! The Pic Status/Error Report ID is a unique 32-bit unsigned integer 373 //! assigned to each picture 374 //! status/error output. Must be zero for encoder mode. 375 enum PIC_STATUSERROR_REPORT_ID 376 { 377 PIC_STATUSERROR_REPORT_ID_32_BITUNSIGNED = 0, //!< Unique ID Number 378 }; 379 380 //! \name Initializations 381 382 //! \brief Explicit member initialization function 383 HCP_PIPE_MODE_SELECT_CMD(); 384 385 static const size_t dwSize = 6; 386 static const size_t byteSize = 24; 387 }; 388 389 //! 390 //! \brief HCP_SURFACE_STATE 391 //! \details 392 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 393 //! Commands. Each HCP command has assigned a media instruction command as 394 //! defined in DWord 0, BitField 22:16. 395 //! 396 //! The HCP_SURFACE_STATE command is responsible for defining the frame 397 //! buffer pitch and the offset of the chroma component. This is a picture 398 //! level state command and is shared by both encoding and decoding 399 //! processes. Note : Only NV12 and Tile Y are being supported for HEVC. 400 //! Hence full pitch and interleaved UV is always in use. U and V Xoffset 401 //! must be set to 0; U and V Yoffset must be 16-pixel aligned. This Surface 402 //! State is not the same as that of the 3D engine and of the MFX pipeline. 403 //! 404 struct HCP_SURFACE_STATE_CMD 405 { 406 union 407 { 408 struct 409 { 410 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 411 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 412 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 413 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 414 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 415 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 416 }; 417 uint32_t Value; 418 } DW0; 419 union 420 { 421 struct 422 { 423 uint32_t SurfacePitchMinus1 : __CODEGEN_BITFIELD( 0, 16) ; //!< Surface Pitch Minus1 424 uint32_t Reserved49 : __CODEGEN_BITFIELD(17, 27) ; //!< Reserved 425 uint32_t SurfaceId : __CODEGEN_BITFIELD(28, 31) ; //!< SURFACE_ID 426 }; 427 uint32_t Value; 428 } DW1; 429 union 430 { 431 struct 432 { 433 uint32_t YOffsetForUCbInPixel : __CODEGEN_BITFIELD( 0, 14) ; //!< Y Offset for U(Cb) in pixel 434 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 26) ; //!< Reserved 435 uint32_t SurfaceFormat : __CODEGEN_BITFIELD(27, 31) ; //!< SURFACE_FORMAT 436 }; 437 uint32_t Value; 438 } DW2; 439 union 440 { 441 struct 442 { 443 uint32_t DefaultAlphaValue : __CODEGEN_BITFIELD( 0, 15) ; //!< Default Alpha Value 444 uint32_t YOffsetForVCr : __CODEGEN_BITFIELD(16, 31) ; //!< Y Offset for V(Cr) 445 }; 446 uint32_t Value; 447 } DW3; 448 449 //! \name Local enumerations 450 451 enum MEDIA_INSTRUCTION_COMMAND 452 { 453 MEDIA_INSTRUCTION_COMMAND_HCPSURFACESTATE = 1, //!< No additional details 454 }; 455 456 //! \brief MEDIA_INSTRUCTION_OPCODE 457 //! \details 458 //! Codec/Engine Name = HCP = 7h 459 enum MEDIA_INSTRUCTION_OPCODE 460 { 461 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 462 }; 463 464 enum PIPELINE_TYPE 465 { 466 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 467 }; 468 469 enum COMMAND_TYPE 470 { 471 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 472 }; 473 474 enum SURFACE_ID 475 { 476 SURFACE_ID_HEVCFORCURRENTDECODEDPICTURE = 0, //!< 8-bit uncompressed data 477 SURFACE_ID_SOURCEINPUTPICTURE_ENCODER = 1, //!< 8-bit uncompressed data 478 SURFACE_ID_PREVREFERENCEPICTURE = 2, //!< (VP9 only) Previous Reference 479 SURFACE_ID_GOLDENREFERENCEPICTURE = 3, //!< (VP9 only) Golden Reference 480 SURFACE_ID_ALTREFREFERENCEPICTURE = 4, //!< (VP9 only) AltRef Reference 481 }; 482 483 //! \brief SURFACE_FORMAT 484 //! \details 485 //! <p>Specifies the format of the surface.</p> 486 enum SURFACE_FORMAT 487 { 488 SURFACE_FORMAT_YUY2FORMAT = 0, //!< No additional details 489 SURFACE_FORMAT_RGB8FORMAT = 1, //!< No additional details 490 SURFACE_FORMAT_AYUV4444FORMAT = 2, //!< No additional details 491 SURFACE_FORMAT_P010VARIANT = 3, //!< No additional details 492 SURFACE_FORMAT_PLANAR4208 = 4, //!< No additional details 493 SURFACE_FORMAT_YCRCBSWAPYFORMAT = 5, //!< No additional details 494 SURFACE_FORMAT_YCRCBSWAPUVFORMAT = 6, //!< No additional details 495 SURFACE_FORMAT_YCRCBSWAPUVYFORMAT = 7, //!< No additional details 496 SURFACE_FORMAT_Y216Y210FORMAT = 8, //!< Same value is used to represent Y216 and Y210 497 SURFACE_FORMAT_RGB10FORMAT = 9, //!< No additional details 498 SURFACE_FORMAT_Y410FORMAT = 10, //!< No additional details 499 SURFACE_FORMAT_NV21PLANAR4208FORMAT = 11, //!< No additional details 500 SURFACE_FORMAT_Y416FORMAT = 12, //!< No additional details 501 SURFACE_FORMAT_P010 = 13, //!< No additional details 502 SURFACE_FORMAT_Y8FORMAT = 15, //!< No additional details 503 SURFACE_FORMAT_Y16FORMAT = 16, //!< No additional details 504 SURFACE_FORMAT_Y216VARIANT = 17, //!< Y216Variant is the modifed Y210/Y216 format, 8 bit planar 422 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The chroma is UV interleaved with identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 505 SURFACE_FORMAT_Y416VARIANT = 18, //!< Y416Variant is the modifed Y410/Y412/Y416 format,8 bit planar 444 with MSB bytes packed together and LSB bytes at an offset in the X-direction where the x-offset is 32-bit aligned. The U channel is below the luma, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma The V channel is below the U, has identical MSB and LSB split as luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 506 SURFACE_FORMAT_YUY2VARIANT = 19, //!< YUY2Variant is the modifed YUY2 format, 8 bit planar 422. The chroma is UV interleaved and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 507 SURFACE_FORMAT_AYUV4444VARIANT = 20, //!< AYUV4444Variant is the modifed AYUV4444 format, 8 bit planar 444 format. The U channel is below the luma and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. The V channel is below the and is at an offset in the Y-direction (similar to NV12) but is the same height as the luma. 508 }; 509 510 //! \name Initializations 511 512 //! \brief Explicit member initialization function 513 HCP_SURFACE_STATE_CMD(); 514 515 static const size_t dwSize = 4; 516 static const size_t byteSize = 16; 517 }; 518 519 //! 520 //! \brief HCP_PIPE_BUF_ADDR_STATE 521 //! \details 522 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 523 //! Commands. Each HCP command has assigned a media instruction command as 524 //! defined in DWord 0, BitField 22:16. 525 //! 526 //! This state command provides the memory base addresses for the row store 527 //! buffer and reconstructed picture output buffers required by the HCP. 528 //! This is a picture level state command and is shared by both encoding and 529 //! decoding processes. 530 //! 531 //! All pixel surface addresses must be 4K byte aligned. There is a max of 8 532 //! Reference Picture Buffer Addresses, and all share the same third address 533 //! DW in specifying 48-bit address. 534 //! 535 struct HCP_PIPE_BUF_ADDR_STATE_CMD 536 { 537 union 538 { 539 struct 540 { 541 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 542 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 543 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 544 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 545 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 546 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 547 }; 548 uint32_t Value; 549 } DW0; 550 SPLITBASEADDRESS4KBYTEALIGNED_CMD DecodedPicture; //!< DW1..2, Decoded Picture 551 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureMemoryAddressAttributes; //!< DW3, Decoded Picture Memory Address Attributes 552 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterLineBuffer; //!< DW4..5, Deblocking Filter Line Buffer 553 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterLineBufferMemoryAddressAttributes; //!< DW6, Deblocking Filter Line Buffer Memory Address Attributes 554 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileLineBuffer; //!< DW7..8, Deblocking Filter Tile Line Buffer 555 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileLineBufferMemoryAddressAttributes; //!< DW9, Deblocking Filter Tile Line Buffer Memory Address Attributes 556 SPLITBASEADDRESS64BYTEALIGNED_CMD DeblockingFilterTileColumnBuffer; //!< DW10..11, Deblocking Filter Tile Column Buffer 557 MEMORYADDRESSATTRIBUTES_CMD DeblockingFilterTileColumnBufferMemoryAddressAttributes; //!< DW12, Deblocking Filter Tile Column Buffer Memory Address Attributes 558 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataLineBuffer; //!< DW13..14, Metadata Line Buffer 559 MEMORYADDRESSATTRIBUTES_CMD MetadataLineBufferMemoryAddressAttributes; //!< DW15, Metadata Line Buffer Memory Address Attributes 560 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileLineBuffer; //!< DW16..17, Metadata Tile Line Buffer 561 MEMORYADDRESSATTRIBUTES_CMD MetadataTileLineBufferMemoryAddressAttributes; //!< DW18, Metadata Tile Line Buffer Memory Address Attributes 562 SPLITBASEADDRESS64BYTEALIGNED_CMD MetadataTileColumnBuffer; //!< DW19..20, Metadata Tile Column Buffer 563 MEMORYADDRESSATTRIBUTES_CMD MetadataTileColumnBufferMemoryAddressAttributes; //!< DW21, Metadata Tile Column Buffer Memory Address Attributes 564 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoLineBuffer; //!< DW22..23, SAO Line Buffer 565 MEMORYADDRESSATTRIBUTES_CMD SaoLineBufferMemoryAddressAttributes; //!< DW24, SAO Line Buffer Memory Address Attributes 566 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileLineBuffer; //!< DW25..26, SAO Tile Line Buffer 567 MEMORYADDRESSATTRIBUTES_CMD SaoTileLineBufferMemoryAddressAttributes; //!< DW27, SAO Tile Line Buffer Memory Address Attributes 568 SPLITBASEADDRESS64BYTEALIGNED_CMD SaoTileColumnBuffer; //!< DW28..29, SAO Tile Column Buffer 569 MEMORYADDRESSATTRIBUTES_CMD SaoTileColumnBufferMemoryAddressAttributes; //!< DW30, SAO Tile Column Buffer Memory Address Attributes 570 SPLITBASEADDRESS64BYTEALIGNED_CMD CurrentMotionVectorTemporalBuffer; //!< DW31..32, Current Motion Vector Temporal Buffer 571 MEMORYADDRESSATTRIBUTES_CMD CurrentMotionVectorTemporalBufferMemoryAddressAttributes; //!< DW33, Current Motion Vector Temporal Buffer Memory Address Attributes 572 union 573 { 574 struct 575 { 576 uint64_t Reserved1088 ; //!< Reserved 577 }; 578 uint32_t Value[2]; 579 } DW34_35; 580 union 581 { 582 struct 583 { 584 uint32_t Reserved1152 ; //!< Reserved 585 }; 586 uint32_t Value; 587 } DW36; 588 SPLITBASEADDRESS64BYTEALIGNED_CMD ReferencePictureBaseAddressRefaddr07[8]; //!< DW37..52, Reference Picture Base Address (RefAddr[0-7]) 589 MEMORYADDRESSATTRIBUTES_CMD ReferencePictureBaseAddressMemoryAddressAttributes; //!< DW53, Reference Picture Base Address Memory Address Attributes 590 SPLITBASEADDRESS64BYTEALIGNED_CMD OriginalUncompressedPictureSource; //!< DW54..55, Original Uncompressed Picture Source 591 MEMORYADDRESSATTRIBUTES_CMD OriginalUncompressedPictureSourceMemoryAddressAttributes; //!< DW56, Original Uncompressed Picture Source Memory Address Attributes 592 SPLITBASEADDRESS64BYTEALIGNED_CMD StreamoutDataDestination; //!< DW57..58, Streamout Data Destination 593 MEMORYADDRESSATTRIBUTES_CMD StreamoutDataDestinationMemoryAddressAttributes; //!< DW59, Streamout Data Destination Memory Address Attributes, Decoder Only 594 SPLITBASEADDRESS64BYTEALIGNED_CMD DecodedPictureStatusErrorBufferBaseAddressOrEncodedSliceSizeStreamoutBaseAddress;//!< DW60..61, Decoded Picture Status/Error Buffer Base Address or Encoded slice size streamout Base Address 595 MEMORYADDRESSATTRIBUTES_CMD DecodedPictureStatusErrorBufferBaseAddressMemoryAddressAttributes; //!< DW62, Decoded Picture Status/Error Buffer Base Address Memory Address Attributes 596 SPLITBASEADDRESS64BYTEALIGNED_CMD LcuIldbStreamoutBuffer; //!< DW63..64, LCU ILDB Streamout Buffer 597 MEMORYADDRESSATTRIBUTES_CMD LcuIldbStreamoutBufferMemoryAddressAttributes; //!< DW65, LCU ILDB Streamout Buffer Memory Address Attributes 598 SPLITBASEADDRESS64BYTEALIGNED_CMD CollocatedMotionVectorTemporalBuffer07[8]; //!< DW66..81, Collocated Motion Vector Temporal Buffer[0-7] 599 MEMORYADDRESSATTRIBUTES_CMD CollocatedMotionVectorTemporalBuffer07MemoryAddressAttributes; //!< DW82, Collocated Motion Vector Temporal Buffer[0-7] Memory Address Attributes 600 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9ProbabilityBufferReadWrite; //!< DW83..84, VP9 Probability Buffer Read/Write 601 MEMORYADDRESSATTRIBUTES_CMD Vp9ProbabilityBufferReadWriteMemoryAddressAttributes; //!< DW85, VP9 Probability Buffer Read/Write Memory Address Attributes 602 union 603 { 604 struct 605 { 606 uint64_t Vp9SegmentIdBufferReadWrite ; //!< VP9 Segment ID Buffer Read/Write 607 }; 608 uint32_t Value[2]; 609 } DW86_87; 610 MEMORYADDRESSATTRIBUTES_CMD Vp9SegmentIdBufferReadWriteMemoryAddressAttributes; //!< DW88, VP9 Segment ID buffer Read/Write Memory Address Attributes 611 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdLineRowstoreBufferReadWrite; //!< DW89..90, VP9 HVD Line Rowstore Buffer Read/Write 612 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdLineRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW91, VP9 HVD Line Rowstore buffer Read/Write Memory Address Attributes 613 SPLITBASEADDRESS64BYTEALIGNED_CMD Vp9HvdTileRowstoreBufferReadWrite; //!< DW92..93, VP9 HVD Tile Rowstore Buffer Read/Write 614 MEMORYADDRESSATTRIBUTES_CMD Vp9HvdTileRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW94, VP9 HVD Tile Rowstore buffer Read/Write Memory Address Attributes 615 union 616 { 617 struct 618 { 619 uint64_t SaoRowstoreBufferBaseAddress ; //!< SAO Rowstore Buffer Base Address 620 }; 621 uint32_t Value[2]; 622 } DW95_96; 623 MEMORYADDRESSATTRIBUTES_CMD SaoRowstoreBufferReadWriteMemoryAddressAttributes; //!< DW97, SAO Rowstore Buffer Read/Write Memory Address Attributes 624 SPLITBASEADDRESS64BYTEALIGNED_CMD FrameStatisticsStreamoutDataDestinationBufferBaseAddress; //!< DW98..99, Frame Statistics Streamout Data Destination Buffer Base Address 625 MEMORYADDRESSATTRIBUTES_CMD FrameStatisticsStreamoutDataDestinationBufferAttributesReadWrite; //!< DW100, Frame Statistics Streamout Data Destination buffer (attributes) Read/Write 626 SPLITBASEADDRESS64BYTEALIGNED_CMD SseSourcePixelRowstoreBufferBaseAddress; //!< DW101..102, SSE Source Pixel RowStore Buffer Base Address 627 MEMORYADDRESSATTRIBUTES_CMD SseSourcePixelRowstoreBufferAttributesReadWrite; //!< DW103, SSE Source Pixel RowStore buffer (attributes) Read/Write 628 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySliceStateBufferBaseAddress; //!< DW104..105, HCP Scalability Slice State Buffer Base Address 629 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySliceStateBufferAttributesReadWrite; //!< DW106, HCP Scalability Slice State Buffer (attributes) Read/Write 630 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferBaseAddress; //!< DW107..108, HCP Scalability CABAC Decoded Syntax Elements Buffer Base Address 631 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferAttributesReadWrite; //!< DW109, HCP Scalability CABAC Decoded Syntax Elements Buffer (attributes) Read/Write 632 SPLITBASEADDRESS64BYTEALIGNED_CMD MotionVectorUpperRightColumnStoreBufferBaseAddress; //!< DW110..111, Motion Vector Upper Right Column Store Buffer Base Address 633 MEMORYADDRESSATTRIBUTES_CMD MotionVectorUpperRightColumnStoreBufferAttributesReadWrite; //!< DW112, Motion Vector Upper Right Column Store Buffer (attributes) Read/Write 634 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionUpperRightColumnStoreBufferBaseAddress; //!< DW113..114, Intra Prediction Upper Right Column Store Buffer Base Address 635 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionUpperRightColumnStoreBufferAttributesReadWrite; //!< DW115, Intra Prediction Upper Right Column Store Buffer (attributes) Read/Write 636 SPLITBASEADDRESS64BYTEALIGNED_CMD IntraPredictionLeftReconColumnStoreBufferBaseAddress; //!< DW116..117, Intra Prediction Left Recon Column Store Buffer Base Address 637 MEMORYADDRESSATTRIBUTES_CMD IntraPredictionLeftReconColumnStoreBufferAttributesReadWrite; //!< DW118, Intra Prediction Left Recon Column Store Buffer (attributes) Read/Write 638 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilityCabacDecodedSyntaxElementsBufferMaxAddress; //!< DW119..120, HCP Scalability CABAC Decoded Syntax Elements Buffer Max Address 639 640 //! \name Local enumerations 641 642 enum MEDIA_INSTRUCTION_COMMAND 643 { 644 MEDIA_INSTRUCTION_COMMAND_HCPPIPEBUFADDRSTATE = 2, //!< No additional details 645 }; 646 647 //! \brief MEDIA_INSTRUCTION_OPCODE 648 //! \details 649 //! Codec/Engine Name = HCP = 7h 650 enum MEDIA_INSTRUCTION_OPCODE 651 { 652 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 653 }; 654 655 enum PIPELINE_TYPE 656 { 657 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 658 }; 659 660 enum COMMAND_TYPE 661 { 662 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 663 }; 664 665 //! \name Initializations 666 667 //! \brief Explicit member initialization function 668 HCP_PIPE_BUF_ADDR_STATE_CMD(); 669 670 static const size_t dwSize = 121; 671 static const size_t byteSize = 484; 672 }; 673 674 //! 675 //! \brief HCP_IND_OBJ_BASE_ADDR_STATE 676 //! \details 677 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 678 //! Commands. Each HCP command has assigned a media instruction command as 679 //! defined in DWord 0, BitField 22:16. 680 //! 681 //! The HCP_IND_OBJ_BASE_ADDR_STATE command is used to define the indirect 682 //! object base address of the stream in graphics memory. This is a frame 683 //! level command. (Is it frame or picture level?) 684 //! This is a picture level state command and is issued in both encoding and 685 //! decoding processes. 686 //! 687 //! Compressed Header Format 688 //! 689 //! 690 //! 691 struct HCP_IND_OBJ_BASE_ADDR_STATE_CMD 692 { 693 union 694 { 695 struct 696 { 697 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 698 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 699 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 700 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 701 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 702 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 703 }; 704 uint32_t Value; 705 } DW0; 706 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectBaseAddress; //!< DW1..2, HCP Indirect Bitstream Object Base Address 707 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectBitstreamObjectMemoryAddressAttributes; //!< DW3, HCP Indirect Bitstream Object Memory Address Attributes 708 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpIndirectBitstreamObjectAccessUpperBound; //!< DW4..5, HCP Indirect Bitstream Object Access Upper Bound 709 union 710 { 711 struct 712 { 713 uint64_t HcpIndirectCuObjectBaseAddress ; //!< HCP Indirect CU Object Base Address 714 }; 715 uint32_t Value[2]; 716 } DW6_7; 717 MEMORYADDRESSATTRIBUTES_CMD HcpIndirectCuObjectObjectMemoryAddressAttributes; //!< DW8, HCP Indirect CU Object Object Memory Address Attributes 718 union 719 { 720 struct 721 { 722 uint64_t HcpPakBseObjectBaseAddress ; //!< HCP PAK-BSE Object Base Address 723 }; 724 uint32_t Value[2]; 725 } DW9_10; 726 MEMORYADDRESSATTRIBUTES_CMD HcpPakBseObjectAddressMemoryAddressAttributes; //!< DW11, HCP PAK-BSE Object Address Memory Address Attributes 727 SPLITBASEADDRESS4KBYTEALIGNED_CMD HcpPakBseObjectAccessUpperBound; //!< DW12..13, HCP PAK-BSE Object Access Upper Bound 728 union 729 { 730 struct 731 { 732 uint64_t HcpVp9PakCompressedHeaderSyntaxStreaminBaseAddress ; //!< HCP VP9 PAK Compressed Header Syntax Streamin- Base Address 733 }; 734 uint32_t Value[2]; 735 } DW14_15; 736 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCompressedHeaderSyntaxStreaminMemoryAddressAttributes; //!< DW16, HCP VP9 PAK Compressed Header Syntax StreamIn Memory Address Attributes 737 union 738 { 739 struct 740 { 741 uint64_t HcpVp9PakProbabilityCounterStreamoutBaseAddress ; //!< HCP VP9 PAK Probability Counter StreamOut- Base Address 742 }; 743 uint32_t Value[2]; 744 } DW17_18; 745 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityCounterStreamoutMemoryAddressAttributes; //!< DW19, HCP VP9 PAK Probability Counter StreamOut Memory Address Attributes 746 union 747 { 748 struct 749 { 750 uint64_t HcpVp9PakProbabilityDeltasStreaminBaseAddress ; //!< HCP VP9 PAK Probability Deltas StreamIn- Base Address 751 }; 752 uint32_t Value[2]; 753 } DW20_21; 754 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakProbabilityDeltasStreaminMemoryAddressAttributes; //!< DW22, HCP VP9 PAK Probability Deltas StreamIn Memory Address Attributes 755 union 756 { 757 struct 758 { 759 uint64_t HcpVp9PakTileRecordStreamoutBaseAddress ; //!< HCP VP9 PAK Tile Record StreamOut- Base Address 760 }; 761 uint32_t Value[2]; 762 } DW23_24; 763 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakTileRecordStreamoutMemoryAddressAttributes; //!< DW25, HCP VP9 PAK Tile Record StreamOut Memory Address Attributes 764 union 765 { 766 struct 767 { 768 uint64_t HcpVp9PakCuLevelStatisticStreamoutBaseAddress ; //!< HCP VP9 PAK CU Level Statistic StreamOut- Base Address 769 }; 770 uint32_t Value[2]; 771 } DW26_27; 772 MEMORYADDRESSATTRIBUTES_CMD HcpVp9PakCuLevelStatisticStreamoutMemoryAddressAttributes; //!< DW28, HCP VP9 PAK CU Level Statistic StreamOut Memory Address Attributes 773 774 //! \name Local enumerations 775 776 enum MEDIA_INSTRUCTION_COMMAND 777 { 778 MEDIA_INSTRUCTION_COMMAND_HCPINDOBJBASEADDRSTATE = 3, //!< No additional details 779 }; 780 781 //! \brief MEDIA_INSTRUCTION_OPCODE 782 //! \details 783 //! Codec/Engine Name = HCP = 7h 784 enum MEDIA_INSTRUCTION_OPCODE 785 { 786 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 787 }; 788 789 enum PIPELINE_TYPE 790 { 791 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 792 }; 793 794 enum COMMAND_TYPE 795 { 796 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 797 }; 798 799 //! \name Initializations 800 801 //! \brief Explicit member initialization function 802 HCP_IND_OBJ_BASE_ADDR_STATE_CMD(); 803 804 static const size_t dwSize = 29; 805 static const size_t byteSize = 116; 806 }; 807 808 //! 809 //! \brief HCP_QM_STATE 810 //! \details 811 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 812 //! Commands. Each HCP command has assigned a media instruction command as 813 //! defined in DWord 0, BitField 22:16. 814 //! 815 //! The HCP_QM_STATE command loads the custom HEVC quantization tables into 816 //! local RAM and may be issued up to 20 times: 3x Colour Component plus 2x 817 //! intra/inter plus 4x SizeID minus 4 for the 32x32 chroma components. When 818 //! the scaling_list_enable_flag is set to disable, the scaling matrix is 819 //! still sent to the decoder, and with all entries programmed to the same 820 //! value = 16. This is a picture level state command and is issued in both 821 //! encoding and decoding processes. 822 //! 823 //! Dwords 2-17 form a table for the DCT coefficients, 4 8-bit 824 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-5. 825 //! Size 8x8 for SizeID1/2/3, DWords 2-17. 826 //! 827 //! 828 //! SizeID 0 (Table 4-10) 829 //! 830 struct HCP_QM_STATE_CMD 831 { 832 union 833 { 834 struct 835 { 836 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 837 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 838 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 839 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 840 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 841 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 842 }; 843 uint32_t Value; 844 } DW0; 845 union 846 { 847 struct 848 { 849 uint32_t PredictionType : __CODEGEN_BITFIELD( 0, 0) ; //!< PREDICTION_TYPE 850 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 851 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 852 uint32_t DcCoefficient : __CODEGEN_BITFIELD( 5, 12) ; //!< DC Coefficient 853 uint32_t Reserved45 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 854 }; 855 uint32_t Value; 856 } DW1; 857 uint32_t Quantizermatrix[16]; //!< QuantizerMatrix 858 859 //! \name Local enumerations 860 861 enum MEDIA_INSTRUCTION_COMMAND 862 { 863 MEDIA_INSTRUCTION_COMMAND_HCPQMSTATE = 4, //!< No additional details 864 }; 865 866 //! \brief MEDIA_INSTRUCTION_OPCODE 867 //! \details 868 //! Codec/Engine Name = HCP = 7h 869 enum MEDIA_INSTRUCTION_OPCODE 870 { 871 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 872 }; 873 874 enum PIPELINE_TYPE 875 { 876 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 877 }; 878 879 enum COMMAND_TYPE 880 { 881 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 882 }; 883 884 enum PREDICTION_TYPE 885 { 886 PREDICTION_TYPE_INTRA = 0, //!< No additional details 887 PREDICTION_TYPE_INTER = 1, //!< No additional details 888 }; 889 890 enum SIZEID 891 { 892 SIZEID_4X4 = 0, //!< No additional details 893 SIZEID_8X8 = 1, //!< No additional details 894 SIZEID_16X16 = 2, //!< No additional details 895 SIZEID_32X32 = 3, //!< (Illegal Value for Colour Component Chroma Cr and Cb.) 896 }; 897 898 //! \brief COLOR_COMPONENT 899 //! \details 900 //! Encoder: When RDOQ is enabled, scaling list for all 3 color components 901 //! must be same. So this field is set to always 0. 902 enum COLOR_COMPONENT 903 { 904 COLOR_COMPONENT_LUMA = 0, //!< No additional details 905 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 906 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 907 }; 908 909 //! \name Initializations 910 911 //! \brief Explicit member initialization function 912 HCP_QM_STATE_CMD(); 913 914 static const size_t dwSize = 18; 915 static const size_t byteSize = 72; 916 }; 917 918 //! 919 //! \brief HCP_PIC_STATE 920 //! \details 921 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 922 //! Commands. Each HCP command has assigned a media instruction command as 923 //! defined in DWord 0, BitField 22:16. 924 //! 925 //! This is a picture level command and is issued only once per workload for 926 //! both encoding and decoding processes. 927 //! 928 struct HCP_PIC_STATE_CMD 929 { 930 union 931 { 932 struct 933 { 934 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 935 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 936 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 937 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 938 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 939 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 940 }; 941 uint32_t Value; 942 } DW0; 943 union 944 { 945 struct 946 { 947 uint32_t Framewidthinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< FrameWidthInMinCbMinus1 948 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 14) ; //!< Reserved 949 uint32_t PakTransformSkipEnable : __CODEGEN_BITFIELD(15, 15) ; //!< PAK Transform Skip Enable 950 uint32_t Frameheightinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< FrameHeightInMinCbMinus1 951 uint32_t Reserved59 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 952 }; 953 uint32_t Value; 954 } DW1; 955 union 956 { 957 struct 958 { 959 uint32_t Mincusize : __CODEGEN_BITFIELD( 0, 1) ; //!< MINCUSIZE 960 uint32_t CtbsizeLcusize : __CODEGEN_BITFIELD( 2, 3) ; //!< CTBSIZE_LCUSIZE 961 uint32_t Mintusize : __CODEGEN_BITFIELD( 4, 5) ; //!< MINTUSIZE 962 uint32_t Maxtusize : __CODEGEN_BITFIELD( 6, 7) ; //!< MAXTUSIZE 963 uint32_t Minpcmsize : __CODEGEN_BITFIELD( 8, 9) ; //!< MINPCMSIZE 964 uint32_t Maxpcmsize : __CODEGEN_BITFIELD(10, 11) ; //!< MAXPCMSIZE 965 uint32_t Log2SaoOffsetScaleLuma : __CODEGEN_BITFIELD(12, 14) ; //!< LOG2_SAO_OFFSET_SCALE_LUMA 966 uint32_t Reserved79 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 967 uint32_t Log2SaoOffsetScaleChroma : __CODEGEN_BITFIELD(16, 18) ; //!< LOG2_SAO_OFFSET_SCALE_CHROMA 968 uint32_t Reserved83 : __CODEGEN_BITFIELD(19, 19) ; //!< Reserved 969 uint32_t ChromaQpOffsetListLenMinus1 : __CODEGEN_BITFIELD(20, 22) ; //!< chroma_qp_offset_list_len_minus1 970 uint32_t Reserved87 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 971 uint32_t DiffCuChromaQpOffsetDepth : __CODEGEN_BITFIELD(24, 27) ; //!< diff_cu_chroma_qp_offset_depth 972 uint32_t ChromaQpOffsetListEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< chroma_qp_offset_list_enabled_flag 973 uint32_t ChromaSubsampling : __CODEGEN_BITFIELD(29, 31) ; //!< CHROMA_SUBSAMPLING 974 }; 975 uint32_t Value; 976 } DW2; 977 union 978 { 979 struct 980 { 981 uint32_t Colpicisi : __CODEGEN_BITFIELD( 0, 0) ; //!< COLPICISI 982 uint32_t Curpicisi : __CODEGEN_BITFIELD( 1, 1) ; //!< CURPICISI 983 uint32_t Inserttestflag : __CODEGEN_BITFIELD( 2, 2) ; //!< INSERTTESTFLAG 984 uint32_t Reserved99 : __CODEGEN_BITFIELD( 3, 18) ; //!< Reserved 985 uint32_t HighPrecisionOffsetsEnableFlag : __CODEGEN_BITFIELD(19, 19) ; //!< High Precision Offsets Enable Flag 986 uint32_t Log2Maxtransformskipsize : __CODEGEN_BITFIELD(20, 22) ; //!< Log2MaxTransformSkipSize 987 uint32_t CrossComponentPredictionEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cross_component_prediction_enabled_flag 988 uint32_t CabacBypassAlignmentEnabledFlag : __CODEGEN_BITFIELD(24, 24) ; //!< cabac_bypass_alignment_enabled_flag 989 uint32_t PersistentRiceAdaptationEnabledFlag : __CODEGEN_BITFIELD(25, 25) ; //!< persistent_rice_adaptation_enabled_flag 990 uint32_t IntraSmoothingDisabledFlag : __CODEGEN_BITFIELD(26, 26) ; //!< intra_smoothing_disabled_flag 991 uint32_t ExplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(27, 27) ; //!< explicit_rdpcm_enabled_flag 992 uint32_t ImplicitRdpcmEnabledFlag : __CODEGEN_BITFIELD(28, 28) ; //!< implicit_rdpcm_enabled_flag 993 uint32_t TransformSkipContextEnabledFlag : __CODEGEN_BITFIELD(29, 29) ; //!< transform_skip_context_enabled_flag 994 uint32_t TransformSkipRotationEnabledFlag : __CODEGEN_BITFIELD(30, 30) ; //!< transform_skip_rotation_enabled_flag 995 uint32_t SpsRangeExtensionEnableFlag : __CODEGEN_BITFIELD(31, 31) ; //!< sps_range_extension_enable_flag 996 }; 997 uint32_t Value; 998 } DW3; 999 union 1000 { 1001 struct 1002 { 1003 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 2) ; //!< Reserved 1004 uint32_t SampleAdaptiveOffsetEnabledFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< sample_adaptive_offset_enabled_flag 1005 uint32_t PcmEnabledFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< pcm_enabled_flag 1006 uint32_t CuQpDeltaEnabledFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< CU_QP_DELTA_ENABLED_FLAG 1007 uint32_t DiffCuQpDeltaDepthOrNamedAsMaxDqpDepth : __CODEGEN_BITFIELD( 6, 7) ; //!< diff_cu_qp_delta_depth (or named as max_dqp_depth) 1008 uint32_t PcmLoopFilterDisableFlag : __CODEGEN_BITFIELD( 8, 8) ; //!< pcm_loop_filter_disable_flag 1009 uint32_t ConstrainedIntraPredFlag : __CODEGEN_BITFIELD( 9, 9) ; //!< constrained_intra_pred_flag 1010 uint32_t Log2ParallelMergeLevelMinus2 : __CODEGEN_BITFIELD(10, 12) ; //!< log2_parallel_merge_level_minus2 1011 uint32_t SignDataHidingFlag : __CODEGEN_BITFIELD(13, 13) ; //!< SIGN_DATA_HIDING_FLAG 1012 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 14) ; //!< Reserved 1013 uint32_t LoopFilterAcrossTilesEnabledFlag : __CODEGEN_BITFIELD(15, 15) ; //!< loop_filter_across_tiles_enabled_flag 1014 uint32_t EntropyCodingSyncEnabledFlag : __CODEGEN_BITFIELD(16, 16) ; //!< entropy_coding_sync_enabled_flag 1015 uint32_t TilesEnabledFlag : __CODEGEN_BITFIELD(17, 17) ; //!< tiles_enabled_flag 1016 uint32_t WeightedBipredFlag : __CODEGEN_BITFIELD(18, 18) ; //!< weighted_bipred_flag 1017 uint32_t WeightedPredFlag : __CODEGEN_BITFIELD(19, 19) ; //!< weighted_pred_flag 1018 uint32_t Fieldpic : __CODEGEN_BITFIELD(20, 20) ; //!< FIELDPIC 1019 uint32_t Bottomfield : __CODEGEN_BITFIELD(21, 21) ; //!< BOTTOMFIELD 1020 uint32_t TransformSkipEnabledFlag : __CODEGEN_BITFIELD(22, 22) ; //!< TRANSFORM_SKIP_ENABLED_FLAG 1021 uint32_t AmpEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< AMP_ENABLED_FLAG 1022 uint32_t Reserved152 : __CODEGEN_BITFIELD(24, 24) ; //!< Reserved 1023 uint32_t TransquantBypassEnableFlag : __CODEGEN_BITFIELD(25, 25) ; //!< TRANSQUANT_BYPASS_ENABLE_FLAG 1024 uint32_t StrongIntraSmoothingEnableFlag : __CODEGEN_BITFIELD(26, 26) ; //!< strong_intra_smoothing_enable_flag 1025 uint32_t CuPacketStructure : __CODEGEN_BITFIELD(27, 27) ; //!< CU packet structure 1026 uint32_t Reserved156 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1027 }; 1028 uint32_t Value; 1029 } DW4; 1030 union 1031 { 1032 struct 1033 { 1034 uint32_t PicCbQpOffset : __CODEGEN_BITFIELD( 0, 4) ; //!< pic_cb_qp_offset 1035 uint32_t PicCrQpOffset : __CODEGEN_BITFIELD( 5, 9) ; //!< pic_cr_qp_offset 1036 uint32_t MaxTransformHierarchyDepthIntraOrNamedAsTuMaxDepthIntra : __CODEGEN_BITFIELD(10, 12) ; //!< max_transform_hierarchy_depth_intra (or named as tu_max_depth_intra) 1037 uint32_t MaxTransformHierarchyDepthInterOrNamedAsTuMaxDepthInter : __CODEGEN_BITFIELD(13, 15) ; //!< max_transform_hierarchy_depth_inter(or named as tu_max_depth_inter) 1038 uint32_t PcmSampleBitDepthChromaMinus1 : __CODEGEN_BITFIELD(16, 19) ; //!< pcm_sample_bit_depth_chroma_minus1 1039 uint32_t PcmSampleBitDepthLumaMinus1 : __CODEGEN_BITFIELD(20, 23) ; //!< pcm_sample_bit_depth_luma_minus1 1040 uint32_t BitDepthChromaMinus8 : __CODEGEN_BITFIELD(24, 26) ; //!< BIT_DEPTH_CHROMA_MINUS8 1041 uint32_t BitDepthLumaMinus8 : __CODEGEN_BITFIELD(27, 29) ; //!< BIT_DEPTH_LUMA_MINUS8 1042 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1043 }; 1044 uint32_t Value; 1045 } DW5; 1046 union 1047 { 1048 struct 1049 { 1050 uint32_t LcuMaxBitsizeAllowed : __CODEGEN_BITFIELD( 0, 15) ; //!< LCU Max BitSize Allowed 1051 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 1052 uint32_t Reserved209 : __CODEGEN_BITFIELD(17, 23) ; //!< Reserved 1053 uint32_t LcumaxbitstatusenLcumaxsizereportmask : __CODEGEN_BITFIELD(24, 24) ; //!< LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1054 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1055 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1056 uint32_t Reserved219 : __CODEGEN_BITFIELD(27, 28) ; //!< Reserved 1057 uint32_t LoadSlicePointerFlag : __CODEGEN_BITFIELD(29, 29) ; //!< LOAD_SLICE_POINTER_FLAG 1058 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1059 }; 1060 uint32_t Value; 1061 } DW6; 1062 union 1063 { 1064 struct 1065 { 1066 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 1067 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1068 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 1069 }; 1070 uint32_t Value; 1071 } DW7; 1072 union 1073 { 1074 struct 1075 { 1076 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 1077 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 1078 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 1079 }; 1080 uint32_t Value; 1081 } DW8; 1082 union 1083 { 1084 struct 1085 { 1086 uint32_t Framebitratemindelta : __CODEGEN_BITFIELD( 0, 14) ; //!< FRAMEBITRATEMINDELTA 1087 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1088 uint32_t Framebitratemaxdelta : __CODEGEN_BITFIELD(16, 30) ; //!< FRAMEBITRATEMAXDELTA 1089 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1090 }; 1091 uint32_t Value; 1092 } DW9; 1093 union 1094 { 1095 struct 1096 { 1097 uint64_t Framedeltaqpmax ; //!< FrameDeltaQpMax 1098 }; 1099 uint32_t Value[2]; 1100 } DW10_11; 1101 union 1102 { 1103 struct 1104 { 1105 uint64_t Framedeltaqpmin ; //!< FrameDeltaQpMin 1106 }; 1107 uint32_t Value[2]; 1108 } DW12_13; 1109 union 1110 { 1111 struct 1112 { 1113 uint64_t Framedeltaqpmaxrange ; //!< FrameDeltaQpMaxRange 1114 }; 1115 uint32_t Value[2]; 1116 } DW14_15; 1117 union 1118 { 1119 struct 1120 { 1121 uint64_t Framedeltaqpminrange ; //!< FrameDeltaQpMinRange 1122 }; 1123 uint32_t Value[2]; 1124 } DW16_17; 1125 union 1126 { 1127 struct 1128 { 1129 uint32_t Minframesize : __CODEGEN_BITFIELD( 0, 15) ; //!< MINFRAMESIZE 1130 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 1131 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 1132 }; 1133 uint32_t Value; 1134 } DW18; 1135 union 1136 { 1137 struct 1138 { 1139 uint32_t FractionalQpInput : __CODEGEN_BITFIELD( 0, 2) ; //!< Fractional QP Input 1140 uint32_t FractionalQpOffset : __CODEGEN_BITFIELD( 3, 5) ; //!< Fractional QP Offset 1141 uint32_t RhodomainRateControlEnable : __CODEGEN_BITFIELD( 6, 6) ; //!< RhoDomain Rate Control Enable 1142 uint32_t FractionalQpAdjustmentEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< Fractional QP adjustment enable 1143 uint32_t Rhodomainframelevelqp : __CODEGEN_BITFIELD( 8, 13) ; //!< RhoDomainFrameLevelQP 1144 uint32_t PakDynamicSliceModeEnable : __CODEGEN_BITFIELD(14, 14) ; //!< PAK Dynamic Slice Mode Enable 1145 uint32_t NoOutputOfPriorPicsFlag : __CODEGEN_BITFIELD(15, 15) ; //!< no_output_of_prior_pics_flag 1146 uint32_t FirstSliceSegmentInPicFlag : __CODEGEN_BITFIELD(16, 16) ; //!< first_slice_segment_in_pic_flag 1147 uint32_t Nalunittypeflag : __CODEGEN_BITFIELD(17, 17) ; //!< NalUnitTypeFlag 1148 uint32_t SlicePicParameterSetId : __CODEGEN_BITFIELD(18, 23) ; //!< slice_pic_parameter_set_id 1149 uint32_t SseEnable : __CODEGEN_BITFIELD(24, 24) ; //!< SSE Enable 1150 uint32_t RdoqEnable : __CODEGEN_BITFIELD(25, 25) ; //!< RDOQ Enable 1151 uint32_t NumberoflcusinnormalSliceSizeConformanceMode : __CODEGEN_BITFIELD(26, 27) ; //!< NumberOfLCUsInNormal Slice size conformance Mode 1152 uint32_t Reserved636 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1153 }; 1154 uint32_t Value; 1155 } DW19; 1156 union 1157 { 1158 struct 1159 { 1160 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 1161 uint32_t Intratucountbasedrdoqdisable : __CODEGEN_BITFIELD( 6, 6) ; //!< IntraTuCountBasedRDOQdisable 1162 uint32_t Reserved647 : __CODEGEN_BITFIELD( 7, 31) ; //!< Reserved 1163 }; 1164 uint32_t Value; 1165 } DW20; 1166 union 1167 { 1168 struct 1169 { 1170 uint32_t SliceSizeThresholdInBytes ; //!< Slice Size Threshold in Bytes 1171 }; 1172 uint32_t Value; 1173 } DW21; 1174 union 1175 { 1176 struct 1177 { 1178 uint32_t TargetSliceSizeInBytes ; //!< Target Slice Size in Bytes 1179 }; 1180 uint32_t Value; 1181 } DW22; 1182 union 1183 { 1184 struct 1185 { 1186 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 1187 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 1188 }; 1189 uint32_t Value; 1190 } DW23; 1191 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 1192 union 1193 { 1194 struct 1195 { 1196 uint32_t CbQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cb_qp_offset_list[0] 1197 uint32_t CbQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cb_qp_offset_list[1] 1198 uint32_t CbQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cb_qp_offset_list[2] 1199 uint32_t CbQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cb_qp_offset_list[3] 1200 uint32_t CbQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cb_qp_offset_list[4] 1201 uint32_t CbQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cb_qp_offset_list[5] 1202 uint32_t Reserved1054 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1203 }; 1204 uint32_t Value; 1205 } DW32; 1206 union 1207 { 1208 struct 1209 { 1210 uint32_t CrQpOffsetList0 : __CODEGEN_BITFIELD( 0, 4) ; //!< cr_qp_offset_list[0] 1211 uint32_t CrQpOffsetList1 : __CODEGEN_BITFIELD( 5, 9) ; //!< cr_qp_offset_list[1] 1212 uint32_t CrQpOffsetList2 : __CODEGEN_BITFIELD(10, 14) ; //!< cr_qp_offset_list[2] 1213 uint32_t CrQpOffsetList3 : __CODEGEN_BITFIELD(15, 19) ; //!< cr_qp_offset_list[3] 1214 uint32_t CrQpOffsetList4 : __CODEGEN_BITFIELD(20, 24) ; //!< cr_qp_offset_list[4] 1215 uint32_t CrQpOffsetList5 : __CODEGEN_BITFIELD(25, 29) ; //!< cr_qp_offset_list[5] 1216 uint32_t Reserved1086 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1217 }; 1218 uint32_t Value; 1219 } DW33; 1220 uint32_t Reserved1088[3]; //!< DWORD34..36 1221 union 1222 { 1223 struct 1224 { 1225 uint32_t Rdoqintratuthreshold : __CODEGEN_BITFIELD( 0, 15) ; //!< RDOQIntraTUThreshold 1226 uint32_t Reserved1168 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1227 }; 1228 uint32_t Value; 1229 } DW37; 1230 1231 //! \name Local enumerations 1232 1233 enum MEDIA_INSTRUCTION_COMMAND 1234 { 1235 MEDIA_INSTRUCTION_COMMAND_HCPPICSTATE = 16, //!< No additional details 1236 }; 1237 1238 //! \brief MEDIA_INSTRUCTION_OPCODE 1239 //! \details 1240 //! Codec/Engine Name = HCP = 7h 1241 enum MEDIA_INSTRUCTION_OPCODE 1242 { 1243 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1244 }; 1245 1246 enum PIPELINE_TYPE 1247 { 1248 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1249 }; 1250 1251 enum COMMAND_TYPE 1252 { 1253 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1254 }; 1255 1256 //! \brief MINCUSIZE 1257 //! \details 1258 //! Specifies the smallest coding block size. 1259 enum MINCUSIZE 1260 { 1261 MINCUSIZE_8X8 = 0, //!< No additional details 1262 MINCUSIZE_16X16 = 1, //!< No additional details 1263 MINCUSIZE_32X32 = 2, //!< No additional details 1264 MINCUSIZE_64X64 = 3, //!< No additional details 1265 }; 1266 1267 //! \brief CTBSIZE_LCUSIZE 1268 //! \details 1269 //! Specifies the coding tree block size. 1270 enum CTBSIZE_LCUSIZE 1271 { 1272 CTBSIZE_LCUSIZE_ILLEGALRESERVED = 0, //!< No additional details 1273 CTBSIZE_LCUSIZE_16X16 = 1, //!< No additional details 1274 CTBSIZE_LCUSIZE_32X32 = 2, //!< No additional details 1275 CTBSIZE_LCUSIZE_64X64 = 3, //!< No additional details 1276 }; 1277 1278 //! \brief MINTUSIZE 1279 //! \details 1280 //! Specifies the smallest allowed transform block size. 1281 enum MINTUSIZE 1282 { 1283 MINTUSIZE_4X4 = 0, //!< No additional details 1284 MINTUSIZE_8X8 = 1, //!< No additional details 1285 MINTUSIZE_16X16 = 2, //!< No additional details 1286 MINTUSIZE_32X32 = 3, //!< No additional details 1287 }; 1288 1289 //! \brief MAXTUSIZE 1290 //! \details 1291 //! Specifies the largest allowed transform block size. 1292 enum MAXTUSIZE 1293 { 1294 MAXTUSIZE_4X4 = 0, //!< No additional details 1295 MAXTUSIZE_8X8 = 1, //!< No additional details 1296 MAXTUSIZE_16X16 = 2, //!< No additional details 1297 MAXTUSIZE_32X32 = 3, //!< No additional details 1298 }; 1299 1300 //! \brief MINPCMSIZE 1301 //! \details 1302 //! Specifies the smallest allowed PCM coding block size. 1303 enum MINPCMSIZE 1304 { 1305 MINPCMSIZE_8X8 = 0, //!< No additional details 1306 MINPCMSIZE_16X16 = 1, //!< No additional details 1307 MINPCMSIZE_32X32 = 2, //!< No additional details 1308 }; 1309 1310 //! \brief MAXPCMSIZE 1311 //! \details 1312 //! Specifies the largest allowed PCM coding block size. 1313 enum MAXPCMSIZE 1314 { 1315 MAXPCMSIZE_8X8 = 0, //!< No additional details 1316 MAXPCMSIZE_16X16 = 1, //!< No additional details 1317 MAXPCMSIZE_32X32 = 2, //!< No additional details 1318 }; 1319 1320 //! \brief LOG2_SAO_OFFSET_SCALE_LUMA 1321 //! \details 1322 //! <p>To scale SAO offset values for luma samples</p> 1323 //! <p>0 to Max(0,BitDepth<sub><font size="2">C</font></sub>−10)</p> 1324 //! <p>Default = 0</p> 1325 enum LOG2_SAO_OFFSET_SCALE_LUMA 1326 { 1327 LOG2_SAO_OFFSET_SCALE_LUMA_0 = 0, //!< No additional details 1328 }; 1329 1330 //! \brief LOG2_SAO_OFFSET_SCALE_CHROMA 1331 //! \details 1332 //! <p>To scale SAO offset values for chroma samples.</p> 1333 //! <p>0 to Max(0,BitDepth<sub>C</sub>−10)</p> 1334 //! <p>default = 0</p> 1335 //! <p>Decoder Only</p> 1336 enum LOG2_SAO_OFFSET_SCALE_CHROMA 1337 { 1338 LOG2_SAO_OFFSET_SCALE_CHROMA_0 = 0, //!< No additional details 1339 }; 1340 1341 //! \brief CHROMA_SUBSAMPLING 1342 //! \details 1343 //! <p>Specify the chroma subsampling of the current bitstream to be decoded 1344 //! or encoded.</p> 1345 //! <p>000 (0h) - Reserved (This setting is reserved for Monochrome 1346 //! setting--currently not suppported)</p> 1347 //! <p>001 (1h) - 4:2:0</p> 1348 //! <p>010 (2h) - 4:2:2</p> 1349 //! <p>011 (3h) - 4:4:4</p> 1350 //! <p>All other values are invalid for both encoder and decoder.</p> 1351 enum CHROMA_SUBSAMPLING 1352 { 1353 CHROMA_SUBSAMPLING_420 = 1, //!< No additional details 1354 CHROMA_SUBSAMPLING_422 = 2, //!< No additional details 1355 CHROMA_SUBSAMPLING_444 = 3, //!< No additional details 1356 }; 1357 1358 //! \brief COLPICISI 1359 //! \details 1360 //! Specifies that the collocated picture is comprised solely of I slices 1361 //! and that there are no P or B slices in the picture. 1362 enum COLPICISI 1363 { 1364 COLPICISI_COLLOCATEDPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1365 }; 1366 1367 //! \brief CURPICISI 1368 //! \details 1369 //! Specifies that the current picture is comprised solely of I slices and 1370 //! that there are no P or B slices in the picture. 1371 enum CURPICISI 1372 { 1373 CURPICISI_CURRENTPICTUREHASATLEASTONEPORBSLICE = 0, //!< No additional details 1374 }; 1375 1376 //! \brief INSERTTESTFLAG 1377 //! \details 1378 //! <p>CABAC 0 Word Insertion Test Enable (Encoder Only)This bit will modify 1379 //! CABAC K equation so that a positive K value can be generated easily. 1380 //! This is done for validation purpose only. In normal usage this bit 1381 //! should be set to 0.</p> 1382 //! <p>Regular equation for generating 'K' value when CABAC 0 Word Insertion 1383 //! Test Enable is set to 0.</p> 1384 //! <pre>K = {[((96 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs *3) 1385 //! + 1023) / 1024] - bytes_in_picture} / 3</pre> 1386 //! 1387 //! <p>Modified equation when CABAC 0 Word Insertion Test Enable bit set to 1388 //! 1.</p> 1389 //! 1390 //! <pre>K = {[((1536 * pic_bin_count()) - (RawMinCUBits * PicSizeInMinCUs 1391 //! *3) + 1023) / 1024] - bytes_in_picture} / 3</pre> 1392 //! 1393 //! <p>Encoder only feature.</p> 1394 enum INSERTTESTFLAG 1395 { 1396 INSERTTESTFLAG_UNNAMED0 = 0, //!< No additional details 1397 INSERTTESTFLAG_UNNAMED1 = 1, //!< No additional details 1398 }; 1399 1400 //! \brief CU_QP_DELTA_ENABLED_FLAG 1401 //! \details 1402 //! <p>cu_qp_delta_enabled_flag = 1 and Max_DQP_Level = 0 or 3 is supported 1403 //! for PAK standalone andVDEnc modes.</p> 1404 enum CU_QP_DELTA_ENABLED_FLAG 1405 { 1406 CU_QP_DELTA_ENABLED_FLAG_DISABLE = 0, //!< Does not allow QP change at CU or LCU level, the same QP is used for the entire slice. Max_DQP_Level = 0 (i.e. diff_cu_qp_delta_depath = 0). 1407 CU_QP_DELTA_ENABLED_FLAG_ENABLE = 1, //!< Allow QP change at CU level. MAX_DQP_level can be >0. 1408 }; 1409 1410 //! \brief SIGN_DATA_HIDING_FLAG 1411 //! \details 1412 //! Currently not supported in encoder, so must be set to 0 for encoding 1413 //! session. 1414 enum SIGN_DATA_HIDING_FLAG 1415 { 1416 SIGN_DATA_HIDING_FLAG_DISABLE = 0, //!< Specifies that sign bit hiding is disabled. 1417 SIGN_DATA_HIDING_FLAG_ENABLE = 1, //!< Specifies that sign bit hiding is enabled. 1418 }; 1419 1420 //! \brief FIELDPIC 1421 //! \details 1422 //! <p>Must be zero for encoder only.</p> 1423 enum FIELDPIC 1424 { 1425 FIELDPIC_VIDEOFRAME = 0, //!< No additional details 1426 FIELDPIC_VIDEOFIELD = 1, //!< No additional details 1427 }; 1428 1429 //! \brief BOTTOMFIELD 1430 //! \details 1431 //! <p>Must be zero for encoder only</p> 1432 enum BOTTOMFIELD 1433 { 1434 BOTTOMFIELD_BOTTOMFIELD = 0, //!< No additional details 1435 BOTTOMFIELD_TOPFIELD = 1, //!< No additional details 1436 }; 1437 1438 enum TRANSFORM_SKIP_ENABLED_FLAG 1439 { 1440 TRANSFORM_SKIP_ENABLED_FLAG_DISABLE = 0, //!< transform_skip_flag is not supported in the residual coding 1441 TRANSFORM_SKIP_ENABLED_FLAG_ENABLE = 1, //!< transform_skip_flag is supported 1442 }; 1443 1444 //! \brief AMP_ENABLED_FLAG 1445 //! \details 1446 //! In VDENC mode, this bit should be set to 1. 1447 enum AMP_ENABLED_FLAG 1448 { 1449 AMP_ENABLED_FLAG_DISABLE = 0, //!< Asymmetric motion partitions cannot be used in coding tree blocks. 1450 AMP_ENABLED_FLAG_ENABLE = 1, //!< Support asymmetric motion partitions, i.e. PartMode equal to PART_2NxnU, PART_2NxnD, PART_nLx2N, or PART_nRx2N. 1451 }; 1452 1453 enum TRANSQUANT_BYPASS_ENABLE_FLAG 1454 { 1455 TRANSQUANT_BYPASS_ENABLE_FLAG_DISABLE = 0, //!< cu_transquant_bypass is not supported 1456 TRANSQUANT_BYPASS_ENABLE_FLAG_ENABLE = 1, //!< cu_transquant_bypass is supported 1457 }; 1458 1459 //! \brief BIT_DEPTH_CHROMA_MINUS8 1460 //! \details 1461 //! This specifies the number of bit allow for Chroma pixels. In 8 bit mode, 1462 //! this must be set to 0. Encoder: Supports bit depths 8, 10 and 12 only. 1463 //! And also it must be same as Luma. Encoder: Does not support 10 or 12 bit 1464 //! Source Pixels and 8bit PAK. i.e. The source pixel depth should be less 1465 //! than or equal to the PAK bit depth. 1466 enum BIT_DEPTH_CHROMA_MINUS8 1467 { 1468 BIT_DEPTH_CHROMA_MINUS8_CHROMA8BIT = 0, //!< No additional details 1469 BIT_DEPTH_CHROMA_MINUS8_CHROMA9BIT = 1, //!< Only HEVC decoder supports 9 bits chroma.HEVC encoder does not supports 9 bits chroma. 1470 BIT_DEPTH_CHROMA_MINUS8_CHROMA10BIT = 2, //!< No additional details 1471 BIT_DEPTH_CHROMA_MINUS8_CHROMA11BIT = 3, //!< Not Validated 1472 BIT_DEPTH_CHROMA_MINUS8_CHROMA12BIT = 4, //!< Not validated 1473 }; 1474 1475 //! \brief BIT_DEPTH_LUMA_MINUS8 1476 //! \details 1477 //! This specifies the number of bit allow for Luma pixels. In 8 bit mode, 1478 //! this must be set to 0. Encoder: Suports bit depths 8, 10 and 12 only. 1479 //! Encoder: Does not support 10 or 12 bit Source Pixels and 8bit PAK i.e. 1480 //! the source pixel depth should be less than or equal to PAK bit depth. 1481 enum BIT_DEPTH_LUMA_MINUS8 1482 { 1483 BIT_DEPTH_LUMA_MINUS8_LUMA8BIT = 0, //!< No additional details 1484 BIT_DEPTH_LUMA_MINUS8_LUMA9BIT = 1, //!< Only HEVC decoder supports 9 bits luma.HEVC encoder does not supports 9 bits luma. 1485 BIT_DEPTH_LUMA_MINUS8_LUMA10BIT = 2, //!< No additional details 1486 BIT_DEPTH_LUMA_MINUS8_LUMA11BIT = 3, //!< Not Validated 1487 BIT_DEPTH_LUMA_MINUS8_LUMA12BIT = 4, //!< Not validated 1488 }; 1489 1490 //! \brief LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1491 //! \details 1492 //! This is a mask bit controlling if the condition of any LCU in the frame 1493 //! exceeds LCUMaxSize. 1494 enum LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK 1495 { 1496 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_DISABLE = 0, //!< Do not update bit 0 of HCP_IMAGE_STATUS control register. 1497 LCUMAXBITSTATUSEN_LCUMAXSIZEREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. 1498 }; 1499 1500 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1501 //! \details 1502 //! This is a mask bit controlling if the condition of frame level bit count 1503 //! exceeds FrameBitRateMax. 1504 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 1505 { 1506 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_IMAGE_STATUS control register. 1507 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit inHCP_IMAGE_STATUS_MASK register 1508 }; 1509 1510 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1511 //! \details 1512 //! This is a mask bit controlling if the condition of frame level bit count 1513 //! is less than FrameBitRateMin. 1514 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 1515 { 1516 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register. 1517 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. HW does not use this bit to set the bit in HCP_IMAGE_STATUS_CONTROL register. It's used pass the bit in HCP_IMAGE_STATUS_MASK register 1518 }; 1519 1520 //! \brief LOAD_SLICE_POINTER_FLAG 1521 //! \details 1522 //! <p>LoadBitStreamPointerPerSlice (Encoder-only)</p> 1523 //! <p>To support multiple slice picture and additional header/data 1524 //! insertion before and after an encoded slice. When this field is set to 1525 //! 0, bitstream pointer is only loaded once for the first slice of a frame. 1526 //! For subsequent slices in the frame, bitstream data are stitched together 1527 //! to form a single output data stream. When this field is set to 1, 1528 //! bitstream pointer is loaded for each slice of a frame. Basically 1529 //! bitstream data for different slices of a frame will be written to 1530 //! different memory locations.</p> 1531 enum LOAD_SLICE_POINTER_FLAG 1532 { 1533 LOAD_SLICE_POINTER_FLAG_DISABLE = 0, //!< Load BitStream Pointer only once for the first slice of a frame. 1534 LOAD_SLICE_POINTER_FLAG_ENABLE = 1, //!< Load/reload BitStream Pointer only once for the each slice, reload the start location of thebitstream buffer from the Indirect PAK-BSE Object Data Start Address field. 1535 }; 1536 1537 //! \brief FRAMEBITRATEMAXUNIT 1538 //! \details 1539 //! This field is the Frame Bitrate Maximum Limit Units. 1540 enum FRAMEBITRATEMAXUNIT 1541 { 1542 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 1543 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4kbyte unit 1544 }; 1545 1546 //! \brief FRAMEBITRATEMINUNIT 1547 //! \details 1548 //! This field is the Frame Bitrate Minimum Limit Units. 1549 enum FRAMEBITRATEMINUNIT 1550 { 1551 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 1552 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4kbyte unit 1553 }; 1554 1555 //! \brief FRAMEBITRATEMINDELTA 1556 //! \details 1557 //! This field is used to select the slice delta QP when FrameBitRateMin Is 1558 //! exceeded. It shares the same 1559 //! FrameBitrateMinUnit. 1560 enum FRAMEBITRATEMINDELTA 1561 { 1562 FRAMEBITRATEMINDELTA_UNNAMED0 = 0, //!< No additional details 1563 }; 1564 1565 //! \brief FRAMEBITRATEMAXDELTA 1566 //! \details 1567 //! This field is used to select the slice delta QP when FrameBitRateMax Is 1568 //! exceeded. It shares the same 1569 //! FrameBitrateMaxUnit. 1570 enum FRAMEBITRATEMAXDELTA 1571 { 1572 FRAMEBITRATEMAXDELTA_UNNAMED0 = 0, //!< No additional details 1573 }; 1574 1575 //! \brief MINFRAMESIZE 1576 //! \details 1577 //! <p>Minimum Frame Size [15:0] (in Word, 16-bit)(Encoder Only)</p> 1578 //! <p>Mininum Frame Size is specified to compensate for intel Rate Control 1579 //! Currently zero fill (no need to perform emulation byte insertion) is 1580 //! done only to the end of the CABAC_ZERO_WORD insertion (if any) at the 1581 //! last slice of a picture. It is needed for CBR. Intel encoder parameter. 1582 //! The caller should always make sure that the value, represented by 1583 //! Mininum Frame Size, is always less than maximum frame size 1584 //! FrameBitRateMax. This field is reserved in Decode mode.</p> 1585 enum MINFRAMESIZE 1586 { 1587 MINFRAMESIZE_UNNAMED0 = 0, //!< No additional details 1588 }; 1589 1590 //! \brief MINFRAMESIZEUNITS 1591 //! \details 1592 //! This field is the Minimum Frame Size Units 1593 enum MINFRAMESIZEUNITS 1594 { 1595 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 1596 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 16Kbytes. 1597 MINFRAMESIZEUNITS_COMPATIBILITYMODE = 2, //!< Minimum Frame Size is in 4bytes 1598 MINFRAMESIZEUNITS_16BYTES = 3, //!< Minimum Frame Size is 16 bytes. 1599 }; 1600 1601 //! \name Initializations 1602 1603 //! \brief Explicit member initialization function 1604 HCP_PIC_STATE_CMD(); 1605 1606 static const size_t dwSize = 38; 1607 static const size_t byteSize = 152; 1608 }; 1609 1610 //! 1611 //! \brief HCP_TILE_POSITION_IN_CTB 1612 //! \details 1613 //! 1614 //! 1615 struct HCP_TILE_POSITION_IN_CTB_CMD 1616 { 1617 union 1618 { 1619 struct 1620 { 1621 uint32_t Ctbpos0I : __CODEGEN_BITFIELD( 0, 7) ; //!< CtbPos0+i 1622 uint32_t Ctbpos1I : __CODEGEN_BITFIELD( 8, 15) ; //!< CtbPos1+i 1623 uint32_t Ctbpos2I : __CODEGEN_BITFIELD(16, 23) ; //!< CtbPos2+i 1624 uint32_t Ctbpos3I : __CODEGEN_BITFIELD(24, 31) ; //!< CtbPos3+i 1625 }; 1626 uint32_t Value; 1627 } DW0; 1628 1629 //! \name Local enumerations 1630 1631 //! \name Initializations 1632 1633 //! \brief Explicit member initialization function 1634 HCP_TILE_POSITION_IN_CTB_CMD(); 1635 1636 static const size_t dwSize = 1; 1637 static const size_t byteSize = 4; 1638 }; 1639 1640 //! 1641 //! \brief HCP_TILE_POSITION_IN_CTB_MSB 1642 //! \details 1643 //! Added to support 16k picture size. 1644 //! 1645 struct HCP_TILE_POSITION_IN_CTB_MSB_CMD 1646 { 1647 union 1648 { 1649 struct 1650 { 1651 uint32_t CtbRowPositionOfTileColumn098 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 0 [9:8] 1652 uint32_t CtbRowPositionOfTileColumn198 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 1 [9:8] 1653 uint32_t CtbRowPositionOfTileColumn298 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 2 [9:8] 1654 uint32_t CtbRowPositionOfTileColumn398 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 3 [9:8] 1655 uint32_t CtbRowPositionOfTileColumn498 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 4 [9:8] 1656 uint32_t CtbRowPositionOfTileColumn598 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb row position of tile column 5 [9:8] 1657 uint32_t CtbRowPositionOfTileColumn698 : __CODEGEN_BITFIELD(12, 13) ; //!< Ctb row position of tile column 6 [9:8] 1658 uint32_t CtbRowPositionOfTileColumn798 : __CODEGEN_BITFIELD(14, 15) ; //!< Ctb row position of tile column 7 [9:8] 1659 uint32_t CtbRowPositionOfTileColumn898 : __CODEGEN_BITFIELD(16, 17) ; //!< Ctb row position of tile column 8 [9:8] 1660 uint32_t CtbRowPositionOfTileColumn998 : __CODEGEN_BITFIELD(18, 19) ; //!< Ctb row position of tile column 9 [9:8] 1661 uint32_t CtbRowPositionOfTileColumn1098 : __CODEGEN_BITFIELD(20, 21) ; //!< Ctb row position of tile column 10 [9:8] 1662 uint32_t CtbRowPositionOfTileColumn1198 : __CODEGEN_BITFIELD(22, 23) ; //!< Ctb row position of tile column 11 [9:8] 1663 uint32_t CtbRowPositionOfTileColumn1298 : __CODEGEN_BITFIELD(24, 25) ; //!< Ctb row position of tile column 12 [9:8] 1664 uint32_t CtbRowPositionOfTileColumn1398 : __CODEGEN_BITFIELD(26, 27) ; //!< Ctb row position of tile column 13 [9:8] 1665 uint32_t CtbRowPositionOfTileColumn1498 : __CODEGEN_BITFIELD(28, 29) ; //!< Ctb row position of tile column 14 [9:8] 1666 uint32_t CtbRowPositionOfTileColumn1598 : __CODEGEN_BITFIELD(30, 31) ; //!< Ctb row position of tile column 15 [9:8] 1667 }; 1668 uint32_t Value; 1669 } DW0; 1670 union 1671 { 1672 struct 1673 { 1674 uint32_t CtbRowPositionOfTileColumn1698 : __CODEGEN_BITFIELD( 0, 1) ; //!< Ctb row position of tile column 16 [9:8] 1675 uint32_t CtbRowPositionOfTileColumn1798 : __CODEGEN_BITFIELD( 2, 3) ; //!< Ctb row position of tile column 17 [9:8] 1676 uint32_t CtbRowPositionOfTileColumn1898 : __CODEGEN_BITFIELD( 4, 5) ; //!< Ctb row position of tile column 18 [9:8] 1677 uint32_t CtbRowPositionOfTileColumn1998 : __CODEGEN_BITFIELD( 6, 7) ; //!< Ctb row position of tile column 19 [9:8] 1678 uint32_t CtbRowPositionOfTileColumn2098 : __CODEGEN_BITFIELD( 8, 9) ; //!< Ctb row position of tile column 20 [9:8] 1679 uint32_t CtbPositionOfTile2198 : __CODEGEN_BITFIELD(10, 11) ; //!< Ctb position of tile 21 [9:8] 1680 uint32_t Reserved44 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 1681 }; 1682 uint32_t Value; 1683 } DW1; 1684 1685 //! \name Local enumerations 1686 1687 //! \name Initializations 1688 1689 //! \brief Explicit member initialization function 1690 HCP_TILE_POSITION_IN_CTB_MSB_CMD(); 1691 1692 static const size_t dwSize = 2; 1693 static const size_t byteSize = 8; 1694 }; 1695 1696 //! 1697 //! \brief HCP_TILE_STATE 1698 //! \details 1699 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1700 //! Commands. Each HCP command has assigned a media instruction command as 1701 //! defined in DWord 0, BitField 22:16. 1702 //! 1703 //! This command is valid for decoder only. 1704 //! 1705 struct HCP_TILE_STATE_CMD 1706 { 1707 union 1708 { 1709 struct 1710 { 1711 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1712 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1713 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1714 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1715 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1716 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1717 }; 1718 uint32_t Value; 1719 } DW0; 1720 union 1721 { 1722 struct 1723 { 1724 uint32_t Numtilerowsminus1 : __CODEGEN_BITFIELD( 0, 4) ; //!< NumTileRowsMinus1 1725 uint32_t Numtilecolumnsminus1 : __CODEGEN_BITFIELD( 5, 9) ; //!< NumTileColumnsMinus1 1726 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1727 }; 1728 uint32_t Value; 1729 } DW1; 1730 HCP_TILE_POSITION_IN_CTB_CMD CtbColumnPositionOfTileColumn[5]; //!< DW2..6, Ctb column position of tile column 1731 HCP_TILE_POSITION_IN_CTB_CMD CtbRowPositionOfTileRow[6]; //!< DW7..12, Ctb row position of tile row 1732 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbColumnPositionMsb; //!< DW13..14, Ctb column position MSB 1733 HCP_TILE_POSITION_IN_CTB_MSB_CMD CtbRowPositionMsb; //!< DW15..16, Ctb row position MSB 1734 1735 //! \name Local enumerations 1736 1737 enum MEDIA_INSTRUCTION_COMMAND 1738 { 1739 MEDIA_INSTRUCTION_COMMAND_HCPTILESTATE = 17, //!< No additional details 1740 }; 1741 1742 //! \brief MEDIA_INSTRUCTION_OPCODE 1743 //! \details 1744 //! Codec/Engine Name = HCP = 7h 1745 enum MEDIA_INSTRUCTION_OPCODE 1746 { 1747 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1748 }; 1749 1750 enum PIPELINE_TYPE 1751 { 1752 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1753 }; 1754 1755 enum COMMAND_TYPE 1756 { 1757 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1758 }; 1759 1760 //! \name Initializations 1761 1762 //! \brief Explicit member initialization function 1763 HCP_TILE_STATE_CMD(); 1764 1765 static const size_t dwSize = 17; 1766 static const size_t byteSize = 68; 1767 }; 1768 1769 //! 1770 //! \brief HCP_REF_LIST_ENTRY 1771 //! \details 1772 //! 1773 //! 1774 struct HCP_REF_LIST_ENTRY_CMD 1775 { 1776 union 1777 { 1778 struct 1779 { 1780 uint32_t ReferencePictureTbValue : __CODEGEN_BITFIELD( 0, 7) ; //!< Reference Picture tb Value 1781 uint32_t ListEntryLxReferencePictureFrameIdRefaddr07 : __CODEGEN_BITFIELD( 8, 10) ; //!< list_entry_lX: Reference Picture Frame ID (RefAddr[0-7]) 1782 uint32_t ChromaWeightLxFlag : __CODEGEN_BITFIELD(11, 11) ; //!< CHROMA_WEIGHT_LX_FLAG 1783 uint32_t LumaWeightLxFlag : __CODEGEN_BITFIELD(12, 12) ; //!< LUMA_WEIGHT_LX_FLAG 1784 uint32_t Longtermreference : __CODEGEN_BITFIELD(13, 13) ; //!< LONGTERMREFERENCE 1785 uint32_t FieldPicFlag : __CODEGEN_BITFIELD(14, 14) ; //!< FIELD_PIC_FLAG 1786 uint32_t BottomFieldFlag : __CODEGEN_BITFIELD(15, 15) ; //!< BOTTOM_FIELD_FLAG 1787 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1788 }; 1789 uint32_t Value; 1790 } DW0; 1791 1792 //! \name Local enumerations 1793 1794 //! \brief CHROMA_WEIGHT_LX_FLAG 1795 //! \details 1796 //! Where X is the RefPicListNum and i is the list entry number 0 through 1797 //! 15. DW2 corresponds to i=0, 1798 //! DW17 corresponds to i=15. 1799 enum CHROMA_WEIGHT_LX_FLAG 1800 { 1801 CHROMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORCHROMA = 0, //!< No additional details 1802 CHROMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORCHROMA = 1, //!< No additional details 1803 }; 1804 1805 //! \brief LUMA_WEIGHT_LX_FLAG 1806 //! \details 1807 //! Where X is the RefPicListNum and i is the list entry number 0 through 1808 //! 15. DW2 corresponds to i=0, 1809 //! DW17 corresponds to i=15. 1810 enum LUMA_WEIGHT_LX_FLAG 1811 { 1812 LUMA_WEIGHT_LX_FLAG_DEFAULTWEIGHTEDPREDICTIONFORLUMA = 0, //!< No additional details 1813 LUMA_WEIGHT_LX_FLAG_EXPLICITWEIGHTEDPREDICTIONFORLUMA = 1, //!< No additional details 1814 }; 1815 1816 //! \brief LONGTERMREFERENCE 1817 //! \details 1818 //! Where X is the RefPicListNum and i is the list entry number 0 through 1819 //! 15. DW2 corresponds to i=0, 1820 //! DW17 corresponds to i=15. 1821 enum LONGTERMREFERENCE 1822 { 1823 LONGTERMREFERENCE_SHORTTERMREFERENCE = 0, //!< No additional details 1824 LONGTERMREFERENCE_LONGTERMREFERENCE = 1, //!< No additional details 1825 }; 1826 1827 //! \brief FIELD_PIC_FLAG 1828 //! \details 1829 //! Where X is the RefPicListNum and i is the list entry number 0 through 1830 //! 15. DW2 corresponds to i=0, 1831 //! DW17 corresponds to i=15. 1832 enum FIELD_PIC_FLAG 1833 { 1834 FIELD_PIC_FLAG_VIDEOFRAME = 0, //!< No additional details 1835 FIELD_PIC_FLAG_VIDEOFIELD = 1, //!< No additional details 1836 }; 1837 1838 //! \brief BOTTOM_FIELD_FLAG 1839 //! \details 1840 //! Where X is the RefPicListNum and i is the list entry number 0 through 1841 //! 15. DW2 corresponds to i=0, 1842 //! DW17 corresponds to i=15. 1843 enum BOTTOM_FIELD_FLAG 1844 { 1845 BOTTOM_FIELD_FLAG_BOTTOMFIELD = 0, //!< No additional details 1846 BOTTOM_FIELD_FLAG_TOPFIELD = 1, //!< No additional details 1847 }; 1848 1849 //! \name Initializations 1850 1851 //! \brief Explicit member initialization function 1852 HCP_REF_LIST_ENTRY_CMD(); 1853 1854 static const size_t dwSize = 1; 1855 static const size_t byteSize = 4; 1856 }; 1857 1858 //! 1859 //! \brief HCP_REF_IDX_STATE 1860 //! \details 1861 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 1862 //! Commands. Each HCP command has assigned a media instruction command as 1863 //! defined in DWord 0, BitField 22:16. 1864 //! 1865 //! This is a slice level command used in both encoding and decoding 1866 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 1867 //! 1868 //! Unlike AVC, HEVC allows 16 reference idx entries in each of the L0 and 1869 //! L1 list for a progressive picture. Hence, a max total 32 reference idx 1870 //! in both lists together. The same when the picture is a field picture. 1871 //! Regardless the number of reference idx entries, there are only max 8 1872 //! reference pictures exist at any one time. Multiple reference idx can 1873 //! point to the same reference picture and can optionally pic a top or 1874 //! bottom field, or frame. 1875 //! 1876 //! For P-Slice, this command is issued only once, representing L0 list. For 1877 //! B-Slice, this command can be issued up to two times, one for L0 list and 1878 //! one for L1 list. 1879 //! 1880 struct HCP_REF_IDX_STATE_CMD 1881 { 1882 union 1883 { 1884 struct 1885 { 1886 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1887 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1888 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 1889 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 1890 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 1891 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1892 }; 1893 uint32_t Value; 1894 } DW0; 1895 union 1896 { 1897 struct 1898 { 1899 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 1900 uint32_t NumRefIdxLRefpiclistnumActiveMinus1 : __CODEGEN_BITFIELD( 1, 4) ; //!< num_ref_idx_l[RefPicListNum]_active_minus1 1901 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 31) ; //!< Reserved 1902 }; 1903 uint32_t Value; 1904 } DW1; 1905 HCP_REF_LIST_ENTRY_CMD Entries[16]; //!< DW2..17, Entries 1906 1907 //! \name Local enumerations 1908 1909 enum MEDIA_INSTRUCTION_COMMAND 1910 { 1911 MEDIA_INSTRUCTION_COMMAND_HCPREFIDXSTATE = 18, //!< No additional details 1912 }; 1913 1914 //! \brief MEDIA_INSTRUCTION_OPCODE 1915 //! \details 1916 //! Codec/Engine Name = HCP = 7h 1917 enum MEDIA_INSTRUCTION_OPCODE 1918 { 1919 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 1920 }; 1921 1922 enum PIPELINE_TYPE 1923 { 1924 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 1925 }; 1926 1927 enum COMMAND_TYPE 1928 { 1929 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1930 }; 1931 1932 enum REFPICLISTNUM 1933 { 1934 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 1935 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 1936 }; 1937 1938 //! \name Initializations 1939 1940 //! \brief Explicit member initialization function 1941 HCP_REF_IDX_STATE_CMD(); 1942 1943 static const size_t dwSize = 18; 1944 static const size_t byteSize = 72; 1945 }; 1946 1947 //! 1948 //! \brief HCP_WEIGHTOFFSET_LUMA_ENTRY 1949 //! \details 1950 //! 1951 //! 1952 struct HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD 1953 { 1954 union 1955 { 1956 struct 1957 { 1958 uint32_t DeltaLumaWeightLxI : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_luma_weight_lX[i] 1959 uint32_t LumaOffsetLxI : __CODEGEN_BITFIELD( 8, 15) ; //!< luma_offset_lX[i] 1960 uint32_t Reserved16 : __CODEGEN_BITFIELD(16, 23) ; //!< Reserved 1961 uint32_t LumaOffsetLxIMsbyte : __CODEGEN_BITFIELD(24, 31) ; //!< luma_offset_lX[i] MSByte 1962 }; 1963 uint32_t Value; 1964 } DW0; 1965 1966 //! \name Local enumerations 1967 1968 //! \name Initializations 1969 1970 //! \brief Explicit member initialization function 1971 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD(); 1972 1973 static const size_t dwSize = 1; 1974 static const size_t byteSize = 4; 1975 }; 1976 1977 //! 1978 //! \brief HCP_WEIGHTOFFSET_CHROMA_ENTRY 1979 //! \details 1980 //! 1981 //! 1982 struct HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD 1983 { 1984 union 1985 { 1986 struct 1987 { 1988 uint32_t DeltaChromaWeightLxI0 : __CODEGEN_BITFIELD( 0, 7) ; //!< delta_chroma_weight_lX[i][0] 1989 uint32_t ChromaoffsetlxI0 : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i][0] 1990 uint32_t DeltaChromaWeightLxI1 : __CODEGEN_BITFIELD(16, 23) ; //!< delta_chroma_weight_lX[i][1] 1991 uint32_t ChromaoffsetlxI1 : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX [i][1] 1992 }; 1993 uint32_t Value; 1994 } DW0; 1995 1996 //! \name Local enumerations 1997 1998 //! \name Initializations 1999 2000 //! \brief Explicit member initialization function 2001 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD(); 2002 2003 static const size_t dwSize = 1; 2004 static const size_t byteSize = 4; 2005 }; 2006 2007 //! 2008 //! \brief HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY 2009 //! \details 2010 //! 2011 //! 2012 struct HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD 2013 { 2014 union 2015 { 2016 struct 2017 { 2018 uint32_t ChromaoffsetlxI0Msbyte : __CODEGEN_BITFIELD( 0, 7) ; //!< ChromaOffsetLX[i][0] MSByte 2019 uint32_t ChromaoffsetlxI10Msbyte : __CODEGEN_BITFIELD( 8, 15) ; //!< ChromaOffsetLX[i+1][0] MSByte 2020 uint32_t ChromaoffsetlxI1Msbyte : __CODEGEN_BITFIELD(16, 23) ; //!< ChromaOffsetLX[i][1] MSByte 2021 uint32_t ChromaoffsetlxI11Msbyte : __CODEGEN_BITFIELD(24, 31) ; //!< ChromaOffsetLX[i+1][1] MSByte 2022 }; 2023 uint32_t Value; 2024 } DW0; 2025 2026 //! \name Local enumerations 2027 2028 //! \name Initializations 2029 2030 //! \brief Explicit member initialization function 2031 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD(); 2032 2033 static const size_t dwSize = 1; 2034 static const size_t byteSize = 4; 2035 }; 2036 2037 //! 2038 //! \brief HCP_WEIGHTOFFSET_STATE 2039 //! \details 2040 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2041 //! Commands. Each HCP command has assigned a media instruction command as 2042 //! defined in DWord 0, BitField 22:16. 2043 //! 2044 //! This slice level command is issued in both the encoding and decoding 2045 //! processes, if the weighted_pred_flag or weighted_bipred_flag equals one. 2046 //! If zero, then this command is not issued. Weight Prediction Values are 2047 //! provided in this command. Only Explicit Weight Prediction is supported 2048 //! in encoder. For P-Slice, this command is issued only once together with 2049 //! HCP_REF_IDX_STATE Command for L0 list. For B-Slice, this command can be 2050 //! issued up to two times together with HCP_REF_IDX_STATE Command, one for 2051 //! L0 list and one for L1 list. 2052 //! 2053 struct HCP_WEIGHTOFFSET_STATE_CMD 2054 { 2055 union 2056 { 2057 struct 2058 { 2059 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2060 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2061 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2062 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2063 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2064 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2065 }; 2066 uint32_t Value; 2067 } DW0; 2068 union 2069 { 2070 struct 2071 { 2072 uint32_t Refpiclistnum : __CODEGEN_BITFIELD( 0, 0) ; //!< REFPICLISTNUM 2073 uint32_t Reserved33 : __CODEGEN_BITFIELD( 1, 31) ; //!< Reserved 2074 }; 2075 uint32_t Value; 2076 } DW1; 2077 HCP_WEIGHTOFFSET_LUMA_ENTRY_CMD Lumaoffsets[16]; //!< DW2..17, LumaOffsets 2078 HCP_WEIGHTOFFSET_CHROMA_ENTRY_CMD Chromaoffsets[16]; //!< DW18..33, ChromaOffsets 2079 HCP_WEIGHTOFFSET_CHROMA_EXT_ENTRY_CMD Chromaoffsetsext[8]; //!< DW34..41, ChromaOffsetsExt 2080 2081 //! \name Local enumerations 2082 2083 enum MEDIA_INSTRUCTION_COMMAND 2084 { 2085 MEDIA_INSTRUCTION_COMMAND_HCPWEIGHTOFFSETSTATE = 19, //!< No additional details 2086 }; 2087 2088 //! \brief MEDIA_INSTRUCTION_OPCODE 2089 //! \details 2090 //! Codec/Engine Name = HCP = 7h 2091 enum MEDIA_INSTRUCTION_OPCODE 2092 { 2093 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2094 }; 2095 2096 enum PIPELINE_TYPE 2097 { 2098 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2099 }; 2100 2101 enum COMMAND_TYPE 2102 { 2103 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2104 }; 2105 2106 enum REFPICLISTNUM 2107 { 2108 REFPICLISTNUM_REFERENCEPICTURELIST0 = 0, //!< No additional details 2109 REFPICLISTNUM_REFERENCEPICTURELIST1 = 1, //!< No additional details 2110 }; 2111 2112 //! \name Initializations 2113 2114 //! \brief Explicit member initialization function 2115 HCP_WEIGHTOFFSET_STATE_CMD(); 2116 2117 static const size_t dwSize = 42; 2118 static const size_t byteSize = 168; 2119 }; 2120 2121 //! 2122 //! \brief HCP_SLICE_STATE 2123 //! \details 2124 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2125 //! Commands. Each HCP command has assigned a media instruction command as 2126 //! defined in DWord 0, BitField 22:16. 2127 //! 2128 //! This is a slice level command used in both encoding and decoding 2129 //! processes. For decoder, it is issued with the HCP_BSD_OBJECT command. 2130 //! 2131 struct HCP_SLICE_STATE_CMD 2132 { 2133 union 2134 { 2135 struct 2136 { 2137 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2138 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2139 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2140 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2141 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2142 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2143 }; 2144 uint32_t Value; 2145 } DW0; 2146 union 2147 { 2148 struct 2149 { 2150 uint32_t SlicestartctbxOrSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< SliceStartCtbX or (slice_start_lcu_x encoder) 2151 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2152 uint32_t SlicestartctbyOrSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 25) ; //!< SliceStartCtbY or (slice_start_lcu_y encoder) 2153 uint32_t Reserved58 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2154 }; 2155 uint32_t Value; 2156 } DW1; 2157 union 2158 { 2159 struct 2160 { 2161 uint32_t NextslicestartctbxOrNextSliceStartLcuXEncoder : __CODEGEN_BITFIELD( 0, 9) ; //!< NextSliceStartCtbX or (next_slice_start_lcu_x encoder) 2162 uint32_t Reserved74 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 2163 uint32_t NextslicestartctbyOrNextSliceStartLcuYEncoder : __CODEGEN_BITFIELD(16, 26) ; //!< NextSliceStartCtbY or (next_slice_start_lcu_y encoder) 2164 uint32_t Reserved91 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 2165 }; 2166 uint32_t Value; 2167 } DW2; 2168 union 2169 { 2170 struct 2171 { 2172 uint32_t SliceType : __CODEGEN_BITFIELD( 0, 1) ; //!< SLICE_TYPE 2173 uint32_t Lastsliceofpic : __CODEGEN_BITFIELD( 2, 2) ; //!< LASTSLICEOFPIC 2174 uint32_t SliceqpSignFlag : __CODEGEN_BITFIELD( 3, 3) ; //!< SliceQp Sign Flag 2175 uint32_t DependentSliceFlag : __CODEGEN_BITFIELD( 4, 4) ; //!< dependent_slice_flag 2176 uint32_t SliceTemporalMvpEnableFlag : __CODEGEN_BITFIELD( 5, 5) ; //!< slice_temporal_mvp_enable_flag 2177 uint32_t Sliceqp : __CODEGEN_BITFIELD( 6, 11) ; //!< SliceQp 2178 uint32_t SliceCbQpOffset : __CODEGEN_BITFIELD(12, 16) ; //!< SLICE_CB_QP_OFFSET 2179 uint32_t SliceCrQpOffset : __CODEGEN_BITFIELD(17, 21) ; //!< SLICE_CR_QP_OFFSET 2180 uint32_t Intrareffetchdisable : __CODEGEN_BITFIELD(22, 22) ; //!< IntraRefFetchDisable 2181 uint32_t CuChromaQpOffsetEnabledFlag : __CODEGEN_BITFIELD(23, 23) ; //!< cu_chroma_qp_offset_enabled_flag 2182 uint32_t Lastsliceoftile : __CODEGEN_BITFIELD(24, 24) ; //!< LastSliceOfTile 2183 uint32_t Lastsliceoftilecolumn : __CODEGEN_BITFIELD(25, 25) ; //!< LastSliceOfTileColumn 2184 uint32_t Reserved122 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 2185 }; 2186 uint32_t Value; 2187 } DW3; 2188 union 2189 { 2190 struct 2191 { 2192 uint32_t SliceHeaderDisableDeblockingFilterFlag : __CODEGEN_BITFIELD( 0, 0) ; //!< slice_header_disable_deblocking_filter_flag 2193 uint32_t SliceTcOffsetDiv2OrFinalTcOffsetDiv2Encoder : __CODEGEN_BITFIELD( 1, 4) ; //!< slice_tc_offset_div2 or (final tc_offset_div2 Encoder) 2194 uint32_t SliceBetaOffsetDiv2OrFinalBetaOffsetDiv2Encoder : __CODEGEN_BITFIELD( 5, 8) ; //!< slice_beta_offset_div2 or (final Beta_Offset_div2 Encoder) 2195 uint32_t Reserved137 : __CODEGEN_BITFIELD( 9, 9) ; //!< Reserved 2196 uint32_t SliceLoopFilterAcrossSlicesEnabledFlag : __CODEGEN_BITFIELD(10, 10) ; //!< slice_loop_filter_across_slices_enabled_flag 2197 uint32_t SliceSaoChromaFlag : __CODEGEN_BITFIELD(11, 11) ; //!< slice_sao_chroma_flag 2198 uint32_t SliceSaoLumaFlag : __CODEGEN_BITFIELD(12, 12) ; //!< slice_sao_luma_flag 2199 uint32_t MvdL1ZeroFlag : __CODEGEN_BITFIELD(13, 13) ; //!< mvd_l1_zero_flag 2200 uint32_t Islowdelay : __CODEGEN_BITFIELD(14, 14) ; //!< isLowDelay 2201 uint32_t CollocatedFromL0Flag : __CODEGEN_BITFIELD(15, 15) ; //!< collocated_from_l0_flag 2202 uint32_t Chromalog2Weightdenom : __CODEGEN_BITFIELD(16, 18) ; //!< ChromaLog2WeightDenom 2203 uint32_t LumaLog2WeightDenom : __CODEGEN_BITFIELD(19, 21) ; //!< luma_log2_weight_denom 2204 uint32_t CabacInitFlag : __CODEGEN_BITFIELD(22, 22) ; //!< cabac_init_flag 2205 uint32_t Maxmergeidx : __CODEGEN_BITFIELD(23, 25) ; //!< MAXMERGEIDX 2206 uint32_t Collocatedrefidx : __CODEGEN_BITFIELD(26, 28) ; //!< CollocatedRefIDX 2207 uint32_t Reserved157 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2208 }; 2209 uint32_t Value; 2210 } DW4; 2211 union 2212 { 2213 struct 2214 { 2215 uint32_t Sliceheaderlength : __CODEGEN_BITFIELD( 0, 15) ; //!< SliceHeaderLength 2216 uint32_t Reserved176 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 2217 }; 2218 uint32_t Value; 2219 } DW5; 2220 union 2221 { 2222 struct 2223 { 2224 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 19) ; //!< Reserved 2225 uint32_t Roundintra : __CODEGEN_BITFIELD(20, 23) ; //!< ROUNDINTRA 2226 uint32_t Reserved216 : __CODEGEN_BITFIELD(24, 25) ; //!< Reserved 2227 uint32_t Roundinter : __CODEGEN_BITFIELD(26, 29) ; //!< ROUNDINTER 2228 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2229 }; 2230 uint32_t Value; 2231 } DW6; 2232 union 2233 { 2234 struct 2235 { 2236 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 2237 uint32_t Cabaczerowordinsertionenable : __CODEGEN_BITFIELD( 1, 1) ; //!< CABACZEROWORDINSERTIONENABLE 2238 uint32_t Emulationbytesliceinsertenable : __CODEGEN_BITFIELD( 2, 2) ; //!< EMULATIONBYTESLICEINSERTENABLE 2239 uint32_t Reserved227 : __CODEGEN_BITFIELD( 3, 7) ; //!< Reserved 2240 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD( 8, 8) ; //!< TAIL_INSERTION_ENABLE 2241 uint32_t SlicedataEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SLICEDATA_ENABLE 2242 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(10, 10) ; //!< HEADER_INSERTION_ENABLE 2243 uint32_t Reserved235 : __CODEGEN_BITFIELD(11, 31) ; //!< Reserved 2244 }; 2245 uint32_t Value; 2246 } DW7; 2247 union 2248 { 2249 struct 2250 { 2251 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 2252 uint32_t IndirectPakBseDataStartOffsetWrite : __CODEGEN_BITFIELD( 6, 28) ; //!< Indirect PAK-BSE Data Start Offset (Write) 2253 uint32_t Reserved285 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2254 }; 2255 uint32_t Value; 2256 } DW8; 2257 union 2258 { 2259 struct 2260 { 2261 uint32_t TransformskipLambda : __CODEGEN_BITFIELD( 0, 15) ; //!< Transformskip_lambda 2262 uint32_t Reserved304 : __CODEGEN_BITFIELD(16, 30) ; //!< Reserved 2263 uint32_t ForceSaoParametersToZero : __CODEGEN_BITFIELD(31, 31) ; //!< Force SAO parameters to zero 2264 }; 2265 uint32_t Value; 2266 } DW9; 2267 union 2268 { 2269 struct 2270 { 2271 uint32_t TransformskipNumzerocoeffsFactor0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Transformskip_numzerocoeffs_factor0 2272 uint32_t TransformskipNumnonzerocoeffsFactor0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Transformskip_numnonzerocoeffs_factor0 2273 uint32_t TransformskipNumzerocoeffsFactor1 : __CODEGEN_BITFIELD(16, 23) ; //!< Transformskip_numzerocoeffs_factor1 2274 uint32_t TransformskipNumnonzerocoeffsFactor1 : __CODEGEN_BITFIELD(24, 31) ; //!< Transformskip_numnonzerocoeffs_factor1 2275 }; 2276 uint32_t Value; 2277 } DW10; 2278 2279 //! \name Local enumerations 2280 2281 enum MEDIA_INSTRUCTION_COMMAND 2282 { 2283 MEDIA_INSTRUCTION_COMMAND_HCPSLICESTATE = 20, //!< No additional details 2284 }; 2285 2286 //! \brief MEDIA_INSTRUCTION_OPCODE 2287 //! \details 2288 //! Codec/Engine Name = HCP = 7h 2289 enum MEDIA_INSTRUCTION_OPCODE 2290 { 2291 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2292 }; 2293 2294 enum PIPELINE_TYPE 2295 { 2296 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2297 }; 2298 2299 enum COMMAND_TYPE 2300 { 2301 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2302 }; 2303 2304 //! \brief SLICE_TYPE 2305 //! \details 2306 //! In VDENC mode, for HEVC standard this field can be 0 or 2 only. 2307 enum SLICE_TYPE 2308 { 2309 SLICE_TYPE_B_SLICE = 0, //!< No additional details 2310 SLICE_TYPE_P_SLICE = 1, //!< No additional details 2311 SLICE_TYPE_I_SLICE = 2, //!< No additional details 2312 SLICE_TYPE_ILLEGALRESERVED = 3, //!< No additional details 2313 }; 2314 2315 //! \brief LASTSLICEOFPIC 2316 //! \details 2317 //! This indicates the current slice is the very last slice of the current 2318 //! picture 2319 enum LASTSLICEOFPIC 2320 { 2321 LASTSLICEOFPIC_NOTTHELASTSLICEOFTHEPICTURE = 0, //!< No additional details 2322 LASTSLICEOFPIC_LASTSLICEOFTHEPICTURE = 1, //!< No additional details 2323 }; 2324 2325 //! \brief SLICE_CB_QP_OFFSET 2326 //! \details 2327 //! For deblocking purpose, the pic and slice level cb qp offset must be 2328 //! provided separately. 2329 enum SLICE_CB_QP_OFFSET 2330 { 2331 SLICE_CB_QP_OFFSET_0 = 0, //!< No additional details 2332 SLICE_CB_QP_OFFSET_1 = 1, //!< No additional details 2333 SLICE_CB_QP_OFFSET_2 = 2, //!< No additional details 2334 SLICE_CB_QP_OFFSET_3 = 3, //!< No additional details 2335 SLICE_CB_QP_OFFSET_4 = 4, //!< No additional details 2336 SLICE_CB_QP_OFFSET_5 = 5, //!< No additional details 2337 SLICE_CB_QP_OFFSET_6 = 6, //!< No additional details 2338 SLICE_CB_QP_OFFSET_7 = 7, //!< No additional details 2339 SLICE_CB_QP_OFFSET_8 = 8, //!< No additional details 2340 SLICE_CB_QP_OFFSET_9 = 9, //!< No additional details 2341 SLICE_CB_QP_OFFSET_10 = 10, //!< No additional details 2342 SLICE_CB_QP_OFFSET_11 = 11, //!< No additional details 2343 SLICE_CB_QP_OFFSET_12 = 12, //!< No additional details 2344 SLICE_CB_QP_OFFSET_NEG_12 = 20, //!< No additional details 2345 SLICE_CB_QP_OFFSET_NEG_11 = 21, //!< No additional details 2346 SLICE_CB_QP_OFFSET_NEG_10 = 22, //!< No additional details 2347 SLICE_CB_QP_OFFSET_NEG_9 = 23, //!< No additional details 2348 SLICE_CB_QP_OFFSET_NEG_8 = 24, //!< No additional details 2349 SLICE_CB_QP_OFFSET_NEG_7 = 25, //!< No additional details 2350 SLICE_CB_QP_OFFSET_NEG_6 = 26, //!< No additional details 2351 SLICE_CB_QP_OFFSET_NEG_5 = 27, //!< No additional details 2352 SLICE_CB_QP_OFFSET_NEG_4 = 28, //!< No additional details 2353 SLICE_CB_QP_OFFSET_NEG_3 = 29, //!< No additional details 2354 SLICE_CB_QP_OFFSET_NEG_2 = 30, //!< No additional details 2355 SLICE_CB_QP_OFFSET_NEG_1 = 31, //!< No additional details 2356 }; 2357 2358 //! \brief SLICE_CR_QP_OFFSET 2359 //! \details 2360 //! For deblocking purpose, the pic and slice level cr qp offset must be 2361 //! provided separately. 2362 enum SLICE_CR_QP_OFFSET 2363 { 2364 SLICE_CR_QP_OFFSET_0 = 0, //!< No additional details 2365 SLICE_CR_QP_OFFSET_1 = 1, //!< No additional details 2366 SLICE_CR_QP_OFFSET_2 = 2, //!< No additional details 2367 SLICE_CR_QP_OFFSET_3 = 3, //!< No additional details 2368 SLICE_CR_QP_OFFSET_4 = 4, //!< No additional details 2369 SLICE_CR_QP_OFFSET_5 = 5, //!< No additional details 2370 SLICE_CR_QP_OFFSET_6 = 6, //!< No additional details 2371 SLICE_CR_QP_OFFSET_7 = 7, //!< No additional details 2372 SLICE_CR_QP_OFFSET_8 = 8, //!< No additional details 2373 SLICE_CR_QP_OFFSET_9 = 9, //!< No additional details 2374 SLICE_CR_QP_OFFSET_10 = 10, //!< No additional details 2375 SLICE_CR_QP_OFFSET_11 = 11, //!< No additional details 2376 SLICE_CR_QP_OFFSET_12 = 12, //!< No additional details 2377 SLICE_CR_QP_OFFSET_NEG_12 = 20, //!< No additional details 2378 SLICE_CR_QP_OFFSET_NEG_11 = 21, //!< No additional details 2379 SLICE_CR_QP_OFFSET_NEG_10 = 22, //!< No additional details 2380 SLICE_CR_QP_OFFSET_NEG_9 = 23, //!< No additional details 2381 SLICE_CR_QP_OFFSET_NEG_8 = 24, //!< No additional details 2382 SLICE_CR_QP_OFFSET_NEG_7 = 25, //!< No additional details 2383 SLICE_CR_QP_OFFSET_NEG_6 = 26, //!< No additional details 2384 SLICE_CR_QP_OFFSET_NEG_5 = 27, //!< No additional details 2385 SLICE_CR_QP_OFFSET_NEG_4 = 28, //!< No additional details 2386 SLICE_CR_QP_OFFSET_NEG_3 = 29, //!< No additional details 2387 SLICE_CR_QP_OFFSET_NEG_2 = 30, //!< No additional details 2388 SLICE_CR_QP_OFFSET_NEG_1 = 31, //!< No additional details 2389 }; 2390 2391 //! \brief MAXMERGEIDX 2392 //! \details 2393 //! MaxNumMergeCand = 5 - five_minus_max_num_merge_cand -1. 2394 enum MAXMERGEIDX 2395 { 2396 MAXMERGEIDX_0 = 0, //!< No additional details 2397 MAXMERGEIDX_1 = 1, //!< No additional details 2398 MAXMERGEIDX_2 = 2, //!< No additional details 2399 MAXMERGEIDX_3 = 3, //!< No additional details 2400 MAXMERGEIDX_4 = 4, //!< No additional details 2401 }; 2402 2403 //! \brief ROUNDINTRA 2404 //! \details 2405 //! In VDENC mode, this field is ignored. 2406 enum ROUNDINTRA 2407 { 2408 ROUNDINTRA_132 = 0, //!< No additional details 2409 ROUNDINTRA_232 = 1, //!< No additional details 2410 ROUNDINTRA_332 = 2, //!< No additional details 2411 ROUNDINTRA_432 = 3, //!< No additional details 2412 ROUNDINTRA_532 = 4, //!< No additional details 2413 ROUNDINTRA_632 = 5, //!< No additional details 2414 ROUNDINTRA_732 = 6, //!< No additional details 2415 ROUNDINTRA_832 = 7, //!< No additional details 2416 ROUNDINTRA_932 = 8, //!< No additional details 2417 ROUNDINTRA_1032 = 9, //!< No additional details 2418 ROUNDINTRA_1132 = 10, //!< No additional details 2419 ROUNDINTRA_1232 = 11, //!< No additional details 2420 ROUNDINTRA_1332 = 12, //!< No additional details 2421 ROUNDINTRA_1432 = 13, //!< No additional details 2422 ROUNDINTRA_1532 = 14, //!< No additional details 2423 ROUNDINTRA_1632 = 15, //!< No additional details 2424 }; 2425 2426 //! \brief ROUNDINTER 2427 //! \details 2428 //! In VDENC mode, this field is ignored. 2429 enum ROUNDINTER 2430 { 2431 ROUNDINTER_132 = 0, //!< No additional details 2432 ROUNDINTER_232 = 1, //!< No additional details 2433 ROUNDINTER_332 = 2, //!< No additional details 2434 ROUNDINTER_432 = 3, //!< No additional details 2435 ROUNDINTER_532 = 4, //!< No additional details 2436 ROUNDINTER_632 = 5, //!< No additional details 2437 ROUNDINTER_732 = 6, //!< No additional details 2438 ROUNDINTER_832 = 7, //!< No additional details 2439 ROUNDINTER_932 = 8, //!< No additional details 2440 ROUNDINTER_1032 = 9, //!< No additional details 2441 ROUNDINTER_1132 = 10, //!< No additional details 2442 ROUNDINTER_1232 = 11, //!< No additional details 2443 ROUNDINTER_1332 = 12, //!< No additional details 2444 ROUNDINTER_1432 = 13, //!< No additional details 2445 ROUNDINTER_1532 = 14, //!< No additional details 2446 ROUNDINTER_1632 = 15, //!< No additional details 2447 }; 2448 2449 //! \brief CABACZEROWORDINSERTIONENABLE 2450 //! \details 2451 //! To pad the end of a SliceLayer RBSP to meet the encoded size 2452 //! requirement. 2453 enum CABACZEROWORDINSERTIONENABLE 2454 { 2455 CABACZEROWORDINSERTIONENABLE_UNNAMED0 = 0, //!< No Cabac_Zero_Word Insertion. 2456 CABACZEROWORDINSERTIONENABLE_UNNAMED1 = 1, //!< Allow internal Cabac_Zero_Word generation and append to the end of RBSP (effectively can be usedas an indicator for last slice of a picture, if the assumption is only the last slice of a pictureneeds to insert CABAC_ZERO_WORDs). 2457 }; 2458 2459 //! \brief EMULATIONBYTESLICEINSERTENABLE 2460 //! \details 2461 //! To have PAK outputting SODB or EBSP to the output bitstream buffer. 2462 enum EMULATIONBYTESLICEINSERTENABLE 2463 { 2464 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGRBSP = 0, //!< No additional details 2465 EMULATIONBYTESLICEINSERTENABLE_OUTPUTTINGEBSP = 1, //!< No additional details 2466 }; 2467 2468 //! \brief TAIL_INSERTION_ENABLE 2469 //! \details 2470 //! Must be followed by the PAK Insertion Object Command to perform the 2471 //! actual insertion. 2472 enum TAIL_INSERTION_ENABLE 2473 { 2474 TAIL_INSERTION_ENABLE_UNNAMED0 = 0, //!< No tail insertion into the output bitstream buffer, after the current slice encoded bits. 2475 TAIL_INSERTION_ENABLE_UNNAMED1 = 1, //!< Tail insertion into the output bitstream buffer is present, and is after the current slice encoded bits.SKL restriction: Tail insertion is only possible at the end of frame but not in the middle (say slice end) 2476 }; 2477 2478 //! \brief SLICEDATA_ENABLE 2479 //! \details 2480 //! <p>Must always be enabled.</p> 2481 //! <p>Encoder only feature.</p> 2482 enum SLICEDATA_ENABLE 2483 { 2484 SLICEDATA_ENABLE_UNNAMED0 = 0, //!< No operation; no insertion. 2485 SLICEDATA_ENABLE_UNNAMED1 = 1, //!< Slice Data insertion by PAK Object Commands into the output bitstream buffer. 2486 }; 2487 2488 //! \brief HEADER_INSERTION_ENABLE 2489 //! \details 2490 //! Must be followed by the PAK Insertion Object Command to perform the 2491 //! actual insertion. 2492 enum HEADER_INSERTION_ENABLE 2493 { 2494 HEADER_INSERTION_ENABLE_UNNAMED0 = 0, //!< No header insertion into the output bitstream buffer, before the current slice encoded bits. 2495 HEADER_INSERTION_ENABLE_UNNAMED1 = 1, //!< Header insertion into the output bitstream buffer is present, and is before the current slice encoded bits. 2496 }; 2497 2498 //! \name Initializations 2499 2500 //! \brief Explicit member initialization function 2501 HCP_SLICE_STATE_CMD(); 2502 2503 static const size_t dwSize = 11; 2504 static const size_t byteSize = 44; 2505 }; 2506 2507 //! 2508 //! \brief HCP_BSD_OBJECT 2509 //! \details 2510 //! The HCP is selected with the Media Instruction Opcode "7h" for all HCP 2511 //! Commands. Each HCP command has assigned a media instruction command as 2512 //! defined in DWord 0, BitField 22:16. 2513 //! 2514 //! The HCP_BSD_OBJECT command fetches the HEVC bit stream for a slice 2515 //! starting with the first byte in the slice. The bit stream ends with the 2516 //! last non-zero bit of the frame and does not include any zero-padding at 2517 //! the end of the bit stream. There can be multiple slices in a HEVC frame 2518 //! and thus this command can be issued multiple times per frame. 2519 //! 2520 //! The HCP_BSD_OBJECT command must be the last command issued in the 2521 //! sequence of batch commands before the HCP starts decoding. Prior to 2522 //! issuing this command, it is assumed that all configuration parameters in 2523 //! the HCP have been loaded including workload configuration registers and 2524 //! configuration tables. When this command is issued, the HCP is waiting 2525 //! for bit stream data to be presented to the shift register. 2526 //! 2527 struct HCP_BSD_OBJECT_CMD 2528 { 2529 union 2530 { 2531 struct 2532 { 2533 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2534 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2535 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2536 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2537 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2538 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2539 }; 2540 uint32_t Value; 2541 } DW0; 2542 union 2543 { 2544 struct 2545 { 2546 uint32_t IndirectBsdDataLength ; //!< Indirect BSD Data Length 2547 }; 2548 uint32_t Value; 2549 } DW1; 2550 union 2551 { 2552 struct 2553 { 2554 uint32_t IndirectDataStartAddress : __CODEGEN_BITFIELD( 0, 28) ; //!< Indirect Data Start Address 2555 uint32_t Reserved93 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 2556 }; 2557 uint32_t Value; 2558 } DW2; 2559 2560 //! \name Local enumerations 2561 2562 enum MEDIA_INSTRUCTION_COMMAND 2563 { 2564 MEDIA_INSTRUCTION_COMMAND_HCPBSDOBJECTSTATE = 32, //!< No additional details 2565 }; 2566 2567 //! \brief MEDIA_INSTRUCTION_OPCODE 2568 //! \details 2569 //! Codec/Engine Name = HCP = 7h 2570 enum MEDIA_INSTRUCTION_OPCODE 2571 { 2572 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2573 }; 2574 2575 enum PIPELINE_TYPE 2576 { 2577 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2578 }; 2579 2580 enum COMMAND_TYPE 2581 { 2582 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2583 }; 2584 2585 //! \name Initializations 2586 2587 //! \brief Explicit member initialization function 2588 HCP_BSD_OBJECT_CMD(); 2589 2590 static const size_t dwSize = 3; 2591 static const size_t byteSize = 12; 2592 }; 2593 2594 //! 2595 //! \brief HCP_VP9_SEGMENT_STATE 2596 //! \details 2597 //! 2598 //! 2599 struct HCP_VP9_SEGMENT_STATE_CMD 2600 { 2601 union 2602 { 2603 struct 2604 { 2605 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2606 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2607 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2608 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2609 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2610 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2611 }; 2612 uint32_t Value; 2613 } DW0; 2614 union 2615 { 2616 struct 2617 { 2618 uint32_t SegmentId : __CODEGEN_BITFIELD( 0, 2) ; //!< Segment ID 2619 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 31) ; //!< Reserved 2620 }; 2621 uint32_t Value; 2622 } DW1; 2623 union 2624 { 2625 struct 2626 { 2627 uint32_t SegmentSkipped : __CODEGEN_BITFIELD( 0, 0) ; //!< Segment Skipped 2628 uint32_t SegmentReference : __CODEGEN_BITFIELD( 1, 2) ; //!< Segment Reference 2629 uint32_t SegmentReferenceEnabled : __CODEGEN_BITFIELD( 3, 3) ; //!< Segment Reference Enabled 2630 uint32_t Reserved68 : __CODEGEN_BITFIELD( 4, 31) ; //!< Reserved 2631 }; 2632 uint32_t Value; 2633 } DW2; 2634 union 2635 { 2636 struct 2637 { 2638 uint32_t Filterlevelref0Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef0Mode0 2639 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2640 uint32_t Filterlevelref0Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef0Mode1 2641 uint32_t Reserved110 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2642 uint32_t Filterlevelref1Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef1Mode0 2643 uint32_t Reserved118 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2644 uint32_t Filterlevelref1Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef1Mode1 2645 uint32_t Reserved126 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2646 }; 2647 uint32_t Value; 2648 } DW3; 2649 union 2650 { 2651 struct 2652 { 2653 uint32_t Filterlevelref2Mode0 : __CODEGEN_BITFIELD( 0, 5) ; //!< FilterLevelRef2Mode0 2654 uint32_t Reserved134 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 2655 uint32_t Filterlevelref2Mode1 : __CODEGEN_BITFIELD( 8, 13) ; //!< FilterLevelRef2Mode1 2656 uint32_t Reserved142 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 2657 uint32_t Filterlevelref3Mode0 : __CODEGEN_BITFIELD(16, 21) ; //!< FilterLevelRef3Mode0 2658 uint32_t Reserved150 : __CODEGEN_BITFIELD(22, 23) ; //!< Reserved 2659 uint32_t Filterlevelref3Mode1 : __CODEGEN_BITFIELD(24, 29) ; //!< FilterLevelRef3Mode1 2660 uint32_t Reserved158 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 2661 }; 2662 uint32_t Value; 2663 } DW4; 2664 union 2665 { 2666 struct 2667 { 2668 uint32_t LumaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Luma DC Quant Scale (Decode mode Only) 2669 uint32_t LumaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Luma AC Quant Scale (Decode mode Only) 2670 }; 2671 uint32_t Value; 2672 } DW5; 2673 union 2674 { 2675 struct 2676 { 2677 uint32_t ChromaDcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD( 0, 15) ; //!< Chroma DC Quant Scale (Decode mode Only) 2678 uint32_t ChromaAcQuantScaleDecodeModeOnly : __CODEGEN_BITFIELD(16, 31) ; //!< Chroma AC Quant Scale (Decode mode Only) 2679 }; 2680 uint32_t Value; 2681 } DW6; 2682 union 2683 { 2684 struct 2685 { 2686 uint32_t SegmentQindexDeltaEncodeModeOnly : __CODEGEN_BITFIELD( 0, 8) ; //!< Segment QIndex Delta (encode mode only) 2687 uint32_t Reserved233 : __CODEGEN_BITFIELD( 9, 15) ; //!< Reserved 2688 uint32_t SegmentLfLevelDeltaEncodeModeOnly : __CODEGEN_BITFIELD(16, 22) ; //!< Segment LF Level Delta (Encode mode Only) 2689 uint32_t Reserved247 : __CODEGEN_BITFIELD(23, 31) ; //!< Reserved 2690 }; 2691 uint32_t Value; 2692 } DW7; 2693 2694 //! \name Local enumerations 2695 2696 enum MEDIA_INSTRUCTION_COMMAND 2697 { 2698 MEDIA_INSTRUCTION_COMMAND_HCPVP9SEGMENTSTATE = 50, //!< No additional details 2699 }; 2700 2701 //! \brief MEDIA_INSTRUCTION_OPCODE 2702 //! \details 2703 //! Codec/Engine Name = HUC = Bh 2704 enum MEDIA_INSTRUCTION_OPCODE 2705 { 2706 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2707 }; 2708 2709 enum PIPELINE_TYPE 2710 { 2711 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2712 }; 2713 2714 enum COMMAND_TYPE 2715 { 2716 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2717 }; 2718 2719 //! \name Initializations 2720 2721 //! \brief Explicit member initialization function 2722 HCP_VP9_SEGMENT_STATE_CMD(); 2723 2724 static const size_t dwSize = 8; 2725 static const size_t byteSize = 32; 2726 }; 2727 2728 //! 2729 //! \brief HCP_FQM_STATE 2730 //! \details 2731 //! The HCP_FQM_STATE command loads the custom HEVC quantization tables into 2732 //! local RAM and may be issued up to 8 times: 4 scaling list per intra and 2733 //! inter. 2734 //! 2735 //! Driver is responsible for performing the Scaling List division. So, save 2736 //! the division HW cost in HW. The 1/x value is provided in 16-bit 2737 //! fixed-point precision as ((1<<17)/QM +1) >> 1. . 2738 //! 2739 //! Note: FQM is computed as (2^16)/QM. If QM=1, FQM=all 1's. 2740 //! 2741 //! To simplify the design, only a limited number of scaling lists are 2742 //! provided at the PAK interface: default two SizeID0 and two SizeID123 2743 //! (one set for inter and the other set for intra), and the encoder only 2744 //! allows custom entries for these four matrices. The DC value of SizeID2 2745 //! and SizeID3 will be provided. 2746 //! 2747 //! When the scaling_list_enable_flag is set to disable, the scaling matrix 2748 //! is still sent to the PAK, and with all entries programmed to the same 2749 //! value of 16. 2750 //! 2751 //! This is a picture level state command and is issued in encoding 2752 //! processes only. 2753 //! 2754 //! Dwords 2-33 form a table for the DCT coefficients, 2 16-bit 2755 //! coefficients/DWord. Size 4x4 for SizeID0, DWords 2-9. 2756 //! Size 8x8 for SizeID1/2/3, DWords 2-33. 2757 //! 2758 //! 2759 //! SizeID 0 (Table 4-13) 2760 //! 2761 struct HCP_FQM_STATE_CMD 2762 { 2763 union 2764 { 2765 struct 2766 { 2767 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2768 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2769 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2770 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2771 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2772 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2773 }; 2774 uint32_t Value; 2775 } DW0; 2776 union 2777 { 2778 struct 2779 { 2780 uint32_t IntraInter : __CODEGEN_BITFIELD( 0, 0) ; //!< INTRAINTER 2781 uint32_t Sizeid : __CODEGEN_BITFIELD( 1, 2) ; //!< SIZEID 2782 uint32_t ColorComponent : __CODEGEN_BITFIELD( 3, 4) ; //!< COLOR_COMPONENT 2783 uint32_t Reserved37 : __CODEGEN_BITFIELD( 5, 15) ; //!< Reserved 2784 uint32_t FqmDcValue1Dc : __CODEGEN_BITFIELD(16, 31) ; //!< FQM DC Value: (1/DC): 2785 }; 2786 uint32_t Value; 2787 } DW1; 2788 uint32_t Quantizermatrix[32]; //!< QuantizerMatrix 2789 2790 //! \name Local enumerations 2791 2792 enum MEDIA_INSTRUCTION_COMMAND 2793 { 2794 MEDIA_INSTRUCTION_COMMAND_HCPFQMSTATE = 5, //!< No additional details 2795 }; 2796 2797 //! \brief MEDIA_INSTRUCTION_OPCODE 2798 //! \details 2799 //! Codec/Engine Name = HCP = 7h 2800 enum MEDIA_INSTRUCTION_OPCODE 2801 { 2802 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2803 }; 2804 2805 enum PIPELINE_TYPE 2806 { 2807 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2808 }; 2809 2810 enum COMMAND_TYPE 2811 { 2812 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2813 }; 2814 2815 //! \brief INTRAINTER 2816 //! \details 2817 //! This field specifies the quant matrix intra or inter type. 2818 enum INTRAINTER 2819 { 2820 INTRAINTER_INTRA = 0, //!< No additional details 2821 INTRAINTER_INTER = 1, //!< No additional details 2822 }; 2823 2824 enum SIZEID 2825 { 2826 SIZEID_SIZEID04X4 = 0, //!< No additional details 2827 SIZEID_SIZEID1_2_3_8X8_16X16_32X32 = 1, //!< No additional details 2828 SIZEID_SIZEID2_FORDCVALUEIN16X16 = 2, //!< No additional details 2829 SIZEID_SIZEID3_FORDCVALUEIN32X32 = 3, //!< No additional details 2830 }; 2831 2832 //! \brief COLOR_COMPONENT 2833 //! \details 2834 //! <p>Luma and Chroma's share the same scaling list and DC value for the 2835 //! same SizeID.</p> 2836 enum COLOR_COMPONENT 2837 { 2838 COLOR_COMPONENT_LUMA = 0, //!< No additional details 2839 COLOR_COMPONENT_CHROMACB = 1, //!< No additional details 2840 COLOR_COMPONENT_CHROMACR = 2, //!< No additional details 2841 }; 2842 2843 //! \name Initializations 2844 2845 //! \brief Explicit member initialization function 2846 HCP_FQM_STATE_CMD(); 2847 2848 static const size_t dwSize = 34; 2849 static const size_t byteSize = 136; 2850 }; 2851 2852 //! 2853 //! \brief HCP_PAK_INSERT_OBJECT 2854 //! \details 2855 //! It is an encoder only command, operating at bitstream level, before and 2856 //! after SliceData compressed bitstream. It is setup by the header and tail 2857 //! present flags in the Slice State command. If these flags are set and no 2858 //! subsequent PAK_INSERT_OBJECT commands are issued, the pipeline will 2859 //! hang. 2860 //! 2861 //! The HCP_ PAK_ INSERT _OBJECT command supports both inline and indirect 2862 //! data payload, but only one can be active at any time. It is issued to 2863 //! insert a chunk of bits (payload) into the current compressed bitstream 2864 //! output buffer (specified in the HCP_PAK-BSE Object Base Address field of 2865 //! the HCP_IND_OBJ_BASE_ADDR_STATE command) starting at its current write 2866 //! pointer bit position. Hardware will keep track of this write pointer's 2867 //! byte position and the associated next bit insertion position index. 2868 //! 2869 //! It is a variable length command when the payload (data to be inserted) 2870 //! is presented as inline data within the command itself. The inline 2871 //! payload is a multiple of 32-bit (1 DW), as the data bus to the 2872 //! compressed bitstream output buffer is 32-bit wide. 2873 //! 2874 //! The payload data is required to be byte aligned on the left (first 2875 //! transmitted bit order) and may or may not be byte aligned on the right 2876 //! (last transmitted bits). The command will specify the bit offset of the 2877 //! last valid DW. Note that : Stitch Command is used if the beginning 2878 //! position of data is in bit position. When PAK Insert Command is used the 2879 //! beginning position must be in byte position. 2880 //! 2881 //! Multiple insertion commands can be issued back to back in a series. It 2882 //! is host software's responsibility to make sure their corresponding data 2883 //! will properly stitch together to form a valid bitstream. 2884 //! 2885 //! Internally, HCP hardware will keep track of the very last two bytes' 2886 //! (the very last byte can be a partial byte) values of the previous 2887 //! insertion. It is required that the next Insertion Object Command or the 2888 //! next PAK Object Command to perform the start code emulation sequence 2889 //! check and prevention 0x03 byte insertion with this end condition of the 2890 //! previous insertion. 2891 //! 2892 //! The payload data may have already been processed for start code 2893 //! emulation byte insertion, except the possibility of the last 2 bytes 2894 //! plus the very last partial byte (if any). Hence, when hardware 2895 //! performing the concatenation of multiple consecutive insertion commands, 2896 //! or concatenation of an insertion command and a PAK object command, it 2897 //! must check and perform the necessary start code emulation byte insert at 2898 //! the junction. 2899 //! 2900 //! Data to be inserted can be a valid NAL units or a partial NAL unit. It 2901 //! can be any encoded syntax elements bit data before the encoded Slice 2902 //! Data (PAK Object Command) of the current Slice - SPS NAL, PPS NAL, SEI 2903 //! NAL and Other Non-Slice NAL, Leading_Zero_8_bits (as many bytes as there 2904 //! is), Start Code , Slice Header. Any encoded syntax elements bit data 2905 //! after the encoded Slice Data (PAK Object Command) of the current Slice 2906 //! and prior to the next encoded Slice Data of the next Slice or prior to 2907 //! the end of the bitstream, whichever comes first Cabac_Zero_Word or 2908 //! Trailing_Zero_8bits (as many bytes as there is). 2909 //! 2910 //! Certain NAL unit has a minimum byte size requirement. As such the 2911 //! hardware will optionally (enabled by SLICE STATE Command) determines the 2912 //! number of CABAC_ZERO_WORD to be inserted to the end of the current NAL, 2913 //! based on the minimum byte size of a NAL and the actual bin count of the 2914 //! encoded Slice. Since prior to the CABAC_ZERO_WORD insertion, the RBSP or 2915 //! EBSP is already byte-aligned, so each CABAC_ZERO_WORD insertion is 2916 //! actually a 3-byte sequence 0x00 00 03. 2917 //! 2918 //! Context switch interrupt is not supported by this command. 2919 //! 2920 struct HCP_PAK_INSERT_OBJECT_CMD 2921 { 2922 union 2923 { 2924 struct 2925 { 2926 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< Dword Length 2927 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2928 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 2929 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 2930 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 2931 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2932 }; 2933 uint32_t Value; 2934 } DW0; 2935 union 2936 { 2937 struct 2938 { 2939 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 2940 uint32_t EndofsliceflagLastdstdatainsertcommandflag : __CODEGEN_BITFIELD( 1, 1) ; //!< EndOfSliceFlag - LastDstDataInsertCommandFlag 2941 uint32_t LastheaderflagLastsrcheaderdatainsertcommandflag : __CODEGEN_BITFIELD( 2, 2) ; //!< LastHeaderFlag - LastSrcHeaderDataInsertCommandFlag 2942 uint32_t EmulationflagEmulationbytebitsinsertenable : __CODEGEN_BITFIELD( 3, 3) ; //!< EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 2943 uint32_t SkipemulbytecntSkipEmulationByteCount : __CODEGEN_BITFIELD( 4, 7) ; //!< SkipEmulByteCnt - Skip Emulation Byte Count 2944 uint32_t DatabitsinlastdwSrcdataendingbitinclusion50 : __CODEGEN_BITFIELD( 8, 13) ; //!< DataBitsInLastDW - SrCDataEndingBitInclusion[5:0] 2945 uint32_t SliceHeaderIndicator : __CODEGEN_BITFIELD(14, 14) ; //!< Slice Header Indicator 2946 uint32_t Headerlengthexcludefrmsize : __CODEGEN_BITFIELD(15, 15) ; //!< HEADERLENGTHEXCLUDEFRMSIZE_ 2947 uint32_t DatabyteoffsetSrcdatastartingbyteoffset10 : __CODEGEN_BITFIELD(16, 17) ; //!< DataByteOffset - SrcDataStartingByteOffset[1:0] 2948 uint32_t Reserved50 : __CODEGEN_BITFIELD(18, 30) ; //!< Reserved 2949 uint32_t IndirectPayloadEnable : __CODEGEN_BITFIELD(31, 31) ; //!< INDIRECT_PAYLOAD_ENABLE 2950 }; 2951 uint32_t Value; 2952 } DW1; 2953 2954 //! \name Local enumerations 2955 2956 enum MEDIA_INSTRUCTION_COMMAND 2957 { 2958 MEDIA_INSTRUCTION_COMMAND_HCPPAKINSERTOBJECT = 34, //!< No additional details 2959 }; 2960 2961 //! \brief MEDIA_INSTRUCTION_OPCODE 2962 //! \details 2963 //! Codec/Engine Name = HCP = 7h 2964 enum MEDIA_INSTRUCTION_OPCODE 2965 { 2966 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 2967 }; 2968 2969 enum PIPELINE_TYPE 2970 { 2971 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 2972 }; 2973 2974 enum COMMAND_TYPE 2975 { 2976 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2977 }; 2978 2979 //! \brief EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 2980 //! \details 2981 //! Only valid for HEVC and reserved for VP9. 2982 enum EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE 2983 { 2984 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_STARTCODEPREFIX = 1, //!< Instruct the hardware to perform Start Code Prefix (0x 00 00 01/02/03/00) Search and Prevention Byte (0x 03) insertion on the insertion data of this command. It is required that hardware will handle a start code prefix crossing the boundary between. 2985 EMULATIONFLAG_EMULATIONBYTEBITSINSERTENABLE_INSERTIONCOMMAND = 2, //!< Insertion commands, or an insertion command followed by a PAK Object command. 2986 }; 2987 2988 //! \brief HEADERLENGTHEXCLUDEFRMSIZE_ 2989 //! \details 2990 //! <p>In case this flag is on, bits are NOT accumulated during current 2991 //! access unit coding neither for Cabac Zero Word insertion bits counting 2992 //! or for output in MMIO register 2993 //! HCP_BITSTREAM_BYTECOUNT_FRAME_NO_HEADER.</p> 2994 //! <p>When using HeaderLenghtExcludeFrmSize for header insertion, the 2995 //! software needs to make sure that data comes already with inserted start 2996 //! code emulation bytes. SW shouldn't set EmulationFlag bit ( Bit 3 of 2997 //! DWORD1 of HCP_PAK_INSERT_OBJECT).</p> 2998 //! <table border="1" cellpadding="0" cellspacing="0" style="width: 100%;" 2999 //! width="100%"> 3000 //! <tbody> 3001 //! <tr> 3002 //! <td> 3003 //! <p align="center"><b>Value</b></p></td> 3004 //! <td> 3005 //! <p align="center"><b style="text-align: 3006 //! -webkit-center;">Description</b></p></td> 3007 //! </tr> 3008 //! <tr> 3009 //! <td> 3010 //! <p>0</p></td> 3011 //! <td> 3012 //! <p>All bits accumulated</p></td> 3013 //! </tr> 3014 //! <tr> 3015 //! <td> 3016 //! <p>1</p></td> 3017 //! <td> 3018 //! <p>Bits during current call are not accumulated</p></td> 3019 //! </tr> 3020 //! </tbody> 3021 //! </table> 3022 //! 3023 //! <p></p> 3024 enum HEADERLENGTHEXCLUDEFRMSIZE_ 3025 { 3026 HEADERLENGTHEXCLUDEFRMSIZE_ALLBITSACCUMULATED = 0, //!< No additional details 3027 HEADERLENGTHEXCLUDEFRMSIZE_BITSDURINGCURRENTCALLARENOTACCUMULATED = 1, //!< No additional details 3028 }; 3029 3030 //! \brief INDIRECT_PAYLOAD_ENABLE 3031 //! \details 3032 //! <p>Only one of these two payload modes can be active at any time.</p> 3033 //! <p>When Slice Size Conformance is enable the Payload(header) must be 3034 //! inline only so this bit set to MBZ.</p> 3035 enum INDIRECT_PAYLOAD_ENABLE 3036 { 3037 INDIRECT_PAYLOAD_ENABLE_INLINEPAYLOADISUSED = 0, //!< No additional details 3038 INDIRECT_PAYLOAD_ENABLE_INDIRECTPAYLOADISUSED = 1, //!< No additional details 3039 }; 3040 3041 //! \name Initializations 3042 3043 //! \brief Explicit member initialization function 3044 HCP_PAK_INSERT_OBJECT_CMD(); 3045 3046 static const size_t dwSize = 2; 3047 static const size_t byteSize = 8; 3048 }; 3049 3050 //! 3051 //! \brief HCP_VP9_PIC_STATE 3052 //! \details 3053 //! 3054 //! 3055 struct HCP_VP9_PIC_STATE_CMD 3056 { 3057 union 3058 { 3059 struct 3060 { 3061 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3062 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3063 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3064 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3065 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3066 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3067 }; 3068 uint32_t Value; 3069 } DW0; 3070 union 3071 { 3072 struct 3073 { 3074 uint32_t FrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Frame Width In Pixels Minus 1 3075 uint32_t Reserved46 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3076 uint32_t FrameHeightInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Frame Height In Pixels Minus 1 3077 uint32_t Reserved62 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3078 }; 3079 uint32_t Value; 3080 } DW1; 3081 union 3082 { 3083 struct 3084 { 3085 uint32_t FrameType : __CODEGEN_BITFIELD( 0, 0) ; //!< FRAME_TYPE 3086 uint32_t AdaptProbabilitiesFlag : __CODEGEN_BITFIELD( 1, 1) ; //!< ADAPT_PROBABILITIES_FLAG 3087 uint32_t IntraonlyFlag : __CODEGEN_BITFIELD( 2, 2) ; //!< IntraOnly Flag 3088 uint32_t AllowHiPrecisionMv : __CODEGEN_BITFIELD( 3, 3) ; //!< ALLOW_HI_PRECISION_MV 3089 uint32_t McompFilterType : __CODEGEN_BITFIELD( 4, 6) ; //!< MCOMP_FILTER_TYPE 3090 uint32_t RefFrameSignBias02 : __CODEGEN_BITFIELD( 7, 9) ; //!< Ref Frame Sign Bias[0..2] 3091 uint32_t UsePrevInFindMvReferences : __CODEGEN_BITFIELD(10, 10) ; //!< Use Prev in Find MV References 3092 uint32_t HybridPredictionMode : __CODEGEN_BITFIELD(11, 11) ; //!< HYBRID_PREDICTION_MODE 3093 uint32_t SelectableTxMode : __CODEGEN_BITFIELD(12, 12) ; //!< SELECTABLE_TX_MODE 3094 uint32_t LastFrameType : __CODEGEN_BITFIELD(13, 13) ; //!< LAST_FRAME_TYPE 3095 uint32_t RefreshFrameContext : __CODEGEN_BITFIELD(14, 14) ; //!< REFRESH_FRAME_CONTEXT 3096 uint32_t ErrorResilientMode : __CODEGEN_BITFIELD(15, 15) ; //!< ERROR_RESILIENT_MODE 3097 uint32_t FrameParallelDecodingMode : __CODEGEN_BITFIELD(16, 16) ; //!< FRAME_PARALLEL_DECODING_MODE 3098 uint32_t FilterLevel : __CODEGEN_BITFIELD(17, 22) ; //!< Filter Level 3099 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(23, 25) ; //!< Sharpness Level 3100 uint32_t SegmentationEnabled : __CODEGEN_BITFIELD(26, 26) ; //!< SEGMENTATION_ENABLED 3101 uint32_t SegmentationUpdateMap : __CODEGEN_BITFIELD(27, 27) ; //!< SEGMENTATION_UPDATE_MAP 3102 uint32_t SegmentationTemporalUpdate : __CODEGEN_BITFIELD(28, 28) ; //!< SEGMENTATION_TEMPORAL_UPDATE 3103 uint32_t LosslessMode : __CODEGEN_BITFIELD(29, 29) ; //!< LOSSLESS_MODE 3104 uint32_t SegmentIdStreamoutEnable : __CODEGEN_BITFIELD(30, 30) ; //!< SEGMENT_ID_STREAMOUT_ENABLE 3105 uint32_t SegmentIdStreaminEnable : __CODEGEN_BITFIELD(31, 31) ; //!< SEGMENT_ID_STREAMIN_ENABLE 3106 }; 3107 uint32_t Value; 3108 } DW2; 3109 union 3110 { 3111 struct 3112 { 3113 uint32_t Log2TileColumn : __CODEGEN_BITFIELD( 0, 3) ; //!< LOG2_TILE_COLUMN 3114 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 3115 uint32_t Log2TileRow : __CODEGEN_BITFIELD( 8, 9) ; //!< LOG2_TILE_ROW 3116 uint32_t Reserved106 : __CODEGEN_BITFIELD(10, 20) ; //!< Reserved 3117 uint32_t SseEnable : __CODEGEN_BITFIELD(21, 21) ; //!< SSE Enable 3118 uint32_t ChromaSamplingFormat : __CODEGEN_BITFIELD(22, 23) ; //!< CHROMA_SAMPLING_FORMAT 3119 uint32_t Bitdepthminus8 : __CODEGEN_BITFIELD(24, 27) ; //!< BITDEPTHMINUS8 3120 uint32_t ProfileLevel : __CODEGEN_BITFIELD(28, 31) ; //!< PROFILE_LEVEL 3121 }; 3122 uint32_t Value; 3123 } DW3; 3124 union 3125 { 3126 struct 3127 { 3128 uint32_t VerticalScaleFactorForLast : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for LAST 3129 uint32_t HorizontalScaleFactorForLast : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for LAST 3130 }; 3131 uint32_t Value; 3132 } DW4; 3133 union 3134 { 3135 struct 3136 { 3137 uint32_t VerticalScaleFactorForGolden : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for GOLDEN 3138 uint32_t HorizontalScaleFactorForGolden : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for GOLDEN 3139 }; 3140 uint32_t Value; 3141 } DW5; 3142 union 3143 { 3144 struct 3145 { 3146 uint32_t VerticalScaleFactorForAltref : __CODEGEN_BITFIELD( 0, 15) ; //!< Vertical Scale Factor for ALTREF 3147 uint32_t HorizontalScaleFactorForAltref : __CODEGEN_BITFIELD(16, 31) ; //!< Horizontal Scale Factor for ALTREF 3148 }; 3149 uint32_t Value; 3150 } DW6; 3151 union 3152 { 3153 struct 3154 { 3155 uint32_t LastFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Last Frame Width In Pixels Minus 1 3156 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3157 uint32_t LastFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Last Frame Hieght In Pixels Minus 1 3158 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3159 }; 3160 uint32_t Value; 3161 } DW7; 3162 union 3163 { 3164 struct 3165 { 3166 uint32_t GoldenFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Golden Frame Width In Pixels Minus 1 3167 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3168 uint32_t GoldenFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Golden Frame Hieght In Pixels Minus 1 3169 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3170 }; 3171 uint32_t Value; 3172 } DW8; 3173 union 3174 { 3175 struct 3176 { 3177 uint32_t AltrefFrameWidthInPixelsMinus1 : __CODEGEN_BITFIELD( 0, 13) ; //!< Altref Frame Width In Pixels Minus 1 3178 uint32_t Reserved302 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 3179 uint32_t AltrefFrameHieghtInPixelsMinus1 : __CODEGEN_BITFIELD(16, 29) ; //!< Altref Frame Hieght In Pixels Minus 1 3180 uint32_t Reserved318 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 3181 }; 3182 uint32_t Value; 3183 } DW9; 3184 union 3185 { 3186 struct 3187 { 3188 uint32_t UncompressedHeaderLengthInBytes70 : __CODEGEN_BITFIELD( 0, 7) ; //!< Uncompressed Header Length in Bytes [7:0] 3189 uint32_t Reserved328 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 3190 uint32_t FirstPartitionSizeInBytes150 : __CODEGEN_BITFIELD(16, 31) ; //!< First Partition Size in Bytes [15:0] 3191 }; 3192 uint32_t Value; 3193 } DW10; 3194 union 3195 { 3196 struct 3197 { 3198 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 3199 uint32_t MotionCompScalingEnableBit : __CODEGEN_BITFIELD( 1, 1) ; //!< MOTION_COMP_SCALING_ENABLE_BIT 3200 uint32_t Reserved354 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 3201 }; 3202 uint32_t Value; 3203 } DW11; 3204 union 3205 { 3206 struct 3207 { 3208 uint32_t Reserved384 ; //!< Reserved 3209 }; 3210 uint32_t Value; 3211 } DW12; 3212 union 3213 { 3214 struct 3215 { 3216 uint32_t CompressedHeaderBinCount : __CODEGEN_BITFIELD( 0, 15) ; //!< Compressed header BIN count 3217 uint32_t BaseQIndexSameAsLumaAc : __CODEGEN_BITFIELD(16, 23) ; //!< Base Q Index (Same as Luma AC) 3218 uint32_t TailInsertionEnable : __CODEGEN_BITFIELD(24, 24) ; //!< Tail Insertion Enable 3219 uint32_t HeaderInsertionEnable : __CODEGEN_BITFIELD(25, 25) ; //!< Header Insertion Enable 3220 uint32_t Reserved442 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 3221 }; 3222 uint32_t Value; 3223 } DW13; 3224 union 3225 { 3226 struct 3227 { 3228 uint32_t ChromaacQindexdelta : __CODEGEN_BITFIELD( 0, 4) ; //!< ChromaAC_QindexDelta 3229 uint32_t Reserved453 : __CODEGEN_BITFIELD( 5, 7) ; //!< Reserved 3230 uint32_t ChromadcQindexdelta : __CODEGEN_BITFIELD( 8, 12) ; //!< ChromaDC_QindexDelta 3231 uint32_t Reserved461 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 3232 uint32_t LumaDcQIndexDelta : __CODEGEN_BITFIELD(16, 20) ; //!< Luma DC Q Index Delta 3233 uint32_t Reserved469 : __CODEGEN_BITFIELD(21, 31) ; //!< Reserved 3234 }; 3235 uint32_t Value; 3236 } DW14; 3237 union 3238 { 3239 struct 3240 { 3241 uint32_t LfRefDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF_ref_delta0 3242 uint32_t Reserved487 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3243 uint32_t LfRefDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF_ref_delta1 3244 uint32_t Reserved495 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 3245 uint32_t LfRefDelta2 : __CODEGEN_BITFIELD(16, 22) ; //!< LF_ref_delta2 3246 uint32_t Reserved503 : __CODEGEN_BITFIELD(23, 23) ; //!< Reserved 3247 uint32_t LfRefDelta3 : __CODEGEN_BITFIELD(24, 30) ; //!< LF_ref_delta3 3248 uint32_t Reserved511 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 3249 }; 3250 uint32_t Value; 3251 } DW15; 3252 union 3253 { 3254 struct 3255 { 3256 uint32_t LfModeDelta0 : __CODEGEN_BITFIELD( 0, 6) ; //!< LF Mode Delta 0 3257 uint32_t Reserved519 : __CODEGEN_BITFIELD( 7, 7) ; //!< Reserved 3258 uint32_t LfModeDelta1 : __CODEGEN_BITFIELD( 8, 14) ; //!< LF Mode Delta 1 3259 uint32_t Reserved527 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 3260 }; 3261 uint32_t Value; 3262 } DW16; 3263 union 3264 { 3265 struct 3266 { 3267 uint32_t Bitoffsetforlfrefdelta : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForLFRefDelta 3268 uint32_t Bitoffsetforlfmodedelta : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFModeDelta 3269 }; 3270 uint32_t Value; 3271 } DW17; 3272 union 3273 { 3274 struct 3275 { 3276 uint32_t Bitoffsetforqindex : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForQindex 3277 uint32_t Bitoffsetforlflevel : __CODEGEN_BITFIELD(16, 31) ; //!< BitOffsetForLFLevel 3278 }; 3279 uint32_t Value; 3280 } DW18; 3281 union 3282 { 3283 struct 3284 { 3285 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 15) ; //!< Reserved 3286 uint32_t Nonfirstpassflag : __CODEGEN_BITFIELD(16, 16) ; //!< NONFIRSTPASSFLAG 3287 uint32_t VdencPakOnlyPass : __CODEGEN_BITFIELD(17, 17) ; //!< VDENC PAK_ONLY PASS 3288 uint32_t Reserved626 : __CODEGEN_BITFIELD(18, 24) ; //!< Reserved 3289 uint32_t FrameszoverstatusenFramebitratemaxreportmask : __CODEGEN_BITFIELD(25, 25) ; //!< FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3290 uint32_t FrameszunderstatusenFramebitrateminreportmask : __CODEGEN_BITFIELD(26, 26) ; //!< FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3291 uint32_t Reserved635 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3292 }; 3293 uint32_t Value; 3294 } DW19; 3295 union 3296 { 3297 struct 3298 { 3299 uint32_t Framebitratemax : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMax 3300 uint32_t Reserved654 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3301 uint32_t Framebitratemaxunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMAXUNIT 3302 }; 3303 uint32_t Value; 3304 } DW20; 3305 union 3306 { 3307 struct 3308 { 3309 uint32_t Framebitratemin : __CODEGEN_BITFIELD( 0, 13) ; //!< FrameBitRateMin 3310 uint32_t Reserved686 : __CODEGEN_BITFIELD(14, 30) ; //!< Reserved 3311 uint32_t Framebitrateminunit : __CODEGEN_BITFIELD(31, 31) ; //!< FRAMEBITRATEMINUNIT 3312 }; 3313 uint32_t Value; 3314 } DW21; 3315 union 3316 { 3317 struct 3318 { 3319 uint64_t Framedeltaqindexmax ; //!< FrameDeltaQindexMax 3320 }; 3321 uint32_t Value[2]; 3322 } DW22_23; 3323 union 3324 { 3325 struct 3326 { 3327 uint32_t Framedeltaqindexmin ; //!< FrameDeltaQindexMin 3328 }; 3329 uint32_t Value; 3330 } DW24; 3331 union 3332 { 3333 struct 3334 { 3335 uint64_t Framedeltalfmax ; //!< FrameDeltaLFMax 3336 }; 3337 uint32_t Value[2]; 3338 } DW25_26; 3339 union 3340 { 3341 struct 3342 { 3343 uint32_t Framedeltalfmin ; //!< FrameDeltaLFMin 3344 }; 3345 uint32_t Value; 3346 } DW27; 3347 union 3348 { 3349 struct 3350 { 3351 uint64_t Framedeltaqindexlfmaxrange ; //!< FrameDeltaQindexLFMaxRange 3352 }; 3353 uint32_t Value[2]; 3354 } DW28_29; 3355 union 3356 { 3357 struct 3358 { 3359 uint32_t Framedeltaqindexlfminrange ; //!< FrameDeltaQindexLFMinRange 3360 }; 3361 uint32_t Value; 3362 } DW30; 3363 union 3364 { 3365 struct 3366 { 3367 uint32_t Minframsize : __CODEGEN_BITFIELD( 0, 15) ; //!< MinFramSize 3368 uint32_t Reserved1008 : __CODEGEN_BITFIELD(16, 29) ; //!< Reserved 3369 uint32_t Minframesizeunits : __CODEGEN_BITFIELD(30, 31) ; //!< MINFRAMESIZEUNITS 3370 }; 3371 uint32_t Value; 3372 } DW31; 3373 union 3374 { 3375 struct 3376 { 3377 uint32_t Bitoffsetforfirstpartitionsize : __CODEGEN_BITFIELD( 0, 15) ; //!< BitOffsetForFirstPartitionSize 3378 uint32_t Reserved1040 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 3379 }; 3380 uint32_t Value; 3381 } DW32; 3382 union 3383 { 3384 struct 3385 { 3386 uint32_t Class0SseThreshold0 : __CODEGEN_BITFIELD( 0, 15) ; //!< Class0_SSE_Threshold0 3387 uint32_t Class0SseThreshold1 : __CODEGEN_BITFIELD(16, 31) ; //!< Class0_SSE_Threshold1 3388 }; 3389 uint32_t Value; 3390 } DW33; 3391 uint32_t SseThresholdsForClass18[8]; //!< SSE thresholds for Class1-8 3392 3393 //! \name Local enumerations 3394 3395 enum MEDIA_INSTRUCTION_COMMAND 3396 { 3397 MEDIA_INSTRUCTION_COMMAND_HCPVP9PICSTATE = 48, //!< No additional details 3398 }; 3399 3400 //! \brief MEDIA_INSTRUCTION_OPCODE 3401 //! \details 3402 //! Codec/Engine Name = HUC = Bh 3403 enum MEDIA_INSTRUCTION_OPCODE 3404 { 3405 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3406 }; 3407 3408 enum PIPELINE_TYPE 3409 { 3410 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3411 }; 3412 3413 enum COMMAND_TYPE 3414 { 3415 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3416 }; 3417 3418 //! \brief FRAME_TYPE 3419 //! \details 3420 //! Specifies the VP9 frame type 3421 enum FRAME_TYPE 3422 { 3423 FRAME_TYPE_KEYFRAME = 0, //!< No additional details 3424 FRAME_TYPE_INTERFRAME = 1, //!< No additional details 3425 }; 3426 3427 //! \brief ADAPT_PROBABILITIES_FLAG 3428 //! \details 3429 //! Indicates that the probabilities used to decode this frame should be 3430 //! adapted 3431 enum ADAPT_PROBABILITIES_FLAG 3432 { 3433 ADAPT_PROBABILITIES_FLAG_0DONOTADAPT_ERRORRESILIENTORFRAMEPARALLELMODEARESET = 0, //!< No additional details 3434 ADAPT_PROBABILITIES_FLAG_1ADAPT_NOTERRORRESILIENTANDNOTFRAMEPARALLELMODE = 1, //!< No additional details 3435 }; 3436 3437 //! \brief ALLOW_HI_PRECISION_MV 3438 //! \details 3439 //! Indicate high precision mode for Motion Vector prediction 3440 enum ALLOW_HI_PRECISION_MV 3441 { 3442 ALLOW_HI_PRECISION_MV_NORMALMODE = 0, //!< No additional details 3443 ALLOW_HI_PRECISION_MV_HIGHPRECISIONMODE = 1, //!< No additional details 3444 }; 3445 3446 //! \brief MCOMP_FILTER_TYPE 3447 //! \details 3448 //! Indicate Motion Compensation Filter type. 3449 enum MCOMP_FILTER_TYPE 3450 { 3451 MCOMP_FILTER_TYPE_EIGHT_TAP = 0, //!< No additional details 3452 MCOMP_FILTER_TYPE_EIGHT_TAP_SMOOTH = 1, //!< No additional details 3453 MCOMP_FILTER_TYPE_EIGHT_TAP_SHARP = 2, //!< No additional details 3454 MCOMP_FILTER_TYPE_BILINEAR = 3, //!< No additional details 3455 MCOMP_FILTER_TYPE_SWITCHABLE = 4, //!< No additional details 3456 }; 3457 3458 //! \brief HYBRID_PREDICTION_MODE 3459 //! \details 3460 //! Indicates if comp_pred_mode is hybrid 3461 enum HYBRID_PREDICTION_MODE 3462 { 3463 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERDOESNOTPACKCOMPPREDMODEINTERPREDCOMPINPAKOBJINTOBITSTREAM = 0, //!< No additional details 3464 HYBRID_PREDICTION_MODE_COMPPREDICTIONMODEHYBRID_ENCODERPACKSCOMPPREDMODEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 1, //!< No additional details 3465 }; 3466 3467 //! \brief SELECTABLE_TX_MODE 3468 //! \details 3469 //! Indicates if tx_mode is selectable 3470 enum SELECTABLE_TX_MODE 3471 { 3472 SELECTABLE_TX_MODE_ENCODERDOESNOTPACKTUSIZEINTOBITSTREAMTHISHELPSREDUCEBITSTREAMSIZEFURTHER = 0, //!< No additional details 3473 SELECTABLE_TX_MODE_ENCODERPACKSTUSIZEINTOBITSTREAM = 1, //!< No additional details 3474 }; 3475 3476 //! \brief LAST_FRAME_TYPE 3477 //! \details 3478 //! <p>It indicates the frame type of previous frame (Key or Non-Key 3479 //! Frame)</p> 3480 enum LAST_FRAME_TYPE 3481 { 3482 LAST_FRAME_TYPE_KEYFRAME = 0, //!< No additional details 3483 LAST_FRAME_TYPE_NONKEYFRAME = 1, //!< No additional details 3484 }; 3485 3486 //! \brief REFRESH_FRAME_CONTEXT 3487 //! \details 3488 //! <p>Indicates if Frame Context should be refresh. This bit should come 3489 //! from Uncompressed header</p> 3490 enum REFRESH_FRAME_CONTEXT 3491 { 3492 REFRESH_FRAME_CONTEXT_DISABLE = 0, //!< No additional details 3493 REFRESH_FRAME_CONTEXT_ENABLE = 1, //!< No additional details 3494 }; 3495 3496 //! \brief ERROR_RESILIENT_MODE 3497 //! \details 3498 //! <p>Indicates if error resilient mode is enabled. This bit should come 3499 //! from Uncompressed header.When error resilient is 1, Frame Parallel 3500 //! Decoding Mode will be 1, and Refresh Frame Context will be 0.When error 3501 //! resilient is 0, Frame Parallel Decoding Mode and Refresh Frame Context 3502 //! read from bit stream.Together with Frame Parallel Decoding mode, they 3503 //! decide the value of AdaptProbabilityFlag.</p> 3504 enum ERROR_RESILIENT_MODE 3505 { 3506 ERROR_RESILIENT_MODE_DISABLE = 0, //!< No additional details 3507 ERROR_RESILIENT_MODE_ENABLE = 1, //!< No additional details 3508 }; 3509 3510 //! \brief FRAME_PARALLEL_DECODING_MODE 3511 //! \details 3512 //! <p>Indicates if parallel decoding mode is enabled. This bit should come 3513 //! from Uncompressed header. Together with Error Resilient mode, they 3514 //! decide the value of AdaptProbabilityFlag.</p> 3515 enum FRAME_PARALLEL_DECODING_MODE 3516 { 3517 FRAME_PARALLEL_DECODING_MODE_DISABLE = 0, //!< No additional details 3518 FRAME_PARALLEL_DECODING_MODE_ENABLE = 1, //!< No additional details 3519 }; 3520 3521 //! \brief SEGMENTATION_ENABLED 3522 //! \details 3523 //! Indicate if segementation is enabled or not 3524 enum SEGMENTATION_ENABLED 3525 { 3526 SEGMENTATION_ENABLED_ALLBLOCKSAREIMPLIEDTOBELONGTOSEGMENT0 = 0, //!< No additional details 3527 SEGMENTATION_ENABLED_SEGIDDETERMINATIONDEPENDSONSEGMENTATIONUPDATEMAPSETTING = 1, //!< No additional details 3528 }; 3529 3530 //! \brief SEGMENTATION_UPDATE_MAP 3531 //! \details 3532 //! Indicates how hardware determines segmentation ID 3533 enum SEGMENTATION_UPDATE_MAP 3534 { 3535 SEGMENTATION_UPDATE_MAP_UNNAMED0 = 0, //!< Intra block: segment ID is zero Inter block: get segment ID from previous frame (streamIN) 3536 SEGMENTATION_UPDATE_MAP_UNNAMED1 = 1, //!< Intra block: decode segment ID from bitstream. Inter block: determins from segmentation_temporal_update setting 3537 }; 3538 3539 //! \brief SEGMENTATION_TEMPORAL_UPDATE 3540 //! \details 3541 //! Indicates whether segID is decoding from bitstream or predicted from 3542 //! previous frame. 3543 enum SEGMENTATION_TEMPORAL_UPDATE 3544 { 3545 SEGMENTATION_TEMPORAL_UPDATE_DECODESEGIDFROMBITSTREAM = 0, //!< No additional details 3546 SEGMENTATION_TEMPORAL_UPDATE_GETSEGIDEITHERFROMBITSTREAMORFROMPREVIOUSFRAME = 1, //!< No additional details 3547 }; 3548 3549 //! \brief LOSSLESS_MODE 3550 //! \details 3551 //! This bitSet to indicate lossless coding mode. 3552 enum LOSSLESS_MODE 3553 { 3554 LOSSLESS_MODE_NORMALMODE = 0, //!< No additional details 3555 LOSSLESS_MODE_LOLESSMODE = 1, //!< No additional details 3556 }; 3557 3558 //! \brief SEGMENT_ID_STREAMOUT_ENABLE 3559 //! \details 3560 //! Indicates SegmentID of current frame needs to be streamOut for next 3561 //! frame 3562 enum SEGMENT_ID_STREAMOUT_ENABLE 3563 { 3564 SEGMENT_ID_STREAMOUT_ENABLE_DISABLE = 0, //!< No additional details 3565 SEGMENT_ID_STREAMOUT_ENABLE_ENABLE = 1, //!< No additional details 3566 }; 3567 3568 //! \brief SEGMENT_ID_STREAMIN_ENABLE 3569 //! \details 3570 //! Indicates SegmentID from previous frame needs to be streamIn for Segment 3571 //! ID prediction 3572 enum SEGMENT_ID_STREAMIN_ENABLE 3573 { 3574 SEGMENT_ID_STREAMIN_ENABLE_DISABLE = 0, //!< No additional details 3575 SEGMENT_ID_STREAMIN_ENABLE_ENABLE = 1, //!< No additional details 3576 }; 3577 3578 //! \brief LOG2_TILE_COLUMN 3579 //! \details 3580 //! This indicates the number of tile rows (log2). 3581 enum LOG2_TILE_COLUMN 3582 { 3583 LOG2_TILE_COLUMN_1TILECOLUMN = 0, //!< No additional details 3584 LOG2_TILE_COLUMN_2TILECOLUMN = 1, //!< No additional details 3585 LOG2_TILE_COLUMN_4TILECOLUMN = 2, //!< No additional details 3586 LOG2_TILE_COLUMN_8TILECOLUMN = 3, //!< No additional details 3587 LOG2_TILE_COLUMN_16TILECOLUMN = 4, //!< No additional details 3588 LOG2_TILE_COLUMN_32TILECOLUMN = 5, //!< No additional details 3589 LOG2_TILE_COLUMN_64TILECOLUMN = 6, //!< No additional details 3590 }; 3591 3592 //! \brief LOG2_TILE_ROW 3593 //! \details 3594 //! This indicates the number of tile rows (log2). 3595 enum LOG2_TILE_ROW 3596 { 3597 LOG2_TILE_ROW_1TILEROW = 0, //!< No additional details 3598 LOG2_TILE_ROW_2TILEROW = 1, //!< No additional details 3599 LOG2_TILE_ROW_4TILEROW = 2, //!< No additional details 3600 }; 3601 3602 //! \brief CHROMA_SAMPLING_FORMAT 3603 //! \details 3604 //! This indicates the chroma sampling format of the bitstream 3605 enum CHROMA_SAMPLING_FORMAT 3606 { 3607 CHROMA_SAMPLING_FORMAT_FORMAT420 = 0, //!< No additional details 3608 CHROMA_SAMPLING_FORMAT_FORMAT444 = 2, //!< No additional details 3609 }; 3610 3611 //! \brief BITDEPTHMINUS8 3612 //! \details 3613 //! This indicates the bitdepth (minus 8) of the pixels 3614 enum BITDEPTHMINUS8 3615 { 3616 BITDEPTHMINUS8_BITDEPTH8 = 0, //!< No additional details 3617 BITDEPTHMINUS8_BITDEPTH10 = 2, //!< No additional details 3618 BITDEPTHMINUS8_BITDEPTH12 = 4, //!< No additional details 3619 }; 3620 3621 //! \brief PROFILE_LEVEL 3622 //! \details 3623 //! This indicates VP9 Profile level from bitstream 3624 enum PROFILE_LEVEL 3625 { 3626 PROFILE_LEVEL_PROFILE0 = 0, //!< Profile 0 only supports 8 bit 420 only 3627 PROFILE_LEVEL_PROFILE1 = 1, //!< Profile 1 only supports 8 bit 444 only 3628 PROFILE_LEVEL_PROFILE2 = 2, //!< Profile 2 only supports 10 bits 420 only 3629 PROFILE_LEVEL_PROFILE3 = 3, //!< Profile 3 only supports 10-bit 444 only 3630 }; 3631 3632 //! \brief MOTION_COMP_SCALING_ENABLE_BIT 3633 //! \details 3634 //! This bit must be set to "1" 3635 enum MOTION_COMP_SCALING_ENABLE_BIT 3636 { 3637 MOTION_COMP_SCALING_ENABLE_BIT_ENABLE = 1, //!< This enables Motion Comp Scaling 3638 }; 3639 3640 //! \brief NONFIRSTPASSFLAG 3641 //! \details 3642 //! This signals the current pass is not the first pass. It will imply 3643 //! designate HW behavior. 3644 enum NONFIRSTPASSFLAG 3645 { 3646 NONFIRSTPASSFLAG_DISABLE = 0, //!< If it is initial-Pass, this bit is set to 0. 3647 NONFIRSTPASSFLAG_ENABLE = 1, //!< For subsequent passes, this bit is set to 1. 3648 }; 3649 3650 //! \brief FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3651 //! \details 3652 //! This is a mask bit controlling if the condition of frame level bit count 3653 //! exceeds FrameBitRateMax. 3654 enum FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK 3655 { 3656 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_DISABLE = 0, //!< Do not update bit 1 of HCP_VP9_IMAGE_STATUS control register. 3657 FRAMESZOVERSTATUSEN_FRAMEBITRATEMAXREPORTMASK_ENABLE = 1, //!< Set bit 1 of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is greater than or equal to Frame Bit Rate Maximum limit. 3658 }; 3659 3660 //! \brief FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3661 //! \details 3662 //! This is a mask bit controlling if the condition of frame level bit count 3663 //! is less than FrameBitRateMin. 3664 enum FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK 3665 { 3666 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_DISABLE = 0, //!< Do not update bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register. 3667 FRAMESZUNDERSTATUSEN_FRAMEBITRATEMINREPORTMASK_ENABLE = 1, //!< Set bit 2 (Frame Bit Count Violate -- under run) of HCP_VP9_IMAGE_STATUS control register if the total frame level bit counter is less than or equal to Frame Bit Rate Minimum limit. 3668 }; 3669 3670 //! \brief FRAMEBITRATEMAXUNIT 3671 //! \details 3672 //! This field is the Frame Bitrate Maximum Limit Units. 3673 enum FRAMEBITRATEMAXUNIT 3674 { 3675 FRAMEBITRATEMAXUNIT_BYTE = 0, //!< 32byte unit 3676 FRAMEBITRATEMAXUNIT_KILOBYTE = 1, //!< 4Kbyte unit 3677 }; 3678 3679 //! \brief FRAMEBITRATEMINUNIT 3680 //! \details 3681 //! This field is the Frame Bitrate Maximum Limit Units. 3682 enum FRAMEBITRATEMINUNIT 3683 { 3684 FRAMEBITRATEMINUNIT_BYTE = 0, //!< 32byte unit 3685 FRAMEBITRATEMINUNIT_KILOBYTE = 1, //!< 4Kbyte unit 3686 }; 3687 3688 //! \brief MINFRAMESIZEUNITS 3689 //! \details 3690 //! This field is the Minimum Frame Size Units 3691 enum MINFRAMESIZEUNITS 3692 { 3693 MINFRAMESIZEUNITS_4KB = 0, //!< Minimum Frame Size is in 4Kbytes. 3694 MINFRAMESIZEUNITS_16KB = 1, //!< Minimum Frame Size is in 4Kbytes. 3695 MINFRAMESIZEUNITS_COMAPTIBILITYMODE = 2, //!< No additional details 3696 MINFRAMESIZEUNITS_6BYTES = 3, //!< No additional details 3697 }; 3698 3699 //! \name Initializations 3700 3701 //! \brief Explicit member initialization function 3702 HCP_VP9_PIC_STATE_CMD(); 3703 3704 static const size_t dwSize = 42; 3705 static const size_t byteSize = 168; 3706 }; 3707 3708 //! 3709 //! \brief HEVC_VP9_RDOQ_LAMBDA_FIELDS 3710 //! \details 3711 //! 3712 //! 3713 struct HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD 3714 { 3715 union 3716 { 3717 struct 3718 { 3719 uint32_t Lambdavalue0 : __CODEGEN_BITFIELD( 0, 15) ; //!< LambdaValue0 3720 uint32_t Lambdavalue1 : __CODEGEN_BITFIELD(16, 31) ; //!< LambdaValue1 3721 }; 3722 uint32_t Value; 3723 } DW0; 3724 3725 //! \name Local enumerations 3726 3727 //! \name Initializations 3728 3729 //! \brief Explicit member initialization function 3730 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD(); 3731 3732 static const size_t dwSize = 1; 3733 static const size_t byteSize = 4; 3734 }; 3735 3736 //! 3737 //! \brief HEVC_VP9_RDOQ_STATE 3738 //! \details 3739 //! 3740 //! 3741 struct HEVC_VP9_RDOQ_STATE_CMD 3742 { 3743 union 3744 { 3745 struct 3746 { 3747 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3748 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3749 uint32_t Subopb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPB 3750 uint32_t Subopa : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPA 3751 uint32_t Opcode : __CODEGEN_BITFIELD(23, 26) ; //!< OPCODE 3752 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 3753 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3754 }; 3755 uint32_t Value; 3756 } DW0; 3757 union 3758 { 3759 struct 3760 { 3761 uint32_t Reserved32 : __CODEGEN_BITFIELD( 0, 29) ; //!< Reserved 3762 uint32_t DisableHtqPerformanceFix1 : __CODEGEN_BITFIELD(30, 30) ; //!< Disable HTQ performance fix1 3763 uint32_t DisableHtqPerformanceFix0 : __CODEGEN_BITFIELD(31, 31) ; //!< Disable HTQ performance fix0 3764 }; 3765 uint32_t Value; 3766 } DW1; 3767 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intralumalambda[32]; //!< DW2..33, IntraLumaLambda 3768 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Intrachromalambda[32]; //!< DW34..65, IntraChromaLambda 3769 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interlumalambda[32]; //!< DW66..97, InterLumaLambda 3770 HEVC_VP9_RDOQ_LAMBDA_FIELDS_CMD Interchromalambda[32]; //!< DW98..129, InterChromaLambda 3771 3772 //! \name Local enumerations 3773 3774 enum SUBOPB 3775 { 3776 SUBOPB_UNNAMED8 = 8, //!< No additional details 3777 }; 3778 3779 enum SUBOPA 3780 { 3781 SUBOPA_UNNAMED0 = 0, //!< No additional details 3782 }; 3783 3784 //! \brief OPCODE 3785 //! \details 3786 //! Codec/Engine Name = HCP = 7h 3787 enum OPCODE 3788 { 3789 OPCODE_UNNAMED7 = 7, //!< No additional details 3790 }; 3791 3792 //! \brief PIPELINE 3793 //! \details 3794 //! MFX_COMMON 3795 enum PIPELINE 3796 { 3797 PIPELINE_UNNAMED2 = 2, //!< No additional details 3798 }; 3799 3800 //! \brief COMMAND_TYPE 3801 //! \details 3802 //! PARALLEL_VIDEO_PIPE 3803 enum COMMAND_TYPE 3804 { 3805 COMMAND_TYPE_UNNAMED3 = 3, //!< No additional details 3806 }; 3807 3808 //! \name Initializations 3809 3810 //! \brief Explicit member initialization function 3811 HEVC_VP9_RDOQ_STATE_CMD(); 3812 3813 static const size_t dwSize = 130; 3814 static const size_t byteSize = 520; 3815 }; 3816 3817 //! 3818 //! \brief HCP_TILE_CODING 3819 //! \details 3820 //! This command is used for both HEVC and VP9 codecs 3821 //! 3822 struct HCP_TILE_CODING_CMD 3823 { 3824 union 3825 { 3826 struct 3827 { 3828 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 3829 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 3830 uint32_t MediaInstructionCommand : __CODEGEN_BITFIELD(16, 22) ; //!< MEDIA_INSTRUCTION_COMMAND 3831 uint32_t MediaInstructionOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_INSTRUCTION_OPCODE 3832 uint32_t PipelineType : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE_TYPE 3833 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 3834 }; 3835 uint32_t Value; 3836 } DW0; 3837 union 3838 { 3839 struct 3840 { 3841 uint32_t NumberOfActiveBePipes : __CODEGEN_BITFIELD( 0, 7) ; //!< Number of Active BE Pipes 3842 uint32_t Reserved40 : __CODEGEN_BITFIELD( 8, 8) ; //!< Reserved 3843 uint32_t TileColumnStoreSelect : __CODEGEN_BITFIELD( 9, 9) ; //!< Tile Column store Select 3844 uint32_t Reserved42 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved MBZ 3845 uint32_t NumOfTileColumnsInAFrame : __CODEGEN_BITFIELD(16, 31) ; //!< Num of Tile columns in a Frame 3846 }; 3847 uint32_t Value; 3848 } DW1; 3849 union 3850 { 3851 struct 3852 { 3853 uint32_t TileColumnPosition : __CODEGEN_BITFIELD( 0, 9) ; //!< Tile Column Position 3854 uint32_t NonFirstPassTile : __CODEGEN_BITFIELD(10, 10) ; //!< Non First Pass Tile 3855 uint32_t Reserved75 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 3856 uint32_t TileRowPosition : __CODEGEN_BITFIELD(16, 25) ; //!< Tile Row Position 3857 uint32_t Reserved90 : __CODEGEN_BITFIELD(26, 30) ; //!< Reserved 3858 uint32_t Islasttileofcolumn : __CODEGEN_BITFIELD(31, 31) ; //!< IsLastTileOfColumn 3859 }; 3860 uint32_t Value; 3861 } DW2; 3862 union 3863 { 3864 struct 3865 { 3866 uint32_t Tileheightinmincbminus1 : __CODEGEN_BITFIELD( 0, 10) ; //!< TileHeightInMinCbMinus1 3867 uint32_t Reserved107 : __CODEGEN_BITFIELD(11, 15) ; //!< Reserved 3868 uint32_t Tilewidthinmincbminus1 : __CODEGEN_BITFIELD(16, 26) ; //!< TileWidthInMinCbMinus1 3869 uint32_t Reserved123 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 3870 }; 3871 uint32_t Value; 3872 } DW3; 3873 union 3874 { 3875 struct 3876 { 3877 uint32_t Reserved128 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3878 uint32_t BitstreamByteOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Bitstream Byte Offset 3879 }; 3880 uint32_t Value; 3881 } DW4; 3882 union 3883 { 3884 struct 3885 { 3886 uint32_t Reserved160 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3887 uint32_t PakFrameStatisticsOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< PAK Frame Statistics Offset 3888 }; 3889 uint32_t Value; 3890 } DW5; 3891 union 3892 { 3893 struct 3894 { 3895 uint32_t Reserved192 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3896 uint32_t CuLevelStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU Level Streamout Offset 3897 }; 3898 uint32_t Value; 3899 } DW6; 3900 union 3901 { 3902 struct 3903 { 3904 uint32_t Reserved224 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3905 uint32_t SliceSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Slice Size Streamout Offset 3906 }; 3907 uint32_t Value; 3908 } DW7; 3909 union 3910 { 3911 struct 3912 { 3913 uint32_t Reserved256 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3914 uint32_t CuRecordOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< CU record offset 3915 }; 3916 uint32_t Value; 3917 } DW8; 3918 union 3919 { 3920 struct 3921 { 3922 uint32_t Reserved288 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3923 uint32_t SseRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SSE RowStore offset 3924 }; 3925 uint32_t Value; 3926 } DW9; 3927 union 3928 { 3929 struct 3930 { 3931 uint32_t Reserved320 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3932 uint32_t SaoRowstoreOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< SAO RowStore offset 3933 }; 3934 uint32_t Value; 3935 } DW10; 3936 union 3937 { 3938 struct 3939 { 3940 uint32_t Reserved352 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3941 uint32_t TileSizeStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< Tile Size StreamOut Offset 3942 }; 3943 uint32_t Value; 3944 } DW11; 3945 union 3946 { 3947 struct 3948 { 3949 uint32_t Reserved384 : __CODEGEN_BITFIELD( 0, 5) ; //!< Reserved 3950 uint32_t Vp9ProbabilityCounterStreamoutOffset : __CODEGEN_BITFIELD( 6, 31) ; //!< VP9 Probability Counter Streamout Offset 3951 }; 3952 uint32_t Value; 3953 } DW12; 3954 SPLITBASEADDRESS64BYTEALIGNED_CMD HcpScalabilitySynchronizeBufferBaseAddress; //!< DW13..14, HCP Scalability Synchronize Buffer - Base Address 3955 MEMORYADDRESSATTRIBUTES_CMD HcpScalabilitySynchronizeBufferAttributes; //!< DW15, HCP Scalability Synchronize Buffer - Attributes 3956 3957 //! \name Local enumerations 3958 3959 enum MEDIA_INSTRUCTION_COMMAND 3960 { 3961 MEDIA_INSTRUCTION_COMMAND_HCPTILECODING = 21, //!< No additional details 3962 }; 3963 3964 enum MEDIA_INSTRUCTION_OPCODE 3965 { 3966 MEDIA_INSTRUCTION_OPCODE_CODECENGINENAME = 7, //!< No additional details 3967 }; 3968 3969 enum PIPELINE_TYPE 3970 { 3971 PIPELINE_TYPE_UNNAMED2 = 2, //!< No additional details 3972 }; 3973 3974 enum COMMAND_TYPE 3975 { 3976 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 3977 }; 3978 3979 //! \name Initializations 3980 3981 //! \brief Explicit member initialization function 3982 HCP_TILE_CODING_CMD(); 3983 3984 static const size_t dwSize = 16; 3985 static const size_t byteSize = 64; 3986 }; 3987 3988 }; 3989 3990 #pragma pack() 3991 3992 #endif // __MHW_VDBOX_HCP_HWCMD_G11_X_H__