1 /* 2 * Copyright (c) 2015-2019, Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included 12 * in all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 */ 22 //! 23 //! \file mhw_sfc_hwcmd_g12_X.h 24 //! \brief Auto-generated constructors for MHW and states. 25 //! \details This file may not be included outside of g12_X as other components 26 //! should use MHW interface to interact with MHW commands and states. 27 //! 28 #ifndef __MHW_SFC_HWCMD_G12_X_H__ 29 #define __MHW_SFC_HWCMD_G12_X_H__ 30 31 #pragma once 32 #pragma pack(1) 33 34 #include <cstdint> 35 #include <cstddef> 36 37 class mhw_sfc_g12_X 38 { 39 public: 40 // Internal Macros 41 #define __CODEGEN_MAX(_a, _b) (((_a) > (_b)) ? (_a) : (_b)) 42 #define __CODEGEN_BITFIELD(l, h) (h) - (l) + 1 43 #define __CODEGEN_OP_LENGTH_BIAS 2 44 #define __CODEGEN_OP_LENGTH(x) (uint32_t)((__CODEGEN_MAX(x, __CODEGEN_OP_LENGTH_BIAS)) - __CODEGEN_OP_LENGTH_BIAS) 45 GetOpLength(uint32_t uiLength)46 static uint32_t GetOpLength(uint32_t uiLength) { return __CODEGEN_OP_LENGTH(uiLength); } 47 48 //! 49 //! \brief SFC_AVS_STATE 50 //! \details 51 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 52 //! each frame once the lock request is granted. 53 //! 54 struct SFC_AVS_STATE_CMD 55 { 56 union 57 { 58 //!< DWORD 0 59 struct 60 { 61 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 62 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 63 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 64 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 65 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 66 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 67 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 68 }; 69 uint32_t Value; 70 } DW0; 71 union 72 { 73 //!< DWORD 1 74 struct 75 { 76 uint32_t TransitionAreaWith8Pixels : __CODEGEN_BITFIELD( 0, 2) ; //!< Transition Area with 8 Pixels 77 uint32_t Reserved35 : __CODEGEN_BITFIELD( 3, 3) ; //!< Reserved 78 uint32_t TransitionAreaWith4Pixels : __CODEGEN_BITFIELD( 4, 6) ; //!< Transition Area with 4 Pixels 79 uint32_t Reserved39 : __CODEGEN_BITFIELD( 7, 23) ; //!< Reserved 80 uint32_t SharpnessLevel : __CODEGEN_BITFIELD(24, 31) ; //!< SHARPNESS_LEVEL 81 }; 82 uint32_t Value; 83 } DW1; 84 union 85 { 86 //!< DWORD 2 87 struct 88 { 89 uint32_t MaxDerivativePoint8 : __CODEGEN_BITFIELD( 0, 7) ; //!< MAX Derivative Point 8 90 uint32_t Reserved72 : __CODEGEN_BITFIELD( 8, 15) ; //!< Reserved 91 uint32_t MaxDerivative4Pixels : __CODEGEN_BITFIELD(16, 23) ; //!< Max Derivative 4 Pixels 92 uint32_t Reserved88 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 93 }; 94 uint32_t Value; 95 } DW2; 96 union 97 { 98 //!< DWORD 3 99 struct 100 { 101 uint32_t InputVerticalSitingSpecifiesTheVerticalSitingOfTheInput : __CODEGEN_BITFIELD( 0, 3) ; //!< INPUT_VERTICAL_SITING__SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 102 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 7) ; //!< Reserved 103 uint32_t InputHorizontalSitingValueSpecifiesTheHorizontalSitingOfTheInput : __CODEGEN_BITFIELD( 8, 11) ; //!< INPUT_HORIZONTAL_SITING_VALUE__SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT 104 uint32_t Reserved108 : __CODEGEN_BITFIELD(12, 31) ; //!< Reserved 105 }; 106 uint32_t Value; 107 } DW3; 108 109 //! \name Local enumerations 110 111 enum SUBOPCODEB 112 { 113 SUBOPCODEB_SFCAVSSTATE = 2, //!< No additional details 114 }; 115 116 enum SUBOPCODEA 117 { 118 SUBOPCODEA_COMMON = 0, //!< No additional details 119 }; 120 121 enum MEDIA_COMMAND_OPCODE 122 { 123 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 124 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 125 }; 126 127 enum PIPELINE 128 { 129 PIPELINE_MEDIA = 2, //!< No additional details 130 }; 131 132 enum COMMAND_TYPE 133 { 134 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 135 }; 136 137 //! \brief SHARPNESS_LEVEL 138 //! \details 139 //! When adaptive scaling is off, determines the balance between sharp and 140 //! smooth scalers. 141 enum SHARPNESS_LEVEL 142 { 143 SHARPNESS_LEVEL_UNNAMED0 = 0, //!< Contribute 1 from the smooth scalar 144 SHARPNESS_LEVEL_UNNAMED255 = 255, //!< Contribute 1 from the sharp scalar 145 }; 146 147 //! \brief INPUT_VERTICAL_SITING__SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 148 //! \details 149 //! For 444 and 422 format, vertical chroma siting should be programmed to 150 //! zero. 151 enum INPUT_VERTICAL_SITING__SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT 152 { 153 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_0 = 0, //!< No additional details 154 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_18 = 1, //!< No additional details 155 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_28 = 2, //!< No additional details 156 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_38 = 3, //!< No additional details 157 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_48 = 4, //!< No additional details 158 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_58 = 5, //!< No additional details 159 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_68 = 6, //!< No additional details 160 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_78 = 7, //!< No additional details 161 INPUT_VERTICAL_SITING_SPECIFIES_THE_VERTICAL_SITING_OF_THE_INPUT_88 = 8, //!< No additional details 162 }; 163 164 //! \brief INPUT_HORIZONTAL_SITING_VALUE__SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT 165 //! \details 166 //! For 444 format, horizontal chroma siting should be programmed to zero. 167 enum INPUT_HORIZONTAL_SITING_VALUE__SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT 168 { 169 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_0_FRACTIONININTEGER = 0, //!< No additional details 170 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_18 = 1, //!< No additional details 171 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_28 = 2, //!< No additional details 172 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_38 = 3, //!< No additional details 173 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_48 = 4, //!< No additional details 174 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_58 = 5, //!< No additional details 175 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_68 = 6, //!< No additional details 176 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_78 = 7, //!< No additional details 177 INPUT_HORIZONTAL_SITING_VALUE_SPECIFIES_THE_HORIZONTAL_SITING_OF_THE_INPUT_88 = 8, //!< No additional details 178 }; 179 180 //! \name Initializations 181 182 //! \brief Explicit member initialization function 183 SFC_AVS_STATE_CMD(); 184 185 static const size_t dwSize = 4; 186 static const size_t byteSize = 16; 187 }; 188 189 //! 190 //! \brief SFC_IEF_STATE 191 //! \details 192 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 193 //! each frame once the lock request is granted. 194 //! 195 struct SFC_IEF_STATE_CMD 196 { 197 union 198 { 199 //!< DWORD 0 200 struct 201 { 202 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 203 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 204 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 205 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 206 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 207 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 208 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 209 }; 210 uint32_t Value; 211 } DW0; 212 union 213 { 214 //!< DWORD 1 215 struct 216 { 217 uint32_t GainFactor : __CODEGEN_BITFIELD( 0, 5) ; //!< GAIN_FACTOR 218 uint32_t WeakEdgeThreshold : __CODEGEN_BITFIELD( 6, 11) ; //!< WEAK_EDGE_THRESHOLD 219 uint32_t StrongEdgeThreshold : __CODEGEN_BITFIELD(12, 17) ; //!< STRONG_EDGE_THRESHOLD 220 uint32_t R3XCoefficient : __CODEGEN_BITFIELD(18, 22) ; //!< R3X_COEFFICIENT 221 uint32_t R3CCoefficient : __CODEGEN_BITFIELD(23, 27) ; //!< R3C_COEFFICIENT 222 uint32_t Reserved60 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 223 }; 224 uint32_t Value; 225 } DW1; 226 union 227 { 228 //!< DWORD 2 229 struct 230 { 231 uint32_t GlobalNoiseEstimation : __CODEGEN_BITFIELD( 0, 7) ; //!< GLOBAL_NOISE_ESTIMATION 232 uint32_t NonEdgeWeight : __CODEGEN_BITFIELD( 8, 10) ; //!< NON_EDGE_WEIGHT 233 uint32_t RegularWeight : __CODEGEN_BITFIELD(11, 13) ; //!< REGULAR_WEIGHT 234 uint32_t StrongEdgeWeight : __CODEGEN_BITFIELD(14, 16) ; //!< STRONG_EDGE_WEIGHT 235 uint32_t R5XCoefficient : __CODEGEN_BITFIELD(17, 21) ; //!< R5X_COEFFICIENT 236 uint32_t R5CxCoefficient : __CODEGEN_BITFIELD(22, 26) ; //!< R5CX_COEFFICIENT 237 uint32_t R5CCoefficient : __CODEGEN_BITFIELD(27, 31) ; //!< R5C_COEFFICIENT 238 }; 239 uint32_t Value; 240 } DW2; 241 union 242 { 243 //!< DWORD 3 244 struct 245 { 246 uint32_t StdSinAlpha : __CODEGEN_BITFIELD( 0, 7) ; //!< STD Sin(alpha) 247 uint32_t StdCosAlpha : __CODEGEN_BITFIELD( 8, 15) ; //!< STD Cos(alpha) 248 uint32_t SatMax : __CODEGEN_BITFIELD(16, 21) ; //!< SAT_MAX 249 uint32_t HueMax : __CODEGEN_BITFIELD(22, 27) ; //!< HUE_MAX 250 uint32_t Reserved124 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 251 }; 252 uint32_t Value; 253 } DW3; 254 union 255 { 256 //!< DWORD 4 257 struct 258 { 259 uint32_t S3U : __CODEGEN_BITFIELD( 0, 10) ; //!< S3U 260 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 261 uint32_t DiamondMargin : __CODEGEN_BITFIELD(12, 14) ; //!< DIAMOND_MARGIN 262 uint32_t VyStdEnable : __CODEGEN_BITFIELD(15, 15) ; //!< VY_STD_Enable 263 uint32_t UMid : __CODEGEN_BITFIELD(16, 23) ; //!< U_MID 264 uint32_t VMid : __CODEGEN_BITFIELD(24, 31) ; //!< V_MID 265 }; 266 uint32_t Value; 267 } DW4; 268 union 269 { 270 //!< DWORD 5 271 struct 272 { 273 uint32_t DiamondDv : __CODEGEN_BITFIELD( 0, 6) ; //!< DIAMOND_DV 274 uint32_t DiamondTh : __CODEGEN_BITFIELD( 7, 12) ; //!< DIAMOND_TH 275 uint32_t DiamondAlpha : __CODEGEN_BITFIELD(13, 20) ; //!< Diamond_alpha 276 uint32_t HsMargin : __CODEGEN_BITFIELD(21, 23) ; //!< HS_MARGIN 277 uint32_t DiamondDu : __CODEGEN_BITFIELD(24, 30) ; //!< DIAMOND_DU 278 uint32_t SkinDetailFactor : __CODEGEN_BITFIELD(31, 31) ; //!< SKIN_DETAIL_FACTOR 279 }; 280 uint32_t Value; 281 } DW5; 282 union 283 { 284 //!< DWORD 6 285 struct 286 { 287 uint32_t YPoint1 : __CODEGEN_BITFIELD( 0, 7) ; //!< Y_POINT_1 288 uint32_t YPoint2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Y_POINT_2 289 uint32_t YPoint3 : __CODEGEN_BITFIELD(16, 23) ; //!< Y_POINT_3 290 uint32_t YPoint4 : __CODEGEN_BITFIELD(24, 31) ; //!< Y_POINT_4 291 }; 292 uint32_t Value; 293 } DW6; 294 union 295 { 296 //!< DWORD 7 297 struct 298 { 299 uint32_t InvMarginVyl : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYL 300 uint32_t Reserved240 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 301 }; 302 uint32_t Value; 303 } DW7; 304 union 305 { 306 //!< DWORD 8 307 struct 308 { 309 uint32_t InvMarginVyu : __CODEGEN_BITFIELD( 0, 15) ; //!< INV_Margin_VYU 310 uint32_t P0L : __CODEGEN_BITFIELD(16, 23) ; //!< P0L 311 uint32_t P1L : __CODEGEN_BITFIELD(24, 31) ; //!< P1L 312 }; 313 uint32_t Value; 314 } DW8; 315 union 316 { 317 //!< DWORD 9 318 struct 319 { 320 uint32_t P2L : __CODEGEN_BITFIELD( 0, 7) ; //!< P2L 321 uint32_t P3L : __CODEGEN_BITFIELD( 8, 15) ; //!< P3L 322 uint32_t B0L : __CODEGEN_BITFIELD(16, 23) ; //!< B0L 323 uint32_t B1L : __CODEGEN_BITFIELD(24, 31) ; //!< B1L 324 }; 325 uint32_t Value; 326 } DW9; 327 union 328 { 329 //!< DWORD 10 330 struct 331 { 332 uint32_t B2L : __CODEGEN_BITFIELD( 0, 7) ; //!< B2L 333 uint32_t B3L : __CODEGEN_BITFIELD( 8, 15) ; //!< B3L 334 uint32_t S0L : __CODEGEN_BITFIELD(16, 26) ; //!< S0L 335 uint32_t YSlope2 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope_2 336 }; 337 uint32_t Value; 338 } DW10; 339 union 340 { 341 //!< DWORD 11 342 struct 343 { 344 uint32_t S1L : __CODEGEN_BITFIELD( 0, 10) ; //!< S1L 345 uint32_t S2L : __CODEGEN_BITFIELD(11, 21) ; //!< S2L 346 uint32_t Reserved374 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 347 }; 348 uint32_t Value; 349 } DW11; 350 union 351 { 352 //!< DWORD 12 353 struct 354 { 355 uint32_t S3L : __CODEGEN_BITFIELD( 0, 10) ; //!< S3L 356 uint32_t P0U : __CODEGEN_BITFIELD(11, 18) ; //!< P0U 357 uint32_t P1U : __CODEGEN_BITFIELD(19, 26) ; //!< P1U 358 uint32_t YSlope1 : __CODEGEN_BITFIELD(27, 31) ; //!< Y_Slope1 359 }; 360 uint32_t Value; 361 } DW12; 362 union 363 { 364 //!< DWORD 13 365 struct 366 { 367 uint32_t P2U : __CODEGEN_BITFIELD( 0, 7) ; //!< P2U 368 uint32_t P3U : __CODEGEN_BITFIELD( 8, 15) ; //!< P3U 369 uint32_t B0U : __CODEGEN_BITFIELD(16, 23) ; //!< B0U 370 uint32_t B1U : __CODEGEN_BITFIELD(24, 31) ; //!< B1U 371 }; 372 uint32_t Value; 373 } DW13; 374 union 375 { 376 //!< DWORD 14 377 struct 378 { 379 uint32_t B2U : __CODEGEN_BITFIELD( 0, 7) ; //!< B2U 380 uint32_t B3U : __CODEGEN_BITFIELD( 8, 15) ; //!< B3U 381 uint32_t S0U : __CODEGEN_BITFIELD(16, 26) ; //!< S0U 382 uint32_t Reserved475 : __CODEGEN_BITFIELD(27, 31) ; //!< Reserved 383 }; 384 uint32_t Value; 385 } DW14; 386 union 387 { 388 //!< DWORD 15 389 struct 390 { 391 uint32_t S1U : __CODEGEN_BITFIELD( 0, 10) ; //!< S1U 392 uint32_t S2U : __CODEGEN_BITFIELD(11, 21) ; //!< S2U 393 uint32_t Reserved502 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 394 }; 395 uint32_t Value; 396 } DW15; 397 union 398 { 399 //!< DWORD 16 400 struct 401 { 402 uint32_t TransformEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< Transform Enable 403 uint32_t YuvChannelSwap : __CODEGEN_BITFIELD( 1, 1) ; //!< YUV Channel Swap 404 uint32_t Reserved514 : __CODEGEN_BITFIELD( 2, 2) ; //!< Reserved 405 uint32_t C0 : __CODEGEN_BITFIELD( 3, 15) ; //!< C0 406 uint32_t C1 : __CODEGEN_BITFIELD(16, 28) ; //!< C1 407 uint32_t Reserved541 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 408 }; 409 uint32_t Value; 410 } DW16; 411 union 412 { 413 //!< DWORD 17 414 struct 415 { 416 uint32_t C2 : __CODEGEN_BITFIELD( 0, 12) ; //!< C2 417 uint32_t C3 : __CODEGEN_BITFIELD(13, 25) ; //!< C3 418 uint32_t Reserved570 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 419 }; 420 uint32_t Value; 421 } DW17; 422 union 423 { 424 //!< DWORD 18 425 struct 426 { 427 uint32_t C4 : __CODEGEN_BITFIELD( 0, 12) ; //!< C4 428 uint32_t C5 : __CODEGEN_BITFIELD(13, 25) ; //!< C5 429 uint32_t Reserved602 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 430 }; 431 uint32_t Value; 432 } DW18; 433 union 434 { 435 //!< DWORD 19 436 struct 437 { 438 uint32_t C6 : __CODEGEN_BITFIELD( 0, 12) ; //!< C6 439 uint32_t C7 : __CODEGEN_BITFIELD(13, 25) ; //!< C7 440 uint32_t Reserved634 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 441 }; 442 uint32_t Value; 443 } DW19; 444 union 445 { 446 //!< DWORD 20 447 struct 448 { 449 uint32_t C8 : __CODEGEN_BITFIELD( 0, 12) ; //!< C8 450 uint32_t Reserved653 : __CODEGEN_BITFIELD(13, 31) ; //!< Reserved 451 }; 452 uint32_t Value; 453 } DW20; 454 union 455 { 456 //!< DWORD 21 457 struct 458 { 459 uint32_t OffsetIn1 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_1 460 uint32_t OffsetOut1 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_1 461 uint32_t Reserved694 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 462 }; 463 uint32_t Value; 464 } DW21; 465 union 466 { 467 //!< DWORD 22 468 struct 469 { 470 uint32_t OffsetIn2 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_2 471 uint32_t OffsetOut2 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_2 472 uint32_t Reserved726 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 473 }; 474 uint32_t Value; 475 } DW22; 476 union 477 { 478 //!< DWORD 23 479 struct 480 { 481 uint32_t OffsetIn3 : __CODEGEN_BITFIELD( 0, 10) ; //!< OFFSET_IN_3 482 uint32_t OffsetOut3 : __CODEGEN_BITFIELD(11, 21) ; //!< OFFSET_OUT_3 483 uint32_t Reserved758 : __CODEGEN_BITFIELD(22, 31) ; //!< Reserved 484 }; 485 uint32_t Value; 486 } DW23; 487 488 //! \name Local enumerations 489 490 enum SUBOPCODEB 491 { 492 SUBOPCODEB_SFCIEFSTATE = 3, //!< No additional details 493 }; 494 495 enum SUBOPCODEA 496 { 497 SUBOPCODEA_COMMON = 0, //!< No additional details 498 }; 499 500 enum MEDIA_COMMAND_OPCODE 501 { 502 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 503 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 504 }; 505 506 enum PIPELINE 507 { 508 PIPELINE_MEDIA = 2, //!< No additional details 509 }; 510 511 enum COMMAND_TYPE 512 { 513 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 514 }; 515 516 //! \brief GAIN_FACTOR 517 //! \details 518 //! User control sharpening strength. 519 enum GAIN_FACTOR 520 { 521 GAIN_FACTOR_UNNAMED_4_4 = 44, //!< No additional details 522 }; 523 524 //! \brief WEAK_EDGE_THRESHOLD 525 //! \details 526 //! If Strong Edge Threshold > EM > Weak Edge Threshold ? the basic 527 //! VSA detects a weak edge. 528 enum WEAK_EDGE_THRESHOLD 529 { 530 WEAK_EDGE_THRESHOLD_UNNAMED1 = 1, //!< No additional details 531 }; 532 533 //! \brief STRONG_EDGE_THRESHOLD 534 //! \details 535 //! If EM > Strong Edge Threshold ? the basic VSA detects a strong edge. 536 enum STRONG_EDGE_THRESHOLD 537 { 538 STRONG_EDGE_THRESHOLD_UNNAMED8 = 8, //!< No additional details 539 }; 540 541 //! \brief R3X_COEFFICIENT 542 //! \details 543 //! IEF smoothing coefficient, <i>see IEF map.</i> 544 enum R3X_COEFFICIENT 545 { 546 R3X_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 547 }; 548 549 //! \brief R3C_COEFFICIENT 550 //! \details 551 //! IEF smoothing coefficient, <i>see IEF map.</i> 552 enum R3C_COEFFICIENT 553 { 554 R3C_COEFFICIENT_UNNAMED5 = 5, //!< No additional details 555 }; 556 557 //! \brief GLOBAL_NOISE_ESTIMATION 558 //! \details 559 //! Global noise estimation of previous frame. 560 enum GLOBAL_NOISE_ESTIMATION 561 { 562 GLOBAL_NOISE_ESTIMATION_UNNAMED255 = 255, //!< No additional details 563 }; 564 565 //! \brief NON_EDGE_WEIGHT 566 //! \details 567 //! . Sharpening strength when <u>NO EDGE</u> is found in basic VSA. 568 enum NON_EDGE_WEIGHT 569 { 570 NON_EDGE_WEIGHT_UNNAMED1 = 1, //!< No additional details 571 }; 572 573 //! \brief REGULAR_WEIGHT 574 //! \details 575 //! Sharpening strength when a <u>WEAK</u> edge is found in basic VSA. 576 enum REGULAR_WEIGHT 577 { 578 REGULAR_WEIGHT_UNNAMED2 = 2, //!< No additional details 579 }; 580 581 //! \brief STRONG_EDGE_WEIGHT 582 //! \details 583 //! Sharpening strength when a <u>STRONG</u> edge is found in basic VSA. 584 enum STRONG_EDGE_WEIGHT 585 { 586 STRONG_EDGE_WEIGHT_UNNAMED7 = 7, //!< No additional details 587 }; 588 589 //! \brief R5X_COEFFICIENT 590 //! \details 591 //! IEF smoothing coefficient, <i>see IEF map.</i> 592 enum R5X_COEFFICIENT 593 { 594 R5X_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 595 }; 596 597 //! \brief R5CX_COEFFICIENT 598 //! \details 599 //! IEF smoothing coefficient, <i>see IEF map.</i> 600 enum R5CX_COEFFICIENT 601 { 602 R5CX_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 603 }; 604 605 //! \brief R5C_COEFFICIENT 606 //! \details 607 //! IEF smoothing coefficient, <i>see IEF map.</i> 608 enum R5C_COEFFICIENT 609 { 610 R5C_COEFFICIENT_UNNAMED7 = 7, //!< No additional details 611 }; 612 613 //! \brief SAT_MAX 614 //! \details 615 //! Rectangle half length. 616 enum SAT_MAX 617 { 618 SAT_MAX_UNNAMED31 = 31, //!< No additional details 619 }; 620 621 //! \brief HUE_MAX 622 //! \details 623 //! Rectangle half width. 624 enum HUE_MAX 625 { 626 HUE_MAX_UNNAMED1_4 = 14, //!< No additional details 627 }; 628 629 enum DIAMOND_MARGIN 630 { 631 DIAMOND_MARGIN_UNNAMED_4 = 4, //!< No additional details 632 }; 633 634 //! \brief U_MID 635 //! \details 636 //! Rectangle middle-point U coordinate. 637 enum U_MID 638 { 639 U_MID_UNNAMED110 = 110, //!< No additional details 640 }; 641 642 //! \brief V_MID 643 //! \details 644 //! Rectangle middle-point V coordinate. 645 enum V_MID 646 { 647 V_MID_UNNAMED15_4 = 154, //!< No additional details 648 }; 649 650 //! \brief DIAMOND_DV 651 //! \details 652 //! Rhombus center shift in the hue-direction, relative to the rectangle 653 //! center. 654 enum DIAMOND_DV 655 { 656 DIAMOND_DV_UNNAMED0 = 0, //!< No additional details 657 }; 658 659 //! \brief DIAMOND_TH 660 //! \details 661 //! Half length of the rhombus axis in the sat-direction. 662 enum DIAMOND_TH 663 { 664 DIAMOND_TH_UNNAMED35 = 35, //!< No additional details 665 }; 666 667 //! \brief HS_MARGIN 668 //! \details 669 //! Defines rectangle margin. 670 enum HS_MARGIN 671 { 672 HS_MARGIN_UNNAMED3 = 3, //!< No additional details 673 }; 674 675 //! \brief DIAMOND_DU 676 //! \details 677 //! Rhombus center shift in the sat-direction, relative to the rectangle 678 //! center. 679 enum DIAMOND_DU 680 { 681 DIAMOND_DU_UNNAMED0 = 0, //!< No additional details 682 }; 683 684 //! \brief SKIN_DETAIL_FACTOR 685 //! \details 686 //! This flag bit is in operation only when one of the following conditions 687 //! exists: 688 //! <ul> 689 //! <li>when the control bit <b>SkinToneTunedIEF_Enable</b> is on. 690 //! </li> 691 //! <Li>When <b>SkinDetailFactor</b> is equal to 0, 692 //! sign(<b>SkinDetailFactor</b>) is equal to +1, and the content of the 693 //! detected skin tone area is detail revealed.</Li> 694 //! <li>When <b>SkinDetailFactor</b> is equal to 1, 695 //! sign(<b>SkinDetailFactor</b>) is equal to -1, and the content of the 696 //! detected skin tone area is not detail revealed.</li> 697 //! </ul> 698 enum SKIN_DETAIL_FACTOR 699 { 700 SKIN_DETAIL_FACTOR_DETAILREVEALED = 0, //!< No additional details 701 SKIN_DETAIL_FACTOR_NOTDETAILREVEALED = 1, //!< No additional details 702 }; 703 704 //! \brief Y_POINT_1 705 //! \details 706 //! First point of the Y piecewise linear membership function. 707 enum Y_POINT_1 708 { 709 Y_POINT_1_UNNAMED_46 = 46, //!< No additional details 710 }; 711 712 //! \brief Y_POINT_2 713 //! \details 714 //! Second point of the Y piecewise linear membership function. 715 enum Y_POINT_2 716 { 717 Y_POINT_2_UNNAMED_47 = 47, //!< No additional details 718 }; 719 720 //! \brief Y_POINT_3 721 //! \details 722 //! Third point of the Y piecewise linear membership function. 723 enum Y_POINT_3 724 { 725 Y_POINT_3_UNNAMED25_4 = 254, //!< No additional details 726 }; 727 728 //! \brief Y_POINT_4 729 //! \details 730 //! Fourth point of the Y piecewise linear membership function. 731 enum Y_POINT_4 732 { 733 Y_POINT_4_UNNAMED255 = 255, //!< No additional details 734 }; 735 736 //! \brief P0L 737 //! \details 738 //! Y Point 0 of the lower part of the detection PWLF. 739 enum P0L 740 { 741 P0L_UNNAMED_46 = 46, //!< No additional details 742 }; 743 744 //! \brief P1L 745 //! \details 746 //! Y Point 1 of the lower part of the detection PWLF. 747 enum P1L 748 { 749 P1L_UNNAMED216 = 216, //!< No additional details 750 }; 751 752 //! \brief P2L 753 //! \details 754 //! Y Point 2 of the lower part of the detection PWLF. 755 enum P2L 756 { 757 P2L_UNNAMED236 = 236, //!< No additional details 758 }; 759 760 //! \brief P3L 761 //! \details 762 //! Y Point 3 of the lower part of the detection PWLF. 763 enum P3L 764 { 765 P3L_UNNAMED236 = 236, //!< No additional details 766 }; 767 768 //! \brief B0L 769 //! \details 770 //! V Bias 0 of the lower part of the detection PWLF. 771 enum B0L 772 { 773 B0L_UNNAMED133 = 133, //!< No additional details 774 }; 775 776 //! \brief B1L 777 //! \details 778 //! V Bias 1 of the lower part of the detection PWLF. 779 enum B1L 780 { 781 B1L_UNNAMED130 = 130, //!< No additional details 782 }; 783 784 //! \brief B2L 785 //! \details 786 //! V Bias 2 of the lower part of the detection PWLF. 787 enum B2L 788 { 789 B2L_UNNAMED130 = 130, //!< No additional details 790 }; 791 792 //! \brief B3L 793 //! \details 794 //! V Bias 3 of the lower part of the detection PWLF. 795 enum B3L 796 { 797 B3L_UNNAMED130 = 130, //!< No additional details 798 }; 799 800 //! \brief P0U 801 //! \details 802 //! Y Point 0 of the upper part of the detection PWLF. 803 enum P0U 804 { 805 P0U_UNNAMED_46 = 46, //!< No additional details 806 }; 807 808 //! \brief P1U 809 //! \details 810 //! Y Point 1 of the upper part of the detection PWLF. 811 enum P1U 812 { 813 P1U_UNNAMED66 = 66, //!< No additional details 814 }; 815 816 //! \brief P2U 817 //! \details 818 //! Y Point 2 of the upper part of the detection PWLF. 819 enum P2U 820 { 821 P2U_UNNAMED150 = 150, //!< No additional details 822 }; 823 824 //! \brief P3U 825 //! \details 826 //! Y Point 3 of the upper part of the detection PWLF. 827 enum P3U 828 { 829 P3U_UNNAMED236 = 236, //!< No additional details 830 }; 831 832 //! \brief B0U 833 //! \details 834 //! V Bias 0 of the upper part of the detection PWLF. 835 enum B0U 836 { 837 B0U_UNNAMED1_43 = 143, //!< No additional details 838 }; 839 840 //! \brief B1U 841 //! \details 842 //! V Bias 1 of the upper part of the detection PWLF. 843 enum B1U 844 { 845 B1U_UNNAMED163 = 163, //!< No additional details 846 }; 847 848 //! \brief B2U 849 //! \details 850 //! V Bias 2 of the upper part of the detection PWLF. 851 enum B2U 852 { 853 B2U_UNNAMED200 = 200, //!< No additional details 854 }; 855 856 //! \brief B3U 857 //! \details 858 //! V Bias 3 of the upper part of the detection PWLF. 859 enum B3U 860 { 861 B3U_UNNAMED1_40 = 140, //!< No additional details 862 }; 863 864 //! \brief C0 865 //! \details 866 //! Transform coefficient 867 enum C0 868 { 869 C0_UNNAMED102_4 = 1024, //!< No additional details 870 }; 871 872 //! \brief C1 873 //! \details 874 //! Transform coefficient 875 enum C1 876 { 877 C1_UNNAMED0 = 0, //!< No additional details 878 }; 879 880 //! \brief C2 881 //! \details 882 //! Transform coefficient 883 enum C2 884 { 885 C2_UNNAMED0 = 0, //!< No additional details 886 }; 887 888 //! \brief C3 889 //! \details 890 //! Transform coefficient 891 enum C3 892 { 893 C3_UNNAMED0 = 0, //!< No additional details 894 }; 895 896 //! \brief C4 897 //! \details 898 //! Transform coefficient 899 enum C4 900 { 901 C4_UNNAMED102_4 = 1024, //!< No additional details 902 }; 903 904 //! \brief C5 905 //! \details 906 //! Transform coefficient 907 enum C5 908 { 909 C5_UNNAMED0 = 0, //!< No additional details 910 }; 911 912 //! \brief C6 913 //! \details 914 //! Transform coefficient 915 enum C6 916 { 917 C6_UNNAMED0 = 0, //!< No additional details 918 }; 919 920 //! \brief C7 921 //! \details 922 //! Transform coefficient 923 enum C7 924 { 925 C7_UNNAMED0 = 0, //!< No additional details 926 }; 927 928 //! \brief C8 929 //! \details 930 //! Transform coefficient 931 enum C8 932 { 933 C8_UNNAMED102_4 = 1024, //!< No additional details 934 }; 935 936 //! \brief OFFSET_IN_1 937 //! \details 938 //! Offset in for Y/R. 939 enum OFFSET_IN_1 940 { 941 OFFSET_IN_1_UNNAMED0 = 0, //!< No additional details 942 }; 943 944 //! \brief OFFSET_OUT_1 945 //! \details 946 //! Offset out for Y/R. 947 enum OFFSET_OUT_1 948 { 949 OFFSET_OUT_1_UNNAMED0 = 0, //!< No additional details 950 }; 951 952 //! \brief OFFSET_IN_2 953 //! \details 954 //! Offset in for U/G. 955 enum OFFSET_IN_2 956 { 957 OFFSET_IN_2_UNNAMED0 = 0, //!< No additional details 958 }; 959 960 //! \brief OFFSET_OUT_2 961 //! \details 962 //! Offset out for U/G. 963 enum OFFSET_OUT_2 964 { 965 OFFSET_OUT_2_UNNAMED0 = 0, //!< No additional details 966 }; 967 968 //! \brief OFFSET_IN_3 969 //! \details 970 //! Offset in for V/B. 971 enum OFFSET_IN_3 972 { 973 OFFSET_IN_3_UNNAMED0 = 0, //!< No additional details 974 }; 975 976 //! \brief OFFSET_OUT_3 977 //! \details 978 //! Offset out for V/B. 979 enum OFFSET_OUT_3 980 { 981 OFFSET_OUT_3_UNNAMED0 = 0, //!< No additional details 982 }; 983 984 //! \name Initializations 985 986 //! \brief Explicit member initialization function 987 SFC_IEF_STATE_CMD(); 988 989 static const size_t dwSize = 24; 990 static const size_t byteSize = 96; 991 }; 992 993 //! 994 //! \brief SFC_FRAME_START 995 //! \details 996 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 997 //! each frame once the lock request is granted. 998 //! 999 struct SFC_FRAME_START_CMD 1000 { 1001 union 1002 { 1003 //!< DWORD 0 1004 struct 1005 { 1006 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1007 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1008 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1009 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1010 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1011 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1012 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1013 }; 1014 uint32_t Value; 1015 } DW0; 1016 union 1017 { 1018 //!< DWORD 1 1019 struct 1020 { 1021 uint32_t Reserved32 ; //!< Reserved 1022 }; 1023 uint32_t Value; 1024 } DW1; 1025 1026 //! \name Local enumerations 1027 1028 enum SUBOPCODEB 1029 { 1030 SUBOPCODEB_SFCFRAMESTART = 4, //!< No additional details 1031 }; 1032 1033 enum SUBOPCODEA 1034 { 1035 SUBOPCODEA_COMMON = 0, //!< No additional details 1036 }; 1037 1038 enum MEDIA_COMMAND_OPCODE 1039 { 1040 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 1041 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 1042 }; 1043 1044 enum PIPELINE 1045 { 1046 PIPELINE_MEDIA = 2, //!< No additional details 1047 }; 1048 1049 enum COMMAND_TYPE 1050 { 1051 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1052 }; 1053 1054 //! \name Initializations 1055 1056 //! \brief Explicit member initialization function 1057 SFC_FRAME_START_CMD(); 1058 1059 static const size_t dwSize = 2; 1060 static const size_t byteSize = 8; 1061 }; 1062 1063 //! 1064 //! \brief SFC_LOCK 1065 //! \details 1066 //! 1067 //! 1068 struct SFC_LOCK_CMD 1069 { 1070 union 1071 { 1072 //!< DWORD 0 1073 struct 1074 { 1075 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1076 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1077 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1078 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1079 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1080 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1081 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1082 }; 1083 uint32_t Value; 1084 } DW0; 1085 union 1086 { 1087 //!< DWORD 1 1088 struct 1089 { 1090 uint32_t VeSfcPipeSelect : __CODEGEN_BITFIELD( 0, 0) ; //!< VE-SFC Pipe Select 1091 uint32_t PreScaledOutputSurfaceOutputEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Pre-Scaled Output Surface Output Enable 1092 uint32_t Reserved34 : __CODEGEN_BITFIELD( 2, 31) ; //!< Reserved 1093 }; 1094 uint32_t Value; 1095 } DW1; 1096 1097 //! \name Local enumerations 1098 1099 enum SUBOPCODEB 1100 { 1101 SUBOPCODEB_SFCLOCK = 0, //!< No additional details 1102 }; 1103 1104 enum SUBOPCODEA 1105 { 1106 SUBOPCODEA_COMMON = 0, //!< No additional details 1107 }; 1108 1109 enum MEDIA_COMMAND_OPCODE 1110 { 1111 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 1112 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 1113 }; 1114 1115 enum PIPELINE 1116 { 1117 PIPELINE_MEDIA = 2, //!< No additional details 1118 }; 1119 1120 enum COMMAND_TYPE 1121 { 1122 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1123 }; 1124 1125 //! \name Initializations 1126 1127 //! \brief Explicit member initialization function 1128 SFC_LOCK_CMD(); 1129 1130 static const size_t dwSize = 2; 1131 static const size_t byteSize = 8; 1132 }; 1133 1134 //! 1135 //! \brief SFC_STATE 1136 //! \details 1137 //! This command is sent from VDBOX/HCP/VEBOX to SFC pipeline at the start 1138 //! of each frame once the lock request is granted. 1139 //! 1140 struct SFC_STATE_CMD 1141 { 1142 union 1143 { 1144 //!< DWORD 0 1145 struct 1146 { 1147 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 1148 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 1149 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 1150 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 1151 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 1152 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 1153 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 1154 }; 1155 uint32_t Value; 1156 } DW0; 1157 union 1158 { 1159 //!< DWORD 1 1160 struct 1161 { 1162 uint32_t SfcPipeMode : __CODEGEN_BITFIELD( 0, 3) ; //!< SFC_PIPE_MODE 1163 uint32_t SfcInputChromaSubSampling : __CODEGEN_BITFIELD( 4, 7) ; //!< SFC_INPUT_CHROMA_SUB_SAMPLING 1164 uint32_t VdVeInputOrderingMode : __CODEGEN_BITFIELD( 8, 10) ; //!< VDVE_INPUT_ORDERING_MODE 1165 uint32_t Reserved43 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1166 uint32_t SfcEngineMode : __CODEGEN_BITFIELD(12, 13) ; //!< SFC Engine Mode 1167 uint32_t SfcInputStreamBitDepth : __CODEGEN_BITFIELD(14, 15) ; //!< SFC Input Stream Bit Depth 1168 uint32_t Reserved48 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1169 }; 1170 uint32_t Value; 1171 } DW1; 1172 union 1173 { 1174 //!< DWORD 2 1175 struct 1176 { 1177 uint32_t InputFrameResolutionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Input Frame Resolution Width 1178 uint32_t Reserved78 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1179 uint32_t InputFrameResolutionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Input Frame Resolution Height 1180 uint32_t Reserved94 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1181 }; 1182 uint32_t Value; 1183 } DW2; 1184 union 1185 { 1186 //!< DWORD 3 1187 struct 1188 { 1189 uint32_t OutputSurfaceFormatType : __CODEGEN_BITFIELD( 0, 3) ; //!< OUTPUT_SURFACE_FORMAT_TYPE 1190 uint32_t Reserved100 : __CODEGEN_BITFIELD( 4, 4) ; //!< Reserved 1191 uint32_t RgbaChannelSwapEnable : __CODEGEN_BITFIELD( 5, 5) ; //!< RGBA_CHANNEL_SWAP_ENABLE 1192 uint32_t Reserved102 : __CODEGEN_BITFIELD( 6, 7) ; //!< Reserved 1193 uint32_t OutputChromaDownsamplingCoSitingPositionVerticalDirection : __CODEGEN_BITFIELD( 8, 11) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 1194 uint32_t OutputChromaDownsamplingCoSitingPositionHorizontalDirection : __CODEGEN_BITFIELD(12, 15) ; //!< OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 1195 uint32_t InputColorSpace0Yuv1Rgb : __CODEGEN_BITFIELD(16, 16) ; //!< INPUT_COLOR_SPACE__0_YUV1__RGB 1196 uint32_t Reserved113 : __CODEGEN_BITFIELD(17, 31) ; //!< Reserved 1197 }; 1198 uint32_t Value; 1199 } DW3; 1200 union 1201 { 1202 //!< DWORD 4 1203 struct 1204 { 1205 uint32_t IefEnable : __CODEGEN_BITFIELD( 0, 0) ; //!< IEF_ENABLE 1206 uint32_t SkinToneTunedIefEnable : __CODEGEN_BITFIELD( 1, 1) ; //!< Skin Tone Tuned IEF_Enable 1207 uint32_t Ief4SmoothEnable : __CODEGEN_BITFIELD( 2, 2) ; //!< IEF4SMOOTH_ENABLE_ 1208 uint32_t Enable8TapForChromaChannelsFiltering : __CODEGEN_BITFIELD( 3, 3) ; //!< Enable 8 tap for Chroma channels filtering 1209 uint32_t AvsFilterMode : __CODEGEN_BITFIELD( 4, 5) ; //!< AVS_FILTER_MODE 1210 uint32_t AdaptiveFilterForAllChannels : __CODEGEN_BITFIELD( 6, 6) ; //!< ADAPTIVE_FILTER_FOR_ALL_CHANNELS 1211 uint32_t AvsScalingEnable : __CODEGEN_BITFIELD( 7, 7) ; //!< AVS_SCALING_ENABLE 1212 uint32_t BypassYAdaptiveFiltering : __CODEGEN_BITFIELD( 8, 8) ; //!< BYPASS_Y_ADAPTIVE_FILTERING 1213 uint32_t BypassXAdaptiveFiltering : __CODEGEN_BITFIELD( 9, 9) ; //!< BYPASS_X_ADAPTIVE_FILTERING 1214 uint32_t RgbAdaptive : __CODEGEN_BITFIELD(10, 10) ; //!< RGB Adaptive 1215 uint32_t Reserved139 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1216 uint32_t ChromaUpsamplingEnable : __CODEGEN_BITFIELD(12, 12) ; //!< Chroma Upsampling Enable 1217 uint32_t Reserved141 : __CODEGEN_BITFIELD(13, 15) ; //!< Reserved 1218 uint32_t RotationMode : __CODEGEN_BITFIELD(16, 17) ; //!< ROTATION_MODE 1219 uint32_t ColorFillEnable : __CODEGEN_BITFIELD(18, 18) ; //!< Color Fill Enable 1220 uint32_t CscEnable : __CODEGEN_BITFIELD(19, 19) ; //!< CSC Enable 1221 uint32_t Bitdepth : __CODEGEN_BITFIELD(20, 21) ; //!< BITDEPTH 1222 uint32_t TileType : __CODEGEN_BITFIELD(22, 22) ; //!< Tile Type 1223 uint32_t HistogramStreamout : __CODEGEN_BITFIELD(23, 23); //!< Tile Type 1224 uint32_t Reserved151 : __CODEGEN_BITFIELD(24, 31) ; //!< Reserved 1225 }; 1226 uint32_t Value; 1227 } DW4; 1228 union 1229 { 1230 //!< DWORD 5 1231 struct 1232 { 1233 uint32_t SourceRegionWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Width 1234 uint32_t Reserved174 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1235 uint32_t SourceRegionHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Height 1236 uint32_t Reserved190 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1237 }; 1238 uint32_t Value; 1239 } DW5; 1240 union 1241 { 1242 //!< DWORD 6 1243 struct 1244 { 1245 uint32_t SourceRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 13) ; //!< Source Region Horizontal Offset 1246 uint32_t Reserved206 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1247 uint32_t SourceRegionVerticalOffset : __CODEGEN_BITFIELD(16, 29) ; //!< Source Region Vertical Offset 1248 uint32_t Reserved222 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1249 }; 1250 uint32_t Value; 1251 } DW6; 1252 union 1253 { 1254 //!< DWORD 7 1255 struct 1256 { 1257 uint32_t OutputFrameWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Output Frame Width 1258 uint32_t Reserved238 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1259 uint32_t OutputFrameHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Output Frame Height 1260 uint32_t Reserved254 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1261 }; 1262 uint32_t Value; 1263 } DW7; 1264 union 1265 { 1266 //!< DWORD 8 1267 struct 1268 { 1269 uint32_t ScaledRegionSizeWidth : __CODEGEN_BITFIELD( 0, 13) ; //!< Scaled Region Size Width 1270 uint32_t Reserved270 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1271 uint32_t ScaledRegionSizeHeight : __CODEGEN_BITFIELD(16, 29) ; //!< Scaled Region Size Height 1272 uint32_t Reserved286 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1273 }; 1274 uint32_t Value; 1275 } DW8; 1276 union 1277 { 1278 //!< DWORD 9 1279 struct 1280 { 1281 uint32_t ScaledRegionHorizontalOffset : __CODEGEN_BITFIELD( 0, 14) ; //!< Scaled Region Horizontal Offset 1282 uint32_t Reserved303 : __CODEGEN_BITFIELD(15, 15) ; //!< Reserved 1283 uint32_t ScaledRegionVerticalOffset : __CODEGEN_BITFIELD(16, 30) ; //!< Scaled Region Vertical Offset 1284 uint32_t Reserved319 : __CODEGEN_BITFIELD(31, 31) ; //!< Reserved 1285 }; 1286 uint32_t Value; 1287 } DW9; 1288 union 1289 { 1290 //!< DWORD 10 1291 struct 1292 { 1293 uint32_t GrayBarPixelUG : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - U/G 1294 uint32_t Reserved330 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1295 uint32_t GrayBarPixelYR : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - Y/R 1296 uint32_t Reserved346 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1297 }; 1298 uint32_t Value; 1299 } DW10; 1300 union 1301 { 1302 //!< DWORD 11 1303 struct 1304 { 1305 uint32_t GrayBarPixelA : __CODEGEN_BITFIELD( 0, 9) ; //!< Gray Bar Pixel - A 1306 uint32_t Reserved362 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1307 uint32_t GrayBarPixelVB : __CODEGEN_BITFIELD(16, 25) ; //!< Gray Bar Pixel - V/B 1308 uint32_t Reserved378 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1309 }; 1310 uint32_t Value; 1311 } DW11; 1312 union 1313 { 1314 //!< DWORD 12 1315 struct 1316 { 1317 uint32_t UvDefaultValueForUChannelForMonoInputSupport : __CODEGEN_BITFIELD( 0, 9) ; //!< UV Default value for U channel (For Mono Input Support) 1318 uint32_t Reserved394 : __CODEGEN_BITFIELD(10, 15) ; //!< Reserved 1319 uint32_t UvDefaultValueForVChannelForMonoInputSupport : __CODEGEN_BITFIELD(16, 25) ; //!< UV Default value for V channel (For Mono Input Support) 1320 uint32_t Reserved410 : __CODEGEN_BITFIELD(26, 31) ; //!< Reserved 1321 }; 1322 uint32_t Value; 1323 } DW12; 1324 union 1325 { 1326 //!< DWORD 13 1327 struct 1328 { 1329 uint32_t AlphaDefaultValue : __CODEGEN_BITFIELD( 0, 9) ; //!< Alpha Default Value 1330 uint32_t Reserved426 : __CODEGEN_BITFIELD(10, 31) ; //!< Reserved 1331 }; 1332 uint32_t Value; 1333 } DW13; 1334 union 1335 { 1336 //!< DWORD 14 1337 struct 1338 { 1339 uint32_t Reserved440 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1340 uint32_t ScalingFactorHeight : __CODEGEN_BITFIELD( 5, 27) ; //!< SCALING_FACTOR_HEIGHT 1341 uint32_t Reserved469 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1342 }; 1343 uint32_t Value; 1344 } DW14; 1345 union 1346 { 1347 //!< DWORD 15 1348 struct 1349 { 1350 uint32_t Reserved480 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1351 uint32_t ScalingFactorWidth : __CODEGEN_BITFIELD( 5, 27) ; //!< SCALING_FACTOR_WIDTH 1352 uint32_t Reserved501 : __CODEGEN_BITFIELD(28, 31) ; //!< Reserved 1353 }; 1354 uint32_t Value; 1355 } DW15; 1356 union 1357 { 1358 //!< DWORD 16 1359 struct 1360 { 1361 uint32_t Reserved512 ; //!< Reserved 1362 }; 1363 uint32_t Value; 1364 } DW16; 1365 union 1366 { 1367 //!< DWORD 17 1368 struct 1369 { 1370 uint32_t Reserved544 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1371 uint32_t OutputFrameSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< Output Frame Surface Base Address 1372 }; 1373 uint32_t Value; 1374 } DW17; 1375 union 1376 { 1377 //!< DWORD 18 1378 struct 1379 { 1380 uint32_t OutputFrameSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Frame Surface Base Address High 1381 uint32_t Reserved592 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1382 }; 1383 uint32_t Value; 1384 } DW18; 1385 union 1386 { 1387 //!< DWORD 19 1388 struct 1389 { 1390 uint32_t Reserved608 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1391 uint32_t OutputFrameSurfaceBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< Output Frame Surface Base Address - Index to Memory Object Control State (MOCS) Tables 1392 uint32_t OutputFrameSurfaceBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< Output Frame Surface Base Address - Arbitration Priority Control 1393 uint32_t OutputFrameSurfaceBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< Output Frame Surface Base Address - Memory Compression Enable 1394 uint32_t OutputFrameSurfaceBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< OUTPUT_FRAME_SURFACE_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 1395 uint32_t Reserved619 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1396 uint32_t OutputFrameSurfaceBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< OUTPUT_FRAME_SURFACE_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1397 uint32_t OutputSurfaceTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< OUTPUT_SURFACE_TILED_MODE 1398 uint32_t Reserved623 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1399 }; 1400 uint32_t Value; 1401 } DW19; 1402 union 1403 { 1404 //!< DWORD 20 1405 struct 1406 { 1407 uint32_t Reserved640 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1408 uint32_t AvsLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Buffer Surface Base Address 1409 }; 1410 uint32_t Value; 1411 } DW20; 1412 union 1413 { 1414 //!< DWORD 21 1415 struct 1416 { 1417 uint32_t AvsLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Buffer Surface Base Address High 1418 uint32_t Reserved688 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1419 }; 1420 uint32_t Value; 1421 } DW21; 1422 union 1423 { 1424 //!< DWORD 22 1425 struct 1426 { 1427 uint32_t Reserved704 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1428 uint32_t AvsLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1429 uint32_t AvsLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Buffer Base Address - Arbitration Priority Control 1430 uint32_t AvsLineBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 1431 uint32_t AvsLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 1432 uint32_t Reserved715 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1433 uint32_t AvsLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1434 uint32_t AvsLineBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< AVS_LINE_BUFFER_TILED_MODE 1435 uint32_t Reserved719 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1436 }; 1437 uint32_t Value; 1438 } DW22; 1439 union 1440 { 1441 //!< DWORD 23 1442 struct 1443 { 1444 uint32_t Reserved736 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1445 uint32_t IefLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Buffer Surface Base Address 1446 }; 1447 uint32_t Value; 1448 } DW23; 1449 union 1450 { 1451 //!< DWORD 24 1452 struct 1453 { 1454 uint32_t IefLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Buffer Surface Base Address High 1455 uint32_t Reserved784 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1456 }; 1457 uint32_t Value; 1458 } DW24; 1459 union 1460 { 1461 //!< DWORD 25 1462 struct 1463 { 1464 uint32_t Reserved800 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1465 uint32_t IefLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1466 uint32_t IefLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Buffer Base Address - Arbitration Priority Control 1467 uint32_t IefLineBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 1468 uint32_t IefLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 1469 uint32_t Reserved811 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1470 uint32_t IefLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1471 uint32_t IefLineBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< IEF_LINE_BUFFER_TILED_MODE 1472 uint32_t Reserved815 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1473 }; 1474 uint32_t Value; 1475 } DW25; 1476 union 1477 { 1478 //!< DWORD 26 1479 struct 1480 { 1481 uint32_t Reserved832 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1482 uint32_t SfdLineBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Buffer Surface Base Address 1483 }; 1484 uint32_t Value; 1485 } DW26; 1486 union 1487 { 1488 //!< DWORD 27 1489 struct 1490 { 1491 uint32_t SfdLineBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Buffer Surface Base Address High 1492 uint32_t Reserved880 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1493 }; 1494 uint32_t Value; 1495 } DW27; 1496 union 1497 { 1498 //!< DWORD 28 1499 struct 1500 { 1501 uint32_t Reserved896 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1502 uint32_t SfdLineBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1503 uint32_t SfdLineBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Buffer Base Address - Arbitration Priority Control 1504 uint32_t SfdLineBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 1505 uint32_t SfdLineBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 1506 uint32_t Reserved907 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1507 uint32_t SfdLineBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1508 uint32_t SfdLineBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< SFD_LINE_BUFFER_TILED_MODE 1509 uint32_t Reserved911 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1510 }; 1511 uint32_t Value; 1512 } DW28; 1513 union 1514 { 1515 //!< DWORD 29 1516 struct 1517 { 1518 uint32_t OutputSurfaceTileWalk : __CODEGEN_BITFIELD( 0, 0) ; //!< OUTPUT_SURFACE_TILE_WALK 1519 uint32_t OutputSurfaceTiled : __CODEGEN_BITFIELD( 1, 1) ; //!< OUTPUT_SURFACE_TILED 1520 uint32_t OutputSurfaceHalfPitchForChroma : __CODEGEN_BITFIELD( 2, 2) ; //!< Output Surface Half Pitch For Chroma 1521 uint32_t OutputSurfacePitch : __CODEGEN_BITFIELD( 3, 19) ; //!< Output Surface Pitch 1522 uint32_t Reserved948 : __CODEGEN_BITFIELD(20, 26) ; //!< Reserved 1523 uint32_t OutputSurfaceInterleaveChromaEnable : __CODEGEN_BITFIELD(27, 27) ; //!< Output Surface Interleave Chroma Enable 1524 uint32_t OutputSurfaceFormat : __CODEGEN_BITFIELD(28, 31) ; //!< Output Surface Format 1525 }; 1526 uint32_t Value; 1527 } DW29; 1528 union 1529 { 1530 //!< DWORD 30 1531 struct 1532 { 1533 uint32_t OutputSurfaceYOffsetForU : __CODEGEN_BITFIELD( 0, 15) ; //!< Output Surface Y Offset For U 1534 uint32_t OutputSurfaceXOffsetForU : __CODEGEN_BITFIELD(16, 31) ; //!< Output Surface X Offset For U 1535 }; 1536 uint32_t Value; 1537 } DW30; 1538 union 1539 { 1540 //!< DWORD 31 1541 struct 1542 { 1543 uint32_t OutputSurfaceYOffsetForV : __CODEGEN_BITFIELD( 0, 13) ; //!< Output Surface Y Offset For V 1544 uint32_t Reserved1006 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1545 uint32_t OutputSurfaceXOffsetForV : __CODEGEN_BITFIELD(16, 29) ; //!< Output Surface X Offset For V 1546 uint32_t Reserved1022 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1547 }; 1548 uint32_t Value; 1549 } DW31; 1550 union 1551 { 1552 //!< DWORD 32 1553 struct 1554 { 1555 uint32_t Reserved1024 ; //!< Reserved 1556 }; 1557 uint32_t Value; 1558 } DW32; 1559 union 1560 { 1561 //!< DWORD 33 1562 struct 1563 { 1564 uint32_t Reserved1056 ; //!< Reserved 1565 }; 1566 uint32_t Value; 1567 } DW33; 1568 union 1569 { 1570 //!< DWORD 34 1571 struct 1572 { 1573 uint32_t SourceStartX : __CODEGEN_BITFIELD( 0, 13) ; //!< SourceStartX 1574 uint32_t Reserved1102 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1575 uint32_t SourceEndX : __CODEGEN_BITFIELD(16, 29) ; //!< SourceEndX 1576 uint32_t Reserved1118 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1577 }; 1578 uint32_t Value; 1579 } DW34; 1580 union 1581 { 1582 //!< DWORD 35 1583 struct 1584 { 1585 uint32_t DestinationStartX : __CODEGEN_BITFIELD( 0, 13) ; //!< DestinationStartx 1586 uint32_t Reserved1134 : __CODEGEN_BITFIELD(14, 15) ; //!< Reserved 1587 uint32_t DestinationEndX : __CODEGEN_BITFIELD(16, 29) ; //!< Destinationendx 1588 uint32_t Reserved1150 : __CODEGEN_BITFIELD(30, 31) ; //!< Reserved 1589 }; 1590 uint32_t Value; 1591 } DW35; 1592 union 1593 { 1594 //!< DWORD 36 1595 struct 1596 { 1597 uint32_t Reserved1160 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1598 uint32_t Xphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Xphaseshift 1599 uint32_t Reserved1174 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1600 }; 1601 uint32_t Value; 1602 } DW36; 1603 union 1604 { 1605 //!< DWORD 37 1606 struct 1607 { 1608 uint32_t Reserved1190 : __CODEGEN_BITFIELD( 0, 4) ; //!< Reserved 1609 uint32_t Yphaseshift : __CODEGEN_BITFIELD( 5, 28) ; //!< Yphaseshift 1610 uint32_t Reserved1206 : __CODEGEN_BITFIELD(29, 31) ; //!< Reserved 1611 }; 1612 uint32_t Value; 1613 } DW37; 1614 union 1615 { 1616 //!< DWORD 38 1617 struct 1618 { 1619 uint32_t Reserved1216 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1620 uint32_t AvsLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< AVS Line Tile Buffer Surface Base Address 1621 }; 1622 uint32_t Value; 1623 } DW38; 1624 union 1625 { 1626 //!< DWORD 39 1627 struct 1628 { 1629 uint32_t AvsLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< AVS Line Tile Buffer Surface Base Address High 1630 uint32_t Reserved1264 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1631 }; 1632 uint32_t Value; 1633 } DW39; 1634 union 1635 { 1636 //!< DWORD 40 1637 struct 1638 { 1639 uint32_t Reserved1280 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1640 uint32_t AvsLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< AVS Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1641 uint32_t AvsLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< AVS Line Tile Buffer Base Address - Arbitration Priority Control 1642 uint32_t AvsLineTileBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 1643 uint32_t AvsLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 1644 uint32_t Reserved1291 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1645 uint32_t AvsLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< AVS_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1646 uint32_t AvsLineTileBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< AVS_LINE_TILE_BUFFER_TILED_MODE 1647 uint32_t Reserved1295 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1648 }; 1649 uint32_t Value; 1650 } DW40; 1651 union 1652 { 1653 //!< DWORD 41 1654 struct 1655 { 1656 uint32_t Reserved1312 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1657 uint32_t IefLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< IEF Line Tile Buffer Surface Base Address 1658 }; 1659 uint32_t Value; 1660 } DW41; 1661 union 1662 { 1663 //!< DWORD 42 1664 struct 1665 { 1666 uint32_t IefLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< IEF Line Tile Buffer Surface Base Address High 1667 uint32_t Reserved1360 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1668 }; 1669 uint32_t Value; 1670 } DW42; 1671 union 1672 { 1673 //!< DWORD 43 1674 struct 1675 { 1676 uint32_t Reserved1376 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1677 uint32_t IefLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< IEF Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1678 uint32_t IefLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< IEF Line Tile Buffer Base Address - Arbitration Priority Control 1679 uint32_t IefLineTileBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 1680 uint32_t IefLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 1681 uint32_t Reserved1387 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1682 uint32_t IefLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< IEF_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1683 uint32_t IefLineTileBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< IEF_LINE_TILE_BUFFER_TILED_MODE 1684 uint32_t Reserved1391 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1685 }; 1686 uint32_t Value; 1687 } DW43; 1688 union 1689 { 1690 //!< DWORD 44 1691 struct 1692 { 1693 uint32_t Reserved1408 : __CODEGEN_BITFIELD( 0, 11) ; //!< Reserved 1694 uint32_t SfdLineTileBufferSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31) ; //!< SFD Line Tile Buffer Surface Base Address 1695 }; 1696 uint32_t Value; 1697 } DW44; 1698 union 1699 { 1700 //!< DWORD 45 1701 struct 1702 { 1703 uint32_t SfdLineTileBufferSurfaceBaseAddressHigh : __CODEGEN_BITFIELD( 0, 15) ; //!< SFD Line Tile Buffer Surface Base Address High 1704 uint32_t Reserved1456 : __CODEGEN_BITFIELD(16, 31) ; //!< Reserved 1705 }; 1706 uint32_t Value; 1707 } DW45; 1708 union 1709 { 1710 //!< DWORD 46 1711 struct 1712 { 1713 uint32_t Reserved1472 : __CODEGEN_BITFIELD( 0, 0) ; //!< Reserved 1714 uint32_t SfdLineTileBufferBaseAddressIndexToMemoryObjectControlStateMocsTables : __CODEGEN_BITFIELD( 1, 6) ; //!< SFD Line Tile Buffer Base Address - Index to Memory Object Control State (MOCS) Tables 1715 uint32_t SfdLineTileBufferBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD( 7, 8) ; //!< SFD Line Tile Buffer Base Address - Arbitration Priority Control 1716 uint32_t SfdLineTileBufferBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD( 9, 9) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 1717 uint32_t SfdLineTileBufferBaseAddressMemoryCompressionMode : __CODEGEN_BITFIELD(10, 10) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 1718 uint32_t Reserved1483 : __CODEGEN_BITFIELD(11, 11) ; //!< Reserved 1719 uint32_t SfdLineTileBufferBaseAddressRowStoreScratchBufferCacheSelect : __CODEGEN_BITFIELD(12, 12) ; //!< SFD_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 1720 uint32_t SfdLineTileBufferTiledMode : __CODEGEN_BITFIELD(13, 14) ; //!< SFD_LINE_TILE_BUFFER_TILED_MODE 1721 uint32_t Reserved1487 : __CODEGEN_BITFIELD(15, 31) ; //!< Reserved 1722 }; 1723 uint32_t Value; 1724 } DW46; 1725 1726 union 1727 { 1728 //!< DWORD 47 1729 struct 1730 { 1731 uint32_t Reserved1729 : __CODEGEN_BITFIELD(0, 11); //!< Reserved 1732 uint32_t HistogramSurfaceBaseAddress : __CODEGEN_BITFIELD(12, 31); //!< Histogram Surface Base Address 1733 }; 1734 uint32_t Value; 1735 } DW47; 1736 union 1737 { 1738 //!< DWORD 48 1739 struct 1740 { 1741 uint32_t HistogramSurfaceBaseAddressHigh : __CODEGEN_BITFIELD(0, 15); //!< Histogram Surface Base Address High 1742 uint32_t Reserved1740 : __CODEGEN_BITFIELD(16, 31); //!< Reserved 1743 }; 1744 uint32_t Value; 1745 } DW48; 1746 union 1747 { 1748 //!< DWORD 49 1749 struct 1750 { 1751 uint32_t HistogramBaseAddressData : __CODEGEN_BITFIELD(0, 0); //!< Histogram Base Address - Resevered Data 1752 uint32_t HistogramBaseAddressMOCSIndex : __CODEGEN_BITFIELD(1, 6); //!< Histogram Base Address - Index to Memory Object Control State (MOCS) Tables 1753 uint32_t HistogramBaseAddressArbitrationPriorityControl : __CODEGEN_BITFIELD(7, 8); //!< Histogram Base Address - Arbitration Priority Control 1754 uint32_t HistogramBaseAddressMemoryCompressionEnable : __CODEGEN_BITFIELD(9, 9); //!< Histogram Base Address - Memory Compression Enable 1755 uint32_t HistogramBaseAddressMemoryCompressionType : __CODEGEN_BITFIELD(10, 10); //!< Histogram Base Address - Memory Compression Type 1756 uint32_t Reserved1754 : __CODEGEN_BITFIELD(11, 11); //!< Reserved 1757 uint32_t HistogramBaseAddressCacheSelect : __CODEGEN_BITFIELD(12, 12); //!< Histogram Base Address - Cache Select 1758 uint32_t HistogramTiledMode : __CODEGEN_BITFIELD(13, 14); //!< Histogram Tiled Mode 1759 uint32_t Reserved1757 : __CODEGEN_BITFIELD(15, 31); //!< Reserved 1760 }; 1761 uint32_t Value; 1762 } DW49; 1763 1764 //! \name Local enumerations 1765 1766 enum SUBOPCODEB 1767 { 1768 SUBOPCODEB_SFCSTATE = 1, //!< No additional details 1769 }; 1770 1771 enum SUBOPCODEA 1772 { 1773 SUBOPCODEA_COMMON = 0, //!< No additional details 1774 }; 1775 1776 enum MEDIA_COMMAND_OPCODE 1777 { 1778 MEDIA_COMMAND_OPCODE_MEDIAHCPSFCMODE = 9, //!< No additional details 1779 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 1780 }; 1781 1782 enum PIPELINE 1783 { 1784 PIPELINE_MEDIA = 2, //!< No additional details 1785 }; 1786 1787 enum COMMAND_TYPE 1788 { 1789 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 1790 }; 1791 1792 //! \brief SFC_PIPE_MODE 1793 //! \details 1794 //! Note: for SFC Pipe mode set to VE-to-SFC AVS mode. 1795 //! IECP pipeline mode MUST be enabled. 1796 //! However, each sub-IECP feature can be turned on/off independently. 1797 enum SFC_PIPE_MODE 1798 { 1799 SFC_PIPE_MODE_UNNAMED0 = 0, //!< VD-to-SFC AVS 1800 SFC_PIPE_MODE_UNNAMED1 = 1, //!< VE-to-SFC AVS + IEF + Rotation 1801 SFC_PIPE_MODE_UNNAMED2 = 2, //!< HCP-to-SFC AVS 1802 SFC_PIPE_MODE_UNNAMED3 = 3, //!< Reserved 1803 SFC_PIPE_MODE_UNNAMED_4 = 4, //!< VE-to-SFC Integral Image 1804 }; 1805 1806 //! \brief SFC_INPUT_CHROMA_SUB_SAMPLING 1807 //! \details 1808 //! This field shall be programmed according to video modes used in VDBOX. 1809 //! NOTE: SFC supports progressive input and output only (Interlaced/MBAFF 1810 //! is not supported). 1811 //! <table border="1"> 1812 //! <tbody> 1813 //! <tr> 1814 //! <td>Video Mode</td> 1815 //! <td>Surface Format</td> 1816 //! <td>SFC Input Chroma Sub-Sampling</td> 1817 //! <td>VD/VE Input Ordering Mode</td> 1818 //! </tr> 1819 //! <tr> 1820 //! <td>VC1 w/o LF and w/o OS Note: VC1 LF applies for ILDB</td> 1821 //! <td>420 (NV12)</td> 1822 //! <td>1</td> 1823 //! <td>0</td> 1824 //! </tr> 1825 //! <tr> 1826 //! <td>VC1 w/ LF or w/ OS or w/ both Note: VC1 LF applies for ILDB</td> 1827 //! <td></td> 1828 //! <td>INVALID with SFC</td> 1829 //! <td>INVALID with SFC</td> 1830 //! </tr> 1831 //! <tr> 1832 //! <td>AVC w/o LF</td> 1833 //! <td>Monochrome</td> 1834 //! <td>0</td> 1835 //! <td>0</td> 1836 //! </tr> 1837 //! <tr> 1838 //! <td>AVC w/o LF</td> 1839 //! <td>420 (NV12)</td> 1840 //! <td>1</td> 1841 //! <td>0</td> 1842 //! </tr> 1843 //! <tr> 1844 //! <td>AVC with LF</td> 1845 //! <td>Monochrome</td> 1846 //! <td>0</td> 1847 //! <td>1</td> 1848 //! </tr> 1849 //! <tr> 1850 //! <td>AVC/VP8 with LF </td> 1851 //! <td>420 (NV12)</td> 1852 //! <td>1</td> 1853 //! <td>1</td> 1854 //! </tr> 1855 //! <tr> 1856 //! <td>VP8 w/o LF</td> 1857 //! <td>420 (NV12)</td> 1858 //! <td>1</td> 1859 //! <td>4</td> 1860 //! </tr> 1861 //! <tr> 1862 //! <td>JPEG (YUV Interleaved)</td> 1863 //! <td>Monochrome</td> 1864 //! <td>0</td> 1865 //! <td>2</td> 1866 //! </tr> 1867 //! <tr> 1868 //! <td>JPEG (YUV Interleaved)</td> 1869 //! <td>420</td> 1870 //! <td>1</td> 1871 //! <td>3</td> 1872 //! </tr> 1873 //! <tr> 1874 //! <td>JPEG (YUV Interleaved)</td> 1875 //! <td>422H_2Y</td> 1876 //! <td>2</td> 1877 //! <td>2</td> 1878 //! </tr> 1879 //! <tr> 1880 //! <td>JPEG (YUV Interleaved)</td> 1881 //! <td>422H_4Y</td> 1882 //! <td>2</td> 1883 //! <td>3</td> 1884 //! </tr> 1885 //! <tr> 1886 //! <td>JPEG (YUV Interleaved)</td> 1887 //! <td>444</td> 1888 //! <td>4</td> 1889 //! <td>2</td> 1890 //! </tr> 1891 //! </tbody> 1892 //! </table> 1893 //! This field shall be programmed according to Image enhancement modes used 1894 //! in VEBOX. 1895 //! 1896 //! <table border="1"> 1897 //! <tbody> 1898 //! <tr> 1899 //! <td>VEBOX MODE</td> 1900 //! <td>Surface Format</td> 1901 //! <td>SFC Input Chroma Sub Sampling</td> 1902 //! <td>VD/VE Input Ordering Mode</td> 1903 //! </tr> 1904 //! <tr> 1905 //! <td>Legacy DN/DI/IECP features</td> 1906 //! <td>Monochrome</td> 1907 //! <td>0</td> 1908 //! <td>0</td> 1909 //! </tr> 1910 //! <tr> 1911 //! <td>Legacy DN/DI/IECP features</td> 1912 //! <td>420 (NV12)</td> 1913 //! <td>1</td> 1914 //! <td>0</td> 1915 //! </tr> 1916 //! <tr> 1917 //! <td>Legacy DN/DI/IECP features</td> 1918 //! <td>422H</td> 1919 //! <td>2</td> 1920 //! <td>0</td> 1921 //! </tr> 1922 //! <tr> 1923 //! <td>Legacy DN/DI/IECP features</td> 1924 //! <td>444</td> 1925 //! <td>4</td> 1926 //! <td>0</td> 1927 //! </tr> 1928 //! <tr> 1929 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1930 //! <td>Monochrome</td> 1931 //! <td>0</td> 1932 //! <td>1</td> 1933 //! </tr> 1934 //! <tr> 1935 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1936 //! <td>420 (NV12)</td> 1937 //! <td>1</td> 1938 //! <td>1</td> 1939 //! </tr> 1940 //! <tr> 1941 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1942 //! <td>422H</td> 1943 //! <td>2</td> 1944 //! <td>1</td> 1945 //! </tr> 1946 //! <tr> 1947 //! <td>Capture/Camera pipe enabled(Demosaic)</td> 1948 //! <td>444</td> 1949 //! <td>4</td> 1950 //! <td>1</td> 1951 //! </tr> 1952 //! </tbody> 1953 //! </table> 1954 enum SFC_INPUT_CHROMA_SUB_SAMPLING 1955 { 1956 SFC_INPUT_CHROMA_SUB_SAMPLING_400 = 0, //!< SFC to insert UV channels 1957 SFC_INPUT_CHROMA_SUB_SAMPLING_420 = 1, //!< No additional details 1958 SFC_INPUT_CHROMA_SUB_SAMPLING_422HORIZONATAL = 2, //!< VD: 2:1:1 1959 SFC_INPUT_CHROMA_SUB_SAMPLING_4_4_4PROGRESSIVEINTERLEAVED = 4, //!< No additional details 1960 }; 1961 1962 //! \brief VDVE_INPUT_ORDERING_MODE 1963 //! \details 1964 //! <ul> 1965 //! <li>VD mode: (SFC pipe mode set as "0")</li> 1966 //! <li> VE mode: (pipe mode set as "1 and 4")</li> 1967 //! </ul> 1968 //! For values for each mode, please refer to the table below: 1969 enum VDVE_INPUT_ORDERING_MODE 1970 { 1971 VDVE_INPUT_ORDERING_MODE_UNNAMED0 = 0, //!< 16x16 block z-scan order - no shift 1972 //!< 16x16 block HEVC Decoderrow-scan order -8 pixel shift upward 1973 //!< 8x4 block column order, 64 pixel column 1974 //!< 16x16 block z-scan order - 4 pixels shift upward 1975 VDVE_INPUT_ORDERING_MODE_UNNAMED1 = 1, //!< 32x32block HEVC Decoderrow-scan order -8 pixel shift upward 1976 //!< 4x4 block column order, 64 pixel column 1977 VDVE_INPUT_ORDERING_MODE_UNNAMED2 = 2, //!< 8x8 block jpeg z-scan order 1978 //!< No additional details 1979 //!< 8x4 block column order, 128 pixel column 1980 VDVE_INPUT_ORDERING_MODE_UNNAMED3 = 3, //!< 16x16 block jpeg z-scan order 1981 //!< No additional details 1982 //!< 4x4 block column order, 128 pixel column 1983 VDVE_INPUT_ORDERING_MODE_UNNAMED_4 = 4, //!< 16x16 block VP8 row-scan order - no shift 1984 //!< 64x64 block VP9 Encoderrow-scan order- 8 pixel shift upward 1985 }; 1986 1987 //! \brief OUTPUT_SURFACE_FORMAT_TYPE 1988 //! \details 1989 //! SFC output surface format type. 1990 enum OUTPUT_SURFACE_FORMAT_TYPE 1991 { 1992 OUTPUT_SURFACE_FORMAT_TYPE_AYUV = 0, //!< AYUV 4:4:4 (8:8:8:8 MSB-A:Y:U:V) 1993 OUTPUT_SURFACE_FORMAT_TYPE_A8B8G8R8 = 1, //!< RGBA8 4:4:4:4 (8:8:8:8 MSB-A:B:G:R) 1994 OUTPUT_SURFACE_FORMAT_TYPE_A2R10G10B10 = 2, //!< RGBA10 10:10:10:2 (2:10:10:10 MSB-A:R:G:B) 1995 OUTPUT_SURFACE_FORMAT_TYPE_R5G6B5 = 3, //!< RGB 5:6:5 (5:6:5 MSB-R:G:B) 1996 OUTPUT_SURFACE_FORMAT_TYPE_NV12 = 4, //!< Planar NV12 4:2:0 8-bit 1997 OUTPUT_SURFACE_FORMAT_TYPE_YUYV = 5, //!< Packed YUYV 4:2:2 8-bit 1998 OUTPUT_SURFACE_FORMAT_TYPE_UYVY = 6, //!< Packed UYVY 4:2:2 8-bit 1999 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_32 = 7, //!< Packed integral Image 32-bit 2000 OUTPUT_SURFACE_FORMAT_TYPE_INTEGRAL_64 = 8, //!< Packed integral Image 64-bit 2001 OUTPUT_SURFACE_FORMAT_TYPE_P016 = 9, //!< P016 format 2002 OUTPUT_SURFACE_FORMAT_TYPE_Y216 = 10, //!< Y210 / Y216 FormatBitDepth = 0 => Y210BitDepth = 1 => Y216 2003 OUTPUT_SURFACE_FORMAT_TYPE_Y416 = 11, //!< Y410 / Y416 FormatBitDepth = 0 => Y410BitDepth = 1 => Y416 2004 }; 2005 2006 //! \brief RGBA_CHANNEL_SWAP_ENABLE 2007 //! \details 2008 //! This bit should only be used with RGB output formats and CSC conversion 2009 //! is turned on. When this bit is set, 2010 //! the R and B channels are swapped into the output RGB channels as 2011 //! shown in the following table: 2012 //! <table> 2013 //! <tr> 2014 //! <th>Name</th> 2015 //! <th>Bits</th> 2016 //! <th>MSB Color Order</th> 2017 //! <th>Swapped</th> 2018 //! </tr> 2019 //! <tr> 2020 //! <td>RGBA8</td> 2021 //! <td>8:8:8:8</td> 2022 //! <td>A:B:G:R</td> 2023 //! <td>A:R:G:B</td> 2024 //! </tr> 2025 //! <tr> 2026 //! <td>RGBA10</td> 2027 //! <td>2:10:10:10</td> 2028 //! <td>A:R:G:B</td> 2029 //! <td>A:B:G:R</td> 2030 //! </tr> 2031 //! <tr> 2032 //! <td>RGB 5:6:5</td> 2033 //! <td>5:6:5</td> 2034 //! <td>R:G:B</td> 2035 //! <td>B:G:R</td> 2036 //! </tr> 2037 //! </table> 2038 enum RGBA_CHANNEL_SWAP_ENABLE 2039 { 2040 RGBA_CHANNEL_SWAP_ENABLE_UNNAMED0 = 0, //!< No additional details 2041 }; 2042 2043 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 2044 //! \details 2045 //! This field specifies the fractional position of the bilinear filter for 2046 //! chroma downsampling. In the Y-axis. 2047 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION 2048 { 2049 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 2050 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 2051 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_1_4_28 = 2, //!< 2 (fraction_in_integer) 2052 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 2053 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 2054 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 2055 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_3_4_68 = 6, //!< 6 (fraction_in_integer) 2056 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2057 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_VERTICAL_DIRECTION_88 = 8, //!< No additional details 2058 }; 2059 2060 //! \brief OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2061 //! \details 2062 //! This field specifies the fractional position of the bilinear filter for 2063 //! chroma downsampling. In the X-axis. 2064 enum OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION 2065 { 2066 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_08_LEFTFULLPIXEL = 0, //!< 0 (fraction_in_integer) 2067 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_18 = 1, //!< 1 (fraction_in_integer) 2068 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_1_4_28 = 2, //!< 2 (fraction_in_integer) 2069 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_38 = 3, //!< 3 (fraction_in_integer) 2070 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_12_48 = 4, //!< 4 (fraction_in_integer) 2071 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_58 = 5, //!< 5 (fraction_in_integer) 2072 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_3_4_68 = 6, //!< 6 (fraction_in_integer) 2073 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_78 = 7, //!< 7 (fraction_in_integer) 2074 OUTPUT_CHROMA_DOWNSAMPLING_CO_SITING_POSITION_HORIZONTAL_DIRECTION_88 = 8, //!< No additional details 2075 }; 2076 2077 //! \brief INPUT_COLOR_SPACE__0_YUV1__RGB 2078 //! \details 2079 //! THis specifies the color space of the input format. RGB is valid only 2080 //! with the VE-SFC mode. 2081 enum INPUT_COLOR_SPACE__0_YUV1__RGB 2082 { 2083 INPUT_COLOR_SPACE_0_YUV1_RGB_YUVCOLORSPACE = 0, //!< No additional details 2084 INPUT_COLOR_SPACE_0_YUV1_RGB_RGBCOLORSPACE = 1, //!< No additional details 2085 }; 2086 2087 //! \brief IEF_ENABLE 2088 //! \details 2089 //! Restriction : For Integral Image Mode and VD Mode, this field is 2090 //! Reserved and MBZ. 2091 enum IEF_ENABLE 2092 { 2093 IEF_ENABLE_DISABLE = 0, //!< IEF Filter is Disabled 2094 IEF_ENABLE_ENABLE = 1, //!< IEF Filter is Enabled 2095 }; 2096 2097 //! \brief IEF4SMOOTH_ENABLE_ 2098 //! \details 2099 //! Restriction : For Integral Image Mode, this field is Reserved and MBZ. 2100 enum IEF4SMOOTH_ENABLE_ 2101 { 2102 IEF4SMOOTH_ENABLE_UNNAMED0 = 0, //!< IEF is operating as a content adaptive detail filter based on 5x5 region. 2103 IEF4SMOOTH_ENABLE_UNNAMED1 = 1, //!< IEF is operating as a content adaptive smooth filter based on 3x3 region 2104 }; 2105 2106 //! \brief AVS_FILTER_MODE 2107 //! \details 2108 //! In VD-to-SFC mode, value of 1 is not allowed. 2109 enum AVS_FILTER_MODE 2110 { 2111 AVS_FILTER_MODE_5X5POLY_PHASEFILTERBILINEAR_ADAPTIVE = 0, //!< No additional details 2112 AVS_FILTER_MODE_8X8POLY_PHASEFILTERBILINEAR_ADAPTIVE = 1, //!< No additional details 2113 AVS_FILTER_MODE_BILINEARFILTERONLY = 2, //!< No additional details 2114 }; 2115 2116 //! \brief ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2117 //! \details 2118 //! The field can be enabled if 8-tap Adaptive filter mode is on. Else it 2119 //! should be disabled. 2120 enum ADAPTIVE_FILTER_FOR_ALL_CHANNELS 2121 { 2122 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_DISABLEADAPTIVEFILTERONUVRBCHANNELS = 0, //!< No additional details 2123 ADAPTIVE_FILTER_FOR_ALL_CHANNELS_ENABLEADAPTIVEFILTERONUVRBCHANNELS = 1, //!< 8-tap Adaptive Filter Mode is on 2124 }; 2125 2126 enum AVS_SCALING_ENABLE 2127 { 2128 AVS_SCALING_ENABLE_DISABLE = 0, //!< The scaling factor is ignored and a scaling ratio of 1:1 is assumed. 2129 AVS_SCALING_ENABLE_ENABLE = 1, //!< No additional details 2130 }; 2131 2132 enum BYPASS_Y_ADAPTIVE_FILTERING 2133 { 2134 BYPASS_Y_ADAPTIVE_FILTERING_ENABLEYADAPTIVEFILTERING = 0, //!< No additional details 2135 BYPASS_Y_ADAPTIVE_FILTERING_DISABLEYADAPTIVEFILTERING = 1, //!< The Y direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2136 }; 2137 2138 enum BYPASS_X_ADAPTIVE_FILTERING 2139 { 2140 BYPASS_X_ADAPTIVE_FILTERING_ENABLEXADAPTIVEFILTERING = 0, //!< No additional details 2141 BYPASS_X_ADAPTIVE_FILTERING_DISABLEXADAPTIVEFILTERING = 1, //!< The X direction will use Default Sharpness Level to blend between the smooth and sharp filters rather than the calculated value. 2142 }; 2143 2144 //! \brief ROTATION_MODE 2145 //! \details 2146 //! <p>SFC rotation (90, 180 and 270) should be set only on VEBox input mode 2147 //! and SFC output set to TileY.</p> 2148 //! Restriction: 2149 //! <ul> 2150 //! <li>For Integral Image Mode, this field is Reserved and MBZ.</li> 2151 //! <li>For VDBox Mode, this field is Reserved and MBZ.</li> 2152 //! <li>For linear or TileX SFC output, this field is Reserved and 2153 //! MBZ.</li> 2154 //! </ul> 2155 enum ROTATION_MODE 2156 { 2157 ROTATION_MODE_0_DEGREES = 0, //!< No additional details 2158 ROTATION_MODE_90CLOCKWISE = 1, //!< No additional details 2159 ROTATION_MODE_180CLOCKWISE = 2, //!< No additional details 2160 ROTATION_MODE_270CLOCKWISE = 3, //!< No additional details 2161 }; 2162 2163 //! \brief BITDEPTH 2164 //! \details 2165 //! This field is valid only for output formats P016/Y216/Y416. This field 2166 //! is used to specify how many of the LSB bits have valid data. 2167 enum BITDEPTH 2168 { 2169 BITDEPTH_10BITFORMAT = 0, //!< Higher 10 bits are valid and lower 6 bits are 0 2170 }; 2171 2172 //! \brief SCALING_FACTOR_HEIGHT 2173 //! \details 2174 //! <p>This field specifies the scaling ratio of the vertical sizes between 2175 //! the crop/source region and the scaled region. 2176 //! The destination pixel coordinate, y-axis, is multiplied with this 2177 //! scaling factor to mapping back to the source input pixel coordinate.</p> 2178 //! <p>The field specifies the ratio of crop height resolution/ scaled 2179 //! height resolution. This implies 1/<i>sf<sub>u</sub></i> in the 2180 //! equation.</p> 2181 enum SCALING_FACTOR_HEIGHT 2182 { 2183 SCALING_FACTOR_HEIGHT_UNNAMED0 = 0, //!< Reserved 2184 }; 2185 2186 //! \brief SCALING_FACTOR_WIDTH 2187 //! \details 2188 //! <p>This field specifies the scaling ratio of the horizontal sizes 2189 //! between the crop/source region and the scaled region. 2190 //! The destination pixel coordinate, x-axis, is multiplied with this 2191 //! scaling factor to mapping back to the source input pixel coordinate. 2192 //! </p> 2193 //! <p>The field specifies the ratio of crop width resolution/ scaled 2194 //! width resolution. This implies 1/<i>sf<sub>u</sub></i> in the equations 2195 //! above.</p> 2196 enum SCALING_FACTOR_WIDTH 2197 { 2198 SCALING_FACTOR_WIDTH_UNNAMED0 = 0, //!< Reserved 2199 }; 2200 2201 //! \brief OUTPUT_FRAME_SURFACE_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2202 //! \details 2203 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2204 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2205 //! vertical from horizontal compression. Please refer to vol1a</span><b 2206 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2207 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2208 //! chapter - section</b><span style="color: rgb(35, 35, 35); font-family: 2209 //! Arial, sans-serif; font-size: 13.3333330154419px; line-height: 2210 //! normal;">media Memory Compression for more details.</span> 2211 enum OUTPUT_FRAME_SURFACE_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2212 { 2213 OUTPUT_FRAME_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_VERTICALCOMPRESSION = 0, //!< No additional details 2214 OUTPUT_FRAME_SURFACE_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSION = 1, //!< No additional details 2215 }; 2216 2217 //! \brief OUTPUT_FRAME_SURFACE_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2218 //! \details 2219 //! This must be set to 0 2220 enum OUTPUT_FRAME_SURFACE_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2221 { 2222 OUTPUT_FRAME_SURFACE_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_DISABLE = 0, //!< This field must be programmed to 0 2223 }; 2224 2225 //! \brief OUTPUT_SURFACE_TILED_MODE 2226 //! \details 2227 //! <b>For Media Surfaces:</b> 2228 //! This field specifies the tiled resource mode. 2229 enum OUTPUT_SURFACE_TILED_MODE 2230 { 2231 OUTPUT_SURFACE_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2232 OUTPUT_SURFACE_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2233 OUTPUT_SURFACE_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2234 }; 2235 2236 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2237 //! \details 2238 //! This bit control memory compression for this surface 2239 enum AVS_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2240 { 2241 AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2242 }; 2243 2244 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2245 //! \details 2246 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2247 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2248 //! vertical from horizontal compression. Please refer to vol1a�</span><b 2249 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2250 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2251 //! chapter - section</b><span style="color: rgb(35, 35, 35); font-family: 2252 //! Arial, sans-serif; font-size: 13.3333330154419px; line-height: 2253 //! normal;">�media Memory Compression for more details.</span> 2254 enum AVS_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2255 { 2256 AVS_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_HORIZONTALCOMPRESSIONMODE = 0, //!< No additional details 2257 }; 2258 2259 //! \brief AVS_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2260 //! \details 2261 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2262 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2263 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2264 //! or to LLC.</span> 2265 enum AVS_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2266 { 2267 AVS_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2268 }; 2269 2270 //! \brief AVS_LINE_BUFFER_TILED_MODE 2271 //! \details 2272 //! <b>For Media Surfaces:</b> 2273 //! This field specifies the tiled resource mode. 2274 enum AVS_LINE_BUFFER_TILED_MODE 2275 { 2276 AVS_LINE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2277 AVS_LINE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2278 AVS_LINE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2279 }; 2280 2281 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2282 //! \details 2283 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2284 //! font-size: 13.3333330154419px; line-height: normal;">Memory compression 2285 //! is not supported for this surface</span></p> 2286 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2287 //! font-size: 13.3333330154419px; line-height: normal;">Must be 2288 //! 0.</span></p> 2289 //! <p></p> 2290 enum IEF_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2291 { 2292 IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2293 }; 2294 2295 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2296 //! \details 2297 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2298 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2299 //! vertical from horizontal compression. Please refer to vol1a�</span><b 2300 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2301 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2302 //! chapter - section</b><span style="color: rgb(35, 35, 35); font-family: 2303 //! Arial, sans-serif; font-size: 13.3333330154419px; line-height: 2304 //! normal;">�media Memory Compression for more details.</span> 2305 enum IEF_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2306 { 2307 IEF_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2308 }; 2309 2310 //! \brief IEF_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2311 //! \details 2312 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2313 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2314 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2315 //! or to LLC.</span> 2316 enum IEF_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2317 { 2318 IEF_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2319 }; 2320 2321 //! \brief IEF_LINE_BUFFER_TILED_MODE 2322 //! \details 2323 //! <b>For Media Surfaces:</b> 2324 //! This field specifies the tiled resource mode. 2325 enum IEF_LINE_BUFFER_TILED_MODE 2326 { 2327 IEF_LINE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2328 IEF_LINE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2329 IEF_LINE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2330 }; 2331 2332 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2333 //! \details 2334 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2335 //! font-size: 13.3333330154419px; line-height: normal;">Memory compression 2336 //! is not supported for this surface</span></p> 2337 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2338 //! font-size: 13.3333330154419px; line-height: normal;">Must be 2339 //! 0.</span></p> 2340 //! <p></p> 2341 enum SFD_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2342 { 2343 SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2344 }; 2345 2346 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2347 //! \details 2348 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2349 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2350 //! vertical from horizontal compression. Please refer to vol1a </span><b 2351 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2352 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2353 //! chapter - section</b><span style="color: rgb(35, 35, 35); font-family: 2354 //! Arial, sans-serif; font-size: 13.3333330154419px; line-height: normal;"> 2355 //! media Memory Compression for more details.</span> 2356 enum SFD_LINE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2357 { 2358 SFD_LINE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2359 }; 2360 2361 //! \brief SFD_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2362 //! \details 2363 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2364 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2365 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2366 //! or to LLC.</span> 2367 enum SFD_LINE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2368 { 2369 SFD_LINE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2370 }; 2371 2372 //! \brief SFD_LINE_BUFFER_TILED_MODE 2373 //! \details 2374 //! <b>For Media Surfaces:</b> 2375 //! This field specifies the tiled resource mode. 2376 enum SFD_LINE_BUFFER_TILED_MODE 2377 { 2378 SFD_LINE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2379 SFD_LINE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2380 SFD_LINE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2381 }; 2382 2383 //! \brief OUTPUT_SURFACE_TILE_WALK 2384 //! \details 2385 //! This field specifies the type of memory tiling (XMajor or YMajor) 2386 //! employed to tile this surface. See <i>Memory Interface Functions</i> for 2387 //! details on memory tiling and restrictions. 2388 enum OUTPUT_SURFACE_TILE_WALK 2389 { 2390 OUTPUT_SURFACE_TILE_WALK_TILEWALKXMAJOR = 0, //!< No additional details 2391 OUTPUT_SURFACE_TILE_WALK_TILEWALKYMAJOR = 1, //!< No additional details 2392 }; 2393 2394 //! \brief OUTPUT_SURFACE_TILED 2395 //! \details 2396 //! This field specifies whether the surface is tiled. 2397 enum OUTPUT_SURFACE_TILED 2398 { 2399 OUTPUT_SURFACE_TILED_FALSE = 0, //!< Linear 2400 OUTPUT_SURFACE_TILED_TRUE = 1, //!< Tiled 2401 }; 2402 2403 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2404 //! \details 2405 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2406 //! font-size: 13.3333330154419px; line-height: normal;">Memory compression 2407 //! is not supported for this surface</span></p> 2408 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2409 //! font-size: 13.3333330154419px; line-height: normal;">Must be 2410 //! 0.</span></p> 2411 //! <p></p> 2412 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2413 { 2414 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2415 }; 2416 2417 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2418 //! \details 2419 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2420 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2421 //! vertical from horizontal compression. Please refer to vol1a </span><b 2422 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2423 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2424 //! chapter - section</b><span style="color: rgb(35, 35, 35); font-family: 2425 //! Arial, sans-serif; font-size: 13.3333330154419px; line-height: normal;"> 2426 //! media Memory Compression for more details.</span> 2427 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2428 { 2429 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2430 }; 2431 2432 //! \brief AVS_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2433 //! \details 2434 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2435 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2436 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2437 //! or to LLC.</span> 2438 enum AVS_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2439 { 2440 AVS_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2441 }; 2442 2443 //! \brief AVS_LINE_TILE_BUFFER_TILED_MODE 2444 //! \details 2445 //! <b>For Media Surfaces:</b> 2446 //! This field specifies the tiled resource mode. 2447 enum AVS_LINE_TILE_BUFFER_TILED_MODE 2448 { 2449 AVS_LINE_TILE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2450 AVS_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2451 AVS_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2452 }; 2453 2454 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2455 //! \details 2456 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2457 //! font-size: 13.3333330154419px; line-height: normal;">Memory compression 2458 //! is not supported for this surface</span></p> 2459 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2460 //! font-size: 13.3333330154419px; line-height: normal;">Must be 2461 //! 0.</span></p> 2462 //! <p></p> 2463 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2464 { 2465 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2466 }; 2467 2468 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2469 //! \details 2470 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2471 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2472 //! vertical from horizontal compression. Please refer to vol1a </span><b 2473 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2474 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2475 //! chapter - section</b><span style="color: rgb(35, 35, 35); font-family: 2476 //! Arial, sans-serif; font-size: 13.3333330154419px; line-height: normal;"> 2477 //! media Memory Compression for more details.</span> 2478 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2479 { 2480 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2481 }; 2482 2483 //! \brief IEF_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2484 //! \details 2485 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2486 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2487 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2488 //! or to LLC.</span> 2489 enum IEF_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2490 { 2491 IEF_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2492 }; 2493 2494 //! \brief IEF_LINE_TILE_BUFFER_TILED_MODE 2495 //! \details 2496 //! <b>For Media Surfaces:</b> 2497 //! This field specifies the tiled resource mode. 2498 enum IEF_LINE_TILE_BUFFER_TILED_MODE 2499 { 2500 IEF_LINE_TILE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2501 IEF_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2502 IEF_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2503 }; 2504 2505 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2506 //! \details 2507 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2508 //! font-size: 13.3333330154419px; line-height: normal;">Memory compression 2509 //! is not supported for this surface</span></p> 2510 //! <p><span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2511 //! font-size: 13.3333330154419px; line-height: normal;">Must be 2512 //! 0.</span></p> 2513 //! <p></p> 2514 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_ENABLE 2515 { 2516 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_ENABLE_DISABLE = 0, //!< No additional details 2517 }; 2518 2519 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2520 //! \details 2521 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2522 //! font-size: 13.3333330154419px; line-height: normal;">Distinguishes 2523 //! vertical from horizontal compression. Please refer to vol1a </span><b 2524 //! style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2525 //! font-size: 13.3333330154419px; line-height: normal;">Memory Data Formats 2526 //! chapter - section</b><span style="color: rgb(35, 35, 35); font-family: 2527 //! Arial, sans-serif; font-size: 13.3333330154419px; line-height: normal;"> 2528 //! media Memory Compression for more details.</span> 2529 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS__MEMORY_COMPRESSION_MODE 2530 { 2531 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_MEMORY_COMPRESSION_MODE_UNNAMED0 = 0, //!< No additional details 2532 }; 2533 2534 //! \brief SFD_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2535 //! \details 2536 //! <span style="color: rgb(35, 35, 35); font-family: Arial, sans-serif; 2537 //! font-size: 13.3333330154419px; line-height: normal;">This field controls 2538 //! if the Row Store is going to store inside Media Cache (rowstore cache) 2539 //! or to LLC.</span> 2540 enum SFD_LINE_TILE_BUFFER_BASE_ADDRESS__ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT 2541 { 2542 SFD_LINE_TILE_BUFFER_BASE_ADDRESS_ROW_STORE_SCRATCH_BUFFER_CACHE_SELECT_LLC = 0, //!< Buffer going to LLC 2543 }; 2544 2545 //! \brief SFD_LINE_TILE_BUFFER_TILED_MODE 2546 //! \details 2547 //! <b>For Media Surfaces:</b> 2548 //! This field specifies the tiled resource mode. 2549 enum SFD_LINE_TILE_BUFFER_TILED_MODE 2550 { 2551 SFD_LINE_TILE_BUFFER_TILED_MODE_TRMODENONE = 0, //!< No tiled resource 2552 SFD_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYF = 1, //!< 4KB tiled resources 2553 SFD_LINE_TILE_BUFFER_TILED_MODE_TRMODETILEYS = 2, //!< 64KB tiled resources 2554 }; 2555 2556 //! \name Initializations 2557 2558 //! \brief Explicit member initialization function 2559 SFC_STATE_CMD(); 2560 2561 static const size_t dwSize = 50; 2562 static const size_t byteSize = 200; 2563 }; 2564 2565 //! 2566 //! \brief SFC_AVS_LUMA_Coeff_Table 2567 //! \details 2568 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2569 //! each frame once the lock request is granted. 2570 //! 2571 struct SFC_AVS_LUMA_Coeff_Table_CMD 2572 { 2573 union 2574 { 2575 //!< DWORD 0 2576 struct 2577 { 2578 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2579 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2580 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2581 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2582 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2583 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2584 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2585 }; 2586 uint32_t Value; 2587 } DW0; 2588 union 2589 { 2590 //!< DWORD 1 2591 struct 2592 { 2593 uint32_t Table0XFilterCoefficientN0 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],0] 2594 uint32_t Table0YFilterCoefficientN0 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],0] 2595 uint32_t Table0XFilterCoefficientN1 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],1] 2596 uint32_t Table0YFilterCoefficientN1 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],1] 2597 }; 2598 uint32_t Value; 2599 } DW1; 2600 union 2601 { 2602 //!< DWORD 2 2603 struct 2604 { 2605 uint32_t Table0XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],2] 2606 uint32_t Table0YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],2] 2607 uint32_t Table0XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],3] 2608 uint32_t Table0YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],3] 2609 }; 2610 uint32_t Value; 2611 } DW2; 2612 union 2613 { 2614 //!< DWORD 3 2615 struct 2616 { 2617 uint32_t Table0XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],4] 2618 uint32_t Table0YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],4] 2619 uint32_t Table0XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],5] 2620 uint32_t Table0YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],5] 2621 }; 2622 uint32_t Value; 2623 } DW3; 2624 union 2625 { 2626 //!< DWORD 4 2627 struct 2628 { 2629 uint32_t Table0XFilterCoefficientN6 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 0X Filter Coefficient[[n],6] 2630 uint32_t Table0YFilterCoefficientN6 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 0Y Filter Coefficient[[n],6] 2631 uint32_t Table0XFilterCoefficientN7 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 0X Filter Coefficient[[n],7] 2632 uint32_t Table0YFilterCoefficientN7 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 0Y Filter Coefficient[[n],7] 2633 }; 2634 uint32_t Value; 2635 } DW4; 2636 2637 uint32_t FilterCoefficients[124]; //!< Filter Coefficients 2638 2639 2640 //! \name Local enumerations 2641 2642 enum SUBOPCODEB 2643 { 2644 SUBOPCODEB_SFCAVSLUMACOEFFTABLE = 5, //!< No additional details 2645 }; 2646 2647 enum SUBOPCODEA 2648 { 2649 SUBOPCODEA_COMMON = 0, //!< No additional details 2650 }; 2651 2652 enum MEDIA_COMMAND_OPCODE 2653 { 2654 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 2655 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 2656 }; 2657 2658 enum PIPELINE 2659 { 2660 PIPELINE_MEDIA = 2, //!< No additional details 2661 }; 2662 2663 enum COMMAND_TYPE 2664 { 2665 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2666 }; 2667 2668 //! \name Initializations 2669 2670 //! \brief Explicit member initialization function 2671 SFC_AVS_LUMA_Coeff_Table_CMD(); 2672 2673 static const size_t dwSize = 129; 2674 static const size_t byteSize = 516; 2675 }; 2676 2677 //! 2678 //! \brief SFC_AVS_CHROMA_Coeff_Table 2679 //! \details 2680 //! This command is sent from VDBOX/VEBOX to SFC pipeline at the start of 2681 //! each frame once the lock request is granted. 2682 //! 2683 struct SFC_AVS_CHROMA_Coeff_Table_CMD 2684 { 2685 union 2686 { 2687 //!< DWORD 0 2688 struct 2689 { 2690 uint32_t DwordLength : __CODEGEN_BITFIELD( 0, 11) ; //!< DWORD_LENGTH 2691 uint32_t Reserved12 : __CODEGEN_BITFIELD(12, 15) ; //!< Reserved 2692 uint32_t Subopcodeb : __CODEGEN_BITFIELD(16, 20) ; //!< SUBOPCODEB 2693 uint32_t Subopcodea : __CODEGEN_BITFIELD(21, 22) ; //!< SUBOPCODEA 2694 uint32_t MediaCommandOpcode : __CODEGEN_BITFIELD(23, 26) ; //!< MEDIA_COMMAND_OPCODE 2695 uint32_t Pipeline : __CODEGEN_BITFIELD(27, 28) ; //!< PIPELINE 2696 uint32_t CommandType : __CODEGEN_BITFIELD(29, 31) ; //!< COMMAND_TYPE 2697 }; 2698 uint32_t Value; 2699 } DW0; 2700 union 2701 { 2702 //!< DWORD 1 2703 struct 2704 { 2705 uint32_t Table1XFilterCoefficientN2 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],2] 2706 uint32_t Table1YFilterCoefficientN2 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],2] 2707 uint32_t Table1XFilterCoefficientN3 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],3] 2708 uint32_t Table1YFilterCoefficientN3 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],3] 2709 }; 2710 uint32_t Value; 2711 } DW1; 2712 union 2713 { 2714 //!< DWORD 2 2715 struct 2716 { 2717 uint32_t Table1XFilterCoefficientN4 : __CODEGEN_BITFIELD( 0, 7) ; //!< Table 1X Filter Coefficient[[n],4] 2718 uint32_t Table1YFilterCoefficientN4 : __CODEGEN_BITFIELD( 8, 15) ; //!< Table 1Y Filter Coefficient[[n],4] 2719 uint32_t Table1XFilterCoefficientN5 : __CODEGEN_BITFIELD(16, 23) ; //!< Table 1X Filter Coefficient[[n],5] 2720 uint32_t Table1YFilterCoefficientN5 : __CODEGEN_BITFIELD(24, 31) ; //!< Table 1Y Filter Coefficient[[n],5] 2721 }; 2722 uint32_t Value; 2723 } DW2; 2724 2725 uint32_t FilterCoefficients[62]; //!< Filter Coefficients 2726 2727 2728 //! \name Local enumerations 2729 2730 enum SUBOPCODEB 2731 { 2732 SUBOPCODEB_SFCAVSCHROMACOEFFTABLE = 6, //!< No additional details 2733 }; 2734 2735 enum SUBOPCODEA 2736 { 2737 SUBOPCODEA_COMMON = 0, //!< No additional details 2738 }; 2739 2740 enum MEDIA_COMMAND_OPCODE 2741 { 2742 MEDIA_COMMAND_OPCODE_MEDIAHEVCSFCMODE = 9, //!< No additional details 2743 MEDIA_COMMAND_OPCODE_MEDIAMFXVEBOXSFCMODE = 10, //!< No additional details 2744 }; 2745 2746 enum PIPELINE 2747 { 2748 PIPELINE_MEDIA = 2, //!< No additional details 2749 }; 2750 2751 enum COMMAND_TYPE 2752 { 2753 COMMAND_TYPE_PARALLELVIDEOPIPE = 3, //!< No additional details 2754 }; 2755 2756 //! \name Initializations 2757 2758 //! \brief Explicit member initialization function 2759 SFC_AVS_CHROMA_Coeff_Table_CMD(); 2760 2761 static const size_t dwSize = 65; 2762 static const size_t byteSize = 260; 2763 }; 2764 2765 }; 2766 2767 #pragma pack() 2768 2769 #endif // __MHW_SFC_HWCMD_G12_X_H__