1 /*
2 * Copyright (c) 2017-2019, Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included
12 * in all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22 //!
23 //! \file     codechal_encode_avc_g9_kbl.cpp
24 //! \brief    AVC dual-pipe encoder for GEN9 KBL.
25 //!
26 #include "codechal_encode_avc_g9_kbl.h"
27 #include "igcodeckrn_g9_kbl.h"
28 #if USE_CODECHAL_DEBUG_TOOL
29 #include "mhw_vdbox_mfx_hwcmd_g9_kbl.h"
30 #endif
31 
32 #define MBENC_NUM_TARGET_USAGES_CM_G9_KBL                       3
33 #define CODECHAL_ENCODE_AVC_BRC_HISTORY_BUFFER_SIZE_G9_KBL      880
34 #define MBENC_BRC_BUFFER_SIZE_G9_KBL                            128
35 #define BRC_CONSTANTSURFACE_LAMBDA_SIZE_G9_KBL                  512
36 #define BRC_CONSTANTSURFACE_FTQ25_SIZE_G9_KBL                   64
37 
38 #define BRC_CONSTANTSURFACE_WIDTH_G9_KBL                        64
39 #define BRC_CONSTANTSURFACE_HEIGHT_G9_KBL                       53
40 
41 #define DEFAULT_TRELLIS_QUANT_INTRA_ROUNDING_G9_KBL             5
42 #define CODECHAL_ENCODE_AVC_BRC_HISTORY_BUFFER_OFFSET_SCENE_CHANGED         0x2FC // (370 + 12)*2 = 764
43 
44 typedef enum _CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_MBENC_G9_KBL
45 {
46     CODECHAL_ENCODE_AVC_MBENC_BRC_CURBE_DATA_G9_KBL = 39,
47     CODECHAL_ENCODE_AVC_MBENC_FORCE_NONSKIP_MB_MAP_G9_KBL = 40,
48     CODECHAL_ENCODE_AVC_MBENC_ADV_WA_G9_KBL = 41,
49     CODECHAL_ENCODE_AVC_MBENC_SFD_COST_TABLE_G9_KBL = 42,
50     CODECHAL_ENCODE_AVC_MBENC_NUM_SURFACES_G9_KBL = 43
51 } CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_MBENC_G9_KBL;
52 
53 typedef enum _CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_MB_BRC_UPDATE_G9_KBL
54 {
55     CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_HISTORY_G9_KBL               = 0,
56     CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_MB_QP_G9_KBL                 = 1,
57     CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_ROI_G9_KBL                   = 2,
58     CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_MB_STAT_G9_KBL               = 3,
59     CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_NUM_SURFACES_G9_KBL          = 4
60 } CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_MB_BRC_UPDATE_G9_KBL;
61 
62 typedef enum _CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_FRAME_BRC_UPDATE_G9_KBL
63 {
64     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_HISTORY_G9_KBL = 0,
65     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_PAK_STATISTICS_OUTPUT_G9_KBL = 1,
66     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_READ_G9_KBL = 2,
67     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_WRITE_G9_KBL = 3,
68     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_WRITE_G9_KBL = 4,
69     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_DISTORTION_G9_KBL = 5,
70     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_CONSTANT_DATA_G9_KBL = 6,
71     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MB_STAT_G9_KBL = 7,
72     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MV_G9_KBL = 8,
73     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_NUM_SURFACES_G9_KBL=9
74 } CODECHAL_ENCODE_AVC_BINDING_TABLE_OFFSET_FRAME_BRC_UPDATE_G9_KBL;
75 
76 static const CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95 g_cInit_CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95 =
77 {
78     // uint32_t 0
79     {
80         {
81             0
82         }
83     },
84 
85     // uint32_t 1
86     {
87         {
88             0
89         }
90     },
91 
92     // uint32_t 2
93     {
94         {
95             0
96         }
97     },
98 
99     // uint32_t 3
100     {
101         {
102             0
103         }
104     },
105 
106     // uint32_t 4
107     {
108         {
109             0
110         }
111     },
112 
113     // uint32_t 5
114     {
115         {
116             0
117         }
118     },
119 
120     // uint32_t 6
121     {
122         {
123             0
124         }
125     },
126 
127     // uint32_t 7
128     {
129         {
130             0
131         }
132     },
133 
134     // uint32_t 8
135     {
136         {
137             0,
138             0
139         }
140     },
141 
142     // uint32_t 9
143     {
144         {
145             0,
146             0
147         }
148     },
149 
150     // uint32_t 10
151     {
152         {
153             0,
154             0
155         }
156     },
157 
158     // uint32_t 11
159     {
160         {
161             0,
162             1
163         }
164     },
165 
166     // uint32_t 12
167     {
168         {
169             51,
170             0
171         }
172     },
173 
174     // uint32_t 13
175     {
176         {
177             40,
178             60,
179             80,
180             120
181         }
182     },
183 
184     // uint32_t 14
185     {
186         {
187             35,
188             60,
189             80,
190             120
191         }
192     },
193 
194     // uint32_t 15
195     {
196         {
197             40,
198             60,
199             90,
200             115
201         }
202     },
203 
204     // uint32_t 16
205     {
206         {
207             0,
208             0,
209             0,
210             0
211         }
212     },
213 
214     // uint32_t 17
215     {
216         {
217             0,
218             0,
219             0,
220             0
221         }
222     },
223 
224     // uint32_t 18
225     {
226         {
227             0,
228             0,
229             0,
230             0
231         }
232     },
233 
234     // uint32_t 19
235     {
236         {
237             0,
238             0,
239             0,
240             0
241         }
242     },
243 
244     // uint32_t 20
245     {
246         {
247             0,
248             0,
249             0,
250             0
251         }
252     },
253 
254     // uint32_t 21
255     {
256         {
257             0,
258             0,
259             0,
260             0
261         }
262     },
263 
264     // uint32_t 22
265     {
266         {
267             0,
268             0,
269             0,
270             0
271         }
272     },
273 
274     // uint32_t 23
275     {
276         {
277             0
278         }
279     },
280 
281     // uint32_t 24
282     {
283         {
284             0,
285             0
286         }
287     },
288 
289     // uint32_t 25
290     {
291         {
292             0
293         }
294     },
295 
296     // uint32_t 26
297     {
298         {
299             0
300         }
301     },
302 
303     // uint32_t 27
304     {
305         {
306             0
307         }
308     },
309 
310     // uint32_t 28
311     {
312         {
313             0
314         }
315     },
316 
317     // uint32_t 29
318     {
319         {
320             0
321         }
322     },
323 
324     // uint32_t 30
325     {
326         {
327             0
328         }
329     },
330 
331     // uint32_t 31
332     {
333         {
334             0
335         }
336     },
337 
338         // uint32_t 32
339     {
340         {
341             0
342         }
343     },
344 
345         // uint32_t 33
346     {
347         {
348             0
349         }
350     },
351 
352 };
353 
354 static const CODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_G95 g_cInit_CODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_G95 =
355 {
356     // uint32_t 0
357     {
358         {
359             0
360         }
361     },
362 
363     // uint32_t 1
364     {
365         {
366             0
367         }
368     },
369 
370     // uint32_t 2
371     {
372         {
373             0
374         }
375     },
376 
377     // uint32_t 3
378     {
379         {
380             10,
381             50
382         }
383     },
384 
385     // uint32_t 4
386     {
387         {
388             100,
389             150
390         }
391     },
392 
393     // uint32_t 5
394     {
395         {
396             0,
397             0,
398             0,
399             0
400         }
401     },
402 
403     // uint32_t 6
404     {
405         {
406             0,
407             0,
408             0,
409             0,
410             0,
411             0,
412             0,
413             0
414         }
415     },
416 
417     // uint32_t 7
418     {
419         {
420             0
421         }
422     },
423 
424     // uint32_t 8
425     {
426         {
427             1,
428             1,
429             3,
430             2
431         }
432     },
433 
434     // uint32_t 9
435     {
436         {
437             1,
438             40,
439             5,
440             5
441         }
442     },
443 
444     // uint32_t 10
445     {
446         {
447             3,
448             1,
449             7,
450             18
451         }
452     },
453 
454     // uint32_t 11
455     {
456         {
457             25,
458             37,
459             40,
460             75
461         }
462     },
463 
464     // uint32_t 12
465     {
466         {
467             97,
468             103,
469             125,
470             160
471         }
472     },
473 
474     // uint32_t 13
475     {
476         {
477             MOS_BITFIELD_VALUE((uint32_t)-3, 8),
478             MOS_BITFIELD_VALUE((uint32_t)-2, 8),
479             MOS_BITFIELD_VALUE((uint32_t)-1, 8),
480             0
481         }
482     },
483 
484     // uint32_t 14
485     {
486         {
487             1,
488             2,
489             3,
490             0xff
491         }
492     },
493 
494     // uint32_t 15
495     {
496         {
497             0,
498             0,
499             0,
500             0
501         }
502     },
503 
504     // uint32_t 16
505     {
506         {
507             0
508         }
509     },
510 
511     // uint32_t 17
512     {
513         {
514             0
515         }
516     },
517 
518     // uint32_t 18
519     {
520         {
521             0
522         }
523     },
524 
525     // uint32_t 19
526     {
527         {
528             0
529         }
530     },
531 
532     // uint32_t 20
533     {
534         {
535             0
536         }
537     },
538 
539     // uint32_t 21
540     {
541         {
542             0
543         }
544     },
545 
546     // uint32_t 22
547     {
548         {
549             0
550         }
551     },
552 
553     // uint32_t 23
554     {
555         {
556             0
557         }
558     },
559 
560         // uint32_t 24
561     {
562         {
563             0
564         }
565     },
566 
567         // uint32_t 25
568     {
569         {
570             0
571         }
572     },
573 
574         // uint32_t 26
575     {
576         {
577             0
578         }
579     },
580 
581         // uint32_t 27
582     {
583         {
584             0
585         }
586     },
587 
588         // uint32_t 28
589     {
590         {
591             0
592         }
593     },
594 
595         // uint32_t 29
596     {
597         {
598             0
599         }
600     },
601 
602         // uint32_t 30
603     {
604         {
605             0
606         }
607     },
608         // uint32_t 31
609     {
610         {
611             0
612         }
613     },
614 
615         // uint32_t 32
616     {
617         {
618             0
619         }
620     },
621 };
622 
623 static const CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_CURBE_G95 g_cInit_CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_CURBE_G95 =
624 {
625     // uint32_t 0
626     {
627         {
628             0,
629             0,
630             0,
631             0
632         }
633     },
634 
635     // uint32_t 1
636     {
637         {
638             0
639         }
640     },
641 
642     // uint32_t 2
643     {
644         {
645             0
646         }
647     },
648 
649     // uint32_t 3
650     {
651         {
652             0
653         }
654     },
655 
656     // uint32_t 4
657     {
658         {
659             0
660         }
661     },
662 
663     // uint32_t 5
664     {
665         {
666             0
667         }
668     },
669 
670     // uint32_t 6
671     {
672         {
673             0
674         }
675     },
676 
677     // uint32_t 7
678     {
679         {
680             0
681         }
682     },
683 
684     // uint32_t 8
685     {
686         {
687             0
688         }
689     },
690 
691     // uint32_t 9
692     {
693         {
694             0
695         }
696     },
697 
698     // uint32_t 10
699     {
700         {
701             0
702         }
703     },
704 
705     // uint32_t 11
706     {
707         {
708             0
709         }
710     },
711 };
712 
713 typedef struct _CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL
714 {
715     // DW0
716     union
717     {
718         struct
719         {
720             uint32_t   SkipModeEn                          : MOS_BITFIELD_BIT(       0);
721             uint32_t   AdaptiveEn                          : MOS_BITFIELD_BIT(       1);
722             uint32_t   BiMixDis                            : MOS_BITFIELD_BIT(       2);
723             uint32_t                                       : MOS_BITFIELD_RANGE( 3,  4);
724             uint32_t   EarlyImeSuccessEn                   : MOS_BITFIELD_BIT(       5);
725             uint32_t                                       : MOS_BITFIELD_BIT(       6);
726             uint32_t   T8x8FlagForInterEn                  : MOS_BITFIELD_BIT(       7);
727             uint32_t                                       : MOS_BITFIELD_RANGE( 8, 23);
728             uint32_t   EarlyImeStop                        : MOS_BITFIELD_RANGE(24, 31);
729         };
730         struct
731         {
732             uint32_t   Value;
733         };
734     } DW0;
735 
736     // DW1
737     union
738     {
739         struct
740         {
741             uint32_t   MaxNumMVs                           : MOS_BITFIELD_RANGE( 0,  5);
742             uint32_t   ExtendedMvCostRange                 : MOS_BITFIELD_BIT(       6);
743             uint32_t                                       : MOS_BITFIELD_RANGE( 7, 15);
744             uint32_t   BiWeight                            : MOS_BITFIELD_RANGE(16, 21);
745             uint32_t                                       : MOS_BITFIELD_RANGE(22, 27);
746             uint32_t   UniMixDisable                       : MOS_BITFIELD_BIT(      28);
747             uint32_t                                       : MOS_BITFIELD_RANGE(29, 31);
748         };
749         struct
750         {
751             uint32_t   Value;
752         };
753     } DW1;
754 
755     // DW2
756     union
757     {
758         struct
759         {
760             uint32_t   LenSP                               : MOS_BITFIELD_RANGE( 0,  7);
761             uint32_t   MaxNumSU                            : MOS_BITFIELD_RANGE( 8, 15);
762             uint32_t   PicWidth                            : MOS_BITFIELD_RANGE(16, 31);
763         };
764         struct
765         {
766             uint32_t   Value;
767         };
768     } DW2;
769 
770     // DW3
771     union
772     {
773         struct
774         {
775             uint32_t   SrcSize                             : MOS_BITFIELD_RANGE( 0,  1);
776             uint32_t                                       : MOS_BITFIELD_RANGE( 2,  3);
777             uint32_t   MbTypeRemap                         : MOS_BITFIELD_RANGE( 4,  5);
778             uint32_t   SrcAccess                           : MOS_BITFIELD_BIT(       6);
779             uint32_t   RefAccess                           : MOS_BITFIELD_BIT(       7);
780             uint32_t   SearchCtrl                          : MOS_BITFIELD_RANGE( 8, 10);
781             uint32_t   DualSearchPathOption                : MOS_BITFIELD_BIT(      11);
782             uint32_t   SubPelMode                          : MOS_BITFIELD_RANGE(12, 13);
783             uint32_t   SkipType                            : MOS_BITFIELD_BIT(      14);
784             uint32_t   DisableFieldCacheAlloc              : MOS_BITFIELD_BIT(      15);
785             uint32_t   InterChromaMode                     : MOS_BITFIELD_BIT(      16);
786             uint32_t   FTEnable                            : MOS_BITFIELD_BIT(      17);
787             uint32_t   BMEDisableFBR                       : MOS_BITFIELD_BIT(      18);
788             uint32_t   BlockBasedSkipEnable                : MOS_BITFIELD_BIT(      19);
789             uint32_t   InterSAD                            : MOS_BITFIELD_RANGE(20, 21);
790             uint32_t   IntraSAD                            : MOS_BITFIELD_RANGE(22, 23);
791             uint32_t   SubMbPartMask                       : MOS_BITFIELD_RANGE(24, 30);
792             uint32_t                                       : MOS_BITFIELD_BIT(      31);
793         };
794         struct
795         {
796             uint32_t   Value;
797         };
798     } DW3;
799 
800     // DW4
801     union
802     {
803         struct
804         {
805             uint32_t   PicHeightMinus1                     : MOS_BITFIELD_RANGE( 0, 15);
806             uint32_t   MvRestrictionInSliceEnable          : MOS_BITFIELD_BIT(      16);
807             uint32_t   DeltaMvEnable                       : MOS_BITFIELD_BIT(      17);
808             uint32_t   TrueDistortionEnable                : MOS_BITFIELD_BIT(      18);
809             uint32_t   EnableWavefrontOptimization         : MOS_BITFIELD_BIT(      19);
810             uint32_t   EnableFBRBypass                     : MOS_BITFIELD_BIT(      20);
811             uint32_t   EnableIntraCostScalingForStaticFrame: MOS_BITFIELD_BIT(      21);
812             uint32_t   EnableIntraRefresh                  : MOS_BITFIELD_BIT(      22);
813             uint32_t   Reserved                            : MOS_BITFIELD_BIT(      23);
814             uint32_t   EnableDirtyRect                     : MOS_BITFIELD_BIT(      24);
815             uint32_t   bCurFldIDR                          : MOS_BITFIELD_BIT(      25);
816             uint32_t   ConstrainedIntraPredFlag            : MOS_BITFIELD_BIT(      26);
817             uint32_t   FieldParityFlag                     : MOS_BITFIELD_BIT(      27);
818             uint32_t   HMEEnable                           : MOS_BITFIELD_BIT(      28);
819             uint32_t   PictureType                         : MOS_BITFIELD_RANGE(29, 30);
820             uint32_t   UseActualRefQPValue                 : MOS_BITFIELD_BIT(      31);
821         };
822         struct
823         {
824             uint32_t   Value;
825         };
826     } DW4;
827 
828     // DW5
829     union
830     {
831         struct
832         {
833             uint32_t   SliceMbHeight                       : MOS_BITFIELD_RANGE( 0, 15);
834             uint32_t   RefWidth                            : MOS_BITFIELD_RANGE(16, 23);
835             uint32_t   RefHeight                           : MOS_BITFIELD_RANGE(24, 31);
836         };
837         struct
838         {
839             uint32_t   Value;
840         };
841     } DW5;
842 
843     // DW6
844     union
845     {
846         struct
847         {
848             uint32_t   BatchBufferEnd                      : MOS_BITFIELD_RANGE( 0, 31);
849         };
850         struct
851         {
852             uint32_t   Value;
853         };
854     } DW6;
855 
856     // DW7
857     union
858     {
859         struct
860         {
861             uint32_t   IntraPartMask                       : MOS_BITFIELD_RANGE( 0,  4);
862             uint32_t   NonSkipZMvAdded                     : MOS_BITFIELD_BIT(       5);
863             uint32_t   NonSkipModeAdded                    : MOS_BITFIELD_BIT(       6);
864             uint32_t   LumaIntraSrcCornerSwap              : MOS_BITFIELD_BIT(       7);
865             uint32_t                                       : MOS_BITFIELD_RANGE( 8, 15);
866             uint32_t   MVCostScaleFactor                   : MOS_BITFIELD_RANGE(16, 17);
867             uint32_t   BilinearEnable                      : MOS_BITFIELD_BIT(      18);
868             uint32_t   SrcFieldPolarity                    : MOS_BITFIELD_BIT(      19);
869             uint32_t   WeightedSADHAAR                     : MOS_BITFIELD_BIT(      20);
870             uint32_t   AConlyHAAR                          : MOS_BITFIELD_BIT(      21);
871             uint32_t   RefIDCostMode                       : MOS_BITFIELD_BIT(      22);
872             uint32_t                                       : MOS_BITFIELD_BIT(      23);
873             uint32_t   SkipCenterMask                      : MOS_BITFIELD_RANGE(24, 31);
874         };
875         struct
876         {
877             uint32_t   Value;
878         };
879     } DW7;
880 
881     struct
882     {
883         // DW8
884         union
885         {
886             struct
887             {
888                 uint32_t   Mode0Cost : MOS_BITFIELD_RANGE(0, 7);
889                 uint32_t   Mode1Cost : MOS_BITFIELD_RANGE(8, 15);
890                 uint32_t   Mode2Cost : MOS_BITFIELD_RANGE(16, 23);
891                 uint32_t   Mode3Cost : MOS_BITFIELD_RANGE(24, 31);
892             };
893             struct
894             {
895                 uint32_t   Value;
896             };
897         } DW8;
898 
899         // DW9
900         union
901         {
902             struct
903             {
904                 uint32_t   Mode4Cost : MOS_BITFIELD_RANGE(0, 7);
905                 uint32_t   Mode5Cost : MOS_BITFIELD_RANGE(8, 15);
906                 uint32_t   Mode6Cost : MOS_BITFIELD_RANGE(16, 23);
907                 uint32_t   Mode7Cost : MOS_BITFIELD_RANGE(24, 31);
908             };
909             struct
910             {
911                 uint32_t   Value;
912             };
913         } DW9;
914 
915         // DW10
916         union
917         {
918             struct
919             {
920                 uint32_t   Mode8Cost : MOS_BITFIELD_RANGE(0, 7);
921                 uint32_t   Mode9Cost : MOS_BITFIELD_RANGE(8, 15);
922                 uint32_t   RefIDCost : MOS_BITFIELD_RANGE(16, 23);
923                 uint32_t   ChromaIntraModeCost : MOS_BITFIELD_RANGE(24, 31);
924             };
925             struct
926             {
927                 uint32_t   Value;
928             };
929         } DW10;
930 
931         // DW11
932         union
933         {
934             struct
935             {
936                 uint32_t   MV0Cost : MOS_BITFIELD_RANGE(0, 7);
937                 uint32_t   MV1Cost : MOS_BITFIELD_RANGE(8, 15);
938                 uint32_t   MV2Cost : MOS_BITFIELD_RANGE(16, 23);
939                 uint32_t   MV3Cost : MOS_BITFIELD_RANGE(24, 31);
940             };
941             struct
942             {
943                 uint32_t   Value;
944             };
945         } DW11;
946 
947         // DW12
948         union
949         {
950             struct
951             {
952                 uint32_t   MV4Cost : MOS_BITFIELD_RANGE(0, 7);
953                 uint32_t   MV5Cost : MOS_BITFIELD_RANGE(8, 15);
954                 uint32_t   MV6Cost : MOS_BITFIELD_RANGE(16, 23);
955                 uint32_t   MV7Cost : MOS_BITFIELD_RANGE(24, 31);
956             };
957             struct
958             {
959                 uint32_t   Value;
960             };
961         } DW12;
962 
963         // DW13
964         union
965         {
966             struct
967             {
968                 uint32_t   QpPrimeY : MOS_BITFIELD_RANGE(0, 7);
969                 uint32_t   QpPrimeCb : MOS_BITFIELD_RANGE(8, 15);
970                 uint32_t   QpPrimeCr : MOS_BITFIELD_RANGE(16, 23);
971                 uint32_t   TargetSizeInWord : MOS_BITFIELD_RANGE(24, 31);
972             };
973             struct
974             {
975                 uint32_t   Value;
976             };
977         } DW13;
978 
979         // DW14
980         union
981         {
982             struct
983             {
984                 uint32_t   SICFwdTransCoeffThreshold_0 : MOS_BITFIELD_RANGE(0, 15);
985                 uint32_t   SICFwdTransCoeffThreshold_1 : MOS_BITFIELD_RANGE(16, 23);
986                 uint32_t   SICFwdTransCoeffThreshold_2 : MOS_BITFIELD_RANGE(24, 31);
987             };
988             struct
989             {
990                 uint32_t   Value;
991             };
992         } DW14;
993 
994         // DW15
995         union
996         {
997             struct
998             {
999                 uint32_t   SICFwdTransCoeffThreshold_3 : MOS_BITFIELD_RANGE(0, 7);
1000                 uint32_t   SICFwdTransCoeffThreshold_4 : MOS_BITFIELD_RANGE(8, 15);
1001                 uint32_t   SICFwdTransCoeffThreshold_5 : MOS_BITFIELD_RANGE(16, 23);
1002                 uint32_t   SICFwdTransCoeffThreshold_6 : MOS_BITFIELD_RANGE(24, 31);    // Highest Freq
1003             };
1004             struct
1005             {
1006                 uint32_t   Value;
1007             };
1008         } DW15;
1009     } ModeMvCost;
1010 
1011     struct
1012     {
1013         // DW16
1014         union
1015         {
1016             struct
1017             {
1018                 SearchPathDelta   SPDelta_0;
1019                 SearchPathDelta   SPDelta_1;
1020                 SearchPathDelta   SPDelta_2;
1021                 SearchPathDelta   SPDelta_3;
1022             };
1023             struct
1024             {
1025                 uint32_t   Value;
1026             };
1027         } DW16;
1028 
1029         // DW17
1030         union
1031         {
1032             struct
1033             {
1034                 SearchPathDelta   SPDelta_4;
1035                 SearchPathDelta   SPDelta_5;
1036                 SearchPathDelta   SPDelta_6;
1037                 SearchPathDelta   SPDelta_7;
1038             };
1039             struct
1040             {
1041                 uint32_t   Value;
1042             };
1043         } DW17;
1044 
1045         // DW18
1046         union
1047         {
1048             struct
1049             {
1050                 SearchPathDelta   SPDelta_8;
1051                 SearchPathDelta   SPDelta_9;
1052                 SearchPathDelta   SPDelta_10;
1053                 SearchPathDelta   SPDelta_11;
1054             };
1055             struct
1056             {
1057                 uint32_t   Value;
1058             };
1059         } DW18;
1060 
1061         // DW19
1062         union
1063         {
1064             struct
1065             {
1066                 SearchPathDelta   SPDelta_12;
1067                 SearchPathDelta   SPDelta_13;
1068                 SearchPathDelta   SPDelta_14;
1069                 SearchPathDelta   SPDelta_15;
1070             };
1071             struct
1072             {
1073                 uint32_t   Value;
1074             };
1075         } DW19;
1076 
1077         // DW20
1078         union
1079         {
1080             struct
1081             {
1082                 SearchPathDelta   SPDelta_16;
1083                 SearchPathDelta   SPDelta_17;
1084                 SearchPathDelta   SPDelta_18;
1085                 SearchPathDelta   SPDelta_19;
1086             };
1087             struct
1088             {
1089                 uint32_t   Value;
1090             };
1091         } DW20;
1092 
1093         // DW21
1094         union
1095         {
1096             struct
1097             {
1098                 SearchPathDelta   SPDelta_20;
1099                 SearchPathDelta   SPDelta_21;
1100                 SearchPathDelta   SPDelta_22;
1101                 SearchPathDelta   SPDelta_23;
1102             };
1103             struct
1104             {
1105                 uint32_t   Value;
1106             };
1107         } DW21;
1108 
1109         // DW22
1110         union
1111         {
1112             struct
1113             {
1114                 SearchPathDelta   SPDelta_24;
1115                 SearchPathDelta   SPDelta_25;
1116                 SearchPathDelta   SPDelta_26;
1117                 SearchPathDelta   SPDelta_27;
1118             };
1119             struct
1120             {
1121                 uint32_t   Value;
1122             };
1123         } DW22;
1124 
1125         // DW23
1126         union
1127         {
1128             struct
1129             {
1130                 SearchPathDelta   SPDelta_28;
1131                 SearchPathDelta   SPDelta_29;
1132                 SearchPathDelta   SPDelta_30;
1133                 SearchPathDelta   SPDelta_31;
1134             };
1135             struct
1136             {
1137                 uint32_t   Value;
1138             };
1139         } DW23;
1140 
1141         // DW24
1142         union
1143         {
1144             struct
1145             {
1146                 SearchPathDelta   SPDelta_32;
1147                 SearchPathDelta   SPDelta_33;
1148                 SearchPathDelta   SPDelta_34;
1149                 SearchPathDelta   SPDelta_35;
1150             };
1151             struct
1152             {
1153                 uint32_t   Value;
1154             };
1155         } DW24;
1156 
1157         // DW25
1158         union
1159         {
1160             struct
1161             {
1162                 SearchPathDelta   SPDelta_36;
1163                 SearchPathDelta   SPDelta_37;
1164                 SearchPathDelta   SPDelta_38;
1165                 SearchPathDelta   SPDelta_39;
1166             };
1167             struct
1168             {
1169                 uint32_t   Value;
1170             };
1171         } DW25;
1172 
1173         // DW26
1174         union
1175         {
1176             struct
1177             {
1178                 SearchPathDelta   SPDelta_40;
1179                 SearchPathDelta   SPDelta_41;
1180                 SearchPathDelta   SPDelta_42;
1181                 SearchPathDelta   SPDelta_43;
1182             };
1183             struct
1184             {
1185                 uint32_t   Value;
1186             };
1187         } DW26;
1188 
1189         // DW27
1190         union
1191         {
1192             struct
1193             {
1194                 SearchPathDelta   SPDelta_44;
1195                 SearchPathDelta   SPDelta_45;
1196                 SearchPathDelta   SPDelta_46;
1197                 SearchPathDelta   SPDelta_47;
1198             };
1199             struct
1200             {
1201                 uint32_t   Value;
1202             };
1203         } DW27;
1204 
1205         // DW28
1206         union
1207         {
1208             struct
1209             {
1210                 SearchPathDelta   SPDelta_48;
1211                 SearchPathDelta   SPDelta_49;
1212                 SearchPathDelta   SPDelta_50;
1213                 SearchPathDelta   SPDelta_51;
1214             };
1215             struct
1216             {
1217                 uint32_t   Value;
1218             };
1219         } DW28;
1220 
1221         // DW29
1222         union
1223         {
1224             struct
1225             {
1226                 SearchPathDelta   SPDelta_52;
1227                 SearchPathDelta   SPDelta_53;
1228                 SearchPathDelta   SPDelta_54;
1229                 SearchPathDelta   SPDelta_55;
1230             };
1231             struct
1232             {
1233                 uint32_t   Value;
1234             };
1235         } DW29;
1236 
1237         // DW30
1238         union
1239         {
1240             struct
1241             {
1242                 uint32_t   Intra4x4ModeMask : MOS_BITFIELD_RANGE(0, 8);
1243             uint32_t: MOS_BITFIELD_RANGE(9, 15);
1244                 uint32_t   Intra8x8ModeMask : MOS_BITFIELD_RANGE(16, 24);
1245             uint32_t: MOS_BITFIELD_RANGE(25, 31);
1246             };
1247             struct
1248             {
1249                 uint32_t   Value;
1250             };
1251         } DW30;
1252 
1253         // DW31
1254         union
1255         {
1256             struct
1257             {
1258                 uint32_t   Intra16x16ModeMask : MOS_BITFIELD_RANGE(0, 3);
1259                 uint32_t   IntraChromaModeMask : MOS_BITFIELD_RANGE(4, 7);
1260                 uint32_t   IntraComputeType : MOS_BITFIELD_RANGE(8, 9);
1261             uint32_t: MOS_BITFIELD_RANGE(10, 31);
1262             };
1263             struct
1264             {
1265                 uint32_t   Value;
1266             };
1267         } DW31;
1268     } SPDelta;
1269 
1270     // DW32
1271     union
1272     {
1273         struct
1274         {
1275             uint32_t   SkipVal                             : MOS_BITFIELD_RANGE( 0, 15);
1276             uint32_t   MultiPredL0Disable                  : MOS_BITFIELD_RANGE(16, 23);
1277             uint32_t   MultiPredL1Disable                  : MOS_BITFIELD_RANGE(24, 31);
1278         };
1279         struct
1280         {
1281             uint32_t   Value;
1282         };
1283     } DW32;
1284 
1285     // DW33
1286     union
1287     {
1288         struct
1289         {
1290             uint32_t   Intra16x16NonDCPredPenalty          : MOS_BITFIELD_RANGE( 0,  7);
1291             uint32_t   Intra8x8NonDCPredPenalty            : MOS_BITFIELD_RANGE( 8, 15);
1292             uint32_t   Intra4x4NonDCPredPenalty            : MOS_BITFIELD_RANGE(16, 23);
1293             uint32_t                                       : MOS_BITFIELD_RANGE(24, 31);
1294         };
1295         struct
1296         {
1297             uint32_t   Value;
1298         };
1299     } DW33;
1300 
1301     // DW34
1302     union
1303     {
1304         struct
1305         {
1306             uint32_t   List0RefID0FieldParity              : MOS_BITFIELD_BIT(       0);
1307             uint32_t   List0RefID1FieldParity              : MOS_BITFIELD_BIT(       1);
1308             uint32_t   List0RefID2FieldParity              : MOS_BITFIELD_BIT(       2);
1309             uint32_t   List0RefID3FieldParity              : MOS_BITFIELD_BIT(       3);
1310             uint32_t   List0RefID4FieldParity              : MOS_BITFIELD_BIT(       4);
1311             uint32_t   List0RefID5FieldParity              : MOS_BITFIELD_BIT(       5);
1312             uint32_t   List0RefID6FieldParity              : MOS_BITFIELD_BIT(       6);
1313             uint32_t   List0RefID7FieldParity              : MOS_BITFIELD_BIT(       7);
1314             uint32_t   List1RefID0FrameFieldFlag           : MOS_BITFIELD_BIT(       8);
1315             uint32_t   List1RefID1FrameFieldFlag           : MOS_BITFIELD_BIT(       9);
1316             uint32_t   IntraRefreshEn                      : MOS_BITFIELD_RANGE(10, 11);
1317             uint32_t   ArbitraryNumMbsPerSlice             : MOS_BITFIELD_BIT(      12);
1318             uint32_t   TQEnable                            : MOS_BITFIELD_BIT(      13);
1319             uint32_t   ForceNonSkipMbEnable                : MOS_BITFIELD_BIT(      14);
1320             uint32_t   DisableEncSkipCheck                 : MOS_BITFIELD_BIT(      15);
1321             uint32_t   EnableDirectBiasAdjustment          : MOS_BITFIELD_BIT(      16);
1322             uint32_t   bForceToSkip                        : MOS_BITFIELD_BIT(      17);
1323             uint32_t   EnableGlobalMotionBiasAdjustment    : MOS_BITFIELD_BIT(      18);
1324             uint32_t   EnableAdaptiveTxDecision            : MOS_BITFIELD_BIT(      19);
1325             uint32_t   EnablePerMBStaticCheck              : MOS_BITFIELD_BIT(      20);
1326             uint32_t   EnableAdaptiveSearchWindowSize      : MOS_BITFIELD_BIT(      21);
1327             uint32_t   RemoveIntraRefreshOverlap           : MOS_BITFIELD_BIT(      22);
1328             uint32_t   CQPFlag                             : MOS_BITFIELD_BIT(      23);
1329             uint32_t   List1RefID0FieldParity              : MOS_BITFIELD_BIT(      24);
1330             uint32_t   List1RefID1FieldParity              : MOS_BITFIELD_BIT(      25);
1331             uint32_t   MADEnableFlag                       : MOS_BITFIELD_BIT(      26);
1332             uint32_t   ROIEnableFlag                       : MOS_BITFIELD_BIT(      27);
1333             uint32_t   EnableMBFlatnessChkOptimization     : MOS_BITFIELD_BIT(      28);
1334             uint32_t   bDirectMode                         : MOS_BITFIELD_BIT(      29);
1335             uint32_t   MBBrcEnable                         : MOS_BITFIELD_BIT(      30);
1336             uint32_t   bOriginalBff                        : MOS_BITFIELD_BIT(      31);
1337         };
1338         struct
1339         {
1340             uint32_t   Value;
1341         };
1342     } DW34;
1343 
1344     // DW35
1345     union
1346     {
1347         struct
1348         {
1349             uint32_t   PanicModeMBThreshold                : MOS_BITFIELD_RANGE( 0, 15);
1350             uint32_t   SmallMbSizeInWord                   : MOS_BITFIELD_RANGE(16, 23);
1351             uint32_t   LargeMbSizeInWord                   : MOS_BITFIELD_RANGE(24, 31);
1352         };
1353         struct
1354         {
1355             uint32_t   Value;
1356         };
1357     } DW35;
1358 
1359     // DW36
1360     union
1361     {
1362         struct
1363         {
1364             uint32_t   NumRefIdxL0MinusOne                 : MOS_BITFIELD_RANGE( 0,  7);
1365             uint32_t   HMECombinedExtraSUs                 : MOS_BITFIELD_RANGE( 8, 15);
1366             uint32_t   NumRefIdxL1MinusOne                 : MOS_BITFIELD_RANGE(16, 23);
1367             uint32_t                                       : MOS_BITFIELD_RANGE(24, 26);
1368             uint32_t   MBInputEnable                       : MOS_BITFIELD_BIT(      27);
1369             uint32_t   IsFwdFrameShortTermRef              : MOS_BITFIELD_BIT(      28);
1370             uint32_t   CheckAllFractionalEnable            : MOS_BITFIELD_BIT(      29);
1371             uint32_t   HMECombineOverlap                   : MOS_BITFIELD_RANGE(30, 31);
1372         };
1373         struct
1374         {
1375             uint32_t   Value;
1376         };
1377     } DW36;
1378 
1379     // DW37
1380     union
1381     {
1382         struct
1383         {
1384             uint32_t   SkipModeEn                          : MOS_BITFIELD_BIT(       0);
1385             uint32_t   AdaptiveEn                          : MOS_BITFIELD_BIT(       1);
1386             uint32_t   BiMixDis                            : MOS_BITFIELD_BIT(       2);
1387             uint32_t                                       : MOS_BITFIELD_RANGE( 3,  4);
1388             uint32_t   EarlyImeSuccessEn                   : MOS_BITFIELD_BIT(       5);
1389             uint32_t                                       : MOS_BITFIELD_BIT(       6);
1390             uint32_t   T8x8FlagForInterEn                  : MOS_BITFIELD_BIT(       7);
1391             uint32_t                                       : MOS_BITFIELD_RANGE( 8, 23);
1392             uint32_t   EarlyImeStop                        : MOS_BITFIELD_RANGE(24, 31);
1393         };
1394         struct
1395         {
1396             uint32_t   Value;
1397         };
1398     } DW37;
1399 
1400     // DW38
1401     union
1402     {
1403         struct
1404         {
1405             uint32_t   LenSP                               : MOS_BITFIELD_RANGE( 0,  7);
1406             uint32_t   MaxNumSU                            : MOS_BITFIELD_RANGE( 8, 15);
1407             uint32_t   RefThreshold                        : MOS_BITFIELD_RANGE(16, 31);
1408         };
1409         struct
1410         {
1411             uint32_t   Value;
1412         };
1413     } DW38;
1414 
1415     // DW39
1416     union
1417     {
1418         struct
1419         {
1420             uint32_t                                       : MOS_BITFIELD_RANGE( 0,  7);
1421             uint32_t   HMERefWindowsCombThreshold          : MOS_BITFIELD_RANGE( 8, 15);
1422             uint32_t   RefWidth                            : MOS_BITFIELD_RANGE(16, 23);
1423             uint32_t   RefHeight                           : MOS_BITFIELD_RANGE(24, 31);
1424         };
1425         struct
1426         {
1427             uint32_t   Value;
1428         };
1429     } DW39;
1430 
1431     // DW40
1432     union
1433     {
1434         struct
1435         {
1436             uint32_t   DistScaleFactorRefID0List0          : MOS_BITFIELD_RANGE( 0, 15);
1437             uint32_t   DistScaleFactorRefID1List0          : MOS_BITFIELD_RANGE(16, 31);
1438         };
1439         struct
1440         {
1441             uint32_t   Value;
1442         };
1443     } DW40;
1444 
1445     // DW41
1446     union
1447     {
1448         struct
1449         {
1450             uint32_t   DistScaleFactorRefID2List0          : MOS_BITFIELD_RANGE( 0, 15);
1451             uint32_t   DistScaleFactorRefID3List0          : MOS_BITFIELD_RANGE(16, 31);
1452         };
1453         struct
1454         {
1455             uint32_t   Value;
1456         };
1457     } DW41;
1458 
1459     // DW42
1460     union
1461     {
1462         struct
1463         {
1464             uint32_t   DistScaleFactorRefID4List0          : MOS_BITFIELD_RANGE( 0, 15);
1465             uint32_t   DistScaleFactorRefID5List0          : MOS_BITFIELD_RANGE(16, 31);
1466         };
1467         struct
1468         {
1469             uint32_t   Value;
1470         };
1471     } DW42;
1472 
1473     // DW43
1474     union
1475     {
1476         struct
1477         {
1478             uint32_t   DistScaleFactorRefID6List0          : MOS_BITFIELD_RANGE( 0, 15);
1479             uint32_t   DistScaleFactorRefID7List0          : MOS_BITFIELD_RANGE(16, 31);
1480         };
1481         struct
1482         {
1483             uint32_t   Value;
1484         };
1485     } DW43;
1486 
1487     // DW44
1488     union
1489     {
1490         struct
1491         {
1492             uint32_t   ActualQPValueForRefID0List0         : MOS_BITFIELD_RANGE( 0,  7);
1493             uint32_t   ActualQPValueForRefID1List0         : MOS_BITFIELD_RANGE( 8, 15);
1494             uint32_t   ActualQPValueForRefID2List0         : MOS_BITFIELD_RANGE(16, 23);
1495             uint32_t   ActualQPValueForRefID3List0         : MOS_BITFIELD_RANGE(24, 31);
1496         };
1497         struct
1498         {
1499             uint32_t   Value;
1500         };
1501     } DW44;
1502 
1503     // DW45
1504     union
1505     {
1506         struct
1507         {
1508             uint32_t   ActualQPValueForRefID4List0         : MOS_BITFIELD_RANGE( 0,  7);
1509             uint32_t   ActualQPValueForRefID5List0         : MOS_BITFIELD_RANGE( 8, 15);
1510             uint32_t   ActualQPValueForRefID6List0         : MOS_BITFIELD_RANGE(16, 23);
1511             uint32_t   ActualQPValueForRefID7List0         : MOS_BITFIELD_RANGE(24, 31);
1512         };
1513         struct
1514         {
1515             uint32_t   Value;
1516         };
1517     } DW45;
1518 
1519     // DW46
1520     union
1521     {
1522         struct
1523         {
1524             uint32_t   ActualQPValueForRefID0List1         : MOS_BITFIELD_RANGE( 0,  7);
1525             uint32_t   ActualQPValueForRefID1List1         : MOS_BITFIELD_RANGE( 8, 15);
1526             uint32_t   RefCost                             : MOS_BITFIELD_RANGE(16, 31);
1527         };
1528         struct
1529         {
1530             uint32_t   Value;
1531         };
1532     } DW46;
1533 
1534     // DW47
1535     union
1536     {
1537         struct
1538         {
1539             uint32_t   MbQpReadFactor                      : MOS_BITFIELD_RANGE( 0,  7);
1540             uint32_t   IntraCostSF                         : MOS_BITFIELD_RANGE( 8, 15);
1541             uint32_t   MaxVmvR                             : MOS_BITFIELD_RANGE(16, 31);
1542         };
1543         struct
1544         {
1545             uint32_t   Value;
1546         };
1547     } DW47;
1548 
1549     //DW48
1550     union
1551     {
1552         struct
1553         {
1554             uint32_t   IntraRefreshMBx                     : MOS_BITFIELD_RANGE( 0, 15);
1555             uint32_t   IntraRefreshUnitInMBMinus1          : MOS_BITFIELD_RANGE(16, 23);
1556             uint32_t   IntraRefreshQPDelta                 : MOS_BITFIELD_RANGE(24, 31);
1557         };
1558         struct
1559         {
1560             uint32_t   Value;
1561         };
1562     } DW48;
1563 
1564     // DW49
1565     union
1566     {
1567         struct
1568         {
1569             uint32_t   ROI1_X_left                         : MOS_BITFIELD_RANGE( 0, 15);
1570             uint32_t   ROI1_Y_top                          : MOS_BITFIELD_RANGE(16, 31);
1571         };
1572         struct
1573         {
1574             uint32_t   Value;
1575         };
1576     } DW49;
1577 
1578     // DW50
1579     union
1580     {
1581         struct
1582         {
1583             uint32_t   ROI1_X_right                        : MOS_BITFIELD_RANGE( 0, 15);
1584             uint32_t   ROI1_Y_bottom                       : MOS_BITFIELD_RANGE(16, 31);
1585         };
1586         struct
1587         {
1588             uint32_t   Value;
1589         };
1590     } DW50;
1591 
1592     // DW51
1593     union
1594     {
1595         struct
1596         {
1597             uint32_t   ROI2_X_left                         : MOS_BITFIELD_RANGE( 0, 15);
1598             uint32_t   ROI2_Y_top                          : MOS_BITFIELD_RANGE(16, 31);
1599         };
1600         struct
1601         {
1602             uint32_t   Value;
1603         };
1604     } DW51;
1605 
1606     // DW52
1607     union
1608     {
1609         struct
1610         {
1611             uint32_t   ROI2_X_right                        : MOS_BITFIELD_RANGE( 0, 15);
1612             uint32_t   ROI2_Y_bottom                       : MOS_BITFIELD_RANGE(16, 31);
1613         };
1614         struct
1615         {
1616             uint32_t   Value;
1617         };
1618     } DW52;
1619 
1620     // DW53
1621     union
1622     {
1623         struct
1624         {
1625             uint32_t   ROI3_X_left                         : MOS_BITFIELD_RANGE( 0, 15);
1626             uint32_t   ROI3_Y_top                          : MOS_BITFIELD_RANGE(16, 31);
1627         };
1628         struct
1629         {
1630             uint32_t   Value;
1631         };
1632     } DW53;
1633 
1634     // DW54
1635     union
1636     {
1637         struct
1638         {
1639             uint32_t   ROI3_X_right                        : MOS_BITFIELD_RANGE( 0, 15);
1640             uint32_t   ROI3_Y_bottom                       : MOS_BITFIELD_RANGE(16, 31);
1641         };
1642         struct
1643         {
1644             uint32_t   Value;
1645         };
1646     } DW54;
1647 
1648     // DW55
1649     union
1650     {
1651         struct
1652         {
1653             uint32_t   ROI4_X_left                         : MOS_BITFIELD_RANGE( 0, 15);
1654             uint32_t   ROI4_Y_top                          : MOS_BITFIELD_RANGE(16, 31);
1655         };
1656         struct
1657         {
1658             uint32_t   Value;
1659         };
1660     } DW55;
1661 
1662     // DW56
1663     union
1664     {
1665         struct
1666         {
1667             uint32_t   ROI4_X_right                        : MOS_BITFIELD_RANGE( 0, 15);
1668             uint32_t   ROI4_Y_bottom                       : MOS_BITFIELD_RANGE(16, 31);
1669         };
1670         struct
1671         {
1672             uint32_t   Value;
1673         };
1674     } DW56;
1675 
1676     // DW57
1677     union
1678     {
1679         struct
1680         {
1681             uint32_t   ROI1_dQpPrimeY                      : MOS_BITFIELD_RANGE( 0,  7);
1682             uint32_t   ROI2_dQpPrimeY                      : MOS_BITFIELD_RANGE( 8, 15);
1683             uint32_t   ROI3_dQpPrimeY                      : MOS_BITFIELD_RANGE(16, 23);
1684             uint32_t   ROI4_dQpPrimeY                      : MOS_BITFIELD_RANGE(24, 31);
1685         };
1686         struct
1687         {
1688             uint32_t   Value;
1689         };
1690     } DW57;
1691 
1692     // DW58
1693     union
1694     {
1695         struct
1696         {
1697             uint32_t   Lambda_8x8Inter                     : MOS_BITFIELD_RANGE( 0, 15);
1698             uint32_t   Lambda_8x8Intra                     : MOS_BITFIELD_RANGE(16, 31);
1699         };
1700         struct
1701         {
1702             uint32_t   Value;
1703         };
1704     } DW58;
1705 
1706     // DW59
1707     union
1708     {
1709         struct
1710         {
1711             uint32_t   Lambda_Inter                        : MOS_BITFIELD_RANGE( 0, 15);
1712             uint32_t   Lambda_Intra                        : MOS_BITFIELD_RANGE(16, 31);
1713         };
1714         struct
1715         {
1716             uint32_t   Value;
1717         };
1718     } DW59;
1719 
1720     // DW60
1721     union
1722     {
1723         struct
1724         {
1725             uint32_t   MBTextureThreshold                  : MOS_BITFIELD_RANGE(0, 15);
1726             uint32_t   TxDecisonThreshold                  : MOS_BITFIELD_RANGE(16, 31);
1727         };
1728         struct
1729         {
1730             uint32_t   Value;
1731         };
1732     } DW60;
1733 
1734     // DW61
1735     union
1736     {
1737         struct
1738         {
1739             uint32_t   HMEMVCostScalingFactor              : MOS_BITFIELD_RANGE(0, 7);
1740             uint32_t   Reserved                            : MOS_BITFIELD_RANGE(8, 15);
1741             uint32_t   IntraRefreshMBy                     : MOS_BITFIELD_RANGE(16, 31);
1742         };
1743         struct
1744         {
1745             uint32_t   Value;
1746         };
1747     } DW61;
1748 
1749     // DW62
1750     union
1751     {
1752         struct
1753         {
1754             uint32_t   IPCM_QP0                            : MOS_BITFIELD_RANGE(  0, 7 );
1755             uint32_t   IPCM_QP1                            : MOS_BITFIELD_RANGE(  8,15 );
1756             uint32_t   IPCM_QP2                            : MOS_BITFIELD_RANGE( 16,23 );
1757             uint32_t   IPCM_QP3                            : MOS_BITFIELD_RANGE( 24,31 );
1758         };
1759         struct
1760         {
1761             uint32_t   Value;
1762         };
1763     } DW62;
1764 
1765     // DW63
1766     union
1767     {
1768         struct
1769         {
1770             uint32_t   IPCM_QP4                            : MOS_BITFIELD_RANGE(  0, 7 );
1771             uint32_t   Reserved                            : MOS_BITFIELD_RANGE(  8,15 );
1772             uint32_t   IPCM_Thresh0                        : MOS_BITFIELD_RANGE( 16,31 );
1773         };
1774         struct
1775         {
1776             uint32_t   Value;
1777         };
1778     } DW63;
1779 
1780     // DW64
1781     union
1782     {
1783         struct
1784         {
1785             uint32_t   IPCM_Thresh1                        : MOS_BITFIELD_RANGE(  0,15 );
1786             uint32_t   IPCM_Thresh2                        : MOS_BITFIELD_RANGE( 16,31 );
1787         };
1788         struct
1789         {
1790             uint32_t   Value;
1791         };
1792     } DW64;
1793 
1794     // DW65
1795     union
1796     {
1797         struct
1798         {
1799             uint32_t   IPCM_Thresh3                        : MOS_BITFIELD_RANGE(  0,15 );
1800             uint32_t   IPCM_Thresh4                        : MOS_BITFIELD_RANGE( 16,31 );
1801         };
1802         struct
1803         {
1804             uint32_t   Value;
1805         };
1806     } DW65;
1807 
1808     // DW66
1809     union
1810     {
1811         struct
1812         {
1813             uint32_t   MBDataSurfIndex                     : MOS_BITFIELD_RANGE( 0, 31);
1814         };
1815         struct
1816         {
1817             uint32_t   Value;
1818         };
1819     } DW66;
1820 
1821     // DW67
1822     union
1823     {
1824         struct
1825         {
1826             uint32_t   MVDataSurfIndex                     : MOS_BITFIELD_RANGE( 0, 31);
1827         };
1828         struct
1829         {
1830             uint32_t   Value;
1831         };
1832     } DW67;
1833 
1834     // DW68
1835     union
1836     {
1837         struct
1838         {
1839             uint32_t   IDistSurfIndex                      : MOS_BITFIELD_RANGE( 0, 31);
1840         };
1841         struct
1842         {
1843             uint32_t   Value;
1844         };
1845     } DW68;
1846 
1847     // DW69
1848     union
1849     {
1850         struct
1851         {
1852             uint32_t   SrcYSurfIndex                       : MOS_BITFIELD_RANGE( 0, 31);
1853         };
1854         struct
1855         {
1856             uint32_t   Value;
1857         };
1858     } DW69;
1859 
1860     // DW70
1861     union
1862     {
1863         struct
1864         {
1865             uint32_t   MBSpecificDataSurfIndex             : MOS_BITFIELD_RANGE( 0, 31);
1866         };
1867         struct
1868         {
1869             uint32_t   Value;
1870         };
1871     } DW70;
1872 
1873     // DW71
1874     union
1875     {
1876         struct
1877         {
1878             uint32_t   AuxVmeOutSurfIndex                  : MOS_BITFIELD_RANGE( 0, 31);
1879         };
1880         struct
1881         {
1882             uint32_t   Value;
1883         };
1884     } DW71;
1885 
1886     // DW72
1887     union
1888     {
1889         struct
1890         {
1891             uint32_t   CurrRefPicSelSurfIndex              : MOS_BITFIELD_RANGE( 0, 31);
1892         };
1893         struct
1894         {
1895             uint32_t   Value;
1896         };
1897     } DW72;
1898 
1899     // DW73
1900     union
1901     {
1902         struct
1903         {
1904             uint32_t   HMEMVPredFwdBwdSurfIndex            : MOS_BITFIELD_RANGE( 0, 31);
1905         };
1906         struct
1907         {
1908             uint32_t   Value;
1909         };
1910     } DW73;
1911 
1912     // DW74
1913     union
1914     {
1915         struct
1916         {
1917             uint32_t   HMEDistSurfIndex                    : MOS_BITFIELD_RANGE( 0, 31);
1918         };
1919         struct
1920         {
1921             uint32_t   Value;
1922         };
1923     } DW74;
1924 
1925     // DW75
1926     union
1927     {
1928         struct
1929         {
1930             uint32_t   SliceMapSurfIndex                   : MOS_BITFIELD_RANGE( 0, 31);
1931         };
1932         struct
1933         {
1934             uint32_t   Value;
1935         };
1936     } DW75;
1937 
1938     // DW76
1939     union
1940     {
1941         struct
1942         {
1943             uint32_t   FwdFrmMBDataSurfIndex               : MOS_BITFIELD_RANGE( 0, 31);
1944         };
1945         struct
1946         {
1947             uint32_t   Value;
1948         };
1949     } DW76;
1950 
1951     // DW77
1952     union
1953     {
1954         struct
1955         {
1956             uint32_t   FwdFrmMVSurfIndex                   : MOS_BITFIELD_RANGE( 0, 31);
1957         };
1958         struct
1959         {
1960             uint32_t   Value;
1961         };
1962     } DW77;
1963 
1964     // DW78
1965     union
1966     {
1967         struct
1968         {
1969             uint32_t   MBQPBuffer                          : MOS_BITFIELD_RANGE( 0, 31);
1970         };
1971         struct
1972         {
1973             uint32_t   Value;
1974         };
1975     } DW78;
1976 
1977     // DW79
1978     union
1979     {
1980         struct
1981         {
1982             uint32_t   MBBRCLut                            : MOS_BITFIELD_RANGE( 0, 31);
1983         };
1984         struct
1985         {
1986             uint32_t   Value;
1987         };
1988     } DW79;
1989 
1990     // DW80
1991     union
1992     {
1993         struct
1994         {
1995             uint32_t   VMEInterPredictionSurfIndex         : MOS_BITFIELD_RANGE( 0, 31);
1996         };
1997         struct
1998         {
1999             uint32_t   Value;
2000         };
2001     } DW80;
2002 
2003     // DW81
2004     union
2005     {
2006         struct
2007         {
2008             uint32_t   VMEInterPredictionMRSurfIndex       : MOS_BITFIELD_RANGE( 0, 31);
2009         };
2010         struct
2011         {
2012             uint32_t   Value;
2013         };
2014     } DW81;
2015 
2016     // DW82
2017     union
2018     {
2019         struct
2020         {
2021             uint32_t   MBStatsSurfIndex                : MOS_BITFIELD_RANGE( 0, 31);
2022         };
2023         struct
2024         {
2025             uint32_t   Value;
2026         };
2027     } DW82;
2028 
2029     // DW83
2030     union
2031     {
2032         struct
2033         {
2034             uint32_t   MADSurfIndex                        : MOS_BITFIELD_RANGE( 0, 31);
2035         };
2036         struct
2037         {
2038             uint32_t   Value;
2039         };
2040     } DW83;
2041 
2042     // DW84
2043     union
2044     {
2045         struct
2046         {
2047             uint32_t   BRCCurbeSurfIndex                   : MOS_BITFIELD_RANGE( 0, 31);
2048         };
2049         struct
2050         {
2051             uint32_t   Value;
2052         };
2053     } DW84;
2054 
2055     // DW85
2056     union
2057     {
2058         struct
2059         {
2060             uint32_t   ForceNonSkipMBmapSurface : MOS_BITFIELD_RANGE(0, 31);
2061         };
2062         struct
2063         {
2064             uint32_t   Value;
2065         };
2066     } DW85;
2067 
2068      // DW86
2069      union
2070      {
2071          struct
2072          {
2073              uint32_t   ReservedIndex                      : MOS_BITFIELD_RANGE(0, 31);
2074          };
2075          struct
2076          {
2077              uint32_t   Value;
2078          };
2079     } DW86;
2080 
2081     // DW87
2082     union
2083     {
2084         struct
2085         {
2086             uint32_t   StaticDetectionCostTableIndex       : MOS_BITFIELD_RANGE( 0, 31);
2087         };
2088         struct
2089         {
2090             uint32_t   Value;
2091         };
2092     } DW87;
2093 
2094 } CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL, *PCODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL;
2095 C_ASSERT(MOS_BYTES_TO_DWORDS(sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)) == 88);
2096 
2097 static const uint32_t CODECHAL_ENCODE_AVC_TrellisQuantizationRounding_G9_KBL[NUM_TARGET_USAGE_MODES] =
2098 {
2099     0, 3, 0, 0, 0, 0, 0, 0
2100 };
2101 
2102 // AVC MBEnc CURBE init data for KBL Kernel
2103 const uint32_t CodechalEncodeAvcEncG9Kbl::MBEnc_CURBE_normal_I_frame[88] =
2104 {
2105     0x00000082, 0x00000000, 0x00003910, 0x00a83000, 0x00000000, 0x28300000, 0x05000000, 0x00000000,
2106     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2107     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2108     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2109     0x80800000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28300000,
2110     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
2111     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2112     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2113     0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2114     0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
2115     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000
2116 };
2117 
2118 const uint32_t CodechalEncodeAvcEncG9Kbl::MBEnc_CURBE_normal_I_field[88] =
2119 {
2120     0x00000082, 0x00000000, 0x00003910, 0x00a830c0, 0x02000000, 0x28300000, 0x05000000, 0x00000000,
2121     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2122     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2123     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2124     0x80800000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28300000,
2125     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000002,
2126     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2127     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2128     0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2129     0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
2130     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000
2131 };
2132 
2133 const uint32_t CodechalEncodeAvcEncG9Kbl::MBEnc_CURBE_normal_P_frame[88] =
2134 {
2135     0x000000a3, 0x00000008, 0x00003910, 0x00ae3000, 0x30000000, 0x28300000, 0x05000000, 0x01400060,
2136     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2137     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2138     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2139     0x80010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x60000000, 0x000000a1, 0x00003900, 0x28300000,
2140     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000002,
2141     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2142     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2143     0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2144     0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
2145     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000
2146 };
2147 
2148 const uint32_t CodechalEncodeAvcEncG9Kbl::MBEnc_CURBE_normal_P_field[88] =
2149 {
2150     0x000000a3, 0x00000008, 0x00003910, 0x00ae30c0, 0x30000000, 0x28300000, 0x05000000, 0x01400060,
2151     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2152     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2153     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2154     0x80010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x000000a1, 0x00003900, 0x28300000,
2155     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x04000002,
2156     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2157     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2158     0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2159     0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
2160     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000
2161 };
2162 
2163 const uint32_t CodechalEncodeAvcEncG9Kbl::MBEnc_CURBE_normal_B_frame[88] =
2164 {
2165     0x000000a3, 0x00200008, 0x00003910, 0x00aa7700, 0x50020000, 0x20200000, 0x05000000, 0xff400000,
2166     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2167     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2168     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2169     0x01010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x60000000, 0x000000a1, 0x00003900, 0x28300000,
2170     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x08000002,
2171     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2172     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2173     0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2174     0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
2175     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000
2176 };
2177 
2178 const uint32_t CodechalEncodeAvcEncG9Kbl::MBEnc_CURBE_normal_B_field[88] =
2179 {
2180     0x000000a3, 0x00200008, 0x00003919, 0x00aa77c0, 0x50020000, 0x20200000, 0x05000000, 0xff400000,
2181     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2182     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2183     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2184     0x01010000, 0x00040c24, 0x00000000, 0xffff00ff, 0x40000000, 0x000000a1, 0x00003900, 0x28300000,
2185     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x04000002,
2186     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2187     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2188     0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2189     0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff,
2190     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0x00000000
2191 };
2192 
2193 // AVC I_DIST CURBE init data for KBL CM Kernel
2194 const uint32_t CodechalEncodeAvcEncG9Kbl::MBEnc_CURBE_I_frame_DIST[88] =
2195 {
2196     0x00000082, 0x00200008, 0x001e3910, 0x00a83000, 0x90000000, 0x28300000, 0x00000000, 0x00000000,
2197     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xff000000, 0x00000000, 0x00000000,
2198     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2199     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000100,
2200     0x80800000, 0x00000000, 0x00000800, 0xffff00ff, 0x40000000, 0x00000080, 0x00003900, 0x28300000,
2201     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2202     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
2203     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0xffffffff,
2204     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2205     0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
2206     0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000
2207 };
2208 
2209 const uint16_t CodechalEncodeAvcEncG9Kbl::Lambda_data[256] = {
2210      9,     7,     9,     6,    12,     8,    12,     8,    15,    10,    15,     9,    19,    13,    19,    12,    24,
2211     17,    24,    15,    30,    21,    30,    19,    38,    27,    38,    24,    48,    34,    48,    31,    60,    43,
2212     60,    39,    76,    54,    76,    49,    96,    68,    96,    62,   121,    85,   121,    78,   153,   108,   153,
2213     99,   193,   135,   193,   125,   243,   171,   243,   157,   306,   215,   307,   199,   385,   271,   387,   251,
2214    485,   342,   488,   317,   612,   431,   616,   400,   771,   543,   777,   505,   971,   684,   981,   638,  1224,
2215    862,  1237,   806,  1542,  1086,  1562,  1018,  1991,  1402,  1971,  1287,  2534,  1785,  2488,  1626,  3077,  2167,
2216   3141,  2054,  3982,  2805,  3966,  2596,  4887,  3442,  5007,  3281,  6154,  4335,  6322,  4148,  7783,  5482,  7984,
2217   5243,  9774,  6885, 10082,  6629, 12489,  8797, 12733,  8382, 15566, 10965, 16082, 10599, 19729, 13897, 20313, 13404,
2218  24797, 17467, 25660, 16954, 31313, 22057, 32415, 21445, 39458, 27795, 40953, 27129, 49594, 34935, 51742, 34323, 61440,
2219  43987, 61440, 43428, 61440, 55462, 61440, 54954, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440,
2220  61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440,
2221  61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440, 61440,
2222  61440, 61440, 61440, 61440,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
2223      0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
2224      0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,     0,
2225      0,
2226 };
2227 
2228 const uint8_t CodechalEncodeAvcEncG9Kbl::FTQ25[64] = //27 value 4 dummy
2229 {
2230     0,                                      //qp=0
2231     0, 0, 0, 0, 0, 0,                       //qp=1,2;3,4;5,6;
2232     1, 1, 3, 3, 6, 6, 8, 8, 11, 11,         //qp=7,8;9,10;11,12;13,14;15;16
2233     13, 13, 16, 16, 19, 19, 22, 22, 26, 26, //qp=17,18;19,20;21,22;23,24;25,26
2234     30, 30, 34, 34, 39, 39, 44, 44, 50, 50, //qp=27,28;29,30;31,32;33,34;35,36
2235     56, 56, 62, 62, 69, 69, 77, 77, 85, 85, //qp=37,38;39,40;41,42;43,44;45,46
2236     94, 94, 104, 104, 115, 115,             //qp=47,48;49,50;51
2237     0, 0, 0, 0, 0, 0, 0, 0                  //dummy
2238 };
2239 
2240 const int32_t CodechalEncodeAvcEncG9Kbl::BRC_BTCOUNTS[CODECHAL_ENCODE_BRC_IDX_NUM] = {
2241     CODECHAL_ENCODE_AVC_BRC_INIT_RESET_NUM_SURFACES,
2242     CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_NUM_SURFACES_G9_KBL,
2243     CODECHAL_ENCODE_AVC_BRC_INIT_RESET_NUM_SURFACES,
2244     CODECHAL_ENCODE_AVC_MBENC_NUM_SURFACES_CM_G9,
2245     CODECHAL_ENCODE_AVC_BRC_BLOCK_COPY_NUM_SURFACES,
2246     CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_NUM_SURFACES_G9_KBL     // MbBRCUpdate kernel starting GEN9
2247 };
2248 
2249 const int32_t CodechalEncodeAvcEncG9Kbl::BRC_CURBE_SIZE[CODECHAL_ENCODE_BRC_IDX_NUM] = {
2250     (sizeof(CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95)),
2251     (sizeof(CODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_G95)),
2252     (sizeof(CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95)),
2253     (sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)),
2254     0,
2255     (sizeof(CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_CURBE_G95))     // MbBRCUpdate kernel starting GEN9
2256 };
2257 
2258 typedef struct _CODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL {
2259     int nKernelCount;
2260 
2261     // Quality mode for Frame/Field
2262     CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_I;
2263     CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_P;
2264     CODECHAL_KERNEL_HEADER AVCMBEnc_Qlty_B;
2265     // Normal mode for Frame/Field
2266     CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_I;
2267     CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_P;
2268     CODECHAL_KERNEL_HEADER AVCMBEnc_Norm_B;
2269     // Performance modes for Frame/Field
2270     CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_I;
2271     CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_P;
2272     CODECHAL_KERNEL_HEADER AVCMBEnc_Perf_B;
2273     // Modes for Frame/Field
2274     CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_I;
2275     CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_P;
2276     CODECHAL_KERNEL_HEADER AVCMBEnc_Adv_B;
2277 
2278     // HME
2279     CODECHAL_KERNEL_HEADER AVC_ME_P;
2280     CODECHAL_KERNEL_HEADER AVC_ME_B;
2281 
2282     // DownScaling
2283     CODECHAL_KERNEL_HEADER PLY_DScale_PLY;
2284     CODECHAL_KERNEL_HEADER PLY_DScale_2f_PLY_2f;
2285 
2286     // BRC init frame
2287     CODECHAL_KERNEL_HEADER InitFrameBRC;
2288 
2289     // Frame BRC update
2290     CODECHAL_KERNEL_HEADER FrameENCUpdate;
2291 
2292     // BRC Reset frame
2293     CODECHAL_KERNEL_HEADER BRC_ResetFrame;
2294 
2295     // BRC I Frame Distortion
2296     CODECHAL_KERNEL_HEADER BRC_IFrame_Dist;
2297 
2298     // BRCBlockCopy
2299     CODECHAL_KERNEL_HEADER BRCBlockCopy;
2300 
2301     // MbBRC Update
2302     CODECHAL_KERNEL_HEADER MbBRCUpdate;
2303 
2304     // 2x DownScaling
2305     CODECHAL_KERNEL_HEADER PLY_2xDScale_PLY;
2306     CODECHAL_KERNEL_HEADER PLY_2xDScale_2f_PLY_2f;
2307 
2308     //Motion estimation kernel for the VDENC StreamIN
2309     CODECHAL_KERNEL_HEADER AVC_ME_VDENC;
2310 
2311     //Weighted Prediction Kernel
2312     CODECHAL_KERNEL_HEADER AVC_WeightedPrediction;
2313 
2314     // Static frame detection Kernel
2315     CODECHAL_KERNEL_HEADER AVC_StaticFrameDetection;
2316 
2317 } CODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL, *PCODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL;
2318 
GetKernelHeaderAndSize(void * binary,EncOperation operation,uint32_t krnStateIdx,void * krnHeader,uint32_t * krnSize)2319 MOS_STATUS CodechalEncodeAvcEncG9Kbl::GetKernelHeaderAndSize(
2320     void                           *binary,
2321     EncOperation                   operation,
2322     uint32_t                       krnStateIdx,
2323     void                           *krnHeader,
2324     uint32_t                       *krnSize)
2325 {
2326     MOS_STATUS  eStatus = MOS_STATUS_SUCCESS;
2327 
2328     CODECHAL_ENCODE_FUNCTION_ENTER;
2329 
2330     CODECHAL_ENCODE_CHK_NULL_RETURN(binary);
2331     CODECHAL_ENCODE_CHK_NULL_RETURN(krnHeader);
2332     CODECHAL_ENCODE_CHK_NULL_RETURN(krnSize);
2333 
2334     auto kernelHeaderTable = (PCODECHAL_ENCODE_AVC_KERNEL_HEADER_G9_KBL)binary;
2335 
2336     auto invalidEntry = &(kernelHeaderTable->AVC_StaticFrameDetection) + 1;
2337     uint32_t nextKrnOffset = *krnSize;
2338     PCODECHAL_KERNEL_HEADER currKrnHeader = nullptr;
2339 
2340     if (operation == ENC_SCALING4X)
2341     {
2342         currKrnHeader = &kernelHeaderTable->PLY_DScale_PLY;
2343     }
2344     else if (operation == ENC_SCALING2X)
2345     {
2346         currKrnHeader = &kernelHeaderTable->PLY_2xDScale_PLY;
2347     }
2348     else if (operation == ENC_ME)
2349     {
2350         currKrnHeader = &kernelHeaderTable->AVC_ME_P;
2351     }
2352     else if (operation == VDENC_ME)
2353     {
2354         currKrnHeader = &kernelHeaderTable->AVC_ME_VDENC;
2355     }
2356     else if (operation == ENC_BRC)
2357     {
2358         currKrnHeader = &kernelHeaderTable->InitFrameBRC;
2359     }
2360     else if (operation == ENC_MBENC)
2361     {
2362         currKrnHeader = &kernelHeaderTable->AVCMBEnc_Qlty_I;
2363     }
2364     else if (operation == ENC_MBENC_ADV)
2365     {
2366         currKrnHeader = &kernelHeaderTable->AVCMBEnc_Adv_I;
2367     }
2368     else if (operation == ENC_WP)
2369     {
2370         currKrnHeader = &kernelHeaderTable->AVC_WeightedPrediction;
2371     }
2372     else if (operation == ENC_SFD)
2373     {
2374         currKrnHeader = &kernelHeaderTable->AVC_StaticFrameDetection;
2375     }
2376     else
2377     {
2378         CODECHAL_ENCODE_ASSERTMESSAGE("Unsupported ENC mode requested");
2379         eStatus = MOS_STATUS_INVALID_PARAMETER;
2380         return eStatus;
2381     }
2382 
2383     currKrnHeader += krnStateIdx;
2384     *((PCODECHAL_KERNEL_HEADER)krnHeader) = *currKrnHeader;
2385 
2386     auto nextKrnHeader = (currKrnHeader + 1);
2387     if (nextKrnHeader < invalidEntry)
2388     {
2389         nextKrnOffset = nextKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT;
2390     }
2391     *krnSize = nextKrnOffset - (currKrnHeader->KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
2392 
2393     return eStatus;
2394 }
2395 
SetCurbeAvcMbEnc(PCODECHAL_ENCODE_AVC_MBENC_CURBE_PARAMS params)2396 MOS_STATUS CodechalEncodeAvcEncG9Kbl::SetCurbeAvcMbEnc(
2397         PCODECHAL_ENCODE_AVC_MBENC_CURBE_PARAMS params)
2398 {
2399 
2400     MOS_STATUS                          eStatus = MOS_STATUS_SUCCESS;
2401 
2402     CODECHAL_ENCODE_FUNCTION_ENTER;
2403 
2404     CODECHAL_ENCODE_CHK_NULL_RETURN(m_hwInterface->GetRenderInterface());
2405     CODECHAL_ENCODE_CHK_NULL_RETURN(params);
2406     CODECHAL_ENCODE_CHK_NULL_RETURN(params->pPicParams);
2407     CODECHAL_ENCODE_CHK_NULL_RETURN(params->pSeqParams);
2408     CODECHAL_ENCODE_CHK_NULL_RETURN(params->pSlcParams);
2409 
2410     auto picParams = params->pPicParams;
2411     auto seqParams = params->pSeqParams;
2412     auto slcParams = params->pSlcParams;
2413 
2414     MHW_VDBOX_AVC_SLICE_STATE sliceState;
2415     MOS_ZeroMemory(&sliceState, sizeof(sliceState));
2416     sliceState.pEncodeAvcSeqParams = seqParams;
2417     sliceState.pEncodeAvcPicParams = picParams;
2418     sliceState.pEncodeAvcSliceParams = slcParams;
2419 
2420     CODECHAL_ENCODE_ASSERT(seqParams->TargetUsage < NUM_TARGET_USAGE_MODES);
2421 
2422     uint8_t meMethod =
2423         (m_pictureCodingType == B_TYPE) ? m_bMeMethodGeneric[seqParams->TargetUsage] : m_meMethodGeneric[seqParams->TargetUsage];
2424     // set sliceQP to MAX_SLICE_QP for MbEnc Adv kernel, we can use it to verify whether QP is changed or not
2425     uint8_t sliceQP = (params->bUseMbEncAdvKernel && params->bBrcEnabled) ? CODECHAL_ENCODE_AVC_MAX_SLICE_QP : picParams->pic_init_qp_minus26 + 26 + slcParams->slice_qp_delta;
2426     bool framePicture = CodecHal_PictureIsFrame(picParams->CurrOriginalPic);
2427     bool topField = CodecHal_PictureIsTopField(picParams->CurrOriginalPic);
2428     bool bottomField = CodecHal_PictureIsBottomField(picParams->CurrOriginalPic);
2429 
2430     CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL cmd;
2431 
2432     if (params->bMbEncIFrameDistEnabled)
2433     {
2434         CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
2435             &cmd,
2436             sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL),
2437             MBEnc_CURBE_I_frame_DIST,
2438             sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)));
2439     }
2440     else
2441     {
2442         switch (m_pictureCodingType)
2443         {
2444         case I_TYPE:
2445             if (framePicture)
2446             {
2447                 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
2448                     &cmd,
2449                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL),
2450                     MBEnc_CURBE_normal_I_frame,
2451                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)));
2452             }
2453             else
2454             {
2455                 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
2456                     &cmd,
2457                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL),
2458                     MBEnc_CURBE_normal_I_field,
2459                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)));
2460             }
2461             break;
2462 
2463         case P_TYPE:
2464             if (framePicture)
2465             {
2466                 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
2467                     &cmd,
2468                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL),
2469                     MBEnc_CURBE_normal_P_frame,
2470                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)));
2471             }
2472             else
2473             {
2474                 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
2475                     &cmd,
2476                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL),
2477                     MBEnc_CURBE_normal_P_field,
2478                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)));
2479             }
2480             break;
2481 
2482         case B_TYPE:
2483             if (framePicture)
2484             {
2485                 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
2486                     &cmd,
2487                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL),
2488                     MBEnc_CURBE_normal_B_frame,
2489                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)));
2490             }
2491             else
2492             {
2493                 CODECHAL_ENCODE_CHK_STATUS_RETURN(MOS_SecureMemcpy(
2494                     &cmd,
2495                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL),
2496                     MBEnc_CURBE_normal_B_field,
2497                     sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL)));
2498             }
2499             break;
2500 
2501         default:
2502             CODECHAL_ENCODE_ASSERTMESSAGE("Invalid picture coding type.");
2503             eStatus = MOS_STATUS_UNKNOWN;
2504             return eStatus;
2505         }
2506     }
2507 
2508     // r1
2509     cmd.DW0.AdaptiveEn =
2510         cmd.DW37.AdaptiveEn = EnableAdaptiveSearch[seqParams->TargetUsage];
2511     cmd.DW0.T8x8FlagForInterEn =
2512         cmd.DW37.T8x8FlagForInterEn = picParams->transform_8x8_mode_flag;
2513     cmd.DW2.LenSP = MaxLenSP[seqParams->TargetUsage];
2514 
2515     cmd.DW1.ExtendedMvCostRange = bExtendedMvCostRange;
2516     cmd.DW36.MBInputEnable = bMbSpecificDataEnabled;
2517     cmd.DW38.LenSP = 0; // MBZ
2518     cmd.DW3.SrcAccess =
2519         cmd.DW3.RefAccess = framePicture ? 0 : 1;
2520     if (m_pictureCodingType != I_TYPE &&  bFTQEnable)
2521     {
2522         if (m_pictureCodingType == P_TYPE)
2523         {
2524             cmd.DW3.FTEnable = FTQBasedSkip[seqParams->TargetUsage] & 0x01;
2525         }
2526         else // B_TYPE
2527         {
2528             cmd.DW3.FTEnable = (FTQBasedSkip[seqParams->TargetUsage] >> 1) & 0x01;
2529         }
2530     }
2531     else
2532     {
2533         cmd.DW3.FTEnable = 0;
2534     }
2535     if (picParams->UserFlags.bDisableSubMBPartition)
2536     {
2537         cmd.DW3.SubMbPartMask = CODECHAL_ENCODE_AVC_DISABLE_4X4_SUB_MB_PARTITION | CODECHAL_ENCODE_AVC_DISABLE_4X8_SUB_MB_PARTITION | CODECHAL_ENCODE_AVC_DISABLE_8X4_SUB_MB_PARTITION;
2538     }
2539     cmd.DW2.PicWidth                             = params->wPicWidthInMb;
2540     cmd.DW4.PicHeightMinus1                      = params->wFieldFrameHeightInMb - 1;
2541     cmd.DW4.FieldParityFlag                      = cmd.DW7.SrcFieldPolarity = bottomField ? 1 : 0;
2542     cmd.DW4.EnableFBRBypass                      =  bFBRBypassEnable;
2543     cmd.DW4.EnableIntraCostScalingForStaticFrame = params->bStaticFrameDetectionEnabled;
2544     cmd.DW4.bCurFldIDR                           = framePicture ? 0 : (picParams->bIdrPic || m_firstFieldIdrPic);
2545     cmd.DW4.ConstrainedIntraPredFlag             = picParams->constrained_intra_pred_flag;
2546     cmd.DW4.HMEEnable                            = m_hmeEnabled;
2547     cmd.DW4.PictureType                          = m_pictureCodingType - 1;
2548     cmd.DW4.UseActualRefQPValue                  = m_hmeEnabled ? (MRDisableQPCheck[seqParams->TargetUsage] == 0) : false;
2549     cmd.DW5.SliceMbHeight                        = params->usSliceHeight;
2550     cmd.DW7.IntraPartMask                        = picParams->transform_8x8_mode_flag ? 0 : 0x2;  // Disable 8x8 if flag is not set
2551 
2552     // r2
2553     if (params->bMbEncIFrameDistEnabled)
2554     {
2555         cmd.DW6.BatchBufferEnd = 0;
2556     }
2557     else
2558     {
2559         uint8_t tableIdx = m_pictureCodingType - 1;
2560         eStatus = MOS_SecureMemcpy(&(cmd.ModeMvCost), 8 * sizeof(uint32_t), ModeMvCost_Cm[tableIdx][sliceQP], 8 * sizeof(uint32_t));
2561         if (eStatus != MOS_STATUS_SUCCESS)
2562         {
2563             CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
2564             return eStatus;
2565         }
2566 
2567         if (m_pictureCodingType == I_TYPE &&  bOldModeCostEnable)
2568         {
2569             // Old intra mode cost needs to be used if bOldModeCostEnable is 1
2570             cmd.ModeMvCost.DW8.Value = OldIntraModeCost_Cm_Common[sliceQP];
2571         }
2572         else if (m_skipBiasAdjustmentEnable)
2573         {
2574             // Load different MvCost for P picture when SkipBiasAdjustment is enabled
2575             // No need to check for P picture as the flag is only enabled for P picture
2576             cmd.ModeMvCost.DW11.Value = MvCost_PSkipAdjustment_Cm_Common[sliceQP];
2577         }
2578     }
2579 
2580     // r3 & r4
2581     if (params->bMbEncIFrameDistEnabled)
2582     {
2583         cmd.SPDelta.DW31.IntraComputeType = 1;
2584     }
2585     else
2586     {
2587         uint8_t tableIdx = (m_pictureCodingType == B_TYPE) ? 1 : 0;
2588         eStatus = MOS_SecureMemcpy(&(cmd.SPDelta), 16 * sizeof(uint32_t), CodechalEncoderState::m_encodeSearchPath[tableIdx][meMethod], 16 * sizeof(uint32_t));
2589         if (eStatus != MOS_STATUS_SUCCESS)
2590         {
2591             CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
2592             return eStatus;
2593         }
2594     }
2595 
2596     // r5
2597     if (m_pictureCodingType == P_TYPE)
2598     {
2599         cmd.DW32.SkipVal = SkipVal_P_Common
2600             [cmd.DW3.BlockBasedSkipEnable]
2601         [picParams->transform_8x8_mode_flag]
2602         [sliceQP];
2603     }
2604     else if (m_pictureCodingType == B_TYPE)
2605     {
2606         cmd.DW32.SkipVal = SkipVal_B_Common
2607             [cmd.DW3.BlockBasedSkipEnable]
2608         [picParams->transform_8x8_mode_flag]
2609         [sliceQP];
2610     }
2611 
2612     cmd.ModeMvCost.DW13.QpPrimeY = sliceQP;
2613     // QpPrimeCb and QpPrimeCr are not used by Kernel. Following settings are for CModel matching.
2614     cmd.ModeMvCost.DW13.QpPrimeCb = sliceQP;
2615     cmd.ModeMvCost.DW13.QpPrimeCr = sliceQP;
2616     cmd.ModeMvCost.DW13.TargetSizeInWord = 0xff; // hardcoded for BRC disabled
2617 
2618     if ( bMultiPredEnable && (m_pictureCodingType != I_TYPE))
2619     {
2620         switch (MultiPred[seqParams->TargetUsage])
2621         {
2622         case 0: // Disable multipred for both P & B picture types
2623             cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2624             cmd.DW32.MultiPredL1Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2625             break;
2626 
2627         case 1: // Enable multipred for P pictures only
2628             cmd.DW32.MultiPredL0Disable = (m_pictureCodingType == P_TYPE) ? CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2629             cmd.DW32.MultiPredL1Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2630             break;
2631 
2632         case 2: // Enable multipred for B pictures only
2633             cmd.DW32.MultiPredL0Disable = (m_pictureCodingType == B_TYPE) ?
2634             CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2635             cmd.DW32.MultiPredL1Disable = (m_pictureCodingType == B_TYPE) ?
2636             CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2637             break;
2638 
2639         case 3: // Enable multipred for both P & B picture types
2640             cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE;
2641             cmd.DW32.MultiPredL1Disable = (m_pictureCodingType == B_TYPE) ?
2642             CODECHAL_ENCODE_AVC_MULTIPRED_ENABLE : CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2643             break;
2644         }
2645     }
2646     else
2647     {
2648         cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2649         cmd.DW32.MultiPredL1Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2650     }
2651 
2652     if (!framePicture)
2653     {
2654         if (m_pictureCodingType != I_TYPE)
2655         {
2656             cmd.DW34.List0RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_0);
2657             cmd.DW34.List0RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_1);
2658             cmd.DW34.List0RefID2FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_2);
2659             cmd.DW34.List0RefID3FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_3);
2660             cmd.DW34.List0RefID4FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_4);
2661             cmd.DW34.List0RefID5FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_5);
2662             cmd.DW34.List0RefID6FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_6);
2663             cmd.DW34.List0RefID7FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_0, CODECHAL_ENCODE_REF_ID_7);
2664         }
2665         if (m_pictureCodingType == B_TYPE)
2666         {
2667             cmd.DW34.List1RefID0FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_0);
2668             cmd.DW34.List1RefID1FieldParity = CodecHalAvcEncode_GetFieldParity(slcParams, LIST_1, CODECHAL_ENCODE_REF_ID_1);
2669         }
2670     }
2671 
2672     if (m_adaptiveTransformDecisionEnabled)
2673     {
2674         if (m_pictureCodingType != I_TYPE)
2675         {
2676             cmd.DW34.EnableAdaptiveTxDecision = true;
2677         }
2678         cmd.DW60.TxDecisonThreshold = CODECHAL_ENCODE_AVC_ADAPTIVE_TX_DECISION_THRESHOLD_G9;
2679     }
2680     if (m_adaptiveTransformDecisionEnabled || m_flatnessCheckEnabled)
2681     {
2682         cmd.DW60.MBTextureThreshold = CODECHAL_ENCODE_AVC_MB_TEXTURE_THRESHOLD_G9;
2683     }
2684     if (m_pictureCodingType == B_TYPE)
2685     {
2686         cmd.DW34.List1RefID0FrameFieldFlag = GetRefPicFieldFlag(params, LIST_1, CODECHAL_ENCODE_REF_ID_0);
2687         cmd.DW34.List1RefID1FrameFieldFlag = GetRefPicFieldFlag(params, LIST_1, CODECHAL_ENCODE_REF_ID_1);
2688         cmd.DW34.bDirectMode = slcParams->direct_spatial_mv_pred_flag;
2689     }
2690 
2691     cmd.DW34.EnablePerMBStaticCheck         = params->bStaticFrameDetectionEnabled;
2692     cmd.DW34.EnableAdaptiveSearchWindowSize = params->bApdatvieSearchWindowSizeEnabled;
2693     cmd.DW34.RemoveIntraRefreshOverlap      = picParams->bDisableRollingIntraRefreshOverlap;
2694     cmd.DW34.bOriginalBff = framePicture ? 0 :
2695         ((m_firstField && (bottomField)) || (!m_firstField && (!bottomField)));
2696     cmd.DW34.EnableMBFlatnessChkOptimization = m_flatnessCheckEnabled;
2697     cmd.DW34.ROIEnableFlag = params->bRoiEnabled;
2698     cmd.DW34.MADEnableFlag                   = m_madEnabled;
2699     cmd.DW34.MBBrcEnable =  bMbBrcEnabled ||  bMbQpDataEnabled;
2700     cmd.DW34.ArbitraryNumMbsPerSlice = m_arbitraryNumMbsInSlice;
2701     cmd.DW34.ForceNonSkipMbEnable = params->bMbDisableSkipMapEnabled;
2702     if (params->pAvcQCParams && !cmd.DW34.ForceNonSkipMbEnable) // ignore DisableEncSkipCheck if Mb Disable Skip Map is available
2703     {
2704         cmd.DW34.DisableEncSkipCheck = params->pAvcQCParams->skipCheckDisable;
2705     }
2706     cmd.DW34.TQEnable = m_trellisQuantParams.dwTqEnabled; //Enabled for KBL
2707     cmd.DW34.CQPFlag = ! bBrcEnabled; // 1 - Rate Control is CQP, 0 - Rate Control is BRC
2708     cmd.DW36.CheckAllFractionalEnable =  bCAFEnable;
2709     cmd.DW38.RefThreshold = m_refThreshold;
2710     cmd.DW39.HMERefWindowsCombThreshold = (m_pictureCodingType == B_TYPE) ?
2711         HMEBCombineLen[seqParams->TargetUsage] : HMECombineLen[seqParams->TargetUsage];
2712 
2713     // Default:2 used for MBBRC (MB QP Surface width and height are 4x downscaled picture in MB unit * 4  bytes)
2714     // 0 used for MBQP data surface (MB QP Surface width and height are same as the input picture size in MB unit * 1bytes)
2715     // BRC use split kernel, MB QP surface is same size as input picture
2716     cmd.DW47.MbQpReadFactor = ( bMbBrcEnabled ||  bMbQpDataEnabled) ? 0 : 2;
2717 
2718     // Those fields are not really used for I_dist kernel,
2719     // but set them to 0 to get bit-exact match with kernel prototype
2720     if (params->bMbEncIFrameDistEnabled)
2721     {
2722         cmd.ModeMvCost.DW13.QpPrimeY = 0;
2723         cmd.ModeMvCost.DW13.QpPrimeCb = 0;
2724         cmd.ModeMvCost.DW13.QpPrimeCr = 0;
2725         cmd.DW33.Intra16x16NonDCPredPenalty = 0;
2726         cmd.DW33.Intra4x4NonDCPredPenalty = 0;
2727         cmd.DW33.Intra8x8NonDCPredPenalty = 0;
2728     }
2729 
2730     //r6
2731     if (cmd.DW4.UseActualRefQPValue)
2732     {
2733         cmd.DW44.ActualQPValueForRefID0List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_0);
2734         cmd.DW44.ActualQPValueForRefID1List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_1);
2735         cmd.DW44.ActualQPValueForRefID2List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_2);
2736         cmd.DW44.ActualQPValueForRefID3List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_3);
2737         cmd.DW45.ActualQPValueForRefID4List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_4);
2738         cmd.DW45.ActualQPValueForRefID5List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_5);
2739         cmd.DW45.ActualQPValueForRefID6List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_6);
2740         cmd.DW45.ActualQPValueForRefID7List0 = AVCGetQPValueFromRefList(params, LIST_0, CODECHAL_ENCODE_REF_ID_7);
2741         cmd.DW46.ActualQPValueForRefID0List1 = AVCGetQPValueFromRefList(params, LIST_1, CODECHAL_ENCODE_REF_ID_0);
2742         cmd.DW46.ActualQPValueForRefID1List1 = AVCGetQPValueFromRefList(params, LIST_1, CODECHAL_ENCODE_REF_ID_1);
2743     }
2744 
2745     uint8_t tableIdx = m_pictureCodingType - 1;
2746     cmd.DW46.RefCost = RefCost_MultiRefQp[tableIdx][sliceQP];
2747 
2748     // Picture Coding Type dependent parameters
2749     if (m_pictureCodingType == I_TYPE)
2750     {
2751         cmd.DW0.SkipModeEn = 0;
2752         cmd.DW37.SkipModeEn = 0;
2753         cmd.DW36.HMECombineOverlap = 0;
2754         cmd.DW47.IntraCostSF = 16; // This is not used but recommended to set this to 16 by Kernel team
2755         cmd.DW34.EnableDirectBiasAdjustment = 0;
2756     }
2757     else if (m_pictureCodingType == P_TYPE)
2758     {
2759         cmd.DW1.MaxNumMVs = GetMaxMvsPer2Mb(seqParams->Level) / 2;
2760         cmd.DW3.BMEDisableFBR = 1;
2761         cmd.DW5.RefWidth = SearchX[seqParams->TargetUsage];
2762         cmd.DW5.RefHeight = SearchY[seqParams->TargetUsage];
2763         cmd.DW7.NonSkipZMvAdded = 1;
2764         cmd.DW7.NonSkipModeAdded = 1;
2765         cmd.DW7.SkipCenterMask = 1;
2766         cmd.DW47.IntraCostSF =
2767              bAdaptiveIntraScalingEnable ?
2768             AdaptiveIntraScalingFactor_Cm_Common[sliceQP] :
2769             IntraScalingFactor_Cm_Common[sliceQP];
2770         cmd.DW47.MaxVmvR = (framePicture) ? CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) * 4 : (CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) >> 1) * 4;
2771         cmd.DW36.HMECombineOverlap = 1;
2772         cmd.DW36.NumRefIdxL0MinusOne =  bMultiPredEnable ? slcParams->num_ref_idx_l0_active_minus1 : 0;
2773         cmd.DW39.RefWidth = SearchX[seqParams->TargetUsage];
2774         cmd.DW39.RefHeight = SearchY[seqParams->TargetUsage];
2775         cmd.DW34.EnableDirectBiasAdjustment = 0;
2776         if (params->pAvcQCParams)
2777         {
2778             cmd.DW34.EnableGlobalMotionBiasAdjustment = params->pAvcQCParams->globalMotionBiasAdjustmentEnable;
2779         }
2780     }
2781     else
2782     {
2783         // B_TYPE
2784         cmd.DW1.MaxNumMVs = GetMaxMvsPer2Mb(seqParams->Level) / 2;
2785         cmd.DW1.BiWeight = m_biWeight;
2786         cmd.DW3.SearchCtrl = 7;
2787         cmd.DW3.SkipType = 1;
2788         cmd.DW5.RefWidth = BSearchX[seqParams->TargetUsage];
2789         cmd.DW5.RefHeight = BSearchY[seqParams->TargetUsage];
2790         cmd.DW7.SkipCenterMask = 0xFF;
2791         cmd.DW47.IntraCostSF =
2792              bAdaptiveIntraScalingEnable ?
2793             AdaptiveIntraScalingFactor_Cm_Common[sliceQP] :
2794             IntraScalingFactor_Cm_Common[sliceQP];
2795         cmd.DW47.MaxVmvR = (framePicture) ? CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) * 4 : (CodecHalAvcEncode_GetMaxMvLen(seqParams->Level) >> 1) * 4;
2796         cmd.DW36.HMECombineOverlap = 1;
2797         // Checking if the forward frame (List 1 index 0) is a short term reference
2798         {
2799             CODEC_PICTURE codecHalPic = params->pSlcParams->RefPicList[LIST_1][0];
2800             if (codecHalPic.PicFlags != PICTURE_INVALID &&
2801                 codecHalPic.FrameIdx != CODECHAL_ENCODE_AVC_INVALID_PIC_ID &&
2802                 params->pPicIdx[codecHalPic.FrameIdx].bValid)
2803             {
2804                 // Although its name is FWD, it actually means the future frame or the backward reference frame
2805                 cmd.DW36.IsFwdFrameShortTermRef = CodecHal_PictureIsShortTermRef(params->pPicParams->RefFrameList[codecHalPic.FrameIdx]);
2806             }
2807             else
2808             {
2809                 CODECHAL_ENCODE_ASSERTMESSAGE("Invalid backward reference frame.");
2810                 eStatus = MOS_STATUS_INVALID_PARAMETER;
2811                 return eStatus;
2812             }
2813         }
2814         cmd.DW36.NumRefIdxL0MinusOne =  bMultiPredEnable ? slcParams->num_ref_idx_l0_active_minus1 : 0;
2815         cmd.DW36.NumRefIdxL1MinusOne =  bMultiPredEnable ? slcParams->num_ref_idx_l1_active_minus1 : 0;
2816         cmd.DW39.RefWidth = BSearchX[seqParams->TargetUsage];
2817         cmd.DW39.RefHeight = BSearchY[seqParams->TargetUsage];
2818         cmd.DW40.DistScaleFactorRefID0List0 = m_distScaleFactorList0[0];
2819         cmd.DW40.DistScaleFactorRefID1List0 = m_distScaleFactorList0[1];
2820         cmd.DW41.DistScaleFactorRefID2List0 = m_distScaleFactorList0[2];
2821         cmd.DW41.DistScaleFactorRefID3List0 = m_distScaleFactorList0[3];
2822         cmd.DW42.DistScaleFactorRefID4List0 = m_distScaleFactorList0[4];
2823         cmd.DW42.DistScaleFactorRefID5List0 = m_distScaleFactorList0[5];
2824         cmd.DW43.DistScaleFactorRefID6List0 = m_distScaleFactorList0[6];
2825         cmd.DW43.DistScaleFactorRefID7List0 = m_distScaleFactorList0[7];
2826         if (params->pAvcQCParams)
2827         {
2828             cmd.DW34.EnableDirectBiasAdjustment = params->pAvcQCParams->directBiasAdjustmentEnable;
2829             if (cmd.DW34.EnableDirectBiasAdjustment)
2830             {
2831                 cmd.DW7.NonSkipModeAdded = 1;
2832                 cmd.DW7.NonSkipZMvAdded  = 1;
2833             }
2834 
2835             cmd.DW34.EnableGlobalMotionBiasAdjustment = params->pAvcQCParams->globalMotionBiasAdjustmentEnable;
2836         }
2837     }
2838 
2839     *params->pdwBlockBasedSkipEn = cmd.DW3.BlockBasedSkipEnable;
2840 
2841     if (picParams->EnableRollingIntraRefresh)
2842     {
2843         cmd.DW34.IntraRefreshEn = picParams->EnableRollingIntraRefresh;
2844 
2845         /* Multiple predictor should be completely disabled for the RollingI feature. This does not lead to much quality drop for P frames especially for TU as 1 */
2846         cmd.DW32.MultiPredL0Disable = CODECHAL_ENCODE_AVC_MULTIPRED_DISABLE;
2847 
2848         /* Pass the same IntraRefreshUnit to the kernel w/o the adjustment by -1, so as to have an overlap of one MB row or column of Intra macroblocks
2849          across one P frame to another P frame, as needed by the RollingI algo */
2850         if (ROLLING_I_SQUARE == picParams->EnableRollingIntraRefresh && RATECONTROL_CQP != seqParams->RateControlMethod)
2851         {
2852             /*BRC update kernel updates these CURBE to MBEnc*/
2853             cmd.DW4.EnableIntraRefresh = false;
2854             cmd.DW34.IntraRefreshEn = ROLLING_I_DISABLED;
2855             cmd.DW48.IntraRefreshMBx = 0; /* MB column number */
2856             cmd.DW61.IntraRefreshMBy = 0; /* MB row number */
2857         }
2858         else
2859         {
2860             cmd.DW4.EnableIntraRefresh = true;
2861             cmd.DW34.IntraRefreshEn = picParams->EnableRollingIntraRefresh;
2862             cmd.DW48.IntraRefreshMBx = picParams->IntraRefreshMBx; /* MB column number */
2863             cmd.DW61.IntraRefreshMBy = picParams->IntraRefreshMBy; /* MB row number */
2864         }
2865         cmd.DW48.IntraRefreshUnitInMBMinus1 = picParams->IntraRefreshUnitinMB;
2866         cmd.DW48.IntraRefreshQPDelta = picParams->IntraRefreshQPDelta;
2867     }
2868     else
2869     {
2870         cmd.DW34.IntraRefreshEn = 0;
2871     }
2872 
2873     if (true == params->bRoiEnabled)
2874     {
2875         cmd.DW49.ROI1_X_left = picParams->ROI[0].Left;
2876         cmd.DW49.ROI1_Y_top = picParams->ROI[0].Top;
2877         cmd.DW50.ROI1_X_right = picParams->ROI[0].Right;
2878         cmd.DW50.ROI1_Y_bottom = picParams->ROI[0].Bottom;
2879 
2880         cmd.DW51.ROI2_X_left = picParams->ROI[1].Left;
2881         cmd.DW51.ROI2_Y_top = picParams->ROI[1].Top;
2882         cmd.DW52.ROI2_X_right = picParams->ROI[1].Right;
2883         cmd.DW52.ROI2_Y_bottom = picParams->ROI[1].Bottom;
2884 
2885         cmd.DW53.ROI3_X_left = picParams->ROI[2].Left;
2886         cmd.DW53.ROI3_Y_top = picParams->ROI[2].Top;
2887         cmd.DW54.ROI3_X_right = picParams->ROI[2].Right;
2888         cmd.DW54.ROI3_Y_bottom = picParams->ROI[2].Bottom;
2889 
2890         cmd.DW55.ROI4_X_left = picParams->ROI[3].Left;
2891         cmd.DW55.ROI4_Y_top = picParams->ROI[3].Top;
2892         cmd.DW56.ROI4_X_right = picParams->ROI[3].Right;
2893         cmd.DW56.ROI4_Y_bottom = picParams->ROI[3].Bottom;
2894 
2895         if ( bBrcEnabled == false)
2896         {
2897             uint16_t numROI = picParams->NumROI;
2898             char priorityLevelOrDQp[CODECHAL_ENCODE_AVC_MAX_ROI_NUMBER] = { 0 };
2899 
2900             // cqp case
2901             for (unsigned int i = 0; i < numROI; i += 1)
2902             {
2903                 char dQpRoi = picParams->ROI[i].PriorityLevelOrDQp;
2904 
2905                 // clip qp roi in order to have (qp + qpY) in range [0, 51]
2906                 priorityLevelOrDQp[i] = (char)CodecHal_Clip3(-sliceQP, CODECHAL_ENCODE_AVC_MAX_SLICE_QP - sliceQP, dQpRoi);
2907             }
2908 
2909             cmd.DW57.ROI1_dQpPrimeY = priorityLevelOrDQp[0];
2910             cmd.DW57.ROI2_dQpPrimeY = priorityLevelOrDQp[1];
2911             cmd.DW57.ROI3_dQpPrimeY = priorityLevelOrDQp[2];
2912             cmd.DW57.ROI4_dQpPrimeY = priorityLevelOrDQp[3];
2913         }
2914         else
2915         {
2916             // kernel does not support BRC case
2917             cmd.DW34.ROIEnableFlag = 0;
2918         }
2919     }
2920     else if (params->bDirtyRoiEnabled)
2921     {
2922         // enable Dirty Rect flag
2923         cmd.DW4.EnableDirtyRect = true;
2924 
2925         cmd.DW49.ROI1_X_left      = params->pPicParams->DirtyROI[0].Left;
2926         cmd.DW49.ROI1_Y_top       = params->pPicParams->DirtyROI[0].Top;
2927         cmd.DW50.ROI1_X_right     = params->pPicParams->DirtyROI[0].Right;
2928         cmd.DW50.ROI1_Y_bottom    = params->pPicParams->DirtyROI[0].Bottom;
2929 
2930         cmd.DW51.ROI2_X_left      = params->pPicParams->DirtyROI[1].Left;
2931         cmd.DW51.ROI2_Y_top       = params->pPicParams->DirtyROI[1].Top;
2932         cmd.DW52.ROI2_X_right     = params->pPicParams->DirtyROI[1].Right;
2933         cmd.DW52.ROI2_Y_bottom    = params->pPicParams->DirtyROI[1].Bottom;
2934 
2935         cmd.DW53.ROI3_X_left      = params->pPicParams->DirtyROI[2].Left;
2936         cmd.DW53.ROI3_Y_top       = params->pPicParams->DirtyROI[2].Top;
2937         cmd.DW54.ROI3_X_right     = params->pPicParams->DirtyROI[2].Right;
2938         cmd.DW54.ROI3_Y_bottom    = params->pPicParams->DirtyROI[2].Bottom;
2939 
2940         cmd.DW55.ROI4_X_left      = params->pPicParams->DirtyROI[3].Left;
2941         cmd.DW55.ROI4_Y_top       = params->pPicParams->DirtyROI[3].Top;
2942         cmd.DW56.ROI4_X_right     = params->pPicParams->DirtyROI[3].Right;
2943         cmd.DW56.ROI4_Y_bottom    = params->pPicParams->DirtyROI[3].Bottom;
2944     }
2945 
2946     if (m_trellisQuantParams.dwTqEnabled)
2947     {
2948         // Lambda values for TQ
2949         if (m_pictureCodingType == I_TYPE)
2950         {
2951             cmd.DW58.Value = TQ_LAMBDA_I_FRAME[sliceQP][0];
2952             cmd.DW59.Value = TQ_LAMBDA_I_FRAME[sliceQP][1];
2953         }
2954         else if (m_pictureCodingType == P_TYPE)
2955         {
2956             cmd.DW58.Value = TQ_LAMBDA_P_FRAME[sliceQP][0];
2957             cmd.DW59.Value = TQ_LAMBDA_P_FRAME[sliceQP][1];
2958 
2959         }
2960         else
2961         {
2962             cmd.DW58.Value = TQ_LAMBDA_B_FRAME[sliceQP][0];
2963             cmd.DW59.Value = TQ_LAMBDA_B_FRAME[sliceQP][1];
2964         }
2965 
2966         // check if Lambda is greater than max value
2967         CODECHAL_ENCODE_CHK_STATUS_RETURN( GetInterRounding(&sliceState));
2968 
2969         if (cmd.DW58.Lambda_8x8Inter > CODECHAL_ENCODE_AVC_MAX_LAMBDA)
2970         {
2971             cmd.DW58.Lambda_8x8Inter = 0xf000 + sliceState.dwRoundingValue;
2972         }
2973 
2974         if (cmd.DW58.Lambda_8x8Intra > CODECHAL_ENCODE_AVC_MAX_LAMBDA)
2975         {
2976 
2977             cmd.DW58.Lambda_8x8Intra = 0xf000 + DEFAULT_TRELLIS_QUANT_INTRA_ROUNDING_G9_KBL;
2978         }
2979 
2980         // check if Lambda is greater than max value
2981         if (cmd.DW59.Lambda_Inter > CODECHAL_ENCODE_AVC_MAX_LAMBDA)
2982         {
2983             cmd.DW59.Lambda_Inter = 0xf000 + sliceState.dwRoundingValue;
2984         }
2985 
2986         if (cmd.DW59.Lambda_Intra > CODECHAL_ENCODE_AVC_MAX_LAMBDA)
2987         {
2988             cmd.DW59.Lambda_Intra = 0xf000 + DEFAULT_TRELLIS_QUANT_INTRA_ROUNDING_G9_KBL;
2989         }
2990     }
2991 
2992     //IPCM QP and threshold
2993     cmd.DW62.IPCM_QP0     = IPCM_Threshold_Table[0].QP;
2994     cmd.DW62.IPCM_QP1     = IPCM_Threshold_Table[1].QP;
2995     cmd.DW62.IPCM_QP2     = IPCM_Threshold_Table[2].QP;
2996     cmd.DW62.IPCM_QP3     = IPCM_Threshold_Table[3].QP;
2997     cmd.DW63.IPCM_QP4     = IPCM_Threshold_Table[4].QP;
2998 
2999     cmd.DW63.IPCM_Thresh0 = IPCM_Threshold_Table[0].Threshold;
3000     cmd.DW64.IPCM_Thresh1 = IPCM_Threshold_Table[1].Threshold;
3001     cmd.DW64.IPCM_Thresh2 = IPCM_Threshold_Table[2].Threshold;
3002     cmd.DW65.IPCM_Thresh3 = IPCM_Threshold_Table[3].Threshold;
3003     cmd.DW65.IPCM_Thresh4 = IPCM_Threshold_Table[4].Threshold;
3004 
3005     cmd.DW66.MBDataSurfIndex                = CODECHAL_ENCODE_AVC_MBENC_MFC_AVC_PAK_OBJ_G9;
3006     cmd.DW67.MVDataSurfIndex                = CODECHAL_ENCODE_AVC_MBENC_IND_MV_DATA_G9;
3007     cmd.DW68.IDistSurfIndex                 = CODECHAL_ENCODE_AVC_MBENC_BRC_DISTORTION_G9;
3008     cmd.DW69.SrcYSurfIndex                  = CODECHAL_ENCODE_AVC_MBENC_CURR_Y_G9;
3009     cmd.DW70.MBSpecificDataSurfIndex        = CODECHAL_ENCODE_AVC_MBENC_MB_SPECIFIC_DATA_G9;
3010     cmd.DW71.AuxVmeOutSurfIndex             = CODECHAL_ENCODE_AVC_MBENC_AUX_VME_OUT_G9;
3011     cmd.DW72.CurrRefPicSelSurfIndex         = CODECHAL_ENCODE_AVC_MBENC_REFPICSELECT_L0_G9;
3012     cmd.DW73.HMEMVPredFwdBwdSurfIndex       = CODECHAL_ENCODE_AVC_MBENC_MV_DATA_FROM_ME_G9;
3013     cmd.DW74.HMEDistSurfIndex               = CODECHAL_ENCODE_AVC_MBENC_4xME_DISTORTION_G9;
3014     cmd.DW75.SliceMapSurfIndex              = CODECHAL_ENCODE_AVC_MBENC_SLICEMAP_DATA_G9;
3015     cmd.DW76.FwdFrmMBDataSurfIndex          = CODECHAL_ENCODE_AVC_MBENC_FWD_MB_DATA_G9;
3016     cmd.DW77.FwdFrmMVSurfIndex              = CODECHAL_ENCODE_AVC_MBENC_FWD_MV_DATA_G9;
3017     cmd.DW78.MBQPBuffer                     = CODECHAL_ENCODE_AVC_MBENC_MBQP_G9;
3018     cmd.DW79.MBBRCLut                       = CODECHAL_ENCODE_AVC_MBENC_MBBRC_CONST_DATA_G9;
3019     cmd.DW80.VMEInterPredictionSurfIndex    = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_G9;
3020     cmd.DW81.VMEInterPredictionMRSurfIndex  = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_G9;
3021     cmd.DW82.MBStatsSurfIndex               = CODECHAL_ENCODE_AVC_MBENC_MB_STATS_G9;
3022     cmd.DW83.MADSurfIndex                   = CODECHAL_ENCODE_AVC_MBENC_MAD_DATA_G9;
3023     cmd.DW84.BRCCurbeSurfIndex              = CODECHAL_ENCODE_AVC_MBENC_BRC_CURBE_DATA_G9_KBL;
3024     cmd.DW85.ForceNonSkipMBmapSurface       = CODECHAL_ENCODE_AVC_MBENC_FORCE_NONSKIP_MB_MAP_G9_KBL;
3025     cmd.DW86.ReservedIndex                  = CODECHAL_ENCODE_AVC_MBENC_ADV_WA_G9_KBL;
3026     cmd.DW87.StaticDetectionCostTableIndex  = CODECHAL_ENCODE_AVC_MBENC_SFD_COST_TABLE_G9_KBL;
3027     auto stateHeapInterface =  m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
3028     CODECHAL_ENCODE_CHK_NULL_RETURN(stateHeapInterface);
3029 
3030     CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
3031         &cmd,
3032         params->pKernelState->dwCurbeOffset,
3033         sizeof(cmd)));
3034 
3035     CODECHAL_DEBUG_TOOL(
3036         CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateEncParam(
3037             meMethod,
3038             &cmd));
3039     )
3040 
3041     return eStatus;
3042 }
3043 
GetTrellisQuantization(PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS params,PCODECHAL_ENCODE_AVC_TQ_PARAMS trellisQuantParams)3044 MOS_STATUS CodechalEncodeAvcEncG9Kbl::GetTrellisQuantization(
3045         PCODECHAL_ENCODE_AVC_TQ_INPUT_PARAMS    params,
3046         PCODECHAL_ENCODE_AVC_TQ_PARAMS          trellisQuantParams)
3047 {
3048     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3049 
3050     CODECHAL_ENCODE_FUNCTION_ENTER;
3051 
3052     CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3053     CODECHAL_ENCODE_CHK_NULL_RETURN(trellisQuantParams);
3054 
3055     trellisQuantParams->dwTqEnabled    = TrellisQuantizationEnable[params->ucTargetUsage];
3056     trellisQuantParams->dwTqRounding   =
3057     trellisQuantParams->dwTqEnabled ? CODECHAL_ENCODE_AVC_TrellisQuantizationRounding_G9_KBL[params->ucTargetUsage]  : 0;
3058 
3059     // If AdaptiveTrellisQuantization is enabled then disable trellis quantization for
3060     // B-frames with QP > 26 only in CQP mode
3061     if(trellisQuantParams->dwTqEnabled
3062         && EnableAdaptiveTrellisQuantization[params->ucTargetUsage]
3063         && params->wPictureCodingType == B_TYPE
3064         && !params->bBrcEnabled && params->ucQP > 26)
3065     {
3066         trellisQuantParams->dwTqEnabled  = 0;
3067         trellisQuantParams->dwTqRounding = 0;
3068     }
3069     return eStatus;
3070 }
3071 
InitBrcConstantBuffer(PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS params)3072 MOS_STATUS CodechalEncodeAvcEncG9Kbl::InitBrcConstantBuffer(
3073         PCODECHAL_ENCODE_AVC_INIT_BRC_CONSTANT_BUFFER_PARAMS        params)
3074 {
3075     MOS_STATUS          eStatus = MOS_STATUS_SUCCESS;
3076 
3077     CODECHAL_ENCODE_FUNCTION_ENTER;
3078 
3079     CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3080     CODECHAL_ENCODE_CHK_NULL_RETURN(params->pOsInterface);
3081     CODECHAL_ENCODE_CHK_NULL_RETURN(params->pPicParams);
3082 
3083     uint8_t tableIdx = params->wPictureCodingType - 1;
3084     bool blockBasedSkipEn = params->dwMbEncBlockBasedSkipEn ? true : false;
3085     bool transform_8x8_mode_flag = params->pPicParams->transform_8x8_mode_flag ? true : false;
3086 
3087     if (tableIdx >= 3)
3088     {
3089         CODECHAL_ENCODE_ASSERTMESSAGE("Invalid input parameter.");
3090         eStatus = MOS_STATUS_INVALID_PARAMETER;
3091         return eStatus;
3092     }
3093     MOS_LOCK_PARAMS     lockFlags;
3094     MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
3095     lockFlags.WriteOnly = 1;
3096     auto data = (uint8_t*)params->pOsInterface->pfnLockResource(
3097         params->pOsInterface,
3098         &params->sBrcConstantDataBuffer.OsResource,
3099         &lockFlags);
3100     CODECHAL_ENCODE_CHK_NULL_RETURN(data);
3101 
3102     MOS_ZeroMemory(data, params->sBrcConstantDataBuffer.dwWidth * params->sBrcConstantDataBuffer.dwHeight);
3103 
3104     // Fill surface with QP Adjustment table, Distortion threshold table, MaxFrame threshold table, Distortion QP Adjustment Table
3105     eStatus = MOS_SecureMemcpy(
3106         data,
3107         sizeof(m_qpDistMaxFrameAdjustmentCm),
3108         (void*)m_qpDistMaxFrameAdjustmentCm,
3109         sizeof(m_qpDistMaxFrameAdjustmentCm));
3110     if (eStatus != MOS_STATUS_SUCCESS)
3111     {
3112         CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3113         return eStatus;
3114     }
3115 
3116     data += sizeof(m_qpDistMaxFrameAdjustmentCm);
3117 
3118     // Fill surface with Skip Threshold Table
3119     switch (params->wPictureCodingType)
3120     {
3121     case P_TYPE:
3122         eStatus = MOS_SecureMemcpy(
3123             data,
3124             m_brcConstantSurfaceEarlySkipTableSize,
3125             (void*)&SkipVal_P_Common[blockBasedSkipEn][transform_8x8_mode_flag][0],
3126             m_brcConstantSurfaceEarlySkipTableSize);
3127         if (eStatus != MOS_STATUS_SUCCESS)
3128         {
3129             CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3130             return eStatus;
3131         }
3132         break;
3133     case B_TYPE:
3134         eStatus = MOS_SecureMemcpy(
3135             data,
3136             m_brcConstantSurfaceEarlySkipTableSize,
3137             (void*)&SkipVal_B_Common[blockBasedSkipEn][transform_8x8_mode_flag][0],
3138             m_brcConstantSurfaceEarlySkipTableSize);
3139         if (eStatus != MOS_STATUS_SUCCESS)
3140         {
3141             CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3142             return eStatus;
3143         }
3144         break;
3145     default:
3146         // do nothing for I TYPE
3147         break;
3148     }
3149 
3150     if ((params->wPictureCodingType != I_TYPE) && (params->pAvcQCParams != nullptr) && (params->pAvcQCParams->NonFTQSkipThresholdLUTInput))
3151     {
3152         for (uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3153         {
3154             *(data + 1 + (qp * 2)) = (uint8_t)CalcSkipVal((params->dwMbEncBlockBasedSkipEn ? true : false), (params->pPicParams->transform_8x8_mode_flag ? true : false), params->pAvcQCParams->NonFTQSkipThresholdLUT[qp]);
3155         }
3156     }
3157 
3158     data += m_brcConstantSurfaceEarlySkipTableSize;
3159 
3160     // Fill surface with QP list
3161 
3162     // Initialize to -1 (0xff)
3163     MOS_FillMemory(data, CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_G9, 0xff);
3164     MOS_FillMemory(data
3165         + CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_G9
3166         + CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_RESERVED_G9,
3167         CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_1_G9, 0xff);
3168 
3169     switch (params->wPictureCodingType)
3170     {
3171     case B_TYPE:
3172         data += (CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_G9 + CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_RESERVED_G9);
3173 
3174         for (uint8_t refIdx = 0; refIdx <= params->pAvcSlcParams->num_ref_idx_l1_active_minus1; refIdx++)
3175         {
3176             CODEC_PICTURE refPic = params->pAvcSlcParams->RefPicList[LIST_1][refIdx];
3177             if (!CodecHal_PictureIsInvalid(refPic) && params->pAvcPicIdx[refPic.FrameIdx].bValid)
3178             {
3179                 *(data + refIdx) = params->pAvcPicIdx[refPic.FrameIdx].ucPicIdx;
3180             }
3181         }
3182         data -= (CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_G9 + CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_RESERVED_G9);
3183         // break statement omitted intentionally
3184     case P_TYPE:
3185         for (uint8_t refIdx = 0; refIdx <= params->pAvcSlcParams->num_ref_idx_l0_active_minus1; refIdx++)
3186         {
3187             CODEC_PICTURE refPic = params->pAvcSlcParams->RefPicList[LIST_0][refIdx];
3188             if (!CodecHal_PictureIsInvalid(refPic) && params->pAvcPicIdx[refPic.FrameIdx].bValid)
3189             {
3190                 *(data + refIdx) = params->pAvcPicIdx[refPic.FrameIdx].ucPicIdx;
3191             }
3192         }
3193         break;
3194     default:
3195         // do nothing for I type
3196         break;
3197     }
3198 
3199     data += (CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_G9 + CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_0_RESERVED_G9
3200         + CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_1_G9 + CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_QP_LIST_1_RESERVED_G9);
3201 
3202     // Fill surface with Mode cost and MV cost
3203     eStatus = MOS_SecureMemcpy(
3204         data,
3205         m_brcConstantSurfacModeMvCostSize,
3206         (void*)ModeMvCost_Cm[tableIdx],
3207         m_brcConstantSurfacModeMvCostSize);
3208     if (eStatus != MOS_STATUS_SUCCESS)
3209     {
3210         CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3211         return eStatus;
3212     }
3213 
3214     // If old mode cost is used the update the table
3215     if (params->wPictureCodingType == I_TYPE && params->bOldModeCostEnable)
3216     {
3217         auto pdwDataTemp = (uint32_t *)data;
3218         for (uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3219         {
3220             // Writing to DW0 in each sub-array of 16 DWs
3221             *pdwDataTemp = (uint32_t)OldIntraModeCost_Cm_Common[qp];
3222             pdwDataTemp += 16;
3223         }
3224     }
3225 
3226     if (params->pAvcQCParams)
3227     {
3228         for (uint8_t qp = 0; qp < CODEC_AVC_NUM_QP; qp++)
3229         {
3230             if (params->pAvcQCParams->FTQSkipThresholdLUTInput)
3231             {
3232                 *(data + (qp * 32) + 24) =
3233                     *(data + (qp * 32) + 25) =
3234                     *(data + (qp * 32) + 27) =
3235                     *(data + (qp * 32) + 28) =
3236                     *(data + (qp * 32) + 29) =
3237                     *(data + (qp * 32) + 30) =
3238                     *(data + (qp * 32) + 31) = params->pAvcQCParams->FTQSkipThresholdLUT[qp];
3239             }
3240         }
3241     }
3242 
3243     data += m_brcConstantSurfacModeMvCostSize;
3244 
3245     // Fill surface with Refcost
3246     eStatus = MOS_SecureMemcpy(
3247         data,
3248         m_brcConstantSurfaceRefCostSize,
3249         (void*)&RefCost_MultiRefQp[tableIdx][0],
3250         m_brcConstantSurfaceRefCostSize);
3251     if (eStatus != MOS_STATUS_SUCCESS)
3252     {
3253         CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3254         return eStatus;
3255     }
3256     data += m_brcConstantSurfaceRefCostSize;
3257 
3258     //Fill surface with Intra cost scaling Factor
3259     if (params->bAdaptiveIntraScalingEnable)
3260     {
3261         eStatus = MOS_SecureMemcpy(
3262             data,
3263             CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_INTRACOST_SCALING_FACTOR_G9,
3264             (void*)&AdaptiveIntraScalingFactor_Cm_Common[0],
3265             CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_INTRACOST_SCALING_FACTOR_G9);
3266         if (eStatus != MOS_STATUS_SUCCESS)
3267         {
3268             CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3269             return eStatus;
3270         }
3271     }
3272     else
3273     {
3274         eStatus = MOS_SecureMemcpy(
3275             data,
3276             CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_INTRACOST_SCALING_FACTOR_G9,
3277             (void*)&IntraScalingFactor_Cm_Common[0],
3278             CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_INTRACOST_SCALING_FACTOR_G9);
3279         if (eStatus != MOS_STATUS_SUCCESS)
3280         {
3281             CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3282             return eStatus;
3283         }
3284     }
3285 
3286     data += CODECHAL_ENCODE_AVC_BRC_CONSTANTSURFACE_INTRACOST_SCALING_FACTOR_G9;
3287 
3288     eStatus = MOS_SecureMemcpy(
3289         data,
3290         BRC_CONSTANTSURFACE_LAMBDA_SIZE_G9_KBL,
3291         (void*)&Lambda_data[0],
3292         BRC_CONSTANTSURFACE_LAMBDA_SIZE_G9_KBL);
3293     if (eStatus != MOS_STATUS_SUCCESS)
3294     {
3295         CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3296         return eStatus;
3297     }
3298 
3299     data += BRC_CONSTANTSURFACE_LAMBDA_SIZE_G9_KBL;
3300 
3301     eStatus = MOS_SecureMemcpy(
3302         data,
3303         BRC_CONSTANTSURFACE_FTQ25_SIZE_G9_KBL,
3304         (void*)&FTQ25[0],
3305         BRC_CONSTANTSURFACE_FTQ25_SIZE_G9_KBL);
3306     if (eStatus != MOS_STATUS_SUCCESS)
3307     {
3308         CODECHAL_ENCODE_ASSERTMESSAGE("Failed to copy memory.");
3309         return eStatus;
3310     }
3311 
3312     params->pOsInterface->pfnUnlockResource(
3313         params->pOsInterface,
3314         &params->sBrcConstantDataBuffer.OsResource);
3315 
3316     return eStatus;
3317 }
3318 
CodechalEncodeAvcEncG9Kbl(CodechalHwInterface * hwInterface,CodechalDebugInterface * debugInterface,PCODECHAL_STANDARD_INFO standardInfo)3319 CodechalEncodeAvcEncG9Kbl::CodechalEncodeAvcEncG9Kbl(
3320         CodechalHwInterface *   hwInterface,
3321         CodechalDebugInterface *debugInterface,
3322         PCODECHAL_STANDARD_INFO standardInfo) : CodechalEncodeAvcEncG9(hwInterface, debugInterface, standardInfo)
3323 {
3324     MOS_STATUS                  eStatus = MOS_STATUS_SUCCESS;
3325 
3326     CODECHAL_ENCODE_FUNCTION_ENTER;
3327     m_cmKernelEnable           = true;
3328     m_mbStatsSupported         = true;
3329     bKernelTrellis             = true;
3330     bExtendedMvCostRange       = false;
3331     bBrcSplitEnable            = true;
3332     bDecoupleMbEncCurbeFromBRC = true;
3333     bHighTextureModeCostEnable = true;
3334 
3335     this->pfnGetKernelHeaderAndSize         = this->GetKernelHeaderAndSize;
3336 
3337     m_kernelBase = (uint8_t *)IGCODECKRN_G9_KBL;
3338     AddIshSize(m_kuid, m_kernelBase);
3339 }
3340 
InitializeState()3341 MOS_STATUS CodechalEncodeAvcEncG9Kbl::InitializeState()
3342 {
3343     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3344     CODECHAL_ENCODE_CHK_STATUS_RETURN(CodechalEncodeAvcEncG9::InitializeState());
3345 
3346     m_brcHistoryBufferSize      = CODECHAL_ENCODE_AVC_BRC_HISTORY_BUFFER_SIZE_G9_KBL;
3347     m_mbencBrcBufferSize        = MBENC_BRC_BUFFER_SIZE_G9_KBL;
3348     dwBrcConstantSurfaceWidth  = BRC_CONSTANTSURFACE_WIDTH_G9_KBL;
3349     dwBrcConstantSurfaceHeight = BRC_CONSTANTSURFACE_HEIGHT_G9_KBL;
3350     m_forceBrcMbStatsEnabled    = true;
3351 
3352     return eStatus;
3353 }
3354 
SetCurbeAvcBrcInitReset(PCODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_PARAMS params)3355 MOS_STATUS CodechalEncodeAvcEncG9Kbl::SetCurbeAvcBrcInitReset(PCODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_PARAMS params)
3356 {
3357     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3358 
3359     CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3360 
3361     auto picParams = m_avcPicParam;
3362     auto seqParams = m_avcSeqParam;
3363     auto vuiParams = m_avcVuiParams;
3364     uint32_t profileLevelMaxFrame;
3365     CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalAvcEncode_GetProfileLevelMaxFrameSize(
3366         seqParams,
3367         this,
3368         (uint32_t*)&profileLevelMaxFrame));
3369 
3370     CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95 cmd = g_cInit_CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95;
3371     cmd.DW0.ProfileLevelMaxFrame = profileLevelMaxFrame;
3372     cmd.DW1.InitBufFullInBits = seqParams->InitVBVBufferFullnessInBit;
3373     cmd.DW2.BufSizeInBits = seqParams->VBVBufferSizeInBit;
3374     cmd.DW3.AverageBitRate = seqParams->TargetBitRate;
3375     cmd.DW4.MaxBitRate = seqParams->MaxBitRate;
3376     cmd.DW8.GopP =
3377         (seqParams->GopRefDist) ? ((seqParams->GopPicSize - 1) / seqParams->GopRefDist) : 0;
3378     cmd.DW9.GopB = seqParams->GopPicSize - 1 - cmd.DW8.GopP;
3379     cmd.DW9.FrameWidthInBytes = m_frameWidth;
3380     cmd.DW10.FrameHeightInBytes = m_frameHeight;
3381     cmd.DW12.NoSlices = m_numSlices;
3382     cmd.DW32.SurfaceIndexhistorybuffer = CODECHAL_ENCODE_AVC_BRC_INIT_RESET_HISTORY;
3383     cmd.DW33.SurfaceIndexdistortionbuffer = CODECHAL_ENCODE_AVC_BRC_INIT_RESET_DISTORTION;
3384 
3385     // if VUI present, VUI data has high priority
3386     if (seqParams->vui_parameters_present_flag && seqParams->RateControlMethod != RATECONTROL_AVBR)
3387     {
3388         cmd.DW4.MaxBitRate =
3389             ((vuiParams->bit_rate_value_minus1[0] + 1) << (6 + vuiParams->bit_rate_scale));
3390 
3391         if (seqParams->RateControlMethod == RATECONTROL_CBR)
3392         {
3393             cmd.DW3.AverageBitRate = cmd.DW4.MaxBitRate;
3394         }
3395     }
3396 
3397     cmd.DW6.FrameRateM = seqParams->FramesPer100Sec;
3398     cmd.DW7.FrameRateD = 100;
3399     cmd.DW8.BRCFlag = (CodecHal_PictureIsFrame(m_currOriginalPic)) ? 0 : CODECHAL_ENCODE_BRCINIT_FIELD_PIC;
3400     // MBBRC should be skipped when BRC ROI is on
3401     cmd.DW8.BRCFlag |= (bMbBrcEnabled && !bBrcRoiEnabled) ? 0 : CODECHAL_ENCODE_BRCINIT_DISABLE_MBBRC;
3402 
3403     if (seqParams->RateControlMethod == RATECONTROL_CBR)
3404     {
3405         cmd.DW4.MaxBitRate = cmd.DW3.AverageBitRate;
3406         cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISCBR;
3407     }
3408     else if (seqParams->RateControlMethod == RATECONTROL_VBR)
3409     {
3410         if (cmd.DW4.MaxBitRate < cmd.DW3.AverageBitRate)
3411         {
3412             cmd.DW3.AverageBitRate = cmd.DW4.MaxBitRate; // Use max bit rate for HRD compliance
3413         }
3414         cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISVBR;
3415     }
3416     else if (seqParams->RateControlMethod == RATECONTROL_AVBR)
3417     {
3418         cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISAVBR;
3419         // For AVBR, max bitrate = target bitrate,
3420         cmd.DW4.MaxBitRate = cmd.DW3.AverageBitRate;
3421     }
3422     else if (seqParams->RateControlMethod == RATECONTROL_ICQ)
3423     {
3424         cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISICQ;
3425         cmd.DW23.ACQP = seqParams->ICQQualityFactor;
3426     }
3427     else if (seqParams->RateControlMethod == RATECONTROL_VCM)
3428     {
3429         cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISVCM;
3430     }
3431     else if (seqParams->RateControlMethod == RATECONTROL_QVBR)
3432     {
3433         if (cmd.DW4.MaxBitRate < cmd.DW3.AverageBitRate)
3434         {
3435             cmd.DW3.AverageBitRate = cmd.DW4.MaxBitRate; // Use max bit rate for HRD compliance
3436         }
3437         cmd.DW8.BRCFlag = cmd.DW8.BRCFlag | CODECHAL_ENCODE_BRCINIT_ISQVBR;
3438         // use ICQQualityFactor to determine the larger Qp for each MB
3439         cmd.DW23.ACQP = seqParams->ICQQualityFactor;
3440     }
3441 
3442     if (seqParams->RateControlMethod == RATECONTROL_AVBR)
3443     {
3444         usAVBRAccuracy    = (uint16_t)seqParams->AVBRAccuracy;
3445         usAVBRConvergence = (uint16_t)seqParams->AVBRConvergence;
3446     }
3447 
3448     cmd.DW10.AVBRAccuracy = usAVBRAccuracy;
3449     cmd.DW11.AVBRConvergence = usAVBRConvergence;
3450 
3451     // Set dynamic thresholds
3452     double inputBitsPerFrame =
3453         ((double)(cmd.DW4.MaxBitRate) * (double)(cmd.DW7.FrameRateD) /
3454         (double)(cmd.DW6.FrameRateM));
3455     if (CodecHal_PictureIsField(m_currOriginalPic))
3456     {
3457         inputBitsPerFrame *= 0.5;
3458     }
3459 
3460     if (cmd.DW2.BufSizeInBits == 0)
3461     {
3462         cmd.DW2.BufSizeInBits = (uint32_t)inputBitsPerFrame * 4;
3463     }
3464 
3465     if (cmd.DW1.InitBufFullInBits == 0)
3466     {
3467         cmd.DW1.InitBufFullInBits = 7 * cmd.DW2.BufSizeInBits / 8;
3468     }
3469     if (cmd.DW1.InitBufFullInBits < (uint32_t)(inputBitsPerFrame * 2))
3470     {
3471         cmd.DW1.InitBufFullInBits = (uint32_t)(inputBitsPerFrame * 2);
3472     }
3473     if (cmd.DW1.InitBufFullInBits > cmd.DW2.BufSizeInBits)
3474     {
3475         cmd.DW1.InitBufFullInBits = cmd.DW2.BufSizeInBits;
3476     }
3477 
3478     if (seqParams->RateControlMethod == RATECONTROL_AVBR)
3479     {
3480         // For AVBR, Buffer size =  2*Bitrate, InitVBV = 0.75 * BufferSize
3481         cmd.DW2.BufSizeInBits = 2 * seqParams->TargetBitRate;
3482         cmd.DW1.InitBufFullInBits = (uint32_t)(0.75 * cmd.DW2.BufSizeInBits);
3483     }
3484 
3485     double dBpsRatio = inputBitsPerFrame / ((double)(cmd.DW2.BufSizeInBits) / 30);
3486     dBpsRatio = (dBpsRatio < 0.1) ? 0.1 : (dBpsRatio > 3.5) ? 3.5 : dBpsRatio;
3487 
3488     cmd.DW16.DeviationThreshold0ForPandB = (uint32_t)(-50 * pow(0.90, dBpsRatio));
3489     cmd.DW16.DeviationThreshold1ForPandB = (uint32_t)(-50 * pow(0.66, dBpsRatio));
3490     cmd.DW16.DeviationThreshold2ForPandB = (uint32_t)(-50 * pow(0.46, dBpsRatio));
3491     cmd.DW16.DeviationThreshold3ForPandB = (uint32_t)(-50 * pow(0.3, dBpsRatio));
3492     cmd.DW17.DeviationThreshold4ForPandB = (uint32_t)(50 * pow(0.3, dBpsRatio));
3493     cmd.DW17.DeviationThreshold5ForPandB = (uint32_t)(50 * pow(0.46, dBpsRatio));
3494     cmd.DW17.DeviationThreshold6ForPandB = (uint32_t)(50 * pow(0.7, dBpsRatio));
3495     cmd.DW17.DeviationThreshold7ForPandB = (uint32_t)(50 * pow(0.9, dBpsRatio));
3496     cmd.DW18.DeviationThreshold0ForVBR = (uint32_t)(-50 * pow(0.9, dBpsRatio));
3497     cmd.DW18.DeviationThreshold1ForVBR = (uint32_t)(-50 * pow(0.7, dBpsRatio));
3498     cmd.DW18.DeviationThreshold2ForVBR = (uint32_t)(-50 * pow(0.5, dBpsRatio));
3499     cmd.DW18.DeviationThreshold3ForVBR = (uint32_t)(-50 * pow(0.3, dBpsRatio));
3500     cmd.DW19.DeviationThreshold4ForVBR = (uint32_t)(100 * pow(0.4, dBpsRatio));
3501     cmd.DW19.DeviationThreshold5ForVBR = (uint32_t)(100 * pow(0.5, dBpsRatio));
3502     cmd.DW19.DeviationThreshold6ForVBR = (uint32_t)(100 * pow(0.75, dBpsRatio));
3503     cmd.DW19.DeviationThreshold7ForVBR = (uint32_t)(100 * pow(0.9, dBpsRatio));
3504     cmd.DW20.DeviationThreshold0ForI = (uint32_t)(-50 * pow(0.8, dBpsRatio));
3505     cmd.DW20.DeviationThreshold1ForI = (uint32_t)(-50 * pow(0.6, dBpsRatio));
3506     cmd.DW20.DeviationThreshold2ForI = (uint32_t)(-50 * pow(0.34, dBpsRatio));
3507     cmd.DW20.DeviationThreshold3ForI = (uint32_t)(-50 * pow(0.2, dBpsRatio));
3508     cmd.DW21.DeviationThreshold4ForI = (uint32_t)(50 * pow(0.2, dBpsRatio));
3509     cmd.DW21.DeviationThreshold5ForI = (uint32_t)(50 * pow(0.4, dBpsRatio));
3510     cmd.DW21.DeviationThreshold6ForI = (uint32_t)(50 * pow(0.66, dBpsRatio));
3511     cmd.DW21.DeviationThreshold7ForI = (uint32_t)(50 * pow(0.9, dBpsRatio));
3512 
3513     cmd.DW22.SlidingWindowSize = dwSlidingWindowSize;
3514 
3515     if (bBrcInit)
3516     {
3517         *params->pdBrcInitCurrentTargetBufFullInBits = cmd.DW1.InitBufFullInBits;
3518     }
3519 
3520     *params->pdwBrcInitResetBufSizeInBits = cmd.DW2.BufSizeInBits;
3521     *params->pdBrcInitResetInputBitsPerFrame = inputBitsPerFrame;
3522 
3523     CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
3524         &cmd,
3525         params->pKernelState->dwCurbeOffset,
3526         sizeof(cmd)));
3527 
3528     CODECHAL_DEBUG_TOOL(
3529         CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcInitParam(
3530             &cmd));
3531     )
3532 
3533     return eStatus;
3534 }
3535 
SetCurbeAvcFrameBrcUpdate(PCODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_PARAMS params)3536 MOS_STATUS CodechalEncodeAvcEncG9Kbl::SetCurbeAvcFrameBrcUpdate(PCODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_PARAMS params)
3537 {
3538     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3539 
3540     CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3541     CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
3542 
3543     auto seqParams = m_avcSeqParam;
3544     auto picParams = m_avcPicParam;
3545     auto slcParams = m_avcSliceParams;
3546 
3547     MHW_VDBOX_AVC_SLICE_STATE sliceState;
3548     MOS_ZeroMemory(&sliceState, sizeof(sliceState));
3549     sliceState.pEncodeAvcSeqParams = seqParams;
3550     sliceState.pEncodeAvcPicParams = picParams;
3551     sliceState.pEncodeAvcSliceParams = slcParams;
3552 
3553     CODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_G95   cmd = g_cInit_CODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_G95;
3554 
3555     cmd.DW5.TargetSizeFlag = 0;
3556     if (*params->pdBrcInitCurrentTargetBufFullInBits > (double)dwBrcInitResetBufSizeInBits)
3557     {
3558         *params->pdBrcInitCurrentTargetBufFullInBits -= (double)dwBrcInitResetBufSizeInBits;
3559         cmd.DW5.TargetSizeFlag = 1;
3560     }
3561 
3562     // skipped frame handling
3563     if (params->dwNumSkipFrames)
3564     {
3565         // pass num/size of skipped frames to update BRC
3566         cmd.DW6.NumSkipFrames = params->dwNumSkipFrames;
3567         cmd.DW7.SizeSkipFrames = params->dwSizeSkipFrames;
3568 
3569         // account for skipped frame in calculating CurrentTargetBufFullInBits
3570         *params->pdBrcInitCurrentTargetBufFullInBits += dBrcInitResetInputBitsPerFrame * params->dwNumSkipFrames;
3571     }
3572 
3573     cmd.DW0.TargetSize = (uint32_t)(*params->pdBrcInitCurrentTargetBufFullInBits);
3574     cmd.DW1.FrameNumber = m_storeData - 1;
3575     cmd.DW2.SizeofPicHeaders = m_headerBytesInserted << 3;   // kernel uses how many bits instead of bytes
3576     cmd.DW5.CurrFrameType =
3577         ((m_pictureCodingType - 2) < 0) ? 2 : (m_pictureCodingType - 2);
3578     cmd.DW5.BRCFlag =
3579         (CodecHal_PictureIsTopField(m_currOriginalPic)) ? brcUpdateIsField :
3580         ((CodecHal_PictureIsBottomField(m_currOriginalPic)) ? (brcUpdateIsField | brcUpdateIsBottomField) : 0);
3581     cmd.DW5.BRCFlag |= (m_refList[m_currReconstructedPic.FrameIdx]->bUsedAsRef) ?
3582         brcUpdateIsReference : 0;
3583 
3584     if (bMultiRefQpEnabled)
3585     {
3586         cmd.DW5.BRCFlag |= brcUpdateIsActualQp;
3587         cmd.DW14.QPIndexOfCurPic = m_currOriginalPic.FrameIdx;
3588     }
3589 
3590     cmd.DW5.BRCFlag |= seqParams->bAutoMaxPBFrameSizeForSceneChange ?
3591         brcUpdateAutoPbFrameSize : 0;
3592 
3593     cmd.DW5.MaxNumPAKs = m_hwInterface->GetMfxInterface()->GetBrcNumPakPasses();
3594 
3595     cmd.DW6.MinimumQP = params->ucMinQP;
3596     cmd.DW6.MaximumQP = params->ucMaxQP;
3597     cmd.DW6.EnableForceToSkip = (bForceToSkipEnable && !m_avcPicParam->bDisableFrameSkip);
3598     cmd.DW6.EnableSlidingWindow = (seqParams->FrameSizeTolerance == EFRAMESIZETOL_LOW);
3599     cmd.DW6.EnableExtremLowDelay = (seqParams->FrameSizeTolerance == EFRAMESIZETOL_EXTREMELY_LOW);
3600     cmd.DW6.DisableVarCompute = bBRCVarCompuBypass;
3601 
3602     *params->pdBrcInitCurrentTargetBufFullInBits += dBrcInitResetInputBitsPerFrame;
3603 
3604     if (seqParams->RateControlMethod == RATECONTROL_AVBR)
3605     {
3606         usAVBRConvergence = (uint16_t)seqParams->AVBRConvergence;
3607         usAVBRAccuracy = (uint16_t)seqParams->AVBRAccuracy;
3608 
3609         cmd.DW3.startGAdjFrame0 = (uint32_t)((10 * usAVBRConvergence) / (double)150);
3610         cmd.DW3.startGAdjFrame1 = (uint32_t)((50 * usAVBRConvergence) / (double)150);
3611         cmd.DW4.startGAdjFrame2 = (uint32_t)((100 * usAVBRConvergence) / (double)150);
3612         cmd.DW4.startGAdjFrame3 = (uint32_t)((150 * usAVBRConvergence) / (double)150);
3613         cmd.DW11.gRateRatioThreshold0 =
3614             (uint32_t)((100 - (usAVBRAccuracy / (double)30)*(100 - 40)));
3615         cmd.DW11.gRateRatioThreshold1 =
3616             (uint32_t)((100 - (usAVBRAccuracy / (double)30)*(100 - 75)));
3617         cmd.DW12.gRateRatioThreshold2 = (uint32_t)((100 - (usAVBRAccuracy / (double)30)*(100 - 97)));
3618         cmd.DW12.gRateRatioThreshold3 = (uint32_t)((100 + (usAVBRAccuracy / (double)30)*(103 - 100)));
3619         cmd.DW12.gRateRatioThreshold4 = (uint32_t)((100 + (usAVBRAccuracy / (double)30)*(125 - 100)));
3620         cmd.DW12.gRateRatioThreshold5 = (uint32_t)((100 + (usAVBRAccuracy / (double)30)*(160 - 100)));
3621     }
3622 
3623     cmd.DW15.EnableROI = params->ucEnableROI;
3624 
3625     CODECHAL_ENCODE_CHK_STATUS_RETURN(GetInterRounding(&sliceState));
3626 
3627     cmd.DW15.RoundingIntra = 5;
3628     cmd.DW15.RoundingInter = sliceState.dwRoundingValue;
3629 
3630     uint32_t profileLevelMaxFrame;
3631     CODECHAL_ENCODE_CHK_STATUS_RETURN(CodecHalAvcEncode_GetProfileLevelMaxFrameSize(
3632         seqParams,
3633         this,
3634         &profileLevelMaxFrame));
3635 
3636     cmd.DW19.UserMaxFrame = profileLevelMaxFrame;
3637 
3638     cmd.DW24.SurfaceIndexBRChistorybuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_HISTORY_G9_KBL;
3639     cmd.DW25.SurfaceIndexPreciousPAKstatisticsoutputbuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_PAK_STATISTICS_OUTPUT_G9_KBL;
3640     cmd.DW26.SurfaceIndexAVCIMGstateinputbuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_READ_G9_KBL;
3641     cmd.DW27.SurfaceIndexAVCIMGstateoutputbuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_WRITE_G9_KBL;
3642     cmd.DW28.SurfaceIndexAVC_Encbuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_WRITE_G9_KBL;
3643     cmd.DW29.SurfaceIndexAVCDISTORTIONbuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_DISTORTION_G9_KBL;
3644     cmd.DW30.SurfaceIndexBRCconstdatabuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_CONSTANT_DATA_G9_KBL;
3645     cmd.DW31.SurfaceIndexMBStatsBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MB_STAT_G9_KBL;
3646     cmd.DW32.SurfaceIndexMotionvectorbuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MV_G9_KBL;
3647     auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
3648     CODECHAL_ENCODE_CHK_NULL_RETURN(stateHeapInterface);
3649 
3650     CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
3651         &cmd,
3652         params->pKernelState->dwCurbeOffset,
3653         sizeof(cmd)));
3654 
3655     CODECHAL_DEBUG_TOOL(
3656         CODECHAL_ENCODE_CHK_STATUS_RETURN(PopulateBrcUpdateParam(
3657             &cmd));
3658     )
3659 
3660     return eStatus;
3661 }
3662 
SetCurbeAvcMbBrcUpdate(PCODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_PARAMS params)3663 MOS_STATUS CodechalEncodeAvcEncG9Kbl::SetCurbeAvcMbBrcUpdate(PCODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_PARAMS params)
3664 {
3665     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3666 
3667     CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3668     CODECHAL_ENCODE_CHK_NULL_RETURN(params->pKernelState);
3669 
3670     auto curbe = g_cInit_CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_CURBE_G95;
3671 
3672     // BRC curbe requires: 2 for I-frame, 0 for P-frame, 1 for B-frame
3673     curbe.DW0.CurrFrameType = (m_pictureCodingType + 1) % 3;
3674     if (params->ucEnableROI)
3675     {
3676         if (bROIValueInDeltaQP)
3677         {
3678             curbe.DW0.EnableROI = 2; // 1-Enabled ROI priority, 2-Enable ROI QP Delta,  0- disabled
3679             curbe.DW0.ROIRatio = 0;
3680         }
3681         else
3682         {
3683             curbe.DW0.EnableROI = 1; // 1-Enabled ROI priority, 2-Enable ROI QP Delta,  0- disabled
3684 
3685             uint32_t roisize = 0;
3686             uint32_t roiratio = 0;
3687 
3688             for (uint32_t i = 0; i < m_avcPicParam->NumROI; ++i)
3689             {
3690                 CODECHAL_ENCODE_VERBOSEMESSAGE("ROI[%d] = {%d, %d, %d, %d} {%d}, size = %d", i,
3691                     m_avcPicParam->ROI[i].Left, m_avcPicParam->ROI[i].Top,
3692                     m_avcPicParam->ROI[i].Bottom, m_avcPicParam->ROI[i].Right,
3693                     m_avcPicParam->ROI[i].PriorityLevelOrDQp,
3694                     (CODECHAL_MACROBLOCK_HEIGHT * MOS_ABS(m_avcPicParam->ROI[i].Top - m_avcPicParam->ROI[i].Bottom)) *
3695                     (CODECHAL_MACROBLOCK_WIDTH * MOS_ABS(m_avcPicParam->ROI[i].Right - m_avcPicParam->ROI[i].Left)));
3696                 roisize += (CODECHAL_MACROBLOCK_HEIGHT * MOS_ABS(m_avcPicParam->ROI[i].Top - m_avcPicParam->ROI[i].Bottom)) *
3697                     (CODECHAL_MACROBLOCK_WIDTH * MOS_ABS(m_avcPicParam->ROI[i].Right - m_avcPicParam->ROI[i].Left));
3698             }
3699 
3700             if (roisize)
3701             {
3702                 uint32_t numMBs = m_picWidthInMb * m_picHeightInMb;
3703                 roiratio = 2 * (numMBs * 256 / roisize - 1);
3704                 roiratio = MOS_MIN(51, roiratio); // clip QP from 0-51
3705             }
3706             CODECHAL_ENCODE_VERBOSEMESSAGE("ROIRatio = %d", roiratio);
3707             curbe.DW0.ROIRatio = roiratio;
3708         }
3709     }
3710     else
3711     {
3712         curbe.DW0.ROIRatio = 0;
3713     }
3714     curbe.DW8.HistorybufferIndex = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_HISTORY_G9_KBL;
3715     curbe.DW9.MBQPbufferIndex = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_MB_QP_G9_KBL;
3716     curbe.DW10.ROIbufferIndex = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_ROI_G9_KBL;
3717     curbe.DW11.MBstatisticalbufferIndex = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_MB_STAT_G9_KBL;
3718     auto stateHeapInterface = m_hwInterface->GetRenderInterface()->m_stateHeapInterface;
3719     CODECHAL_ENCODE_CHK_NULL_RETURN(stateHeapInterface);
3720 
3721     CODECHAL_ENCODE_CHK_STATUS_RETURN(params->pKernelState->m_dshRegion.AddData(
3722         &curbe,
3723         params->pKernelState->dwCurbeOffset,
3724         sizeof(curbe)));
3725 
3726     return eStatus;
3727 }
3728 
InitKernelStateMbEnc()3729 MOS_STATUS CodechalEncodeAvcEncG9Kbl::InitKernelStateMbEnc()
3730 {
3731     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3732 
3733     CODECHAL_ENCODE_FUNCTION_ENTER;
3734 
3735     dwNumMbEncEncKrnStates =
3736         MBENC_TARGET_USAGE_CM * MBENC_NUM_TARGET_USAGES_CM_G9_KBL;
3737     dwNumMbEncEncKrnStates += MBENC_TARGET_USAGE_CM;
3738     pMbEncKernelStates =
3739         MOS_NewArray(MHW_KERNEL_STATE, dwNumMbEncEncKrnStates);
3740     CODECHAL_ENCODE_CHK_NULL_RETURN(pMbEncKernelStates);
3741 
3742     PMHW_KERNEL_STATE                           kernelStatePtr = pMbEncKernelStates;
3743     CODECHAL_KERNEL_HEADER                      currKrnHeader;
3744 
3745     uint8_t* kernelBinary;
3746     uint32_t kernelSize;
3747 
3748     MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, m_kuid, &kernelBinary, &kernelSize);
3749     CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
3750 
3751     for (uint32_t krnStateIdx = 0; krnStateIdx < dwNumMbEncEncKrnStates; krnStateIdx++)
3752     {
3753         bool kernelState = (krnStateIdx >= MBENC_TARGET_USAGE_CM * MBENC_NUM_TARGET_USAGES_CM_G9_KBL);
3754 
3755         CODECHAL_ENCODE_CHK_STATUS_RETURN(GetKernelHeaderAndSize(
3756             kernelBinary,
3757             (kernelState ? ENC_MBENC_ADV : ENC_MBENC),
3758             (kernelState ? krnStateIdx - MBENC_TARGET_USAGE_CM * MBENC_NUM_TARGET_USAGES_CM_G9_KBL : krnStateIdx),
3759             (void*)&currKrnHeader,
3760             &kernelSize));
3761 
3762         kernelStatePtr->KernelParams.iBTCount = CODECHAL_ENCODE_AVC_MBENC_NUM_SURFACES_G9_KBL;
3763         kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
3764         kernelStatePtr->KernelParams.iCurbeLength = sizeof(CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL);
3765         kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
3766         kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
3767         kernelStatePtr->KernelParams.iIdCount = 1;
3768 
3769         kernelStatePtr->dwCurbeOffset = m_stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
3770         kernelStatePtr->KernelParams.pBinary = kernelBinary + (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
3771         kernelStatePtr->KernelParams.iSize = kernelSize;
3772 
3773         CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
3774             m_stateHeapInterface,
3775             kernelStatePtr->KernelParams.iBTCount,
3776             &kernelStatePtr->dwSshSize,
3777             &kernelStatePtr->dwBindingTableSize));
3778 
3779         CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(m_stateHeapInterface, kernelStatePtr));
3780 
3781         kernelStatePtr++;
3782     }
3783 
3784     // Until a better way can be found, maintain old binding table structures
3785     auto bindingTable = &MbEncBindingTable;
3786 
3787     bindingTable->dwAvcMBEncMfcAvcPakObj = CODECHAL_ENCODE_AVC_MBENC_MFC_AVC_PAK_OBJ_G9;
3788     bindingTable->dwAvcMBEncIndMVData = CODECHAL_ENCODE_AVC_MBENC_IND_MV_DATA_G9;
3789     bindingTable->dwAvcMBEncBRCDist = CODECHAL_ENCODE_AVC_MBENC_BRC_DISTORTION_G9;
3790     bindingTable->dwAvcMBEncCurrY = CODECHAL_ENCODE_AVC_MBENC_CURR_Y_G9;
3791     bindingTable->dwAvcMBEncCurrUV = CODECHAL_ENCODE_AVC_MBENC_CURR_UV_G9;
3792     bindingTable->dwAvcMBEncMbSpecificData = CODECHAL_ENCODE_AVC_MBENC_MB_SPECIFIC_DATA_G9;
3793 
3794     bindingTable->dwAvcMBEncRefPicSelectL0 = CODECHAL_ENCODE_AVC_MBENC_REFPICSELECT_L0_G9;
3795     bindingTable->dwAvcMBEncMVDataFromME = CODECHAL_ENCODE_AVC_MBENC_MV_DATA_FROM_ME_G9;
3796     bindingTable->dwAvcMBEncMEDist = CODECHAL_ENCODE_AVC_MBENC_4xME_DISTORTION_G9;
3797     bindingTable->dwAvcMBEncSliceMapData = CODECHAL_ENCODE_AVC_MBENC_SLICEMAP_DATA_G9;
3798     bindingTable->dwAvcMBEncBwdRefMBData = CODECHAL_ENCODE_AVC_MBENC_FWD_MB_DATA_G9;
3799     bindingTable->dwAvcMBEncBwdRefMVData = CODECHAL_ENCODE_AVC_MBENC_FWD_MV_DATA_G9;
3800     bindingTable->dwAvcMBEncMbBrcConstData = CODECHAL_ENCODE_AVC_MBENC_MBBRC_CONST_DATA_G9;
3801     bindingTable->dwAvcMBEncMBStats = CODECHAL_ENCODE_AVC_MBENC_MB_STATS_G9;
3802     bindingTable->dwAvcMBEncMADData = CODECHAL_ENCODE_AVC_MBENC_MAD_DATA_G9;
3803     bindingTable->dwAvcMBEncMbNonSkipMap = CODECHAL_ENCODE_AVC_MBENC_FORCE_NONSKIP_MB_MAP_G9_KBL;
3804     bindingTable->dwAvcMBEncAdv = CODECHAL_ENCODE_AVC_MBENC_ADV_WA_G9_KBL;
3805     bindingTable->dwAvcMbEncBRCCurbeData = CODECHAL_ENCODE_AVC_MBENC_BRC_CURBE_DATA_G9_KBL;
3806     bindingTable->dwAvcMBEncStaticDetectionCostTable = CODECHAL_ENCODE_AVC_MBENC_SFD_COST_TABLE_G9_KBL;
3807 
3808     // Frame
3809     bindingTable->dwAvcMBEncMbQpFrame = CODECHAL_ENCODE_AVC_MBENC_MBQP_G9;
3810     bindingTable->dwAvcMBEncCurrPicFrame[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_G9;
3811     bindingTable->dwAvcMBEncFwdPicFrame[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX0_G9;
3812     bindingTable->dwAvcMBEncBwdPicFrame[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_G9;
3813     bindingTable->dwAvcMBEncFwdPicFrame[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX1_G9;
3814     bindingTable->dwAvcMBEncBwdPicFrame[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_G9;
3815     bindingTable->dwAvcMBEncFwdPicFrame[2] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX2_G9;
3816     bindingTable->dwAvcMBEncFwdPicFrame[3] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX3_G9;
3817     bindingTable->dwAvcMBEncFwdPicFrame[4] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX4_G9;
3818     bindingTable->dwAvcMBEncFwdPicFrame[5] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX5_G9;
3819     bindingTable->dwAvcMBEncFwdPicFrame[6] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX6_G9;
3820     bindingTable->dwAvcMBEncFwdPicFrame[7] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX7_G9;
3821     bindingTable->dwAvcMBEncCurrPicFrame[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_G9;
3822     bindingTable->dwAvcMBEncBwdPicFrame[2] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_G9;
3823     bindingTable->dwAvcMBEncBwdPicFrame[3] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_G9;
3824 
3825     // Field
3826     bindingTable->dwAvcMBEncMbQpField = CODECHAL_ENCODE_AVC_MBENC_MBQP_G9;
3827     bindingTable->dwAvcMBEncFieldCurrPic[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_0_G9;
3828     bindingTable->dwAvcMBEncFwdPicTopField[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX0_G9;
3829     bindingTable->dwAvcMBEncBwdPicTopField[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_G9;
3830     bindingTable->dwAvcMBEncFwdPicBotField[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX0_G9;
3831     bindingTable->dwAvcMBEncBwdPicBotField[0] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_0_G9;
3832     bindingTable->dwAvcMBEncFwdPicTopField[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX1_G9;
3833     bindingTable->dwAvcMBEncBwdPicTopField[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_G9;
3834     bindingTable->dwAvcMBEncFwdPicBotField[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX1_G9;
3835     bindingTable->dwAvcMBEncBwdPicBotField[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_0_G9;
3836     bindingTable->dwAvcMBEncFwdPicTopField[2] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX2_G9;
3837     bindingTable->dwAvcMBEncFwdPicBotField[2] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX2_G9;
3838     bindingTable->dwAvcMBEncFwdPicTopField[3] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX3_G9;
3839     bindingTable->dwAvcMBEncFwdPicBotField[3] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX3_G9;
3840     bindingTable->dwAvcMBEncFwdPicTopField[4] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX4_G9;
3841     bindingTable->dwAvcMBEncFwdPicBotField[4] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX4_G9;
3842     bindingTable->dwAvcMBEncFwdPicTopField[5] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX5_G9;
3843     bindingTable->dwAvcMBEncFwdPicBotField[5] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX5_G9;
3844     bindingTable->dwAvcMBEncFwdPicTopField[6] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX6_G9;
3845     bindingTable->dwAvcMBEncFwdPicBotField[6] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX6_G9;
3846     bindingTable->dwAvcMBEncFwdPicTopField[7] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX7_G9;
3847     bindingTable->dwAvcMBEncFwdPicBotField[7] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_FWD_PIC_IDX7_G9;
3848     bindingTable->dwAvcMBEncFieldCurrPic[1] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_CURR_PIC_IDX_1_G9;
3849     bindingTable->dwAvcMBEncBwdPicTopField[2] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_G9;
3850     bindingTable->dwAvcMBEncBwdPicBotField[2] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX0_1_G9;
3851     bindingTable->dwAvcMBEncBwdPicTopField[3] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_G9;
3852     bindingTable->dwAvcMBEncBwdPicBotField[3] = CODECHAL_ENCODE_AVC_MBENC_VME_INTER_PRED_BWD_PIC_IDX1_1_G9;
3853 
3854     return eStatus;
3855 }
3856 
InitKernelStateBrc()3857 MOS_STATUS CodechalEncodeAvcEncG9Kbl::InitKernelStateBrc()
3858 {
3859     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3860 
3861     CODECHAL_ENCODE_FUNCTION_ENTER;
3862 
3863     uint8_t* kernelBinary;
3864     uint32_t kernelSize;
3865 
3866     MOS_STATUS status = CodecHalGetKernelBinaryAndSize(m_kernelBase, m_kuid, &kernelBinary, &kernelSize);
3867     CODECHAL_ENCODE_CHK_STATUS_RETURN(status);
3868 
3869     CODECHAL_KERNEL_HEADER currKrnHeader;
3870     for (uint32_t krnStateIdx = 0; krnStateIdx < CODECHAL_ENCODE_BRC_IDX_NUM; krnStateIdx++)
3871     {
3872         auto kernelStatePtr = &BrcKernelStates[krnStateIdx];
3873         CODECHAL_ENCODE_CHK_STATUS_RETURN(GetKernelHeaderAndSize(
3874             kernelBinary,
3875             ENC_BRC,
3876             krnStateIdx,
3877             (void*)&currKrnHeader,
3878             &kernelSize));
3879 
3880         kernelStatePtr->KernelParams.iBTCount = BRC_BTCOUNTS[krnStateIdx];
3881         kernelStatePtr->KernelParams.iThreadCount = m_renderEngineInterface->GetHwCaps()->dwMaxThreads;
3882         kernelStatePtr->KernelParams.iCurbeLength = BRC_CURBE_SIZE[krnStateIdx];
3883         kernelStatePtr->KernelParams.iBlockWidth = CODECHAL_MACROBLOCK_WIDTH;
3884         kernelStatePtr->KernelParams.iBlockHeight = CODECHAL_MACROBLOCK_HEIGHT;
3885         kernelStatePtr->KernelParams.iIdCount = 1;
3886 
3887         kernelStatePtr->dwCurbeOffset = m_stateHeapInterface->pStateHeapInterface->GetSizeofCmdInterfaceDescriptorData();
3888         kernelStatePtr->KernelParams.pBinary = kernelBinary + (currKrnHeader.KernelStartPointer << MHW_KERNEL_OFFSET_SHIFT);
3889         kernelStatePtr->KernelParams.iSize = kernelSize;
3890 
3891         CODECHAL_ENCODE_CHK_STATUS_RETURN(m_stateHeapInterface->pfnCalculateSshAndBtSizesRequested(
3892             m_stateHeapInterface,
3893             kernelStatePtr->KernelParams.iBTCount,
3894             &kernelStatePtr->dwSshSize,
3895             &kernelStatePtr->dwBindingTableSize));
3896 
3897         CODECHAL_ENCODE_CHK_STATUS_RETURN(m_hwInterface->MhwInitISH(m_stateHeapInterface, kernelStatePtr));
3898     }
3899 
3900     // Until a better way can be found, maintain old binding table structures
3901     auto bindingTable = &BrcUpdateBindingTable;
3902     bindingTable->dwFrameBrcHistoryBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_HISTORY_G9_KBL;
3903     bindingTable->dwFrameBrcPakStatisticsOutputBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_PAK_STATISTICS_OUTPUT_G9_KBL;
3904     bindingTable->dwFrameBrcImageStateReadBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_READ_G9_KBL;
3905     bindingTable->dwFrameBrcImageStateWriteBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_IMAGE_STATE_WRITE_G9_KBL;
3906 
3907     bindingTable->dwFrameBrcMbEncCurbeWriteData = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MBENC_CURBE_WRITE_G9_KBL;
3908     bindingTable->dwFrameBrcDistortionBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_DISTORTION_G9_KBL;
3909     bindingTable->dwFrameBrcConstantData = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_CONSTANT_DATA_G9_KBL;
3910     bindingTable->dwFrameBrcMbStatBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MB_STAT_G9_KBL;
3911     bindingTable->dwFrameBrcMvDataBuffer = CODECHAL_ENCODE_AVC_FRAME_BRC_UPDATE_MV_G9_KBL;
3912 
3913     // starting GEN9 BRC kernel has split into a frame level update, and an MB level update.
3914     // above is BTI for frame level, below is BTI for MB level
3915     bindingTable->dwMbBrcHistoryBuffer = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_HISTORY_G9_KBL;
3916     bindingTable->dwMbBrcMbQpBuffer = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_MB_QP_G9_KBL;
3917     bindingTable->dwMbBrcROISurface = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_ROI_G9_KBL;
3918     bindingTable->dwMbBrcMbStatBuffer = CODECHAL_ENCODE_AVC_MB_BRC_UPDATE_MB_STAT_G9_KBL;
3919 
3920     return eStatus;
3921 }
3922 
SetCurbeAvcWP(PCODECHAL_ENCODE_AVC_WP_CURBE_PARAMS params)3923 MOS_STATUS CodechalEncodeAvcEncG9Kbl::SetCurbeAvcWP(PCODECHAL_ENCODE_AVC_WP_CURBE_PARAMS params)
3924 {
3925     MOS_STATUS eStatus = MOS_STATUS_SUCCESS;
3926     int16_t    weight;
3927 
3928     CODECHAL_ENCODE_CHK_NULL_RETURN(params);
3929 
3930     auto slcParams = m_avcSliceParams;
3931     auto seqParams = m_avcSeqParam;
3932     auto kernelState = pWPKernelState;
3933     CODECHAL_ENCODE_ASSERT(seqParams->TargetUsage < NUM_TARGET_USAGE_MODES);
3934 
3935     CODECHAL_ENCODE_AVC_WP_CURBE_G9_KBL cmd;
3936     MOS_ZeroMemory(&cmd, sizeof(CODECHAL_ENCODE_AVC_WP_CURBE_G9_KBL));
3937 
3938     /* Weights[i][j][k][m] is interpreted as:
3939 
3940     i refers to reference picture list 0 or 1;
3941     j refers to reference list entry 0-31;
3942     k refers to data for the luma (Y) component when it is 0, the Cb chroma component when it is 1 and the Cr chroma component when it is 2;
3943     m refers to weight when it is 0 and offset when it is 1
3944     */
3945     weight =  slcParams->Weights[params->RefPicListIdx][params->WPIdx][0][0];
3946     cmd.DW0.DefaultWeight = (weight << 6) >> (slcParams->luma_log2_weight_denom);
3947     cmd.DW0.DefaultOffset = slcParams->Weights[params->RefPicListIdx][params->WPIdx][0][1];
3948 
3949     cmd.DW49.InputSurface = CODECHAL_ENCODE_AVC_WP_INPUT_REF_SURFACE_G9;
3950     cmd.DW50.OutputSurface = CODECHAL_ENCODE_AVC_WP_OUTPUT_SCALED_SURFACE_G9;
3951 
3952     CODECHAL_ENCODE_CHK_STATUS_RETURN(kernelState->m_dshRegion.AddData(
3953         &cmd,
3954         kernelState->dwCurbeOffset,
3955         sizeof(cmd)));
3956 
3957     return eStatus;
3958 }
3959 
SceneChangeReport(PMOS_COMMAND_BUFFER cmdBuffer,PCODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS params)3960 MOS_STATUS CodechalEncodeAvcEncG9Kbl::SceneChangeReport(PMOS_COMMAND_BUFFER    cmdBuffer, PCODECHAL_ENCODE_AVC_GENERIC_PICTURE_LEVEL_PARAMS params)
3961 {
3962 
3963     MHW_MI_COPY_MEM_MEM_PARAMS                      copyMemMemParams;
3964     uint32_t offset = (m_encodeStatusBuf.wCurrIndex * m_encodeStatusBuf.dwReportSize)
3965         + (sizeof(uint32_t) * 2) + m_encodeStatusBuf.dwSceneChangedOffset;
3966 
3967     MOS_ZeroMemory(&copyMemMemParams, sizeof(copyMemMemParams));
3968     copyMemMemParams.presSrc = params->presBrcHistoryBuffer;
3969     copyMemMemParams.dwSrcOffset = CODECHAL_ENCODE_AVC_BRC_HISTORY_BUFFER_OFFSET_SCENE_CHANGED;
3970     copyMemMemParams.presDst = &m_encodeStatusBuf.resStatusBuffer;
3971     copyMemMemParams.dwDstOffset = offset;
3972     CODECHAL_ENCODE_CHK_STATUS_RETURN(m_miInterface->AddMiCopyMemMemCmd(
3973         cmdBuffer,
3974         &copyMemMemParams));
3975 
3976     return MOS_STATUS_SUCCESS;
3977 }
3978 
3979 #if USE_CODECHAL_DEBUG_TOOL
PopulateBrcInitParam(void * cmd)3980 MOS_STATUS CodechalEncodeAvcEncG9Kbl::PopulateBrcInitParam(
3981     void *cmd)
3982 {
3983     CODECHAL_DEBUG_FUNCTION_ENTER;
3984 
3985     CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
3986 
3987     if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
3988     {
3989         return MOS_STATUS_SUCCESS;
3990     }
3991 
3992     CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95 *curbe = (CODECHAL_ENCODE_AVC_BRC_INIT_RESET_CURBE_G95 *)cmd;
3993 
3994     if (m_pictureCodingType == I_TYPE)
3995     {
3996         m_avcPar->MBBRCEnable          = bMbBrcEnabled;
3997         m_avcPar->MBRC                 = bMbBrcEnabled;
3998         m_avcPar->BitRate              = curbe->DW3.AverageBitRate;
3999         m_avcPar->InitVbvFullnessInBit = curbe->DW1.InitBufFullInBits;
4000         m_avcPar->MaxBitRate           = curbe->DW4.MaxBitRate;
4001         m_avcPar->VbvSzInBit           = curbe->DW2.BufSizeInBits;
4002         m_avcPar->AvbrAccuracy         = curbe->DW10.AVBRAccuracy;
4003         m_avcPar->AvbrConvergence      = curbe->DW11.AVBRConvergence;
4004         m_avcPar->SlidingWindowSize    = curbe->DW22.SlidingWindowSize;
4005         m_avcPar->LongTermInterval     = curbe->DW24.LongTermInterval;
4006     }
4007 
4008     return MOS_STATUS_SUCCESS;
4009 }
4010 
PopulateBrcUpdateParam(void * cmd)4011 MOS_STATUS CodechalEncodeAvcEncG9Kbl::PopulateBrcUpdateParam(
4012     void *cmd)
4013 {
4014     CODECHAL_DEBUG_FUNCTION_ENTER;
4015 
4016     CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
4017 
4018     if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
4019     {
4020         return MOS_STATUS_SUCCESS;
4021     }
4022 
4023     CODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_G95 *curbe = (CODECHAL_ENCODE_AVC_BRC_UPDATE_CURBE_G95 *)cmd;
4024 
4025     if (m_pictureCodingType == I_TYPE)
4026     {
4027         m_avcPar->EnableMultipass     = (curbe->DW5.MaxNumPAKs > 0) ? 1 : 0;
4028         m_avcPar->MaxNumPakPasses     = curbe->DW5.MaxNumPAKs;
4029         m_avcPar->SlidingWindowEnable = curbe->DW6.EnableSlidingWindow;
4030         m_avcPar->FrameSkipEnable     = curbe->DW6.EnableForceToSkip;
4031         m_avcPar->UserMaxFrame        = curbe->DW19.UserMaxFrame;
4032     }
4033     else
4034     {
4035         m_avcPar->UserMaxFrameP = curbe->DW19.UserMaxFrame;
4036     }
4037 
4038     return MOS_STATUS_SUCCESS;
4039 }
4040 
PopulateEncParam(uint8_t meMethod,void * cmd)4041 MOS_STATUS CodechalEncodeAvcEncG9Kbl::PopulateEncParam(
4042     uint8_t meMethod,
4043     void    *cmd)
4044 {
4045     CODECHAL_DEBUG_FUNCTION_ENTER;
4046 
4047     CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
4048 
4049     if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
4050     {
4051         return MOS_STATUS_SUCCESS;
4052     }
4053 
4054     CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL *curbe = (CODECHAL_ENCODE_AVC_MBENC_CURBE_G9_KBL *)cmd;
4055 
4056     if (m_pictureCodingType == I_TYPE)
4057     {
4058         m_avcPar->MRDisableQPCheck = MRDisableQPCheck[m_targetUsage];
4059         m_avcPar->AllFractional =
4060             CODECHAL_ENCODE_AVC_AllFractional_Common[m_targetUsage & 0x7];
4061         m_avcPar->DisableAllFractionalCheckForHighRes =
4062             CODECHAL_ENCODE_AVC_DisableAllFractionalCheckForHighRes_Common[m_targetUsage & 0x7];
4063         m_avcPar->EnableAdaptiveSearch              = curbe->DW37.AdaptiveEn;
4064         m_avcPar->EnableFBRBypass                   = curbe->DW4.EnableFBRBypass;
4065         m_avcPar->BlockBasedSkip                    = curbe->DW3.BlockBasedSkipEnable;
4066         m_avcPar->MADEnableFlag                     = curbe->DW34.MADEnableFlag;
4067         m_avcPar->MBTextureThreshold                = curbe->DW60.MBTextureThreshold;
4068         m_avcPar->EnableMBFlatnessCheckOptimization = curbe->DW34.EnableMBFlatnessChkOptimization;
4069         m_avcPar->EnableArbitrarySliceSize          = curbe->DW34.ArbitraryNumMbsPerSlice;
4070         m_avcPar->RefThresh                         = curbe->DW38.RefThreshold;
4071         m_avcPar->EnableWavefrontOptimization       = curbe->DW4.EnableWavefrontOptimization;
4072         m_avcPar->MaxLenSP                          = curbe->DW2.LenSP;
4073         m_avcPar->DisableExtendedMvCostRange        = !curbe->DW1.ExtendedMvCostRange;
4074     }
4075     else if (m_pictureCodingType == P_TYPE)
4076     {
4077         m_avcPar->MEMethod                             = meMethod;
4078         m_avcPar->HMECombineLen                        = HMECombineLen[m_targetUsage];
4079         m_avcPar->FTQBasedSkip                         = FTQBasedSkip[m_targetUsage];
4080         m_avcPar->MultiplePred                         = MultiPred[m_targetUsage];
4081         m_avcPar->EnableAdaptiveIntraScaling           = bAdaptiveIntraScalingEnable;
4082         m_avcPar->StaticFrameIntraCostScalingRatioP    = 240;
4083         m_avcPar->SubPelMode                           = curbe->DW3.SubPelMode;
4084         m_avcPar->HMECombineOverlap                    = curbe->DW36.HMECombineOverlap;
4085         m_avcPar->SearchX                              = curbe->DW5.RefWidth;
4086         m_avcPar->SearchY                              = curbe->DW5.RefHeight;
4087         m_avcPar->SearchControl                        = curbe->DW3.SearchCtrl;
4088         m_avcPar->EnableAdaptiveTxDecision             = curbe->DW34.EnableAdaptiveTxDecision;
4089         m_avcPar->TxDecisionThr                        = curbe->DW60.TxDecisonThreshold;
4090         m_avcPar->EnablePerMBStaticCheck               = curbe->DW34.EnablePerMBStaticCheck;
4091         m_avcPar->EnableAdaptiveSearchWindowSize       = curbe->DW34.EnableAdaptiveSearchWindowSize;
4092         m_avcPar->EnableIntraCostScalingForStaticFrame = curbe->DW4.EnableIntraCostScalingForStaticFrame;
4093         m_avcPar->BiMixDisable                         = curbe->DW0.BiMixDis;
4094         m_avcPar->SurvivedSkipCost                     = (curbe->DW7.NonSkipZMvAdded << 1) + curbe->DW7.NonSkipModeAdded;
4095         m_avcPar->UniMixDisable                        = curbe->DW1.UniMixDisable;
4096     }
4097     else if (m_pictureCodingType == B_TYPE)
4098     {
4099         m_avcPar->BMEMethod                         = meMethod;
4100         m_avcPar->HMEBCombineLen                    = HMEBCombineLen[m_targetUsage];
4101         m_avcPar->StaticFrameIntraCostScalingRatioB = 200;
4102         m_avcPar->BSearchX                          = curbe->DW5.RefWidth;
4103         m_avcPar->BSearchY                          = curbe->DW5.RefHeight;
4104         m_avcPar->BSearchControl                    = curbe->DW3.SearchCtrl;
4105         m_avcPar->BSkipType                         = curbe->DW3.SkipType;
4106         m_avcPar->DirectMode                        = curbe->DW34.bDirectMode;
4107         m_avcPar->BiWeight                          = curbe->DW1.BiWeight;
4108     }
4109 
4110     return MOS_STATUS_SUCCESS;
4111 }
4112 
PopulatePakParam(PMOS_COMMAND_BUFFER cmdBuffer,PMHW_BATCH_BUFFER secondLevelBatchBuffer)4113 MOS_STATUS CodechalEncodeAvcEncG9Kbl::PopulatePakParam(
4114     PMOS_COMMAND_BUFFER cmdBuffer,
4115     PMHW_BATCH_BUFFER   secondLevelBatchBuffer)
4116 {
4117     CODECHAL_DEBUG_FUNCTION_ENTER;
4118 
4119     CODECHAL_DEBUG_CHK_NULL(m_debugInterface);
4120 
4121     if (!m_debugInterface->DumpIsEnabled(CodechalDbgAttr::attrDumpEncodePar))
4122     {
4123         return MOS_STATUS_SUCCESS;
4124     }
4125 
4126     uint8_t         *data = nullptr;
4127     MOS_LOCK_PARAMS lockFlags;
4128     MOS_ZeroMemory(&lockFlags, sizeof(MOS_LOCK_PARAMS));
4129     lockFlags.ReadOnly = 1;
4130 
4131     if (cmdBuffer != nullptr)
4132     {
4133         data = (uint8_t*)(cmdBuffer->pCmdPtr - (mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD::byteSize / sizeof(uint32_t)));
4134     }
4135     else if (secondLevelBatchBuffer != nullptr)
4136     {
4137         data = secondLevelBatchBuffer->pData;
4138     }
4139     else
4140     {
4141         data = (uint8_t*)m_osInterface->pfnLockResource(m_osInterface, &BrcBuffers.resBrcImageStatesReadBuffer[m_currRecycledBufIdx], &lockFlags);
4142     }
4143 
4144     CODECHAL_DEBUG_CHK_NULL(data);
4145 
4146     mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD mfxCmd;
4147     mfxCmd = *(mhw_vdbox_mfx_g9_kbl::MFX_AVC_IMG_STATE_CMD *)(data);
4148 
4149     if (m_pictureCodingType == I_TYPE)
4150     {
4151         m_avcPar->TrellisQuantizationEnable         = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
4152         m_avcPar->EnableAdaptiveTrellisQuantization = mfxCmd.DW5.TrellisQuantizationEnabledTqenb;
4153         m_avcPar->TrellisQuantizationRounding       = mfxCmd.DW5.TrellisQuantizationRoundingTqr;
4154         m_avcPar->TrellisQuantizationChromaDisable  = mfxCmd.DW5.TrellisQuantizationChromaDisableTqchromadisable;
4155         m_avcPar->ExtendedRhoDomainEn               = mfxCmd.DW16_17.ExtendedRhodomainStatisticsEnable;
4156     }
4157 
4158     if (data && (cmdBuffer == nullptr) && (secondLevelBatchBuffer == nullptr))
4159     {
4160         m_osInterface->pfnUnlockResource(
4161             m_osInterface,
4162             &BrcBuffers.resBrcImageStatesReadBuffer[m_currRecycledBufIdx]);
4163     }
4164 
4165     return MOS_STATUS_SUCCESS;
4166 }
4167 #endif
4168