1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include <linux/slab.h>
27
28 #include "dm_services.h"
29
30 #include "link_encoder.h"
31 #include "stream_encoder.h"
32
33 #include "resource.h"
34 #include "include/irq_service_interface.h"
35 #include "../virtual/virtual_stream_encoder.h"
36 #include "dce110/dce110_resource.h"
37 #include "dce110/dce110_timing_generator.h"
38 #include "irq/dce110/irq_service_dce110.h"
39 #include "dce/dce_link_encoder.h"
40 #include "dce/dce_stream_encoder.h"
41 #include "dce/dce_mem_input.h"
42 #include "dce/dce_ipp.h"
43 #include "dce/dce_transform.h"
44 #include "dce/dce_opp.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
48 #include "dce100/dce100_hw_sequencer.h"
49 #include "dce/dce_panel_cntl.h"
50
51 #include "reg_helper.h"
52
53 #include "dce/dce_10_0_d.h"
54 #include "dce/dce_10_0_sh_mask.h"
55
56 #include "dce/dce_dmcu.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_abm.h"
59 #include "dce/dce_i2c.h"
60
61 #include "dce100_resource.h"
62
63 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
64 #include "gmc/gmc_8_2_d.h"
65 #include "gmc/gmc_8_2_sh_mask.h"
66 #endif
67
68 #ifndef mmDP_DPHY_INTERNAL_CTRL
69 #define mmDP_DPHY_INTERNAL_CTRL 0x4aa7
70 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x4aa7
71 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x4ba7
72 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x4ca7
73 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x4da7
74 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x4ea7
75 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4fa7
76 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x54a7
77 #define mmDP7_DP_DPHY_INTERNAL_CTRL 0x56a7
78 #define mmDP8_DP_DPHY_INTERNAL_CTRL 0x57a7
79 #endif
80
81 #ifndef mmBIOS_SCRATCH_2
82 #define mmBIOS_SCRATCH_2 0x05CB
83 #define mmBIOS_SCRATCH_3 0x05CC
84 #define mmBIOS_SCRATCH_6 0x05CF
85 #endif
86
87 #ifndef mmDP_DPHY_BS_SR_SWAP_CNTL
88 #define mmDP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
89 #define mmDP0_DP_DPHY_BS_SR_SWAP_CNTL 0x4ADC
90 #define mmDP1_DP_DPHY_BS_SR_SWAP_CNTL 0x4BDC
91 #define mmDP2_DP_DPHY_BS_SR_SWAP_CNTL 0x4CDC
92 #define mmDP3_DP_DPHY_BS_SR_SWAP_CNTL 0x4DDC
93 #define mmDP4_DP_DPHY_BS_SR_SWAP_CNTL 0x4EDC
94 #define mmDP5_DP_DPHY_BS_SR_SWAP_CNTL 0x4FDC
95 #define mmDP6_DP_DPHY_BS_SR_SWAP_CNTL 0x54DC
96 #endif
97
98 #ifndef mmDP_DPHY_FAST_TRAINING
99 #define mmDP_DPHY_FAST_TRAINING 0x4ABC
100 #define mmDP0_DP_DPHY_FAST_TRAINING 0x4ABC
101 #define mmDP1_DP_DPHY_FAST_TRAINING 0x4BBC
102 #define mmDP2_DP_DPHY_FAST_TRAINING 0x4CBC
103 #define mmDP3_DP_DPHY_FAST_TRAINING 0x4DBC
104 #define mmDP4_DP_DPHY_FAST_TRAINING 0x4EBC
105 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4FBC
106 #define mmDP6_DP_DPHY_FAST_TRAINING 0x54BC
107 #endif
108
109 static const struct dce110_timing_generator_offsets dce100_tg_offsets[] = {
110 {
111 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
112 .dcp = (mmDCP0_GRPH_CONTROL - mmGRPH_CONTROL),
113 },
114 {
115 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
116 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
117 },
118 {
119 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
120 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
121 },
122 {
123 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
125 },
126 {
127 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
128 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
129 },
130 {
131 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
132 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
133 }
134 };
135
136 /* set register offset */
137 #define SR(reg_name)\
138 .reg_name = mm ## reg_name
139
140 /* set register offset with instance */
141 #define SRI(reg_name, block, id)\
142 .reg_name = mm ## block ## id ## _ ## reg_name
143
144 #define ipp_regs(id)\
145 [id] = {\
146 IPP_DCE100_REG_LIST_DCE_BASE(id)\
147 }
148
149 static const struct dce_ipp_registers ipp_regs[] = {
150 ipp_regs(0),
151 ipp_regs(1),
152 ipp_regs(2),
153 ipp_regs(3),
154 ipp_regs(4),
155 ipp_regs(5)
156 };
157
158 static const struct dce_ipp_shift ipp_shift = {
159 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
160 };
161
162 static const struct dce_ipp_mask ipp_mask = {
163 IPP_DCE100_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
164 };
165
166 #define transform_regs(id)\
167 [id] = {\
168 XFM_COMMON_REG_LIST_DCE100(id)\
169 }
170
171 static const struct dce_transform_registers xfm_regs[] = {
172 transform_regs(0),
173 transform_regs(1),
174 transform_regs(2),
175 transform_regs(3),
176 transform_regs(4),
177 transform_regs(5)
178 };
179
180 static const struct dce_transform_shift xfm_shift = {
181 XFM_COMMON_MASK_SH_LIST_DCE110(__SHIFT)
182 };
183
184 static const struct dce_transform_mask xfm_mask = {
185 XFM_COMMON_MASK_SH_LIST_DCE110(_MASK)
186 };
187
188 #define aux_regs(id)\
189 [id] = {\
190 AUX_REG_LIST(id)\
191 }
192
193 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
194 aux_regs(0),
195 aux_regs(1),
196 aux_regs(2),
197 aux_regs(3),
198 aux_regs(4),
199 aux_regs(5)
200 };
201
202 #define hpd_regs(id)\
203 [id] = {\
204 HPD_REG_LIST(id)\
205 }
206
207 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
208 hpd_regs(0),
209 hpd_regs(1),
210 hpd_regs(2),
211 hpd_regs(3),
212 hpd_regs(4),
213 hpd_regs(5)
214 };
215
216 #define link_regs(id)\
217 [id] = {\
218 LE_DCE100_REG_LIST(id)\
219 }
220
221 static const struct dce110_link_enc_registers link_enc_regs[] = {
222 link_regs(0),
223 link_regs(1),
224 link_regs(2),
225 link_regs(3),
226 link_regs(4),
227 link_regs(5),
228 link_regs(6),
229 };
230
231 #define stream_enc_regs(id)\
232 [id] = {\
233 SE_COMMON_REG_LIST_DCE_BASE(id),\
234 .AFMT_CNTL = 0,\
235 }
236
237 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
238 stream_enc_regs(0),
239 stream_enc_regs(1),
240 stream_enc_regs(2),
241 stream_enc_regs(3),
242 stream_enc_regs(4),
243 stream_enc_regs(5),
244 stream_enc_regs(6)
245 };
246
247 static const struct dce_stream_encoder_shift se_shift = {
248 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
249 };
250
251 static const struct dce_stream_encoder_mask se_mask = {
252 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
253 };
254
255 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
256 { DCE_PANEL_CNTL_REG_LIST() }
257 };
258
259 static const struct dce_panel_cntl_shift panel_cntl_shift = {
260 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
261 };
262
263 static const struct dce_panel_cntl_mask panel_cntl_mask = {
264 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
265 };
266
267 #define opp_regs(id)\
268 [id] = {\
269 OPP_DCE_100_REG_LIST(id),\
270 }
271
272 static const struct dce_opp_registers opp_regs[] = {
273 opp_regs(0),
274 opp_regs(1),
275 opp_regs(2),
276 opp_regs(3),
277 opp_regs(4),
278 opp_regs(5)
279 };
280
281 static const struct dce_opp_shift opp_shift = {
282 OPP_COMMON_MASK_SH_LIST_DCE_100(__SHIFT)
283 };
284
285 static const struct dce_opp_mask opp_mask = {
286 OPP_COMMON_MASK_SH_LIST_DCE_100(_MASK)
287 };
288 #define aux_engine_regs(id)\
289 [id] = {\
290 AUX_COMMON_REG_LIST(id), \
291 .AUX_RESET_MASK = 0 \
292 }
293
294 static const struct dce110_aux_registers aux_engine_regs[] = {
295 aux_engine_regs(0),
296 aux_engine_regs(1),
297 aux_engine_regs(2),
298 aux_engine_regs(3),
299 aux_engine_regs(4),
300 aux_engine_regs(5)
301 };
302
303 #define audio_regs(id)\
304 [id] = {\
305 AUD_COMMON_REG_LIST(id)\
306 }
307
308 static const struct dce_audio_registers audio_regs[] = {
309 audio_regs(0),
310 audio_regs(1),
311 audio_regs(2),
312 audio_regs(3),
313 audio_regs(4),
314 audio_regs(5),
315 audio_regs(6),
316 };
317
318 static const struct dce_audio_shift audio_shift = {
319 AUD_COMMON_MASK_SH_LIST(__SHIFT)
320 };
321
322 static const struct dce_audio_mask audio_mask = {
323 AUD_COMMON_MASK_SH_LIST(_MASK)
324 };
325
326 #define clk_src_regs(id)\
327 [id] = {\
328 CS_COMMON_REG_LIST_DCE_100_110(id),\
329 }
330
331 static const struct dce110_clk_src_regs clk_src_regs[] = {
332 clk_src_regs(0),
333 clk_src_regs(1),
334 clk_src_regs(2)
335 };
336
337 static const struct dce110_clk_src_shift cs_shift = {
338 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
339 };
340
341 static const struct dce110_clk_src_mask cs_mask = {
342 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
343 };
344
345 static const struct dce_dmcu_registers dmcu_regs = {
346 DMCU_DCE110_COMMON_REG_LIST()
347 };
348
349 static const struct dce_dmcu_shift dmcu_shift = {
350 DMCU_MASK_SH_LIST_DCE110(__SHIFT)
351 };
352
353 static const struct dce_dmcu_mask dmcu_mask = {
354 DMCU_MASK_SH_LIST_DCE110(_MASK)
355 };
356
357 static const struct dce_abm_registers abm_regs = {
358 ABM_DCE110_COMMON_REG_LIST()
359 };
360
361 static const struct dce_abm_shift abm_shift = {
362 ABM_MASK_SH_LIST_DCE110(__SHIFT)
363 };
364
365 static const struct dce_abm_mask abm_mask = {
366 ABM_MASK_SH_LIST_DCE110(_MASK)
367 };
368
369 #define DCFE_MEM_PWR_CTRL_REG_BASE 0x1b03
370
371 static const struct bios_registers bios_regs = {
372 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3,
373 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
374 };
375
376 static const struct resource_caps res_cap = {
377 .num_timing_generator = 6,
378 .num_audio = 6,
379 .num_stream_encoder = 6,
380 .num_pll = 3,
381 .num_ddc = 6,
382 };
383
384 static const struct dc_plane_cap plane_cap = {
385 .type = DC_PLANE_TYPE_DCE_RGB,
386
387 .pixel_format_support = {
388 .argb8888 = true,
389 .nv12 = false,
390 .fp16 = true
391 },
392
393 .max_upscale_factor = {
394 .argb8888 = 16000,
395 .nv12 = 1,
396 .fp16 = 1
397 },
398
399 .max_downscale_factor = {
400 .argb8888 = 250,
401 .nv12 = 1,
402 .fp16 = 1
403 }
404 };
405
406 #define CTX ctx
407 #define REG(reg) mm ## reg
408
409 #ifndef mmCC_DC_HDMI_STRAPS
410 #define mmCC_DC_HDMI_STRAPS 0x1918
411 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
412 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
413 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
414 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
415 #endif
416
map_transmitter_id_to_phy_instance(enum transmitter transmitter)417 static int map_transmitter_id_to_phy_instance(
418 enum transmitter transmitter)
419 {
420 switch (transmitter) {
421 case TRANSMITTER_UNIPHY_A:
422 return 0;
423 case TRANSMITTER_UNIPHY_B:
424 return 1;
425 case TRANSMITTER_UNIPHY_C:
426 return 2;
427 case TRANSMITTER_UNIPHY_D:
428 return 3;
429 case TRANSMITTER_UNIPHY_E:
430 return 4;
431 case TRANSMITTER_UNIPHY_F:
432 return 5;
433 case TRANSMITTER_UNIPHY_G:
434 return 6;
435 default:
436 ASSERT(0);
437 return 0;
438 }
439 }
440
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)441 static void read_dce_straps(
442 struct dc_context *ctx,
443 struct resource_straps *straps)
444 {
445 REG_GET_2(CC_DC_HDMI_STRAPS,
446 HDMI_DISABLE, &straps->hdmi_disable,
447 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
448
449 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
450 }
451
create_audio(struct dc_context * ctx,unsigned int inst)452 static struct audio *create_audio(
453 struct dc_context *ctx, unsigned int inst)
454 {
455 return dce_audio_create(ctx, inst,
456 &audio_regs[inst], &audio_shift, &audio_mask);
457 }
458
dce100_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)459 static struct timing_generator *dce100_timing_generator_create(
460 struct dc_context *ctx,
461 uint32_t instance,
462 const struct dce110_timing_generator_offsets *offsets)
463 {
464 struct dce110_timing_generator *tg110 =
465 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
466
467 if (!tg110)
468 return NULL;
469
470 dce110_timing_generator_construct(tg110, ctx, instance, offsets);
471 return &tg110->base;
472 }
473
dce100_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)474 static struct stream_encoder *dce100_stream_encoder_create(
475 enum engine_id eng_id,
476 struct dc_context *ctx)
477 {
478 struct dce110_stream_encoder *enc110 =
479 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
480
481 if (!enc110)
482 return NULL;
483
484 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
485 &stream_enc_regs[eng_id], &se_shift, &se_mask);
486 return &enc110->base;
487 }
488
489 #define SRII(reg_name, block, id)\
490 .reg_name[id] = mm ## block ## id ## _ ## reg_name
491
492 static const struct dce_hwseq_registers hwseq_reg = {
493 HWSEQ_DCE10_REG_LIST()
494 };
495
496 static const struct dce_hwseq_shift hwseq_shift = {
497 HWSEQ_DCE10_MASK_SH_LIST(__SHIFT)
498 };
499
500 static const struct dce_hwseq_mask hwseq_mask = {
501 HWSEQ_DCE10_MASK_SH_LIST(_MASK)
502 };
503
dce100_hwseq_create(struct dc_context * ctx)504 static struct dce_hwseq *dce100_hwseq_create(
505 struct dc_context *ctx)
506 {
507 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
508
509 if (hws) {
510 hws->ctx = ctx;
511 hws->regs = &hwseq_reg;
512 hws->shifts = &hwseq_shift;
513 hws->masks = &hwseq_mask;
514 }
515 return hws;
516 }
517
518 static const struct resource_create_funcs res_create_funcs = {
519 .read_dce_straps = read_dce_straps,
520 .create_audio = create_audio,
521 .create_stream_encoder = dce100_stream_encoder_create,
522 .create_hwseq = dce100_hwseq_create,
523 };
524
525 #define mi_inst_regs(id) { \
526 MI_DCE8_REG_LIST(id), \
527 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
528 }
529 static const struct dce_mem_input_registers mi_regs[] = {
530 mi_inst_regs(0),
531 mi_inst_regs(1),
532 mi_inst_regs(2),
533 mi_inst_regs(3),
534 mi_inst_regs(4),
535 mi_inst_regs(5),
536 };
537
538 static const struct dce_mem_input_shift mi_shifts = {
539 MI_DCE8_MASK_SH_LIST(__SHIFT),
540 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
541 };
542
543 static const struct dce_mem_input_mask mi_masks = {
544 MI_DCE8_MASK_SH_LIST(_MASK),
545 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
546 };
547
548 static const struct dce110_aux_registers_shift aux_shift = {
549 DCE10_AUX_MASK_SH_LIST(__SHIFT)
550 };
551
552 static const struct dce110_aux_registers_mask aux_mask = {
553 DCE10_AUX_MASK_SH_LIST(_MASK)
554 };
555
dce100_mem_input_create(struct dc_context * ctx,uint32_t inst)556 static struct mem_input *dce100_mem_input_create(
557 struct dc_context *ctx,
558 uint32_t inst)
559 {
560 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
561 GFP_KERNEL);
562
563 if (!dce_mi) {
564 BREAK_TO_DEBUGGER();
565 return NULL;
566 }
567
568 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
569 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
570 return &dce_mi->base;
571 }
572
dce100_transform_destroy(struct transform ** xfm)573 static void dce100_transform_destroy(struct transform **xfm)
574 {
575 kfree(TO_DCE_TRANSFORM(*xfm));
576 *xfm = NULL;
577 }
578
dce100_transform_create(struct dc_context * ctx,uint32_t inst)579 static struct transform *dce100_transform_create(
580 struct dc_context *ctx,
581 uint32_t inst)
582 {
583 struct dce_transform *transform =
584 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
585
586 if (!transform)
587 return NULL;
588
589 dce_transform_construct(transform, ctx, inst,
590 &xfm_regs[inst], &xfm_shift, &xfm_mask);
591 return &transform->base;
592 }
593
dce100_ipp_create(struct dc_context * ctx,uint32_t inst)594 static struct input_pixel_processor *dce100_ipp_create(
595 struct dc_context *ctx, uint32_t inst)
596 {
597 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
598
599 if (!ipp) {
600 BREAK_TO_DEBUGGER();
601 return NULL;
602 }
603
604 dce_ipp_construct(ipp, ctx, inst,
605 &ipp_regs[inst], &ipp_shift, &ipp_mask);
606 return &ipp->base;
607 }
608
609 static const struct encoder_feature_support link_enc_feature = {
610 .max_hdmi_deep_color = COLOR_DEPTH_121212,
611 .max_hdmi_pixel_clock = 300000,
612 .flags.bits.IS_HBR2_CAPABLE = true,
613 .flags.bits.IS_TPS3_CAPABLE = true
614 };
615
dce100_link_encoder_create(const struct encoder_init_data * enc_init_data)616 static struct link_encoder *dce100_link_encoder_create(
617 const struct encoder_init_data *enc_init_data)
618 {
619 struct dce110_link_encoder *enc110 =
620 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
621 int link_regs_id;
622
623 if (!enc110)
624 return NULL;
625
626 link_regs_id =
627 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
628
629 dce110_link_encoder_construct(enc110,
630 enc_init_data,
631 &link_enc_feature,
632 &link_enc_regs[link_regs_id],
633 &link_enc_aux_regs[enc_init_data->channel - 1],
634 &link_enc_hpd_regs[enc_init_data->hpd_source]);
635 return &enc110->base;
636 }
637
dce100_panel_cntl_create(const struct panel_cntl_init_data * init_data)638 static struct panel_cntl *dce100_panel_cntl_create(const struct panel_cntl_init_data *init_data)
639 {
640 struct dce_panel_cntl *panel_cntl =
641 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
642
643 if (!panel_cntl)
644 return NULL;
645
646 dce_panel_cntl_construct(panel_cntl,
647 init_data,
648 &panel_cntl_regs[init_data->inst],
649 &panel_cntl_shift,
650 &panel_cntl_mask);
651
652 return &panel_cntl->base;
653 }
654
dce100_opp_create(struct dc_context * ctx,uint32_t inst)655 static struct output_pixel_processor *dce100_opp_create(
656 struct dc_context *ctx,
657 uint32_t inst)
658 {
659 struct dce110_opp *opp =
660 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
661
662 if (!opp)
663 return NULL;
664
665 dce110_opp_construct(opp,
666 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
667 return &opp->base;
668 }
669
dce100_aux_engine_create(struct dc_context * ctx,uint32_t inst)670 static struct dce_aux *dce100_aux_engine_create(
671 struct dc_context *ctx,
672 uint32_t inst)
673 {
674 struct aux_engine_dce110 *aux_engine =
675 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
676
677 if (!aux_engine)
678 return NULL;
679
680 dce110_aux_engine_construct(aux_engine, ctx, inst,
681 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
682 &aux_engine_regs[inst],
683 &aux_mask,
684 &aux_shift,
685 ctx->dc->caps.extended_aux_timeout_support);
686
687 return &aux_engine->base;
688 }
689 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
690
691 static const struct dce_i2c_registers i2c_hw_regs[] = {
692 i2c_inst_regs(1),
693 i2c_inst_regs(2),
694 i2c_inst_regs(3),
695 i2c_inst_regs(4),
696 i2c_inst_regs(5),
697 i2c_inst_regs(6),
698 };
699
700 static const struct dce_i2c_shift i2c_shifts = {
701 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
702 };
703
704 static const struct dce_i2c_mask i2c_masks = {
705 I2C_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
706 };
707
dce100_i2c_hw_create(struct dc_context * ctx,uint32_t inst)708 static struct dce_i2c_hw *dce100_i2c_hw_create(
709 struct dc_context *ctx,
710 uint32_t inst)
711 {
712 struct dce_i2c_hw *dce_i2c_hw =
713 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
714
715 if (!dce_i2c_hw)
716 return NULL;
717
718 dce100_i2c_hw_construct(dce_i2c_hw, ctx, inst,
719 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
720
721 return dce_i2c_hw;
722 }
dce100_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)723 static struct clock_source *dce100_clock_source_create(
724 struct dc_context *ctx,
725 struct dc_bios *bios,
726 enum clock_source_id id,
727 const struct dce110_clk_src_regs *regs,
728 bool dp_clk_src)
729 {
730 struct dce110_clk_src *clk_src =
731 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
732
733 if (!clk_src)
734 return NULL;
735
736 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
737 regs, &cs_shift, &cs_mask)) {
738 clk_src->base.dp_clk_src = dp_clk_src;
739 return &clk_src->base;
740 }
741
742 kfree(clk_src);
743 BREAK_TO_DEBUGGER();
744 return NULL;
745 }
746
dce100_clock_source_destroy(struct clock_source ** clk_src)747 static void dce100_clock_source_destroy(struct clock_source **clk_src)
748 {
749 kfree(TO_DCE110_CLK_SRC(*clk_src));
750 *clk_src = NULL;
751 }
752
dce100_resource_destruct(struct dce110_resource_pool * pool)753 static void dce100_resource_destruct(struct dce110_resource_pool *pool)
754 {
755 unsigned int i;
756
757 for (i = 0; i < pool->base.pipe_count; i++) {
758 if (pool->base.opps[i] != NULL)
759 dce110_opp_destroy(&pool->base.opps[i]);
760
761 if (pool->base.transforms[i] != NULL)
762 dce100_transform_destroy(&pool->base.transforms[i]);
763
764 if (pool->base.ipps[i] != NULL)
765 dce_ipp_destroy(&pool->base.ipps[i]);
766
767 if (pool->base.mis[i] != NULL) {
768 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
769 pool->base.mis[i] = NULL;
770 }
771
772 if (pool->base.timing_generators[i] != NULL) {
773 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
774 pool->base.timing_generators[i] = NULL;
775 }
776 }
777
778 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
779 if (pool->base.engines[i] != NULL)
780 dce110_engine_destroy(&pool->base.engines[i]);
781 if (pool->base.hw_i2cs[i] != NULL) {
782 kfree(pool->base.hw_i2cs[i]);
783 pool->base.hw_i2cs[i] = NULL;
784 }
785 if (pool->base.sw_i2cs[i] != NULL) {
786 kfree(pool->base.sw_i2cs[i]);
787 pool->base.sw_i2cs[i] = NULL;
788 }
789 }
790
791 for (i = 0; i < pool->base.stream_enc_count; i++) {
792 if (pool->base.stream_enc[i] != NULL)
793 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
794 }
795
796 for (i = 0; i < pool->base.clk_src_count; i++) {
797 if (pool->base.clock_sources[i] != NULL)
798 dce100_clock_source_destroy(&pool->base.clock_sources[i]);
799 }
800
801 if (pool->base.dp_clock_source != NULL)
802 dce100_clock_source_destroy(&pool->base.dp_clock_source);
803
804 for (i = 0; i < pool->base.audio_count; i++) {
805 if (pool->base.audios[i] != NULL)
806 dce_aud_destroy(&pool->base.audios[i]);
807 }
808
809 if (pool->base.abm != NULL)
810 dce_abm_destroy(&pool->base.abm);
811
812 if (pool->base.dmcu != NULL)
813 dce_dmcu_destroy(&pool->base.dmcu);
814
815 if (pool->base.irqs != NULL)
816 dal_irq_service_destroy(&pool->base.irqs);
817 }
818
build_mapped_resource(const struct dc * dc,struct dc_state * context,struct dc_stream_state * stream)819 static enum dc_status build_mapped_resource(
820 const struct dc *dc,
821 struct dc_state *context,
822 struct dc_stream_state *stream)
823 {
824 struct pipe_ctx *pipe_ctx = resource_get_head_pipe_for_stream(&context->res_ctx, stream);
825
826 if (!pipe_ctx)
827 return DC_ERROR_UNEXPECTED;
828
829 dce110_resource_build_pipe_hw_param(pipe_ctx);
830
831 resource_build_info_frame(pipe_ctx);
832
833 return DC_OK;
834 }
835
dce100_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)836 static bool dce100_validate_bandwidth(
837 struct dc *dc,
838 struct dc_state *context,
839 bool fast_validate)
840 {
841 int i;
842 bool at_least_one_pipe = false;
843
844 for (i = 0; i < dc->res_pool->pipe_count; i++) {
845 if (context->res_ctx.pipe_ctx[i].stream)
846 at_least_one_pipe = true;
847 }
848
849 if (at_least_one_pipe) {
850 /* TODO implement when needed but for now hardcode max value*/
851 context->bw_ctx.bw.dce.dispclk_khz = 681000;
852 context->bw_ctx.bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER_CZ;
853 } else {
854 context->bw_ctx.bw.dce.dispclk_khz = 0;
855 context->bw_ctx.bw.dce.yclk_khz = 0;
856 }
857
858 return true;
859 }
860
dce100_validate_surface_sets(struct dc_state * context)861 static bool dce100_validate_surface_sets(
862 struct dc_state *context)
863 {
864 int i;
865
866 for (i = 0; i < context->stream_count; i++) {
867 if (context->stream_status[i].plane_count == 0)
868 continue;
869
870 if (context->stream_status[i].plane_count > 1)
871 return false;
872
873 if (context->stream_status[i].plane_states[0]->format
874 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
875 return false;
876 }
877
878 return true;
879 }
880
dce100_validate_global(struct dc * dc,struct dc_state * context)881 static enum dc_status dce100_validate_global(
882 struct dc *dc,
883 struct dc_state *context)
884 {
885 if (!dce100_validate_surface_sets(context))
886 return DC_FAIL_SURFACE_VALIDATE;
887
888 return DC_OK;
889 }
890
dce100_add_stream_to_ctx(struct dc * dc,struct dc_state * new_ctx,struct dc_stream_state * dc_stream)891 enum dc_status dce100_add_stream_to_ctx(
892 struct dc *dc,
893 struct dc_state *new_ctx,
894 struct dc_stream_state *dc_stream)
895 {
896 enum dc_status result = DC_ERROR_UNEXPECTED;
897
898 result = resource_map_pool_resources(dc, new_ctx, dc_stream);
899
900 if (result == DC_OK)
901 result = resource_map_clock_resources(dc, new_ctx, dc_stream);
902
903 if (result == DC_OK)
904 result = build_mapped_resource(dc, new_ctx, dc_stream);
905
906 return result;
907 }
908
dce100_destroy_resource_pool(struct resource_pool ** pool)909 static void dce100_destroy_resource_pool(struct resource_pool **pool)
910 {
911 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
912
913 dce100_resource_destruct(dce110_pool);
914 kfree(dce110_pool);
915 *pool = NULL;
916 }
917
dce100_validate_plane(const struct dc_plane_state * plane_state,struct dc_caps * caps)918 enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state, struct dc_caps *caps)
919 {
920
921 if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
922 return DC_OK;
923
924 return DC_FAIL_SURFACE_VALIDATE;
925 }
926
dce100_find_first_free_match_stream_enc_for_link(struct resource_context * res_ctx,const struct resource_pool * pool,struct dc_stream_state * stream)927 struct stream_encoder *dce100_find_first_free_match_stream_enc_for_link(
928 struct resource_context *res_ctx,
929 const struct resource_pool *pool,
930 struct dc_stream_state *stream)
931 {
932 int i;
933 int j = -1;
934 struct dc_link *link = stream->link;
935
936 for (i = 0; i < pool->stream_enc_count; i++) {
937 if (!res_ctx->is_stream_enc_acquired[i] &&
938 pool->stream_enc[i]) {
939 /* Store first available for MST second display
940 * in daisy chain use case
941 */
942 j = i;
943 if (pool->stream_enc[i]->id ==
944 link->link_enc->preferred_engine)
945 return pool->stream_enc[i];
946 }
947 }
948
949 /*
950 * below can happen in cases when stream encoder is acquired:
951 * 1) for second MST display in chain, so preferred engine already
952 * acquired;
953 * 2) for another link, which preferred engine already acquired by any
954 * MST configuration.
955 *
956 * If signal is of DP type and preferred engine not found, return last available
957 *
958 * TODO - This is just a patch up and a generic solution is
959 * required for non DP connectors.
960 */
961
962 if (j >= 0 && link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
963 return pool->stream_enc[j];
964
965 return NULL;
966 }
967
968 static const struct resource_funcs dce100_res_pool_funcs = {
969 .destroy = dce100_destroy_resource_pool,
970 .link_enc_create = dce100_link_encoder_create,
971 .panel_cntl_create = dce100_panel_cntl_create,
972 .validate_bandwidth = dce100_validate_bandwidth,
973 .validate_plane = dce100_validate_plane,
974 .add_stream_to_ctx = dce100_add_stream_to_ctx,
975 .validate_global = dce100_validate_global,
976 .find_first_free_match_stream_enc_for_link = dce100_find_first_free_match_stream_enc_for_link
977 };
978
dce100_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)979 static bool dce100_resource_construct(
980 uint8_t num_virtual_links,
981 struct dc *dc,
982 struct dce110_resource_pool *pool)
983 {
984 unsigned int i;
985 struct dc_context *ctx = dc->ctx;
986 struct dc_bios *bp;
987
988 ctx->dc_bios->regs = &bios_regs;
989
990 pool->base.res_cap = &res_cap;
991 pool->base.funcs = &dce100_res_pool_funcs;
992 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
993
994 bp = ctx->dc_bios;
995
996 if (bp->fw_info_valid && bp->fw_info.external_clock_source_frequency_for_dp != 0) {
997 pool->base.dp_clock_source =
998 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
999
1000 pool->base.clock_sources[0] =
1001 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1002 pool->base.clock_sources[1] =
1003 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1004 pool->base.clock_sources[2] =
1005 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1006 pool->base.clk_src_count = 3;
1007
1008 } else {
1009 pool->base.dp_clock_source =
1010 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1011
1012 pool->base.clock_sources[0] =
1013 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1014 pool->base.clock_sources[1] =
1015 dce100_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1016 pool->base.clk_src_count = 2;
1017 }
1018
1019 if (pool->base.dp_clock_source == NULL) {
1020 dm_error("DC: failed to create dp clock source!\n");
1021 BREAK_TO_DEBUGGER();
1022 goto res_create_fail;
1023 }
1024
1025 for (i = 0; i < pool->base.clk_src_count; i++) {
1026 if (pool->base.clock_sources[i] == NULL) {
1027 dm_error("DC: failed to create clock sources!\n");
1028 BREAK_TO_DEBUGGER();
1029 goto res_create_fail;
1030 }
1031 }
1032
1033 pool->base.dmcu = dce_dmcu_create(ctx,
1034 &dmcu_regs,
1035 &dmcu_shift,
1036 &dmcu_mask);
1037 if (pool->base.dmcu == NULL) {
1038 dm_error("DC: failed to create dmcu!\n");
1039 BREAK_TO_DEBUGGER();
1040 goto res_create_fail;
1041 }
1042
1043 pool->base.abm = dce_abm_create(ctx,
1044 &abm_regs,
1045 &abm_shift,
1046 &abm_mask);
1047 if (pool->base.abm == NULL) {
1048 dm_error("DC: failed to create abm!\n");
1049 BREAK_TO_DEBUGGER();
1050 goto res_create_fail;
1051 }
1052
1053 {
1054 struct irq_service_init_data init_data;
1055 init_data.ctx = dc->ctx;
1056 pool->base.irqs = dal_irq_service_dce110_create(&init_data);
1057 if (!pool->base.irqs)
1058 goto res_create_fail;
1059 }
1060
1061 /*************************************************
1062 * Resource + asic cap harcoding *
1063 *************************************************/
1064 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1065 pool->base.pipe_count = res_cap.num_timing_generator;
1066 pool->base.timing_generator_count = pool->base.res_cap->num_timing_generator;
1067 dc->caps.max_downscale_ratio = 200;
1068 dc->caps.i2c_speed_in_khz = 40;
1069 dc->caps.i2c_speed_in_khz = 40;
1070 dc->caps.max_cursor_size = 128;
1071 dc->caps.min_horizontal_blanking_period = 80;
1072 dc->caps.dual_link_dvi = true;
1073 dc->caps.disable_dp_clk_share = true;
1074 dc->caps.extended_aux_timeout_support = false;
1075
1076 for (i = 0; i < pool->base.pipe_count; i++) {
1077 pool->base.timing_generators[i] =
1078 dce100_timing_generator_create(
1079 ctx,
1080 i,
1081 &dce100_tg_offsets[i]);
1082 if (pool->base.timing_generators[i] == NULL) {
1083 BREAK_TO_DEBUGGER();
1084 dm_error("DC: failed to create tg!\n");
1085 goto res_create_fail;
1086 }
1087
1088 pool->base.mis[i] = dce100_mem_input_create(ctx, i);
1089 if (pool->base.mis[i] == NULL) {
1090 BREAK_TO_DEBUGGER();
1091 dm_error(
1092 "DC: failed to create memory input!\n");
1093 goto res_create_fail;
1094 }
1095
1096 pool->base.ipps[i] = dce100_ipp_create(ctx, i);
1097 if (pool->base.ipps[i] == NULL) {
1098 BREAK_TO_DEBUGGER();
1099 dm_error(
1100 "DC: failed to create input pixel processor!\n");
1101 goto res_create_fail;
1102 }
1103
1104 pool->base.transforms[i] = dce100_transform_create(ctx, i);
1105 if (pool->base.transforms[i] == NULL) {
1106 BREAK_TO_DEBUGGER();
1107 dm_error(
1108 "DC: failed to create transform!\n");
1109 goto res_create_fail;
1110 }
1111
1112 pool->base.opps[i] = dce100_opp_create(ctx, i);
1113 if (pool->base.opps[i] == NULL) {
1114 BREAK_TO_DEBUGGER();
1115 dm_error(
1116 "DC: failed to create output pixel processor!\n");
1117 goto res_create_fail;
1118 }
1119 }
1120
1121 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1122 pool->base.engines[i] = dce100_aux_engine_create(ctx, i);
1123 if (pool->base.engines[i] == NULL) {
1124 BREAK_TO_DEBUGGER();
1125 dm_error(
1126 "DC:failed to create aux engine!!\n");
1127 goto res_create_fail;
1128 }
1129 pool->base.hw_i2cs[i] = dce100_i2c_hw_create(ctx, i);
1130 if (pool->base.hw_i2cs[i] == NULL) {
1131 BREAK_TO_DEBUGGER();
1132 dm_error(
1133 "DC:failed to create i2c engine!!\n");
1134 goto res_create_fail;
1135 }
1136 pool->base.sw_i2cs[i] = NULL;
1137 }
1138
1139 dc->caps.max_planes = pool->base.pipe_count;
1140
1141 for (i = 0; i < dc->caps.max_planes; ++i)
1142 dc->caps.planes[i] = plane_cap;
1143
1144 if (!resource_construct(num_virtual_links, dc, &pool->base,
1145 &res_create_funcs))
1146 goto res_create_fail;
1147
1148 /* Create hardware sequencer */
1149 dce100_hw_sequencer_construct(dc);
1150 return true;
1151
1152 res_create_fail:
1153 dce100_resource_destruct(pool);
1154
1155 return false;
1156 }
1157
dce100_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1158 struct resource_pool *dce100_create_resource_pool(
1159 uint8_t num_virtual_links,
1160 struct dc *dc)
1161 {
1162 struct dce110_resource_pool *pool =
1163 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1164
1165 if (!pool)
1166 return NULL;
1167
1168 if (dce100_resource_construct(num_virtual_links, dc, pool))
1169 return &pool->base;
1170
1171 kfree(pool);
1172 BREAK_TO_DEBUGGER();
1173 return NULL;
1174 }
1175
1176