1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 * Copyright 2019 Raptor Engineering, LLC
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: AMD
24 *
25 */
26
27 #include <linux/slab.h>
28
29 #include "dm_services.h"
30 #include "dc.h"
31
32 #include "dcn21_init.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "dcn20/dcn20_resource.h"
37
38 #include "clk_mgr.h"
39 #include "dcn10/dcn10_hubp.h"
40 #include "dcn10/dcn10_ipp.h"
41 #include "dcn20/dcn20_hubbub.h"
42 #include "dcn20/dcn20_mpc.h"
43 #include "dcn20/dcn20_hubp.h"
44 #include "dcn21_hubp.h"
45 #include "irq/dcn21/irq_service_dcn21.h"
46 #include "dcn20/dcn20_dpp.h"
47 #include "dcn20/dcn20_optc.h"
48 #include "dcn21/dcn21_hwseq.h"
49 #include "dce110/dce110_hw_sequencer.h"
50 #include "dcn20/dcn20_opp.h"
51 #include "dcn20/dcn20_dsc.h"
52 #include "dcn21/dcn21_link_encoder.h"
53 #include "dcn20/dcn20_stream_encoder.h"
54 #include "dce/dce_clock_source.h"
55 #include "dce/dce_audio.h"
56 #include "dce/dce_hwseq.h"
57 #include "virtual/virtual_stream_encoder.h"
58 #include "dml/display_mode_vba.h"
59 #include "dcn20/dcn20_dccg.h"
60 #include "dcn21/dcn21_dccg.h"
61 #include "dcn21_hubbub.h"
62 #include "dcn10/dcn10_resource.h"
63 #include "dce/dce_panel_cntl.h"
64
65 #include "dcn20/dcn20_dwb.h"
66 #include "dcn20/dcn20_mmhubbub.h"
67 #include "dpcs/dpcs_2_1_0_offset.h"
68 #include "dpcs/dpcs_2_1_0_sh_mask.h"
69
70 #include "renoir_ip_offset.h"
71 #include "dcn/dcn_2_1_0_offset.h"
72 #include "dcn/dcn_2_1_0_sh_mask.h"
73
74 #include "nbio/nbio_7_0_offset.h"
75
76 #include "mmhub/mmhub_2_0_0_offset.h"
77 #include "mmhub/mmhub_2_0_0_sh_mask.h"
78
79 #include "reg_helper.h"
80 #include "dce/dce_abm.h"
81 #include "dce/dce_dmcu.h"
82 #include "dce/dce_aux.h"
83 #include "dce/dce_i2c.h"
84 #include "dcn21_resource.h"
85 #include "vm_helper.h"
86 #include "dcn20/dcn20_vmid.h"
87 #include "dce/dmub_psr.h"
88 #include "dce/dmub_abm.h"
89
90 #define DC_LOGGER_INIT(logger)
91
92
93 struct _vcs_dpi_ip_params_st dcn2_1_ip = {
94 .odm_capable = 1,
95 .gpuvm_enable = 1,
96 .hostvm_enable = 1,
97 .gpuvm_max_page_table_levels = 1,
98 .hostvm_max_page_table_levels = 4,
99 .hostvm_cached_page_table_levels = 2,
100 .num_dsc = 3,
101 .rob_buffer_size_kbytes = 168,
102 .det_buffer_size_kbytes = 164,
103 .dpte_buffer_size_in_pte_reqs_luma = 44,
104 .dpte_buffer_size_in_pte_reqs_chroma = 42,//todo
105 .dpp_output_buffer_pixels = 2560,
106 .opp_output_buffer_lines = 1,
107 .pixel_chunk_size_kbytes = 8,
108 .pte_enable = 1,
109 .max_page_table_levels = 4,
110 .pte_chunk_size_kbytes = 2,
111 .meta_chunk_size_kbytes = 2,
112 .writeback_chunk_size_kbytes = 2,
113 .line_buffer_size_bits = 789504,
114 .is_line_buffer_bpp_fixed = 0,
115 .line_buffer_fixed_bpp = 0,
116 .dcc_supported = true,
117 .max_line_buffer_lines = 12,
118 .writeback_luma_buffer_size_kbytes = 12,
119 .writeback_chroma_buffer_size_kbytes = 8,
120 .writeback_chroma_line_buffer_width_pixels = 4,
121 .writeback_max_hscl_ratio = 1,
122 .writeback_max_vscl_ratio = 1,
123 .writeback_min_hscl_ratio = 1,
124 .writeback_min_vscl_ratio = 1,
125 .writeback_max_hscl_taps = 12,
126 .writeback_max_vscl_taps = 12,
127 .writeback_line_buffer_luma_buffer_size = 0,
128 .writeback_line_buffer_chroma_buffer_size = 14643,
129 .cursor_buffer_size = 8,
130 .cursor_chunk_size = 2,
131 .max_num_otg = 4,
132 .max_num_dpp = 4,
133 .max_num_wb = 1,
134 .max_dchub_pscl_bw_pix_per_clk = 4,
135 .max_pscl_lb_bw_pix_per_clk = 2,
136 .max_lb_vscl_bw_pix_per_clk = 4,
137 .max_vscl_hscl_bw_pix_per_clk = 4,
138 .max_hscl_ratio = 4,
139 .max_vscl_ratio = 4,
140 .hscl_mults = 4,
141 .vscl_mults = 4,
142 .max_hscl_taps = 8,
143 .max_vscl_taps = 8,
144 .dispclk_ramp_margin_percent = 1,
145 .underscan_factor = 1.10,
146 .min_vblank_lines = 32, //
147 .dppclk_delay_subtotal = 77, //
148 .dppclk_delay_scl_lb_only = 16,
149 .dppclk_delay_scl = 50,
150 .dppclk_delay_cnvc_formatter = 8,
151 .dppclk_delay_cnvc_cursor = 6,
152 .dispclk_delay_subtotal = 87, //
153 .dcfclk_cstate_latency = 10, // SRExitTime
154 .max_inter_dcn_tile_repeaters = 8,
155
156 .xfc_supported = false,
157 .xfc_fill_bw_overhead_percent = 10.0,
158 .xfc_fill_constant_bytes = 0,
159 .ptoi_supported = 0,
160 .number_of_cursors = 1,
161 };
162
163 struct _vcs_dpi_soc_bounding_box_st dcn2_1_soc = {
164 .clock_limits = {
165 {
166 .state = 0,
167 .dcfclk_mhz = 400.0,
168 .fabricclk_mhz = 400.0,
169 .dispclk_mhz = 600.0,
170 .dppclk_mhz = 400.00,
171 .phyclk_mhz = 600.0,
172 .socclk_mhz = 278.0,
173 .dscclk_mhz = 205.67,
174 .dram_speed_mts = 1600.0,
175 },
176 {
177 .state = 1,
178 .dcfclk_mhz = 464.52,
179 .fabricclk_mhz = 800.0,
180 .dispclk_mhz = 654.55,
181 .dppclk_mhz = 626.09,
182 .phyclk_mhz = 600.0,
183 .socclk_mhz = 278.0,
184 .dscclk_mhz = 205.67,
185 .dram_speed_mts = 1600.0,
186 },
187 {
188 .state = 2,
189 .dcfclk_mhz = 514.29,
190 .fabricclk_mhz = 933.0,
191 .dispclk_mhz = 757.89,
192 .dppclk_mhz = 685.71,
193 .phyclk_mhz = 600.0,
194 .socclk_mhz = 278.0,
195 .dscclk_mhz = 287.67,
196 .dram_speed_mts = 1866.0,
197 },
198 {
199 .state = 3,
200 .dcfclk_mhz = 576.00,
201 .fabricclk_mhz = 1067.0,
202 .dispclk_mhz = 847.06,
203 .dppclk_mhz = 757.89,
204 .phyclk_mhz = 600.0,
205 .socclk_mhz = 715.0,
206 .dscclk_mhz = 318.334,
207 .dram_speed_mts = 2134.0,
208 },
209 {
210 .state = 4,
211 .dcfclk_mhz = 626.09,
212 .fabricclk_mhz = 1200.0,
213 .dispclk_mhz = 900.00,
214 .dppclk_mhz = 847.06,
215 .phyclk_mhz = 810.0,
216 .socclk_mhz = 953.0,
217 .dscclk_mhz = 489.0,
218 .dram_speed_mts = 2400.0,
219 },
220 {
221 .state = 5,
222 .dcfclk_mhz = 685.71,
223 .fabricclk_mhz = 1333.0,
224 .dispclk_mhz = 1028.57,
225 .dppclk_mhz = 960.00,
226 .phyclk_mhz = 810.0,
227 .socclk_mhz = 278.0,
228 .dscclk_mhz = 287.67,
229 .dram_speed_mts = 2666.0,
230 },
231 {
232 .state = 6,
233 .dcfclk_mhz = 757.89,
234 .fabricclk_mhz = 1467.0,
235 .dispclk_mhz = 1107.69,
236 .dppclk_mhz = 1028.57,
237 .phyclk_mhz = 810.0,
238 .socclk_mhz = 715.0,
239 .dscclk_mhz = 318.334,
240 .dram_speed_mts = 3200.0,
241 },
242 {
243 .state = 7,
244 .dcfclk_mhz = 847.06,
245 .fabricclk_mhz = 1600.0,
246 .dispclk_mhz = 1395.0,
247 .dppclk_mhz = 1285.00,
248 .phyclk_mhz = 1325.0,
249 .socclk_mhz = 953.0,
250 .dscclk_mhz = 489.0,
251 .dram_speed_mts = 4266.0,
252 },
253 /*Extra state, no dispclk ramping*/
254 {
255 .state = 8,
256 .dcfclk_mhz = 847.06,
257 .fabricclk_mhz = 1600.0,
258 .dispclk_mhz = 1395.0,
259 .dppclk_mhz = 1285.0,
260 .phyclk_mhz = 1325.0,
261 .socclk_mhz = 953.0,
262 .dscclk_mhz = 489.0,
263 .dram_speed_mts = 4266.0,
264 },
265
266 },
267
268 .sr_exit_time_us = 12.5,
269 .sr_enter_plus_exit_time_us = 17.0,
270 .urgent_latency_us = 4.0,
271 .urgent_latency_pixel_data_only_us = 4.0,
272 .urgent_latency_pixel_mixed_with_vm_data_us = 4.0,
273 .urgent_latency_vm_data_only_us = 4.0,
274 .urgent_out_of_order_return_per_channel_pixel_only_bytes = 4096,
275 .urgent_out_of_order_return_per_channel_pixel_and_vm_bytes = 4096,
276 .urgent_out_of_order_return_per_channel_vm_only_bytes = 4096,
277 .pct_ideal_dram_sdp_bw_after_urgent_pixel_only = 80.0,
278 .pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm = 75.0,
279 .pct_ideal_dram_sdp_bw_after_urgent_vm_only = 40.0,
280 .max_avg_sdp_bw_use_normal_percent = 60.0,
281 .max_avg_dram_bw_use_normal_percent = 100.0,
282 .writeback_latency_us = 12.0,
283 .max_request_size_bytes = 256,
284 .dram_channel_width_bytes = 4,
285 .fabric_datapath_to_dcn_data_return_bytes = 32,
286 .dcn_downspread_percent = 0.5,
287 .downspread_percent = 0.38,
288 .dram_page_open_time_ns = 50.0,
289 .dram_rw_turnaround_time_ns = 17.5,
290 .dram_return_buffer_per_channel_bytes = 8192,
291 .round_trip_ping_latency_dcfclk_cycles = 128,
292 .urgent_out_of_order_return_per_channel_bytes = 4096,
293 .channel_interleave_bytes = 256,
294 .num_banks = 8,
295 .num_chans = 4,
296 .vmm_page_size_bytes = 4096,
297 .dram_clock_change_latency_us = 23.84,
298 .return_bus_width_bytes = 64,
299 .dispclk_dppclk_vco_speed_mhz = 3600,
300 .xfc_bus_transport_time_us = 4,
301 .xfc_xbuf_latency_tolerance_us = 4,
302 .use_urgent_burst_bw = 1,
303 .num_states = 8
304 };
305
306 #ifndef MAX
307 #define MAX(X, Y) ((X) > (Y) ? (X) : (Y))
308 #endif
309 #ifndef MIN
310 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
311 #endif
312
313 /* begin *********************
314 * macros to expend register list macro defined in HW object header file */
315
316 /* DCN */
317 /* TODO awful hack. fixup dcn20_dwb.h */
318 #undef BASE_INNER
319 #define BASE_INNER(seg) DMU_BASE__INST0_SEG ## seg
320
321 #define BASE(seg) BASE_INNER(seg)
322
323 #define SR(reg_name)\
324 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \
325 mm ## reg_name
326
327 #define SRI(reg_name, block, id)\
328 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
329 mm ## block ## id ## _ ## reg_name
330
331 #define SRIR(var_name, reg_name, block, id)\
332 .var_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
333 mm ## block ## id ## _ ## reg_name
334
335 #define SRII(reg_name, block, id)\
336 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
337 mm ## block ## id ## _ ## reg_name
338
339 #define DCCG_SRII(reg_name, block, id)\
340 .block ## _ ## reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
341 mm ## block ## id ## _ ## reg_name
342
343 #define VUPDATE_SRII(reg_name, block, id)\
344 .reg_name[id] = BASE(mm ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
345 mm ## reg_name ## _ ## block ## id
346
347 /* NBIO */
348 #define NBIO_BASE_INNER(seg) \
349 NBIF0_BASE__INST0_SEG ## seg
350
351 #define NBIO_BASE(seg) \
352 NBIO_BASE_INNER(seg)
353
354 #define NBIO_SR(reg_name)\
355 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
356 mm ## reg_name
357
358 /* MMHUB */
359 #define MMHUB_BASE_INNER(seg) \
360 MMHUB_BASE__INST0_SEG ## seg
361
362 #define MMHUB_BASE(seg) \
363 MMHUB_BASE_INNER(seg)
364
365 #define MMHUB_SR(reg_name)\
366 .reg_name = MMHUB_BASE(mmMM ## reg_name ## _BASE_IDX) + \
367 mmMM ## reg_name
368
369 #define clk_src_regs(index, pllid)\
370 [index] = {\
371 CS_COMMON_REG_LIST_DCN2_1(index, pllid),\
372 }
373
374 static const struct dce110_clk_src_regs clk_src_regs[] = {
375 clk_src_regs(0, A),
376 clk_src_regs(1, B),
377 clk_src_regs(2, C),
378 clk_src_regs(3, D),
379 clk_src_regs(4, E),
380 };
381
382 static const struct dce110_clk_src_shift cs_shift = {
383 CS_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
384 };
385
386 static const struct dce110_clk_src_mask cs_mask = {
387 CS_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
388 };
389
390 static const struct bios_registers bios_regs = {
391 NBIO_SR(BIOS_SCRATCH_3),
392 NBIO_SR(BIOS_SCRATCH_6)
393 };
394
395 static const struct dce_dmcu_registers dmcu_regs = {
396 DMCU_DCN20_REG_LIST()
397 };
398
399 static const struct dce_dmcu_shift dmcu_shift = {
400 DMCU_MASK_SH_LIST_DCN10(__SHIFT)
401 };
402
403 static const struct dce_dmcu_mask dmcu_mask = {
404 DMCU_MASK_SH_LIST_DCN10(_MASK)
405 };
406
407 static const struct dce_abm_registers abm_regs = {
408 ABM_DCN20_REG_LIST()
409 };
410
411 static const struct dce_abm_shift abm_shift = {
412 ABM_MASK_SH_LIST_DCN20(__SHIFT)
413 };
414
415 static const struct dce_abm_mask abm_mask = {
416 ABM_MASK_SH_LIST_DCN20(_MASK)
417 };
418
419 #define audio_regs(id)\
420 [id] = {\
421 AUD_COMMON_REG_LIST(id)\
422 }
423
424 static const struct dce_audio_registers audio_regs[] = {
425 audio_regs(0),
426 audio_regs(1),
427 audio_regs(2),
428 audio_regs(3),
429 audio_regs(4),
430 audio_regs(5),
431 };
432
433 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
434 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
435 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
436 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
437
438 static const struct dce_audio_shift audio_shift = {
439 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
440 };
441
442 static const struct dce_audio_mask audio_mask = {
443 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
444 };
445
446 static const struct dccg_registers dccg_regs = {
447 DCCG_COMMON_REG_LIST_DCN_BASE()
448 };
449
450 static const struct dccg_shift dccg_shift = {
451 DCCG_MASK_SH_LIST_DCN2(__SHIFT)
452 };
453
454 static const struct dccg_mask dccg_mask = {
455 DCCG_MASK_SH_LIST_DCN2(_MASK)
456 };
457
458 #define opp_regs(id)\
459 [id] = {\
460 OPP_REG_LIST_DCN20(id),\
461 }
462
463 static const struct dcn20_opp_registers opp_regs[] = {
464 opp_regs(0),
465 opp_regs(1),
466 opp_regs(2),
467 opp_regs(3),
468 opp_regs(4),
469 opp_regs(5),
470 };
471
472 static const struct dcn20_opp_shift opp_shift = {
473 OPP_MASK_SH_LIST_DCN20(__SHIFT)
474 };
475
476 static const struct dcn20_opp_mask opp_mask = {
477 OPP_MASK_SH_LIST_DCN20(_MASK)
478 };
479
480 #define tg_regs(id)\
481 [id] = {TG_COMMON_REG_LIST_DCN2_0(id)}
482
483 static const struct dcn_optc_registers tg_regs[] = {
484 tg_regs(0),
485 tg_regs(1),
486 tg_regs(2),
487 tg_regs(3)
488 };
489
490 static const struct dcn_optc_shift tg_shift = {
491 TG_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT)
492 };
493
494 static const struct dcn_optc_mask tg_mask = {
495 TG_COMMON_MASK_SH_LIST_DCN2_0(_MASK)
496 };
497
498 static const struct dcn20_mpc_registers mpc_regs = {
499 MPC_REG_LIST_DCN2_0(0),
500 MPC_REG_LIST_DCN2_0(1),
501 MPC_REG_LIST_DCN2_0(2),
502 MPC_REG_LIST_DCN2_0(3),
503 MPC_REG_LIST_DCN2_0(4),
504 MPC_REG_LIST_DCN2_0(5),
505 MPC_OUT_MUX_REG_LIST_DCN2_0(0),
506 MPC_OUT_MUX_REG_LIST_DCN2_0(1),
507 MPC_OUT_MUX_REG_LIST_DCN2_0(2),
508 MPC_OUT_MUX_REG_LIST_DCN2_0(3),
509 MPC_DBG_REG_LIST_DCN2_0()
510 };
511
512 static const struct dcn20_mpc_shift mpc_shift = {
513 MPC_COMMON_MASK_SH_LIST_DCN2_0(__SHIFT),
514 MPC_DEBUG_REG_LIST_SH_DCN20
515 };
516
517 static const struct dcn20_mpc_mask mpc_mask = {
518 MPC_COMMON_MASK_SH_LIST_DCN2_0(_MASK),
519 MPC_DEBUG_REG_LIST_MASK_DCN20
520 };
521
522 #define hubp_regs(id)\
523 [id] = {\
524 HUBP_REG_LIST_DCN21(id)\
525 }
526
527 static const struct dcn_hubp2_registers hubp_regs[] = {
528 hubp_regs(0),
529 hubp_regs(1),
530 hubp_regs(2),
531 hubp_regs(3)
532 };
533
534 static const struct dcn_hubp2_shift hubp_shift = {
535 HUBP_MASK_SH_LIST_DCN21(__SHIFT)
536 };
537
538 static const struct dcn_hubp2_mask hubp_mask = {
539 HUBP_MASK_SH_LIST_DCN21(_MASK)
540 };
541
542 static const struct dcn_hubbub_registers hubbub_reg = {
543 HUBBUB_REG_LIST_DCN21()
544 };
545
546 static const struct dcn_hubbub_shift hubbub_shift = {
547 HUBBUB_MASK_SH_LIST_DCN21(__SHIFT)
548 };
549
550 static const struct dcn_hubbub_mask hubbub_mask = {
551 HUBBUB_MASK_SH_LIST_DCN21(_MASK)
552 };
553
554
555 #define vmid_regs(id)\
556 [id] = {\
557 DCN20_VMID_REG_LIST(id)\
558 }
559
560 static const struct dcn_vmid_registers vmid_regs[] = {
561 vmid_regs(0),
562 vmid_regs(1),
563 vmid_regs(2),
564 vmid_regs(3),
565 vmid_regs(4),
566 vmid_regs(5),
567 vmid_regs(6),
568 vmid_regs(7),
569 vmid_regs(8),
570 vmid_regs(9),
571 vmid_regs(10),
572 vmid_regs(11),
573 vmid_regs(12),
574 vmid_regs(13),
575 vmid_regs(14),
576 vmid_regs(15)
577 };
578
579 static const struct dcn20_vmid_shift vmid_shifts = {
580 DCN20_VMID_MASK_SH_LIST(__SHIFT)
581 };
582
583 static const struct dcn20_vmid_mask vmid_masks = {
584 DCN20_VMID_MASK_SH_LIST(_MASK)
585 };
586
587 #define dsc_regsDCN20(id)\
588 [id] = {\
589 DSC_REG_LIST_DCN20(id)\
590 }
591
592 static const struct dcn20_dsc_registers dsc_regs[] = {
593 dsc_regsDCN20(0),
594 dsc_regsDCN20(1),
595 dsc_regsDCN20(2),
596 dsc_regsDCN20(3),
597 dsc_regsDCN20(4),
598 dsc_regsDCN20(5)
599 };
600
601 static const struct dcn20_dsc_shift dsc_shift = {
602 DSC_REG_LIST_SH_MASK_DCN20(__SHIFT)
603 };
604
605 static const struct dcn20_dsc_mask dsc_mask = {
606 DSC_REG_LIST_SH_MASK_DCN20(_MASK)
607 };
608
609 #define ipp_regs(id)\
610 [id] = {\
611 IPP_REG_LIST_DCN20(id),\
612 }
613
614 static const struct dcn10_ipp_registers ipp_regs[] = {
615 ipp_regs(0),
616 ipp_regs(1),
617 ipp_regs(2),
618 ipp_regs(3),
619 };
620
621 static const struct dcn10_ipp_shift ipp_shift = {
622 IPP_MASK_SH_LIST_DCN20(__SHIFT)
623 };
624
625 static const struct dcn10_ipp_mask ipp_mask = {
626 IPP_MASK_SH_LIST_DCN20(_MASK),
627 };
628
629 #define opp_regs(id)\
630 [id] = {\
631 OPP_REG_LIST_DCN20(id),\
632 }
633
634
635 #define aux_engine_regs(id)\
636 [id] = {\
637 AUX_COMMON_REG_LIST0(id), \
638 .AUXN_IMPCAL = 0, \
639 .AUXP_IMPCAL = 0, \
640 .AUX_RESET_MASK = DP_AUX0_AUX_CONTROL__AUX_RESET_MASK, \
641 }
642
643 static const struct dce110_aux_registers aux_engine_regs[] = {
644 aux_engine_regs(0),
645 aux_engine_regs(1),
646 aux_engine_regs(2),
647 aux_engine_regs(3),
648 aux_engine_regs(4),
649 };
650
651 #define tf_regs(id)\
652 [id] = {\
653 TF_REG_LIST_DCN20(id),\
654 TF_REG_LIST_DCN20_COMMON_APPEND(id),\
655 }
656
657 static const struct dcn2_dpp_registers tf_regs[] = {
658 tf_regs(0),
659 tf_regs(1),
660 tf_regs(2),
661 tf_regs(3),
662 };
663
664 static const struct dcn2_dpp_shift tf_shift = {
665 TF_REG_LIST_SH_MASK_DCN20(__SHIFT),
666 TF_DEBUG_REG_LIST_SH_DCN20
667 };
668
669 static const struct dcn2_dpp_mask tf_mask = {
670 TF_REG_LIST_SH_MASK_DCN20(_MASK),
671 TF_DEBUG_REG_LIST_MASK_DCN20
672 };
673
674 #define stream_enc_regs(id)\
675 [id] = {\
676 SE_DCN2_REG_LIST(id)\
677 }
678
679 static const struct dcn10_stream_enc_registers stream_enc_regs[] = {
680 stream_enc_regs(0),
681 stream_enc_regs(1),
682 stream_enc_regs(2),
683 stream_enc_regs(3),
684 stream_enc_regs(4),
685 };
686
687 static const struct dce110_aux_registers_shift aux_shift = {
688 DCN_AUX_MASK_SH_LIST(__SHIFT)
689 };
690
691 static const struct dce110_aux_registers_mask aux_mask = {
692 DCN_AUX_MASK_SH_LIST(_MASK)
693 };
694
695 static const struct dcn10_stream_encoder_shift se_shift = {
696 SE_COMMON_MASK_SH_LIST_DCN20(__SHIFT)
697 };
698
699 static const struct dcn10_stream_encoder_mask se_mask = {
700 SE_COMMON_MASK_SH_LIST_DCN20(_MASK)
701 };
702
703 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu);
704
705 static int dcn21_populate_dml_pipes_from_context(
706 struct dc *dc,
707 struct dc_state *context,
708 display_e2e_pipe_params_st *pipes,
709 bool fast_validate);
710
dcn21_ipp_create(struct dc_context * ctx,uint32_t inst)711 static struct input_pixel_processor *dcn21_ipp_create(
712 struct dc_context *ctx, uint32_t inst)
713 {
714 struct dcn10_ipp *ipp =
715 kzalloc(sizeof(struct dcn10_ipp), GFP_KERNEL);
716
717 if (!ipp) {
718 BREAK_TO_DEBUGGER();
719 return NULL;
720 }
721
722 dcn20_ipp_construct(ipp, ctx, inst,
723 &ipp_regs[inst], &ipp_shift, &ipp_mask);
724 return &ipp->base;
725 }
726
dcn21_dpp_create(struct dc_context * ctx,uint32_t inst)727 static struct dpp *dcn21_dpp_create(
728 struct dc_context *ctx,
729 uint32_t inst)
730 {
731 struct dcn20_dpp *dpp =
732 kzalloc(sizeof(struct dcn20_dpp), GFP_KERNEL);
733
734 if (!dpp)
735 return NULL;
736
737 if (dpp2_construct(dpp, ctx, inst,
738 &tf_regs[inst], &tf_shift, &tf_mask))
739 return &dpp->base;
740
741 BREAK_TO_DEBUGGER();
742 kfree(dpp);
743 return NULL;
744 }
745
dcn21_aux_engine_create(struct dc_context * ctx,uint32_t inst)746 static struct dce_aux *dcn21_aux_engine_create(
747 struct dc_context *ctx,
748 uint32_t inst)
749 {
750 struct aux_engine_dce110 *aux_engine =
751 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
752
753 if (!aux_engine)
754 return NULL;
755
756 dce110_aux_engine_construct(aux_engine, ctx, inst,
757 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
758 &aux_engine_regs[inst],
759 &aux_mask,
760 &aux_shift,
761 ctx->dc->caps.extended_aux_timeout_support);
762
763 return &aux_engine->base;
764 }
765
766 #define i2c_inst_regs(id) { I2C_HW_ENGINE_COMMON_REG_LIST(id) }
767
768 static const struct dce_i2c_registers i2c_hw_regs[] = {
769 i2c_inst_regs(1),
770 i2c_inst_regs(2),
771 i2c_inst_regs(3),
772 i2c_inst_regs(4),
773 i2c_inst_regs(5),
774 };
775
776 static const struct dce_i2c_shift i2c_shifts = {
777 I2C_COMMON_MASK_SH_LIST_DCN2(__SHIFT)
778 };
779
780 static const struct dce_i2c_mask i2c_masks = {
781 I2C_COMMON_MASK_SH_LIST_DCN2(_MASK)
782 };
783
dcn21_i2c_hw_create(struct dc_context * ctx,uint32_t inst)784 struct dce_i2c_hw *dcn21_i2c_hw_create(
785 struct dc_context *ctx,
786 uint32_t inst)
787 {
788 struct dce_i2c_hw *dce_i2c_hw =
789 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
790
791 if (!dce_i2c_hw)
792 return NULL;
793
794 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
795 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
796
797 return dce_i2c_hw;
798 }
799
800 static const struct resource_caps res_cap_rn = {
801 .num_timing_generator = 4,
802 .num_opp = 4,
803 .num_video_plane = 4,
804 .num_audio = 4, // 4 audio endpoints. 4 audio streams
805 .num_stream_encoder = 5,
806 .num_pll = 5, // maybe 3 because the last two used for USB-c
807 .num_dwb = 1,
808 .num_ddc = 5,
809 .num_vmid = 16,
810 .num_dsc = 3,
811 };
812
813 #ifdef DIAGS_BUILD
814 static const struct resource_caps res_cap_rn_FPGA_4pipe = {
815 .num_timing_generator = 4,
816 .num_opp = 4,
817 .num_video_plane = 4,
818 .num_audio = 7,
819 .num_stream_encoder = 4,
820 .num_pll = 4,
821 .num_dwb = 1,
822 .num_ddc = 4,
823 .num_dsc = 0,
824 };
825
826 static const struct resource_caps res_cap_rn_FPGA_2pipe_dsc = {
827 .num_timing_generator = 2,
828 .num_opp = 2,
829 .num_video_plane = 2,
830 .num_audio = 7,
831 .num_stream_encoder = 2,
832 .num_pll = 4,
833 .num_dwb = 1,
834 .num_ddc = 4,
835 .num_dsc = 2,
836 };
837 #endif
838
839 static const struct dc_plane_cap plane_cap = {
840 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
841 .blends_with_above = true,
842 .blends_with_below = true,
843 .per_pixel_alpha = true,
844
845 .pixel_format_support = {
846 .argb8888 = true,
847 .nv12 = true,
848 .fp16 = true,
849 .p010 = true
850 },
851
852 .max_upscale_factor = {
853 .argb8888 = 16000,
854 .nv12 = 16000,
855 .fp16 = 16000
856 },
857
858 .max_downscale_factor = {
859 .argb8888 = 250,
860 .nv12 = 250,
861 .fp16 = 250
862 },
863 64,
864 64
865 };
866
867 static const struct dc_debug_options debug_defaults_drv = {
868 .disable_dmcu = false,
869 .force_abm_enable = false,
870 .timing_trace = false,
871 .clock_trace = true,
872 .disable_pplib_clock_request = true,
873 .min_disp_clk_khz = 100000,
874 .pipe_split_policy = MPC_SPLIT_AVOID_MULT_DISP,
875 .force_single_disp_pipe_split = false,
876 .disable_dcc = DCC_ENABLE,
877 .vsr_support = true,
878 .performance_trace = false,
879 .max_downscale_src_width = 4096,
880 .disable_pplib_wm_range = false,
881 .scl_reset_length10 = true,
882 .sanity_checks = true,
883 .disable_48mhz_pwrdwn = false,
884 .usbc_combo_phy_reset_wa = true,
885 .dmub_command_table = true,
886 .use_max_lb = true
887 };
888
889 static const struct dc_debug_options debug_defaults_diags = {
890 .disable_dmcu = false,
891 .force_abm_enable = false,
892 .timing_trace = true,
893 .clock_trace = true,
894 .disable_dpp_power_gate = true,
895 .disable_hubp_power_gate = true,
896 .disable_clock_gate = true,
897 .disable_pplib_clock_request = true,
898 .disable_pplib_wm_range = true,
899 .disable_stutter = true,
900 .disable_48mhz_pwrdwn = true,
901 .disable_psr = true,
902 .enable_tri_buf = true,
903 .use_max_lb = true
904 };
905
906 enum dcn20_clk_src_array_id {
907 DCN20_CLK_SRC_PLL0,
908 DCN20_CLK_SRC_PLL1,
909 DCN20_CLK_SRC_PLL2,
910 DCN20_CLK_SRC_PLL3,
911 DCN20_CLK_SRC_PLL4,
912 DCN20_CLK_SRC_TOTAL_DCN21
913 };
914
dcn21_resource_destruct(struct dcn21_resource_pool * pool)915 static void dcn21_resource_destruct(struct dcn21_resource_pool *pool)
916 {
917 unsigned int i;
918
919 for (i = 0; i < pool->base.stream_enc_count; i++) {
920 if (pool->base.stream_enc[i] != NULL) {
921 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
922 pool->base.stream_enc[i] = NULL;
923 }
924 }
925
926 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
927 if (pool->base.dscs[i] != NULL)
928 dcn20_dsc_destroy(&pool->base.dscs[i]);
929 }
930
931 if (pool->base.mpc != NULL) {
932 kfree(TO_DCN20_MPC(pool->base.mpc));
933 pool->base.mpc = NULL;
934 }
935 if (pool->base.hubbub != NULL) {
936 kfree(pool->base.hubbub);
937 pool->base.hubbub = NULL;
938 }
939 for (i = 0; i < pool->base.pipe_count; i++) {
940 if (pool->base.dpps[i] != NULL)
941 dcn20_dpp_destroy(&pool->base.dpps[i]);
942
943 if (pool->base.ipps[i] != NULL)
944 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
945
946 if (pool->base.hubps[i] != NULL) {
947 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
948 pool->base.hubps[i] = NULL;
949 }
950
951 if (pool->base.irqs != NULL) {
952 dal_irq_service_destroy(&pool->base.irqs);
953 }
954 }
955
956 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
957 if (pool->base.engines[i] != NULL)
958 dce110_engine_destroy(&pool->base.engines[i]);
959 if (pool->base.hw_i2cs[i] != NULL) {
960 kfree(pool->base.hw_i2cs[i]);
961 pool->base.hw_i2cs[i] = NULL;
962 }
963 if (pool->base.sw_i2cs[i] != NULL) {
964 kfree(pool->base.sw_i2cs[i]);
965 pool->base.sw_i2cs[i] = NULL;
966 }
967 }
968
969 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
970 if (pool->base.opps[i] != NULL)
971 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
972 }
973
974 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
975 if (pool->base.timing_generators[i] != NULL) {
976 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
977 pool->base.timing_generators[i] = NULL;
978 }
979 }
980
981 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
982 if (pool->base.dwbc[i] != NULL) {
983 kfree(TO_DCN20_DWBC(pool->base.dwbc[i]));
984 pool->base.dwbc[i] = NULL;
985 }
986 if (pool->base.mcif_wb[i] != NULL) {
987 kfree(TO_DCN20_MMHUBBUB(pool->base.mcif_wb[i]));
988 pool->base.mcif_wb[i] = NULL;
989 }
990 }
991
992 for (i = 0; i < pool->base.audio_count; i++) {
993 if (pool->base.audios[i])
994 dce_aud_destroy(&pool->base.audios[i]);
995 }
996
997 for (i = 0; i < pool->base.clk_src_count; i++) {
998 if (pool->base.clock_sources[i] != NULL) {
999 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1000 pool->base.clock_sources[i] = NULL;
1001 }
1002 }
1003
1004 if (pool->base.dp_clock_source != NULL) {
1005 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1006 pool->base.dp_clock_source = NULL;
1007 }
1008
1009 if (pool->base.abm != NULL) {
1010 if (pool->base.abm->ctx->dc->config.disable_dmcu)
1011 dmub_abm_destroy(&pool->base.abm);
1012 else
1013 dce_abm_destroy(&pool->base.abm);
1014 }
1015
1016 if (pool->base.dmcu != NULL)
1017 dce_dmcu_destroy(&pool->base.dmcu);
1018
1019 if (pool->base.psr != NULL)
1020 dmub_psr_destroy(&pool->base.psr);
1021
1022 if (pool->base.dccg != NULL)
1023 dcn_dccg_destroy(&pool->base.dccg);
1024
1025 if (pool->base.pp_smu != NULL)
1026 dcn21_pp_smu_destroy(&pool->base.pp_smu);
1027 }
1028
1029
calculate_wm_set_for_vlevel(int vlevel,struct wm_range_table_entry * table_entry,struct dcn_watermarks * wm_set,struct display_mode_lib * dml,display_e2e_pipe_params_st * pipes,int pipe_cnt)1030 static void calculate_wm_set_for_vlevel(
1031 int vlevel,
1032 struct wm_range_table_entry *table_entry,
1033 struct dcn_watermarks *wm_set,
1034 struct display_mode_lib *dml,
1035 display_e2e_pipe_params_st *pipes,
1036 int pipe_cnt)
1037 {
1038 double dram_clock_change_latency_cached = dml->soc.dram_clock_change_latency_us;
1039
1040 ASSERT(vlevel < dml->soc.num_states);
1041 /* only pipe 0 is read for voltage and dcf/soc clocks */
1042 pipes[0].clks_cfg.voltage = vlevel;
1043 pipes[0].clks_cfg.dcfclk_mhz = dml->soc.clock_limits[vlevel].dcfclk_mhz;
1044 pipes[0].clks_cfg.socclk_mhz = dml->soc.clock_limits[vlevel].socclk_mhz;
1045
1046 dml->soc.dram_clock_change_latency_us = table_entry->pstate_latency_us;
1047 dml->soc.sr_exit_time_us = table_entry->sr_exit_time_us;
1048 dml->soc.sr_enter_plus_exit_time_us = table_entry->sr_enter_plus_exit_time_us;
1049
1050 wm_set->urgent_ns = get_wm_urgent(dml, pipes, pipe_cnt) * 1000;
1051 wm_set->cstate_pstate.cstate_enter_plus_exit_ns = get_wm_stutter_enter_exit(dml, pipes, pipe_cnt) * 1000;
1052 wm_set->cstate_pstate.cstate_exit_ns = get_wm_stutter_exit(dml, pipes, pipe_cnt) * 1000;
1053 wm_set->cstate_pstate.pstate_change_ns = get_wm_dram_clock_change(dml, pipes, pipe_cnt) * 1000;
1054 wm_set->pte_meta_urgent_ns = get_wm_memory_trip(dml, pipes, pipe_cnt) * 1000;
1055 wm_set->frac_urg_bw_nom = get_fraction_of_urgent_bandwidth(dml, pipes, pipe_cnt) * 1000;
1056 wm_set->frac_urg_bw_flip = get_fraction_of_urgent_bandwidth_imm_flip(dml, pipes, pipe_cnt) * 1000;
1057 wm_set->urgent_latency_ns = get_urgent_latency(dml, pipes, pipe_cnt) * 1000;
1058 dml->soc.dram_clock_change_latency_us = dram_clock_change_latency_cached;
1059
1060 }
1061
patch_bounding_box(struct dc * dc,struct _vcs_dpi_soc_bounding_box_st * bb)1062 static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
1063 {
1064 int i;
1065
1066 if (dc->bb_overrides.sr_exit_time_ns) {
1067 for (i = 0; i < WM_SET_COUNT; i++) {
1068 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
1069 dc->bb_overrides.sr_exit_time_ns / 1000.0;
1070 }
1071 }
1072
1073 if (dc->bb_overrides.sr_enter_plus_exit_time_ns) {
1074 for (i = 0; i < WM_SET_COUNT; i++) {
1075 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us =
1076 dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;
1077 }
1078 }
1079
1080 if (dc->bb_overrides.urgent_latency_ns) {
1081 bb->urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;
1082 }
1083
1084 if (dc->bb_overrides.dram_clock_change_latency_ns) {
1085 for (i = 0; i < WM_SET_COUNT; i++) {
1086 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us =
1087 dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
1088 }
1089 }
1090 }
1091
dcn21_calculate_wm(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * out_pipe_cnt,int * pipe_split_from,int vlevel_req,bool fast_validate)1092 void dcn21_calculate_wm(
1093 struct dc *dc, struct dc_state *context,
1094 display_e2e_pipe_params_st *pipes,
1095 int *out_pipe_cnt,
1096 int *pipe_split_from,
1097 int vlevel_req,
1098 bool fast_validate)
1099 {
1100 int pipe_cnt, i, pipe_idx;
1101 int vlevel, vlevel_max;
1102 struct wm_range_table_entry *table_entry;
1103 struct clk_bw_params *bw_params = dc->clk_mgr->bw_params;
1104
1105 ASSERT(bw_params);
1106
1107 patch_bounding_box(dc, &context->bw_ctx.dml.soc);
1108
1109 for (i = 0, pipe_idx = 0, pipe_cnt = 0; i < dc->res_pool->pipe_count; i++) {
1110 if (!context->res_ctx.pipe_ctx[i].stream)
1111 continue;
1112
1113 pipes[pipe_cnt].clks_cfg.refclk_mhz = dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000.0;
1114 pipes[pipe_cnt].clks_cfg.dispclk_mhz = context->bw_ctx.dml.vba.RequiredDISPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb];
1115
1116 if (pipe_split_from[i] < 0) {
1117 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1118 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx];
1119 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_idx] == pipe_idx)
1120 pipes[pipe_cnt].pipe.dest.odm_combine =
1121 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_idx];
1122 else
1123 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1124 pipe_idx++;
1125 } else {
1126 pipes[pipe_cnt].clks_cfg.dppclk_mhz =
1127 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel_req][context->bw_ctx.dml.vba.maxMpcComb][pipe_split_from[i]];
1128 if (context->bw_ctx.dml.vba.BlendingAndTiming[pipe_split_from[i]] == pipe_split_from[i])
1129 pipes[pipe_cnt].pipe.dest.odm_combine =
1130 context->bw_ctx.dml.vba.ODMCombineEnablePerState[vlevel_req][pipe_split_from[i]];
1131 else
1132 pipes[pipe_cnt].pipe.dest.odm_combine = 0;
1133 }
1134 pipe_cnt++;
1135 }
1136
1137 if (pipe_cnt != pipe_idx) {
1138 if (dc->res_pool->funcs->populate_dml_pipes)
1139 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc,
1140 context, pipes, fast_validate);
1141 else
1142 pipe_cnt = dcn21_populate_dml_pipes_from_context(dc,
1143 context, pipes, fast_validate);
1144 }
1145
1146 *out_pipe_cnt = pipe_cnt;
1147
1148 vlevel_max = bw_params->clk_table.num_entries - 1;
1149
1150
1151 /* WM Set D */
1152 table_entry = &bw_params->wm_table.entries[WM_D];
1153 if (table_entry->wm_type == WM_TYPE_RETRAINING)
1154 vlevel = 0;
1155 else
1156 vlevel = vlevel_max;
1157 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.d,
1158 &context->bw_ctx.dml, pipes, pipe_cnt);
1159 /* WM Set C */
1160 table_entry = &bw_params->wm_table.entries[WM_C];
1161 vlevel = MIN(MAX(vlevel_req, 3), vlevel_max);
1162 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.c,
1163 &context->bw_ctx.dml, pipes, pipe_cnt);
1164 /* WM Set B */
1165 table_entry = &bw_params->wm_table.entries[WM_B];
1166 vlevel = MIN(MAX(vlevel_req, 2), vlevel_max);
1167 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.b,
1168 &context->bw_ctx.dml, pipes, pipe_cnt);
1169
1170 /* WM Set A */
1171 table_entry = &bw_params->wm_table.entries[WM_A];
1172 vlevel = MIN(vlevel_req, vlevel_max);
1173 calculate_wm_set_for_vlevel(vlevel, table_entry, &context->bw_ctx.bw.dcn.watermarks.a,
1174 &context->bw_ctx.dml, pipes, pipe_cnt);
1175 }
1176
1177
dcn21_fast_validate_bw(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,int * pipe_cnt_out,int * pipe_split_from,int * vlevel_out,bool fast_validate)1178 static bool dcn21_fast_validate_bw(
1179 struct dc *dc,
1180 struct dc_state *context,
1181 display_e2e_pipe_params_st *pipes,
1182 int *pipe_cnt_out,
1183 int *pipe_split_from,
1184 int *vlevel_out,
1185 bool fast_validate)
1186 {
1187 bool out = false;
1188 int split[MAX_PIPES] = { 0 };
1189 int pipe_cnt, i, pipe_idx, vlevel;
1190
1191 ASSERT(pipes);
1192 if (!pipes)
1193 return false;
1194
1195 dcn20_merge_pipes_for_validate(dc, context);
1196
1197 pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate);
1198
1199 *pipe_cnt_out = pipe_cnt;
1200
1201 if (!pipe_cnt) {
1202 out = true;
1203 goto validate_out;
1204 }
1205 /*
1206 * DML favors voltage over p-state, but we're more interested in
1207 * supporting p-state over voltage. We can't support p-state in
1208 * prefetch mode > 0 so try capping the prefetch mode to start.
1209 */
1210 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1211 dm_allow_self_refresh_and_mclk_switch;
1212 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1213
1214 if (vlevel > context->bw_ctx.dml.soc.num_states) {
1215 /*
1216 * If mode is unsupported or there's still no p-state support then
1217 * fall back to favoring voltage.
1218 *
1219 * We don't actually support prefetch mode 2, so require that we
1220 * at least support prefetch mode 1.
1221 */
1222 context->bw_ctx.dml.soc.allow_dram_self_refresh_or_dram_clock_change_in_vblank =
1223 dm_allow_self_refresh;
1224 vlevel = dml_get_voltage_level(&context->bw_ctx.dml, pipes, pipe_cnt);
1225 if (vlevel > context->bw_ctx.dml.soc.num_states)
1226 goto validate_fail;
1227 }
1228
1229 vlevel = dcn20_validate_apply_pipe_split_flags(dc, context, vlevel, split, NULL);
1230
1231 for (i = 0, pipe_idx = 0; i < dc->res_pool->pipe_count; i++) {
1232 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1233 struct pipe_ctx *mpo_pipe = pipe->bottom_pipe;
1234 struct vba_vars_st *vba = &context->bw_ctx.dml.vba;
1235
1236 if (!pipe->stream)
1237 continue;
1238
1239 /* We only support full screen mpo with ODM */
1240 if (vba->ODMCombineEnabled[vba->pipe_plane[pipe_idx]] != dm_odm_combine_mode_disabled
1241 && pipe->plane_state && mpo_pipe
1242 && memcmp(&mpo_pipe->plane_res.scl_data.recout,
1243 &pipe->plane_res.scl_data.recout,
1244 sizeof(struct rect)) != 0) {
1245 ASSERT(mpo_pipe->plane_state != pipe->plane_state);
1246 goto validate_fail;
1247 }
1248 pipe_idx++;
1249 }
1250
1251 /*initialize pipe_just_split_from to invalid idx*/
1252 for (i = 0; i < MAX_PIPES; i++)
1253 pipe_split_from[i] = -1;
1254
1255 for (i = 0, pipe_idx = -1; i < dc->res_pool->pipe_count; i++) {
1256 struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
1257 struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
1258
1259 if (!pipe->stream || pipe_split_from[i] >= 0)
1260 continue;
1261
1262 pipe_idx++;
1263
1264 if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1265 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1266 ASSERT(hsplit_pipe);
1267 if (!dcn20_split_stream_for_odm(
1268 dc, &context->res_ctx,
1269 pipe, hsplit_pipe))
1270 goto validate_fail;
1271 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1272 dcn20_build_mapped_resource(dc, context, pipe->stream);
1273 }
1274
1275 if (!pipe->plane_state)
1276 continue;
1277 /* Skip 2nd half of already split pipe */
1278 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state)
1279 continue;
1280
1281 if (split[i] == 2) {
1282 if (!hsplit_pipe || hsplit_pipe->plane_state != pipe->plane_state) {
1283 /* pipe not split previously needs split */
1284 hsplit_pipe = dcn20_find_secondary_pipe(dc, &context->res_ctx, dc->res_pool, pipe);
1285 ASSERT(hsplit_pipe);
1286 if (!hsplit_pipe) {
1287 context->bw_ctx.dml.vba.RequiredDPPCLK[vlevel][context->bw_ctx.dml.vba.maxMpcComb][pipe_idx] *= 2;
1288 continue;
1289 }
1290 if (context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) {
1291 if (!dcn20_split_stream_for_odm(
1292 dc, &context->res_ctx,
1293 pipe, hsplit_pipe))
1294 goto validate_fail;
1295 dcn20_build_mapped_resource(dc, context, pipe->stream);
1296 } else {
1297 dcn20_split_stream_for_mpc(
1298 &context->res_ctx, dc->res_pool,
1299 pipe, hsplit_pipe);
1300 resource_build_scaling_params(pipe);
1301 resource_build_scaling_params(hsplit_pipe);
1302 }
1303 pipe_split_from[hsplit_pipe->pipe_idx] = pipe_idx;
1304 }
1305 } else if (hsplit_pipe && hsplit_pipe->plane_state == pipe->plane_state) {
1306 /* merge should already have been done */
1307 ASSERT(0);
1308 }
1309 }
1310 /* Actual dsc count per stream dsc validation*/
1311 if (!dcn20_validate_dsc(dc, context)) {
1312 context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] =
1313 DML_FAIL_DSC_VALIDATION_FAILURE;
1314 goto validate_fail;
1315 }
1316
1317 *vlevel_out = vlevel;
1318
1319 out = true;
1320 goto validate_out;
1321
1322 validate_fail:
1323 out = false;
1324
1325 validate_out:
1326 return out;
1327 }
1328
dcn21_validate_bandwidth_fp(struct dc * dc,struct dc_state * context,bool fast_validate)1329 static noinline bool dcn21_validate_bandwidth_fp(struct dc *dc,
1330 struct dc_state *context, bool fast_validate)
1331 {
1332 bool out = false;
1333
1334 BW_VAL_TRACE_SETUP();
1335
1336 int vlevel = 0;
1337 int pipe_split_from[MAX_PIPES];
1338 int pipe_cnt = 0;
1339 display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
1340 DC_LOGGER_INIT(dc->ctx->logger);
1341
1342 BW_VAL_TRACE_COUNT();
1343
1344 /*Unsafe due to current pipe merge and split logic*/
1345 ASSERT(context != dc->current_state);
1346
1347 out = dcn21_fast_validate_bw(dc, context, pipes, &pipe_cnt, pipe_split_from, &vlevel, fast_validate);
1348
1349 if (pipe_cnt == 0)
1350 goto validate_out;
1351
1352 if (!out)
1353 goto validate_fail;
1354
1355 BW_VAL_TRACE_END_VOLTAGE_LEVEL();
1356
1357 if (fast_validate) {
1358 BW_VAL_TRACE_SKIP(fast);
1359 goto validate_out;
1360 }
1361
1362 dcn21_calculate_wm(dc, context, pipes, &pipe_cnt, pipe_split_from, vlevel, fast_validate);
1363 dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
1364
1365 BW_VAL_TRACE_END_WATERMARKS();
1366
1367 goto validate_out;
1368
1369 validate_fail:
1370 DC_LOG_WARNING("Mode Validation Warning: %s failed validation.\n",
1371 dml_get_status_message(context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states]));
1372
1373 BW_VAL_TRACE_SKIP(fail);
1374 out = false;
1375
1376 validate_out:
1377 kfree(pipes);
1378
1379 BW_VAL_TRACE_FINISH();
1380
1381 return out;
1382 }
1383
1384 /*
1385 * Some of the functions further below use the FPU, so we need to wrap this
1386 * with DC_FP_START()/DC_FP_END(). Use the same approach as for
1387 * dcn20_validate_bandwidth in dcn20_resource.c.
1388 */
dcn21_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1389 bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
1390 bool fast_validate)
1391 {
1392 bool voltage_supported;
1393 DC_FP_START();
1394 voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
1395 DC_FP_END();
1396 return voltage_supported;
1397 }
1398
dcn21_destroy_resource_pool(struct resource_pool ** pool)1399 static void dcn21_destroy_resource_pool(struct resource_pool **pool)
1400 {
1401 struct dcn21_resource_pool *dcn21_pool = TO_DCN21_RES_POOL(*pool);
1402
1403 dcn21_resource_destruct(dcn21_pool);
1404 kfree(dcn21_pool);
1405 *pool = NULL;
1406 }
1407
dcn21_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)1408 static struct clock_source *dcn21_clock_source_create(
1409 struct dc_context *ctx,
1410 struct dc_bios *bios,
1411 enum clock_source_id id,
1412 const struct dce110_clk_src_regs *regs,
1413 bool dp_clk_src)
1414 {
1415 struct dce110_clk_src *clk_src =
1416 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
1417
1418 if (!clk_src)
1419 return NULL;
1420
1421 if (dcn20_clk_src_construct(clk_src, ctx, bios, id,
1422 regs, &cs_shift, &cs_mask)) {
1423 clk_src->base.dp_clk_src = dp_clk_src;
1424 return &clk_src->base;
1425 }
1426
1427 BREAK_TO_DEBUGGER();
1428 return NULL;
1429 }
1430
dcn21_hubp_create(struct dc_context * ctx,uint32_t inst)1431 static struct hubp *dcn21_hubp_create(
1432 struct dc_context *ctx,
1433 uint32_t inst)
1434 {
1435 struct dcn21_hubp *hubp21 =
1436 kzalloc(sizeof(struct dcn21_hubp), GFP_KERNEL);
1437
1438 if (!hubp21)
1439 return NULL;
1440
1441 if (hubp21_construct(hubp21, ctx, inst,
1442 &hubp_regs[inst], &hubp_shift, &hubp_mask))
1443 return &hubp21->base;
1444
1445 BREAK_TO_DEBUGGER();
1446 kfree(hubp21);
1447 return NULL;
1448 }
1449
dcn21_hubbub_create(struct dc_context * ctx)1450 static struct hubbub *dcn21_hubbub_create(struct dc_context *ctx)
1451 {
1452 int i;
1453
1454 struct dcn20_hubbub *hubbub = kzalloc(sizeof(struct dcn20_hubbub),
1455 GFP_KERNEL);
1456
1457 if (!hubbub)
1458 return NULL;
1459
1460 hubbub21_construct(hubbub, ctx,
1461 &hubbub_reg,
1462 &hubbub_shift,
1463 &hubbub_mask);
1464
1465 for (i = 0; i < res_cap_rn.num_vmid; i++) {
1466 struct dcn20_vmid *vmid = &hubbub->vmid[i];
1467
1468 vmid->ctx = ctx;
1469
1470 vmid->regs = &vmid_regs[i];
1471 vmid->shifts = &vmid_shifts;
1472 vmid->masks = &vmid_masks;
1473 }
1474 hubbub->num_vmid = res_cap_rn.num_vmid;
1475
1476 return &hubbub->base;
1477 }
1478
dcn21_opp_create(struct dc_context * ctx,uint32_t inst)1479 struct output_pixel_processor *dcn21_opp_create(
1480 struct dc_context *ctx, uint32_t inst)
1481 {
1482 struct dcn20_opp *opp =
1483 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
1484
1485 if (!opp) {
1486 BREAK_TO_DEBUGGER();
1487 return NULL;
1488 }
1489
1490 dcn20_opp_construct(opp, ctx, inst,
1491 &opp_regs[inst], &opp_shift, &opp_mask);
1492 return &opp->base;
1493 }
1494
dcn21_timing_generator_create(struct dc_context * ctx,uint32_t instance)1495 struct timing_generator *dcn21_timing_generator_create(
1496 struct dc_context *ctx,
1497 uint32_t instance)
1498 {
1499 struct optc *tgn10 =
1500 kzalloc(sizeof(struct optc), GFP_KERNEL);
1501
1502 if (!tgn10)
1503 return NULL;
1504
1505 tgn10->base.inst = instance;
1506 tgn10->base.ctx = ctx;
1507
1508 tgn10->tg_regs = &tg_regs[instance];
1509 tgn10->tg_shift = &tg_shift;
1510 tgn10->tg_mask = &tg_mask;
1511
1512 dcn20_timing_generator_init(tgn10);
1513
1514 return &tgn10->base;
1515 }
1516
dcn21_mpc_create(struct dc_context * ctx)1517 struct mpc *dcn21_mpc_create(struct dc_context *ctx)
1518 {
1519 struct dcn20_mpc *mpc20 = kzalloc(sizeof(struct dcn20_mpc),
1520 GFP_KERNEL);
1521
1522 if (!mpc20)
1523 return NULL;
1524
1525 dcn20_mpc_construct(mpc20, ctx,
1526 &mpc_regs,
1527 &mpc_shift,
1528 &mpc_mask,
1529 6);
1530
1531 return &mpc20->base;
1532 }
1533
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1534 static void read_dce_straps(
1535 struct dc_context *ctx,
1536 struct resource_straps *straps)
1537 {
1538 generic_reg_get(ctx, mmDC_PINSTRAPS + BASE(mmDC_PINSTRAPS_BASE_IDX),
1539 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1540
1541 }
1542
1543
dcn21_dsc_create(struct dc_context * ctx,uint32_t inst)1544 struct display_stream_compressor *dcn21_dsc_create(
1545 struct dc_context *ctx, uint32_t inst)
1546 {
1547 struct dcn20_dsc *dsc =
1548 kzalloc(sizeof(struct dcn20_dsc), GFP_KERNEL);
1549
1550 if (!dsc) {
1551 BREAK_TO_DEBUGGER();
1552 return NULL;
1553 }
1554
1555 dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1556 return &dsc->base;
1557 }
1558
construct_low_pstate_lvl(struct clk_limit_table * clk_table,unsigned int high_voltage_lvl)1559 static struct _vcs_dpi_voltage_scaling_st construct_low_pstate_lvl(struct clk_limit_table *clk_table, unsigned int high_voltage_lvl)
1560 {
1561 struct _vcs_dpi_voltage_scaling_st low_pstate_lvl;
1562 int i;
1563
1564 low_pstate_lvl.state = 1;
1565 low_pstate_lvl.dcfclk_mhz = clk_table->entries[0].dcfclk_mhz;
1566 low_pstate_lvl.fabricclk_mhz = clk_table->entries[0].fclk_mhz;
1567 low_pstate_lvl.socclk_mhz = clk_table->entries[0].socclk_mhz;
1568 low_pstate_lvl.dram_speed_mts = clk_table->entries[0].memclk_mhz * 2;
1569
1570 low_pstate_lvl.dispclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dispclk_mhz;
1571 low_pstate_lvl.dppclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dppclk_mhz;
1572 low_pstate_lvl.dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[high_voltage_lvl].dram_bw_per_chan_gbps;
1573 low_pstate_lvl.dscclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dscclk_mhz;
1574 low_pstate_lvl.dtbclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].dtbclk_mhz;
1575 low_pstate_lvl.phyclk_d18_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_d18_mhz;
1576 low_pstate_lvl.phyclk_mhz = dcn2_1_soc.clock_limits[high_voltage_lvl].phyclk_mhz;
1577
1578 for (i = clk_table->num_entries; i > 1; i--)
1579 clk_table->entries[i] = clk_table->entries[i-1];
1580 clk_table->entries[1] = clk_table->entries[0];
1581 clk_table->num_entries++;
1582
1583 return low_pstate_lvl;
1584 }
1585
update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1586 static void update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1587 {
1588 struct dcn21_resource_pool *pool = TO_DCN21_RES_POOL(dc->res_pool);
1589 struct clk_limit_table *clk_table = &bw_params->clk_table;
1590 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES];
1591 unsigned int i, closest_clk_lvl = 0, k = 0;
1592 int j;
1593
1594 dcn2_1_ip.max_num_otg = pool->base.res_cap->num_timing_generator;
1595 dcn2_1_ip.max_num_dpp = pool->base.pipe_count;
1596 dcn2_1_soc.num_chans = bw_params->num_channels;
1597
1598 ASSERT(clk_table->num_entries);
1599 /* Copy dcn2_1_soc.clock_limits to clock_limits to avoid copying over null states later */
1600 for (i = 0; i < dcn2_1_soc.num_states + 1; i++) {
1601 clock_limits[i] = dcn2_1_soc.clock_limits[i];
1602 }
1603
1604 for (i = 0; i < clk_table->num_entries; i++) {
1605 /* loop backwards*/
1606 for (closest_clk_lvl = 0, j = dcn2_1_soc.num_states - 1; j >= 0; j--) {
1607 if ((unsigned int) dcn2_1_soc.clock_limits[j].dcfclk_mhz <= clk_table->entries[i].dcfclk_mhz) {
1608 closest_clk_lvl = j;
1609 break;
1610 }
1611 }
1612
1613 /* clk_table[1] is reserved for min DF PState. skip here to fill in later. */
1614 if (i == 1)
1615 k++;
1616
1617 clock_limits[k].state = k;
1618 clock_limits[k].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz;
1619 clock_limits[k].fabricclk_mhz = clk_table->entries[i].fclk_mhz;
1620 clock_limits[k].socclk_mhz = clk_table->entries[i].socclk_mhz;
1621 clock_limits[k].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2;
1622
1623 clock_limits[k].dispclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dispclk_mhz;
1624 clock_limits[k].dppclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dppclk_mhz;
1625 clock_limits[k].dram_bw_per_chan_gbps = dcn2_1_soc.clock_limits[closest_clk_lvl].dram_bw_per_chan_gbps;
1626 clock_limits[k].dscclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dscclk_mhz;
1627 clock_limits[k].dtbclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].dtbclk_mhz;
1628 clock_limits[k].phyclk_d18_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_d18_mhz;
1629 clock_limits[k].phyclk_mhz = dcn2_1_soc.clock_limits[closest_clk_lvl].phyclk_mhz;
1630
1631 k++;
1632 }
1633 for (i = 0; i < clk_table->num_entries + 1; i++)
1634 dcn2_1_soc.clock_limits[i] = clock_limits[i];
1635 if (clk_table->num_entries) {
1636 dcn2_1_soc.num_states = clk_table->num_entries + 1;
1637 /* fill in min DF PState */
1638 dcn2_1_soc.clock_limits[1] = construct_low_pstate_lvl(clk_table, closest_clk_lvl);
1639 /* duplicate last level */
1640 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states] = dcn2_1_soc.clock_limits[dcn2_1_soc.num_states - 1];
1641 dcn2_1_soc.clock_limits[dcn2_1_soc.num_states].state = dcn2_1_soc.num_states;
1642 }
1643
1644 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
1645 }
1646
dcn21_pp_smu_create(struct dc_context * ctx)1647 static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx)
1648 {
1649 struct pp_smu_funcs *pp_smu = kzalloc(sizeof(*pp_smu), GFP_KERNEL);
1650
1651 if (!pp_smu)
1652 return pp_smu;
1653
1654 dm_pp_get_funcs(ctx, pp_smu);
1655
1656 if (pp_smu->ctx.ver != PP_SMU_VER_RN)
1657 pp_smu = memset(pp_smu, 0, sizeof(struct pp_smu_funcs));
1658
1659
1660 return pp_smu;
1661 }
1662
dcn21_pp_smu_destroy(struct pp_smu_funcs ** pp_smu)1663 static void dcn21_pp_smu_destroy(struct pp_smu_funcs **pp_smu)
1664 {
1665 if (pp_smu && *pp_smu) {
1666 kfree(*pp_smu);
1667 *pp_smu = NULL;
1668 }
1669 }
1670
dcn21_create_audio(struct dc_context * ctx,unsigned int inst)1671 static struct audio *dcn21_create_audio(
1672 struct dc_context *ctx, unsigned int inst)
1673 {
1674 return dce_audio_create(ctx, inst,
1675 &audio_regs[inst], &audio_shift, &audio_mask);
1676 }
1677
1678 static struct dc_cap_funcs cap_funcs = {
1679 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1680 };
1681
dcn21_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1682 struct stream_encoder *dcn21_stream_encoder_create(
1683 enum engine_id eng_id,
1684 struct dc_context *ctx)
1685 {
1686 struct dcn10_stream_encoder *enc1 =
1687 kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1688
1689 if (!enc1)
1690 return NULL;
1691
1692 dcn20_stream_encoder_construct(enc1, ctx, ctx->dc_bios, eng_id,
1693 &stream_enc_regs[eng_id],
1694 &se_shift, &se_mask);
1695
1696 return &enc1->base;
1697 }
1698
1699 static const struct dce_hwseq_registers hwseq_reg = {
1700 HWSEQ_DCN21_REG_LIST()
1701 };
1702
1703 static const struct dce_hwseq_shift hwseq_shift = {
1704 HWSEQ_DCN21_MASK_SH_LIST(__SHIFT)
1705 };
1706
1707 static const struct dce_hwseq_mask hwseq_mask = {
1708 HWSEQ_DCN21_MASK_SH_LIST(_MASK)
1709 };
1710
dcn21_hwseq_create(struct dc_context * ctx)1711 static struct dce_hwseq *dcn21_hwseq_create(
1712 struct dc_context *ctx)
1713 {
1714 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1715
1716 if (hws) {
1717 hws->ctx = ctx;
1718 hws->regs = &hwseq_reg;
1719 hws->shifts = &hwseq_shift;
1720 hws->masks = &hwseq_mask;
1721 hws->wa.DEGVIDCN21 = true;
1722 hws->wa.disallow_self_refresh_during_multi_plane_transition = true;
1723 }
1724 return hws;
1725 }
1726
1727 static const struct resource_create_funcs res_create_funcs = {
1728 .read_dce_straps = read_dce_straps,
1729 .create_audio = dcn21_create_audio,
1730 .create_stream_encoder = dcn21_stream_encoder_create,
1731 .create_hwseq = dcn21_hwseq_create,
1732 };
1733
1734 static const struct resource_create_funcs res_create_maximus_funcs = {
1735 .read_dce_straps = NULL,
1736 .create_audio = NULL,
1737 .create_stream_encoder = NULL,
1738 .create_hwseq = dcn21_hwseq_create,
1739 };
1740
1741 static const struct encoder_feature_support link_enc_feature = {
1742 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1743 .max_hdmi_pixel_clock = 600000,
1744 .hdmi_ycbcr420_supported = true,
1745 .dp_ycbcr420_supported = true,
1746 .fec_supported = true,
1747 .flags.bits.IS_HBR2_CAPABLE = true,
1748 .flags.bits.IS_HBR3_CAPABLE = true,
1749 .flags.bits.IS_TPS3_CAPABLE = true,
1750 .flags.bits.IS_TPS4_CAPABLE = true
1751 };
1752
1753
1754 #define link_regs(id, phyid)\
1755 [id] = {\
1756 LE_DCN2_REG_LIST(id), \
1757 UNIPHY_DCN2_REG_LIST(phyid), \
1758 DPCS_DCN21_REG_LIST(id), \
1759 SRI(DP_DPHY_INTERNAL_CTRL, DP, id) \
1760 }
1761
1762 static const struct dcn10_link_enc_registers link_enc_regs[] = {
1763 link_regs(0, A),
1764 link_regs(1, B),
1765 link_regs(2, C),
1766 link_regs(3, D),
1767 link_regs(4, E),
1768 };
1769
1770 static const struct dce_panel_cntl_registers panel_cntl_regs[] = {
1771 { DCN_PANEL_CNTL_REG_LIST() }
1772 };
1773
1774 static const struct dce_panel_cntl_shift panel_cntl_shift = {
1775 DCE_PANEL_CNTL_MASK_SH_LIST(__SHIFT)
1776 };
1777
1778 static const struct dce_panel_cntl_mask panel_cntl_mask = {
1779 DCE_PANEL_CNTL_MASK_SH_LIST(_MASK)
1780 };
1781
1782 #define aux_regs(id)\
1783 [id] = {\
1784 DCN2_AUX_REG_LIST(id)\
1785 }
1786
1787 static const struct dcn10_link_enc_aux_registers link_enc_aux_regs[] = {
1788 aux_regs(0),
1789 aux_regs(1),
1790 aux_regs(2),
1791 aux_regs(3),
1792 aux_regs(4)
1793 };
1794
1795 #define hpd_regs(id)\
1796 [id] = {\
1797 HPD_REG_LIST(id)\
1798 }
1799
1800 static const struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[] = {
1801 hpd_regs(0),
1802 hpd_regs(1),
1803 hpd_regs(2),
1804 hpd_regs(3),
1805 hpd_regs(4)
1806 };
1807
1808 static const struct dcn10_link_enc_shift le_shift = {
1809 LINK_ENCODER_MASK_SH_LIST_DCN20(__SHIFT),\
1810 DPCS_DCN21_MASK_SH_LIST(__SHIFT)
1811 };
1812
1813 static const struct dcn10_link_enc_mask le_mask = {
1814 LINK_ENCODER_MASK_SH_LIST_DCN20(_MASK),\
1815 DPCS_DCN21_MASK_SH_LIST(_MASK)
1816 };
1817
map_transmitter_id_to_phy_instance(enum transmitter transmitter)1818 static int map_transmitter_id_to_phy_instance(
1819 enum transmitter transmitter)
1820 {
1821 switch (transmitter) {
1822 case TRANSMITTER_UNIPHY_A:
1823 return 0;
1824 break;
1825 case TRANSMITTER_UNIPHY_B:
1826 return 1;
1827 break;
1828 case TRANSMITTER_UNIPHY_C:
1829 return 2;
1830 break;
1831 case TRANSMITTER_UNIPHY_D:
1832 return 3;
1833 break;
1834 case TRANSMITTER_UNIPHY_E:
1835 return 4;
1836 break;
1837 default:
1838 ASSERT(0);
1839 return 0;
1840 }
1841 }
1842
dcn21_link_encoder_create(const struct encoder_init_data * enc_init_data)1843 static struct link_encoder *dcn21_link_encoder_create(
1844 const struct encoder_init_data *enc_init_data)
1845 {
1846 struct dcn21_link_encoder *enc21 =
1847 kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL);
1848 int link_regs_id;
1849
1850 if (!enc21)
1851 return NULL;
1852
1853 link_regs_id =
1854 map_transmitter_id_to_phy_instance(enc_init_data->transmitter);
1855
1856 dcn21_link_encoder_construct(enc21,
1857 enc_init_data,
1858 &link_enc_feature,
1859 &link_enc_regs[link_regs_id],
1860 &link_enc_aux_regs[enc_init_data->channel - 1],
1861 &link_enc_hpd_regs[enc_init_data->hpd_source],
1862 &le_shift,
1863 &le_mask);
1864
1865 return &enc21->enc10.base;
1866 }
1867
dcn21_panel_cntl_create(const struct panel_cntl_init_data * init_data)1868 static struct panel_cntl *dcn21_panel_cntl_create(const struct panel_cntl_init_data *init_data)
1869 {
1870 struct dce_panel_cntl *panel_cntl =
1871 kzalloc(sizeof(struct dce_panel_cntl), GFP_KERNEL);
1872
1873 if (!panel_cntl)
1874 return NULL;
1875
1876 dce_panel_cntl_construct(panel_cntl,
1877 init_data,
1878 &panel_cntl_regs[init_data->inst],
1879 &panel_cntl_shift,
1880 &panel_cntl_mask);
1881
1882 return &panel_cntl->base;
1883 }
1884
1885 #define CTX ctx
1886
1887 #define REG(reg_name) \
1888 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
1889
read_pipe_fuses(struct dc_context * ctx)1890 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1891 {
1892 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1893 /* RV1 support max 4 pipes */
1894 value = value & 0xf;
1895 return value;
1896 }
1897
dcn21_populate_dml_pipes_from_context(struct dc * dc,struct dc_state * context,display_e2e_pipe_params_st * pipes,bool fast_validate)1898 static int dcn21_populate_dml_pipes_from_context(
1899 struct dc *dc,
1900 struct dc_state *context,
1901 display_e2e_pipe_params_st *pipes,
1902 bool fast_validate)
1903 {
1904 uint32_t pipe_cnt = dcn20_populate_dml_pipes_from_context(dc, context, pipes, fast_validate);
1905 int i;
1906
1907 for (i = 0; i < pipe_cnt; i++) {
1908
1909 pipes[i].pipe.src.hostvm = dc->res_pool->hubbub->riommu_active;
1910 pipes[i].pipe.src.gpuvm = 1;
1911 }
1912
1913 return pipe_cnt;
1914 }
1915
dcn21_patch_unknown_plane_state(struct dc_plane_state * plane_state)1916 enum dc_status dcn21_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1917 {
1918 enum dc_status result = DC_OK;
1919
1920 if (plane_state->ctx->dc->debug.disable_dcc == DCC_ENABLE) {
1921 plane_state->dcc.enable = 1;
1922 /* align to our worst case block width */
1923 plane_state->dcc.meta_pitch = ((plane_state->src_rect.width + 1023) / 1024) * 1024;
1924 }
1925 result = dcn20_patch_unknown_plane_state(plane_state);
1926 return result;
1927 }
1928
1929 static const struct resource_funcs dcn21_res_pool_funcs = {
1930 .destroy = dcn21_destroy_resource_pool,
1931 .link_enc_create = dcn21_link_encoder_create,
1932 .panel_cntl_create = dcn21_panel_cntl_create,
1933 .validate_bandwidth = dcn21_validate_bandwidth,
1934 .populate_dml_pipes = dcn21_populate_dml_pipes_from_context,
1935 .add_stream_to_ctx = dcn20_add_stream_to_ctx,
1936 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1937 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1938 .acquire_idle_pipe_for_layer = dcn20_acquire_idle_pipe_for_layer,
1939 .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context,
1940 .patch_unknown_plane_state = dcn21_patch_unknown_plane_state,
1941 .set_mcif_arb_params = dcn20_set_mcif_arb_params,
1942 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1943 .update_bw_bounding_box = update_bw_bounding_box
1944 };
1945
dcn21_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn21_resource_pool * pool)1946 static bool dcn21_resource_construct(
1947 uint8_t num_virtual_links,
1948 struct dc *dc,
1949 struct dcn21_resource_pool *pool)
1950 {
1951 int i, j;
1952 struct dc_context *ctx = dc->ctx;
1953 struct irq_service_init_data init_data;
1954 uint32_t pipe_fuses = read_pipe_fuses(ctx);
1955 uint32_t num_pipes;
1956
1957 ctx->dc_bios->regs = &bios_regs;
1958
1959 pool->base.res_cap = &res_cap_rn;
1960 #ifdef DIAGS_BUILD
1961 if (IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment))
1962 //pool->base.res_cap = &res_cap_nv10_FPGA_2pipe_dsc;
1963 pool->base.res_cap = &res_cap_rn_FPGA_4pipe;
1964 #endif
1965
1966 pool->base.funcs = &dcn21_res_pool_funcs;
1967
1968 /*************************************************
1969 * Resource + asic cap harcoding *
1970 *************************************************/
1971 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1972
1973 /* max pipe num for ASIC before check pipe fuses */
1974 pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
1975
1976 dc->caps.max_downscale_ratio = 200;
1977 dc->caps.i2c_speed_in_khz = 100;
1978 dc->caps.i2c_speed_in_khz_hdcp = 5; /*1.4 w/a applied by default*/
1979 dc->caps.max_cursor_size = 256;
1980 dc->caps.min_horizontal_blanking_period = 80;
1981 dc->caps.dmdata_alloc_size = 2048;
1982
1983 dc->caps.max_slave_planes = 1;
1984 dc->caps.max_slave_yuv_planes = 1;
1985 dc->caps.max_slave_rgb_planes = 1;
1986 dc->caps.post_blend_color_processing = true;
1987 dc->caps.force_dp_tps4_for_cp2520 = true;
1988 dc->caps.extended_aux_timeout_support = true;
1989 dc->caps.dmcub_support = true;
1990 dc->caps.is_apu = true;
1991
1992 /* Color pipeline capabilities */
1993 dc->caps.color.dpp.dcn_arch = 1;
1994 dc->caps.color.dpp.input_lut_shared = 0;
1995 dc->caps.color.dpp.icsc = 1;
1996 dc->caps.color.dpp.dgam_ram = 1;
1997 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1998 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1999 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 0;
2000 dc->caps.color.dpp.dgam_rom_caps.pq = 0;
2001 dc->caps.color.dpp.dgam_rom_caps.hlg = 0;
2002 dc->caps.color.dpp.post_csc = 0;
2003 dc->caps.color.dpp.gamma_corr = 0;
2004 dc->caps.color.dpp.dgam_rom_for_yuv = 1;
2005
2006 dc->caps.color.dpp.hw_3d_lut = 1;
2007 dc->caps.color.dpp.ogam_ram = 1;
2008 // no OGAM ROM on DCN2
2009 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
2010 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
2011 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
2012 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
2013 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
2014 dc->caps.color.dpp.ocsc = 0;
2015
2016 dc->caps.color.mpc.gamut_remap = 0;
2017 dc->caps.color.mpc.num_3dluts = 0;
2018 dc->caps.color.mpc.shared_3d_lut = 0;
2019 dc->caps.color.mpc.ogam_ram = 1;
2020 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
2021 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
2022 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
2023 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
2024 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
2025 dc->caps.color.mpc.ocsc = 1;
2026
2027 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
2028 dc->debug = debug_defaults_drv;
2029 else if (dc->ctx->dce_environment == DCE_ENV_FPGA_MAXIMUS) {
2030 pool->base.pipe_count = 4;
2031 dc->debug = debug_defaults_diags;
2032 } else
2033 dc->debug = debug_defaults_diags;
2034
2035 // Init the vm_helper
2036 if (dc->vm_helper)
2037 vm_helper_init(dc->vm_helper, 16);
2038
2039 /*************************************************
2040 * Create resources *
2041 *************************************************/
2042
2043 pool->base.clock_sources[DCN20_CLK_SRC_PLL0] =
2044 dcn21_clock_source_create(ctx, ctx->dc_bios,
2045 CLOCK_SOURCE_COMBO_PHY_PLL0,
2046 &clk_src_regs[0], false);
2047 pool->base.clock_sources[DCN20_CLK_SRC_PLL1] =
2048 dcn21_clock_source_create(ctx, ctx->dc_bios,
2049 CLOCK_SOURCE_COMBO_PHY_PLL1,
2050 &clk_src_regs[1], false);
2051 pool->base.clock_sources[DCN20_CLK_SRC_PLL2] =
2052 dcn21_clock_source_create(ctx, ctx->dc_bios,
2053 CLOCK_SOURCE_COMBO_PHY_PLL2,
2054 &clk_src_regs[2], false);
2055 pool->base.clock_sources[DCN20_CLK_SRC_PLL3] =
2056 dcn21_clock_source_create(ctx, ctx->dc_bios,
2057 CLOCK_SOURCE_COMBO_PHY_PLL3,
2058 &clk_src_regs[3], false);
2059 pool->base.clock_sources[DCN20_CLK_SRC_PLL4] =
2060 dcn21_clock_source_create(ctx, ctx->dc_bios,
2061 CLOCK_SOURCE_COMBO_PHY_PLL4,
2062 &clk_src_regs[4], false);
2063
2064 pool->base.clk_src_count = DCN20_CLK_SRC_TOTAL_DCN21;
2065
2066 /* todo: not reuse phy_pll registers */
2067 pool->base.dp_clock_source =
2068 dcn21_clock_source_create(ctx, ctx->dc_bios,
2069 CLOCK_SOURCE_ID_DP_DTO,
2070 &clk_src_regs[0], true);
2071
2072 for (i = 0; i < pool->base.clk_src_count; i++) {
2073 if (pool->base.clock_sources[i] == NULL) {
2074 dm_error("DC: failed to create clock sources!\n");
2075 BREAK_TO_DEBUGGER();
2076 goto create_fail;
2077 }
2078 }
2079
2080 pool->base.dccg = dccg21_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
2081 if (pool->base.dccg == NULL) {
2082 dm_error("DC: failed to create dccg!\n");
2083 BREAK_TO_DEBUGGER();
2084 goto create_fail;
2085 }
2086
2087 if (!dc->config.disable_dmcu) {
2088 pool->base.dmcu = dcn21_dmcu_create(ctx,
2089 &dmcu_regs,
2090 &dmcu_shift,
2091 &dmcu_mask);
2092 if (pool->base.dmcu == NULL) {
2093 dm_error("DC: failed to create dmcu!\n");
2094 BREAK_TO_DEBUGGER();
2095 goto create_fail;
2096 }
2097
2098 dc->debug.dmub_command_table = false;
2099 }
2100
2101 if (dc->config.disable_dmcu) {
2102 pool->base.psr = dmub_psr_create(ctx);
2103
2104 if (pool->base.psr == NULL) {
2105 dm_error("DC: failed to create psr obj!\n");
2106 BREAK_TO_DEBUGGER();
2107 goto create_fail;
2108 }
2109 }
2110
2111 if (dc->config.disable_dmcu)
2112 pool->base.abm = dmub_abm_create(ctx,
2113 &abm_regs,
2114 &abm_shift,
2115 &abm_mask);
2116 else
2117 pool->base.abm = dce_abm_create(ctx,
2118 &abm_regs,
2119 &abm_shift,
2120 &abm_mask);
2121
2122 pool->base.pp_smu = dcn21_pp_smu_create(ctx);
2123
2124 num_pipes = dcn2_1_ip.max_num_dpp;
2125
2126 for (i = 0; i < dcn2_1_ip.max_num_dpp; i++)
2127 if (pipe_fuses & 1 << i)
2128 num_pipes--;
2129 dcn2_1_ip.max_num_dpp = num_pipes;
2130 dcn2_1_ip.max_num_otg = num_pipes;
2131
2132 dml_init_instance(&dc->dml, &dcn2_1_soc, &dcn2_1_ip, DML_PROJECT_DCN21);
2133
2134 init_data.ctx = dc->ctx;
2135 pool->base.irqs = dal_irq_service_dcn21_create(&init_data);
2136 if (!pool->base.irqs)
2137 goto create_fail;
2138
2139 j = 0;
2140 /* mem input -> ipp -> dpp -> opp -> TG */
2141 for (i = 0; i < pool->base.pipe_count; i++) {
2142 /* if pipe is disabled, skip instance of HW pipe,
2143 * i.e, skip ASIC register instance
2144 */
2145 if ((pipe_fuses & (1 << i)) != 0)
2146 continue;
2147
2148 pool->base.hubps[j] = dcn21_hubp_create(ctx, i);
2149 if (pool->base.hubps[j] == NULL) {
2150 BREAK_TO_DEBUGGER();
2151 dm_error(
2152 "DC: failed to create memory input!\n");
2153 goto create_fail;
2154 }
2155
2156 pool->base.ipps[j] = dcn21_ipp_create(ctx, i);
2157 if (pool->base.ipps[j] == NULL) {
2158 BREAK_TO_DEBUGGER();
2159 dm_error(
2160 "DC: failed to create input pixel processor!\n");
2161 goto create_fail;
2162 }
2163
2164 pool->base.dpps[j] = dcn21_dpp_create(ctx, i);
2165 if (pool->base.dpps[j] == NULL) {
2166 BREAK_TO_DEBUGGER();
2167 dm_error(
2168 "DC: failed to create dpps!\n");
2169 goto create_fail;
2170 }
2171
2172 pool->base.opps[j] = dcn21_opp_create(ctx, i);
2173 if (pool->base.opps[j] == NULL) {
2174 BREAK_TO_DEBUGGER();
2175 dm_error(
2176 "DC: failed to create output pixel processor!\n");
2177 goto create_fail;
2178 }
2179
2180 pool->base.timing_generators[j] = dcn21_timing_generator_create(
2181 ctx, i);
2182 if (pool->base.timing_generators[j] == NULL) {
2183 BREAK_TO_DEBUGGER();
2184 dm_error("DC: failed to create tg!\n");
2185 goto create_fail;
2186 }
2187 j++;
2188 }
2189
2190 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2191 pool->base.engines[i] = dcn21_aux_engine_create(ctx, i);
2192 if (pool->base.engines[i] == NULL) {
2193 BREAK_TO_DEBUGGER();
2194 dm_error(
2195 "DC:failed to create aux engine!!\n");
2196 goto create_fail;
2197 }
2198 pool->base.hw_i2cs[i] = dcn21_i2c_hw_create(ctx, i);
2199 if (pool->base.hw_i2cs[i] == NULL) {
2200 BREAK_TO_DEBUGGER();
2201 dm_error(
2202 "DC:failed to create hw i2c!!\n");
2203 goto create_fail;
2204 }
2205 pool->base.sw_i2cs[i] = NULL;
2206 }
2207
2208 pool->base.timing_generator_count = j;
2209 pool->base.pipe_count = j;
2210 pool->base.mpcc_count = j;
2211
2212 pool->base.mpc = dcn21_mpc_create(ctx);
2213 if (pool->base.mpc == NULL) {
2214 BREAK_TO_DEBUGGER();
2215 dm_error("DC: failed to create mpc!\n");
2216 goto create_fail;
2217 }
2218
2219 pool->base.hubbub = dcn21_hubbub_create(ctx);
2220 if (pool->base.hubbub == NULL) {
2221 BREAK_TO_DEBUGGER();
2222 dm_error("DC: failed to create hubbub!\n");
2223 goto create_fail;
2224 }
2225
2226 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2227 pool->base.dscs[i] = dcn21_dsc_create(ctx, i);
2228 if (pool->base.dscs[i] == NULL) {
2229 BREAK_TO_DEBUGGER();
2230 dm_error("DC: failed to create display stream compressor %d!\n", i);
2231 goto create_fail;
2232 }
2233 }
2234
2235 if (!dcn20_dwbc_create(ctx, &pool->base)) {
2236 BREAK_TO_DEBUGGER();
2237 dm_error("DC: failed to create dwbc!\n");
2238 goto create_fail;
2239 }
2240 if (!dcn20_mmhubbub_create(ctx, &pool->base)) {
2241 BREAK_TO_DEBUGGER();
2242 dm_error("DC: failed to create mcif_wb!\n");
2243 goto create_fail;
2244 }
2245
2246 if (!resource_construct(num_virtual_links, dc, &pool->base,
2247 (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ?
2248 &res_create_funcs : &res_create_maximus_funcs)))
2249 goto create_fail;
2250
2251 dcn21_hw_sequencer_construct(dc);
2252
2253 dc->caps.max_planes = pool->base.pipe_count;
2254
2255 for (i = 0; i < dc->caps.max_planes; ++i)
2256 dc->caps.planes[i] = plane_cap;
2257
2258 dc->cap_funcs = cap_funcs;
2259
2260 return true;
2261
2262 create_fail:
2263
2264 dcn21_resource_destruct(pool);
2265
2266 return false;
2267 }
2268
dcn21_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2269 struct resource_pool *dcn21_create_resource_pool(
2270 const struct dc_init_data *init_data,
2271 struct dc *dc)
2272 {
2273 struct dcn21_resource_pool *pool =
2274 kzalloc(sizeof(struct dcn21_resource_pool), GFP_KERNEL);
2275
2276 if (!pool)
2277 return NULL;
2278
2279 if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
2280 return &pool->base;
2281
2282 BREAK_TO_DEBUGGER();
2283 kfree(pool);
2284 return NULL;
2285 }
2286