1 /*
2  * Copyright ? 2006-2007 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *	Eric Anholt <eric@anholt.net>
25  */
26 
27 /**
28  * @file SDVO command definitions and structures.
29  */
30 
31 #define SDVO_OUTPUT_FIRST   (0)
32 #define SDVO_OUTPUT_TMDS0   (1 << 0)
33 #define SDVO_OUTPUT_RGB0    (1 << 1)
34 #define SDVO_OUTPUT_CVBS0   (1 << 2)
35 #define SDVO_OUTPUT_SVID0   (1 << 3)
36 #define SDVO_OUTPUT_YPRPB0  (1 << 4)
37 #define SDVO_OUTPUT_SCART0  (1 << 5)
38 #define SDVO_OUTPUT_LVDS0   (1 << 6)
39 #define SDVO_OUTPUT_TMDS1   (1 << 8)
40 #define SDVO_OUTPUT_RGB1    (1 << 9)
41 #define SDVO_OUTPUT_CVBS1   (1 << 10)
42 #define SDVO_OUTPUT_SVID1   (1 << 11)
43 #define SDVO_OUTPUT_YPRPB1  (1 << 12)
44 #define SDVO_OUTPUT_SCART1  (1 << 13)
45 #define SDVO_OUTPUT_LVDS1   (1 << 14)
46 #define SDVO_OUTPUT_LAST    (14)
47 
48 struct psb_intel_sdvo_caps {
49     u8 vendor_id;
50     u8 device_id;
51     u8 device_rev_id;
52     u8 sdvo_version_major;
53     u8 sdvo_version_minor;
54     unsigned int sdvo_inputs_mask:2;
55     unsigned int smooth_scaling:1;
56     unsigned int sharp_scaling:1;
57     unsigned int up_scaling:1;
58     unsigned int down_scaling:1;
59     unsigned int stall_support:1;
60     unsigned int pad:1;
61     u16 output_flags;
62 } __attribute__((packed));
63 
64 /** This matches the EDID DTD structure, more or less */
65 struct psb_intel_sdvo_dtd {
66     struct {
67 	u16 clock;		/**< pixel clock, in 10kHz units */
68 	u8 h_active;		/**< lower 8 bits (pixels) */
69 	u8 h_blank;		/**< lower 8 bits (pixels) */
70 	u8 h_high;		/**< upper 4 bits each h_active, h_blank */
71 	u8 v_active;		/**< lower 8 bits (lines) */
72 	u8 v_blank;		/**< lower 8 bits (lines) */
73 	u8 v_high;		/**< upper 4 bits each v_active, v_blank */
74     } part1;
75 
76     struct {
77 	u8 h_sync_off;	/**< lower 8 bits, from hblank start */
78 	u8 h_sync_width;	/**< lower 8 bits (pixels) */
79 	/** lower 4 bits each vsync offset, vsync width */
80 	u8 v_sync_off_width;
81 	/**
82 	 * 2 high bits of hsync offset, 2 high bits of hsync width,
83 	 * bits 4-5 of vsync offset, and 2 high bits of vsync width.
84 	 */
85 	u8 sync_off_width_high;
86 	u8 dtd_flags;
87 	u8 sdvo_flags;
88 	/** bits 6-7 of vsync offset at bits 6-7 */
89 	u8 v_sync_off_high;
90 	u8 reserved;
91     } part2;
92 } __attribute__((packed));
93 
94 struct psb_intel_sdvo_pixel_clock_range {
95     u16 min;			/**< pixel clock, in 10kHz units */
96     u16 max;			/**< pixel clock, in 10kHz units */
97 } __attribute__((packed));
98 
99 struct psb_intel_sdvo_preferred_input_timing_args {
100     u16 clock;
101     u16 width;
102     u16 height;
103     u8	interlace:1;
104     u8	scaled:1;
105     u8	pad:6;
106 } __attribute__((packed));
107 
108 /* I2C registers for SDVO */
109 #define SDVO_I2C_ARG_0				0x07
110 #define SDVO_I2C_ARG_1				0x06
111 #define SDVO_I2C_ARG_2				0x05
112 #define SDVO_I2C_ARG_3				0x04
113 #define SDVO_I2C_ARG_4				0x03
114 #define SDVO_I2C_ARG_5				0x02
115 #define SDVO_I2C_ARG_6				0x01
116 #define SDVO_I2C_ARG_7				0x00
117 #define SDVO_I2C_OPCODE				0x08
118 #define SDVO_I2C_CMD_STATUS			0x09
119 #define SDVO_I2C_RETURN_0			0x0a
120 #define SDVO_I2C_RETURN_1			0x0b
121 #define SDVO_I2C_RETURN_2			0x0c
122 #define SDVO_I2C_RETURN_3			0x0d
123 #define SDVO_I2C_RETURN_4			0x0e
124 #define SDVO_I2C_RETURN_5			0x0f
125 #define SDVO_I2C_RETURN_6			0x10
126 #define SDVO_I2C_RETURN_7			0x11
127 #define SDVO_I2C_VENDOR_BEGIN			0x20
128 
129 /* Status results */
130 #define SDVO_CMD_STATUS_POWER_ON		0x0
131 #define SDVO_CMD_STATUS_SUCCESS			0x1
132 #define SDVO_CMD_STATUS_NOTSUPP			0x2
133 #define SDVO_CMD_STATUS_INVALID_ARG		0x3
134 #define SDVO_CMD_STATUS_PENDING			0x4
135 #define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED	0x5
136 #define SDVO_CMD_STATUS_SCALING_NOT_SUPP	0x6
137 
138 /* SDVO commands, argument/result registers */
139 
140 #define SDVO_CMD_RESET					0x01
141 
142 /** Returns a struct intel_sdvo_caps */
143 #define SDVO_CMD_GET_DEVICE_CAPS			0x02
144 
145 #define SDVO_CMD_GET_FIRMWARE_REV			0x86
146 # define SDVO_DEVICE_FIRMWARE_MINOR			SDVO_I2C_RETURN_0
147 # define SDVO_DEVICE_FIRMWARE_MAJOR			SDVO_I2C_RETURN_1
148 # define SDVO_DEVICE_FIRMWARE_PATCH			SDVO_I2C_RETURN_2
149 
150 /**
151  * Reports which inputs are trained (managed to sync).
152  *
153  * Devices must have trained within 2 vsyncs of a mode change.
154  */
155 #define SDVO_CMD_GET_TRAINED_INPUTS			0x03
156 struct psb_intel_sdvo_get_trained_inputs_response {
157     unsigned int input0_trained:1;
158     unsigned int input1_trained:1;
159     unsigned int pad:6;
160 } __attribute__((packed));
161 
162 /** Returns a struct intel_sdvo_output_flags of active outputs. */
163 #define SDVO_CMD_GET_ACTIVE_OUTPUTS			0x04
164 
165 /**
166  * Sets the current set of active outputs.
167  *
168  * Takes a struct intel_sdvo_output_flags.  Must be preceded by a SET_IN_OUT_MAP
169  * on multi-output devices.
170  */
171 #define SDVO_CMD_SET_ACTIVE_OUTPUTS			0x05
172 
173 /**
174  * Returns the current mapping of SDVO inputs to outputs on the device.
175  *
176  * Returns two struct intel_sdvo_output_flags structures.
177  */
178 #define SDVO_CMD_GET_IN_OUT_MAP				0x06
179 struct psb_intel_sdvo_in_out_map {
180     u16 in0, in1;
181 };
182 
183 /**
184  * Sets the current mapping of SDVO inputs to outputs on the device.
185  *
186  * Takes two struct i380_sdvo_output_flags structures.
187  */
188 #define SDVO_CMD_SET_IN_OUT_MAP				0x07
189 
190 /**
191  * Returns a struct intel_sdvo_output_flags of attached displays.
192  */
193 #define SDVO_CMD_GET_ATTACHED_DISPLAYS			0x0b
194 
195 /**
196  * Returns a struct intel_sdvo_ouptut_flags of displays supporting hot plugging.
197  */
198 #define SDVO_CMD_GET_HOT_PLUG_SUPPORT			0x0c
199 
200 /**
201  * Takes a struct intel_sdvo_output_flags.
202  */
203 #define SDVO_CMD_SET_ACTIVE_HOT_PLUG			0x0d
204 
205 /**
206  * Returns a struct intel_sdvo_output_flags of displays with hot plug
207  * interrupts enabled.
208  */
209 #define SDVO_CMD_GET_ACTIVE_HOT_PLUG			0x0e
210 
211 #define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE		0x0f
212 struct intel_sdvo_get_interrupt_event_source_response {
213     u16 interrupt_status;
214     unsigned int ambient_light_interrupt:1;
215     unsigned int hdmi_audio_encrypt_change:1;
216     unsigned int pad:6;
217 } __attribute__((packed));
218 
219 /**
220  * Selects which input is affected by future input commands.
221  *
222  * Commands affected include SET_INPUT_TIMINGS_PART[12],
223  * GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
224  * GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
225  */
226 #define SDVO_CMD_SET_TARGET_INPUT			0x10
227 struct psb_intel_sdvo_set_target_input_args {
228     unsigned int target_1:1;
229     unsigned int pad:7;
230 } __attribute__((packed));
231 
232 /**
233  * Takes a struct intel_sdvo_output_flags of which outputs are targeted by
234  * future output commands.
235  *
236  * Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
237  * GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
238  */
239 #define SDVO_CMD_SET_TARGET_OUTPUT			0x11
240 
241 #define SDVO_CMD_GET_INPUT_TIMINGS_PART1		0x12
242 #define SDVO_CMD_GET_INPUT_TIMINGS_PART2		0x13
243 #define SDVO_CMD_SET_INPUT_TIMINGS_PART1		0x14
244 #define SDVO_CMD_SET_INPUT_TIMINGS_PART2		0x15
245 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1		0x16
246 #define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2		0x17
247 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1		0x18
248 #define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2		0x19
249 /* Part 1 */
250 # define SDVO_DTD_CLOCK_LOW				SDVO_I2C_ARG_0
251 # define SDVO_DTD_CLOCK_HIGH				SDVO_I2C_ARG_1
252 # define SDVO_DTD_H_ACTIVE				SDVO_I2C_ARG_2
253 # define SDVO_DTD_H_BLANK				SDVO_I2C_ARG_3
254 # define SDVO_DTD_H_HIGH				SDVO_I2C_ARG_4
255 # define SDVO_DTD_V_ACTIVE				SDVO_I2C_ARG_5
256 # define SDVO_DTD_V_BLANK				SDVO_I2C_ARG_6
257 # define SDVO_DTD_V_HIGH				SDVO_I2C_ARG_7
258 /* Part 2 */
259 # define SDVO_DTD_HSYNC_OFF				SDVO_I2C_ARG_0
260 # define SDVO_DTD_HSYNC_WIDTH				SDVO_I2C_ARG_1
261 # define SDVO_DTD_VSYNC_OFF_WIDTH			SDVO_I2C_ARG_2
262 # define SDVO_DTD_SYNC_OFF_WIDTH_HIGH			SDVO_I2C_ARG_3
263 # define SDVO_DTD_DTD_FLAGS				SDVO_I2C_ARG_4
264 # define SDVO_DTD_DTD_FLAG_INTERLACED				(1 << 7)
265 # define SDVO_DTD_DTD_FLAG_STEREO_MASK				(3 << 5)
266 # define SDVO_DTD_DTD_FLAG_INPUT_MASK				(3 << 3)
267 # define SDVO_DTD_DTD_FLAG_SYNC_MASK				(3 << 1)
268 # define SDVO_DTD_SDVO_FLAS				SDVO_I2C_ARG_5
269 # define SDVO_DTD_SDVO_FLAG_STALL				(1 << 7)
270 # define SDVO_DTD_SDVO_FLAG_CENTERED				(0 << 6)
271 # define SDVO_DTD_SDVO_FLAG_UPPER_LEFT				(1 << 6)
272 # define SDVO_DTD_SDVO_FLAG_SCALING_MASK			(3 << 4)
273 # define SDVO_DTD_SDVO_FLAG_SCALING_NONE			(0 << 4)
274 # define SDVO_DTD_SDVO_FLAG_SCALING_SHARP			(1 << 4)
275 # define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH			(2 << 4)
276 # define SDVO_DTD_VSYNC_OFF_HIGH			SDVO_I2C_ARG_6
277 
278 /**
279  * Generates a DTD based on the given width, height, and flags.
280  *
281  * This will be supported by any device supporting scaling or interlaced
282  * modes.
283  */
284 #define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING		0x1a
285 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW		SDVO_I2C_ARG_0
286 # define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH		SDVO_I2C_ARG_1
287 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW		SDVO_I2C_ARG_2
288 # define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH		SDVO_I2C_ARG_3
289 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW		SDVO_I2C_ARG_4
290 # define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH	SDVO_I2C_ARG_5
291 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS		SDVO_I2C_ARG_6
292 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED		(1 << 0)
293 # define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED		(1 << 1)
294 
295 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1	0x1b
296 #define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2	0x1c
297 
298 /** Returns a struct intel_sdvo_pixel_clock_range */
299 #define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE		0x1d
300 /** Returns a struct intel_sdvo_pixel_clock_range */
301 #define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE		0x1e
302 
303 /** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
304 #define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS		0x1f
305 
306 /** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
307 #define SDVO_CMD_GET_CLOCK_RATE_MULT			0x20
308 /** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
309 #define SDVO_CMD_SET_CLOCK_RATE_MULT			0x21
310 # define SDVO_CLOCK_RATE_MULT_1X				(1 << 0)
311 # define SDVO_CLOCK_RATE_MULT_2X				(1 << 1)
312 # define SDVO_CLOCK_RATE_MULT_4X				(1 << 3)
313 
314 #define SDVO_CMD_GET_SUPPORTED_TV_FORMATS		0x27
315 /** 6 bytes of bit flags for TV formats shared by all TV format functions */
316 struct psb_intel_sdvo_tv_format {
317     unsigned int ntsc_m:1;
318     unsigned int ntsc_j:1;
319     unsigned int ntsc_443:1;
320     unsigned int pal_b:1;
321     unsigned int pal_d:1;
322     unsigned int pal_g:1;
323     unsigned int pal_h:1;
324     unsigned int pal_i:1;
325 
326     unsigned int pal_m:1;
327     unsigned int pal_n:1;
328     unsigned int pal_nc:1;
329     unsigned int pal_60:1;
330     unsigned int secam_b:1;
331     unsigned int secam_d:1;
332     unsigned int secam_g:1;
333     unsigned int secam_k:1;
334 
335     unsigned int secam_k1:1;
336     unsigned int secam_l:1;
337     unsigned int secam_60:1;
338     unsigned int hdtv_std_smpte_240m_1080i_59:1;
339     unsigned int hdtv_std_smpte_240m_1080i_60:1;
340     unsigned int hdtv_std_smpte_260m_1080i_59:1;
341     unsigned int hdtv_std_smpte_260m_1080i_60:1;
342     unsigned int hdtv_std_smpte_274m_1080i_50:1;
343 
344     unsigned int hdtv_std_smpte_274m_1080i_59:1;
345     unsigned int hdtv_std_smpte_274m_1080i_60:1;
346     unsigned int hdtv_std_smpte_274m_1080p_23:1;
347     unsigned int hdtv_std_smpte_274m_1080p_24:1;
348     unsigned int hdtv_std_smpte_274m_1080p_25:1;
349     unsigned int hdtv_std_smpte_274m_1080p_29:1;
350     unsigned int hdtv_std_smpte_274m_1080p_30:1;
351     unsigned int hdtv_std_smpte_274m_1080p_50:1;
352 
353     unsigned int hdtv_std_smpte_274m_1080p_59:1;
354     unsigned int hdtv_std_smpte_274m_1080p_60:1;
355     unsigned int hdtv_std_smpte_295m_1080i_50:1;
356     unsigned int hdtv_std_smpte_295m_1080p_50:1;
357     unsigned int hdtv_std_smpte_296m_720p_59:1;
358     unsigned int hdtv_std_smpte_296m_720p_60:1;
359     unsigned int hdtv_std_smpte_296m_720p_50:1;
360     unsigned int hdtv_std_smpte_293m_480p_59:1;
361 
362     unsigned int hdtv_std_smpte_170m_480i_59:1;
363     unsigned int hdtv_std_iturbt601_576i_50:1;
364     unsigned int hdtv_std_iturbt601_576p_50:1;
365     unsigned int hdtv_std_eia_7702a_480i_60:1;
366     unsigned int hdtv_std_eia_7702a_480p_60:1;
367     unsigned int pad:3;
368 } __attribute__((packed));
369 
370 #define SDVO_CMD_GET_TV_FORMAT				0x28
371 
372 #define SDVO_CMD_SET_TV_FORMAT				0x29
373 
374 /** Returns the resolutiosn that can be used with the given TV format */
375 #define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT		0x83
376 struct psb_intel_sdvo_sdtv_resolution_request {
377     unsigned int ntsc_m:1;
378     unsigned int ntsc_j:1;
379     unsigned int ntsc_443:1;
380     unsigned int pal_b:1;
381     unsigned int pal_d:1;
382     unsigned int pal_g:1;
383     unsigned int pal_h:1;
384     unsigned int pal_i:1;
385 
386     unsigned int pal_m:1;
387     unsigned int pal_n:1;
388     unsigned int pal_nc:1;
389     unsigned int pal_60:1;
390     unsigned int secam_b:1;
391     unsigned int secam_d:1;
392     unsigned int secam_g:1;
393     unsigned int secam_k:1;
394 
395     unsigned int secam_k1:1;
396     unsigned int secam_l:1;
397     unsigned int secam_60:1;
398     unsigned int pad:5;
399 } __attribute__((packed));
400 
401 struct psb_intel_sdvo_sdtv_resolution_reply {
402     unsigned int res_320x200:1;
403     unsigned int res_320x240:1;
404     unsigned int res_400x300:1;
405     unsigned int res_640x350:1;
406     unsigned int res_640x400:1;
407     unsigned int res_640x480:1;
408     unsigned int res_704x480:1;
409     unsigned int res_704x576:1;
410 
411     unsigned int res_720x350:1;
412     unsigned int res_720x400:1;
413     unsigned int res_720x480:1;
414     unsigned int res_720x540:1;
415     unsigned int res_720x576:1;
416     unsigned int res_768x576:1;
417     unsigned int res_800x600:1;
418     unsigned int res_832x624:1;
419 
420     unsigned int res_920x766:1;
421     unsigned int res_1024x768:1;
422     unsigned int res_1280x1024:1;
423     unsigned int pad:5;
424 } __attribute__((packed));
425 
426 /* Get supported resolution with squire pixel aspect ratio that can be
427    scaled for the requested HDTV format */
428 #define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT		0x85
429 
430 struct psb_intel_sdvo_hdtv_resolution_request {
431     unsigned int hdtv_std_smpte_240m_1080i_59:1;
432     unsigned int hdtv_std_smpte_240m_1080i_60:1;
433     unsigned int hdtv_std_smpte_260m_1080i_59:1;
434     unsigned int hdtv_std_smpte_260m_1080i_60:1;
435     unsigned int hdtv_std_smpte_274m_1080i_50:1;
436     unsigned int hdtv_std_smpte_274m_1080i_59:1;
437     unsigned int hdtv_std_smpte_274m_1080i_60:1;
438     unsigned int hdtv_std_smpte_274m_1080p_23:1;
439 
440     unsigned int hdtv_std_smpte_274m_1080p_24:1;
441     unsigned int hdtv_std_smpte_274m_1080p_25:1;
442     unsigned int hdtv_std_smpte_274m_1080p_29:1;
443     unsigned int hdtv_std_smpte_274m_1080p_30:1;
444     unsigned int hdtv_std_smpte_274m_1080p_50:1;
445     unsigned int hdtv_std_smpte_274m_1080p_59:1;
446     unsigned int hdtv_std_smpte_274m_1080p_60:1;
447     unsigned int hdtv_std_smpte_295m_1080i_50:1;
448 
449     unsigned int hdtv_std_smpte_295m_1080p_50:1;
450     unsigned int hdtv_std_smpte_296m_720p_59:1;
451     unsigned int hdtv_std_smpte_296m_720p_60:1;
452     unsigned int hdtv_std_smpte_296m_720p_50:1;
453     unsigned int hdtv_std_smpte_293m_480p_59:1;
454     unsigned int hdtv_std_smpte_170m_480i_59:1;
455     unsigned int hdtv_std_iturbt601_576i_50:1;
456     unsigned int hdtv_std_iturbt601_576p_50:1;
457 
458     unsigned int hdtv_std_eia_7702a_480i_60:1;
459     unsigned int hdtv_std_eia_7702a_480p_60:1;
460     unsigned int pad:6;
461 } __attribute__((packed));
462 
463 struct psb_intel_sdvo_hdtv_resolution_reply {
464     unsigned int res_640x480:1;
465     unsigned int res_800x600:1;
466     unsigned int res_1024x768:1;
467     unsigned int res_1280x960:1;
468     unsigned int res_1400x1050:1;
469     unsigned int res_1600x1200:1;
470     unsigned int res_1920x1440:1;
471     unsigned int res_2048x1536:1;
472 
473     unsigned int res_2560x1920:1;
474     unsigned int res_3200x2400:1;
475     unsigned int res_3840x2880:1;
476     unsigned int pad1:5;
477 
478     unsigned int res_848x480:1;
479     unsigned int res_1064x600:1;
480     unsigned int res_1280x720:1;
481     unsigned int res_1360x768:1;
482     unsigned int res_1704x960:1;
483     unsigned int res_1864x1050:1;
484     unsigned int res_1920x1080:1;
485     unsigned int res_2128x1200:1;
486 
487     unsigned int res_2560x1400:1;
488     unsigned int res_2728x1536:1;
489     unsigned int res_3408x1920:1;
490     unsigned int res_4264x2400:1;
491     unsigned int res_5120x2880:1;
492     unsigned int pad2:3;
493 
494     unsigned int res_768x480:1;
495     unsigned int res_960x600:1;
496     unsigned int res_1152x720:1;
497     unsigned int res_1124x768:1;
498     unsigned int res_1536x960:1;
499     unsigned int res_1680x1050:1;
500     unsigned int res_1728x1080:1;
501     unsigned int res_1920x1200:1;
502 
503     unsigned int res_2304x1440:1;
504     unsigned int res_2456x1536:1;
505     unsigned int res_3072x1920:1;
506     unsigned int res_3840x2400:1;
507     unsigned int res_4608x2880:1;
508     unsigned int pad3:3;
509 
510     unsigned int res_1280x1024:1;
511     unsigned int pad4:7;
512 
513     unsigned int res_1280x768:1;
514     unsigned int pad5:7;
515 } __attribute__((packed));
516 
517 /* Get supported power state returns info for encoder and monitor, rely on
518    last SetTargetInput and SetTargetOutput calls */
519 #define SDVO_CMD_GET_SUPPORTED_POWER_STATES		0x2a
520 /* Get power state returns info for encoder and monitor, rely on last
521    SetTargetInput and SetTargetOutput calls */
522 #define SDVO_CMD_GET_POWER_STATE			0x2b
523 #define SDVO_CMD_GET_ENCODER_POWER_STATE		0x2b
524 #define SDVO_CMD_SET_ENCODER_POWER_STATE		0x2c
525 # define SDVO_ENCODER_STATE_ON					(1 << 0)
526 # define SDVO_ENCODER_STATE_STANDBY				(1 << 1)
527 # define SDVO_ENCODER_STATE_SUSPEND				(1 << 2)
528 # define SDVO_ENCODER_STATE_OFF					(1 << 3)
529 # define SDVO_MONITOR_STATE_ON					(1 << 4)
530 # define SDVO_MONITOR_STATE_STANDBY				(1 << 5)
531 # define SDVO_MONITOR_STATE_SUSPEND				(1 << 6)
532 # define SDVO_MONITOR_STATE_OFF					(1 << 7)
533 
534 #define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING		0x2d
535 #define SDVO_CMD_GET_PANEL_POWER_SEQUENCING		0x2e
536 #define SDVO_CMD_SET_PANEL_POWER_SEQUENCING		0x2f
537 /**
538  * The panel power sequencing parameters are in units of milliseconds.
539  * The high fields are bits 8:9 of the 10-bit values.
540  */
541 struct psb_sdvo_panel_power_sequencing {
542     u8 t0;
543     u8 t1;
544     u8 t2;
545     u8 t3;
546     u8 t4;
547 
548     unsigned int t0_high:2;
549     unsigned int t1_high:2;
550     unsigned int t2_high:2;
551     unsigned int t3_high:2;
552 
553     unsigned int t4_high:2;
554     unsigned int pad:6;
555 } __attribute__((packed));
556 
557 #define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL		0x30
558 struct sdvo_max_backlight_reply {
559     u8 max_value;
560     u8 default_value;
561 } __attribute__((packed));
562 
563 #define SDVO_CMD_GET_BACKLIGHT_LEVEL			0x31
564 #define SDVO_CMD_SET_BACKLIGHT_LEVEL			0x32
565 
566 #define SDVO_CMD_GET_AMBIENT_LIGHT			0x33
567 struct sdvo_get_ambient_light_reply {
568     u16 trip_low;
569     u16 trip_high;
570     u16 value;
571 } __attribute__((packed));
572 #define SDVO_CMD_SET_AMBIENT_LIGHT			0x34
573 struct sdvo_set_ambient_light_reply {
574     u16 trip_low;
575     u16 trip_high;
576     unsigned int enable:1;
577     unsigned int pad:7;
578 } __attribute__((packed));
579 
580 /* Set display power state */
581 #define SDVO_CMD_SET_DISPLAY_POWER_STATE		0x7d
582 # define SDVO_DISPLAY_STATE_ON				(1 << 0)
583 # define SDVO_DISPLAY_STATE_STANDBY			(1 << 1)
584 # define SDVO_DISPLAY_STATE_SUSPEND			(1 << 2)
585 # define SDVO_DISPLAY_STATE_OFF				(1 << 3)
586 
587 #define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS		0x84
588 struct psb_intel_sdvo_enhancements_reply {
589     unsigned int flicker_filter:1;
590     unsigned int flicker_filter_adaptive:1;
591     unsigned int flicker_filter_2d:1;
592     unsigned int saturation:1;
593     unsigned int hue:1;
594     unsigned int brightness:1;
595     unsigned int contrast:1;
596     unsigned int overscan_h:1;
597 
598     unsigned int overscan_v:1;
599     unsigned int hpos:1;
600     unsigned int vpos:1;
601     unsigned int sharpness:1;
602     unsigned int dot_crawl:1;
603     unsigned int dither:1;
604     unsigned int tv_chroma_filter:1;
605     unsigned int tv_luma_filter:1;
606 } __attribute__((packed));
607 
608 /* Picture enhancement limits below are dependent on the current TV format,
609  * and thus need to be queried and set after it.
610  */
611 #define SDVO_CMD_GET_MAX_FLICKER_FILTER			0x4d
612 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE	0x7b
613 #define SDVO_CMD_GET_MAX_FLICKER_FILTER_2D		0x52
614 #define SDVO_CMD_GET_MAX_SATURATION			0x55
615 #define SDVO_CMD_GET_MAX_HUE				0x58
616 #define SDVO_CMD_GET_MAX_BRIGHTNESS			0x5b
617 #define SDVO_CMD_GET_MAX_CONTRAST			0x5e
618 #define SDVO_CMD_GET_MAX_OVERSCAN_H			0x61
619 #define SDVO_CMD_GET_MAX_OVERSCAN_V			0x64
620 #define SDVO_CMD_GET_MAX_HPOS				0x67
621 #define SDVO_CMD_GET_MAX_VPOS				0x6a
622 #define SDVO_CMD_GET_MAX_SHARPNESS			0x6d
623 #define SDVO_CMD_GET_MAX_TV_CHROMA_FILTER		0x74
624 #define SDVO_CMD_GET_MAX_TV_LUMA_FILTER			0x77
625 struct psb_intel_sdvo_enhancement_limits_reply {
626     u16 max_value;
627     u16 default_value;
628 } __attribute__((packed));
629 
630 #define SDVO_CMD_GET_LVDS_PANEL_INFORMATION		0x7f
631 #define SDVO_CMD_SET_LVDS_PANEL_INFORMATION		0x80
632 # define SDVO_LVDS_COLOR_DEPTH_18			(0 << 0)
633 # define SDVO_LVDS_COLOR_DEPTH_24			(1 << 0)
634 # define SDVO_LVDS_CONNECTOR_SPWG			(0 << 2)
635 # define SDVO_LVDS_CONNECTOR_OPENLDI			(1 << 2)
636 # define SDVO_LVDS_SINGLE_CHANNEL			(0 << 4)
637 # define SDVO_LVDS_DUAL_CHANNEL				(1 << 4)
638 
639 #define SDVO_CMD_GET_FLICKER_FILTER			0x4e
640 #define SDVO_CMD_SET_FLICKER_FILTER			0x4f
641 #define SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE		0x50
642 #define SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE		0x51
643 #define SDVO_CMD_GET_FLICKER_FILTER_2D			0x53
644 #define SDVO_CMD_SET_FLICKER_FILTER_2D			0x54
645 #define SDVO_CMD_GET_SATURATION				0x56
646 #define SDVO_CMD_SET_SATURATION				0x57
647 #define SDVO_CMD_GET_HUE				0x59
648 #define SDVO_CMD_SET_HUE				0x5a
649 #define SDVO_CMD_GET_BRIGHTNESS				0x5c
650 #define SDVO_CMD_SET_BRIGHTNESS				0x5d
651 #define SDVO_CMD_GET_CONTRAST				0x5f
652 #define SDVO_CMD_SET_CONTRAST				0x60
653 #define SDVO_CMD_GET_OVERSCAN_H				0x62
654 #define SDVO_CMD_SET_OVERSCAN_H				0x63
655 #define SDVO_CMD_GET_OVERSCAN_V				0x65
656 #define SDVO_CMD_SET_OVERSCAN_V				0x66
657 #define SDVO_CMD_GET_HPOS				0x68
658 #define SDVO_CMD_SET_HPOS				0x69
659 #define SDVO_CMD_GET_VPOS				0x6b
660 #define SDVO_CMD_SET_VPOS				0x6c
661 #define SDVO_CMD_GET_SHARPNESS				0x6e
662 #define SDVO_CMD_SET_SHARPNESS				0x6f
663 #define SDVO_CMD_GET_TV_CHROMA_FILTER			0x75
664 #define SDVO_CMD_SET_TV_CHROMA_FILTER			0x76
665 #define SDVO_CMD_GET_TV_LUMA_FILTER			0x78
666 #define SDVO_CMD_SET_TV_LUMA_FILTER			0x79
667 struct psb_intel_sdvo_enhancements_arg {
668     u16 value;
669 }__attribute__((packed));
670 
671 #define SDVO_CMD_GET_DOT_CRAWL				0x70
672 #define SDVO_CMD_SET_DOT_CRAWL				0x71
673 # define SDVO_DOT_CRAWL_ON					(1 << 0)
674 # define SDVO_DOT_CRAWL_DEFAULT_ON				(1 << 1)
675 
676 #define SDVO_CMD_GET_DITHER				0x72
677 #define SDVO_CMD_SET_DITHER				0x73
678 # define SDVO_DITHER_ON						(1 << 0)
679 # define SDVO_DITHER_DEFAULT_ON					(1 << 1)
680 
681 #define SDVO_CMD_SET_CONTROL_BUS_SWITCH			0x7a
682 # define SDVO_CONTROL_BUS_PROM				(1 << 0)
683 # define SDVO_CONTROL_BUS_DDC1				(1 << 1)
684 # define SDVO_CONTROL_BUS_DDC2				(1 << 2)
685 # define SDVO_CONTROL_BUS_DDC3				(1 << 3)
686 
687 /* HDMI op codes */
688 #define SDVO_CMD_GET_SUPP_ENCODE	0x9d
689 #define SDVO_CMD_GET_ENCODE		0x9e
690 #define SDVO_CMD_SET_ENCODE		0x9f
691   #define SDVO_ENCODE_DVI	0x0
692   #define SDVO_ENCODE_HDMI	0x1
693 #define SDVO_CMD_SET_PIXEL_REPLI	0x8b
694 #define SDVO_CMD_GET_PIXEL_REPLI	0x8c
695 #define SDVO_CMD_GET_COLORIMETRY_CAP	0x8d
696 #define SDVO_CMD_SET_COLORIMETRY	0x8e
697   #define SDVO_COLORIMETRY_RGB256   0x0
698   #define SDVO_COLORIMETRY_RGB220   0x1
699   #define SDVO_COLORIMETRY_YCrCb422 0x3
700   #define SDVO_COLORIMETRY_YCrCb444 0x4
701 #define SDVO_CMD_GET_COLORIMETRY	0x8f
702 #define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
703 #define SDVO_CMD_SET_AUDIO_STAT		0x91
704 #define SDVO_CMD_GET_AUDIO_STAT		0x92
705 #define SDVO_CMD_SET_HBUF_INDEX		0x93
706 #define SDVO_CMD_GET_HBUF_INDEX		0x94
707 #define SDVO_CMD_GET_HBUF_INFO		0x95
708 #define SDVO_CMD_SET_HBUF_AV_SPLIT	0x96
709 #define SDVO_CMD_GET_HBUF_AV_SPLIT	0x97
710 #define SDVO_CMD_SET_HBUF_DATA		0x98
711 #define SDVO_CMD_GET_HBUF_DATA		0x99
712 #define SDVO_CMD_SET_HBUF_TXRATE	0x9a
713 #define SDVO_CMD_GET_HBUF_TXRATE	0x9b
714   #define SDVO_HBUF_TX_DISABLED	(0 << 6)
715   #define SDVO_HBUF_TX_ONCE	(2 << 6)
716   #define SDVO_HBUF_TX_VSYNC	(3 << 6)
717 #define SDVO_CMD_GET_AUDIO_TX_INFO	0x9c
718 #define SDVO_NEED_TO_STALL  (1 << 7)
719 
720 struct psb_intel_sdvo_encode {
721     u8 dvi_rev;
722     u8 hdmi_rev;
723 } __attribute__ ((packed));
724