1 /* SPDX-License-Identifier: MIT */
2 #ifndef _INTEL_RINGBUFFER_H_
3 #define _INTEL_RINGBUFFER_H_
4
5 #include <drm/drm_util.h>
6
7 #include <linux/hashtable.h>
8 #include <linux/irq_work.h>
9 #include <linux/random.h>
10 #include <linux/seqlock.h>
11
12 #include "i915_pmu.h"
13 #include "i915_reg.h"
14 #include "i915_request.h"
15 #include "i915_selftest.h"
16 #include "gt/intel_timeline.h"
17 #include "intel_engine_types.h"
18 #include "intel_workarounds.h"
19
20 struct drm_printer;
21 struct intel_gt;
22
23 /* Early gen2 devices have a cacheline of just 32 bytes, using 64 is overkill,
24 * but keeps the logic simple. Indeed, the whole purpose of this macro is just
25 * to give some inclination as to some of the magic values used in the various
26 * workarounds!
27 */
28 #define CACHELINE_BYTES 64
29 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(u32))
30
31 #define ENGINE_TRACE(e, fmt, ...) do { \
32 const struct intel_engine_cs *e__ __maybe_unused = (e); \
33 GEM_TRACE("%s %s: " fmt, \
34 dev_name(e__->i915->drm.dev), e__->name, \
35 ##__VA_ARGS__); \
36 } while (0)
37
38 /*
39 * The register defines to be used with the following macros need to accept a
40 * base param, e.g:
41 *
42 * REG_FOO(base) _MMIO((base) + <relative offset>)
43 * ENGINE_READ(engine, REG_FOO);
44 *
45 * register arrays are to be defined and accessed as follows:
46 *
47 * REG_BAR(base, i) _MMIO((base) + <relative offset> + (i) * <shift>)
48 * ENGINE_READ_IDX(engine, REG_BAR, i)
49 */
50
51 #define __ENGINE_REG_OP(op__, engine__, ...) \
52 intel_uncore_##op__((engine__)->uncore, __VA_ARGS__)
53
54 #define __ENGINE_READ_OP(op__, engine__, reg__) \
55 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base))
56
57 #define ENGINE_READ16(...) __ENGINE_READ_OP(read16, __VA_ARGS__)
58 #define ENGINE_READ(...) __ENGINE_READ_OP(read, __VA_ARGS__)
59 #define ENGINE_READ_FW(...) __ENGINE_READ_OP(read_fw, __VA_ARGS__)
60 #define ENGINE_POSTING_READ(...) __ENGINE_READ_OP(posting_read_fw, __VA_ARGS__)
61 #define ENGINE_POSTING_READ16(...) __ENGINE_READ_OP(posting_read16, __VA_ARGS__)
62
63 #define ENGINE_READ64(engine__, lower_reg__, upper_reg__) \
64 __ENGINE_REG_OP(read64_2x32, (engine__), \
65 lower_reg__((engine__)->mmio_base), \
66 upper_reg__((engine__)->mmio_base))
67
68 #define ENGINE_READ_IDX(engine__, reg__, idx__) \
69 __ENGINE_REG_OP(read, (engine__), reg__((engine__)->mmio_base, (idx__)))
70
71 #define __ENGINE_WRITE_OP(op__, engine__, reg__, val__) \
72 __ENGINE_REG_OP(op__, (engine__), reg__((engine__)->mmio_base), (val__))
73
74 #define ENGINE_WRITE16(...) __ENGINE_WRITE_OP(write16, __VA_ARGS__)
75 #define ENGINE_WRITE(...) __ENGINE_WRITE_OP(write, __VA_ARGS__)
76 #define ENGINE_WRITE_FW(...) __ENGINE_WRITE_OP(write_fw, __VA_ARGS__)
77
78 #define GEN6_RING_FAULT_REG_READ(engine__) \
79 intel_uncore_read((engine__)->uncore, RING_FAULT_REG(engine__))
80
81 #define GEN6_RING_FAULT_REG_POSTING_READ(engine__) \
82 intel_uncore_posting_read((engine__)->uncore, RING_FAULT_REG(engine__))
83
84 #define GEN6_RING_FAULT_REG_RMW(engine__, clear__, set__) \
85 ({ \
86 u32 __val; \
87 \
88 __val = intel_uncore_read((engine__)->uncore, \
89 RING_FAULT_REG(engine__)); \
90 __val &= ~(clear__); \
91 __val |= (set__); \
92 intel_uncore_write((engine__)->uncore, RING_FAULT_REG(engine__), \
93 __val); \
94 })
95
96 /* seqno size is actually only a uint32, but since we plan to use MI_FLUSH_DW to
97 * do the writes, and that must have qw aligned offsets, simply pretend it's 8b.
98 */
99
100 static inline unsigned int
execlists_num_ports(const struct intel_engine_execlists * const execlists)101 execlists_num_ports(const struct intel_engine_execlists * const execlists)
102 {
103 return execlists->port_mask + 1;
104 }
105
106 static inline struct i915_request *
execlists_active(const struct intel_engine_execlists * execlists)107 execlists_active(const struct intel_engine_execlists *execlists)
108 {
109 struct i915_request * const *cur, * const *old, *active;
110
111 cur = READ_ONCE(execlists->active);
112 smp_rmb(); /* pairs with overwrite protection in process_csb() */
113 do {
114 old = cur;
115
116 active = READ_ONCE(*cur);
117 cur = READ_ONCE(execlists->active);
118
119 smp_rmb(); /* and complete the seqlock retry */
120 } while (unlikely(cur != old));
121
122 return active;
123 }
124
125 static inline void
execlists_active_lock_bh(struct intel_engine_execlists * execlists)126 execlists_active_lock_bh(struct intel_engine_execlists *execlists)
127 {
128 local_bh_disable(); /* prevent local softirq and lock recursion */
129 tasklet_lock(&execlists->tasklet);
130 }
131
132 static inline void
execlists_active_unlock_bh(struct intel_engine_execlists * execlists)133 execlists_active_unlock_bh(struct intel_engine_execlists *execlists)
134 {
135 tasklet_unlock(&execlists->tasklet);
136 local_bh_enable(); /* restore softirq, and kick ksoftirqd! */
137 }
138
139 struct i915_request *
140 execlists_unwind_incomplete_requests(struct intel_engine_execlists *execlists);
141
142 static inline u32
intel_read_status_page(const struct intel_engine_cs * engine,int reg)143 intel_read_status_page(const struct intel_engine_cs *engine, int reg)
144 {
145 /* Ensure that the compiler doesn't optimize away the load. */
146 return READ_ONCE(engine->status_page.addr[reg]);
147 }
148
149 static inline void
intel_write_status_page(struct intel_engine_cs * engine,int reg,u32 value)150 intel_write_status_page(struct intel_engine_cs *engine, int reg, u32 value)
151 {
152 /* Writing into the status page should be done sparingly. Since
153 * we do when we are uncertain of the device state, we take a bit
154 * of extra paranoia to try and ensure that the HWS takes the value
155 * we give and that it doesn't end up trapped inside the CPU!
156 */
157 if (static_cpu_has(X86_FEATURE_CLFLUSH)) {
158 mb();
159 clflush(&engine->status_page.addr[reg]);
160 engine->status_page.addr[reg] = value;
161 clflush(&engine->status_page.addr[reg]);
162 mb();
163 } else {
164 WRITE_ONCE(engine->status_page.addr[reg], value);
165 }
166 }
167
168 /*
169 * Reads a dword out of the status page, which is written to from the command
170 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
171 * MI_STORE_DATA_IMM.
172 *
173 * The following dwords have a reserved meaning:
174 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
175 * 0x04: ring 0 head pointer
176 * 0x05: ring 1 head pointer (915-class)
177 * 0x06: ring 2 head pointer (915-class)
178 * 0x10-0x1b: Context status DWords (GM45)
179 * 0x1f: Last written status offset. (GM45)
180 * 0x20-0x2f: Reserved (Gen6+)
181 *
182 * The area from dword 0x30 to 0x3ff is available for driver usage.
183 */
184 #define I915_GEM_HWS_PREEMPT 0x32
185 #define I915_GEM_HWS_PREEMPT_ADDR (I915_GEM_HWS_PREEMPT * sizeof(u32))
186 #define I915_GEM_HWS_SEQNO 0x40
187 #define I915_GEM_HWS_SEQNO_ADDR (I915_GEM_HWS_SEQNO * sizeof(u32))
188 #define I915_GEM_HWS_SCRATCH 0x80
189
190 #define I915_HWS_CSB_BUF0_INDEX 0x10
191 #define I915_HWS_CSB_WRITE_INDEX 0x1f
192 #define CNL_HWS_CSB_WRITE_INDEX 0x2f
193
194 void intel_engine_stop(struct intel_engine_cs *engine);
195 void intel_engine_cleanup(struct intel_engine_cs *engine);
196
197 int intel_engines_init_mmio(struct intel_gt *gt);
198 int intel_engines_init(struct intel_gt *gt);
199
200 void intel_engine_free_request_pool(struct intel_engine_cs *engine);
201
202 void intel_engines_release(struct intel_gt *gt);
203 void intel_engines_free(struct intel_gt *gt);
204
205 int intel_engine_init_common(struct intel_engine_cs *engine);
206 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
207
208 int intel_engine_resume(struct intel_engine_cs *engine);
209
210 int intel_ring_submission_setup(struct intel_engine_cs *engine);
211
212 int intel_engine_stop_cs(struct intel_engine_cs *engine);
213 void intel_engine_cancel_stop_cs(struct intel_engine_cs *engine);
214
215 void intel_engine_set_hwsp_writemask(struct intel_engine_cs *engine, u32 mask);
216
217 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine);
218 u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine);
219
220 void intel_engine_get_instdone(const struct intel_engine_cs *engine,
221 struct intel_instdone *instdone);
222
223 void intel_engine_init_execlists(struct intel_engine_cs *engine);
224
__intel_engine_reset(struct intel_engine_cs * engine,bool stalled)225 static inline void __intel_engine_reset(struct intel_engine_cs *engine,
226 bool stalled)
227 {
228 if (engine->reset.rewind)
229 engine->reset.rewind(engine, stalled);
230 engine->serial++; /* contexts lost */
231 }
232
233 bool intel_engines_are_idle(struct intel_gt *gt);
234 bool intel_engine_is_idle(struct intel_engine_cs *engine);
235
236 void __intel_engine_flush_submission(struct intel_engine_cs *engine, bool sync);
intel_engine_flush_submission(struct intel_engine_cs * engine)237 static inline void intel_engine_flush_submission(struct intel_engine_cs *engine)
238 {
239 __intel_engine_flush_submission(engine, true);
240 }
241
242 void intel_engines_reset_default_submission(struct intel_gt *gt);
243
244 bool intel_engine_can_store_dword(struct intel_engine_cs *engine);
245
246 __printf(3, 4)
247 void intel_engine_dump(struct intel_engine_cs *engine,
248 struct drm_printer *m,
249 const char *header, ...);
250
251 ktime_t intel_engine_get_busy_time(struct intel_engine_cs *engine,
252 ktime_t *now);
253
254 struct i915_request *
255 intel_engine_find_active_request(struct intel_engine_cs *engine);
256
257 u32 intel_engine_context_size(struct intel_gt *gt, u8 class);
258
259 void intel_engine_init_active(struct intel_engine_cs *engine,
260 unsigned int subclass);
261 #define ENGINE_PHYSICAL 0
262 #define ENGINE_MOCK 1
263 #define ENGINE_VIRTUAL 2
264
265 static inline bool
intel_engine_has_preempt_reset(const struct intel_engine_cs * engine)266 intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
267 {
268 if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
269 return false;
270
271 return intel_engine_has_preemption(engine);
272 }
273
274 static inline bool
intel_engine_has_heartbeat(const struct intel_engine_cs * engine)275 intel_engine_has_heartbeat(const struct intel_engine_cs *engine)
276 {
277 if (!IS_ACTIVE(CONFIG_DRM_I915_HEARTBEAT_INTERVAL))
278 return false;
279
280 return READ_ONCE(engine->props.heartbeat_interval_ms);
281 }
282
283 #endif /* _INTEL_RINGBUFFER_H_ */
284